diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
index 7e61500080ecdcf9914fef4f36789b46790da87b..e9471152492f83f69932c2bef842b12adad62cbd 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
@@ -30,11 +30,11 @@
-- that occurs due to shared complex FFT and seperate in PFT_MODE_REAL2.
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2 is
generic (
@@ -88,27 +88,27 @@ begin
gen_pfs : if g_pfs_bypass = false generate
u_pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_points,
- g_nof_taps => c_nof_coeffs,
- g_in_dat_w => g_pfs_in_dat_w,
- g_out_dat_w => g_pfs_out_dat_w,
- g_coef_dat_w => g_pfs_coef_dat_w,
- g_coefs_file => g_pfs_coefs_file
- )
- port map (
- in_dat_x => pfs_in_dat_x,
- in_dat_y => pfs_in_dat_y,
- in_val => pfs_in_val,
- in_sync => pfs_in_sync,
- out_dat_x => fil_out_dat_x,
- out_dat_y => fil_out_dat_y,
- out_val => fil_out_val,
- out_sync => fil_out_sync,
- clk => dp_clk,
- rst => dp_rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_points,
+ g_nof_taps => c_nof_coeffs,
+ g_in_dat_w => g_pfs_in_dat_w,
+ g_out_dat_w => g_pfs_out_dat_w,
+ g_coef_dat_w => g_pfs_coef_dat_w,
+ g_coefs_file => g_pfs_coefs_file
+ )
+ port map (
+ in_dat_x => pfs_in_dat_x,
+ in_dat_y => pfs_in_dat_y,
+ in_val => pfs_in_val,
+ in_sync => pfs_in_sync,
+ out_dat_x => fil_out_dat_x,
+ out_dat_y => fil_out_dat_y,
+ out_val => fil_out_val,
+ out_sync => fil_out_sync,
+ clk => dp_clk,
+ rst => dp_rst,
+ restart => '0'
+ );
end generate;
no_pfs : if g_pfs_bypass = true generate
@@ -124,26 +124,26 @@ begin
fil_sosi.sync <= fil_out_sync;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => ceil_log2(g_nof_points),
- g_in_dat_w => g_pfs_out_dat_w,
- g_out_dat_w => g_pft_out_dat_w,
- g_stage_dat_w => g_pft_stage_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => fil_out_dat_x,
- in_im => fil_out_dat_y,
- in_val => fil_out_val,
- in_sync => fil_out_sync,
- switch_en => g_pft_switch_en,
- out_re => pft_out_dat_re,
- out_im => pft_out_dat_im,
- out_val => pft_out_val,
- out_sync => pft_out_sync,
- clk => dp_clk,
- rst => dp_rst
- );
+ generic map (
+ g_fft_size_w => ceil_log2(g_nof_points),
+ g_in_dat_w => g_pfs_out_dat_w,
+ g_out_dat_w => g_pft_out_dat_w,
+ g_stage_dat_w => g_pft_stage_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => fil_out_dat_x,
+ in_im => fil_out_dat_y,
+ in_val => fil_out_val,
+ in_sync => fil_out_sync,
+ switch_en => g_pft_switch_en,
+ out_re => pft_out_dat_re,
+ out_im => pft_out_dat_im,
+ out_val => pft_out_val,
+ out_sync => pft_out_sync,
+ clk => dp_clk,
+ rst => dp_rst
+ );
-- Delay pft sync with respect pft data to fit DP sync timing
out_sosi.re <= RESIZE_DP_DSP_DATA(pft_out_dat_re);
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index 424b49e6e684b57931790f725b8111ca58123d8c..5181960682369a604b8147a09daff0477f113714 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -29,12 +29,12 @@
-- Remark:
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use pfs_lib.pfs_pkg.all;
-use pft2_lib.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use pfs_lib.pfs_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pfb2_unit is
generic (
@@ -85,30 +85,30 @@ begin
---------------------------------------------------------------
gen_pfb2: for I in 0 to g_nof_streams - 1 generate
u_pfb2 : entity work.pfb2
- generic map (
- g_nof_points => g_nof_points,
+ generic map (
+ g_nof_points => g_nof_points,
- -- pfs
- g_pfs_bypass => g_pfs_bypass,
- g_pfs_nof_taps => g_pfs_nof_taps,
- g_pfs_in_dat_w => g_pfs_in_dat_w,
- g_pfs_out_dat_w => g_pfs_out_dat_w,
- g_pfs_coef_dat_w => g_pfs_coef_dat_w,
- g_pfs_coefs_file => g_pfs_coefs_file,
+ -- pfs
+ g_pfs_bypass => g_pfs_bypass,
+ g_pfs_nof_taps => g_pfs_nof_taps,
+ g_pfs_in_dat_w => g_pfs_in_dat_w,
+ g_pfs_out_dat_w => g_pfs_out_dat_w,
+ g_pfs_coef_dat_w => g_pfs_coef_dat_w,
+ g_pfs_coefs_file => g_pfs_coefs_file,
- -- pft2
- g_pft_mode => g_pft_mode,
- g_pft_switch_en => g_pft_switch_en,
- g_pft_stage_dat_w => g_pft_stage_dat_w,
- g_pft_out_dat_w => g_pft_out_dat_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => in_sosi_arr(I),
- fil_sosi => fil_sosi_arr(I),
- out_sosi => pft_sosi_arr(I)
- );
+ -- pft2
+ g_pft_mode => g_pft_mode,
+ g_pft_switch_en => g_pft_switch_en,
+ g_pft_stage_dat_w => g_pft_stage_dat_w,
+ g_pft_out_dat_w => g_pft_out_dat_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => in_sosi_arr(I),
+ fil_sosi => fil_sosi_arr(I),
+ out_sosi => pft_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
@@ -116,34 +116,34 @@ begin
---------------------------------------------------------------
-- MM mux for SST
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
- )
- port map (
- mosi => ram_st_sst_mosi,
- miso => ram_st_sst_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
-
- gen_sst: for I in 0 to g_nof_streams - 1 generate
- u_sst : entity st_lib.st_sst
generic map (
- g_nof_stat => c_nof_stats,
- g_in_data_w => g_pft_out_dat_w,
- g_stat_data_w => g_sst_data_w,
- g_stat_data_sz => g_sst_data_sz
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_sst_data_sz * c_nof_stats)
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => pft_sosi_arr(I),
- ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
- ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ mosi => ram_st_sst_mosi,
+ miso => ram_st_sst_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
);
+
+ gen_sst: for I in 0 to g_nof_streams - 1 generate
+ u_sst : entity st_lib.st_sst
+ generic map (
+ g_nof_stat => c_nof_stats,
+ g_in_data_w => g_pft_out_dat_w,
+ g_stat_data_w => g_sst_data_w,
+ g_stat_data_sz => g_sst_data_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => pft_sosi_arr(I),
+ ram_st_sst_mosi => ram_st_sst_mosi_arr(I),
+ ram_st_sst_miso => ram_st_sst_miso_arr(I)
+ );
end generate;
out_sosi_arr <= pft_sosi_arr;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
index db798f9feb7d11e4bc06bdcf5264f541a7366801..37b4f384cc68132cf43c779de2dab5fe61552a2e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
@@ -1,3 +1,4 @@
+
architecture empty of pfs is
begin
end empty;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
index 09cb45d5da45fd5f9956ede23c99fc12c3d2e0d4..10d6ce5be4a486633233f92e4d3c473a24b26e39 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs is
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
@@ -18,101 +18,101 @@ architecture str of pfs is
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity pfs_lib.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity pfs_lib.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity pfs_lib.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity pfs_lib.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index ffdeb470a07fcd58c59d2c230f970b5e9fe0af0f..011f76277e49322e9357670c8be73e71c24f6874 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.pfs_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.pfs_pkg.all;
entity pfs is
generic (
@@ -67,102 +67,102 @@ architecture str of pfs is
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity work.pfs_ctrl
- generic map (
- g_nof_bands_w => c_nof_bands_w,
- g_nof_taps => c_nof_fir_taps,
- g_nof_taps_w => c_nof_fir_taps_w,
- g_taps_w => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- restart => restart,
- in_x => in_dat_x,
- in_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- taps_rdaddr => taps_rdaddr,
- taps_wraddr => taps_wraddr,
- taps_wren => taps_wren,
- taps_in_x => taps_in_x,
- taps_in_y => taps_in_y,
- taps_out_x => taps_out_x,
- taps_out_y => taps_out_y,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_bands_w => c_nof_bands_w,
+ g_nof_taps => c_nof_fir_taps,
+ g_nof_taps_w => c_nof_fir_taps_w,
+ g_taps_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ restart => restart,
+ in_x => in_dat_x,
+ in_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ taps_rdaddr => taps_rdaddr,
+ taps_wraddr => taps_wraddr,
+ taps_wren => taps_wren,
+ taps_in_x => taps_in_x,
+ taps_in_y => taps_in_y,
+ taps_out_x => taps_out_x,
+ taps_out_y => taps_out_y,
+ out_val => out_val,
+ out_sync => out_sync
+ );
firx : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map(
- clk => clk,
- taps => taps_out_x,
- coefs => coefs,
- result => out_dat_x
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map(
+ clk => clk,
+ taps => taps_out_x,
+ coefs => coefs,
+ result => out_dat_x
+ );
firy : entity work.pfs_filter
- generic map (
- g_coef_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => g_in_dat_w,
- g_nof_taps => c_nof_fir_taps
- )
- port map (
- clk => clk,
- taps => taps_out_y,
- coefs => coefs,
- result => out_dat_y
- );
+ generic map (
+ g_coef_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => g_in_dat_w,
+ g_nof_taps => c_nof_fir_taps
+ )
+ port map (
+ clk => clk,
+ taps => taps_out_y,
+ coefs => coefs,
+ result => out_dat_y
+ );
tapsbufx : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_x,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_x,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_x,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_x,
+ clk => clk,
+ rst => rst
+ );
tapsbufy : entity work.pfs_tapsbuf
- generic map (
- g_data_w => g_in_dat_w * c_nof_fir_taps,
- g_nof_words => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- wrdata => taps_out_y,
- wren => taps_wren,
- wraddr => taps_wraddr,
- rdaddr => taps_rdaddr,
- rddata => taps_in_y,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w * c_nof_fir_taps,
+ g_nof_words => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ wrdata => taps_out_y,
+ wren => taps_wren,
+ wraddr => taps_wraddr,
+ rdaddr => taps_rdaddr,
+ rddata => taps_in_y,
+ clk => clk,
+ rst => rst
+ );
coefsbuf : entity work.pfs_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w * c_nof_fir_taps,
- g_coefs_file => g_coefs_file,
- g_nof_coefs => g_nof_bands,
- g_addr_w => c_nof_bands_w
- )
- port map (
- addr => taps_rdaddr,
- data => coefs,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_coef_dat_w * c_nof_fir_taps,
+ g_coefs_file => g_coefs_file,
+ g_nof_coefs => g_nof_bands,
+ g_addr_w => c_nof_bands_w
+ )
+ port map (
+ addr => taps_rdaddr,
+ data => coefs,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 257754314c9c4fb000af3c2034c2080e988d1750..dc07813b0656c636a81edf26349f48e8c3630a6a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -1,25 +1,26 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0');
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => "data/pfs_coefsbuf_1024.hex" -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --g_init_file => "data/pfs_coefsbuf_1024.bin" -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
index 2983acb7242e17968f0beb65dad4bd95a9a44b98..ee5dda5668a3e1f1c4dc2a3c998a29439fe7d31b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
@@ -1,30 +1,30 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_a : out std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
rom : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
index d28621875de50bba54bae8ff7dbb1cbcfd9ce970..e868fcc36c5aff8a928296fc6f851a94103a6cbc 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_mem_pkg.all;
entity pfs_coefsbuf is
generic (
@@ -45,21 +45,22 @@ entity pfs_coefsbuf is
end pfs_coefsbuf;
architecture str of pfs_coefsbuf is
- constant c_coefs_rom : t_c_mem := (latency => 2,
- adr_w => g_addr_w,
- dat_w => g_data_w,
- nof_dat => g_nof_coefs, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_coefs_rom : t_c_mem := (
+ latency => 2,
+ adr_w => g_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_nof_coefs, -- <= 2**g_addr_w
+ init_sl => '0');
begin
rom : entity common_lib.common_rom
- generic map (
- g_ram => c_coefs_rom,
- g_init_file => g_coefs_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => addr,
- rd_dat => data
- );
+ generic map (
+ g_ram => c_coefs_rom,
+ g_init_file => g_coefs_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => addr,
+ rd_dat => data
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
index 63fc7c73471a552a4a428a166707c13976e98ceb..7c53ab67074f146f16775dbaaf33e2e3d10703ec 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_combine is
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
@@ -32,7 +32,7 @@ begin
end process;
select_value : process (i_out_dat_x, i_out_dat_y, in_val, in_dat_x, in_dat_y,
- in_sync)
+ in_sync)
begin
nxt_out_dat_x <= i_out_dat_x;
nxt_out_dat_y <= i_out_dat_y;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
index 6c921d33b654b58e4ae42d7c793b191d4c8f3a68..8868aeaf9ec41863eb1fd37bb5400ba322c51430 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_combine is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
index 315298a5ae8096c295e9af10fb55e0ba4234a6b1..bf832181f6d9e8f297e18b6460d856da10dd54b1 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_ctrl is
-- The number of cycles that should be waited until the result that comes out
@@ -71,7 +71,7 @@ begin
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
- in_y_reg)
+ in_y_reg)
begin
nxt_taps_wraddr <= std_logic_vector(unsigned(i_taps_wraddr) + 1);
if restart = '1' then
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
index ab0bcedb05208d4f158befcd644b567dc9509d8b..294ed765102d51dcbcdcb6375e862d8b7f788682 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_ctrl is
generic (
@@ -123,7 +123,7 @@ begin
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
- in_y_reg)
+ in_y_reg)
begin
nxt_taps_wraddr <= std_logic_vector(unsigned(i_taps_wraddr) + 1);
if restart = '1' then
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index c17e494eb6f07d436f9ae722f90652f4642090fe..18c9d207f0664ab38d124933afbbe23c8f77df7b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_filter is
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
@@ -25,27 +25,27 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index d551fa62270d140d88209eb96a728e47634e08c8..b2548ef14716c46c9f3c00e3e25c754e63d161ce 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -1,80 +1,80 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_filter is
component altmult_add
- generic (
- input_register_b2 : string := "CLOCK0";
- input_register_a1 : string := "CLOCK0";
- multiplier_register0 : string := "CLOCK0";
- signed_pipeline_aclr_b : string := "ACLR3";
- input_register_b3 : string := "CLOCK0";
- input_register_a2 : string := "CLOCK0";
- multiplier_register1 : string := "CLOCK0";
- addnsub_multiplier_pipeline_aclr1 : string := "ACLR3";
- input_register_a3 : string := "CLOCK0";
- multiplier_register2 : string := "CLOCK0";
- signed_aclr_a : string := "ACLR3";
- signed_register_a : string := "CLOCK0";
- number_of_multipliers : natural := 4;
- multiplier_register3 : string := "CLOCK0";
- multiplier_aclr0 : string := "ACLR3";
- addnsub_multiplier_pipeline_aclr3 : string := "ACLR3";
- signed_aclr_b : string := "ACLR3";
- signed_register_b : string := "CLOCK0";
- lpm_type : string := "altmult_add";
- multiplier_aclr1 : string := "ACLR3";
- input_aclr_b0 : string := "ACLR3";
- output_register : string := "CLOCK0";
- width_result : natural := g_taps_w + g_coef_w + 2;
- representation_a : string := "SIGNED";
- signed_pipeline_register_a : string := "CLOCK0";
- input_source_b0 : string := "DATAB";
- multiplier_aclr2 : string := "ACLR3";
- input_aclr_b1 : string := "ACLR3";
- input_aclr_a0 : string := "ACLR3";
- multiplier3_direction : string := "ADD";
- addnsub_multiplier_register1 : string := "CLOCK0";
- representation_b : string := "SIGNED";
- signed_pipeline_register_b : string := "CLOCK0";
- input_source_b1 : string := "DATAB";
- input_source_a0 : string := "DATAA";
- multiplier_aclr3 : string := "ACLR3";
- input_aclr_b2 : string := "ACLR3";
- input_aclr_a1 : string := "ACLR3";
- dedicated_multiplier_circuitry : string := "YES";
- input_source_b2 : string := "DATAB";
- input_source_a1 : string := "DATAA";
- input_aclr_b3 : string := "ACLR3";
- input_aclr_a2 : string := "ACLR3";
- addnsub_multiplier_register3 : string := "CLOCK0";
- addnsub_multiplier_aclr1 : string := "ACLR3";
- output_aclr : string := "ACLR3";
- input_source_b3 : string := "DATAB";
- input_source_a2 : string := "DATAA";
- input_aclr_a3 : string := "ACLR3";
- input_source_a3 : string := "DATAA";
- addnsub_multiplier_aclr3 : string := "ACLR3";
- intended_device_family : string := "Stratix II";
- addnsub_multiplier_pipeline_register1 : string := "CLOCK0";
- width_a : natural := g_taps_w;
- input_register_b0 : string := "CLOCK0";
- width_b : natural := g_coef_w;
- input_register_b1 : string := "CLOCK0";
- input_register_a0 : string := "CLOCK0";
- addnsub_multiplier_pipeline_register3 : string := "CLOCK0";
- multiplier1_direction : string := "ADD";
- signed_pipeline_aclr_a : string := "ACLR3"
- );
- port (
- dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
- datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
- clock0 : in std_logic;
- aclr3 : in std_logic;
- result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
- );
+ generic (
+ input_register_b2 : string := "CLOCK0";
+ input_register_a1 : string := "CLOCK0";
+ multiplier_register0 : string := "CLOCK0";
+ signed_pipeline_aclr_b : string := "ACLR3";
+ input_register_b3 : string := "CLOCK0";
+ input_register_a2 : string := "CLOCK0";
+ multiplier_register1 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_aclr1 : string := "ACLR3";
+ input_register_a3 : string := "CLOCK0";
+ multiplier_register2 : string := "CLOCK0";
+ signed_aclr_a : string := "ACLR3";
+ signed_register_a : string := "CLOCK0";
+ number_of_multipliers : natural := 4;
+ multiplier_register3 : string := "CLOCK0";
+ multiplier_aclr0 : string := "ACLR3";
+ addnsub_multiplier_pipeline_aclr3 : string := "ACLR3";
+ signed_aclr_b : string := "ACLR3";
+ signed_register_b : string := "CLOCK0";
+ lpm_type : string := "altmult_add";
+ multiplier_aclr1 : string := "ACLR3";
+ input_aclr_b0 : string := "ACLR3";
+ output_register : string := "CLOCK0";
+ width_result : natural := g_taps_w + g_coef_w + 2;
+ representation_a : string := "SIGNED";
+ signed_pipeline_register_a : string := "CLOCK0";
+ input_source_b0 : string := "DATAB";
+ multiplier_aclr2 : string := "ACLR3";
+ input_aclr_b1 : string := "ACLR3";
+ input_aclr_a0 : string := "ACLR3";
+ multiplier3_direction : string := "ADD";
+ addnsub_multiplier_register1 : string := "CLOCK0";
+ representation_b : string := "SIGNED";
+ signed_pipeline_register_b : string := "CLOCK0";
+ input_source_b1 : string := "DATAB";
+ input_source_a0 : string := "DATAA";
+ multiplier_aclr3 : string := "ACLR3";
+ input_aclr_b2 : string := "ACLR3";
+ input_aclr_a1 : string := "ACLR3";
+ dedicated_multiplier_circuitry : string := "YES";
+ input_source_b2 : string := "DATAB";
+ input_source_a1 : string := "DATAA";
+ input_aclr_b3 : string := "ACLR3";
+ input_aclr_a2 : string := "ACLR3";
+ addnsub_multiplier_register3 : string := "CLOCK0";
+ addnsub_multiplier_aclr1 : string := "ACLR3";
+ output_aclr : string := "ACLR3";
+ input_source_b3 : string := "DATAB";
+ input_source_a2 : string := "DATAA";
+ input_aclr_a3 : string := "ACLR3";
+ input_source_a3 : string := "DATAA";
+ addnsub_multiplier_aclr3 : string := "ACLR3";
+ intended_device_family : string := "Stratix II";
+ addnsub_multiplier_pipeline_register1 : string := "CLOCK0";
+ width_a : natural := g_taps_w;
+ input_register_b0 : string := "CLOCK0";
+ width_b : natural := g_coef_w;
+ input_register_b1 : string := "CLOCK0";
+ input_register_a0 : string := "CLOCK0";
+ addnsub_multiplier_pipeline_register3 : string := "CLOCK0";
+ multiplier1_direction : string := "ADD";
+ signed_pipeline_aclr_a : string := "ACLR3"
+ );
+ port (
+ dataa : in std_logic_vector(g_taps_w * 4 - 1 downto 0);
+ datab : in std_logic_vector(g_coef_w * 4 - 1 downto 0);
+ clock0 : in std_logic;
+ aclr3 : in std_logic;
+ result : out std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0)
+ );
end component;
signal res_0 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
@@ -99,7 +99,7 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
ALTMULT_ADD_0 : altmult_add
port map (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index ba25c7ab38656b7edf7bf6ce78db76ffb66da00d..51a600298e5d38617f4f21e736843b8e1998704d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib, common_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity pfs_filter is
generic (
@@ -65,27 +65,27 @@ begin
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
--- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
+ -- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
--MULT_ADD : ENTITY common_lib.common_mult_add(rtl)
--MULT_ADD : ENTITY common_lib.common_mult_add(virtex)
MULT_ADD : entity common_mult_lib.common_mult_add -- rtl
- generic map (
- g_in_a_w => g_taps_w,
- g_in_b_w => g_coef_w,
- g_out_dat_w => g_coef_w + g_taps_w + 1,
- g_add_sub => "ADD",
- g_pipeline => 3
- )
- port map (
- clk => clk,
- in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
- in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
- in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
- in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
- out_dat => res(i)
- );
+ generic map (
+ g_in_a_w => g_taps_w,
+ g_in_b_w => g_coef_w,
+ g_out_dat_w => g_coef_w + g_taps_w + 1,
+ g_add_sub => "ADD",
+ g_pipeline => 3
+ )
+ port map (
+ clk => clk,
+ in_a0 => taps (g_taps_w * (2 * i + 1) - 1 downto g_taps_w * 2 * i),
+ in_b0 => coefs(g_coef_w * (2 * i + 1) - 1 downto g_coef_w * 2 * i),
+ in_a1 => taps (g_taps_w * (2 * i + 2) - 1 downto g_taps_w * (2 * i + 1)),
+ in_b1 => coefs(g_coef_w * (2 * i + 2) - 1 downto g_coef_w * (2 * i + 1)),
+ out_dat => res(i)
+ );
end generate;
pipe : process (clk)
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
index abe1bfdfcd8001d60681e6c1c36120765b94dbe7..81e7044b5a55cb5872fa74882b6acb986d7652b7 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
@@ -1,7 +1,7 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
library common_lib;
-use common_lib.common_pkg.all;
+ use common_lib.common_pkg.all;
architecture str of pfs_fir is
constant c_nof_taps_w : natural := ceil_log2(g_nof_taps);
@@ -25,138 +25,138 @@ architecture str of pfs_fir is
signal i_res_val : std_logic;
begin
ctrl : entity pfs_lib.pfs_fir_ctrl
- generic map (
- g_nof_prefilter => g_nof_prefilter,
- g_nof_prefilter_w => c_nof_prefilter_w,
- g_nof_taps => g_nof_taps,
- g_nof_taps_w => c_nof_taps_w,
- g_sample_width => g_in_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- input_hor => in_hor,
- input_ver => in_ver,
- input_val => in_val,
- input_sync => in_sync,
- coefs_addr => coefs_addr,
- coefs_rden => coefs_rden,
- sample_addr => sample_addr,
- sample_data_hor => sample_data_hor,
- sample_data_ver => sample_data_ver,
- sample_wren => sample_wren,
- taps_addr => taps_addr,
- taps_rden => taps_rden,
- res_clr => res_clr,
- result_val => i_res_val,
- result_sync => res_sync
- );
+ generic map (
+ g_nof_prefilter => g_nof_prefilter,
+ g_nof_prefilter_w => c_nof_prefilter_w,
+ g_nof_taps => g_nof_taps,
+ g_nof_taps_w => c_nof_taps_w,
+ g_sample_width => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ input_hor => in_hor,
+ input_ver => in_ver,
+ input_val => in_val,
+ input_sync => in_sync,
+ coefs_addr => coefs_addr,
+ coefs_rden => coefs_rden,
+ sample_addr => sample_addr,
+ sample_data_hor => sample_data_hor,
+ sample_data_ver => sample_data_ver,
+ sample_wren => sample_wren,
+ taps_addr => taps_addr,
+ taps_rden => taps_rden,
+ res_clr => res_clr,
+ result_val => i_res_val,
+ result_sync => res_sync
+ );
mac_hor : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_hor,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_hor
- );
+ generic map (
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
+ )
+ port map (
+ data_a => taps_data_hor,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_hor
+ );
mac_ver : entity pfs_lib.pfs_fir_mac
- generic map (
- g_a_in_w => g_in_dat_w,
- g_b_in_w => g_coef_dat_w,
- g_out_w => g_out_dat_w,
- g_taps_w => c_nof_taps_w,
- g_mult_pipeline => c_mult_latency
- )
- port map (
- data_a => taps_data_ver,
- data_b => coefs_data,
- res_clr => res_clr,
- res_val => i_res_val,
- clk => clk,
- rst => rst,
- result => res_ver
- );
-
- coefsbuf_0 : if g_fir_nr = 0 generate
- coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
- & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
+ g_a_in_w => g_in_dat_w,
+ g_b_in_w => g_coef_dat_w,
+ g_out_w => g_out_dat_w,
+ g_taps_w => c_nof_taps_w,
+ g_mult_pipeline => c_mult_latency
)
port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
+ data_a => taps_data_ver,
+ data_b => coefs_data,
+ res_clr => res_clr,
+ res_val => i_res_val,
+ clk => clk,
+ rst => rst,
+ result => res_ver
);
+
+ coefsbuf_0 : if g_fir_nr = 0 generate
+ coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_0_"
+ & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
coefsbuf_N : if g_fir_nr > 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
- generic map (
- g_data_w => g_coef_dat_w,
- g_coefs_w => c_addr_w,
- g_nof_coefs => c_nof_coefs,
- g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
+ generic map (
+ g_data_w => g_coef_dat_w,
+ g_coefs_w => c_addr_w,
+ g_nof_coefs => c_nof_coefs,
+ g_init_file => "../../../../../EPA/pfs/src/data/pfs_fir_coeff_"
& natural'image(g_fir_nr) & "_" & natural'image(g_nof_prefilter * g_nof_taps) & "pts.hex"
- )
- port map (
- addr => coefs_addr,
- rden => coefs_rden,
- data => coefs_data,
- clk => clk,
- rst => rst
- );
+ )
+ port map (
+ addr => coefs_addr,
+ rden => coefs_rden,
+ data => coefs_data,
+ clk => clk,
+ rst => rst
+ );
end generate;
tapsbuf_hor : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_hor,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_hor,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_hor,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_hor,
+ clk => clk,
+ rst => rst
+ );
tapsbuf_ver : entity pfs_lib.pfs_fir_tapsbuf
- generic map (
- g_data_w => g_in_dat_w,
- g_nof_words => c_nof_coefs,
- g_addr_w => c_addr_w
- )
- port map (
- data_a => sample_data_ver,
- wren_a => sample_wren,
- addr_a => sample_addr,
- addr_b => taps_addr,
- rden_b => taps_rden,
- data_b => taps_data_ver,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_data_w => g_in_dat_w,
+ g_nof_words => c_nof_coefs,
+ g_addr_w => c_addr_w
+ )
+ port map (
+ data_a => sample_data_ver,
+ wren_a => sample_wren,
+ addr_a => sample_addr,
+ addr_b => taps_addr,
+ rden_b => taps_rden,
+ data_b => taps_data_ver,
+ clk => clk,
+ rst => rst
+ );
res_val <= i_res_val;
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
index b0c265b36f1be8d98b008da7050314745af124a7..55cf7fe981d35438c0609ee16a7390637f486f1b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
@@ -1,16 +1,16 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir is
generic (
g_in_dat_w : natural;
g_out_dat_w : natural;
g_coef_dat_w : natural;
--- g_nof_fir : NATURAL;
--- g_nof_subbands : NATURAL;
+ -- g_nof_fir : NATURAL;
+ -- g_nof_subbands : NATURAL;
g_nof_prefilter : natural;
--- g_nof_polarizations : NATURAL;
+ -- g_nof_polarizations : NATURAL;
g_nof_taps : natural;
g_fir_nr : natural
);
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
index 75cc60eba806430d870b0a73f851b054ace794b1..0273a8f7f6d4962ed4cca6d758c85aa0b5272e9c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
@@ -1,30 +1,30 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_coefsbuf is
component altsyncram
- generic (
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_a : string;
- outdata_aclr_a : string;
- read_during_write_mode_mixed_ports : string;
- ram_block_type : string;
- init_file : string;
- intended_device_family : string
- );
- port (
+ generic (
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_a : string;
+ outdata_aclr_a : string;
+ read_during_write_mode_mixed_ports : string;
+ ram_block_type : string;
+ init_file : string;
+ intended_device_family : string
+ );
+ port (
aclr0 : in std_logic;
clock0 : in std_logic;
address_a : in std_logic_vector(g_coefs_w - 1 downto 0);
q_a : out std_logic_vector(g_data_w - 1 downto 0)
- );
+ );
end component;
begin
rom : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
index 5bd64c7a4a5eab7647529c9f694c20ab2b9b4c11..a4e2717f21cd8576299619b38c4d61b6206b9b25 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_coefsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
index 1a2fc318a95852a567b1043632652faaee2d0c06..cf5d56d4e09bce82a23d72a38d32eaa8da46707f 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
architecture rtl of pfs_fir_ctrl is
-- The number of cycles that should be waited until the result that comes out
@@ -46,7 +46,7 @@ begin
-- Output signals.
result_val <= mac_res_delay(mac_res_delay'high);
result_sync <= sync_delay(sync_delay'high);
--- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
+ -- res_clr <= mac_res_delay(c_mac_clr_delay - 1);
taps_addr <= i_taps_addr;
sample_data_hor <= i_sample_data_hor;
sample_data_ver <= i_sample_data_ver;
@@ -175,9 +175,9 @@ begin
if input_val = '1' then
nxt_sample_data_hor <= std_logic_vector(to_signed(
- to_integer(signed(input_hor)), i_sample_data_hor'length));
+ to_integer(signed(input_hor)), i_sample_data_hor'length));
nxt_sample_data_ver <= std_logic_vector(to_signed(
- to_integer(signed(input_ver)), i_sample_data_ver'length));
+ to_integer(signed(input_ver)), i_sample_data_ver'length));
end if;
end process;
@@ -198,12 +198,12 @@ begin
if unsigned(prefilter_cnt) = (g_nof_prefilter - 1) and last_tap = '1' then
nxt_taps_addr_base <=
- std_logic_vector(unsigned(taps_addr_base) + 1);
+ std_logic_vector(unsigned(taps_addr_base) + 1);
end if;
end process;
taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
- + unsigned(taps_cnt));
+ + unsigned(taps_cnt));
-- The MAC delay register is used to generate a valid pulse for the MAC output
-- when the FIR calculation is done, and to generate a reset pulse to set the
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
index d3c70a8bb12eb819e523dbb900ac90f2e3cd9c6d..1b28c5c2b514e80db87a42537eb75186ce1b3800 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
@@ -1,5 +1,5 @@
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity pfs_fir_ctrl is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
index e036325cd4a2e27cbc4ce7300d213f6d70826c5c..5bcada560a7e7e7f9d406b042d8fbdbc3a13f36c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
@@ -1,47 +1,47 @@
library IEEE, lpm, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_mac is
component altmult_accum
- generic (
- intended_device_family : string;
- width_a : natural;
- width_b : natural;
- representation_a : string;
- representation_b : string;
- lpm_type : string;
- width_result : natural;
- input_source_a : string;
- input_source_b : string;
- multiplier_rounding : string;
- multiplier_saturation : string;
- port_mult_is_saturated : string;
- accumulator_rounding : string;
- accumulator_saturation : string;
- port_accum_is_saturated : string;
- accum_direction : string;
- input_reg_a : string;
- input_aclr_a : string;
- input_reg_b : string;
- input_aclr_b : string;
- multiplier_reg : string;
- multiplier_aclr : string;
- accum_sload_reg : string;
- accum_sload_pipeline_reg : string;
- output_reg : string;
- output_aclr : string;
- dedicated_multiplier_circuitry : string
- );
- port (
- dataa : in std_logic_vector(width_a - 1 downto 0);
- datab : in std_logic_vector(width_b - 1 downto 0);
- accum_sload : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- result : out std_logic_vector(width_result - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ width_a : natural;
+ width_b : natural;
+ representation_a : string;
+ representation_b : string;
+ lpm_type : string;
+ width_result : natural;
+ input_source_a : string;
+ input_source_b : string;
+ multiplier_rounding : string;
+ multiplier_saturation : string;
+ port_mult_is_saturated : string;
+ accumulator_rounding : string;
+ accumulator_saturation : string;
+ port_accum_is_saturated : string;
+ accum_direction : string;
+ input_reg_a : string;
+ input_aclr_a : string;
+ input_reg_b : string;
+ input_aclr_b : string;
+ multiplier_reg : string;
+ multiplier_aclr : string;
+ accum_sload_reg : string;
+ accum_sload_pipeline_reg : string;
+ output_reg : string;
+ output_aclr : string;
+ dedicated_multiplier_circuitry : string
+ );
+ port (
+ dataa : in std_logic_vector(width_a - 1 downto 0);
+ datab : in std_logic_vector(width_b - 1 downto 0);
+ accum_sload : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ result : out std_logic_vector(width_result - 1 downto 0)
+ );
end component;
-- NOTE: although it appears otherwise, bit growth in the accumulation is accounted for!
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
index a9ff53a2ccad0feca77b90310e37cf29b721715c..e62ca5df4448f0a1684b21fcbd88402599ac0945 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_mac is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
index 000968fe0ec5143ebf9c7ca9f03d6bd551ab15db..ca240f70619ecf1a75da8c8ea740b4a864c69128 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
@@ -1,37 +1,37 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_fir_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
index 05d25645123dc0bc1a0ac4e9fa72c85f8be9b337..3f3f594777d18477db178f0a9f3af236465cf03a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_fir_tapsbuf is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
index 47dcc7272d22339a9cd1055c5137ac925d19c6f4..623dd3f8e58578c3a378ae3cb4b7f700016ab5aa 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Use package to keep default pfs constants
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pfs_pkg is
constant c_pfs_coef_w : natural := 16;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
index de1f3ccf289e5afe7aefb1d5aa91533267529a74..80f0911b7f087fad016c30eec85618b26727809e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pfs_rotate is
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
@@ -43,7 +43,7 @@ begin
end process;
interleaver_proc : process (in_val, cnt, in_dat_x, in_dat_y, in_sync,
- i_out_dat_x, i_out_dat_y)
+ i_out_dat_x, i_out_dat_y)
begin
nxt_out_dat_x <= i_out_dat_x;
nxt_out_dat_y <= i_out_dat_y;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
index 96b25a28cd47f08211a9150d702b724ad41880f3..8b2a949fefc7a5f74bf3ebf333e13fadacde35f9 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pfs_rotate is
generic (
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
index 5f59cf66fdc9ff4b49f7238087e7732de7b8b691..90231a976ff5456c8e0a0d01336d994a4eaf6a7b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
@@ -1,28 +1,28 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
+ use common_lib.common_pkg.all;
architecture rtl of pfs_tapsbuf is
-type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
+ type RamType is array(0 to 2 ** g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
--- pfs_tapsbuf_1024.hex is empty (all zeros)
-signal RAM : RamType := (others => (others => '0'));
+ -- pfs_tapsbuf_1024.hex is empty (all zeros)
+ signal RAM : RamType := (others => (others => '0'));
-signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
+ signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
begin
----------------------------------------------------------------
-process (clk)
-begin
- if (clk'event and clk = '1') then
- if (wren = '1') then
- RAM (conv_integer(wraddr)) <= wrdata;
- end if;
- read_addrb <= rdaddr;
+ ---------------------------------------------------------------
+ process (clk)
+ begin
+ if (clk'event and clk = '1') then
+ if (wren = '1') then
+ RAM (conv_integer(wraddr)) <= wrdata;
+ end if;
+ read_addrb <= rdaddr;
rddata <= RAM(conv_integer(read_addrb));
- end if;
-end process;
+ end if;
+ end process;
----------------------------------------------------------------
----------------------------------------------------------------
+ ---------------------------------------------------------------
+ ---------------------------------------------------------------
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
index c7dcd76860c71e5c9c37a712e3abb37615f6580e..0f7f20475d387d7728e17ab27156ded2ae77e75d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
@@ -1,37 +1,37 @@
library IEEE, altera_mf, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
architecture stratix of pfs_tapsbuf is
component altsyncram
- generic (
- intended_device_family : string;
- operation_mode : string;
- width_a : natural;
- widthad_a : natural;
- numwords_a : natural;
- width_b : natural;
- widthad_b : natural;
- numwords_b : natural;
- lpm_type : string;
- width_byteena_a : natural;
- outdata_reg_b : string;
- address_reg_b : string;
- outdata_aclr_b : string;
- read_during_write_mode_mixed_ports : string;
- init_file : string;
- ram_block_type : string
- );
- port (
- wren_a : in std_logic;
- aclr0 : in std_logic;
- clock0 : in std_logic;
- address_a : in std_logic_vector(g_addr_w - 1 downto 0);
- address_b : in std_logic_vector(g_addr_w - 1 downto 0);
- q_b : out std_logic_vector(g_data_w - 1 downto 0);
- data_a : in std_logic_vector(g_data_w - 1 downto 0)
- );
+ generic (
+ intended_device_family : string;
+ operation_mode : string;
+ width_a : natural;
+ widthad_a : natural;
+ numwords_a : natural;
+ width_b : natural;
+ widthad_b : natural;
+ numwords_b : natural;
+ lpm_type : string;
+ width_byteena_a : natural;
+ outdata_reg_b : string;
+ address_reg_b : string;
+ outdata_aclr_b : string;
+ read_during_write_mode_mixed_ports : string;
+ init_file : string;
+ ram_block_type : string
+ );
+ port (
+ wren_a : in std_logic;
+ aclr0 : in std_logic;
+ clock0 : in std_logic;
+ address_a : in std_logic_vector(g_addr_w - 1 downto 0);
+ address_b : in std_logic_vector(g_addr_w - 1 downto 0);
+ q_b : out std_logic_vector(g_data_w - 1 downto 0);
+ data_a : in std_logic_vector(g_data_w - 1 downto 0)
+ );
end component;
begin
altsyncram_component : altsyncram
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
index fcbf46518a8a28e3d78eec83b0d5221fa2c308cf..db4a5ce6aecd5901f3c43e3fd2425c94ef91db19 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_unsigned.all;
entity pfs_tapsbuf is
generic (
@@ -46,7 +46,7 @@ entity pfs_tapsbuf is
end pfs_tapsbuf;
architecture rtl of pfs_tapsbuf is
- type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
+ type RamType is array(0 to 2 ** g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
-- pfs_tapsbuf_1024.hex is empty (all zeros)
signal RAM : RamType := (others => (others => '0'));
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
index 9651e9c167dd46c943f9d91e38b81a42f7bd97a0..f067d35ca5aec88a4e83ac8c6c8c8e524f41de9a 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
@@ -1,5 +1,5 @@
library IEEE, pfs_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture str of pfs_top is
signal reg_in_dat_x : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -26,24 +26,24 @@ begin
end process;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => g_nof_bands,
- g_nof_taps => g_nof_taps,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_coef_dat_w => g_coef_dat_w
- )
- port map (
- in_dat_x => reg_in_dat_x,
- in_dat_y => reg_in_dat_y,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- out_dat_x => d_out_dat_x,
- out_dat_y => d_out_dat_y,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => g_nof_bands,
+ g_nof_taps => g_nof_taps,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_coef_dat_w => g_coef_dat_w
+ )
+ port map (
+ in_dat_x => reg_in_dat_x,
+ in_dat_y => reg_in_dat_y,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ out_dat_x => d_out_dat_x,
+ out_dat_y => d_out_dat_y,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
index a69a35d77d304525196608786a1730d395dd5a8c..aad940e76564a989bcc8644ca7501623a05bafa7 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pfs_top is
generic (
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index 17cc8b68856ffcc2f6e91ce4279749b0757421ad..150e750b5b6bee423a021a8890f9a495f399fe5a 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -30,10 +30,10 @@
-- . View pfs_dat_x in decimal radix and analog format (right click)
library IEEE, pfs_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pfs is
end tb_pfs;
@@ -57,26 +57,26 @@ begin
rst <= '0' after 3 * clk_period;
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 1024,
- g_nof_taps => 16 * 1024,
- g_in_dat_w => 12,
- g_out_dat_w => 18,
- g_coef_dat_w => 16
- )
- port map (
- in_dat_x => in_dat_x,
- in_dat_y => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_dat_x,
- out_dat_y => pfs_dat_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- restart => '0',
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_nof_bands => 1024,
+ g_nof_taps => 16 * 1024,
+ g_in_dat_w => 12,
+ g_out_dat_w => 18,
+ g_coef_dat_w => 16
+ )
+ port map (
+ in_dat_x => in_dat_x,
+ in_dat_y => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_dat_x,
+ out_dat_y => pfs_dat_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ restart => '0',
+ clk => clk,
+ rst => rst
+ );
-- Keep in_dat_x high for one slice to get the filter impules response. Using amplitude 1024
-- yields the FIR coefficients, this amplitude compensates the PFS scaling of 2^4/2^14. The
@@ -100,7 +100,7 @@ begin
for j in 1 to 16 loop
for i in 1 to 1024 loop
if j = 1 then
- in_dat_x <= TO_UVEC(2**10, in_dat_x'length);
+ in_dat_x <= TO_UVEC(2 ** 10, in_dat_x'length);
else
in_dat_x <= TO_UVEC(0, in_dat_x'length);
end if;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
index 84fa87eb0c39a4f8ff2dad9f2e783c8b1d36d892..11c5c2eaa70b91cd8a8440df3e693500c185ecd9 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
@@ -1,3 +1,4 @@
+
architecture empty of pft is
begin
end empty;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
index 20e0854462a20340b86b60b89dd1282e43f4b4ea..75e102b69c2baca1eae49615760993c1803411e6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
constant c_pft_stage_dat_w : natural := 20;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
index 47cd94497c6b680649d154a9e7abc18602d80def..fa9ef5bc0a27d810a455a45a008bee696c54a0c3 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
architecture str of pft is
function pft_dat_w ( output_w : in natural; mode : in PFT_MODE_TYPE) return natural is
@@ -77,23 +77,23 @@ begin
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
switch: entity pft2_lib.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity pft2_lib.pft_stage
@@ -160,23 +160,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity pft2_lib.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -210,7 +210,7 @@ begin
);
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity pft2_lib.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -260,65 +260,66 @@ begin
end generate;
unswitch: entity pft2_lib.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
+ end if;
+ end process;
- band <= bin(bin'high downto 1);
+ band <= bin(bin'high downto 1);
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
+ ) when unswitch_val = '1' else (others => '0');
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
+
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
index 167561784c506e95549ea815b4773596ec4e747e..86c2d1bd5c7faaa47445d580e1280f3f74bbdef7 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
@@ -24,9 +24,9 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
entity pft is
generic (
@@ -122,23 +122,23 @@ begin
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
switch: entity work.pft_switch
- generic map (
- g_dat_w => g_in_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_sync => in_sync,
- in_re => in_re,
- in_im => in_im,
- switch_en => switch_en,
- out_re => switch_re,
- out_im => switch_im,
- out_val => switch_val,
- out_sync => switch_sync
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_sync => in_sync,
+ in_re => in_re,
+ in_im => in_im,
+ switch_en => switch_en,
+ out_re => switch_re,
+ out_im => switch_im,
+ out_val => switch_val,
+ out_sync => switch_sync
+ );
first_gen : if (c_nof_stages > 1) generate
first_stage : entity work.pft_stage
@@ -205,23 +205,23 @@ begin
only_gen : if c_nof_stages = 1 generate
only_stage : entity work.pft_stage
- generic map (
- g_index => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_pft_dat_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => pft_re,
- out_im => pft_im,
- out_val => pft_val,
- out_sync => pft_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_pft_dat_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => pft_re,
+ out_im => pft_im,
+ out_val => pft_val,
+ out_sync => pft_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
-- In "BITREV" mode, fft output is in bit reversed order.
@@ -255,7 +255,7 @@ begin
);
end generate;
- reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
+ reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity work.pft_reverse
generic map (
g_fft_sz => 2**g_fft_size_w,
@@ -305,65 +305,66 @@ begin
end generate;
unswitch: entity work.pft_unswitch
- generic map (
- g_dat_w => g_out_dat_w,
- g_fft_sz_w => g_fft_size_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => sep_val,
- in_sync => sep_sync,
- in_re => sep_re,
- in_im => sep_im,
- switch_en => switch_en,
- out_re => unswitch_re,
- out_im => unswitch_im,
- out_val => unswitch_val,
- out_sync => unswitch_sync
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fft_sz_w => g_fft_size_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => sep_val,
+ in_sync => sep_sync,
+ in_re => sep_re,
+ in_im => sep_im,
+ switch_en => switch_en,
+ out_re => unswitch_re,
+ out_im => unswitch_im,
+ out_val => unswitch_val,
+ out_sync => unswitch_sync
+ );
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
- determine_bin : process (clk)
- begin
- if rising_edge(clk) then
- if unswitch_val = '1' then
- bin <= std_logic_vector(unsigned(bin) + 1);
- end if;
+ determine_bin : process (clk)
+ begin
+ if rising_edge(clk) then
+ if unswitch_val = '1' then
+ bin <= std_logic_vector(unsigned(bin) + 1);
end if;
- end process;
+ end if;
+ end process;
- band <= bin(bin'high downto 1);
+ band <= bin(bin'high downto 1);
- power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ power <= std_logic_vector( signed(unswitch_re) * signed(unswitch_re)
+ signed(unswitch_im) * signed(unswitch_im)
- ) when unswitch_val = '1' else (others => '0');
-
- -- Wave window: View fft_re, fft_im in analogue format
- -- Wave window: View power in binary format to get a spectrum diagram
-
- -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
- -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
-
- -- Use clk to avoid limit cycle pulses in power_x and power_y
- demux_power : process(clk)
- begin
- if falling_edge(clk) then
- if unswitch_val = '1' then
- if bin(0) = '0' then
- fft_x_re <= unswitch_re;
- fft_x_im <= unswitch_im;
- power_x <= power;
- else
- fft_y_re <= unswitch_re;
- fft_y_im <= unswitch_im;
- power_y <= power;
- end if;
+ ) when unswitch_val = '1' else (others => '0');
+
+ -- Wave window: View fft_re, fft_im in analogue format
+ -- Wave window: View power in binary format to get a spectrum diagram
+
+ -- power_x <= power WHEN bin(0) = '0' ELSE power_x;
+ -- power_y <= power WHEN bin(0) = '1' ELSE power_y;
+
+ -- Use clk to avoid limit cycle pulses in power_x and power_y
+ demux_power : process(clk)
+ begin
+ if falling_edge(clk) then
+ if unswitch_val = '1' then
+ if bin(0) = '0' then
+ fft_x_re <= unswitch_re;
+ fft_x_im <= unswitch_im;
+ power_x <= power;
+ else
+ fft_y_re <= unswitch_re;
+ fft_y_im <= unswitch_im;
+ power_y <= power;
end if;
end if;
- end process;
+ end if;
+ end process;
+
-- synthesis translate_on
out_re <= unswitch_re;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 36e8e2a0075c428aee6e6f9a319fd30ec9a899c6..908aac668899c536c9095f9e0f3f10fc99f4c219 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf is
constant c_read_pipeline : natural := 1;
@@ -12,7 +12,7 @@ architecture rtl of pft_bf is
constant c_pipeline : natural := c_read_pipeline + c_add_pipeline + c_write_pipeline;
constant c_cnt_w : natural := g_index + 2;
constant c_regbank_size_w : natural := g_index;
- constant c_regbank_size : natural := 2**c_regbank_size_w;
+ constant c_regbank_size : natural := 2 ** c_regbank_size_w;
constant c_dat_w : natural := g_in_dat_w + 1;
type sig_rec is record
@@ -209,11 +209,11 @@ begin
end if;
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -237,119 +237,121 @@ begin
--);
cadd : entity common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
+
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
+
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 52eebaf095bcdbb3292059b408909b75c15f7ed5..30a9864208060bd60b6458653f929e6af218602c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -59,7 +59,7 @@ architecture rtl of pft_bf is
constant c_pipeline : natural := c_read_pipeline + c_add_pipeline + c_write_pipeline;
constant c_cnt_w : natural := g_index + 2;
constant c_regbank_size_w : natural := g_index;
- constant c_regbank_size : natural := 2**c_regbank_size_w;
+ constant c_regbank_size : natural := 2 ** c_regbank_size_w;
constant c_dat_w : natural := g_in_dat_w + 1;
type sig_rec is record
@@ -256,11 +256,11 @@ begin
end if;
end process;
--- Adds/ Subs ------------------------------------------------------------------
+ -- Adds/ Subs ------------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--cadd : ENTITY common_lib.common_caddsub
--GENERIC MAP (
@@ -284,119 +284,121 @@ begin
--);
cadd : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => add_ar,
- in_ai => add_ai,
- in_br => add_br,
- in_bi => add_bi,
- out_re => add_cr,
- out_im => add_ci
- );
-
--- csub : ENTITY common_lib.common_caddsub
--- GENERIC MAP (
--- g_in_a_w => c_dat_w,
--- g_in_b_w => c_dat_w,
--- g_out_c_w => c_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_ar => sub_ar,
--- in_ai => sub_ai,
--- in_br => sub_br,
--- in_bi => sub_bi,
--- in_cr => '1',
--- in_ci => '1',
--- out_cr => sub_cr,
--- out_ci => sub_ci,
--- clk => clk,
--- rst => rst
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => add_ar,
+ in_ai => add_ai,
+ in_br => add_br,
+ in_bi => add_bi,
+ out_re => add_cr,
+ out_im => add_ci
+ );
+
+ -- csub : ENTITY common_lib.common_caddsub
+ -- GENERIC MAP (
+ -- g_in_a_w => c_dat_w,
+ -- g_in_b_w => c_dat_w,
+ -- g_out_c_w => c_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_ar => sub_ar,
+ -- in_ai => sub_ai,
+ -- in_br => sub_br,
+ -- in_bi => sub_bi,
+ -- in_cr => '1',
+ -- in_ci => '1',
+ -- out_cr => sub_cr,
+ -- out_ci => sub_ci,
+ -- clk => clk,
+ -- rst => rst
+ -- );
csub : entity common_lib.common_complex_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_ar => sub_ar,
- in_ai => sub_ai,
- in_br => sub_br,
- in_bi => sub_bi,
- out_re => sub_cr,
- out_im => sub_ci
- );
-
--- regbank --------------------------------------------------------------------------
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_ar => sub_ar,
+ in_ai => sub_ai,
+ in_br => sub_br,
+ in_bi => sub_bi,
+ out_re => sub_cr,
+ out_im => sub_ci
+ );
+
+ -- regbank --------------------------------------------------------------------------
fifo_gen: if c_regbank_size > 8 generate
- fifo : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => wr_dat'LENGTH,
- g_nof_words => c_regbank_size
- )
- port map (
- wr_dat => wr_dat,
- wr_req => wr_req,
- rd_dat => rd_dat,
- rd_req => rd_req,
- clk => clk,
- rst => rst
- );
+ fifo : entity common_lib.common_fifo_sc
+ generic map (
+ g_dat_w => wr_dat'LENGTH,
+ g_nof_words => c_regbank_size
+ )
+ port map (
+ wr_dat => wr_dat,
+ wr_req => wr_req,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ clk => clk,
+ rst => rst
+ );
end generate fifo_gen;
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
- fifo2_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo2_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
+
+ fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
fifo3_gen : if c_regbank_size = c_pipeline generate
- fifo3_reg : process (clk, rst)
- begin
- if rst = '1' then
- fifo_dat <= (others => (others => '0'));
- elsif rising_edge(clk) then
- fifo_dat <= nxt_fifo_dat;
- end if;
- end process;
- fifo3_proc : process(fifo_dat, wr_req, wr_dat)
- begin
- nxt_fifo_dat <= fifo_dat;
- if wr_req = '1' then
- nxt_fifo_dat(0) <= wr_dat;
- end if;
- rd_dat <= fifo_dat(0);
- end process;
+ fifo3_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ fifo_dat <= (others => (others => '0'));
+ elsif rising_edge(clk) then
+ fifo_dat <= nxt_fifo_dat;
+ end if;
+ end process;
+
+ fifo3_proc : process(fifo_dat, wr_req, wr_dat)
+ begin
+ nxt_fifo_dat <= fifo_dat;
+ if wr_req = '1' then
+ nxt_fifo_dat(0) <= wr_dat;
+ end if;
+ rd_dat <= fifo_dat(0);
+ end process;
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index c8467e44759e8f153de12a1fc307f04e6963a553..0e83427857df438bd41ff5779271efbebe5b2be3 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -1,13 +1,13 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_bf_fw is
constant c_add_pipeline : natural := 2;
- constant c_dist : natural := 2**g_index;
+ constant c_dist : natural := 2 ** g_index;
constant c_pipeline : natural := c_add_pipeline + c_dist + 2;
constant c_cnt_w : natural := g_index + 2;
@@ -154,79 +154,79 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index f777f5e18d382a71341aaa2c01de40cff0f3f6e2..b0dbafcaa74721f203418f3a990c4688053963f0 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
@@ -54,7 +54,7 @@ end pft_bf_fw;
architecture rtl of pft_bf_fw is
constant c_add_pipeline : natural := 2;
- constant c_dist : natural := 2**g_index;
+ constant c_dist : natural := 2 ** g_index;
constant c_pipeline : natural := c_add_pipeline + c_dist + 2;
constant c_cnt_w : natural := g_index + 2;
@@ -201,79 +201,79 @@ begin
-- Adds/ Subs ----------------------------------------------------------------
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- yr_cry <= NOT yr_add;
-
--- yr : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yr_a,
--- in_b => yr_b,
--- in_cry => yr_cry,
--- add_sub => yr_add,
--- clk => clk,
--- out_c => out_re
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- yr_cry <= NOT yr_add;
+
+ -- yr : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yr_a,
+ -- in_b => yr_b,
+ -- in_cry => yr_cry,
+ -- add_sub => yr_add,
+ -- clk => clk,
+ -- out_c => out_re
+ -- );
yr : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yr_add,
- in_a => yr_a,
- in_b => yr_b,
- result => out_re
- );
-
--- yi_cry <= NOT yi_add;
---
--- yi : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => g_in_dat_w,
--- g_in_b_w => g_in_dat_w,
--- g_out_c_w => g_out_dat_w,
--- g_pipeline => c_add_pipeline,
--- g_add_sub => "BOTH"
--- )
--- PORT MAP (
--- in_a => yi_a,
--- in_b => yi_b,
--- in_cry => yi_cry,
--- add_sub => yi_add,
--- clk => clk,
--- out_c => out_im
--- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yr_add,
+ in_a => yr_a,
+ in_b => yr_b,
+ result => out_re
+ );
+
+ -- yi_cry <= NOT yi_add;
+ --
+ -- yi : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => g_in_dat_w,
+ -- g_in_b_w => g_in_dat_w,
+ -- g_out_c_w => g_out_dat_w,
+ -- g_pipeline => c_add_pipeline,
+ -- g_add_sub => "BOTH"
+ -- )
+ -- PORT MAP (
+ -- in_a => yi_a,
+ -- in_b => yi_b,
+ -- in_cry => yi_cry,
+ -- add_sub => yi_add,
+ -- clk => clk,
+ -- out_c => out_im
+ -- );
yi : entity common_lib.common_add_sub
- generic map (
- g_direction => "BOTH",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_pipeline, -- >= 0
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- sel_add => yi_add,
- in_a => yi_a,
- in_b => yi_b,
- result => out_im
- );
+ generic map (
+ g_direction => "BOTH",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_pipeline, -- >= 0
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ sel_add => yi_add,
+ in_a => yi_a,
+ in_b => yi_b,
+ result => out_im
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index 85ff4fdba8fa3418b4ad97b1822d11048cf95d67..23816c5623ec7314cb5b306d94018c2e1d98ef49 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -1,46 +1,47 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_buffer is
constant c_latency : natural := 2;
constant c_adr_w : natural := g_fft_size_w + 1;
- constant c_nof_words : natural := 2**c_adr_w;
+ constant c_nof_words : natural := 2 ** c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0');
- signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
- signal wr_dat : std_logic_vector(rd_dat'range);
- signal rd_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
- signal wr_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
- signal wr_adr : std_logic_vector(g_fft_size_w - 1 downto 0);
- signal nxt_wr_adr : std_logic_vector(wr_adr'range);
- signal wr_page : std_logic;
- signal nxt_wr_page : std_logic;
- signal rd_page : std_logic;
- signal nxt_rd_page : std_logic;
- signal wr_en : std_logic;
+ signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
+ signal wr_dat : std_logic_vector(rd_dat'range);
+ signal rd_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
+ signal wr_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
+ signal wr_adr : std_logic_vector(g_fft_size_w - 1 downto 0);
+ signal nxt_wr_adr : std_logic_vector(wr_adr'range);
+ signal wr_page : std_logic;
+ signal nxt_wr_page : std_logic;
+ signal rd_page : std_logic;
+ signal nxt_rd_page : std_logic;
+ signal wr_en : std_logic;
- signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
- signal nxt_pipe_val : std_logic_vector(pipe_val'range);
+ signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
+ signal nxt_pipe_val : std_logic_vector(pipe_val'range);
- function bit_rev(adr : in std_logic_vector) return std_logic_vector is
- variable result: std_logic_vector(adr'range);
- begin
- for i in adr'high downto 0 loop
- result(i) := adr(adr'high - i);
- end loop;
- return result;
- end function;
+ function bit_rev(adr : in std_logic_vector) return std_logic_vector is
+ variable result: std_logic_vector(adr'range);
+ begin
+ for i in adr'high downto 0 loop
+ result(i) := adr(adr'high - i);
+ end loop;
+ return result;
+ end function;
begin
nxt_rd_page <= not nxt_wr_page;
rd_adr_paged <= rd_page & rd_adr;
@@ -101,36 +102,36 @@ begin
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 33f764deb9248f081270a60e9b8f988ee8ba4d68..39c3fa39f1641ecfc9416fb2b9da5eca881aaa11 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -24,12 +24,12 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity pft_buffer is
generic (
@@ -56,37 +56,38 @@ end pft_buffer;
architecture rtl of pft_buffer is
constant c_latency : natural := 2;
constant c_adr_w : natural := g_fft_size_w + 1;
- constant c_nof_words : natural := 2**c_adr_w;
+ constant c_nof_words : natural := 2 ** c_adr_w;
- constant c_ram : t_c_mem := (latency => c_latency,
- adr_w => c_adr_w,
- dat_w => 2 * g_dat_w,
- nof_dat => c_nof_words, -- <= 2**g_addr_w
- init_sl => '0');
+ constant c_ram : t_c_mem := (
+ latency => c_latency,
+ adr_w => c_adr_w,
+ dat_w => 2 * g_dat_w,
+ nof_dat => c_nof_words, -- <= 2**g_addr_w
+ init_sl => '0');
- signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
- signal wr_dat : std_logic_vector(rd_dat'range);
- signal rd_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
- signal wr_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
- signal wr_adr : std_logic_vector(g_fft_size_w - 1 downto 0);
- signal nxt_wr_adr : std_logic_vector(wr_adr'range);
- signal wr_page : std_logic;
- signal nxt_wr_page : std_logic;
- signal rd_page : std_logic;
- signal nxt_rd_page : std_logic;
- signal wr_en : std_logic;
+ signal rd_dat : std_logic_vector(2 * g_dat_w - 1 downto 0);
+ signal wr_dat : std_logic_vector(rd_dat'range);
+ signal rd_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
+ signal wr_adr_paged : std_logic_vector(c_adr_w - 1 downto 0);
+ signal wr_adr : std_logic_vector(g_fft_size_w - 1 downto 0);
+ signal nxt_wr_adr : std_logic_vector(wr_adr'range);
+ signal wr_page : std_logic;
+ signal nxt_wr_page : std_logic;
+ signal rd_page : std_logic;
+ signal nxt_rd_page : std_logic;
+ signal wr_en : std_logic;
- signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
- signal nxt_pipe_val : std_logic_vector(pipe_val'range);
+ signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
+ signal nxt_pipe_val : std_logic_vector(pipe_val'range);
- function bit_rev(adr : in std_logic_vector) return std_logic_vector is
- variable result: std_logic_vector(adr'range);
- begin
- for i in adr'high downto 0 loop
- result(i) := adr(adr'high - i);
- end loop;
- return result;
- end function;
+ function bit_rev(adr : in std_logic_vector) return std_logic_vector is
+ variable result: std_logic_vector(adr'range);
+ begin
+ for i in adr'high downto 0 loop
+ result(i) := adr(adr'high - i);
+ end loop;
+ return result;
+ end function;
begin
nxt_rd_page <= not nxt_wr_page;
rd_adr_paged <= rd_page & rd_adr;
@@ -147,36 +148,36 @@ begin
wr_dat <= wr_re & wr_im;
wr_en <= wr_val;
--- -- ram module
--- ram : ENTITY common_lib.common_dpram
--- GENERIC MAP (
--- g_dat_w => 2*g_dat_w,
--- g_adr_w => c_adr_w,
--- g_nof_words => c_nof_words
--- )
--- PORT MAP (
--- rd_dat => rd_dat,
--- rd_adr => rd_adr_paged,
--- rd_en => rd_en,
--- wr_dat => wr_dat,
--- wr_adr => wr_adr_paged,
--- wr_en => wr_en,
--- clk => clk,
--- rst => rst
--- );
+ -- -- ram module
+ -- ram : ENTITY common_lib.common_dpram
+ -- GENERIC MAP (
+ -- g_dat_w => 2*g_dat_w,
+ -- g_adr_w => c_adr_w,
+ -- g_nof_words => c_nof_words
+ -- )
+ -- PORT MAP (
+ -- rd_dat => rd_dat,
+ -- rd_adr => rd_adr_paged,
+ -- rd_en => rd_en,
+ -- wr_dat => wr_dat,
+ -- wr_adr => wr_adr_paged,
+ -- wr_en => wr_en,
+ -- clk => clk,
+ -- rst => rst
+ -- );
ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_en,
- wr_adr => wr_adr_paged,
- wr_dat => wr_dat,
- rd_en => rd_en,
- rd_adr => rd_adr_paged,
- rd_dat => rd_dat
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_en,
+ wr_adr => wr_adr_paged,
+ wr_dat => wr_dat,
+ rd_en => rd_en,
+ rd_adr => rd_adr_paged,
+ rd_dat => rd_dat
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
index 73c752e25b1ca2a39e139d33bf2679c903f3049f..dcc668e24d7568f2e0f7fe49d7a3f2c6fcbaeba6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
@@ -1,5 +1,5 @@
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
architecture rtl of pft_lfsr is
-- uses preferred pair of pritive trinomials
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index c6250be5bcfe8928822af3b70a4ea08bd354f43f..eeb6d51c739903ecc944acca9075f6caa965b04c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_lfsr is
port (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
index 75fcb992ca37e651d4d4fac16d9fc9a089c70e99..3da701efe2892081a1c1d3e954f0b5db2992c5df 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
@@ -24,8 +24,8 @@
-- Remark: Copy of pft(pkg).vhd to avoid () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
package pft_pkg is
constant c_pft_twiddle_w : natural := 16;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
index 86d5cdd9f8b248a002e0fb1f7400bdf123eebcbc..db768abce60c1712b0c5d6d34eea8bdd32ce57f9 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
@@ -1,6 +1,6 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
architecture rtl of pft_reverse is
signal i_rdaddr : std_logic_vector(rdaddr'range);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
index 80ebdc99694b1ed0082d0329a9a70f65f1014c96..488813a0019384d8fb37b25b194c5d39c6b39cd6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_reverse is
generic (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index 885d8a147e4ce267f05bdcc4e7fbf506db9f85c8..fdc7d0ee7dfd7775299a7d1fe3467a8e934c337c 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use common_lib.all;
+ use common_lib.all;
architecture rtl of pft_separate is
constant c_reg_delay : natural := 2;
@@ -164,71 +164,71 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
-
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
-
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
+
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 538b57aac83328aa950606c8ec148b4e48c09ae2..5967f04f720278f2c51f3f1c404cbec7496ff27d 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_separate is
generic (
@@ -210,71 +210,71 @@ begin
nxt_out_val <= rdval_dly(rdval_dly'high);
nxt_out_sync <= rdsync_dly(rdsync_dly'high);
--- Intel Altera lmp_add_sub carry in:
--- ADD: out = a + b + cin => cin = '0' to have out = a + b
--- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
+ -- Intel Altera lmp_add_sub carry in:
+ -- ADD: out = a + b + cin => cin = '0' to have out = a + b
+ -- SUB: out = a - b + cin - 1 => cin = '1' to have out = a - b
--- add : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => add0'LENGTH,
--- g_in_b_w => add1'LENGTH,
--- g_out_c_w => add_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "ADD"
--- )
--- PORT MAP (
--- in_a => add0,
--- in_b => add1,
--- in_cry => '0',
--- out_c => add_out,
--- clk => clk
--- );
+ -- add : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => add0'LENGTH,
+ -- g_in_b_w => add1'LENGTH,
+ -- g_out_c_w => add_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "ADD"
+ -- )
+ -- PORT MAP (
+ -- in_a => add0,
+ -- in_b => add1,
+ -- in_cry => '0',
+ -- out_c => add_out,
+ -- clk => clk
+ -- );
add : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => add0,
- in_b => add1,
- result => add_out
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => add0,
+ in_b => add1,
+ result => add_out
+ );
--- sub : ENTITY common_lib.common_addsub
--- GENERIC MAP (
--- g_in_a_w => sub0'LENGTH,
--- g_in_b_w => sub1'LENGTH,
--- g_out_c_w => sub_out'LENGTH,
--- g_pipeline => c_add_delay-1,
--- g_add_sub => "SUB"
--- )
--- PORT MAP (
--- in_a => sub0,
--- in_b => sub1,
--- in_cry => '1',
--- out_c => sub_out,
--- clk => clk
--- );
+ -- sub : ENTITY common_lib.common_addsub
+ -- GENERIC MAP (
+ -- g_in_a_w => sub0'LENGTH,
+ -- g_in_b_w => sub1'LENGTH,
+ -- g_out_c_w => sub_out'LENGTH,
+ -- g_pipeline => c_add_delay-1,
+ -- g_add_sub => "SUB"
+ -- )
+ -- PORT MAP (
+ -- in_a => sub0,
+ -- in_b => sub1,
+ -- in_cry => '1',
+ -- out_c => sub_out,
+ -- clk => clk
+ -- );
sub : entity common_lib.common_add_sub
- generic map (
- g_direction => "SUB",
- g_representation => "SIGNED",
- g_pipeline_input => 0, -- 0 or 1
- g_pipeline_output => c_add_delay - 1, -- >= 0
- g_in_dat_w => g_rd_dat_w,
- g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
- )
- port map (
- clk => clk,
- in_a => sub0,
- in_b => sub1,
- result => sub_out
- );
+ generic map (
+ g_direction => "SUB",
+ g_representation => "SIGNED",
+ g_pipeline_input => 0, -- 0 or 1
+ g_pipeline_output => c_add_delay - 1, -- >= 0
+ g_in_dat_w => g_rd_dat_w,
+ g_out_dat_w => g_out_dat_w -- only support g_out_dat_w=g_in_dat_w and g_out_dat_w=g_in_dat_w+1
+ )
+ port map (
+ clk => clk,
+ in_a => sub0,
+ in_b => sub1,
+ result => sub_out
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
index b4069cd55e894f35425bc864e9ccead2124b2f93..6a04eae8ed6017773817e4792c9f4cd41b9136d0 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library common_lib, pft2_lib;
-use common_lib.all;
+ use common_lib.all;
architecture str of pft_stage is
constant c_round_pipeline_in : natural := 1;
@@ -42,128 +42,128 @@ architecture str of pft_stage is
begin
gen_middle: if g_index > 0 generate
bf1 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity pft2_lib.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity pft2_lib.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
signal reg_val : std_logic;
signal reg_sync : std_logic;
- begin
+ begin
bf1_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity pft2_lib.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
@@ -179,7 +179,5 @@ begin
reg_sync <= bf2_sync;
end if;
end process;
-
end generate;
-
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
index 08b73281a27042197d8ee89d6f075cf2c1679cfd..92136c13900392ca75401d2005bc486c0205b064 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
@@ -24,7 +24,7 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity pft_stage is
generic (
@@ -43,7 +43,7 @@ entity pft_stage is
out_sync : out std_logic;
clk : in std_logic;
rst : in std_logic
- );
+ );
end pft_stage;
architecture str of pft_stage is
@@ -66,128 +66,128 @@ architecture str of pft_stage is
begin
gen_middle: if g_index > 0 generate
bf1 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2 : entity work.pft_bf
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
tmult : entity work.pft_tmult
- generic map (
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w,
- g_index => g_index
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- in_val => bf2_val,
- in_sync => bf2_sync,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w,
+ g_index => g_index
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ in_val => bf2_val,
+ in_sync => bf2_sync,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
end generate;
gen_last: if g_index = 0 generate
signal reg_val : std_logic;
signal reg_sync : std_logic;
- begin
+ begin
bf1_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index + 1,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_bf1_out_w,
- g_bf_name => "bf1"
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- in_val => in_val,
- in_sync => in_sync,
- out_re => bf1_re,
- out_im => bf1_im,
- out_val => bf1_val,
- out_sync => bf1_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index + 1,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_bf1_out_w,
+ g_bf_name => "bf1"
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_re => bf1_re,
+ out_im => bf1_im,
+ out_val => bf1_val,
+ out_sync => bf1_sync,
+ clk => clk,
+ rst => rst
+ );
bf2_fw : entity work.pft_bf_fw
- generic map (
- g_index => 2 * g_index,
- g_in_dat_w => c_bf1_out_w,
- g_out_dat_w => c_bf2_out_w,
- g_bf_name => "bf2"
- )
- port map (
- in_re => bf1_re,
- in_im => bf1_im,
- in_val => bf1_val,
- in_sync => bf1_sync,
- out_re => bf2_re,
- out_im => bf2_im,
- out_val => bf2_val,
- out_sync => bf2_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_index => 2 * g_index,
+ g_in_dat_w => c_bf1_out_w,
+ g_out_dat_w => c_bf2_out_w,
+ g_bf_name => "bf2"
+ )
+ port map (
+ in_re => bf1_re,
+ in_im => bf1_im,
+ in_val => bf1_val,
+ in_sync => bf1_sync,
+ out_re => bf2_re,
+ out_im => bf2_im,
+ out_val => bf2_val,
+ out_sync => bf2_sync,
+ clk => clk,
+ rst => rst
+ );
u_rnd : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_bf2_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => bf2_re,
- in_im => bf2_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_bf2_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => bf2_re,
+ in_im => bf2_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
p_regs: process(clk,rst)
begin
@@ -203,7 +203,5 @@ begin
reg_sync <= bf2_sync;
end if;
end process;
-
end generate;
-
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
index f721e586262435efb9becf043fdc10c9dacd8185..a5aed7fc373cc12eeb1b310df8c0ee8d74bc56e4 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
@@ -1,22 +1,22 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -73,11 +73,11 @@ begin
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
index 0c6daed641bee4d02364616f52b3da4f03912ad7..a8d8275f8c60eb3817ba3ed4fa8fdda3ef68c3f5 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_switch is
generic (
@@ -48,17 +48,17 @@ entity pft_switch is
end pft_switch;
architecture rtl of pft_switch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -115,11 +115,11 @@ begin
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index fc220fa98cf914dfde56a210489d62a7a3db4f9d..fc38feaae6566d855649d3e7f35c47c403263459 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -20,67 +20,68 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
architecture rtl of pft_tmult is
- constant c_nof_twids : natural := 16 * 2**(2 * (g_index - 1));
+ constant c_nof_twids : natural := 16 * 2 ** (2 * (g_index - 1));
constant c_adr_w : natural := 2 + 2 * g_index;
constant c_mult_in_w : natural := 18;
constant c_coeff_w : natural := 16;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
-
- constant c_twid_file : string :=
- "data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --CONSTANT c_twid_file : STRING :=
- -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
- -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
-
- constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
- constant c_round_pipeline_in : natural := 1;
- constant c_round_pipeline_out : natural := 1;
- constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
- constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
-
- signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
- signal nxt_reg_val : std_logic_vector(reg_val'range);
- signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
-
- signal nxt_reg_sync : std_logic_vector(reg_sync'range);
-
- signal adr : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
-
- signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_cnt : std_logic_vector(cnt'range);
-
- signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
- signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
-
- signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
- signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
-
- signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
- signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
- signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0');
+
+ constant c_twid_file : string :=
+ "data/twiddle_" & natural'image(c_coeff_w)
+ & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --CONSTANT c_twid_file : STRING :=
+ -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+
+ constant c_read_pipeline : natural := 1;
+ constant c_mult_pipeline_input : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0; -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_output : natural := 1; -- >= 0
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ constant c_round_pipeline_in : natural := 1;
+ constant c_round_pipeline_out : natural := 1;
+ constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
+ constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
+
+ signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
+ signal nxt_reg_val : std_logic_vector(reg_val'range);
+ signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
+
+ signal nxt_reg_sync : std_logic_vector(reg_sync'range);
+
+ signal adr : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
+
+ signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
+
+ signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
+ signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
+
+ signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
+ signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
+
+ signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
+ signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
+ signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
begin
p_regs : process (clk, rst)
begin
@@ -127,72 +128,72 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index e6ab7f98a95ffa1977924cc1b3b6c11e64902133..f3ff9877b3993d9296ce8da904c54a37062101ab 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -24,14 +24,14 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_mult_lib;
library common_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.pft_pkg.all;
entity pft_tmult is
generic (
@@ -54,58 +54,59 @@ entity pft_tmult is
end pft_tmult;
architecture rtl of pft_tmult is
- constant c_nof_twids : natural := 16 * 2**(2 * (g_index - 1));
+ constant c_nof_twids : natural := 16 * 2 ** (2 * (g_index - 1));
constant c_adr_w : natural := 2 + 2 * g_index;
constant c_mult_in_w : natural := 18;
constant c_coeff_w : natural := c_pft_twiddle_w;
constant c_mult_out_w : natural := c_mult_in_w + c_coeff_w - 1;
- constant c_twid_rom : t_c_mem := (latency => 2,
- adr_w => c_adr_w,
- dat_w => 2 * c_coeff_w, -- complex
- nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
- init_sl => '0');
-
- constant c_twid_file : string :=
- "data/twiddle_" & natural'image(c_coeff_w)
- & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
- --CONSTANT c_twid_file : STRING :=
- -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
- -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
-
- constant c_read_pipeline : natural := 1;
- constant c_mult_pipeline_input : natural := 1; -- 0 or 1
- constant c_mult_pipeline_product : natural := 0; -- 0 or 1
- constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
- constant c_mult_pipeline_output : natural := 1; -- >= 0
- constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
- constant c_round_pipeline_in : natural := 1;
- constant c_round_pipeline_out : natural := 1;
- constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
- constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
-
- signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
- signal nxt_reg_val : std_logic_vector(reg_val'range);
- signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
-
- signal nxt_reg_sync : std_logic_vector(reg_sync'range);
-
- signal adr : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
-
- signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
- signal nxt_cnt : std_logic_vector(cnt'range);
-
- signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
- signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
-
- signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
- signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
-
- signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
- signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
- signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
+ constant c_twid_rom : t_c_mem := (
+ latency => 2,
+ adr_w => c_adr_w,
+ dat_w => 2 * c_coeff_w, -- complex
+ nof_dat => 3 * c_nof_twids / 4, -- <= 2**g_addr_w
+ init_sl => '0');
+
+ constant c_twid_file : string :=
+ "data/twiddle_" & natural'image(c_coeff_w)
+ & "_" & natural'image(g_index) & ".hex"; -- Quartus .hex extension, replaced by .bin in common_rom works for XST
+ --CONSTANT c_twid_file : STRING :=
+ -- "../../../../../pft2/src/data/twiddle_" & NATURAL'IMAGE(c_coeff_w)
+ -- & "_" & NATURAL'IMAGE(g_index) & ".bin"; -- Synplify fails on file extension change to .bin in common_rom and requires extra ../
+
+ constant c_read_pipeline : natural := 1;
+ constant c_mult_pipeline_input : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_product : natural := 0; -- 0 or 1
+ constant c_mult_pipeline_adder : natural := 1; -- 0 or 1
+ constant c_mult_pipeline_output : natural := 1; -- >= 0
+ constant c_mult_pipeline : natural := c_mult_pipeline_input + c_mult_pipeline_product + c_mult_pipeline_adder + c_mult_pipeline_output; -- = 3
+ constant c_round_pipeline_in : natural := 1;
+ constant c_round_pipeline_out : natural := 1;
+ constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
+ constant c_pipeline : natural := c_round_pipeline + c_mult_pipeline + c_round_pipeline;
+
+ signal reg_val : std_logic_vector(c_pipeline-1 downto 0);
+ signal nxt_reg_val : std_logic_vector(reg_val'range);
+ signal reg_sync : std_logic_vector(c_pipeline-1 downto 0);
+
+ signal nxt_reg_sync : std_logic_vector(reg_sync'range);
+
+ signal adr : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_adr : std_logic_vector(c_adr_w - 1 downto 0);
+
+ signal cnt : std_logic_vector(c_adr_w - 1 downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
+
+ signal mult_in_re : std_logic_vector(c_mult_in_w - 1 downto 0);
+ signal mult_in_im : std_logic_vector(c_mult_in_w - 1 downto 0);
+
+ signal mult_out_re : std_logic_vector(c_mult_out_w - 1 downto 0);
+ signal mult_out_im : std_logic_vector(c_mult_out_w - 1 downto 0);
+
+ signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
+ signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
+ signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
begin
p_regs : process (clk, rst)
begin
@@ -152,72 +153,72 @@ begin
out_sync <= reg_sync(0);
u_coeff : entity common_lib.common_rom
- generic map (
- g_ram => c_twid_rom,
- g_init_file => c_twid_file
- )
- port map (
- rst => rst,
- clk => clk,
- rd_adr => adr,
- rd_dat => coeff_dat
- );
+ generic map (
+ g_ram => c_twid_rom,
+ g_init_file => c_twid_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rd_adr => adr,
+ rd_dat => coeff_dat
+ );
u_rnd1 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_mult_in_w
- )
- port map (
- in_re => in_re,
- in_im => in_im,
- out_re => mult_in_re,
- out_im => mult_in_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_mult_in_w
+ )
+ port map (
+ in_re => in_re,
+ in_im => in_im,
+ out_re => mult_in_re,
+ out_im => mult_in_im,
+ clk => clk
+ );
u_cmult : entity common_mult_lib.common_complex_mult
- generic map (
- g_variant => "IP",
- g_in_a_w => c_mult_in_w,
- g_in_b_w => c_coeff_w,
- g_out_p_w => c_mult_out_w,
- g_conjugate_b => false,
- g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
- g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
- g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
- g_pipeline_output => c_mult_pipeline_output -- >= 0
- )
- port map (
- in_ar => mult_in_re,
- in_ai => mult_in_im,
- in_br => coeff_re,
- in_bi => coeff_im,
- out_pr => mult_out_re,
- out_pi => mult_out_im,
- clk => clk
- );
+ generic map (
+ g_variant => "IP",
+ g_in_a_w => c_mult_in_w,
+ g_in_b_w => c_coeff_w,
+ g_out_p_w => c_mult_out_w,
+ g_conjugate_b => false,
+ g_pipeline_input => c_mult_pipeline_input, -- 0 or 1
+ g_pipeline_product => c_mult_pipeline_product, -- 0 or 1
+ g_pipeline_adder => c_mult_pipeline_adder, -- 0 or 1
+ g_pipeline_output => c_mult_pipeline_output -- >= 0
+ )
+ port map (
+ in_ar => mult_in_re,
+ in_ai => mult_in_im,
+ in_br => coeff_re,
+ in_bi => coeff_im,
+ out_pr => mult_out_re,
+ out_pi => mult_out_im,
+ clk => clk
+ );
u_rnd2 : entity common_lib.common_complex_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_round_pipeline_in,
- g_pipeline_output => c_round_pipeline_out,
- g_in_dat_w => c_mult_out_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- in_re => mult_out_re,
- in_im => mult_out_im,
- out_re => out_re,
- out_im => out_im,
- clk => clk
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_round_pipeline_in,
+ g_pipeline_output => c_round_pipeline_out,
+ g_in_dat_w => c_mult_out_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ in_re => mult_out_re,
+ in_im => mult_out_im,
+ out_re => out_re,
+ out_im => out_im,
+ clk => clk
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
index 6edd1a89f60db877e92ec5a3fc0c897ca8cad584..7836e4672bc9e4d33d37f2912011bd9fe1eb6bae 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
@@ -1,6 +1,6 @@
library IEEE, common_lib, pft2_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
architecture str of pft_top is
signal reg_in_re : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -33,23 +33,23 @@ begin
end process;
u_pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => g_mode
- )
- port map (
- in_re => reg_in_re,
- in_im => reg_in_im,
- in_val => reg_in_val,
- in_sync => reg_in_sync,
- switch_en => switch_en,
- out_re => d_out_re,
- out_im => d_out_im,
- out_val => d_out_val,
- out_sync => d_out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => g_mode
+ )
+ port map (
+ in_re => reg_in_re,
+ in_im => reg_in_im,
+ in_val => reg_in_val,
+ in_sync => reg_in_sync,
+ switch_en => switch_en,
+ out_re => d_out_re,
+ out_im => d_out_im,
+ out_val => d_out_val,
+ out_sync => d_out_sync,
+ clk => clk,
+ rst => rst
+ );
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
index f6d0eeb201ee792c957c8ca6152ec348f30e9341..80f58fd09b18ffd331ef53e4ebdb1fccf2a9fa79 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
@@ -1,9 +1,9 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.pft_pkg.all;
+ use pft2_lib.pft_pkg.all;
entity pft_top is
generic (
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
index e12c3622fe32f9a7f9dd5390db7f249959ea1788..6145d432458d75e5628ec830ef4c88df2a9a8ac9 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
@@ -1,23 +1,23 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib;
-use pft2_lib.all;
+ use pft2_lib.all;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -62,18 +62,18 @@ begin
nxt_out_re <= in_re;
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
- or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity pft2_lib.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index 726636e03b031b6933e1dfad0b6a0a8e589d7902..a2b0c3a6b6ea0519613d060cd5eb8cabb2321ba2 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -24,8 +24,8 @@
-- Remark: Put entity and architecture in same file without () in file name.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity pft_unswitch is
generic (
@@ -48,18 +48,18 @@ entity pft_unswitch is
end pft_unswitch;
architecture rtl of pft_unswitch is
-signal cnt : std_logic_vector(g_fft_sz_w downto 0);
-signal nxt_cnt : std_logic_vector(cnt'range);
+ signal cnt : std_logic_vector(g_fft_sz_w downto 0);
+ signal nxt_cnt : std_logic_vector(cnt'range);
-signal lfsr_bit1 : std_logic;
-signal lfsr_bit2 : std_logic;
+ signal lfsr_bit1 : std_logic;
+ signal lfsr_bit2 : std_logic;
-signal lfsr_en : std_logic;
+ signal lfsr_en : std_logic;
-signal nxt_out_val : std_logic;
-signal nxt_out_sync : std_logic;
-signal nxt_out_re : std_logic_vector(in_re'range);
-signal nxt_out_im : std_logic_vector(in_im'range);
+ signal nxt_out_val : std_logic;
+ signal nxt_out_sync : std_logic;
+ signal nxt_out_re : std_logic_vector(in_re'range);
+ signal nxt_out_im : std_logic_vector(in_im'range);
begin
registers : process (rst, clk)
begin
@@ -104,18 +104,18 @@ begin
nxt_out_re <= in_re;
nxt_out_im <= in_im;
if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1)
- or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
- nxt_out_re <= std_logic_vector(-signed(in_re));
- nxt_out_im <= std_logic_vector(-signed(in_im));
+ or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then
+ nxt_out_re <= std_logic_vector(-signed(in_re));
+ nxt_out_im <= std_logic_vector(-signed(in_im));
end if;
end process;
lfsr: entity work.pft_lfsr
- port map (
- clk => clk,
- rst => rst,
- in_en => lfsr_en,
- out_bit1 => lfsr_bit1,
- out_bit2 => lfsr_bit2
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ in_en => lfsr_en,
+ out_bit1 => lfsr_bit1,
+ out_bit2 => lfsr_bit2
+ );
end rtl;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
index 5294b0a66bf24ef523fb548d624319a6b7774459..c1c5418bd7a17acb39ecb46eb0069a3f46788edc 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
@@ -1,7 +1,7 @@
library ieee, pfs_lib, pft2_lib, tst_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use pft2_lib.pft_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use pft2_lib.pft_pkg.all;
entity tb_pft is
generic (
@@ -41,9 +41,9 @@ architecture tb of tb_pft is
signal out_val : std_logic;
signal out_sync : std_logic;
--- SIGNAL ref_re : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
--- SIGNAL ref_im : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
--- SIGNAL ref_val : STD_LOGIC;
+ -- SIGNAL ref_re : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
+ -- SIGNAL ref_im : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
+ -- SIGNAL ref_val : STD_LOGIC;
begin
rst <= '0' after g_rst_period;
val <= '1' after g_rst_period + g_clk_period / 2;
@@ -51,89 +51,89 @@ begin
clk <= not clk after g_clk_period / 2;
in_dat: entity tst_lib.tst_input
- generic map (
- g_file_name => c_pft_in_file,
- g_data_width => g_in_w
- )
- port map (
- clk => clk,
- rst => rst,
- en => '1',
- out_dat1 => in_x,
- out_dat2 => in_y,
- out_val => open -- in_val
- );
+ generic map (
+ g_file_name => c_pft_in_file,
+ g_data_width => g_in_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => '1',
+ out_dat1 => in_x,
+ out_dat2 => in_y,
+ out_val => open -- in_val
+ );
in_val <= val;
in_sync <= '0';
pfs : entity pfs_lib.pfs
- generic map (
- g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
- g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
- g_in_dat_w => g_in_w,
- g_out_dat_w => g_pfs_w,
- g_coef_dat_w => g_pfs_coef_w
- )
- port map (
- in_dat_x => in_x,
- in_dat_y => in_y,
- in_val => in_val,
- in_sync => in_sync,
- out_dat_x => pfs_x,
- out_dat_y => pfs_y,
- out_val => pfs_val,
- out_sync => pfs_sync,
- clk => clk,
- rst => rst,
- restart => '0'
- );
+ generic map (
+ g_nof_bands => 2**g_fft_size_w, -- 2*g_nof_subbands,
+ g_nof_taps => 2**g_fft_size_w * 16, -- 2*16*g_nof_subbands,
+ g_in_dat_w => g_in_w,
+ g_out_dat_w => g_pfs_w,
+ g_coef_dat_w => g_pfs_coef_w
+ )
+ port map (
+ in_dat_x => in_x,
+ in_dat_y => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ out_dat_x => pfs_x,
+ out_dat_y => pfs_y,
+ out_val => pfs_val,
+ out_sync => pfs_sync,
+ clk => clk,
+ rst => rst,
+ restart => '0'
+ );
pft : entity pft2_lib.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_pfs_w,
- g_out_dat_w => g_out_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => pfs_x,
- in_im => pfs_y,
- in_val => pfs_val,
- in_sync => pfs_sync,
- switch_en => '1',
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_pfs_w,
+ g_out_dat_w => g_out_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => pfs_x,
+ in_im => pfs_y,
+ in_val => pfs_val,
+ in_sync => pfs_sync,
+ switch_en => '1',
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
--- out_dat: ENTITY tst_lib.tst_output
--- GENERIC MAP (
--- g_file_name => c_pft_out_file,
--- g_data_width => out_re'LENGTH
--- )
--- PORT MAP (
--- clk => clk,
--- rst => rst,
--- in_dat1 => out_re,
--- in_dat2 => out_im,
--- in_val => out_val
--- );
+ -- out_dat: ENTITY tst_lib.tst_output
+ -- GENERIC MAP (
+ -- g_file_name => c_pft_out_file,
+ -- g_data_width => out_re'LENGTH
+ -- )
+ -- PORT MAP (
+ -- clk => clk,
+ -- rst => rst,
+ -- in_dat1 => out_re,
+ -- in_dat2 => out_im,
+ -- in_val => out_val
+ -- );
--- ref_dat: ENTITY tst_lib.tst_input
--- GENERIC MAP (
--- g_file_name => c_pft_ref_file,
--- g_data_width => ref_re'LENGTH
--- )
--- PORT MAP (
--- clk => clk,
--- rst => rst,
--- en => out_val,
--- out_dat1 => ref_re,
--- out_dat2 => ref_im,
--- out_val => ref_val
--- );
+ -- ref_dat: ENTITY tst_lib.tst_input
+ -- GENERIC MAP (
+ -- g_file_name => c_pft_ref_file,
+ -- g_data_width => ref_re'LENGTH
+ -- )
+ -- PORT MAP (
+ -- clk => clk,
+ -- rst => rst,
+ -- en => out_val,
+ -- out_dat1 => ref_re,
+ -- out_dat2 => ref_im,
+ -- out_val => ref_val
+ -- );
end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 7c4aa160e924e499109ada8f001609d5febcfb05..a0cf37a4d069aefee1fc6eaab62d389ff02873c8 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -32,11 +32,11 @@
-- - The tb works OK for all three PFT modes.
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.pft_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.pft_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_pft2 is
generic (
@@ -120,7 +120,7 @@ architecture tb of tb_pft2 is
constant c_file_pft_ref_y_im : string := c_tst_data_dir & g_name_y & ".im";
constant c_file_pft_dat_w : natural := 32;
- constant c_fft_size : natural := 2**c_fft_size_w;
+ constant c_fft_size : natural := 2 ** c_fft_size_w;
type t_ref_dat is array (0 to c_fft_size ) of integer; -- one extra dummy
type t_ref_fft_dat is array (0 to c_fft_size-1) of integer; -- PFT_MODE_BITREV, PFT_MODE_COMPLEX scaled and rounded
@@ -235,9 +235,10 @@ architecture tb of tb_pft2 is
return to_integer(ur);
end func_bitrev;
- procedure proc_fft_bitrev(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_bitrev(
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
constant w : natural := c_fft_size_w;
variable r : natural;
@@ -251,9 +252,10 @@ architecture tb of tb_pft2 is
end proc_fft_bitrev;
-- PFT_MODE_COMPLEX
- procedure proc_fft_complex(en : in std_logic;
- ref : in t_ref_dat;
- signal sr : out t_ref_fft_dat) is
+ procedure proc_fft_complex(
+ en : in std_logic;
+ ref : in t_ref_dat;
+ signal sr : out t_ref_fft_dat) is
constant N : natural := c_fft_size;
begin
if en = '1' then
@@ -269,10 +271,11 @@ architecture tb of tb_pft2 is
-- . PFT seperate does not divide by 2 in Xa(m) = [X*(N-m) + X(m)]/2, Xb(m)=j[X*(N-m) - X(m)]/2
-- . PFT seperate result for m=N is same as for m=0
-- . PFT seperate puts real result for m=N/2 in imag of m=0
- procedure proc_fft_real2_im(en : in std_logic;
- re : in t_ref_dat;
- im : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_im(
+ en : in std_logic;
+ re : in t_ref_dat;
+ im : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -287,9 +290,10 @@ architecture tb of tb_pft2 is
end if;
end proc_fft_real2_im;
- procedure proc_fft_real2_re(en : in std_logic;
- re : in t_ref_dat;
- signal sr : out t_ref_real2_dat) is
+ procedure proc_fft_real2_re(
+ en : in std_logic;
+ re : in t_ref_dat;
+ signal sr : out t_ref_real2_dat) is
constant N : natural := c_fft_size;
variable lo : integer;
variable hi : integer;
@@ -327,104 +331,104 @@ begin
-----------------------------------------------------------------------------
u_in_x: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_x,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_x,
- out_val => in_val_x
- );
+ generic map (
+ g_file_name => c_file_pft_in_x,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_x,
+ out_val => in_val_x
+ );
u_in_y: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_in_y,
- g_file_repeat => g_repeat,
- g_nof_data => 1,
- g_data_width => c_in_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_en,
- out_dat => in_dat_y,
- out_val => in_val_y
- );
+ generic map (
+ g_file_name => c_file_pft_in_y,
+ g_file_repeat => g_repeat,
+ g_nof_data => 1,
+ g_data_width => c_in_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_en,
+ out_dat => in_dat_y,
+ out_val => in_val_y
+ );
-----------------------------------------------------------------------------
-- Read expected Xre, Xim, Yre, Yim data
-----------------------------------------------------------------------------
u_ref_x_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_re,
- out_val => ref_val_x_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_re,
+ out_val => ref_val_x_re
+ );
u_ref_x_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_x_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_x_im,
- out_val => ref_val_x_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_x_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_x_im,
+ out_val => ref_val_x_im
+ );
u_ref_y_re: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_re,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_re,
- out_val => ref_val_y_re
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_re,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_re,
+ out_val => ref_val_y_re
+ );
u_ref_y_im: entity tst_lib.tst_input
- generic map (
- g_file_name => c_file_pft_ref_y_im,
- g_file_repeat => 1,
- g_nof_data => 1,
- g_data_width => c_file_pft_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => ref_en,
- out_dat => ref_dat_y_im,
- out_val => ref_val_y_im
- );
+ generic map (
+ g_file_name => c_file_pft_ref_y_im,
+ g_file_repeat => 1,
+ g_nof_data => 1,
+ g_data_width => c_file_pft_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => ref_en,
+ out_dat => ref_dat_y_im,
+ out_val => ref_val_y_im
+ );
p_ref_reg : process(clk)
begin
@@ -482,7 +486,7 @@ begin
gen_diff_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and diff_cnt < c_fft_size-1 else
0 when out_val_dly = '1' and diff_cnt = c_fft_size-1 else
- diff_cnt;
+ diff_cnt;
nxt_diff_rdy <= '1' when diff_cnt = c_fft_size-1 else '0';
diff_fft_re <= 0 when out_val_dly = '0' else ref_fft_dat_re(diff_cnt) - out_fft_re;
@@ -498,106 +502,106 @@ begin
begin
if diff_rdy = '1' then
if diff_max_fft_re <= c_diff_max then report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
- if diff_max_fft_im <= c_diff_max then report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
- else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
- end if;
- end process;
- end generate;
-
- gen_diff_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
- nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt < c_fft_size / 2 - 1 else
+ else report "FFT real output for re " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ if diff_max_fft_im <= c_diff_max then report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is OK" severity NOTE;
+ else report "FFT imag output for im " & g_name_x & " and im " & g_name_y & " is wrong" severity ERROR; end if;
+ end if;
+ end process;
+ end generate;
+
+ gen_diff_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
+ nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt < c_fft_size / 2 - 1 else
0 when out_val_dly = '1' and toggle_dly = '1' and diff_cnt = c_fft_size / 2 - 1 else
- diff_cnt;
- nxt_diff_rdy <= '1' when diff_cnt = c_fft_size / 2 - 1 else '0';
-
- diff_x_re <= 0 when out_val_dly = '0' else ref_real2_dat_x_re(diff_cnt) - out_x_re when toggle_dly = '0' else diff_x_re;
- diff_x_im <= 0 when out_val_dly = '0' else ref_real2_dat_x_im(diff_cnt) - out_x_im when toggle_dly = '0' else diff_x_im;
- diff_y_re <= 0 when out_val_dly = '0' else ref_real2_dat_y_re(diff_cnt) - out_y_re when toggle_dly = '1' else diff_y_re;
- diff_y_im <= 0 when out_val_dly = '0' else ref_real2_dat_y_im(diff_cnt) - out_y_im when toggle_dly = '1' else diff_y_im;
-
- diff_max_x_re <= largest(abs(diff_x_re), diff_max_x_re);
- diff_max_x_im <= largest(abs(diff_x_im), diff_max_x_im);
- diff_max_y_re <= largest(abs(diff_y_re), diff_max_y_re);
- diff_max_y_im <= largest(abs(diff_y_im), diff_max_y_im);
-
- assert diff_max_x_re <= c_diff_max report "FFT X re output differs too much from reference data" severity ERROR;
- assert diff_max_x_im <= c_diff_max report "FFT X im output differs too much from reference data" severity ERROR;
- assert diff_max_y_re <= c_diff_max report "FFT Y re output differs too much from reference data" severity ERROR;
- assert diff_max_y_im <= c_diff_max report "FFT Y im output differs too much from reference data" severity ERROR;
-
- p_report : process(diff_rdy)
- begin
- if diff_rdy = '1' then
- if diff_max_x_re <= c_diff_max then report "FFT X real output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
- if diff_max_x_im <= c_diff_max then report "FFT X imag output for " & g_name_x & " is OK" severity NOTE;
- else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
- if diff_max_y_re <= c_diff_max then report "FFT Y real output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
- if diff_max_y_im <= c_diff_max then report "FFT Y imag output for " & g_name_y & " is OK" severity NOTE;
- else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
- end if;
- end process;
- end generate;
-
- diff_val <= out_val_dly;
-
- -----------------------------------------------------------------------------
- -- PFT
- -----------------------------------------------------------------------------
-
- u_pft : entity work.pft
- generic map (
- g_fft_size_w => c_fft_size_w,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w,
- g_stage_dat_w => g_stage_dat_w,
- g_mode => g_pft_mode
- )
- port map (
- in_re => in_dat_x,
- in_im => in_dat_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => g_switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
-
- p_pft_reg : process(clk)
- begin
- if rising_edge(clk) then
- toggle <= nxt_toggle;
- toggle_dly <= toggle;
- out_re_dly <= out_re;
- out_im_dly <= out_im;
- out_val_dly <= out_val;
- out_fft_re <= nxt_out_fft_re;
- out_fft_im <= nxt_out_fft_im;
- out_x_re <= nxt_out_x_re;
- out_y_re <= nxt_out_y_re;
- out_x_im <= nxt_out_x_im;
- out_y_im <= nxt_out_y_im;
- end if;
- end process;
-
- nxt_toggle <= '0' when out_val = '0' else not toggle;
-
- gen_out_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
- nxt_out_fft_re <= 0 when out_val = '0' else to_integer(signed(out_re));
- nxt_out_fft_im <= 0 when out_val = '0' else to_integer(signed(out_im));
- end generate;
-
- gen_out_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
- nxt_out_x_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '0' else out_x_re;
- nxt_out_y_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '1' else out_y_re;
- nxt_out_x_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '0' else out_x_im;
- nxt_out_y_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '1' else out_y_im;
- end generate;
-
-end tb;
+ diff_cnt;
+ nxt_diff_rdy <= '1' when diff_cnt = c_fft_size / 2 - 1 else '0';
+
+ diff_x_re <= 0 when out_val_dly = '0' else ref_real2_dat_x_re(diff_cnt) - out_x_re when toggle_dly = '0' else diff_x_re;
+ diff_x_im <= 0 when out_val_dly = '0' else ref_real2_dat_x_im(diff_cnt) - out_x_im when toggle_dly = '0' else diff_x_im;
+ diff_y_re <= 0 when out_val_dly = '0' else ref_real2_dat_y_re(diff_cnt) - out_y_re when toggle_dly = '1' else diff_y_re;
+ diff_y_im <= 0 when out_val_dly = '0' else ref_real2_dat_y_im(diff_cnt) - out_y_im when toggle_dly = '1' else diff_y_im;
+
+ diff_max_x_re <= largest(abs(diff_x_re), diff_max_x_re);
+ diff_max_x_im <= largest(abs(diff_x_im), diff_max_x_im);
+ diff_max_y_re <= largest(abs(diff_y_re), diff_max_y_re);
+ diff_max_y_im <= largest(abs(diff_y_im), diff_max_y_im);
+
+ assert diff_max_x_re <= c_diff_max report "FFT X re output differs too much from reference data" severity ERROR;
+ assert diff_max_x_im <= c_diff_max report "FFT X im output differs too much from reference data" severity ERROR;
+ assert diff_max_y_re <= c_diff_max report "FFT Y re output differs too much from reference data" severity ERROR;
+ assert diff_max_y_im <= c_diff_max report "FFT Y im output differs too much from reference data" severity ERROR;
+
+ p_report : process(diff_rdy)
+ begin
+ if diff_rdy = '1' then
+ if diff_max_x_re <= c_diff_max then report "FFT X real output for " & g_name_x & " is OK" severity NOTE;
+ else report "FFT X real output for " & g_name_x & " is wrong" severity ERROR; end if;
+ if diff_max_x_im <= c_diff_max then report "FFT X imag output for " & g_name_x & " is OK" severity NOTE;
+ else report "FFT X imag output for " & g_name_x & " is wrong" severity ERROR; end if;
+ if diff_max_y_re <= c_diff_max then report "FFT Y real output for " & g_name_y & " is OK" severity NOTE;
+ else report "FFT Y real output for " & g_name_y & " is wrong" severity ERROR; end if;
+ if diff_max_y_im <= c_diff_max then report "FFT Y imag output for " & g_name_y & " is OK" severity NOTE;
+ else report "FFT Y imag output for " & g_name_y & " is wrong" severity ERROR; end if;
+ end if;
+ end process;
+ end generate;
+
+ diff_val <= out_val_dly;
+
+ -----------------------------------------------------------------------------
+ -- PFT
+ -----------------------------------------------------------------------------
+
+ u_pft : entity work.pft
+ generic map (
+ g_fft_size_w => c_fft_size_w,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w,
+ g_stage_dat_w => g_stage_dat_w,
+ g_mode => g_pft_mode
+ )
+ port map (
+ in_re => in_dat_x,
+ in_im => in_dat_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => g_switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
+
+ p_pft_reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ toggle <= nxt_toggle;
+ toggle_dly <= toggle;
+ out_re_dly <= out_re;
+ out_im_dly <= out_im;
+ out_val_dly <= out_val;
+ out_fft_re <= nxt_out_fft_re;
+ out_fft_im <= nxt_out_fft_im;
+ out_x_re <= nxt_out_x_re;
+ out_y_re <= nxt_out_y_re;
+ out_x_im <= nxt_out_x_im;
+ out_y_im <= nxt_out_y_im;
+ end if;
+ end process;
+
+ nxt_toggle <= '0' when out_val = '0' else not toggle;
+
+ gen_out_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
+ nxt_out_fft_re <= 0 when out_val = '0' else to_integer(signed(out_re));
+ nxt_out_fft_im <= 0 when out_val = '0' else to_integer(signed(out_im));
+ end generate;
+
+ gen_out_real2 : if g_pft_mode = PFT_MODE_REAL2 generate
+ nxt_out_x_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '0' else out_x_re;
+ nxt_out_y_re <= 0 when out_val = '0' else to_integer(signed(out_re)) when toggle = '1' else out_y_re;
+ nxt_out_x_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '0' else out_x_im;
+ nxt_out_y_im <= 0 when out_val = '0' else to_integer(signed(out_im)) when toggle = '1' else out_y_im;
+ end generate;
+
+ end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index cdc09c717a053e14a256d95aaf0a35ef34f2159d..2b5d68a7d4ee3ebc779f454d2b89d36184c3c5df 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -1,10 +1,10 @@
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library pft2_lib,common_lib;
-use pft2_lib.pft_pkg.all;
-use common_lib.common_pkg.all;
+ use pft2_lib.pft_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_pft is
end tb_pft;
@@ -44,39 +44,39 @@ begin
cnt <= (others => '0');
elsif rising_edge(clk) then
cnt <= nxt_cnt;
- end if;
+ end if;
end process;
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1) when in_sync = '0' else (others => '0');
pft : entity work.pft
- generic map (
- g_fft_size_w => g_fft_size_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_mode => PFT_MODE_REAL2
- )
- port map (
- in_re => in_x,
- in_im => in_y,
- in_val => in_val,
- in_sync => in_sync,
- switch_en => switch_en,
- out_re => out_re,
- out_im => out_im,
- out_val => out_val,
- out_sync => out_sync,
- clk => clk,
- rst => rst
- );
+ generic map (
+ g_fft_size_w => g_fft_size_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_mode => PFT_MODE_REAL2
+ )
+ port map (
+ in_re => in_x,
+ in_im => in_y,
+ in_val => in_val,
+ in_sync => in_sync,
+ switch_en => switch_en,
+ out_re => out_re,
+ out_im => out_im,
+ out_val => out_val,
+ out_sync => out_sync,
+ clk => clk,
+ rst => rst
+ );
clk <= not(clk) after clk_period / 2;
rst <= '0' after rst_period;
switch_en <= '0';
--- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
--- in_val <= '1' WHEN UNSIGNED(cnt)=732;
+ -- in_sync <= '1' WHEN UNSIGNED(cnt)=g_pps_ps-1 ELSE '0';
+ -- in_val <= '1' WHEN UNSIGNED(cnt)=732;
input_ctrl : process
begin
@@ -91,7 +91,7 @@ begin
-- val
wait until unsigned(cnt) = 1024;
--- WAIT UNTIL UNSIGNED(cnt)=731;
+ -- WAIT UNTIL UNSIGNED(cnt)=731;
in_val <= '1';
for J in 1 to 10 loop
@@ -109,28 +109,28 @@ begin
wait;
end process;
--- -----------------------------------------------------------------------------
--- --
--- -- X = Y is sliding impulse
--- --
--- -----------------------------------------------------------------------------
--- in_gen: PROCESS
--- BEGIN
--- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
--- FOR J IN 1 TO 1 LOOP -- Repeat impulse
--- IF in_val='1' THEN
--- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
--- WAIT FOR clk_period;
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- WAIT FOR clk_period;
--- ELSE
--- WAIT UNTIL in_val='1';
--- END IF;
--- END LOOP;
--- END LOOP;
--- END PROCESS;
--- in_y <= in_x;
+ -- -----------------------------------------------------------------------------
+ -- --
+ -- -- X = Y is sliding impulse
+ -- --
+ -- -----------------------------------------------------------------------------
+ -- in_gen: PROCESS
+ -- BEGIN
+ -- FOR I IN 0 TO g_fft_size-1 LOOP -- Slide impulse
+ -- FOR J IN 1 TO 1 LOOP -- Repeat impulse
+ -- IF in_val='1' THEN
+ -- WAIT UNTIL UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=I;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- WAIT FOR clk_period;
+ -- ELSE
+ -- WAIT UNTIL in_val='1';
+ -- END IF;
+ -- END LOOP;
+ -- END LOOP;
+ -- END PROCESS;
+ -- in_y <= in_x;
-----------------------------------------------------------------------------
--
@@ -145,40 +145,40 @@ begin
elsif rising_edge(clk) then
if cnt(0) = '1' then
if in_val = '1' then
- in_x <= std_logic_vector(-signed(in_x));
- in_y <= std_logic_vector(signed(in_y));
+ in_x <= std_logic_vector(-signed(in_x));
+ in_y <= std_logic_vector(signed(in_y));
end if;
end if;
end if;
end process;
--- -----------------------------------------------------------------------------
--- --
--- -- X, Y is impulse 0, impulse 1 or DC
--- --
--- -----------------------------------------------------------------------------
--- --dc <= 0;
--- dc <= 300;
--- in_gen: PROCESS (clk,rst)
--- BEGIN
--- IF rst='1' THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
--- ELSIF rising_edge(clk) THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
--- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=0 THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
--- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
--- END IF;
--- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=1 THEN
--- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
--- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
--- -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
--- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
--- END IF;
--- END IF;
--- END PROCESS;
+ -- -----------------------------------------------------------------------------
+ -- --
+ -- -- X, Y is impulse 0, impulse 1 or DC
+ -- --
+ -- -----------------------------------------------------------------------------
+ -- --dc <= 0;
+ -- dc <= 300;
+ -- in_gen: PROCESS (clk,rst)
+ -- BEGIN
+ -- IF rst='1' THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
+ -- ELSIF rising_edge(clk) THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w));
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w));
+ -- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=0 THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
+ -- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 0
+ -- END IF;
+ -- IF UNSIGNED(nxt_cnt(g_fft_size_w-1 DOWNTO 0))=1 THEN
+ -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(0,g_in_dat_w)); -- DC 0
+ -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(dc,g_in_dat_w)); -- DC
+ -- -- in_x <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
+ -- -- in_y <= STD_LOGIC_VECTOR(TO_SIGNED(131000,g_in_dat_w)); -- impulse 1
+ -- END IF;
+ -- END IF;
+ -- END PROCESS;
end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
index 48440aff8717881673e5e82c0fa2e71ab61d25f7..a5f9fa6e8657324a563166aa749a4ff388826ed1 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
@@ -25,12 +25,12 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_pft2 is
end tb_tb_pft2;
-use work.pft_pkg.all;
+ use work.pft_pkg.all;
architecture tb of tb_tb_pft2 is
constant c_sw : std_logic := '1'; -- default for g_switch_en
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 36aaca529eb85f3b060a0b8c60f04698c276d2ec..cf86f9d8782bdaa14e879290639ac05fd9f88f0f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_6ch_200MHz is
generic (
@@ -75,7 +75,7 @@ entity lofar2_unb2b_adc_6ch_200MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -107,52 +107,52 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
index d1e33a7ff0d788701309206613f646f48f8a0601..763ac32b9abb568562edfae19ad82e0f23865b55 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -28,11 +28,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_6ch_200MHz is
end tb_lofar2_unb2b_adc_6ch_200MHz;
@@ -105,48 +105,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_6ch_200MHz : entity work.lofar2_unb2b_adc_6ch_200MHz
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 7e46728d34127e2043e52764741dcad8b2cd8b47..eb9d8683543251a6279764dc848dc2fbe318fec7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_adc_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index 02076e8cc845c1469e638ecf7d10c6e04674db58..ece17b0efcae605848f68adab9ca6b0cab5b4d0f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_full is
end tb_lofar2_unb2b_adc_full;
@@ -106,48 +106,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_full : entity work.lofar2_unb2b_adc_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 88acdb6b718de2b491b79f1c68a0de9a898b422f..2b3bb307cd7a7e9c2ec5089bbd8a6e0fc47e798c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 1 ADC stream
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_adc_one_node is
generic (
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index 768efa68b74c1bd9b3245e1b9ec0d5ee58f94def..9fec5faffcb6f65c9555de81a26f3b32f3b761ac 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -29,11 +29,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc_one_node is
end tb_lofar2_unb2b_adc_one_node;
@@ -106,48 +106,48 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_one_node : entity work.lofar2_unb2b_adc_one_node
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- BCK_RX => bck_rx,
- BCK_REF_CLK => bck_ref_clk,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index f23f05116a5a424ccf0273da9f2827046a750d00..e2de8fc79a6015f18d3384a061e8e6c13078e49f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -26,15 +26,15 @@
-- Use revisions to select one_node or full versions
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
entity lofar2_unb2b_adc is
generic (
@@ -81,9 +81,9 @@ entity lofar2_unb2b_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -228,209 +228,209 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => open,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => open,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_adc
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -438,75 +438,75 @@ begin
-----------------------------------------------------------------------------
u_ait: entity work.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_nof_streams,
- g_jesd_freq => g_jesd_freq,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => alt_sosi_arr
- );
-
- u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_jesd_freq => g_jesd_freq,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => alt_sosi_arr
+ );
+
+ u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index 27c3add61508aed51f55a6e905fd5bd8f45c96ba..4d2814567f4916800f1bd6ef2aa02e63fde3a4ca 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package lofar2_unb2b_adc_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -41,7 +41,6 @@ package lofar2_unb2b_adc_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_adc_config;
-
end lofar2_unb2b_adc_pkg;
package body lofar2_unb2b_adc_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index daffa485ac9a95f2265164cc80f90ed0bb1062c9..e2f2d45386ac8899b95be41ade25f4ccdce1af24 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_adc_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_adc_pkg.all;
entity mmm_lofar2_unb2b_adc is
generic (
@@ -152,63 +152,87 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -285,9 +309,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -303,9 +327,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 869b3d932d615a4da5f73c9a8440766d3460d248..acfdabb9aa1768096d02f53b7125d97a6ab307db 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -27,16 +27,16 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2b_board_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.lofar2_unb2b_adc_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.lofar2_unb2b_adc_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity node_adc_input_and_timing is
generic (
@@ -119,53 +119,54 @@ end node_adc_input_and_timing;
architecture str of node_adc_input_and_timing is
constant c_nof_streams_jesd204b : natural := 12; -- IP is set up for 12 streams
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
-
- -- Waveform Generator
- constant c_wg_buf_directory : string := "data/";
- constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
- constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples;
- signal wg_out_ovr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal wg_out_val : std_logic_vector(g_nof_streams - 1 downto 0);
- signal wg_out_data : std_logic_vector(g_nof_streams * c_wg_buf_dat_w - 1 downto 0);
- signal wg_out_sync : std_logic_vector(g_nof_streams - 1 downto 0);
- signal trigger_wg : std_logic;
-
- -- Frame parameters TBC
- constant c_bs_bsn_w : natural := 64; -- 51;
- constant c_bs_block_size : natural := 1024;
- constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
- constant c_dp_shiftram_nof_samples: natural := 4096;
- constant c_data_w : natural := 16;
- constant c_dp_fifo_dc_size : natural := 64;
-
- -- QSFP leds
- signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
- signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
-
- -- JESD signals
- signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
- signal rx_rst : std_logic;
- signal rx_sysref : std_logic;
-
- -- Sosis and sosi arrays
- signal rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
- signal dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
- signal ant_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
- signal bs_sosi : t_dp_sosi;
- signal wg_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
- signal mm_rst_internal : std_logic;
- signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
- signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal jesd204b_reset : std_logic;
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
+
+ -- Waveform Generator
+ constant c_wg_buf_directory : string := "data/";
+ constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
+ constant c_wg_buf_addr_w : natural := 10; -- default value of WG for 1024 samples;
+ signal wg_out_ovr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal wg_out_val : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal wg_out_data : std_logic_vector(g_nof_streams * c_wg_buf_dat_w - 1 downto 0);
+ signal wg_out_sync : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal trigger_wg : std_logic;
+
+ -- Frame parameters TBC
+ constant c_bs_bsn_w : natural := 64; -- 51;
+ constant c_bs_block_size : natural := 1024;
+ constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
+ constant c_dp_shiftram_nof_samples: natural := 4096;
+ constant c_data_w : natural := 16;
+ constant c_dp_fifo_dc_size : natural := 64;
+
+ -- QSFP leds
+ signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
+ signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
+
+ -- JESD signals
+ signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
+ signal rx_rst : std_logic;
+ signal rx_sysref : std_logic;
+
+ -- Sosis and sosi arrays
+ signal rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
+ signal dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
+ signal ant_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
+ signal bs_sosi : t_dp_sosi;
+ signal wg_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+
+ signal mm_rst_internal : std_logic;
+ signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
+ signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal jesd204b_reset : std_logic;
begin
-- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
@@ -186,35 +187,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
@@ -224,6 +225,7 @@ begin
-----------------------------------------------------------------------------
gen_force_valid : for I in 0 to c_nof_streams_jesd204b - 1 generate
+
p_sosi : process(rx_sosi_arr)
begin
dp_shiftram_snk_in_arr(I) <= rx_sosi_arr(I);
@@ -232,120 +234,121 @@ begin
end generate;
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_words => c_dp_shiftram_nof_samples,
- g_data_w => c_data_w,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_nof_words => c_dp_shiftram_nof_samples,
+ g_data_w => c_data_w,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
gen_mux : for I in 0 to g_nof_streams - 1 generate
+
p_sosi : process(ant_sosi_arr(I), wg_sosi_arr(I))
begin
-- Default use the ADC data
@@ -364,6 +367,7 @@ begin
-----------------------------------------------------------------------------
gen_concat : for I in 0 to g_nof_streams - 1 generate
+
p_sosi : process(mux_sosi_arr(I), bs_sosi)
begin
st_sosi_arr(I) <= bs_sosi;
@@ -382,80 +386,80 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => g_nof_streams,
- g_symbol_w => c_data_w, -- TBD 16?
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
- g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
- g_buffer_use_sync => true -- True to capture all streams synchronously
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
- buf_miso => ram_aduh_monitor_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => g_nof_streams,
+ g_symbol_w => c_data_w, -- TBD 16?
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
+ g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
+ g_buffer_use_sync => true -- True to capture all streams synchronously
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+ buf_miso => ram_aduh_monitor_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- Output Stage
@@ -486,23 +490,23 @@ begin
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index cd479c2bdbe001e2bd25df14c936a10be5cffdda..9207738288e572a7b87a50aabffb220b0a423218 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_adc_pkg is
-----------------------------------------------------------------------------
@@ -28,213 +28,212 @@ package qsys_lofar2_unb2b_adc_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_adc is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_adc;
-
+ component qsys_lofar2_unb2b_adc is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_adc;
end qsys_lofar2_unb2b_adc_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 627ac45ba488fb71a0073ea24bb1a910369afdf6..bab5ccf9c28fa01d3357fee25202595536b007a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -31,11 +31,11 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_lofar2_unb2b_adc is
end tb_lofar2_unb2b_adc;
@@ -108,50 +108,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 16294442b7b7a21a596125399d2de3cd0c9483c8..93d51a2dd643a52046a557f3fce191e1aa73e3b9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -31,12 +31,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.all;
entity tb_lofar2_unb2b_adc_multichannel is
end tb_lofar2_unb2b_adc_multichannel;
@@ -59,30 +59,32 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
-- Transport delays
type t_time_arr is array (0 to 11) of time;
constant c_nof_jesd204b_tx : natural := 3; -- number of jesd204b input sources to instantiate
- constant c_delay_data_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps,
- 5000 ps); -- transport delays tx to rx data
- constant c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
- 5000 ps,
- 6000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps,
- 1000 ps); -- transport delays clock source to adc(tx)
+ constant c_delay_data_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps,
+ 5000 ps); -- transport delays tx to rx data
+ constant c_delay_sysreftoadc_arr : t_time_arr := (
+ 4000 ps,
+ 5000 ps,
+ 6000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps); -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
-- clocks and resets for the jesd204b tx
@@ -181,50 +183,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => bck_rx,
- JESD204B_REFCLK => jesd204b_sampclk_fpga,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref_fpga,
- JESD204B_SYNC_N => jesd204b_sync_n_fpga
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => bck_rx,
+ JESD204B_REFCLK => jesd204b_sampclk_fpga,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref_fpga,
+ JESD204B_SYNC_N => jesd204b_sync_n_fpga
+ );
-----------------------------------------------------------------------------
-- Transport
@@ -233,7 +235,7 @@ begin
gen_transport : for i in 0 to c_nof_jesd204b_tx - 1 generate
jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
--- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+ -- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
end generate;
@@ -247,56 +249,56 @@ begin
gen_jesd204b_tx : for i in 0 to c_nof_jesd204b_tx - 1 generate
u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- port map
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, -- out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
- jesd204_tx_avs_chipselect => avs_chipselect(i), -- jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_n_adc(i), -- in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
+ port map
+ (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, -- out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), -- out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), -- jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
+ mdev_sync_n => dev_sync_n(i), -- in
+ pll_locked => pll_locked, -- in
+ sync_n => jesd204b_sync_n_adc(i), -- in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
-- Generate test pattern at each ADC
@@ -305,41 +307,41 @@ begin
variable even_sample : boolean := true;
begin
if mm_rst = '1' then
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- data := 0;
- even_sample := true;
- else
- if rising_edge(jesd204b_sampclk_adc(i)) then
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
- if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
- data := 1000;
- elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
- data := -1000;
- else
- data := 0;
- end if;
-
- -- Frame the data to 32 bits at half the rate
- if(jesd204b_tx_link_ready(i) = '0') then
- even_sample := true;
- else
- even_sample := not even_sample;
- end if;
- if (even_sample = true) then
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- else
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- end if;
- end if;
- end if;
- end process;
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ data := 0;
+ even_sample := true;
+ else
+ if rising_edge(jesd204b_sampclk_adc(i)) then
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+ if (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') then
+ data := 1000;
+ elsif (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') then
+ data := -1000;
+ else
+ data := 0;
+ end if;
+
+ -- Frame the data to 32 bits at half the rate
+ if(jesd204b_tx_link_ready(i) = '0') then
+ even_sample := true;
+ else
+ even_sample := not even_sample;
+ end if;
+ if (even_sample = true) then
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ else
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
end generate;
-----------------------------------------------------------------------------
@@ -385,23 +387,23 @@ begin
variable count : natural := 0;
begin
if mm_rst = '1' then
- jesd204b_sysref <= '0';
- count := 0;
- else
- if rising_edge(jesd204b_sampclk) then
+ jesd204b_sysref <= '0';
+ count := 0;
+ else
+ if rising_edge(jesd204b_sampclk) then
if (count = c_sysref_period - 1) then
- count := 0;
- else
- count := count + 1;
- end if;
-
- if count > c_sysref_period - 8 then
- jesd204b_sysref <= '1';
- else
- jesd204b_sysref <= '0';
- end if;
- end if;
- end if;
+ count := 0;
+ else
+ count := count + 1;
+ end if;
+
+ if count > c_sysref_period - 8 then
+ jesd204b_sysref <= '1';
+ else
+ jesd204b_sysref <= '0';
+ end if;
+ end if;
+ end if;
end process;
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index 470c7ab17576fd1237034c445cf190d39a3004df..603d3e58729415158f4169271812ec8c552093b7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -47,16 +47,16 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_lofar2_unb2b_adc_wg is
end tb_lofar2_unb2b_adc_wg;
@@ -77,8 +77,8 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_tb_clk_period : time := 100 ps; -- use fast tb_clk to speed up M&C
constant c_cable_delay : time := 12 ns;
- constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10**6; -- 200 MSps
- constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps;
+ constant c_sample_freq : natural := c_unb2b_board_ext_clk_freq_200M / 10 ** 6; -- 200 MSps
+ constant c_sample_period : time := (10 ** 6 / c_sample_freq) * 1 ps;
constant c_nof_sync : natural := 5;
constant c_nof_block_per_sync : natural := 16;
@@ -93,13 +93,13 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_subband_period : time := c_nof_points * c_sample_period;
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2 ** (18 - 1) - 1); -- = full scale of WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp : natural := 2**(14 - 1) / 2; -- in number of lsb
+ constant c_ampl_sp : natural := 2 ** (14 - 1) / 2; -- in number of lsb
constant c_subband_sp : real := 51.2; -- Select subband at index 512/10 = 51.2 = 20 MHz
constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / 512.0; -- subband freq = Fs/512 = 200 MSps/512 = 390625 Hz sinus
constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- constant c_exp_wg_power_sp : real := real(c_ampl_sp**2) / 2.0 * real(c_nof_points * c_nof_block_per_sync);
+ constant c_exp_wg_power_sp : real := real(c_ampl_sp ** 2) / 2.0 * real(c_nof_points * c_nof_block_per_sync);
-- ADUH
constant c_mon_buffer_nof_samples : natural := 1024; -- samples per stream
@@ -179,50 +179,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : entity work.lofar2_unb2b_adc
- generic map (
- g_design_name => "lofar2_unb2b_adc_one_node",
- g_design_note => "Lofar2 adc with one node",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -254,7 +254,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp * c_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp) * c_wg_ampl_lsb), tb_clk); -- ampl
@@ -280,8 +280,8 @@ begin
----------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_subband_period, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_subband_period, tb_clk);
wait for c_subband_period; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
@@ -304,8 +304,8 @@ begin
---------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
- c_subband_period, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_subband_period, tb_clk);
-- Read ADUH monitor power sum
mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
@@ -318,7 +318,7 @@ begin
-- Verification
---------------------------------------------------------------------------
-- Convert UNSIGNED sp_power_sum to REAL
- v_sp_power_sum := real(real(to_integer(sp_power_sum(61 downto 30))) * real(2**30) + real(to_integer(sp_power_sum(29 downto 0))));
+ v_sp_power_sum := real(real(to_integer(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(to_integer(sp_power_sum(29 downto 0))));
assert v_sp_power_sum > c_lo_factor * c_exp_wg_power_sp report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum < c_hi_factor * c_exp_wg_power_sp report "Wrong SP power for SP 0" severity ERROR;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index 90b3f265619797cda4aaf7e0ba26920a0409748c..57bd95a2fbf084c48217bfa1f0320bc54cdb92ad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_beamformer_one_node is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index ebaa797084ef9a4b6a073ae64fc2e71cae0a060d..91a2b0b758ce560916ff0951101522442dfde086 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF with a DP_clk of 256MHz
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_beamformer_one_node_256MHz is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 0d815568ee1674d47062268d8106f9c41ab9358d..7e4758d032beccf23809ebaf3d3d28723e3e6d3c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_beamformer_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_beamformer_pkg.all;
entity lofar2_unb2b_beamformer is
generic (
@@ -91,9 +91,9 @@ entity lofar2_unb2b_beamformer is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -111,7 +111,7 @@ architecture str of lofar2_unb2b_beamformer is
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10 ** 6; -- alternate 160MHz. TODO: Use to check PPS
-- 10 GbE Interface
constant c_nof_streams_qsfp : natural := 4;
@@ -391,267 +391,267 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_beamformer
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+ reg_bf_scale_mosi => reg_bf_scale_mosi,
+ reg_bf_scale_miso => reg_bf_scale_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso,
+ ram_st_bst_mosi => ram_st_bst_mosi,
+ ram_st_bst_miso => ram_st_bst_miso,
+ reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
+ reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
+ reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
-----------------------------------------------------------------------------
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- nof beamsets node_sdp_beamformers (BF)
@@ -672,211 +672,211 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd_ctrl_mosi => c_mem_mosi_rst,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd_ctrl_mosi => c_mem_mosi_rst,
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
-
- -- Beamformers
- gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
- u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
generic map(
g_sim => g_sim,
- g_beamset_id => beamset_id,
- g_scope_selected_beamlet => g_scope_selected_subband
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
)
port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_sosi_arr,
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => OPEN,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => cep_eth_src_mac,
- ip_src_addr => cep_ip_src_addr,
- udp_src_port => cep_udp_src_port,
-
- hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
+
+ -- Beamformers
+ gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
+ u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
+ generic map(
+ g_sim => g_sim,
+ g_beamset_id => beamset_id,
+ g_scope_selected_beamlet => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_sosi_arr,
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => OPEN,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => cep_eth_src_mac,
+ ip_src_addr => cep_ip_src_addr,
+ udp_src_port => cep_udp_src_port,
+
+ hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_mosi,
+ miso => ram_ss_ss_wide_miso,
+ mosi_arr => ram_ss_ss_wide_mosi_arr,
+ miso_arr => ram_ss_ss_wide_miso_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_mosi,
+ miso => ram_bf_weights_miso,
+ mosi_arr => ram_bf_weights_mosi_arr,
+ miso_arr => ram_bf_weights_miso_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_mosi,
+ miso => reg_bf_scale_miso,
+ mosi_arr => reg_bf_scale_mosi_arr,
+ miso_arr => reg_bf_scale_miso_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_mosi,
+ miso => reg_dp_xonoff_miso,
+ mosi_arr => reg_dp_xonoff_mosi_arr,
+ miso_arr => reg_dp_xonoff_miso_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_mosi,
+ miso => ram_st_bst_miso,
+ mosi_arr => ram_st_bst_mosi_arr,
+ miso_arr => ram_st_bst_miso_arr
+ );
-----------------------------------------------------------------------------
-- DP MUX
@@ -887,34 +887,34 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
-
- src_out => nw_10gbe_snk_in_arr(0),
- src_in => nw_10gbe_snk_out_arr(0)
- );
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
+
+ src_out => nw_10gbe_snk_in_arr(0),
+ src_in => nw_10gbe_snk_out_arr(0)
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
- -- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_1_RX;
- QSFP_1_TX <= i_QSFP_TX(0);
- ------------
- -- Front IO
- ------------
- u_front_io : entity unb2b_board_lib.unb2b_board_front_io
+ -- put the QSFP_TX/RX ports into arrays
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
+ ------------
+ -- Front IO
+ ------------
+ u_front_io : entity unb2b_board_lib.unb2b_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
)
@@ -931,10 +931,10 @@ begin
QSFP_LED => QSFP_LED
);
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
)
port map (
@@ -946,10 +946,10 @@ begin
rst_312 => open
);
- ---------------
- -- nw_10GbE
- ---------------
- u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
+ ---------------
+ -- nw_10GbE
+ ---------------
+ u_nw_10GbE: entity nw_10GbE_lib.nw_10GbE
generic map (
g_sim => g_sim,
g_sim_level => 1,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
index 5fc60b88b1e6f6c4e1072a7becc7aedb2b2dbd71..a54afc6dc79fa9713481bd1d7da937f50e5dc0d6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_beamformer_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,6 @@ package lofar2_unb2b_beamformer_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_beamformer_config;
-
end lofar2_unb2b_beamformer_pkg;
package body lofar2_unb2b_beamformer_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
index 27f912bd203d366a6d1cafe3ffe0fad8ae38d046..f676dd96ac17c89dc1be9ce1e787af64be429c2b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_beamformer_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_beamformer_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_beamformer is
generic (
@@ -154,49 +154,49 @@ entity mmm_lofar2_unb2b_beamformer is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
- -- SDP Info
- reg_sdp_info_mosi : out t_mem_mosi;
- reg_sdp_info_miso : in t_mem_miso;
+ -- SDP Info
+ reg_sdp_info_mosi : out t_mem_mosi;
+ reg_sdp_info_miso : in t_mem_miso;
- -- Beamlet Subband Select
- ram_ss_ss_wide_mosi : out t_mem_mosi;
- ram_ss_ss_wide_miso : in t_mem_miso;
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_mosi : out t_mem_mosi;
+ ram_ss_ss_wide_miso : in t_mem_miso;
- -- Local BF bf weights
- ram_bf_weights_mosi : out t_mem_mosi;
- ram_bf_weights_miso : in t_mem_miso;
+ -- Local BF bf weights
+ ram_bf_weights_mosi : out t_mem_mosi;
+ ram_bf_weights_miso : in t_mem_miso;
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : out t_mem_mosi;
- reg_bf_scale_miso : in t_mem_miso;
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_mosi : out t_mem_mosi;
+ reg_bf_scale_miso : in t_mem_miso;
- -- Beamlet Data Output header fields
- reg_hdr_dat_mosi : out t_mem_mosi;
- reg_hdr_dat_miso : in t_mem_miso;
+ -- Beamlet Data Output header fields
+ reg_hdr_dat_mosi : out t_mem_mosi;
+ reg_hdr_dat_miso : in t_mem_miso;
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : out t_mem_mosi;
- reg_dp_xonoff_miso : in t_mem_miso;
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_mosi : out t_mem_mosi;
+ reg_dp_xonoff_miso : in t_mem_miso;
- -- Beamlet Statistics (BST)
- ram_st_bst_mosi : out t_mem_mosi;
- ram_st_bst_miso : in t_mem_miso;
+ -- Beamlet Statistics (BST)
+ ram_st_bst_mosi : out t_mem_mosi;
+ ram_st_bst_miso : in t_mem_miso;
- -- 10 GbE mac
- reg_nw_10GbE_mac_mosi : out t_mem_mosi;
- reg_nw_10GbE_mac_miso : in t_mem_miso;
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_mosi : out t_mem_mosi;
+ reg_nw_10GbE_mac_miso : in t_mem_miso;
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : in t_mem_miso;
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_mosi : out t_mem_mosi;
+ reg_nw_10GbE_eth10g_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -214,113 +214,155 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -396,9 +438,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -414,9 +456,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index 1df2a17b4164dfe45e634bc1c67f6ca4b3a2b35b..8eec569e2b90e54aeae8967b46a3c01b7dfdcbb2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -19,331 +19,330 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_beamformer_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_beamformer is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_beamformer;
-
+ component qsys_lofar2_unb2b_beamformer is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_beamformer;
end qsys_lofar2_unb2b_beamformer_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index aef82a89ff36116894d3267561d23df702a525e7..d49e4bc1d1207837b6e679b890c393bf55b8aff8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -49,20 +49,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_beamformer is
end tb_lofar2_unb2b_beamformer;
@@ -92,14 +92,14 @@ architecture tb of tb_lofar2_unb2b_beamformer is
constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
-- WG
- constant c_full_scale_ampl : real := real(2**(14 - 1) - 1); -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2 ** (14 - 1) - 1); -- = full scale of WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2 ** (c_sdp_W_adc - 1) / 2; -- in number of lsb
constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
constant c_wb_leakage_bin : natural := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
@@ -220,60 +220,60 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_beamformer : entity work.lofar2_unb2b_beamformer
- generic map (
- g_design_name => "lofar2_unb2b_beamformer_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "lofar2_unb2b_beamformer_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -283,7 +283,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
@@ -350,7 +350,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
@@ -369,8 +369,8 @@ begin
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read subband statistics
@@ -430,8 +430,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_beamlet_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_beamlet_power_sum(v_S) <= sp_beamlet_power_sum(v_S) + v_sp_beamlet_power;
end if;
@@ -441,8 +441,8 @@ begin
-- sp_beamlet_power_sum is the sum of all subband powers per SP, this value will be close to sp_beamlet_power
-- because the input is a sinus, so most power will be in 1 subband. The sp_beamlet_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
- sp_beamlet_power_0 <= real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ sp_beamlet_power_0 <= real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_beamlet_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_beamlet_power_sum_0 <= sp_beamlet_power_sum(0);
@@ -493,18 +493,18 @@ begin
if v_S = 0 then
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_beamlet_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_beamlet_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_beamlet_powers_arr2(v_S)(v_B)(29 downto 0)));
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- verify if subband power and beamlet power are the same. This is expected because we only use 1 WG input and the BF weights have unit value.
-- the difference should not be larger than 0.5% (+/- 2^13 for low values)
- assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0**13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
- assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0**13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
+ assert v_sp_beamlet_power > 0.995 * v_sp_subband_power - 2.0 ** 13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
+ assert v_sp_beamlet_power < 1.005 * v_sp_subband_power + 2.0 ** 13 report "index (" & integer'image(v_S) & "," & integer'image(v_B) & "): Subband power = " & real'image(v_sp_subband_power) & " and Beamlet power = " & real'image(v_sp_beamlet_power) & " are not equal" severity ERROR;
end if;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index bae7a2ad5adc1e17b9214db699ee4da18638515d..d63e44233ca118dc08bd3dd14be7857f3ba3c4a4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index e541eecf75e176cc2737f809a6499ac7cc2f8d40..59a6c2de72113a8a42a3cea4297394a1044f2b5e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_filterbank_full_256MHz is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 9a0af000e4e08da7987274fa4ee76a468ce5f354..5775b156c48aaefaa8d6540bea41f765b76b364e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -27,19 +27,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib, wpfb_lib, lofar2_sdp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_filterbank_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_filterbank_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_filterbank is
generic (
@@ -87,9 +87,9 @@ entity lofar2_unb2b_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -107,7 +107,7 @@ architecture str of lofar2_unb2b_filterbank is
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10 ** 6; -- alternate 160MHz. TODO: Use to check PPS
constant c_udp_offload_nof_streams : natural := c_eth_nof_udp_ports;
@@ -299,243 +299,243 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_dp_clk_freq,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_dp_clk_freq,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Statistics offload
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
- reg_stat_enable_mosi => reg_stat_enable_mosi,
- reg_stat_enable_miso => reg_stat_enable_miso,
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Statistics offload
+ reg_sdp_info_mosi => reg_sdp_info_mosi,
+ reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_stat_enable_mosi => reg_stat_enable_mosi,
+ reg_stat_enable_miso => reg_stat_enable_miso,
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_miso
+ );
-----------------------------------------------------------------------------
-- SDP Info register
@@ -548,25 +548,25 @@ begin
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -574,102 +574,102 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_unb2b_adc_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_V_si_db,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_V_si_db,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 7b732860482965946a9be4fd98a18552c43ea78b..38903b4bd4b6bafe53278ca8f0eeb28e8436ad8d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,6 @@ package lofar2_unb2b_filterbank_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_filterbank_config;
-
end lofar2_unb2b_filterbank_pkg;
package body lofar2_unb2b_filterbank_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index 736f555d99d7bab483adde375befeb779fe9e9e7..fc31d90fb8f88c1dc290dc734a28fac645771496 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_filterbank is
generic (
@@ -194,95 +194,131 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
- u_mm_file_reg_stat_enable : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
- port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+ u_mm_file_reg_stat_enable : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
+ port map(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
- u_mm_file_reg_stat_hdr_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
+ u_mm_file_reg_stat_hdr_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -375,9 +411,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index 21dc8f5640f021b9394624c55618ecaf3286de3a..5fb2432d0d051f704b6342d5168f2a8931005430 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -19,299 +19,298 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ component qsys_lofar2_unb2b_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_clk_export : out std_logic; -- export
- reg_stat_enable_read_export : out std_logic; -- export
- reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_reset_export : out std_logic; -- export
- reg_stat_enable_write_export : out std_logic; -- export
- reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_read_export : out std_logic; -- export
- reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_write_export : out std_logic; -- export
- reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_clk_export : out std_logic; -- export
+ reg_stat_enable_read_export : out std_logic; -- export
+ reg_stat_enable_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_reset_export : out std_logic; -- export
+ reg_stat_enable_write_export : out std_logic; -- export
+ reg_stat_enable_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
-
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2b_filterbank;
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2b_filterbank;
end qsys_lofar2_unb2b_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index a0ade62951545450169b348d329fc8db6ee5de08..721ba0264b5d1e4dce870d8b0280b56559f1c643 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -51,19 +51,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_filterbank is
end tb_lofar2_unb2b_filterbank;
@@ -92,14 +92,14 @@ architecture tb of tb_lofar2_unb2b_filterbank is
constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2 ** (18 - 1) - 1); -- = full scale of WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2 ** (c_sdp_W_adc - 1) / 2; -- in number of lsb
constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -199,52 +199,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_filterbank : entity work.lofar2_unb2b_filterbank
- generic map (
- g_design_name => "lofar2_unb2b_filterbank_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_filterbank_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -278,7 +278,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
@@ -304,8 +304,8 @@ begin
----------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
wait for c_sdp_T_sub; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
@@ -328,8 +328,8 @@ begin
---------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
-- Read ADUH monitor power sum
mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
@@ -343,7 +343,7 @@ begin
---------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
- v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
+ v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(TO_UINT(sp_power_sum(29 downto 0))));
assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
@@ -375,8 +375,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_subband_power_sum(v_S) <= sp_subband_power_sum(v_S) + v_sp_subband_power;
end if;
@@ -385,8 +385,8 @@ begin
-- sp_subband_power_sum is the sum of all subband powers per SP, this value will be close to sp_subband_power
-- because the input is a sinus, so most power will be in 1 subband. The sp_subband_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
- sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_subband_power_sum_0 <= sp_subband_power_sum(0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index afbced0491d2897686cfa308ee72ff868e9ab676..16c31d39d25a4b5b36181c102f0a19c256847d0b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete ring design with all 8 lanes.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_full is
generic (
@@ -93,56 +93,56 @@ end lofar2_unb2b_ring_full;
architecture str of lofar2_unb2b_ring_full is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
index 18ccf3dd9ee22e084b529e1a948256a2e6ecd29d..b1a0fbc0abbb5afd4797c3c5db795a9fb93ce092 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_full is
end tb_lofar2_unb2b_ring_full;
@@ -100,53 +100,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_full : entity work.lofar2_unb2b_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index 86bb45908a0af897cc16e31e7c6369e2846ec416..823c8e0b3072aa90499a88aca95e7dd42eb2c525 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -29,13 +29,13 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_ring_one is
generic (
@@ -96,56 +96,56 @@ end lofar2_unb2b_ring_one;
architecture str of lofar2_unb2b_ring_one is
begin
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
index eccc9a2de90ef4ffdfb240ba21b931328522b699..37dbd9552746b7bcda68a439229c37345eea3dc0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2b_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_one is
end tb_lofar2_unb2b_ring_one;
@@ -100,53 +100,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_one : entity work.lofar2_unb2b_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index dbf744910f3b14dca09265aa302b51d6732d67f0..926e94da3ebb452fe557de8de509a1e8b644a0c1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2b_ring is
generic (
@@ -110,7 +110,7 @@ architecture str of lofar2_unb2b_ring is
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2b_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -149,512 +149,513 @@ architecture str of lofar2_unb2b_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
-
- signal gn_index : natural;
- signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
-
- -- System
- signal cs_sim : std_logic;
- signal xo_ethclk : std_logic;
- signal xo_rst : std_logic;
- signal xo_rst_n : std_logic;
- signal mm_clk : std_logic;
- signal mm_rst : std_logic := '0';
-
- signal dp_pps : std_logic;
- signal dp_rst : std_logic;
- signal dp_clk : std_logic;
-
- -- PIOs
- signal pout_wdi : std_logic;
-
- -- WDI override
- signal reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- PPSH
- signal reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- UniBoard system info
- signal reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
- signal rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- UniBoard I2C sens
- signal reg_unb_sens_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_unb_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- pm bus
- signal reg_unb_pmbus_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_unb_pmbus_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- FPGA sensors
- signal reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- eth1g
- signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
- signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
- signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
- signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS read
- signal reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS write
- signal reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS status/control
- signal reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- Remote Update
- signal reg_remu_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- Scrap ram
- signal ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
- signal ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- ----------------------------------------------
- -- 10 GbE
- ----------------------------------------------
- signal reg_tr_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_tr_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
- signal ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_lane_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ring_lane_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_bsn_monitor_v2_ring_rx_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_bsn_monitor_v2_ring_rx_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_bsn_monitor_v2_ring_tx_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_bsn_monitor_v2_ring_tx_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_block_validate_err_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_block_validate_err_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_block_validate_bsn_at_sync_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_block_validate_bsn_at_sync_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_lane_info_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_ring_lane_info_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_bsn_monitor_v2_ring_rx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_bsn_monitor_v2_ring_rx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_bsn_monitor_v2_ring_tx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_bsn_monitor_v2_ring_tx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_dp_block_validate_err_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_dp_block_validate_err_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_dp_block_validate_bsn_at_sync_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_dp_block_validate_bsn_at_sync_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
-
- signal from_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal to_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal dp_mux_snk_out_2arr : t_dp_siso_2arr_2(c_nof_lanes - 1 downto 0);
- signal dp_mux_snk_in_2arr : t_dp_sosi_2arr_2(c_nof_lanes - 1 downto 0);
-
- signal dp_xonoff_lane_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_lane_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
- signal dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
-
- signal lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal tr_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
- signal tr_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
- signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
- signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
-
- signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
-
- signal ring_info : t_ring_info;
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'); -- default use lane input = 0, 1 = local input.
- -- 10GbE
- signal tr_ref_clk_312 : std_logic;
- signal tr_ref_clk_156 : std_logic;
- signal tr_ref_rst_156 : std_logic;
- signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
- signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
- signal i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
- signal i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ signal gn_index : natural;
+ signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
- signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
- signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+ -- System
+ signal cs_sim : std_logic;
+ signal xo_ethclk : std_logic;
+ signal xo_rst : std_logic;
+ signal xo_rst_n : std_logic;
+ signal mm_clk : std_logic;
+ signal mm_rst : std_logic := '0';
- signal unb2_board_front_io_serial_tx_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
- signal unb2_board_front_io_serial_rx_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ signal dp_pps : std_logic;
+ signal dp_rst : std_logic;
+ signal dp_clk : std_logic;
- signal this_bck_id : std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0);
- signal this_chip_id : std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0);
+ -- PIOs
+ signal pout_wdi : std_logic;
- -- QSFP LEDS
- signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
- signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
+ -- WDI override
+ signal reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
-begin
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
+ -- PPSH
+ signal reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+ -- UniBoard system info
+ signal reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+ -- UniBoard I2C sens
+ signal reg_unb_sens_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_unb_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
+ -- pm bus
+ signal reg_unb_pmbus_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_unb_pmbus_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
+ -- FPGA sensors
+ signal reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+ -- eth1g
+ signal eth1g_mm_rst : std_logic;
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal eth1g_reg_interrupt : std_logic; -- Interrupt
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+ -- EPCS read
+ signal reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
+ -- EPCS write
+ signal reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- EPCS status/control
+ signal reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- Remote Update
+ signal reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- Scrap ram
+ signal ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ signal ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ ----------------------------------------------
+ -- 10 GbE
+ ----------------------------------------------
+ signal reg_tr_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_tr_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
+ signal ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_lane_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ring_lane_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_bsn_monitor_v2_ring_rx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_ring_rx_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_bsn_monitor_v2_ring_tx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_ring_tx_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_block_validate_err_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_block_validate_err_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_block_validate_bsn_at_sync_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_block_validate_bsn_at_sync_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_lane_info_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_ring_lane_info_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_bsn_monitor_v2_ring_rx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_bsn_monitor_v2_ring_rx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_bsn_monitor_v2_ring_tx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_bsn_monitor_v2_ring_tx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_dp_block_validate_err_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_dp_block_validate_err_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_dp_block_validate_bsn_at_sync_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_dp_block_validate_bsn_at_sync_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+
+ signal from_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal to_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal dp_mux_snk_out_2arr : t_dp_siso_2arr_2(c_nof_lanes - 1 downto 0);
+ signal dp_mux_snk_in_2arr : t_dp_sosi_2arr_2(c_nof_lanes - 1 downto 0);
+
+ signal dp_xonoff_lane_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_lane_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
+ signal dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
+
+ signal lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal tr_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal tr_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
+ signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
+
+ signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
+ signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+ signal ring_info : t_ring_info;
+
+ -- 10GbE
+ signal tr_ref_clk_312 : std_logic;
+ signal tr_ref_clk_156 : std_logic;
+ signal tr_ref_rst_156 : std_logic;
+ signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+
+ signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+ signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+
+ signal unb2_board_front_io_serial_tx_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ signal unb2_board_front_io_serial_rx_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+
+ signal this_bck_id : std_logic_vector(c_unb2b_board_nof_uniboard_w - 1 downto 0);
+ signal this_chip_id : std_logic_vector(c_unb2b_board_nof_chip_w - 1 downto 0);
+
+ -- QSFP LEDS
+ signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
+ signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
+
+ signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
+begin
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2b_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -664,26 +665,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -695,49 +696,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -748,50 +749,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -799,50 +800,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -854,7 +855,7 @@ begin
lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> odd lanes receive from cable
-- QSFP_TX
tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else -- use_cable_to_next_rn=1 -> even lanes transmit to cable
- lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
@@ -871,45 +872,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -937,14 +938,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -954,21 +955,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -983,18 +984,18 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index d922173d669de38fbd3b051ba1e456e904460dfc..624b7ec9105c50a901e851f83624b4ab96e250bf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -19,13 +19,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -39,7 +39,6 @@ package lofar2_unb2b_ring_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_ring_config;
-
end lofar2_unb2b_ring_pkg;
package body lofar2_unb2b_ring_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index 1ae1c752c22c1e09deeff3e8e390387ec3b170b3..19f85b5d5ad61b21c3c26a759d474e295391f518 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2b_ring is
generic (
@@ -159,71 +159,95 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+
+ u_mm_file_reg_dp_block_validate_err : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
- u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+ u_mm_file_reg_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+ u_mm_file_ram_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
- u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+ u_mm_file_reg_ring_lane_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
- u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+ u_mm_file_reg_dp_xonoff_lane : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
- u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+ u_mm_file_reg_dp_xonoff_local : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 44c943c0a76371ac71bff7354db5faa72e782bba..49a3b9203b03f5ee442369490b2982560a1df750 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -19,227 +19,226 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_ring_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_ring;
-
+ component qsys_lofar2_unb2b_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_ring;
end qsys_lofar2_unb2b_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index a41b295e624654a5b30cfca9e41c1f014839f0b1..3e1f315318e207a09b25b139b258dbd7b8de746c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -33,22 +33,22 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.lofar2_unb2b_ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.lofar2_unb2b_ring_pkg.all;
entity tb_lofar2_unb2b_ring is
generic (
@@ -164,55 +164,55 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to g_nof_rn - 1 generate
u_lofar_unb2b_ring : entity work.lofar2_unb2b_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => g_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_sim_sync_timeout => c_sync_timeout
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
- -- LEDs
- QSFP_LED => open
-
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => g_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_sim_sync_timeout => c_sync_timeout
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+ -- LEDs
+ QSFP_LED => open
+
+ );
end generate;
-- Ring connections
@@ -263,9 +263,9 @@ begin
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn, tb_clk);
end loop;
- ----------------------------------------------------------------------------
- -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
+ ----------------------------------------------------------------------------
else
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop
@@ -293,8 +293,8 @@ begin
if g_access_scheme = 1 then
-- Wait for bsn monitor to have received a sync period.
mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
for I in 0 to c_nof_lanes - 1 loop
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
@@ -316,14 +316,14 @@ begin
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
end loop;
- ----------------------------------------------------------------------------
- -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
+ ----------------------------------------------------------------------------
else
- -- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop -- lane index
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d3b80ca5d9bb1acacc0877d95d9ae7ab801c8751..a849e66204f41fe878756dedc718c5d26182380d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2b_ring is
end tb_tb_lofar2_unb2b_ring;
@@ -42,14 +42,14 @@ architecture tb of tb_tb_lofar2_unb2b_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 0, "lofar2_unb2b_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2b_ring generic map(true, 1, "lofar2_unb2b_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2b_ring generic map(true, 2, "lofar2_unb2b_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index bd619d79329a78c77405e68e916edc70d06c6e90..bcd3dba039a35d516aa70e40a315cbb5c1250343 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, oversampeld FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2b_sdp_station_full is
generic (
@@ -90,7 +90,7 @@ entity disturb2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index f8d63040562e1ce27dddf1de39a6e3e71ca931cb..d09f22cd754c4a8913a1a8c2e6ab586d0b76d3a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -26,15 +26,15 @@
-- Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity disturb2_unb2b_sdp_station_full_wg is
generic (
@@ -100,61 +100,61 @@ end disturb2_unb2b_sdp_station_full_wg;
architecture str of disturb2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
index 4a1080e7605e740d0ba02b7b772795396a5a6d44..0abf51ffe560c6bf22aa6d7cde22d814ff9a007f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -63,20 +63,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_disturb2_unb2b_sdp_station_full_wg is
end tb_disturb2_unb2b_sdp_station_full_wg;
@@ -106,7 +106,7 @@ architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
-- WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-- . ampl
- constant c_beamlet_scale : real := 1.0 / 2.0**9;
+ constant c_beamlet_scale : real := 1.0 / 2.0 ** 9;
constant c_wg_ampl_sp_0 : natural := natural(7.0 / c_beamlet_scale); -- choose < 8.0 to have no beamlet output overflow with unit weights and unit beamlet scale
constant c_wg_ampl_sp_2 : natural := c_wg_ampl_sp_0 / 3; -- use different ampl for sp_0 and sp_2 to distinghuis them
-- . phase
@@ -153,9 +153,9 @@ architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
constant c_addr_w_reg_dp_xonoff : natural := 1;
constant c_addr_w_reg_bf_scale : natural := 1;
-- . Address spans of a single MM instance
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
- constant c_mm_span_reg_dp_xonoff : natural := 2**c_addr_w_reg_dp_xonoff;
- constant c_mm_span_reg_bf_scale : natural := 2**c_addr_w_reg_bf_scale;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_dp_xonoff : natural := 2 ** c_addr_w_reg_dp_xonoff;
+ constant c_mm_span_reg_bf_scale : natural := 2 ** c_addr_w_reg_bf_scale;
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -247,52 +247,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_disturb2_unb2b_sdp_station_full_wg : entity work.disturb2_unb2b_sdp_station_full_wg
- generic map (
- g_design_name => "disturb2_unb2b_sdp_station_full_wg",
- g_design_note => "SIM Disturb2 SDP station full design WG",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_wpfb_complex => c_wpfb_complex_sim
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "disturb2_unb2b_sdp_station_full_wg",
+ g_design_note => "SIM Disturb2 SDP station full design WG",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_wpfb_complex => c_wpfb_complex_sim
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -302,7 +302,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
@@ -383,13 +383,13 @@ begin
-- 3 : ampl[16:0]
-- WG at signal input 0
v_offset := 0 * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
-- WG at signal input 2
v_offset := 2 * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase_sp_2 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(c_subband_sp_2 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl_sp_2) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -408,8 +408,8 @@ begin
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read 10GbE Stream
@@ -519,9 +519,9 @@ begin
assert signed(beamlet_arr2_im(c_exp_beamlet_index)) = c_exp_beamlet_im_sp_0 report "Wrong 10GbE beamlet output /= c_exp_beamlet_im_sp_0 in beamset 0" severity ERROR;
-- WG at subband edge will change phase 180 degrees in every subband period, so expect factor +-1
assert signed(beamlet_arr2_re(c_exp_beamlet_index_os)) = c_exp_beamlet_re_sp_2 or
- signed(beamlet_arr2_re(c_exp_beamlet_index_os)) = -c_exp_beamlet_re_sp_2 report "Wrong 10GbE beamlet output /= c_exp_beamlet_re_sp_2 in beamset 1 (shifted subbands)" severity ERROR;
+ signed(beamlet_arr2_re(c_exp_beamlet_index_os)) = -c_exp_beamlet_re_sp_2 report "Wrong 10GbE beamlet output /= c_exp_beamlet_re_sp_2 in beamset 1 (shifted subbands)" severity ERROR;
assert signed(beamlet_arr2_im(c_exp_beamlet_index_os)) = c_exp_beamlet_im_sp_2 or
- signed(beamlet_arr2_im(c_exp_beamlet_index_os)) = -c_exp_beamlet_im_sp_2 report "Wrong 10GbE beamlet output /= c_exp_beamlet_im_sp_2 in beamset 1 (shifted subbands)" severity ERROR;
+ signed(beamlet_arr2_im(c_exp_beamlet_index_os)) = -c_exp_beamlet_im_sp_2 report "Wrong 10GbE beamlet output /= c_exp_beamlet_im_sp_2 in beamset 1 (shifted subbands)" severity ERROR;
---------------------------------------------------------------------------
-- End Simulation
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index 061841c5e476d3f97ddef6398e4caa6978ab842a..85ef8c9df1e0bf6a4983896374a46cd0778e384a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_adc is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index eefec65249bc24e73d6ebd6d769fe7c3963852f0..1216ff474acacdd588394c70acd1475414d2c748 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -44,19 +44,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_adc is
end tb_lofar2_unb2b_sdp_station_adc;
@@ -89,7 +89,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_adc is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
@@ -168,52 +168,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_adc : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -249,7 +249,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -270,8 +270,8 @@ begin
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
@@ -286,7 +286,7 @@ begin
-- Verify sp_power_sum
---------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
- v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
+ v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(TO_UINT(sp_power_sum(29 downto 0))));
assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index 852d977aeeeecea267480821e3338a2d5fcf37ce..8479da0e8201da897628a075ca1f9f77d4d81a3b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_bf is
generic (
@@ -81,7 +81,7 @@ entity lofar2_unb2b_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -113,58 +113,58 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index fc88e90a4a3bb1d561ce39a0571146b0799a99ec..6c30d294054bb202f1091dbe13dccc8ba9fa0abb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -65,24 +65,24 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_sdp_station_bf is
generic (
@@ -143,23 +143,23 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_beamlet_index_mod : boolean := true;
- constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(3, 6), -- antenna_field_index
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-- .ampl
constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
+ constant c_exp_sp_power : real := real(c_wg_ampl ** 2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
@@ -175,7 +175,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_subband_weight_gain : real := 1.0; -- use default unit subband weights
constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex, so no divide by 2
+ constant c_exp_subband_power : real := c_exp_subband_ampl ** 2.0; -- complex, so no divide by 2
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
type t_real_arr is array (integer range <>) of real;
@@ -194,8 +194,8 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_exp_beamlet_re : real := c_exp_beamlet_ampl * COS(c_exp_beamlet_phase * MATH_2_PI / 360.0);
constant c_exp_beamlet_im : real := c_exp_beamlet_ampl * SIN(c_exp_beamlet_phase * MATH_2_PI / 360.0);
-- . BST
- constant c_exp_beamlet_power : real := c_exp_beamlet_ampl**2.0; -- complex, so no divide by 2
- constant c_exp_beamlet_bst : real := c_exp_subband_sst * g_bf_gain**2.0; -- = c_exp_beamlet_power * REAL(c_nof_block_per_sync)
+ constant c_exp_beamlet_power : real := c_exp_beamlet_ampl ** 2.0; -- complex, so no divide by 2
+ constant c_exp_beamlet_bst : real := c_exp_subband_sst * g_bf_gain ** 2.0; -- = c_exp_beamlet_power * REAL(c_nof_block_per_sync)
-- . Beamlet output
constant c_exp_beamlet_output_ampl : real := c_exp_beamlet_ampl * g_beamlet_scale;
constant c_exp_beamlet_output_phase : real := c_exp_beamlet_phase;
@@ -215,14 +215,14 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz);
-- . Address spans of a single MM instance
-- . c_sdp_S_pn = 12 instances
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
-- . c_sdp_N_beamsets = 2 instances
- constant c_mm_span_ram_ss_ss_wide : natural := 2**c_addr_w_ram_ss_ss_wide;
- constant c_mm_span_ram_bf_weights : natural := 2**c_addr_w_ram_bf_weights;
- constant c_mm_span_reg_bf_scale : natural := 2**c_addr_w_reg_bf_scale;
- constant c_mm_span_reg_hdr_dat : natural := 2**c_addr_w_reg_hdr_dat;
- constant c_mm_span_reg_dp_xonoff : natural := 2**c_addr_w_reg_dp_xonoff;
- constant c_mm_span_ram_st_bst : natural := 2**c_addr_w_ram_st_bst;
+ constant c_mm_span_ram_ss_ss_wide : natural := 2 ** c_addr_w_ram_ss_ss_wide;
+ constant c_mm_span_ram_bf_weights : natural := 2 ** c_addr_w_ram_bf_weights;
+ constant c_mm_span_reg_bf_scale : natural := 2 ** c_addr_w_reg_bf_scale;
+ constant c_mm_span_reg_hdr_dat : natural := 2 ** c_addr_w_reg_hdr_dat;
+ constant c_mm_span_reg_dp_xonoff : natural := 2 ** c_addr_w_reg_dp_xonoff;
+ constant c_mm_span_ram_st_bst : natural := 2 ** c_addr_w_ram_st_bst;
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -383,125 +383,125 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_bf : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => si_lpbk_0(0),
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => rx_beamlet_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -696,7 +696,7 @@ begin
-- 3 : ampl[16:0]
-- . Put wanted signal on g_sp input
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -732,7 +732,7 @@ begin
v_im := unpack_complex_im(rd_data, c_sdp_W_sub_weight);
sp_subband_weight_re <= v_re;
sp_subband_weight_im <= v_im;
- sp_subband_weight_gain <= SQRT(real(v_re)**2.0 + real(v_im)**2.0) / real(c_sdp_unit_sub_weight);
+ sp_subband_weight_gain <= SQRT(real(v_re) ** 2.0 + real(v_im) ** 2.0) / real(c_sdp_unit_sub_weight);
sp_subband_weight_phase <= atan2(Y => real(v_im), X => real(v_re)) * 360.0 / MATH_2_PI;
-- No need to write subband weight, because default it is unit weight
@@ -813,7 +813,7 @@ begin
v_S := A * c_sdp_N_pol + P;
sp_bf_weights_re_arr(v_S) <= v_re;
sp_bf_weights_im_arr(v_S) <= v_im;
- sp_bf_weights_gain_arr(v_S) <= SQRT(real(v_re)**2.0 + real(v_im)**2.0) / real(c_sdp_unit_bf_weight);
+ sp_bf_weights_gain_arr(v_S) <= SQRT(real(v_re) ** 2.0 + real(v_im) ** 2.0) / real(c_sdp_unit_bf_weight);
sp_bf_weights_phase_arr(v_S) <= atan2(Y => real(v_im), X => real(v_re)) * 360.0 / MATH_2_PI;
end loop;
end loop;
@@ -825,8 +825,8 @@ begin
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
-- Stimuli done, now verify results at end of test
stimuli_done <= '1';
@@ -1048,7 +1048,7 @@ begin
exp_payload_error,
c_exp_beamlet_scale,
c_exp_beamlet_index,
- exp_dp_bsn);
+ exp_dp_bsn);
rx_sdp_cep_header <= func_sdp_map_cep_header(rx_hdr_fields_raw);
@@ -1096,8 +1096,8 @@ begin
-- in func_sdp_verify_cep_header().
if rx_beamlet_sosi.eop = '1' then
v_bool := func_sdp_verify_cep_header(rx_sdp_cep_header,
- exp_sdp_cep_header,
- c_beamlet_index_mod);
+ exp_sdp_cep_header,
+ c_beamlet_index_mod);
end if;
end process;
@@ -1114,13 +1114,13 @@ begin
-- . Beamlets array is stored big endian in the data, so X.real index 0 first
-- in MSByte of rx_beamlet_sosi.data.
proc_sdp_rx_beamlet_octets(ext_clk,
- rx_beamlet_sosi,
- rx_beamlet_cnt,
- rx_beamlet_valid,
- rx_beamlet_arr_re,
- rx_beamlet_arr_im,
- rx_packet_list_re,
- rx_packet_list_im);
+ rx_beamlet_sosi,
+ rx_beamlet_cnt,
+ rx_beamlet_valid,
+ rx_beamlet_arr_re,
+ rx_beamlet_arr_im,
+ rx_packet_list_re,
+ rx_packet_list_im);
-- To view the 64 bit 10GbE offload data more easily in the Wave window
rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w - 1 downto 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index 2285e92f73ce6f98e3395c146054461765d58284..f22b4e87c4f45ce4b6c68671bb17a6ff24ee0501 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -39,19 +39,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_bf_bst_offload is
end tb_lofar2_unb2b_sdp_station_bf_bst_offload;
@@ -150,52 +150,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_bf : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -241,9 +241,9 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 486993590125f4e5b065d84dbb19c848d0f80367..877fe97c9a07c5c52229d6672c407cd81b0dae08 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_fsub is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index ae4d83d08ea97fa788ff42172351ba2766e67b31..55d45e0ed8f117868dfcd9abe6a30f6ee15fe6da 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -59,19 +59,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
entity tb_lofar2_unb2b_sdp_station_fsub is
generic (
@@ -114,7 +114,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-- .ampl
constant c_wg_ampl : natural := natural(g_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
+ constant c_exp_sp_power : real := real(c_wg_ampl ** 2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
constant c_subband_phase : real := 0.0; -- wanted subband phase in degrees = WG phase at sop
@@ -129,8 +129,8 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
constant c_pfb_index : natural := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
constant c_exp_subband_ampl_raw : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
constant c_exp_subband_ampl_weighted : real := c_exp_subband_ampl_raw * g_subband_weight_gain;
- constant c_exp_subband_power_raw : real := c_exp_subband_ampl_raw**2.0; -- complex, so no divide by 2
- constant c_exp_subband_power_weighted : real := c_exp_subband_ampl_weighted**2.0; -- complex, so no divide by 2
+ constant c_exp_subband_power_raw : real := c_exp_subband_ampl_raw ** 2.0; -- complex, so no divide by 2
+ constant c_exp_subband_power_weighted : real := c_exp_subband_ampl_weighted ** 2.0; -- complex, so no divide by 2
constant c_exp_subband_sst_raw : real := c_exp_subband_power_raw * real(c_nof_block_per_sync);
constant c_exp_subband_sst_weighted : real := c_exp_subband_power_weighted * real(c_nof_block_per_sync);
@@ -150,7 +150,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
-- . Address widths of a single MM instance
constant c_addr_w_reg_diag_wg : natural := 2;
-- . Address spans of a single MM instance
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
constant c_mm_file_reg_bsn_scheduler_wg : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
@@ -245,53 +245,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_fsub : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
-- Raw or weighted subbands
exp_subband_ampl <= sel_a_b(sst_offload_weighted_subbands = '0', c_exp_subband_ampl_raw, c_exp_subband_ampl_weighted);
@@ -343,7 +343,7 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -370,7 +370,7 @@ begin
v_im := unpack_complex_im(rd_data, c_sdp_W_sub_weight);
sp_subband_weight_re <= v_re;
sp_subband_weight_im <= v_im;
- sp_subband_weight_gain <= SQRT(real(v_re)**2.0 + real(v_im)**2.0) / real(c_sdp_unit_sub_weight);
+ sp_subband_weight_gain <= SQRT(real(v_re) ** 2.0 + real(v_im) ** 2.0) / real(c_sdp_unit_sub_weight);
sp_subband_weight_phase <= atan2(Y => real(v_im), X => real(v_re)) * 360.0 / MATH_2_PI;
-- . write
v_weight := pack_complex(re => c_subband_weight_re, im => c_subband_weight_im, w => c_sdp_W_sub_weight); -- c_sdp_W_sub_weight = 16 bit
@@ -381,15 +381,15 @@ begin
v_im := unpack_complex_im(rd_data, c_sdp_W_sub_weight);
sp_subband_weight_re <= v_re;
sp_subband_weight_im <= v_im;
- sp_subband_weight_gain <= SQRT(real(v_re)**2.0 + real(v_im)**2.0) / real(c_sdp_unit_sub_weight);
+ sp_subband_weight_gain <= SQRT(real(v_re) ** 2.0 + real(v_im) ** 2.0) / real(c_sdp_unit_sub_weight);
sp_subband_weight_phase <= atan2(Y => real(v_im), X => real(v_re)) * 360.0 / MATH_2_PI;
----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read subband statistics
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
index 01701f878f46068c3a02ac7b9f690496b64f6208..c2857f43d83eae36acadd7808209b672768c40b8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -38,19 +38,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2b_sdp_station_fsub_sst_offload;
@@ -149,52 +149,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_fsub : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -240,9 +240,9 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index fd878bb3cf9de4a6271d3a4b340665f85b2b7383..a26ca92a9bb8210a347fcc240b57c9460eaecb76 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full is
generic (
@@ -90,7 +90,7 @@ entity lofar2_unb2b_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index 5412994b0eead9bb2323560ce8d2bb771a82c8c3..5321f5e2c14f5403de6f350e4c4f2def20326477 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_full_wg is
generic (
@@ -96,59 +96,59 @@ end lofar2_unb2b_sdp_station_full_wg;
architecture str of lofar2_unb2b_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 925e86ef84fc7f1e3f86c40c9a2c239e8e5e5992..c7d563a7d346436a968a4781f11835941ebe8926 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_one is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2b_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2b_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 95899d4d5894634e6b1ab3fda7976c57cc8819e0..f4e8be5b4ded22c2c2d92c4b4320df99272d63db 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -46,19 +46,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_one is
end tb_lofar2_unb2b_sdp_station_xsub_one;
@@ -92,7 +92,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_nof_clk_per_sync);
-- WPFB
constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -176,53 +176,53 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_xsub_one : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -264,7 +264,7 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -289,8 +289,8 @@ begin
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read crosslet statistics
@@ -330,37 +330,37 @@ begin
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
- -- Check real values of odd indices
- if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check real values of even correlated with odd indices
- if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
- -- Check im values of even indices
- if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of odd indices
- if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of even correlated with odd indices
- if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check if values are > 0
- if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
- end loop;
-
- ---------------------------------------------------------------------------
- -- End Simulation
- ---------------------------------------------------------------------------
- sim_done <= '1';
- proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
- wait;
- end process;
-end tb;
+ -- Check real values of odd indices
+ if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check real values of even correlated with odd indices
+ if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of odd indices
+ if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of even correlated with odd indices
+ if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check if values are > 0
+ if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
+ end loop;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
+ wait;
+ end process;
+ end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index 955572365e77b02697bb9109ae11fccf0bd528a7..b08ba8b701693c7864d755fe99faef99d448fb30 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -39,19 +39,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
end tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload;
@@ -149,52 +149,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_sdp_station_xsub_one : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -252,9 +252,9 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index 1cd39a4cd95fd46ed27f655314b2054711fd1046..693db344f062bc2691b418cc0a08bed0d4ebb1f5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB with ring
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2b_sdp_station_xsub_ring is
generic (
@@ -90,7 +90,7 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2b)
+ -- back transceivers (note only 6 are used in unb2b)
BCK_RX : in std_logic_vector(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b - 1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -122,67 +122,67 @@ begin
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 9e7401c049e4ad2d0100efebeca9f6cac2999df2..9d38e57649e70ccc8c019f8b8894ae88ae2bc002 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -46,20 +46,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, lofar2_unb2b_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2b_sdp_station_xsub_ring is
end tb_lofar2_unb2b_sdp_station_xsub_ring;
@@ -97,7 +97,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_nof_clk_per_sync);
-- WPFB
constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -192,65 +192,65 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to c_nof_rn - 1 generate
u_lofar_unb2b_sdp_station_xsub_ring : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_xsub_ring",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_xsub_ring",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2b_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
end generate;
-- Ring connections
@@ -316,18 +316,18 @@ begin
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_RING_LANE_INFO_XST", I * 2 + 1, c_nof_rn - 1, tb_clk);
end loop;
- ----------------------------------------------------------------------------
- -- Disable unused streams in dp_bsn_align_v2
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Disable unused streams in dp_bsn_align_v2
+ ----------------------------------------------------------------------------
for I in 0 to c_sdp_P_sq - 1 loop
if I >= c_P_sq then
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_ALIGN_V2_XSUB", I, 0, tb_clk);
end if;
end loop;
- ----------------------------------------------------------------------------
- -- Crosslets Info
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Crosslets Info
+ ----------------------------------------------------------------------------
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 0, integer(c_subband_sp_0), tb_clk); -- offset
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk); -- stepsize
end loop;
@@ -341,7 +341,7 @@ begin
-- 3 : ampl[16:0]
for RN in 0 to c_nof_rn - 1 loop
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_WG", I * 4 + 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -370,8 +370,8 @@ begin
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read crosslet statistics
@@ -381,7 +381,7 @@ begin
for I in 0 to c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz) - 1 loop
v_W := I mod 2;
v_B := I / 2;
- v_SQ_offset := 2**ceil_log2(c_sdp_N_crosslets_max * c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz)); -- Address offset for next P_sq.
+ v_SQ_offset := 2 ** ceil_log2(c_sdp_N_crosslets_max * c_nof_complex * c_sdp_X_sq * (c_longword_sz / c_word_sz)); -- Address offset for next P_sq.
if v_W = 0 then
-- low part
mmf_mm_bus_rd(c_mm_file_ram_st_xsq, v_SQ_offset + I, rd_data, tb_clk);
@@ -414,69 +414,69 @@ begin
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
- -- Check real values of odd indices
- if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check real values of even correlated with odd indices
- if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
- -- Check im values of even indices
- if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of odd indices
- if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of even correlated with odd indices
- if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check if values are > 0
- if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
- end loop;
-
- ----------------------------------------------------------------------------
- -- Reporting BSN monitors of the bsn_align_v2
- ----------------------------------------------------------------------------
- for RN in 0 to c_nof_rn - 1 loop
- for J in 0 to c_P_sq - 1 loop -- bsn_monitor index
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 0, rd_data, tb_clk); -- status bits
- report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 1, rd_data, tb_clk); -- bsn at sync
- report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 3, rd_data, tb_clk); -- nof_sop
- report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 4, rd_data, tb_clk); -- nof_valid
- report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 5, rd_data, tb_clk); -- nof_err
- report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 6, rd_data, tb_clk); -- latency
- report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
- end loop;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk); -- status bits
- report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk); -- bsn at sync
- report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk); -- nof_sop
- report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk); -- nof_valid
- report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk); -- nof_err
- report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk); -- latency
- report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
- end loop;
-
- ---------------------------------------------------------------------------
- -- End Simulation
- ---------------------------------------------------------------------------
- sim_done <= '1';
- proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
- wait;
- end process;
-end tb;
+ -- Check real values of odd indices
+ if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check real values of even correlated with odd indices
+ if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of odd indices
+ if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of even correlated with odd indices
+ if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check if values are > 0
+ if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
+ end loop;
+
+ ----------------------------------------------------------------------------
+ -- Reporting BSN monitors of the bsn_align_v2
+ ----------------------------------------------------------------------------
+ for RN in 0 to c_nof_rn - 1 loop
+ for J in 0 to c_P_sq - 1 loop -- bsn_monitor index
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 0, rd_data, tb_clk); -- status bits
+ report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 1, rd_data, tb_clk); -- bsn at sync
+ report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 3, rd_data, tb_clk); -- nof_sop
+ report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 4, rd_data, tb_clk); -- nof_valid
+ report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 5, rd_data, tb_clk); -- nof_err
+ report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8 + 6, rd_data, tb_clk); -- latency
+ report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & integer'image(RN) & ", CH_" & integer'image(J) & "." severity NOTE;
+ end loop;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk); -- status bits
+ report "sync_timeout = " & integer'image(TO_UINT(rd_data(2 downto 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk); -- bsn at sync
+ report "bsn_at_sync = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk); -- nof_sop
+ report "nof_sop = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk); -- nof_valid
+ report "nof_valid = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk); -- nof_err
+ report "nof_err = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk); -- latency
+ report "latency = " & integer'image(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & integer'image(RN) & "." severity NOTE;
+ end loop;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
+ wait;
+ end process;
+ end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 50813fd6e158e303f7439e6ff6cda8bcacb5dbfc..63ba76428952e3bfe8df55b410fb03baa7dcb4e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2b_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2b_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2b_sdp_station is
generic (
@@ -104,9 +104,9 @@ entity lofar2_unb2b_sdp_station is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -488,317 +488,317 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_copi,
- reg_unb_sens_miso => reg_unb_sens_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
- reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2b_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_unb_sens_copi => reg_unb_sens_copi,
- reg_unb_sens_cipo => reg_unb_sens_cipo,
- reg_unb_pmbus_copi => reg_unb_pmbus_copi,
- reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bdo_destinations_copi => reg_bdo_destinations_copi,
- reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -807,204 +807,204 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_bdo_transpose => c_revision_select.use_bdo_transpose,
- g_nof_bdo_destinations_max => c_revision_select.nof_bdo_destinations_max,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bdo_destinations_copi => reg_bdo_destinations_copi,
- reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_bdo_transpose => c_revision_select.use_bdo_transpose,
+ g_nof_bdo_destinations_max => c_revision_select.nof_bdo_destinations_max,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -1018,40 +1018,40 @@ begin
-- Front IO
------------
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index 5f3c67cba2d45e3b1a17a1f40ee74994c39095fd..79bed6ac4af57586544b21177d8f2cfeecebd925 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -20,46 +20,45 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
type t_lofar2_unb2b_sdp_station_config is record
no_jesd : boolean;
- use_fsub : boolean;
- use_oversample : boolean;
- use_bf : boolean;
- use_bdo_transpose : boolean;
- nof_bdo_destinations_max : natural; -- <= c_sdp_bdo_mm_nof_destinations_max
- use_xsub : boolean;
- use_ring : boolean;
- P_sq : natural;
- end record;
-
- constant c_ait : t_lofar2_unb2b_sdp_station_config := (false, false, false, false, false, 1, false, false, 0);
- constant c_fsub : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, false, false, 0);
- -- use c_bf on one node also to simulate bdo transpose
- -- use c_bf_ring with ring also to simulate bdo identity
- constant c_bf : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, false, false, 0);
- constant c_bf_ring : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, false, true, 0);
- constant c_xsub_one : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
- constant c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
- -- use c_full_wg for SDP regression test on Arts-unb2b
- constant c_full_wg : t_lofar2_unb2b_sdp_station_config := (true, true, false, true, true, 32, true, true, 9);
- constant c_full : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, true, true, 9);
- constant c_full_wg_os : t_lofar2_unb2b_sdp_station_config := (true, true, true, true, false, 1, true, true, 9);
- -- use c_full_os for SDP on LTS-unb2b of Disturb2
- constant c_full_os : t_lofar2_unb2b_sdp_station_config := (false, true, true, true, false, 1, true, true, 9);
+ use_fsub : boolean;
+ use_oversample : boolean;
+ use_bf : boolean;
+ use_bdo_transpose : boolean;
+nof_bdo_destinations_max : natural; -- <= c_sdp_bdo_mm_nof_destinations_max
+ use_xsub : boolean;
+ use_ring : boolean;
+P_sq : natural;
+end record;
- -- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config;
+constant c_ait : t_lofar2_unb2b_sdp_station_config := (false, false, false, false, false, 1, false, false, 0);
+constant c_fsub : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, false, false, 0);
+-- use c_bf on one node also to simulate bdo transpose
+-- use c_bf_ring with ring also to simulate bdo identity
+constant c_bf : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, false, false, 0);
+constant c_bf_ring : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, false, true, 0);
+constant c_xsub_one : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
+constant c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
+-- use c_full_wg for SDP regression test on Arts-unb2b
+constant c_full_wg : t_lofar2_unb2b_sdp_station_config := (true, true, false, true, true, 32, true, true, 9);
+constant c_full : t_lofar2_unb2b_sdp_station_config := (false, true, false, true, false, 1, true, true, 9);
+constant c_full_wg_os : t_lofar2_unb2b_sdp_station_config := (true, true, true, true, false, 1, true, true, 9);
+-- use c_full_os for SDP on LTS-unb2b of Disturb2
+constant c_full_os : t_lofar2_unb2b_sdp_station_config := (false, true, true, true, false, 1, true, true, 9);
+-- Function to select the revision configuration.
+function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config;
end lofar2_unb2b_sdp_station_pkg;
package body lofar2_unb2b_sdp_station_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 7a65b2f2389ca4570b8af8e2db5ef8cc21079339..b0e137ab55f062dd6575a173a7106aa46ece85e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2b_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2b_sdp_station is
generic (
@@ -150,191 +150,191 @@ entity mmm_lofar2_unb2b_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
-
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
-
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
-
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
-
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
-
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
-
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
-
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output (BDO) header fields
- -- . single destination, used when revision.nof_bdo_destinations_max = 1
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
- -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
- reg_bdo_destinations_copi : out t_mem_copi;
- reg_bdo_destinations_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
+
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
+
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
+
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
+
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
+
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output (BDO) header fields
+ -- . single destination, used when revision.nof_bdo_destinations_max = 1
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+ -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
+ reg_bdo_destinations_copi : out t_mem_copi;
+ reg_bdo_destinations_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2b_sdp_station;
@@ -348,217 +348,292 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+
+ u_mm_file_pio_jesd_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
- u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ u_mm_file_ram_st_histogram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
- u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
- u_mm_file_reg_bdo_destinations : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
- port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
+ u_mm_file_reg_bdo_destinations : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
+ port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
- u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+ u_mm_file_reg_stat_enable_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
- u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+ u_mm_file_reg_stat_hdr_info_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
- u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+ u_mm_file_reg_stat_enable_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
- u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+ u_mm_file_reg_stat_hdr_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
- u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+ u_mm_file_reg_stat_enable_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
- u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+ u_mm_file_reg_stat_hdr_info_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
- u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+ u_mm_file_reg_crosslets_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
- u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+ u_mm_file_reg_nof_crosslets : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
- u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
- u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+ u_mm_file_ram_st_xsq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
- u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+ u_mm_file_reg_bsn_align_v2_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
- u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
+ u_mm_file_reg_ring_lane_info_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
- u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
- u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
- u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
- u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ u_mm_file_reg_ring_lane_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
- u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
+ u_mm_file_reg_dp_block_validate_err_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -634,8 +709,8 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
rom_system_info_write_export => rom_unb_system_info_copi.wr,
rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 22317623fe4c3cb97e9edcc11d1fda430002e025..e200adb41a29454d38e3803198c6da7a6d87a2b1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -19,568 +19,568 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2b_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
- reg_bdo_destinations_clk_export : out std_logic; -- export
- reg_bdo_destinations_read_export : out std_logic; -- export
- reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bdo_destinations_reset_export : out std_logic; -- export
- reg_bdo_destinations_write_export : out std_logic; -- export
- reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2b_sdp_station;
+ component qsys_lofar2_unb2b_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
+ reg_bdo_destinations_clk_export : out std_logic; -- export
+ reg_bdo_destinations_read_export : out std_logic; -- export
+ reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bdo_destinations_reset_export : out std_logic; -- export
+ reg_bdo_destinations_write_export : out std_logic; -- export
+ reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2b_sdp_station;
end qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index a057ddef1ed45cbf28976e972f10acd299a5b213..70452e845fc1b7aa963e06cb0b358f941b684bad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -31,20 +31,20 @@
-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_lofar2_unb2b_sdp_station is
end tb_lofar2_unb2b_sdp_station;
@@ -72,7 +72,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
--- . 1GbE output
+ -- . 1GbE output
constant c_eth_check_nof_packets : natural := 1;
constant c_eth_runtime_timeout : time := 300 us;
@@ -140,52 +140,52 @@ begin
-- >> DUT <<
u_lofar_unb2b_sdp_station : entity work.lofar2_unb2b_sdp_station
- generic map (
- g_design_name => "lofar2_unb2b_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
@@ -212,7 +212,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -245,12 +245,12 @@ begin
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : entity eth_lib.eth_statistics
- generic map (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout
- )
- port map (
- eth_serial_in => eth_txp(0),
- tb_end => eth_done
- );
+ generic map (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index 1556515bae9a2a48edf9c1abafa56ba96312953a..6d2e5f8892822a02f564bdbdb40aae08fa7dddd1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, lofar2_ddrctrl_lib, tech_ddr_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use diag_lib.diag_pkg.all;
entity lofar2_unb2c_ddrctrl is
generic (
@@ -255,87 +255,88 @@ begin
end process;
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => open
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => c_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => open
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_mosi,
- reg_miso => reg_bsn_scheduler_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_mosi,
+ reg_miso => reg_bsn_scheduler_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_wideband_arr_mosi,
- reg_miso => reg_wg_wideband_arr_miso,
-
- buf_mosi => ram_wg_wideband_arr_mosi,
- buf_miso => ram_wg_wideband_arr_miso,
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_wideband_arr_mosi,
+ reg_miso => reg_wg_wideband_arr_miso,
+
+ buf_mosi => ram_wg_wideband_arr_mosi,
+ buf_miso => ram_wg_wideband_arr_miso,
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
+
p_sosi : process(wg_sosi_arr(I), bs_sosi)
begin
st_sosi_arr(I) <= bs_sosi;
@@ -344,397 +345,397 @@ begin
end generate;
u_stop_in_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_stop_in_mosi,
- reg_miso => reg_stop_in_miso,
+ reg_mosi => reg_stop_in_mosi,
+ reg_miso => reg_stop_in_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => stop_in_arr,
- out_reg => stop_in_arr
- );
+ in_reg => stop_in_arr,
+ out_reg => stop_in_arr
+ );
u_ddrctrl_ctrl_state_reg : entity common_lib.mms_common_reg
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_miso => reg_ddrctrl_ctrl_state_miso,
+ reg_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_miso => reg_ddrctrl_ctrl_state_miso,
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
- in_reg => ddrctrl_ctrl_state,
- out_reg => open
- );
+ in_reg => ddrctrl_ctrl_state,
+ out_reg => open
+ );
u_ddrctrl : entity lofar2_ddrctrl_lib.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_stop_percentage => c_stop_percentage,
- g_block_size => c_bs_block_size
- )
- port map (
- clk => st_clk,
- rst => st_rst,
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => st_sosi_arr,
- stop_in => stop_in_arr(0),
- out_sosi_arr => out_sosi_arr_ddrctrl,
- out_siso => out_siso,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- --PHY
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_stop_percentage => c_stop_percentage,
+ g_block_size => c_bs_block_size
+ )
+ port map (
+ clk => st_clk,
+ rst => st_rst,
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => st_sosi_arr,
+ stop_in => stop_in_arr(0),
+ out_sosi_arr => out_sosi_arr_ddrctrl,
+ out_siso => out_siso,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ --PHY
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU
+ );
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_data_type,
- g_data_w => c_word_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
-
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_data_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_data_type,
+ g_data_w => c_word_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_data_done_arr
+ );
u_diag_bsn_buffer : entity diag_lib.mms_diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
-
- -- General
- g_nof_streams => c_nof_streams,
-
- -- DB settings
- g_data_type => c_bsn_type,
- g_data_w => c_dp_stream_bsn_w,
- g_buf_nof_data => c_buf_nof_words,
- g_buf_use_sync => false,
- g_use_steps => false,
- g_nof_steps => c_diag_seq_rx_reg_nof_steps
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_data_buf_mosi => reg_bsn_buf_mosi,
- reg_data_buf_miso => reg_bsn_buf_miso,
-
- ram_data_buf_mosi => ram_bsn_buf_mosi,
- ram_data_buf_miso => ram_bsn_buf_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- in_sync => st_pps,
- in_sosi_arr => in_sosi_arr_data_buf,
- out_wr_done_arr => out_wr_bsn_done_arr
- );
+ generic map (
+ g_technology => g_technology,
+
+ -- General
+ g_nof_streams => c_nof_streams,
+
+ -- DB settings
+ g_data_type => c_bsn_type,
+ g_data_w => c_dp_stream_bsn_w,
+ g_buf_nof_data => c_buf_nof_words,
+ g_buf_use_sync => false,
+ g_use_steps => false,
+ g_nof_steps => c_diag_seq_rx_reg_nof_steps
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_data_buf_mosi => reg_bsn_buf_mosi,
+ reg_data_buf_miso => reg_bsn_buf_miso,
+
+ ram_data_buf_mosi => ram_bsn_buf_mosi,
+ ram_data_buf_miso => ram_bsn_buf_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ in_sync => st_pps,
+ in_sosi_arr => in_sosi_arr_data_buf,
+ out_wr_done_arr => out_wr_bsn_done_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_ddrctrl
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- bsn_source_v2
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
-
- -- bsn_scheduler
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
-
- -- wg_wideband_arr
- reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
- reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
- ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
- ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
-
- -- stop_in
- reg_stop_in_mosi => reg_stop_in_mosi,
- reg_stop_in_miso => reg_stop_in_miso,
-
- -- ddrctrl_ctrl_state
- reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
- reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
-
- -- io_ddr
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- data_buffer
- reg_data_buf_mosi => reg_data_buf_mosi,
- reg_data_buf_miso => reg_data_buf_miso,
- ram_data_buf_mosi => ram_data_buf_mosi,
- ram_data_buf_miso => ram_data_buf_miso,
- reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
- reg_rx_seq_data_miso => reg_rx_seq_data_miso,
-
- -- bsn_buffer
- reg_bsn_buf_mosi => reg_bsn_buf_mosi,
- reg_bsn_buf_miso => reg_bsn_buf_miso,
- ram_bsn_buf_mosi => ram_bsn_buf_mosi,
- ram_bsn_buf_miso => ram_bsn_buf_miso,
- reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
- reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- bsn_source_v2
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
+
+ -- bsn_scheduler
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_miso,
+
+ -- wg_wideband_arr
+ reg_wg_wideband_arr_mosi => reg_wg_wideband_arr_mosi,
+ reg_wg_wideband_arr_miso => reg_wg_wideband_arr_miso,
+ ram_wg_wideband_arr_mosi => ram_wg_wideband_arr_mosi,
+ ram_wg_wideband_arr_miso => ram_wg_wideband_arr_miso,
+
+ -- stop_in
+ reg_stop_in_mosi => reg_stop_in_mosi,
+ reg_stop_in_miso => reg_stop_in_miso,
+
+ -- ddrctrl_ctrl_state
+ reg_ddrctrl_ctrl_state_mosi => reg_ddrctrl_ctrl_state_mosi,
+ reg_ddrctrl_ctrl_state_miso => reg_ddrctrl_ctrl_state_miso,
+
+ -- io_ddr
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- data_buffer
+ reg_data_buf_mosi => reg_data_buf_mosi,
+ reg_data_buf_miso => reg_data_buf_miso,
+ ram_data_buf_mosi => ram_data_buf_mosi,
+ ram_data_buf_miso => ram_data_buf_miso,
+ reg_rx_seq_data_mosi => reg_rx_seq_data_mosi,
+ reg_rx_seq_data_miso => reg_rx_seq_data_miso,
+
+ -- bsn_buffer
+ reg_bsn_buf_mosi => reg_bsn_buf_mosi,
+ reg_bsn_buf_miso => reg_bsn_buf_miso,
+ ram_bsn_buf_mosi => ram_bsn_buf_mosi,
+ ram_bsn_buf_miso => ram_bsn_buf_miso,
+ reg_rx_seq_bsn_mosi => reg_rx_seq_bsn_mosi,
+ reg_rx_seq_bsn_miso => reg_rx_seq_bsn_miso
+
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index bc7d3e754784cf6a70dbd23d2c0ec3c2f91c8c01..9e8bd335fa67261dd76764909dfc29f871eda4ab 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
entity mmm_lofar2_unb2c_ddrctrl is
generic (
@@ -137,7 +137,7 @@ entity mmm_lofar2_unb2c_ddrctrl is
reg_rx_seq_bsn_mosi : out t_mem_mosi;
reg_rx_seq_bsn_miso : in t_mem_miso
-);
+ );
end mmm_lofar2_unb2c_ddrctrl;
architecture str of mmm_lofar2_unb2c_ddrctrl is
@@ -150,69 +150,91 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_reg_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
+ u_mm_file_reg_wg_wideband_arr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG_WIDEBAND_ARR")
+ port map(mm_rst, mm_clk, reg_wg_wideband_arr_mosi, reg_wg_wideband_arr_miso);
- u_mm_file_ram_wg_wideband_arr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
- port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
+ u_mm_file_ram_wg_wideband_arr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG_WIDEBAND_ARR")
+ port map(mm_rst, mm_clk, ram_wg_wideband_arr_mosi, ram_wg_wideband_arr_miso);
- u_mm_file_reg_stop_in : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
- port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
+ u_mm_file_reg_stop_in : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STOP_IN")
+ port map(mm_rst, mm_clk, reg_stop_in_mosi, reg_stop_in_miso);
- u_mm_file_reg_ddrctrl_state : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
- port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
+ u_mm_file_reg_ddrctrl_state : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DDRCTRL_CTRL_STATE")
+ port map(mm_rst, mm_clk, reg_ddrctrl_ctrl_state_mosi, reg_ddrctrl_ctrl_state_miso);
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
- u_mm_file_reg_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
- port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
+ u_mm_file_reg_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DATA_BUF")
+ port map(mm_rst, mm_clk, reg_data_buf_mosi, reg_data_buf_miso);
- u_mm_file_ram_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
- port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
+ u_mm_file_ram_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DATA_BUF")
+ port map(mm_rst, mm_clk, ram_data_buf_mosi, ram_data_buf_miso);
- u_mm_file_reg_rx_seq_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
- port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
+ u_mm_file_reg_rx_seq_data : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_DATA")
+ port map(mm_rst, mm_clk, reg_rx_seq_data_mosi, reg_rx_seq_data_miso);
- u_mm_file_reg_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
- port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
+ u_mm_file_reg_bsn_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_BUF")
+ port map(mm_rst, mm_clk, reg_bsn_buf_mosi, reg_bsn_buf_miso);
- u_mm_file_ram_bsn_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
- port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
+ u_mm_file_ram_bsn_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BSN_BUF")
+ port map(mm_rst, mm_clk, ram_bsn_buf_mosi, ram_bsn_buf_miso);
- u_mm_file_reg_rx_seq_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
- port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
+ u_mm_file_reg_rx_seq_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
+ port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -431,7 +453,6 @@ begin
reg_ddrctrl_ctrl_state_readdata_export => reg_ddrctrl_ctrl_state_miso.rddata(c_word_w - 1 downto 0),
reg_ddrctrl_ctrl_state_write_export => reg_ddrctrl_ctrl_state_mosi.wr,
reg_ddrctrl_ctrl_state_writedata_export => reg_ddrctrl_ctrl_state_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index aa9cb7c67cda243aa068f6502e8a4471b38a6cee..534a166a90c857a459774f038b67f8426f1d22d8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -20,192 +20,191 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ddrctrl_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
-
- component qsys_lofar2_unb2c_ddrctrl is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bsn_buf_reset_export : out std_logic; -- export
- ram_bsn_buf_clk_export : out std_logic; -- export
- ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bsn_buf_write_export : out std_logic; -- export
- ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bsn_buf_read_export : out std_logic; -- export
- ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_data_buf_reset_export : out std_logic; -- export
- ram_data_buf_clk_export : out std_logic; -- export
- ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
- ram_data_buf_write_export : out std_logic; -- export
- ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_data_buf_read_export : out std_logic; -- export
- ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_wideband_arr_reset_export : out std_logic; -- export
- ram_wg_wideband_arr_clk_export : out std_logic; -- export
- ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_wideband_arr_write_export : out std_logic; -- export
- ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_wideband_arr_read_export : out std_logic; -- export
- ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stop_in_reset_export : out std_logic; -- export
- reg_stop_in_clk_export : out std_logic; -- export
- reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stop_in_write_export : out std_logic; -- export
- reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stop_in_read_export : out std_logic; -- export
- reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_reset_export : out std_logic; -- export
- reg_io_ddr_clk_export : out std_logic; -- export
- reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
- reg_io_ddr_write_export : out std_logic; -- export
- reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_read_export : out std_logic; -- export
- reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_wideband_arr_reset_export : out std_logic; -- export
- reg_wg_wideband_arr_clk_export : out std_logic; -- export
- reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_wideband_arr_write_export : out std_logic; -- export
- reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_wideband_arr_read_export : out std_logic; -- export
- reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
- reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_ddrctrl;
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
+ component qsys_lofar2_unb2c_ddrctrl is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bsn_buf_reset_export : out std_logic; -- export
+ ram_bsn_buf_clk_export : out std_logic; -- export
+ ram_bsn_buf_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bsn_buf_write_export : out std_logic; -- export
+ ram_bsn_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bsn_buf_read_export : out std_logic; -- export
+ ram_bsn_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_data_buf_reset_export : out std_logic; -- export
+ ram_data_buf_clk_export : out std_logic; -- export
+ ram_data_buf_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_data_buf_write_export : out std_logic; -- export
+ ram_data_buf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_data_buf_read_export : out std_logic; -- export
+ ram_data_buf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_wideband_arr_reset_export : out std_logic; -- export
+ ram_wg_wideband_arr_clk_export : out std_logic; -- export
+ ram_wg_wideband_arr_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_wideband_arr_write_export : out std_logic; -- export
+ ram_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_wideband_arr_read_export : out std_logic; -- export
+ ram_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stop_in_reset_export : out std_logic; -- export
+ reg_stop_in_clk_export : out std_logic; -- export
+ reg_stop_in_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stop_in_write_export : out std_logic; -- export
+ reg_stop_in_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stop_in_read_export : out std_logic; -- export
+ reg_stop_in_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_reset_export : out std_logic; -- export
+ reg_io_ddr_clk_export : out std_logic; -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_io_ddr_write_export : out std_logic; -- export
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_read_export : out std_logic; -- export
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_wideband_arr_reset_export : out std_logic; -- export
+ reg_wg_wideband_arr_clk_export : out std_logic; -- export
+ reg_wg_wideband_arr_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_wideband_arr_write_export : out std_logic; -- export
+ reg_wg_wideband_arr_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_wideband_arr_read_export : out std_logic; -- export
+ reg_wg_wideband_arr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ddrctrl_ctrl_state_reset_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_clk_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ddrctrl_ctrl_state_write_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_ddrctrl_ctrl_state_read_export : out std_logic; -- export
+ reg_ddrctrl_ctrl_state_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_ddrctrl;
end qsys_lofar2_unb2c_ddrctrl_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 2e4ac9d8d868dd53538e960a49ef02807376189c..9dc5d9e3d94e7172b15c90014c837813c17b1c29 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -42,27 +42,27 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, mm_lib, dp_lib, tech_ddr_lib, lofar2_sdp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use diag_lib.diag_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity tb_lofar2_unb2c_ddrctrl is
- generic (
- g_design_name : string := "lofar2_unb2c_ddrctrl";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "lofar2_unb2c_ddrctrl";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_lofar2_unb2c_ddrctrl;
architecture tb of tb_lofar2_unb2c_ddrctrl is
@@ -99,7 +99,7 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
constant c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
constant c_ctrl_data_w : natural := func_tech_ddr_ctlr_data_w(c_tech_ddr); -- 576
constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the address vector length
+ constant c_max_adr : natural := 2 ** (c_adr_w) - 1; -- the maximal address that is possible within the address vector length
constant c_block_size : natural := 1024;
constant c_nof_streams : natural := 12;
constant c_data_w : natural := 14;
@@ -120,7 +120,7 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
constant c_wg_freq : real := 160.0; -- WG freq
constant c_wg_ampl : natural := natural(1.0 * real(c_sdp_FS_adc)); -- in number of lsb
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_subband : real := 1.0 * (2**c_speed);
+ constant c_subband : real := 1.0 * (2 ** c_speed);
-- DUT
signal st_clk : std_logic := '0';
@@ -178,7 +178,7 @@ begin
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_lofar2_unb2c_ddrctrl : entity work.lofar2_unb2c_ddrctrl
+ u_lofar2_unb2c_ddrctrl : entity work.lofar2_unb2c_ddrctrl
generic map (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
@@ -209,7 +209,7 @@ begin
);
- -- WG
+ -- WG
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -217,8 +217,7 @@ begin
tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
p_mm_stimuli : process
-
- variable v_bsn : natural := 0;
+ variable v_bsn : natural := 0;
begin
wait for 1 us;
----------------------------------------------------------------------------
@@ -241,7 +240,7 @@ begin
-- 3 : ampl[16:0]
for I in 0 to c_nof_streams - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 1, integer(c_wg_phase), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 2, integer(real(c_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I * 4) + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -258,7 +257,7 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -270,7 +269,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -280,7 +279,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -290,7 +289,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -300,7 +299,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -310,7 +309,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -320,7 +319,7 @@ begin
wait for c_st_clk_period * c_block_size;
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 240000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -330,7 +329,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -340,7 +339,7 @@ begin
wait for c_st_clk_period * (c_block_size-500);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -350,7 +349,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -360,7 +359,7 @@ begin
wait for c_st_clk_period * (c_block_size);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
wait for c_mm_clk_period * 24000;
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1, tb_clk);
@@ -370,7 +369,7 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
- for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
+ for K in c_block_size - (c_block_size / (2 ** c_speed)) to c_block_size-1 loop
mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
@@ -380,7 +379,7 @@ begin
wait for c_st_clk_period * (c_block_size);
end loop;
------------------------------------------------------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------------------------------------------------------
tb_end <= '1';
assert false report "Test: OK" severity FAILURE;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index e8ebe5092ffb6baf376b6bf33af2e15c31ae5968..9bc349a60504ed17b41ff90011e7c918bc7f256d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2c_filterbank_full is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index 82942a08d3a10ab712f640a73207bcb9a7d7d6b1..07e233688a7df91216de301a9a5ea1637e275c80 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_filterbank_full_256MHz is
generic (
@@ -74,7 +74,7 @@ entity lofar2_unb2c_filterbank_full_256MHz is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 6 are used in unb2c)
+ -- back transceivers (note only 6 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b + c_unb2c_board_start_tr_jesd204b - 1 downto c_unb2c_board_nof_tr_jesd204b);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -106,51 +106,51 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index a8ae459ab259b858a1f6e7a89ff8c8a4f60bdde6..8be378229a738fd40abfb8a1db7acd1ae60012d0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -27,17 +27,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_filterbank_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_filterbank_pkg.all;
entity lofar2_unb2c_filterbank is
generic (
@@ -85,9 +85,9 @@ entity lofar2_unb2c_filterbank is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -104,7 +104,7 @@ architecture str of lofar2_unb2c_filterbank is
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
- constant c_lofar2_sample_clk_freq : natural := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
+ constant c_lofar2_sample_clk_freq : natural := 200 * 10 ** 6; -- alternate 160MHz. TODO: Use to check PPS
-- System
signal cs_sim : std_logic;
@@ -259,221 +259,221 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_filterbank
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
+ ram_equalizer_gains_miso => ram_equalizer_gains_miso,
+ reg_dp_selector_mosi => reg_dp_selector_mosi,
+ reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
@@ -481,82 +481,82 @@ begin
-----------------------------------------------------------------------------
u_ait: entity lofar2_sdp_lib.node_adc_input_and_timing
- generic map(
- g_nof_streams => c_sdp_S_pn,
- g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
- ram_aduh_monitor_miso => ram_aduh_monitor_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_sdp_S_pn,
+ g_buf_nof_data => c_sdp_ait_buf_nof_data_bsn,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+ reg_wg_mosi => reg_wg_mosi,
+ reg_wg_miso => reg_wg_miso,
+ ram_wg_mosi => ram_wg_mosi,
+ ram_wg_miso => ram_wg_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
+ ram_aduh_monitor_miso => ram_aduh_monitor_miso,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr
+ );
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+ ram_st_sst_mosi => ram_st_sst_mosi,
+ ram_st_sst_miso => ram_st_sst_miso,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_gains_mosi => ram_equalizer_gains_mosi,
+ ram_gains_miso => ram_equalizer_gains_miso,
+ reg_selector_mosi => reg_dp_selector_mosi,
+ reg_selector_miso => reg_dp_selector_miso
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
index 617e401becaadd6ae2136b036964cb07dc2348f4..2babc9a9bd67cfb934164a28bb6bc9cc15110404 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_filterbank_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,7 +43,6 @@ package lofar2_unb2c_filterbank_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_filterbank_config;
-
end lofar2_unb2c_filterbank_pkg;
package body lofar2_unb2c_filterbank_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
index fa4e12bb7ebf8ffe23157e2fa7f24779c4c37f30..22ed970c8623851bcf8a82da4ca84db6625a8dd7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_filterbank_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_filterbank_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_filterbank is
generic (
@@ -154,13 +154,13 @@ entity mmm_lofar2_unb2c_filterbank is
reg_si_mosi : out t_mem_mosi;
reg_si_miso : in t_mem_miso;
- -- Equalizer gains
- ram_equalizer_gains_mosi : out t_mem_mosi;
- ram_equalizer_gains_miso : in t_mem_miso;
+ -- Equalizer gains
+ ram_equalizer_gains_mosi : out t_mem_mosi;
+ ram_equalizer_gains_miso : in t_mem_miso;
- -- DP Selector
- reg_dp_selector_mosi : out t_mem_mosi;
- reg_dp_selector_miso : in t_mem_miso;
+ -- DP Selector
+ reg_dp_selector_mosi : out t_mem_mosi;
+ reg_dp_selector_miso : in t_mem_miso;
-- Scrap ram
ram_scrap_mosi : out t_mem_mosi;
@@ -178,86 +178,119 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+
+ u_mm_file_reg_bsn_source : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
+ port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- port map(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_reg_bsn_source : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- port map(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_ram_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ u_mm_file_reg_diag_data_buf_jesd : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, ram_diag_data_buf_jesd_mosi, ram_diag_data_buf_jesd_miso );
- u_mm_file_reg_diag_data_buf_jesd : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_JESD")
- port map(mm_rst, mm_clk, reg_diag_data_buf_jesd_mosi, reg_diag_data_buf_jesd_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_ram_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ADUH_MONITOR")
- port map(mm_rst, mm_clk, ram_aduh_monitor_mosi, ram_aduh_monitor_miso );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -333,9 +366,9 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ -- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -351,9 +384,9 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
+ -- ToDo: This has changed in the peripherals package
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
--- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ -- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 3193b1a4e866e50ee1b08de077a7ac83b789782d..3808754179eefb147e90b4207ff8ebcfff9272ce 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -19,268 +19,267 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_filterbank_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_filterbank is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_filterbank;
-
+ component qsys_lofar2_unb2c_filterbank is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_aduh_monitor_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_aduh_monitor_clk_export : out std_logic; -- export
+ ram_aduh_monitor_read_export : out std_logic; -- export
+ ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_aduh_monitor_reset_export : out std_logic; -- export
+ ram_aduh_monitor_write_export : out std_logic; -- export
+ ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_bsn_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_filterbank;
end qsys_lofar2_unb2c_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
index 260d1427fd7440fac1f3a4aec28bf8c4a34955b3..a92a06c663b4cc4c3fabb7445758f96c760bf8a6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
@@ -51,19 +51,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_filterbank is
end tb_lofar2_unb2c_filterbank;
@@ -92,14 +92,14 @@ architecture tb of tb_lofar2_unb2c_filterbank is
constant c_hi_factor : real := 1.0 + c_percentage; -- higher boundary
-- WG
- constant c_full_scale_ampl : real := real(2**(18 - 1) - 1); -- = full scale of WG
+ constant c_full_scale_ampl : real := real(2 ** (18 - 1) - 1); -- = full scale of WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2 ** (c_sdp_W_adc - 1) / 2; -- in number of lsb
constant c_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
constant c_wg_ampl_lsb : real := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_sdp_N_fft * c_nof_block_per_sync);
-- WPFB
constant c_nof_pfb : natural := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -199,52 +199,52 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_filterbank : entity work.lofar2_unb2c_filterbank
- generic map (
- g_design_name => "lofar2_unb2c_filterbank_full",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_filterbank_full",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -278,7 +278,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
@@ -304,8 +304,8 @@ begin
----------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
wait for c_sdp_T_sub; -- ensure that one block of samples has filled the ADUH monitor buffer after the sync
@@ -328,8 +328,8 @@ begin
---------------------------------------------------------------------------
-- Wait for start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
-- Read ADUH monitor power sum
mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
@@ -343,7 +343,7 @@ begin
---------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
- v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
+ v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(TO_UINT(sp_power_sum(29 downto 0))));
assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
@@ -375,8 +375,8 @@ begin
-- Convert STD_LOGIC_VECTOR to REAL
v_sp_subband_power := real(TO_UINT(rd_data(29 downto 0) &
- sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
+ sp_subband_powers_arr2(v_S)(v_B)(31 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_subband_powers_arr2(v_S)(v_B)(29 downto 0)));
-- sum
sp_subband_power_sum(v_S) <= sp_subband_power_sum(v_S) + v_sp_subband_power;
end if;
@@ -385,8 +385,8 @@ begin
-- sp_subband_power_sum is the sum of all subband powers per SP, this value will be close to sp_subband_power
-- because the input is a sinus, so most power will be in 1 subband. The sp_subband_power_leakage_sum shows
-- how much power from the input sinus at a specific subband has leaked into the 511 other subbands.
- sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0**30 +
- real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
+ sp_subband_power_0 <= real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(61 downto 30))) * 2.0 ** 30 +
+ real(TO_UINT(sp_subband_powers_arr2(0)(integer(ROUND(c_subband_sp_0)))(29 downto 0)));
sp_subband_power_sum_0 <= sp_subband_power_sum(0);
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 896329e2ff83779b74d415115d61552c3a367eb4..b52458675f59a8af738760e90f28bbe0a5cd8d9e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete ring design with all 8 lanes.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_full is
generic (
@@ -85,48 +85,48 @@ end lofar2_unb2c_ring_full;
architecture str of lofar2_unb2c_ring_full is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
index 17830917aa4976d86f2bd11c8a9c70e26ce0206b..c45c1b0536b6fb017ee627cdc38cd44fce2501b5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_full is
end tb_lofar2_unb2c_ring_full;
@@ -94,45 +94,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_full : entity work.lofar2_unb2c_ring_full
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index 991fdeb9228a16aadb54889827c1f81d926359e5..3284ffa9db29ab2ab758f134d388f861a1e2e4aa 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -29,13 +29,13 @@
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_ring_one is
generic (
@@ -88,48 +88,48 @@ end lofar2_unb2c_ring_one;
architecture str of lofar2_unb2c_ring_one is
begin
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
index 0aff49975ac74650b42b8206d7c239f9c9319ed2..4df91bd7158c98810b43e8f8f265d32d64e79413 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
@@ -28,12 +28,12 @@
-- > run -a # check that design can simulate some us without error
library IEEE, common_lib, unb2c_board_lib, i2c_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2c_ring_one is
end tb_lofar2_unb2c_ring_one;
@@ -94,45 +94,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_ring_one : entity work.lofar2_unb2c_ring_one
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX,
- QSFP_0_TX => i_QSFP_0_TX,
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX,
- RING_0_TX => i_RING_0_TX,
- RING_1_RX => i_RING_1_RX,
- RING_1_TX => i_RING_1_TX,
-
- -- LEDs
- QSFP_LED => open
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX,
+ QSFP_0_TX => i_QSFP_0_TX,
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX,
+ RING_0_TX => i_RING_0_TX,
+ RING_1_RX => i_RING_1_RX,
+ RING_1_TX => i_RING_1_TX,
+
+ -- LEDs
+ QSFP_LED => open
+ );
------------------------------------------------------------------------------
-- Simulation end
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index 44d0371592780c69ebd37b2599f76fa3075634f9..77f892d588497b71186715409b839741f972b51e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -27,21 +27,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, tr_10gbe_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_ring_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_ring_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity lofar2_unb2c_ring is
generic (
@@ -102,7 +102,7 @@ architecture str of lofar2_unb2c_ring is
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_100M;
constant c_lofar2_sample_clk_freq : natural := c_sdp_N_clk_per_sync; -- fixed 200 MHz for LOFAR2.0 stage 1
- -- QSFP
+ -- QSFP
constant c_nof_qsfp_bus : natural := 1;
constant c_nof_streams_qsfp : natural := c_unb2c_board_tr_qsfp.bus_w * c_nof_qsfp_bus; -- 4
@@ -141,486 +141,487 @@ architecture str of lofar2_unb2c_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
- constant c_reg_ring_input_select : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_lanes),
- dat_w => 1,
- nof_dat => c_nof_lanes,
- init_sl => '0'); -- default use lane input = 0, 1 = local input.
-
- signal gn_index : natural;
- signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
-
- -- System
- signal cs_sim : std_logic;
- signal xo_ethclk : std_logic;
- signal xo_rst : std_logic;
- signal xo_rst_n : std_logic;
- signal mm_clk : std_logic;
- signal mm_rst : std_logic := '0';
-
- signal dp_pps : std_logic;
- signal dp_rst : std_logic;
- signal dp_clk : std_logic;
-
- -- PIOs
- signal pout_wdi : std_logic;
-
- -- WDI override
- signal reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- PPSH
- signal reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- UniBoard system info
- signal reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
- signal rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- FPGA sensors
- signal reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- eth1g
- signal eth1g_mm_rst : std_logic;
- signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
- signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
- signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal eth1g_reg_interrupt : std_logic; -- Interrupt
- signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
- signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS read
- signal reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS write
- signal reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- EPCS status/control
- signal reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- Remote Update
- signal reg_remu_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- -- Scrap ram
- signal ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
- signal ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- ----------------------------------------------
- -- 10 GbE
- ----------------------------------------------
- signal reg_tr_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_tr_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
- signal ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_lane_info_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_ring_lane_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_bsn_monitor_v2_ring_rx_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_bsn_monitor_v2_ring_rx_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_bsn_monitor_v2_ring_tx_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_bsn_monitor_v2_ring_tx_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_block_validate_err_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_block_validate_err_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_dp_block_validate_bsn_at_sync_copi : t_mem_copi := c_mem_copi_rst;
- signal reg_dp_block_validate_bsn_at_sync_cipo : t_mem_cipo := c_mem_cipo_rst;
-
- signal reg_ring_lane_info_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_ring_lane_info_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_bsn_monitor_v2_ring_rx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_bsn_monitor_v2_ring_rx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_bsn_monitor_v2_ring_tx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_bsn_monitor_v2_ring_tx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_dp_block_validate_err_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_dp_block_validate_err_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
- signal reg_dp_block_validate_bsn_at_sync_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
- signal reg_dp_block_validate_bsn_at_sync_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
-
- signal from_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal to_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal dp_mux_snk_out_2arr : t_dp_siso_2arr_2(c_nof_lanes - 1 downto 0);
- signal dp_mux_snk_in_2arr : t_dp_sosi_2arr_2(c_nof_lanes - 1 downto 0);
-
- signal dp_xonoff_lane_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_lane_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
- signal dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
-
- signal lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_rx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
- signal lane_tx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal tr_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
- signal tr_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
- signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
- signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
-
- signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
- signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
-
- signal ring_info : t_ring_info;
+ constant c_reg_ring_input_select : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'); -- default use lane input = 0, 1 = local input.
- -- 10GbE
- signal tr_ref_clk_312 : std_logic;
- signal tr_ref_clk_156 : std_logic;
- signal tr_ref_rst_156 : std_logic;
- signal i_QSFP_TX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
- signal i_QSFP_RX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
- signal i_RING_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
- signal i_RING_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ signal gn_index : natural;
+ signal this_rn : std_logic_vector(c_byte_w - 1 downto 0);
- signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
- signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+ -- System
+ signal cs_sim : std_logic;
+ signal xo_ethclk : std_logic;
+ signal xo_rst : std_logic;
+ signal xo_rst_n : std_logic;
+ signal mm_clk : std_logic;
+ signal mm_rst : std_logic := '0';
- signal unb2_board_front_io_serial_tx_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
- signal unb2_board_front_io_serial_rx_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ signal dp_pps : std_logic;
+ signal dp_rst : std_logic;
+ signal dp_clk : std_logic;
- signal this_bck_id : std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0);
- signal this_chip_id : std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0);
+ -- PIOs
+ signal pout_wdi : std_logic;
- -- QSFP LEDS
- signal qsfp_green_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
- signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
+ -- WDI override
+ signal reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
-begin
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
+ -- PPSH
+ signal reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+ -- UniBoard system info
+ signal reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+ -- FPGA sensors
+ signal reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
+ -- eth1g
+ signal eth1g_mm_rst : std_logic;
+ signal eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ signal eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ signal eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal eth1g_reg_interrupt : std_logic; -- Interrupt
+ signal eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ signal eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+ -- EPCS read
+ signal reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
+ -- EPCS write
+ signal reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ -- EPCS status/control
+ signal reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- Remote Update
+ signal reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- Scrap ram
+ signal ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ signal ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ ----------------------------------------------
+ -- 10 GbE
+ ----------------------------------------------
+ signal reg_tr_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_tr_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
+ signal ram_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_xonoff_lane_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_xonoff_lane_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_xonoff_local_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_xonoff_local_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_lane_info_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_ring_lane_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_bsn_monitor_v2_ring_rx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_ring_rx_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_bsn_monitor_v2_ring_tx_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_bsn_monitor_v2_ring_tx_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_block_validate_err_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_block_validate_err_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_dp_block_validate_bsn_at_sync_copi : t_mem_copi := c_mem_copi_rst;
+ signal reg_dp_block_validate_bsn_at_sync_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ signal reg_ring_lane_info_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_ring_lane_info_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_bsn_monitor_v2_ring_rx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_bsn_monitor_v2_ring_rx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_bsn_monitor_v2_ring_tx_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_bsn_monitor_v2_ring_tx_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_dp_block_validate_err_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_dp_block_validate_err_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+ signal reg_dp_block_validate_bsn_at_sync_copi_arr : t_mem_copi_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_copi_rst);
+ signal reg_dp_block_validate_bsn_at_sync_cipo_arr : t_mem_cipo_arr(c_nof_lanes - 1 downto 0) := (others => c_mem_cipo_rst);
+
+ signal from_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal to_lane_sosi_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal dp_mux_snk_out_2arr : t_dp_siso_2arr_2(c_nof_lanes - 1 downto 0);
+ signal dp_mux_snk_in_2arr : t_dp_sosi_2arr_2(c_nof_lanes - 1 downto 0);
+
+ signal dp_xonoff_lane_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_lane_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
+ signal dp_xonoff_local_snk_in_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_local_src_out_arr : t_dp_sosi_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_xonoff_local_src_in_arr : t_dp_siso_arr(c_nof_lanes - 1 downto 0) := (others => c_dp_siso_rdy);
+
+ signal lane_rx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_cable_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_board_even_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_rx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_cable_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal lane_tx_board_odd_sosi_arr : t_dp_sosi_arr(c_nof_even_lanes - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal tr_10gbe_src_out_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal tr_10gbe_snk_in_arr : t_dp_sosi_arr(c_nof_mac - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
+ signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
+
+ signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
+ signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+ signal ring_info : t_ring_info;
+
+ -- 10GbE
+ signal tr_ref_clk_312 : std_logic;
+ signal tr_ref_clk_156 : std_logic;
+ signal tr_ref_rst_156 : std_logic;
+ signal i_QSFP_TX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_QSFP_RX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_RING_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+ signal i_RING_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
+
+ signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+ signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
+
+ signal unb2_board_front_io_serial_tx_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+ signal unb2_board_front_io_serial_rx_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
+
+ signal this_bck_id : std_logic_vector(c_unb2c_board_nof_uniboard_w - 1 downto 0);
+ signal this_chip_id : std_logic_vector(c_unb2c_board_nof_chip_w - 1 downto 0);
+
+ -- QSFP LEDS
+ signal qsfp_green_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
+ signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
+
+ signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
+begin
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM controller
-----------------------------------------------------------------------------
u_mmc : entity work.mmc_lofar2_unb2c_ring
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
- reg_diag_bg_copi => reg_diag_bg_copi,
- reg_diag_bg_cipo => reg_diag_bg_cipo,
- ram_diag_bg_copi => ram_diag_bg_copi,
- ram_diag_bg_cipo => ram_diag_bg_cipo,
- reg_ring_lane_info_copi => reg_ring_lane_info_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
- reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
- reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
- reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
- reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo,
+ reg_diag_bg_copi => reg_diag_bg_copi,
+ reg_diag_bg_cipo => reg_diag_bg_cipo,
+ ram_diag_bg_copi => ram_diag_bg_copi,
+ ram_diag_bg_cipo => ram_diag_bg_cipo,
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo,
+ reg_dp_xonoff_lane_copi => reg_dp_xonoff_lane_copi,
+ reg_dp_xonoff_lane_cipo => reg_dp_xonoff_lane_cipo,
+ reg_dp_xonoff_local_copi => reg_dp_xonoff_local_copi,
+ reg_dp_xonoff_local_cipo => reg_dp_xonoff_local_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo
+ );
-----------------------------------------------------------------------------
-- MM Mux
-----------------------------------------------------------------------------
u_mem_mux_ring_lane_info : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info
- )
- port map (
- mosi => reg_ring_lane_info_copi,
- miso => reg_ring_lane_info_cipo,
- mosi_arr => reg_ring_lane_info_copi_arr,
- miso_arr => reg_ring_lane_info_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info
+ )
+ port map (
+ mosi => reg_ring_lane_info_copi,
+ miso => reg_ring_lane_info_cipo,
+ mosi_arr => reg_ring_lane_info_copi_arr,
+ miso_arr => reg_ring_lane_info_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_rx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_copi,
- miso => reg_bsn_monitor_v2_ring_rx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_cipo_arr
+ );
u_mem_mux_bsn_monitor_v2_ring_tx : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_copi,
- miso => reg_bsn_monitor_v2_ring_tx_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_cipo_arr
+ );
u_mem_mux_dp_block_validate_err : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
- )
- port map (
- mosi => reg_dp_block_validate_err_copi,
- miso => reg_dp_block_validate_err_cipo,
- mosi_arr => reg_dp_block_validate_err_copi_arr,
- miso_arr => reg_dp_block_validate_err_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_err
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_copi,
+ miso => reg_dp_block_validate_err_cipo,
+ mosi_arr => reg_dp_block_validate_err_copi_arr,
+ miso_arr => reg_dp_block_validate_err_cipo_arr
+ );
u_mem_mux_dp_block_validate_bsn_at_sync : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_lanes,
- g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_copi,
- miso => reg_dp_block_validate_bsn_at_sync_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_lanes,
+ g_mult_addr_w => c_addr_w_reg_dp_block_validate_bsn_at_sync
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_cipo_arr
+ );
-----------------------------------------------------------------------------
-- MMP diag_block_gen
-----------------------------------------------------------------------------
u_mmp_diag_block_gen : entity diag_lib.mms_diag_block_gen
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
-
- reg_bg_ctrl_mosi => reg_diag_bg_copi,
- reg_bg_ctrl_miso => reg_diag_bg_cipo,
- ram_bg_data_mosi => ram_diag_bg_copi,
- ram_bg_data_miso => ram_diag_bg_cipo,
-
- out_sosi_arr(0) => local_sosi
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_copi,
+ reg_bg_ctrl_miso => reg_diag_bg_cipo,
+ ram_bg_data_mosi => ram_diag_bg_copi,
+ ram_bg_data_miso => ram_diag_bg_cipo,
+
+ out_sosi_arr(0) => local_sosi
+ );
bs_sosi <= local_sosi;
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '1' -- default enabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_lane_copi,
- reg_miso => reg_dp_xonoff_lane_cipo,
+ reg_mosi => reg_dp_xonoff_lane_copi,
+ reg_miso => reg_dp_xonoff_lane_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => from_lane_sosi_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => from_lane_sosi_arr,
- src_in_arr => dp_xonoff_lane_src_in_arr,
- src_out_arr => dp_xonoff_lane_src_out_arr
- );
+ src_in_arr => dp_xonoff_lane_src_in_arr,
+ src_out_arr => dp_xonoff_lane_src_out_arr
+ );
-----------------------------------------------------------------------------
-- MMP dp_xonoff local_sosi
@@ -630,26 +631,26 @@ begin
end generate;
u_mmp_dp_xonoff_local : entity dp_lib.mms_dp_xonoff
- generic map (
- g_nof_streams => c_nof_lanes,
- g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => c_nof_lanes,
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_dp_xonoff_local_copi,
- reg_miso => reg_dp_xonoff_local_cipo,
+ reg_mosi => reg_dp_xonoff_local_copi,
+ reg_miso => reg_dp_xonoff_local_cipo,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- snk_out_arr => OPEN,
- snk_in_arr => dp_xonoff_local_snk_in_arr,
+ snk_out_arr => OPEN,
+ snk_in_arr => dp_xonoff_local_snk_in_arr,
- src_in_arr => dp_xonoff_local_src_in_arr,
- src_out_arr => dp_xonoff_local_src_out_arr
- );
+ src_in_arr => dp_xonoff_local_src_in_arr,
+ src_out_arr => dp_xonoff_local_src_out_arr
+ );
-----------------------------------------------------------------------------
-- DP Mux
@@ -661,49 +662,49 @@ begin
dp_mux_snk_in_2arr(I)(1) <= dp_xonoff_local_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true,
- g_use_fifo => true,
- g_bsn_w => c_longword_w,
- g_data_w => c_lane_data_w,
- g_in_channel_w => c_byte_w,
- g_error_w => c_nof_err_counts,
- g_use_bsn => true,
- g_use_in_channel => true,
- g_use_error => true,
- g_use_sync => true,
- -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
- g_fifo_size => array_init(2 * c_lane_packet_length, 2)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_mux_snk_out_2arr(I),
- snk_in_arr => dp_mux_snk_in_2arr(I),
-
- src_in => c_dp_siso_rdy,
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true,
+ g_use_fifo => true,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => true,
+ g_use_in_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ -- Using fifo size of 2 * packet length for both inputs of the mux as a packet might arrive on both the local and remote input.
+ g_fifo_size => array_init(2 * c_lane_packet_length, 2)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_mux_snk_out_2arr(I),
+ snk_in_arr => dp_mux_snk_in_2arr(I),
+
+ src_in => c_dp_siso_rdy,
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
-- Use full c_byte_w range of ID for gn_index and ring_info.O_rn
gn_index <= TO_UINT(ID);
@@ -714,50 +715,50 @@ begin
-----------------------------------------------------------------------------
gen_even_lanes: for I in 0 to c_nof_even_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
- to_lane_sosi => to_lane_sosi_arr(2 * I),
- lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I), -- even indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I),
+ lane_rx_cable_sosi => lane_rx_cable_even_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_even_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_even_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_even_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -765,50 +766,50 @@ begin
-----------------------------------------------------------------------------
gen_odd_lanes : for I in 0 to c_nof_odd_lanes - 1 generate
u_ring_lane : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 0, -- transport in negative direction.
- g_lane_data_w => c_lane_data_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_nof_rx_monitors,
- g_nof_tx_monitors => c_nof_tx_monitors,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
- to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
- lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
- lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
- lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
- lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
- reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
- tx_select => ring_info.use_cable_to_previous_rn
- );
+ generic map (
+ g_lane_direction => 0, -- transport in negative direction.
+ g_lane_data_w => c_lane_data_w,
+ g_lane_packet_length => c_lane_packet_length,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_nof_rx_monitors,
+ g_nof_tx_monitors => c_nof_tx_monitors,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => from_lane_sosi_arr(2 * I + 1), -- odd indices
+ to_lane_sosi => to_lane_sosi_arr(2 * I + 1),
+ lane_rx_cable_sosi => lane_rx_cable_odd_sosi_arr(I),
+ lane_rx_board_sosi => lane_rx_board_odd_sosi_arr(I),
+ lane_tx_cable_sosi => lane_tx_cable_odd_sosi_arr(I),
+ lane_tx_board_sosi => lane_tx_board_odd_sosi_arr(I),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_copi_arr(2 * I + 1),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_cipo_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_copi_arr(2 * I + 1),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_copi_arr(2 * I + 1),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_cipo_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2 * I + 1),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2 * I + 1),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
+ );
end generate;
-----------------------------------------------------------------------------
@@ -820,7 +821,7 @@ begin
lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) when ring_info.use_cable_to_next_rn = '1' else c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> odd lanes receive from cable
-- QSFP_TX
tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) when ring_info.use_cable_to_next_rn = '1' else -- use_cable_to_next_rn=1 -> even lanes transmit to cable
- lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
+ lane_tx_cable_odd_sosi_arr(I) when ring_info.use_cable_to_previous_rn = '1' else c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
-- RING_0_RX even lanes receive from RING_0 (from the left)
lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
@@ -837,45 +838,45 @@ begin
-- tr_10GbE
-----------------------------------------------------------------------------
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill,
- g_tx_fifo_size => c_fifo_tx_size
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill,
+ g_tx_fifo_size => c_fifo_tx_size
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -903,14 +904,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- Front IO
@@ -920,21 +921,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- RING IO
@@ -949,18 +950,18 @@ begin
------------
unb2_board_qsfp_leds_tx_siso_arr(0) <= tr_10gbe_snk_out_arr(0);
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
index 28a9c8341d315412c0150b7a8905bc1fb0f4c6c7..1492953e79b10f059a67c45b82d9fd2fdb4a8af7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
@@ -20,13 +20,13 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_ring_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -40,7 +40,6 @@ package lofar2_unb2c_ring_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_ring_config;
-
end lofar2_unb2c_ring_pkg;
package body lofar2_unb2c_ring_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
index 42f7512e380976a981493559160d58b0950a99a8..632d5257efc7ed3e9f340a0289b3575548ea2c45 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_ring_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_ring_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmc_lofar2_unb2c_ring is
generic (
@@ -153,65 +153,87 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+
+ u_mm_file_reg_dp_block_validate_err : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
- u_mm_file_reg_dp_block_validate_err : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_copi, reg_dp_block_validate_err_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_copi, reg_dp_block_validate_bsn_at_sync_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_copi, reg_bsn_monitor_v2_ring_rx_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_copi, reg_bsn_monitor_v2_ring_tx_cipo );
+ u_mm_file_reg_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_reg_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_copi, reg_diag_bg_cipo );
- u_mm_file_ram_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
+ u_mm_file_ram_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_copi, ram_diag_bg_cipo );
- u_mm_file_reg_ring_lane_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
- port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
+ u_mm_file_reg_ring_lane_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_copi, reg_ring_lane_info_cipo );
- u_mm_file_reg_dp_xonoff_lane : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
+ u_mm_file_reg_dp_xonoff_lane : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_lane_copi, reg_dp_xonoff_lane_cipo );
- u_mm_file_reg_dp_xonoff_local : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
- port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
+ u_mm_file_reg_dp_xonoff_local : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_LOCAL")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_local_copi, reg_dp_xonoff_local_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo);
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 8c35d482f28c694e83468ddaca51cb3918516597..9d6a4f5e3b64bddfcc9258fb80cf5e66e9b7e4d7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -19,213 +19,212 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ring_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_ring is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_clk_export : out std_logic; -- export
- ram_diag_bg_read_export : out std_logic; -- export
- ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_reset_export : out std_logic; -- export
- ram_diag_bg_write_export : out std_logic; -- export
- ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_clk_export : out std_logic; -- export
- reg_diag_bg_read_export : out std_logic; -- export
- reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_reset_export : out std_logic; -- export
- reg_diag_bg_write_export : out std_logic; -- export
- reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
- reg_dp_block_validate_err_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_read_export : out std_logic; -- export
- reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_write_export : out std_logic; -- export
- reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_xonoff_local_clk_export : out std_logic; -- export
- reg_dp_xonoff_local_read_export : out std_logic; -- export
- reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_local_reset_export : out std_logic; -- export
- reg_dp_xonoff_local_write_export : out std_logic; -- export
- reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_ring_lane_info_clk_export : out std_logic; -- export
- reg_ring_lane_info_read_export : out std_logic; -- export
- reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_reset_export : out std_logic; -- export
- reg_ring_lane_info_write_export : out std_logic; -- export
- reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_lofar2_unb2c_ring;
-
+ component qsys_lofar2_unb2c_ring is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_address_export : out std_logic_vector(6 downto 0); -- export
+ ram_diag_bg_clk_export : out std_logic; -- export
+ ram_diag_bg_read_export : out std_logic; -- export
+ ram_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_reset_export : out std_logic; -- export
+ ram_diag_bg_write_export : out std_logic; -- export
+ ram_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_clk_export : out std_logic; -- export
+ reg_diag_bg_read_export : out std_logic; -- export
+ reg_diag_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_reset_export : out std_logic; -- export
+ reg_diag_bg_write_export : out std_logic; -- export
+ reg_diag_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_dp_block_validate_err_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_lane_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_local_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_xonoff_local_clk_export : out std_logic; -- export
+ reg_dp_xonoff_local_read_export : out std_logic; -- export
+ reg_dp_xonoff_local_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_local_reset_export : out std_logic; -- export
+ reg_dp_xonoff_local_write_export : out std_logic; -- export
+ reg_dp_xonoff_local_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_ring_lane_info_clk_export : out std_logic; -- export
+ reg_ring_lane_info_read_export : out std_logic; -- export
+ reg_ring_lane_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_reset_export : out std_logic; -- export
+ reg_ring_lane_info_write_export : out std_logic; -- export
+ reg_ring_lane_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_lofar2_unb2c_ring;
end qsys_lofar2_unb2c_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index 60dc7bbea0781615a5844d2c59e1ec938e65793a..80387e2620edc1422ca0b3c36632dd75a980db65 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -33,22 +33,22 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.lofar2_unb2c_ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.lofar2_unb2c_ring_pkg.all;
entity tb_lofar2_unb2c_ring is
generic (
@@ -162,49 +162,49 @@ begin
------------------------------------------------------------------------------
-- DUTs
------------------------------------------------------------------------------
- gen_dut_rn : for RN in 0 to g_nof_rn - 1 generate
+ gen_dut_rn : for RN in 0 to g_nof_rn - 1 generate
u_lofar_unb2c_ring : entity work.lofar2_unb2c_ring
- generic map (
- g_design_name => g_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => g_unb_nr + (RN / c_quad),
- g_sim_node_nr => RN mod c_quad,
- g_sim_sync_timeout => c_sync_timeout
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2c_board_nof_chip_w) ),
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
- -- LEDs
- QSFP_LED => open
-
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => g_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN mod c_quad,
+ g_sim_sync_timeout => c_sync_timeout
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN mod c_quad, c_unb2c_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+ -- LEDs
+ QSFP_LED => open
+
+ );
end generate;
-- Ring connections
@@ -255,9 +255,9 @@ begin
mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_LANE_INFO", I * 2 + 1, g_nof_rn, tb_clk);
end loop;
- ----------------------------------------------------------------------------
- -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
+ ----------------------------------------------------------------------------
else
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop
@@ -285,8 +285,8 @@ begin
if g_access_scheme = 1 then
-- Wait for bsn monitor to have received a sync period.
mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
for I in 0 to c_nof_lanes - 1 loop
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I * c_sdp_N_pn_max * 8 + 1, rd_data, tb_clk); -- bsn at sync
@@ -308,14 +308,14 @@ begin
assert TO_UINT(rd_data) = 0 report "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." severity ERROR;
end loop;
- ----------------------------------------------------------------------------
- -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
+ ----------------------------------------------------------------------------
else
- -- Wait for bsn monitor to have received a sync period.
- mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
- "SIGNED", rd_data, ">", 0, -- this is the wait until condition
- 1 us, tb_clk); -- read every 1 us
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr + ((g_nof_rn - 1) / c_quad), (g_nof_rn - 1) mod c_quad) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
for RN in 0 to g_nof_rn - 1 loop
for I in 0 to c_nof_lanes - 1 loop -- lane index
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 8d8576c59fc5a8963b9b38fd9587c055aaa59e37..f0971b198609a05636cae5ca3547723ea26cf637 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -29,9 +29,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_pkg.all;
entity tb_tb_lofar2_unb2c_ring is
end tb_tb_lofar2_unb2c_ring;
@@ -42,14 +42,14 @@ architecture tb of tb_tb_lofar2_unb2c_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
--- g_multi_tb : BOOLEAN := FALSE;
--- g_unb_nr : NATURAL := 4;
--- g_design_name : STRING := "lofar2_unb2c_ring_one";
--- g_nof_rn : NATURAL := 16;
--- g_nof_block_per_sync : NATURAL := 32;
--- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
+ -- g_multi_tb : BOOLEAN := FALSE;
+ -- g_unb_nr : NATURAL := 4;
+ -- g_design_name : STRING := "lofar2_unb2c_ring_one";
+ -- g_nof_rn : NATURAL := 16;
+ -- g_nof_block_per_sync : NATURAL := 32;
+ -- g_access_scheme : INTEGER RANGE 1 TO 3 := 2
--- using different g_unb_nr to avoid MM file clashing.
+ -- using different g_unb_nr to avoid MM file clashing.
u_one_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 0, "lofar2_unb2c_ring_one", c_nof_rn, 3, 1) port map(tb_end_vec(0)); -- access scheme 1.
u_one_2_3 : entity work.tb_lofar2_unb2c_ring generic map(true, 1, "lofar2_unb2c_ring_one", c_nof_rn, 3, 2) port map(tb_end_vec(1)); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
u_full_1 : entity work.tb_lofar2_unb2c_ring generic map(true, 2, "lofar2_unb2c_ring_full", c_nof_rn, 3, 1) port map(tb_end_vec(2)); -- access scheme 1.
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index 0a7c377d0a2ce6f6fff31adfcae2f1efb453f3f1..1aa3b6d07d3ef9487407ba7aef031117e36c8ca6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full is
generic (
@@ -82,7 +82,7 @@ entity disturb2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index 0bd6efeaed403e1242fac2f0ef8779b4507fee20..90bb3bb17c61afc8bb1f16c109855c121c4fd759 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity disturb2_unb2c_sdp_station_full_wg is
generic (
@@ -87,51 +87,51 @@ end disturb2_unb2c_sdp_station_full_wg;
architecture str of disturb2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index cde951b9a50baab6ffdcbb9846b03923bc9b252b..e6af7c560ba804d777c8046f62e2093deb4008c8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_adc is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_adc is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index e94d9e9a29ac5f69d5f323243a791b7d0f1fb4dd..3a5bfec6ac9b275b97bb5f16cd7065cdae6a0fe9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -44,19 +44,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_adc is
end tb_lofar2_unb2c_sdp_station_adc;
@@ -89,7 +89,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
@@ -158,44 +158,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_adc : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -231,7 +231,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -252,8 +252,8 @@ begin
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read ADUH monitor power sum
@@ -268,7 +268,7 @@ begin
-- Verify sp_power_sum
---------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
- v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
+ v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(TO_UINT(sp_power_sum(29 downto 0))));
assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
index 02130ecf7708d27b33d450f0218a278e92a10272..0e56765103558a973b6873d03eb12f4297488e3f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -53,20 +53,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use tech_jesd204b_lib.tech_jesd204b_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use tech_jesd204b_lib.tech_jesd204b_pkg.all;
entity tb_lofar2_unb2c_sdp_station_adc_jesd is
end tb_lofar2_unb2c_sdp_station_adc_jesd;
@@ -104,7 +104,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
constant c_ampl_sp_0 : natural := c_sdp_FS_adc / 2; -- = 0.5 * FS, so in number of lsb
constant c_wg_freq_offset : real := 0.0 / 11.0; -- in freq_unit
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0**2) / 2.0 * real(c_nof_clk_per_sync);
+ constant c_exp_wg_power_sp_0 : real := real(c_ampl_sp_0 ** 2) / 2.0 * real(c_nof_clk_per_sync);
-- ADUH
constant c_mon_buffer_nof_samples : natural := 512; -- samples per stream
@@ -217,17 +217,18 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
signal dbg_link_reinit : std_logic := '0';
-- Read JESD204B IP status per signal input c_si
- procedure proc_read_jesd204b(c_si : in natural;
- signal rd_clk : in std_logic;
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- signal dbg_read : out std_logic;
- signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
- signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
- signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
- signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
+ procedure proc_read_jesd204b(
+ c_si : in natural;
+ signal rd_clk : in std_logic;
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ signal dbg_read : out std_logic;
+ signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
+ signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
+ signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
+ signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
constant c_offset : natural := c_si * tech_jesd204b_port_span;
begin
dbg_read <= '1';
@@ -248,26 +249,27 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
dbg_read <= '0';
end;
- procedure proc_read_jesd204b_arr(signal rd_clk : in std_logic;
- signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
- signal dbg_read : out std_logic;
- signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
- signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
- signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
- signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
- signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
+ procedure proc_read_jesd204b_arr(
+ signal rd_clk : in std_logic;
+ signal rd_data : inout std_logic_vector(c_word_w - 1 downto 0);
+ signal dbg_read : out std_logic;
+ signal rx_err_enable : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err_link_reinit : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_syncn_sysref_ctrl : out std_logic_vector(c_word_w - 1 downto 0);
+ signal rx_err0 : out std_logic_vector(tech_jesd204b_field_rx_err0_w - 1 downto 0);
+ signal rx_err1 : out std_logic_vector(tech_jesd204b_field_rx_err1_w - 1 downto 0);
+ signal csr_rbd_count : out std_logic_vector(tech_jesd204b_field_csr_rbd_count_w - 1 downto 0);
+ signal csr_dev_syncn : out std_logic_vector(tech_jesd204b_field_csr_dev_syncn_w - 1 downto 0)) is
begin
for I in 0 to c_sdp_S_pn - 1 loop
proc_read_jesd204b(I, rd_clk, rd_data, dbg_read,
- rx_err_enable,
- rx_err_link_reinit,
- rx_syncn_sysref_ctrl,
- rx_err0,
- rx_err1,
- csr_rbd_count,
- csr_dev_syncn);
+ rx_err_enable,
+ rx_err_link_reinit,
+ rx_syncn_sysref_ctrl,
+ rx_err0,
+ rx_err1,
+ csr_rbd_count,
+ csr_dev_syncn);
end loop;
end;
begin
@@ -292,44 +294,44 @@ begin
-- DUT with JESD204B Rx
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_adc : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_adc",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N
+ );
-----------------------------------------------------------------------------
-- Use a JESD204b Tx instance to model the ADCs
@@ -371,55 +373,55 @@ begin
gen_jesd204b_tx : for i in 0 to c_nof_jesd204b_tx - 1 generate
-- Tb DAC
u_tech_jesd204b_tx : entity tech_jesd204b_lib.tech_jesd204b_tx
- port map (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, -- out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), -- out
- jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
- jesd204_tx_avs_address => tx_avs_address(i),
- jesd204_tx_avs_read => tx_avs_read(i),
- jesd204_tx_avs_readdata => tx_avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => tx_avs_clk,
- jesd204_tx_avs_rst_n => tx_avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
- mdev_sync_n => dev_sync_n(i), -- in
- pll_locked => pll_locked, -- in
- sync_n => jesd204b_sync_adc_n(i), -- in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => JESD204B_SYSREF
- );
+ port map (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, -- out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), -- out
+ jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
+ jesd204_tx_avs_address => tx_avs_address(i),
+ jesd204_tx_avs_read => tx_avs_read(i),
+ jesd204_tx_avs_readdata => tx_avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => tx_avs_clk,
+ jesd204_tx_avs_rst_n => tx_avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), -- in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), -- in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), -- out
+ mdev_sync_n => dev_sync_n(i), -- in
+ pll_locked => pll_locked, -- in
+ sync_n => jesd204b_sync_adc_n(i), -- in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks, -- : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => JESD204B_SYSREF
+ );
-- One JESD204B_SYNC_N per RCU2
jesd204b_sync_adc_n(i) <= JESD204B_SYNC_N(i / c_sdp_S_rcu);
@@ -430,36 +432,35 @@ begin
variable v_even_sample : boolean := true;
begin
if mm_rst = '1' then
- jesd204b_tx_link_data_arr(i) <= (others => '0');
- jesd204b_tx_link_valid(i) <= '0';
- txlink_clk(i) <= '0';
- v_data := 0;
- v_even_sample := true;
- elsif rising_edge(JESD204B_REFCLK) then
- txlink_clk(i) <= not txlink_clk(i);
-
- -- Incrementing data in c_sdp_W_adc_jesd = 16 bits
- -- . use range c_sdp_W_adc_jesd-1 to avoid simulation warnings:
- -- Warning: NUMERIC_STD.TO_SIGNED: vector truncated
- -- Time: 164635 ns Iteration: 0 Region: /tb_lofar2_unb2c_sdp_station_adc_jesd/gen_jesd204b_tx(2)
- v_data := (v_data + 1) mod 2**(c_sdp_W_adc_jesd - 1);
-
- -- Frame the data to 32 bits at half the rate
- if jesd204b_tx_link_ready(i) = '0' then
- v_even_sample := true;
- else
- v_even_sample := not v_even_sample;
- end if;
- if v_even_sample = true then
- jesd204b_tx_link_data_arr(i)(c_sdp_W_adc_jesd - 1 downto 0) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
- jesd204b_tx_link_valid(i) <= '0';
- else
- jesd204b_tx_link_data_arr(i)(2 * c_sdp_W_adc_jesd - 1 downto c_sdp_W_adc_jesd) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
- jesd204b_tx_link_valid(i) <= '1';
- end if;
- end if;
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ v_data := 0;
+ v_even_sample := true;
+ elsif rising_edge(JESD204B_REFCLK) then
+ txlink_clk(i) <= not txlink_clk(i);
+
+ -- Incrementing data in c_sdp_W_adc_jesd = 16 bits
+ -- . use range c_sdp_W_adc_jesd-1 to avoid simulation warnings:
+ -- Warning: NUMERIC_STD.TO_SIGNED: vector truncated
+ -- Time: 164635 ns Iteration: 0 Region: /tb_lofar2_unb2c_sdp_station_adc_jesd/gen_jesd204b_tx(2)
+ v_data := (v_data + 1) mod 2 ** (c_sdp_W_adc_jesd - 1);
+
+ -- Frame the data to 32 bits at half the rate
+ if jesd204b_tx_link_ready(i) = '0' then
+ v_even_sample := true;
+ else
+ v_even_sample := not v_even_sample;
+ end if;
+ if v_even_sample = true then
+ jesd204b_tx_link_data_arr(i)(c_sdp_W_adc_jesd - 1 downto 0) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '0';
+ else
+ jesd204b_tx_link_data_arr(i)(2 * c_sdp_W_adc_jesd - 1 downto c_sdp_W_adc_jesd) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '1';
+ end if;
+ end if;
end process;
-
end generate;
------------------------------------------------------------------------------
@@ -523,7 +524,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -544,21 +545,21 @@ begin
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
----------------------------------------------------------------------------
-- Read JESD204B IP status per signal input
----------------------------------------------------------------------------
for I in 0 to c_sdp_S_pn - 1 loop
proc_read_jesd204b(I, tb_clk, rd_data, dbg_read_jesd204b,
- reg_jesd204b_rx_err_enable,
- reg_jesd204b_rx_err_link_reinit,
- reg_jesd204b_rx_syncn_sysref_ctrl,
- reg_jesd204b_rx_err0,
- reg_jesd204b_rx_err1,
- reg_jesd204b_csr_rbd_count,
- reg_jesd204b_csr_dev_syncn);
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
proc_common_wait_some_cycles(tb_clk, 10);
-----------------------------------------------------------------------
@@ -566,9 +567,9 @@ begin
-----------------------------------------------------------------------
if I < c_nof_jesd204b_tx then
assert unsigned(reg_jesd204b_rx_err_enable) = tech_jesd204b_field_rx_err_enable_reset
- report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_enable)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset) severity ERROR;
+ report "Wrong rx_err_enable_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_enable)) & " /= " & integer'image(tech_jesd204b_field_rx_err_enable_reset) severity ERROR;
assert unsigned(reg_jesd204b_rx_err_link_reinit) = tech_jesd204b_field_rx_err_link_reinit_reset
- report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_link_reinit)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset) severity ERROR;
+ report "Wrong rx_err_link_reinit_reset: " & integer'image(TO_SINT(reg_jesd204b_rx_err_link_reinit)) & " /= " & integer'image(tech_jesd204b_field_rx_err_link_reinit_reset) severity ERROR;
end if;
end loop;
@@ -585,7 +586,7 @@ begin
-- Verify sp_power_sum
---------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
- v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2**30) + real(TO_UINT(sp_power_sum(29 downto 0))));
+ v_sp_power_sum_0 := real(real(TO_UINT(sp_power_sum(61 downto 30))) * real(2 ** 30) + real(TO_UINT(sp_power_sum(29 downto 0))));
assert v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
assert v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 report "Wrong SP power for SP 0" severity ERROR;
@@ -648,13 +649,13 @@ begin
wait for 1 us;
-- Read Rx JESD_204B IP status during reset
proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
- reg_jesd204b_rx_err_enable,
- reg_jesd204b_rx_err_link_reinit,
- reg_jesd204b_rx_syncn_sysref_ctrl,
- reg_jesd204b_rx_err0,
- reg_jesd204b_rx_err1,
- reg_jesd204b_csr_rbd_count,
- reg_jesd204b_csr_dev_syncn);
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
-- Read input delay during reset
mmf_mm_bus_rd(c_mm_file_reg_dp_shiftram, 0, rd_data, tb_clk);
@@ -687,32 +688,32 @@ begin
wait for c_pps_period;
-- Read Rx JESD_204B IP status
proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
- reg_jesd204b_rx_err_enable,
- reg_jesd204b_rx_err_link_reinit,
- reg_jesd204b_rx_syncn_sysref_ctrl,
- reg_jesd204b_rx_err0,
- reg_jesd204b_rx_err1,
- reg_jesd204b_csr_rbd_count,
- reg_jesd204b_csr_dev_syncn);
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
-- 3) Reinit the JESD204B link per signal input
dbg_link_reinit <= '1'; -- marker in wave window
for I in 0 to c_sdp_S_pn - 1 loop
v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_link_reinit +
- tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
+ tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
mmf_mm_bus_wr(c_mm_file_jesd204b, v_offset + tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, v_int, tb_clk);
end loop;
wait for 1 us;
-- Read Rx JESD_204B IP status
proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
- reg_jesd204b_rx_err_enable,
- reg_jesd204b_rx_err_link_reinit,
- reg_jesd204b_rx_syncn_sysref_ctrl,
- reg_jesd204b_rx_err0,
- reg_jesd204b_rx_err1,
- reg_jesd204b_csr_rbd_count,
- reg_jesd204b_csr_dev_syncn);
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
for I in 0 to c_sdp_S_pn - 1 loop
v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
@@ -724,13 +725,13 @@ begin
wait for c_pps_period;
-- Read Rx JESD_204B IP status
proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
- reg_jesd204b_rx_err_enable,
- reg_jesd204b_rx_err_link_reinit,
- reg_jesd204b_rx_syncn_sysref_ctrl,
- reg_jesd204b_rx_err0,
- reg_jesd204b_rx_err1,
- reg_jesd204b_csr_rbd_count,
- reg_jesd204b_csr_dev_syncn);
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
-- Count restart loops
dbg_restart <= dbg_restart + 1;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 9abb13ac1daf7f49579863db07164826d96ae873..04c11f90201b52ecae159c7126f3ceb6cb03ee04 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -73,7 +73,7 @@ entity lofar2_unb2c_sdp_station_bf is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -94,50 +94,50 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
-
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index e1121127b6c8ce995c9ee29cae088f497193767d..631b6720a89fbba639b805756a20b5474b631e9b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -142,27 +142,27 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, reorder_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use lofar2_sdp_lib.sdp_bdo_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use lofar2_sdp_lib.sdp_bdo_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf is
generic (
@@ -240,17 +240,17 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_beamlet_index_mod : boolean := true;
- constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(3, 6), -- antenna_field_index
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- Expected transposed indices order by func_sdp_undo_transpose_beamlet_packet().
-- Yields same c_transpose_indices order as func_reorder_transpose_packet():
@@ -260,20 +260,20 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- The c_transpose_indices is used in sdp_beamformer_output, therefore use
-- c_transpose_indices_inv for func_reorder_transpose_packet() in the tb.
constant c_transpose_indices : t_natural_arr(0 to c_nof_ch - 1) :=
- func_reorder_transpose_indices(c_sdp_cep_nof_blocks_per_packet,
- c_sdp_cep_nof_beamlets_per_block,
- c_sdp_N_pol_bf);
+ func_reorder_transpose_indices(c_sdp_cep_nof_blocks_per_packet,
+ c_sdp_cep_nof_beamlets_per_block,
+ c_sdp_N_pol_bf);
constant c_transpose_indices_inv : t_natural_arr(0 to c_nof_ch - 1) :=
- func_reorder_transpose_indices(c_sdp_cep_nof_beamlets_per_block,
- c_sdp_cep_nof_blocks_per_packet,
- c_sdp_N_pol_bf);
+ func_reorder_transpose_indices(c_sdp_cep_nof_beamlets_per_block,
+ c_sdp_cep_nof_blocks_per_packet,
+ c_sdp_N_pol_bf);
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-- .ampl
constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
+ constant c_exp_sp_power : real := real(c_wg_ampl ** 2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
@@ -290,7 +290,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
constant c_exp_subband_phase : real := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl ** 2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_remnant_subband_phase : real := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
@@ -317,26 +317,26 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- . Beamlet internal
constant c_nof_remnant : natural := c_sdp_S_pn - 1;
constant c_exp_beamlet_x_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
+ c_nof_remnant);
constant c_exp_beamlet_x_ampl : real := c_exp_beamlet_x_tuple(0);
constant c_exp_beamlet_x_phase : real := c_exp_beamlet_x_tuple(1);
constant c_exp_beamlet_x_re : real := c_exp_beamlet_x_tuple(2);
constant c_exp_beamlet_x_im : real := c_exp_beamlet_x_tuple(3);
constant c_exp_beamlet_y_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
+ c_nof_remnant);
constant c_exp_beamlet_y_ampl : real := c_exp_beamlet_y_tuple(0);
constant c_exp_beamlet_y_phase : real := c_exp_beamlet_y_tuple(1);
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
constant c_exp_beamlet_y_im : real := c_exp_beamlet_y_tuple(3);
-- . BST
- constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl ** 2.0; -- complex signal ampl, so no divide by 2
constant c_exp_beamlet_x_bst : real := c_exp_beamlet_x_power * real(c_nof_block_per_sync);
- constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl ** 2.0; -- complex signal ampl, so no divide by 2
constant c_exp_beamlet_y_bst : real := c_exp_beamlet_y_power * real(c_nof_block_per_sync);
-- . Beamlet output
constant c_exp_beamlet_x_output_ampl : real := c_exp_beamlet_x_ampl * g_beamlet_scale;
@@ -363,16 +363,16 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz);
-- . Address spans of a single MM instance
-- . c_sdp_S_pn = 12 instances
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
-- . c_sdp_N_beamsets = 2 instances
- constant c_mm_span_ram_ss_ss_wide : natural := 2**c_addr_w_ram_ss_ss_wide;
- constant c_mm_span_ram_bf_weights : natural := 2**c_addr_w_ram_bf_weights;
- constant c_mm_span_reg_bf_scale : natural := 2**c_addr_w_reg_bf_scale;
- constant c_mm_span_reg_hdr_dat : natural := 2**c_addr_w_reg_hdr_dat;
- constant c_mm_span_reg_bdo_destinations : natural := 2**c_addr_w_reg_bdo_destinations;
- constant c_mm_span_reg_stat_enable_bst : natural := 2**c_addr_w_reg_stat_enable_bst;
- constant c_mm_span_reg_dp_xonoff : natural := 2**c_addr_w_reg_dp_xonoff;
- constant c_mm_span_ram_st_bst : natural := 2**c_addr_w_ram_st_bst;
+ constant c_mm_span_ram_ss_ss_wide : natural := 2 ** c_addr_w_ram_ss_ss_wide;
+ constant c_mm_span_ram_bf_weights : natural := 2 ** c_addr_w_ram_bf_weights;
+ constant c_mm_span_reg_bf_scale : natural := 2 ** c_addr_w_reg_bf_scale;
+ constant c_mm_span_reg_hdr_dat : natural := 2 ** c_addr_w_reg_hdr_dat;
+ constant c_mm_span_reg_bdo_destinations : natural := 2 ** c_addr_w_reg_bdo_destinations;
+ constant c_mm_span_reg_stat_enable_bst : natural := 2 ** c_addr_w_reg_stat_enable_bst;
+ constant c_mm_span_reg_dp_xonoff : natural := 2 ** c_addr_w_reg_dp_xonoff;
+ constant c_mm_span_ram_st_bst : natural := 2 ** c_addr_w_ram_st_bst;
constant c_mm_file_reg_ppsh : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -567,120 +567,120 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => c_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_1_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_0,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => c_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_1_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_0,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- CEP model
------------------------------------------------------------------------------
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => si_lpbk_0(0),
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => rx_hdr_dat_mosi,
- reg_hdr_dat_miso => rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => rx_beamlet_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -692,8 +692,8 @@ begin
variable v_data_lo, v_data_hi : std_logic_vector(c_word_w - 1 downto 0);
variable v_stat_data : std_logic_vector(c_longword_w - 1 downto 0);
variable v_len, v_span,
- v_offset, v_offset_bdo,
- v_addr, v_sel : natural; -- address ranges, indices
+ v_offset, v_offset_bdo,
+ v_addr, v_sel : natural; -- address ranges, indices
variable v_W, v_P, v_PB, v_S, v_A, v_B, v_G : natural; -- array indicies
variable v_re, v_im, v_weight : integer;
variable v_re_exp, v_im_exp : real := 0.0;
@@ -935,13 +935,13 @@ begin
v_offset := S * c_mm_span_reg_diag_wg;
if S = g_sp then
-- Strong WG signal at g_sp
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
else
-- Weak WG signal on all other (remnant) SP
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -1118,8 +1118,8 @@ begin
----------------------------------------------------------------------------
-- read BSN low, this is the wait until condition
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
- "UNSIGNED", rd_data_bsn, ">=", c_stimuli_done_bsn,
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data_bsn, ">=", c_stimuli_done_bsn,
+ c_sdp_T_sub, tb_clk);
-- Stimuli done, now verify results at end of test
stimuli_done <= '1';
@@ -1362,7 +1362,7 @@ begin
exp_payload_error,
c_exp_beamlet_scale,
c_exp_beamlet_index,
- exp_dp_bsn);
+ exp_dp_bsn);
rx_sdp_cep_header <= func_sdp_map_cep_header(rx_hdr_fields_raw);
@@ -1410,8 +1410,8 @@ begin
-- in func_sdp_verify_cep_header().
if rx_beamlet_sosi.eop = '1' then
v_bool := func_sdp_verify_cep_header(rx_sdp_cep_header,
- exp_sdp_cep_header,
- c_beamlet_index_mod);
+ exp_sdp_cep_header,
+ c_beamlet_index_mod);
end if;
end process;
@@ -1428,13 +1428,13 @@ begin
-- . Expect c_nof_block_per_sync / c_sdp_cep_nof_blocks_per_packet *
-- c_sdp_N_beamsets = 16 / 4 * 2 = 4 * 2 = 8 packets per sync interval
proc_sdp_rx_beamlet_octets(ext_clk,
- rx_beamlet_sosi,
- rx_beamlet_cnt,
- rx_beamlet_valid,
- rx_beamlet_arr_re,
- rx_beamlet_arr_im,
- rx_packet_list_re,
- rx_packet_list_im);
+ rx_beamlet_sosi,
+ rx_beamlet_cnt,
+ rx_beamlet_valid,
+ rx_beamlet_arr_re,
+ rx_beamlet_arr_im,
+ rx_packet_list_re,
+ rx_packet_list_im);
-- Undo the beamlet output transpose, to have original beamlet order
p_rx_reordered_list : process
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index 17d6d80420055ba503fdec77b55034b2de8d537c..683fc470418b2a094393f01c823bc1cb0deda05b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -39,20 +39,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf_bst_offload is
end tb_lofar2_unb2c_sdp_station_bf_bst_offload;
@@ -82,17 +82,17 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
-- header fields
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
- constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(3, 6), -- antenna_field_index
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- MM
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
@@ -173,44 +173,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -276,38 +276,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . Verify XST packet header
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
- snk_in_arr(0) => eth_rx_sosi,
+ snk_in_arr(0) => eth_rx_sosi,
- src_out_arr(0) => rx_offload_sosi,
+ src_out_arr(0) => rx_offload_sosi,
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
@@ -322,7 +322,7 @@ begin
0, -- not used for BST, subband_index
0, -- not used for BST, xst_signal_input_A
0, -- not used for BST, xst_signal_input_B
- 0); -- dp_bsn
+ 0); -- dp_bsn
p_verify_header : process(rx_offload_sosi)
variable v_bool : boolean;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
index b85519e4bd8305f112efcc0135334b271e4b60b7..34079fe34f04f26770b344e8b70ac0b80ba4f906 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_bf is
end tb_tb_lofar2_unb2c_sdp_station_bf;
@@ -37,24 +37,24 @@ architecture tb of tb_tb_lofar2_unb2c_sdp_station_bf is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
u_bf : entity work.tb_lofar2_unb2c_sdp_station_bf
- generic map (
- g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
- g_sp_ampl => 0.5, -- WG normalized amplitude
- g_sp_phase => -110.0, -- WG phase in degrees = subband phase
- g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
- g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
- g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
- g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
- g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
- g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
- g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
- g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
- g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
- g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
- );
+ generic map (
+ g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl => 0.5, -- WG normalized amplitude
+ g_sp_phase => -110.0, -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
+ g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet => c_sdp_S_sub_bf - 1, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
+ g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index 2292509910d6d2468f946f75ee0c52bb5cbb5a07..b48b46c7da07216f6c3c168bb91e0d5e388a3fef 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_bf is
generic (
@@ -83,7 +83,7 @@ entity lofar2_unb2c_sdp_station_bf is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -104,59 +104,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
index 18702afb27646b839fa7bcb523075e7799bd1366..09814e63ed0f9b01d54f0024b2cd53491aaeaca3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -138,26 +138,26 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, reorder_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station_pkg.all;
entity tb_lofar2_unb2c_sdp_station_bf_ring is
generic (
@@ -247,17 +247,17 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_exp_beamlet_index : natural := 0; -- depends on beamset bset * c_sdp_S_sub_bf
constant c_beamlet_index_mod : boolean := true;
- constant c_exp_sdp_info : t_sdp_info := (
- TO_UVEC(3, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ constant c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(3, 6), -- antenna_field_index
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
-- Expected transposed indices order by func_reorder_transpose_packet().
-- Yields same c_reorder_transpose_indices order as:
@@ -265,15 +265,15 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_nof_ch : natural := c_sdp_cep_nof_beamlets_per_packet * c_sdp_N_pol_bf;
constant c_reorder_transpose_indices : t_natural_arr(0 to c_nof_ch - 1) :=
func_reorder_transpose_indices(c_sdp_cep_nof_blocks_per_packet,
- c_sdp_cep_nof_beamlets_per_block,
- c_sdp_N_pol_bf);
+ c_sdp_cep_nof_beamlets_per_block,
+ c_sdp_N_pol_bf);
-- WG
constant c_bsn_start_wg : natural := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-- .ampl
constant c_wg_ampl : natural := natural(g_sp_ampl * real(c_sdp_FS_adc)); -- in number of lsb
constant c_wg_remnant_ampl : natural := natural(g_sp_remnant_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_exp_sp_power : real := real(c_wg_ampl**2) / 2.0;
+ constant c_exp_sp_power : real := real(c_wg_ampl ** 2) / 2.0;
constant c_exp_sp_ast : real := c_exp_sp_power * real(c_nof_clk_per_sync);
-- . phase
constant c_subband_freq : real := real(g_subband) / real(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
@@ -290,7 +290,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_subband_weight_phase : real := 0.0; -- use default unit subband weights
constant c_exp_subband_phase : real := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl ** 2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_remnant_subband_phase : real := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
@@ -317,26 +317,26 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- . Beamlet internal
constant c_nof_remnant : natural := g_nof_rn * c_sdp_S_pn - 1;
constant c_exp_beamlet_x_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase,
+ c_nof_remnant);
constant c_exp_beamlet_x_ampl : real := c_exp_beamlet_x_tuple(0);
constant c_exp_beamlet_x_phase : real := c_exp_beamlet_x_tuple(1);
constant c_exp_beamlet_x_re : real := c_exp_beamlet_x_tuple(2);
constant c_exp_beamlet_x_im : real := c_exp_beamlet_x_tuple(3);
constant c_exp_beamlet_y_tuple : t_real_arr(0 to 3) := func_sdp_beamformer(
- c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
- c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
- c_nof_remnant);
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase,
+ c_nof_remnant);
constant c_exp_beamlet_y_ampl : real := c_exp_beamlet_y_tuple(0);
constant c_exp_beamlet_y_phase : real := c_exp_beamlet_y_tuple(1);
constant c_exp_beamlet_y_re : real := c_exp_beamlet_y_tuple(2);
constant c_exp_beamlet_y_im : real := c_exp_beamlet_y_tuple(3);
-- . BST
- constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_x_power : real := c_exp_beamlet_x_ampl ** 2.0; -- complex signal ampl, so no divide by 2
constant c_exp_beamlet_x_bst : real := c_exp_beamlet_x_power * real(c_nof_block_per_sync);
- constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ constant c_exp_beamlet_y_power : real := c_exp_beamlet_y_ampl ** 2.0; -- complex signal ampl, so no divide by 2
constant c_exp_beamlet_y_bst : real := c_exp_beamlet_y_power * real(c_nof_block_per_sync);
-- . Beamlet output
constant c_exp_beamlet_x_output_ampl : real := c_exp_beamlet_x_ampl * g_beamlet_scale;
@@ -362,15 +362,15 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz);
-- . Address spans of a single MM instance
-- . c_sdp_S_pn = 12 instances
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
-- . c_sdp_N_beamsets = 2 instances
- constant c_mm_span_ram_ss_ss_wide : natural := 2**c_addr_w_ram_ss_ss_wide;
- constant c_mm_span_ram_bf_weights : natural := 2**c_addr_w_ram_bf_weights;
- constant c_mm_span_reg_bf_scale : natural := 2**c_addr_w_reg_bf_scale;
- constant c_mm_span_reg_hdr_dat : natural := 2**c_addr_w_reg_hdr_dat;
- constant c_mm_span_reg_stat_enable_bst : natural := 2**c_addr_w_reg_stat_enable_bst;
- constant c_mm_span_reg_dp_xonoff : natural := 2**c_addr_w_reg_dp_xonoff;
- constant c_mm_span_ram_st_bst : natural := 2**c_addr_w_ram_st_bst;
+ constant c_mm_span_ram_ss_ss_wide : natural := 2 ** c_addr_w_ram_ss_ss_wide;
+ constant c_mm_span_ram_bf_weights : natural := 2 ** c_addr_w_ram_bf_weights;
+ constant c_mm_span_reg_bf_scale : natural := 2 ** c_addr_w_reg_bf_scale;
+ constant c_mm_span_reg_hdr_dat : natural := 2 ** c_addr_w_reg_hdr_dat;
+ constant c_mm_span_reg_stat_enable_bst : natural := 2 ** c_addr_w_reg_stat_enable_bst;
+ constant c_mm_span_reg_dp_xonoff : natural := 2 ** c_addr_w_reg_dp_xonoff;
+ constant c_mm_span_ram_st_bst : natural := 2 ** c_addr_w_ram_st_bst;
-- Use c_mm_file_reg_* on c_last_gn for MM accesses to only last node in ring, e.g. for control beamlet output, read BSN, read back
-- Use mmf_unb_file_prefix() and range(g_nof_rn) for MM access loop to all nodes in ring, e.g. for control BSN source, BF weights
@@ -565,61 +565,61 @@ begin
------------------------------------------------------------------------------
gen_dut : for RN in 0 to c_last_rn generate
u_lofar_unb2c_sdp_station_bf : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => c_design_name,
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => (g_first_gn + RN) / c_quad,
- g_sim_node_nr => (g_first_gn + RN) mod c_quad,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => ( TO_UVEC((g_first_gn + RN) / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC((g_first_gn + RN) mod c_quad, c_unb2c_board_nof_chip_w) ),
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers for ring
- QSFP_0_RX => i_QSFP_0_RX(RN),
- QSFP_0_TX => i_QSFP_0_TX(RN),
-
- -- ring transceivers
- RING_0_RX => i_RING_0_RX(RN),
- RING_0_TX => i_RING_0_TX(RN),
- RING_1_RX => i_RING_1_RX(RN),
- RING_1_TX => i_RING_1_TX(RN),
-
- -- front transceivers for CEP
- QSFP_1_RX => i_QSFP_1_lpbk(RN),
- QSFP_1_TX => i_QSFP_1_lpbk(RN),
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => c_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => (g_first_gn + RN) / c_quad,
+ g_sim_node_nr => (g_first_gn + RN) mod c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC((g_first_gn + RN) / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC((g_first_gn + RN) mod c_quad, c_unb2c_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers for ring
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- front transceivers for CEP
+ QSFP_1_RX => i_QSFP_1_lpbk(RN),
+ QSFP_1_TX => i_QSFP_1_lpbk(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
end generate;
-- Ring connections
@@ -637,70 +637,70 @@ begin
-- CEP model
------------------------------------------------------------------------------
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => dest_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => true,
- g_sim_level => 1,
- g_nof_macs => 1,
- g_use_mdio => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM interface
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- -- DP interface
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0), -- Last RN must be used as end node.
-
- src_out_arr(0) => tr_10GbE_src_out,
- src_in_arr(0) => tr_10GbE_src_in
- );
+ generic map (
+ g_sim => true,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => i_QSFP_1_lpbk(c_last_rn)(0), -- Last RN must be used as end node.
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => dest_rst,
- mm_clk => tb_clk,
-
- dp_rst => dest_rst,
- dp_clk => ext_clk,
-
- reg_hdr_dat_mosi => rx_hdr_dat_mosi,
- reg_hdr_dat_miso => rx_hdr_dat_miso,
-
- snk_in_arr(0) => tr_10GbE_src_out,
- snk_out_arr(0) => tr_10GbE_src_in,
-
- src_out_arr(0) => rx_beamlet_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -969,13 +969,13 @@ begin
for S in 0 to c_sdp_S_pn - 1 loop
if v_gn * c_sdp_S_pn + S = g_global_sp then
-- Strong WG signal at g_global_sp
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
else
-- Weak WG signal on all other (remnant) SP
- mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 1, integer(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(mmf_unb_file_prefix(v_gn / c_quad, v_gn mod c_quad) & "REG_WG", S * 4 + 3, integer(real(c_wg_remnant_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -1152,8 +1152,8 @@ begin
----------------------------------------------------------------------------
-- read BSN low, this is the wait until condition
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0,
- "UNSIGNED", rd_data_bsn, ">=", c_stimuli_done_bsn,
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data_bsn, ">=", c_stimuli_done_bsn,
+ c_sdp_T_sub, tb_clk);
-- Stimuli done, now verify results at end of test
stimuli_done <= '1';
@@ -1397,7 +1397,7 @@ begin
exp_payload_error,
c_exp_beamlet_scale,
c_exp_beamlet_index,
- exp_dp_bsn);
+ exp_dp_bsn);
rx_sdp_cep_header <= func_sdp_map_cep_header(rx_hdr_fields_raw);
@@ -1445,8 +1445,8 @@ begin
-- in func_sdp_verify_cep_header().
if rx_beamlet_sosi.eop = '1' then
v_bool := func_sdp_verify_cep_header(rx_sdp_cep_header,
- exp_sdp_cep_header,
- c_beamlet_index_mod);
+ exp_sdp_cep_header,
+ c_beamlet_index_mod);
end if;
end process;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 10853a63baf3dd229888366c988e34cc04299429..41819e2537e5703d989a54a90b7d679ba0c2aa50 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams and FSUB
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_fsub is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_fsub is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index 7d739b0f82e19e68cee96ffde59911ff0b4aa33e..6e4e81c5d07c0adbc11c11f72fd4cf6f135981b6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -62,20 +62,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use lofar2_sdp_lib.tb_sdp_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use lofar2_sdp_lib.tb_sdp_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity tb_lofar2_unb2c_sdp_station_fsub is
generic (
@@ -127,8 +127,8 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-- .ampl
constant c_co_wg_ampl : natural := natural(g_co_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
constant c_cross_wg_ampl : natural := natural(g_cross_wg_ampl * real(c_sdp_FS_adc)); -- in number of lsb
- constant c_exp_co_sp_power : real := real(c_co_wg_ampl**2) / 2.0;
- constant c_exp_cross_sp_power : real := real(c_cross_wg_ampl**2) / 2.0;
+ constant c_exp_co_sp_power : real := real(c_co_wg_ampl ** 2) / 2.0;
+ constant c_exp_cross_sp_power : real := real(c_cross_wg_ampl ** 2) / 2.0;
constant c_exp_co_sp_ast : real := c_exp_co_sp_power * real(c_nof_clk_per_sync);
constant c_exp_cross_sp_ast : real := c_exp_cross_sp_power * real(c_nof_clk_per_sync);
-- . freq
@@ -153,14 +153,14 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
constant c_exp_co_subband_ampl_weighted : real := c_exp_co_subband_ampl_raw * g_co_subband_weight_gain;
constant c_exp_cross_subband_ampl_weighted : real := c_exp_cross_subband_ampl_raw * 1.0; -- unit gain, this is co gain for cross sp
constant c_exp_jones_subband_tuple : t_real_arr(0 to 3) := func_sdp_subband_equalizer(
- c_exp_co_subband_ampl_raw, c_co_subband_phase, g_co_subband_weight_gain, g_co_subband_weight_phase,
- c_exp_cross_subband_ampl_raw, c_cross_subband_phase, g_sp_cross_subband_weight_gain, g_sp_cross_subband_weight_phase);
+ c_exp_co_subband_ampl_raw, c_co_subband_phase, g_co_subband_weight_gain, g_co_subband_weight_phase,
+ c_exp_cross_subband_ampl_raw, c_cross_subband_phase, g_sp_cross_subband_weight_gain, g_sp_cross_subband_weight_phase);
constant c_exp_sp_subband_ampl_weighted : real := sel_a_b(g_use_cross_weight, c_exp_jones_subband_tuple(0), c_exp_co_subband_ampl_weighted);
- constant c_exp_co_subband_power_raw : real := c_exp_co_subband_ampl_raw**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
- constant c_exp_cross_subband_power_raw : real := c_exp_cross_subband_ampl_raw**2.0;
- constant c_exp_sp_subband_power_weighted : real := c_exp_sp_subband_ampl_weighted**2.0;
- constant c_exp_cross_subband_power_weighted : real := c_exp_cross_subband_ampl_weighted**2.0;
+ constant c_exp_co_subband_power_raw : real := c_exp_co_subband_ampl_raw ** 2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_cross_subband_power_raw : real := c_exp_cross_subband_ampl_raw ** 2.0;
+ constant c_exp_sp_subband_power_weighted : real := c_exp_sp_subband_ampl_weighted ** 2.0;
+ constant c_exp_cross_subband_power_weighted : real := c_exp_cross_subband_ampl_weighted ** 2.0;
constant c_exp_co_subband_sst_raw : real := c_exp_co_subband_power_raw * real(c_nof_block_per_sync);
constant c_exp_cross_subband_sst_raw : real := c_exp_cross_subband_power_raw * real(c_nof_block_per_sync);
constant c_exp_sp_subband_sst_weighted : real := c_exp_sp_subband_power_weighted * real(c_nof_block_per_sync);
@@ -186,7 +186,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-- . Address widths of a single MM instance
constant c_addr_w_reg_diag_wg : natural := 2;
-- . Address spans of a single MM instance
- constant c_mm_span_reg_diag_wg : natural := 2**c_addr_w_reg_diag_wg;
+ constant c_mm_span_reg_diag_wg : natural := 2 ** c_addr_w_reg_diag_wg;
constant c_mm_file_reg_bsn_source_v2 : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
constant c_mm_file_reg_bsn_scheduler_wg : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
@@ -281,45 +281,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_fsub : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => g_subband
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
-- Raw or weighted subbands
exp_sp_subband_ampl <= sel_a_b(sst_offload_weighted_subbands = '0', c_exp_co_subband_ampl_raw, c_exp_sp_subband_ampl_weighted);
@@ -373,7 +373,7 @@ begin
-- 3 : ampl[16:0]
-- g_sp is co-polarization
v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_co_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_co_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -381,7 +381,7 @@ begin
if g_use_cross_weight then
-- c_cross_sp is cross-polarization for g_sp, use same WG settings for c_cross_sp as for g_sp
v_offset := c_cross_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, integer(c_cross_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, integer(real(g_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, integer(real(c_cross_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -429,7 +429,7 @@ begin
sp_co_subband_weight_im <= v_im;
sp_co_subband_weight_gain <= COMPLEX_RADIUS(real(v_re), real(v_im)) / real(c_sdp_unit_sub_weight);
sp_co_subband_weight_phase <= COMPLEX_PHASE(real(v_re), real(v_im));
- proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(tb_clk, 1);
assert sp_co_subband_weight_re = c_co_subband_weight_re report "Readback sp_co_subband_weight_re /= c_co_subband_weight_re" severity ERROR;
assert sp_co_subband_weight_im = c_co_subband_weight_im report "Readback sp_co_subband_weight_im /= c_co_subband_weight_im" severity ERROR;
@@ -470,8 +470,8 @@ begin
-- Wait for enough WG data and start of sync interval
----------------------------------------------------------------------------
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read subband statistics
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
index 15dc0b787d0e20a7d0dff92dbeaadb648a837fe0..4b4bbffd086efe581ca71f96a59e0e292f81aaa0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
@@ -39,19 +39,19 @@
-- Takes about 1h 15 m
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2c_sdp_station_fsub_sst_offload;
@@ -154,44 +154,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_fsub : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_fsub",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -244,38 +244,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . Verify XST packet header
u_rx_statistics : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
-
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
-
- snk_in_arr(0) => eth_rx_sosi,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
+
+ snk_in_arr(0) => eth_rx_sosi,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
index 5ee8de349555ef55110c507da66066e4cebbe049..4f23552032672425fb1bb40cb9f1123d0df7ada0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_tb_lofar2_unb2c_sdp_station_fsub is
end tb_tb_lofar2_unb2c_sdp_station_fsub;
@@ -36,34 +36,34 @@ end tb_tb_lofar2_unb2c_sdp_station_fsub;
architecture tb of tb_tb_lofar2_unb2c_sdp_station_fsub is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- Commented to save sim time in regression test
--- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
--- GENERIC MAP (
--- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
--- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
--- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
--- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
--- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
--- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
--- g_use_cross_weight => FALSE,
--- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
--- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
--- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
--- );
+ -- Commented to save sim time in regression test
+ -- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
+ -- GENERIC MAP (
+ -- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ -- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ -- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ -- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ -- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ -- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ -- g_use_cross_weight => FALSE,
+ -- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ -- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ -- g_read_all_SST => TRUE -- when FALSE only read SST for g_subband, to save sim time
+ -- );
u_fsub_use_cross : entity work.tb_lofar2_unb2c_sdp_station_fsub
- generic map (
- g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
- g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
- g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
- g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
- g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
- g_use_cross_weight => true,
- g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
- g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
- g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
- );
+ generic map (
+ g_sp => 3, -- signal path index in range(S_pn = 12) of co-polarization
+ g_co_wg_ampl => 0.5, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_ampl => 0.4, -- WG normalized amplitude, use same WG settings for both polarizations (g_sp and c_cross_sp)
+ g_cross_wg_phase => 90.0, -- WG phase in degrees for cross-sp, relative to co-sp
+ g_subband => 102, -- select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_co_subband_weight_gain => 1.0, -- subband weight normalized gain, for co-polarization in g_sp
+ g_co_subband_weight_phase => 30.0, -- subband weight phase rotation in degrees, for co-polarization in g_sp
+ g_use_cross_weight => true,
+ g_sp_cross_subband_weight_gain => 0.5, -- subband weight normalized gain, for cross polarization of g_sp
+ g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
+ g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
+ );
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index f637461c321b7f1416fadff1251f8bba7facf813..c864334d9c109191e1199401cc8a6c43012b1791 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2c_sdp_station_full is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 9e7d7250d9cc32cdaaad1ae0a4d120d643c38ca4..f9cccf6220d3bcc4826491f7e06364e3f074dd66 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -26,13 +26,13 @@
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_full_wg is
generic (
@@ -87,51 +87,51 @@ end lofar2_unb2c_sdp_station_full_wg;
architecture str of lofar2_unb2c_sdp_station_full_wg is
begin
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index d210c368ad6efc98f279a3d97fe2809eb83f8294..3aa74325863ecfa9585422b6a6e7f837f8c9ec7c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_one is
generic (
@@ -66,7 +66,7 @@ entity lofar2_unb2c_sdp_station_xsub_one is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -87,43 +87,43 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- LEDs
- QSFP_LED => QSFP_LED,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index ae39ff5891c1972fcf7a040bd245d465d9095cbc..c031f32b34172105be3eb157b609d6fb2c2a10c4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -47,19 +47,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_xsub_one is
end tb_lofar2_unb2c_sdp_station_xsub_one;
@@ -95,7 +95,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
-- WPFB
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio;
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl ** 2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_subband_xst : real := c_exp_subband_sst; -- all signal inputs use same WG, and auto correlation XST = SST
@@ -165,45 +165,45 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_xsub_one : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
- g_scope_selected_subband => natural(c_subband_sp)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => natural(c_subband_sp)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -245,7 +245,7 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer((c_subband_sp + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -270,8 +270,8 @@ begin
-- Wait for enough WG data and start of sync interval
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
- c_sdp_T_sub, tb_clk);
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
-- Read crosslet statistics
@@ -311,47 +311,47 @@ begin
if v_C = 0 and v_A_even = 0 and v_B_even = 0 then
assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(0)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
- -- Check real values of odd indices
- if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check real values of even correlated with odd indices
- if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
- assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
- -- Check im values of even indices
- if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of odd indices
- if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check im values of even correlated with odd indices
- if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
- assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
-
- -- Check if values are > 0
- if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
-
- -- All XST values (almost) equal, because they use the same WG setting.
- -- therefore also verify the expected XST value for all XST.
- if I mod c_nof_complex = 0 then
- -- real part
- assert almost_equal(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, 1.0, c_max_ratio) report "Wrong XST real value at I = " & int_to_str(I) severity ERROR;
- else
- -- imag part
- assert almost_zero(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, c_max_ratio) report "Wrong XST imag value at I = " & int_to_str(I) severity ERROR;
- end if;
- end loop;
-
- ---------------------------------------------------------------------------
- -- End Simulation
- ---------------------------------------------------------------------------
- sim_done <= '1';
- proc_common_wait_some_cycles(ext_clk, 100);
- proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
- wait;
- end process;
-end tb;
+ -- Check real values of odd indices
+ if v_C = 0 and v_A_even = 1 and v_B_even = 1 then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex)) report "correlation between odd indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check real values of even correlated with odd indices
+ if v_C = 0 and (v_A_even = 0 xor v_B_even = 0) then
+ assert signed(xsub_stats_arr(I)) = signed(xsub_stats_arr(1 * c_nof_complex)) report "correlation between even indexed signals (re) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Using absolute value of the imaginary part (force positive) as the sign can be opposite when comparing A to B vs B to A.
+ -- Check im values of even indices
+ if v_C = 1 and v_A_even = 0 and v_B_even = 0 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1))) report "correlation between even indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of odd indices
+ if v_C = 1 and v_A_even = 1 and v_B_even = 1 then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr((c_sdp_S_pn + 1) * c_nof_complex + 1))) report "correlation between odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check im values of even correlated with odd indices
+ if v_C = 1 and (v_A_even = 0 xor v_B_even = 0) then
+ assert abs(signed(xsub_stats_arr(I))) = abs(signed(xsub_stats_arr(1 * c_nof_complex + 1))) report "correlation between even/odd indexed signals (im) is wrong at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- Check if values are > 0
+ if v_C = 0 then assert (signed(xsub_stats_arr(I)) > to_signed(0, c_longword_w)) report "correlation is 0 which is unexpected! at I = " & int_to_str(I) severity ERROR; end if;
+
+ -- All XST values (almost) equal, because they use the same WG setting.
+ -- therefore also verify the expected XST value for all XST.
+ if I mod c_nof_complex = 0 then
+ -- real part
+ assert almost_equal(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, 1.0, c_max_ratio) report "Wrong XST real value at I = " & int_to_str(I) severity ERROR;
+ else
+ -- imag part
+ assert almost_zero(TO_SREAL(xsub_stats_arr(I)) / c_exp_subband_xst, c_max_ratio) report "Wrong XST imag value at I = " & int_to_str(I) severity ERROR;
+ end if;
+ end loop;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
+ wait;
+ end process;
+ end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 657a3cebece3eccf10a661c3f3d048487d7d783a..869c5ea403addba2bfacdae966cd83514593c067 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -52,19 +52,19 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
generic (
@@ -108,7 +108,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
-- WPFB
constant c_exp_subband_ampl : real := real(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio; -- = c_wg_ampl * 0.994817 * 8
- constant c_exp_subband_power : real := c_exp_subband_ampl**2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
+ constant c_exp_subband_power : real := c_exp_subband_ampl ** 2.0; -- complex signal ampl, so power is A**2 (not A**2 / 2 as for real)
constant c_exp_subband_sst : real := c_exp_subband_power * real(c_nof_block_per_sync);
constant c_exp_subband_xst : real := c_exp_subband_sst; -- all signal inputs use same WG, and auto correlation XST = SST
@@ -205,44 +205,44 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2c_sdp_station_xsub_one : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_xsub_one",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
@@ -276,7 +276,7 @@ begin
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
for I in 0 to c_sdp_S_pn - 1 loop
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 1, integer(0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 2, integer(real(c_wg_subband) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, I * 4 + 3, integer(real(c_wg_ampl) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -360,38 +360,38 @@ begin
g_runtime_timeout => c_eth_runtime_timeout,
g_check_nof_valid => true,
g_check_nof_valid_ref => c_eth_check_nof_valid
- )
- port map (
- eth_serial_in => eth_txp(0),
- eth_src_out => eth_rx_sosi,
- tb_end => eth_done
- );
+ )
+ port map (
+ eth_serial_in => eth_txp(0),
+ eth_src_out => eth_rx_sosi,
+ tb_end => eth_done
+ );
eth_rx_data <= eth_rx_sosi.data(c_32 - 1 downto 0);
-- . View / verify XST packet header
u_rx_statistics : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => pps_rst,
- mm_clk => tb_clk,
-
- dp_rst => pps_rst,
- dp_clk => eth_clk(0),
-
- snk_in_arr(0) => eth_rx_sosi,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => pps_rst,
+ dp_clk => eth_clk(0),
+
+ snk_in_arr(0) => eth_rx_sosi,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
@@ -413,10 +413,10 @@ begin
case rx_word_cnt is
when 0 => rx_sdp_stat_data <= rx_offload_sosi.data(c_32 - 1 downto 0);
when 1 => rx_sdp_stat_re <= rx_sdp_stat_data & rx_offload_sosi.data(c_32 - 1 downto 0);
- rx_sdp_stat_re_val <= '1';
+ rx_sdp_stat_re_val <= '1';
when 2 => rx_sdp_stat_data <= rx_offload_sosi.data(c_32 - 1 downto 0);
when 3 => rx_sdp_stat_im <= rx_sdp_stat_data & rx_offload_sosi.data(c_32 - 1 downto 0);
- rx_sdp_stat_im_val <= '1';
+ rx_sdp_stat_im_val <= '1';
when others => null;
end case;
end if;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index 40b0196d31b2f7a8aed0ebb53653aa608a97bd41..4439251d764ca0fa33243171114e11c1b548873b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -26,13 +26,13 @@
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB with ring.
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity lofar2_unb2c_sdp_station_xsub_ring is
generic (
@@ -82,7 +82,7 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
- -- back transceivers (note only 12 are used in unb2c)
+ -- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -103,59 +103,59 @@ begin
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- front transceivers QSFP0 for Ring.
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
-
- -- front transceivers QSFP1 for 10GbE output to CEP.
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- -- LEDs
- QSFP_LED => QSFP_LED,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => jesd204b_sync_n_arr
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 18a8782ce0d6a3d9e0ebd512aefa68d9bdf7e76a..32e50081097e53505243ca859c7680f62f23c3f3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -27,20 +27,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.lofar2_unb2c_sdp_station_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.lofar2_unb2c_sdp_station_pkg.all;
+ use eth_lib.eth_pkg.all;
entity lofar2_unb2c_sdp_station is
generic (
@@ -96,9 +96,9 @@ entity lofar2_unb2c_sdp_station is
-- LEDs
QSFP_LED : out std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0) := (others => '0'); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -472,299 +472,299 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => false,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_eth_nof_udp_ports
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_copi,
- reg_remu_miso => reg_remu_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_copi,
- reg_dpmm_data_miso => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_copi,
- reg_mmdp_data_miso => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_copi,
- reg_epcs_miso => reg_epcs_cipo,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_copi,
- reg_wdi_miso => reg_wdi_cipo,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_copi,
- reg_unb_system_info_miso => reg_unb_system_info_cipo,
- rom_unb_system_info_mosi => rom_unb_system_info_copi,
- rom_unb_system_info_miso => rom_unb_system_info_cipo,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_copi,
- reg_ppsh_miso => reg_ppsh_cipo,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_copi,
- eth1g_tse_miso => eth1g_tse_cipo,
- eth1g_reg_mosi => eth1g_reg_copi,
- eth1g_reg_miso => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_copi,
- eth1g_ram_miso => eth1g_ram_cipo,
-
- -- eth1g UDP streaming
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- ram_scrap_mosi => ram_scrap_copi,
- ram_scrap_miso => ram_scrap_cipo,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2c_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => false,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- Can be external 200MHz, or PLL generated
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
+
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_lofar2_unb2c_sdp_station
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- mm interfaces for control
- reg_wdi_copi => reg_wdi_copi,
- reg_wdi_cipo => reg_wdi_cipo,
- reg_unb_system_info_copi => reg_unb_system_info_copi,
- reg_unb_system_info_cipo => reg_unb_system_info_cipo,
- rom_unb_system_info_copi => rom_unb_system_info_copi,
- rom_unb_system_info_cipo => rom_unb_system_info_cipo,
- reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
- reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
- reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
- reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
- reg_ppsh_copi => reg_ppsh_copi,
- reg_ppsh_cipo => reg_ppsh_cipo,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_copi => eth1g_tse_copi,
- eth1g_tse_cipo => eth1g_tse_cipo,
- eth1g_reg_copi => eth1g_reg_copi,
- eth1g_reg_cipo => eth1g_reg_cipo,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_copi => eth1g_ram_copi,
- eth1g_ram_cipo => eth1g_ram_cipo,
- reg_dpmm_data_copi => reg_dpmm_data_copi,
- reg_dpmm_data_cipo => reg_dpmm_data_cipo,
- reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
- reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
- reg_mmdp_data_copi => reg_mmdp_data_copi,
- reg_mmdp_data_cipo => reg_mmdp_data_cipo,
- reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
- reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
- reg_epcs_copi => reg_epcs_copi,
- reg_epcs_cipo => reg_epcs_cipo,
- reg_remu_copi => reg_remu_copi,
- reg_remu_cipo => reg_remu_cipo,
-
- -- mm buses for signal flow blocks
- -- Jesd ip status/control
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bdo_destinations_copi => reg_bdo_destinations_copi,
- reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
- ram_scrap_copi => ram_scrap_copi,
- ram_scrap_cipo => ram_scrap_cipo,
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- mm interfaces for control
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
+
+ -- mm buses for signal flow blocks
+ -- Jesd ip status/control
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
+ );
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -773,203 +773,203 @@ begin
-- sdp nodes
-----------------------------------------------------------------------------
u_sdp_station : entity lofar2_sdp_lib.sdp_station
- generic map (
- g_sim => g_sim,
- g_wpfb => g_wpfb,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_scope_selected_subband => g_scope_selected_subband,
- g_no_jesd => c_revision_select.no_jesd,
- g_use_fsub => c_revision_select.use_fsub,
- g_use_oversample => c_revision_select.use_oversample,
- g_use_xsub => c_revision_select.use_xsub,
- g_use_bf => c_revision_select.use_bf,
- g_use_bdo_transpose => c_revision_select.use_bdo_transpose,
- g_nof_bdo_destinations_max => c_revision_select.nof_bdo_destinations_max,
- g_use_ring => c_revision_select.use_ring,
- g_P_sq => c_revision_select.P_sq
- )
- port map (
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_pps => dp_pps,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- gn_id => gn_id,
- this_bck_id => this_bck_id,
- this_chip_id => this_chip_id,
-
- SA_CLK => SA_CLK,
-
- -- jesd204b
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC_N => JESD204B_SYNC_N,
-
- -- UDP Offload
- udp_tx_sosi_arr => udp_tx_sosi_arr,
- udp_tx_siso_arr => udp_tx_siso_arr,
-
- -- 10 GbE
- reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
- reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
- reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
- reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-
- -- AIT
- jesd204b_copi => jesd204b_copi,
- jesd204b_cipo => jesd204b_cipo,
- jesd_ctrl_copi => jesd_ctrl_copi,
- jesd_ctrl_cipo => jesd_ctrl_cipo,
- reg_dp_shiftram_copi => reg_dp_shiftram_copi,
- reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
- reg_wg_copi => reg_wg_copi,
- reg_wg_cipo => reg_wg_cipo,
- ram_wg_copi => ram_wg_copi,
- ram_wg_cipo => ram_wg_cipo,
- reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_copi => ram_st_histogram_copi,
- ram_st_histogram_cipo => ram_st_histogram_cipo,
- reg_aduh_monitor_copi => reg_aduh_monitor_copi,
- reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-
- -- FSUB
- ram_st_sst_copi => ram_st_sst_copi,
- ram_st_sst_cipo => ram_st_sst_cipo,
- reg_si_copi => reg_si_copi,
- reg_si_cipo => reg_si_cipo,
- ram_fil_coefs_copi => ram_fil_coefs_copi,
- ram_fil_coefs_cipo => ram_fil_coefs_cipo,
- ram_equalizer_gains_copi => ram_equalizer_gains_copi,
- ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
- ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
- ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
- reg_dp_selector_copi => reg_dp_selector_copi,
- reg_dp_selector_cipo => reg_dp_selector_cipo,
-
- -- SDP Info
- reg_sdp_info_copi => reg_sdp_info_copi,
- reg_sdp_info_cipo => reg_sdp_info_cipo,
-
- -- RING Info
- reg_ring_info_copi => reg_ring_info_copi,
- reg_ring_info_cipo => reg_ring_info_cipo,
-
- -- XSUB
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- -- BF
- ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
- ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
- ram_bf_weights_copi => ram_bf_weights_copi,
- ram_bf_weights_cipo => ram_bf_weights_cipo,
- reg_bf_scale_copi => reg_bf_scale_copi,
- reg_bf_scale_cipo => reg_bf_scale_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bdo_destinations_copi => reg_bdo_destinations_copi,
- reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
- reg_dp_xonoff_copi => reg_dp_xonoff_copi,
- reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
- ram_st_bst_copi => ram_st_bst_copi,
- ram_st_bst_cipo => ram_st_bst_cipo,
- reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
- reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
- reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
- reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
- reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
- reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
- reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
- reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
- reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
- reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
- reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
-
- -- SST
- reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
- reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
- reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
- reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- -- XST
- reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
- reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
- reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
- reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
- reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
- -- BST
- reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
- reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
- reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
- reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- RING_0_TX => RING_0_TX,
- RING_0_RX => RING_0_RX,
- RING_1_TX => RING_1_TX,
- RING_1_RX => RING_1_RX,
-
- -- QSFP serial
- unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- -- QSFP LEDS
- unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_wpfb => g_wpfb,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
+ g_use_fsub => c_revision_select.use_fsub,
+ g_use_oversample => c_revision_select.use_oversample,
+ g_use_xsub => c_revision_select.use_xsub,
+ g_use_bf => c_revision_select.use_bf,
+ g_use_bdo_transpose => c_revision_select.use_bdo_transpose,
+ g_nof_bdo_destinations_max => c_revision_select.nof_bdo_destinations_max,
+ g_use_ring => c_revision_select.use_ring,
+ g_P_sq => c_revision_select.P_sq
+ )
+ port map (
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_pps => dp_pps,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ gn_id => gn_id,
+ this_bck_id => this_bck_id,
+ this_chip_id => this_chip_id,
+
+ SA_CLK => SA_CLK,
+
+ -- jesd204b
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N,
+
+ -- UDP Offload
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
+ -- 10 GbE
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+
+ -- AIT
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+
+ -- FSUB
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ ram_equalizer_gains_cross_copi => ram_equalizer_gains_cross_copi,
+ ram_equalizer_gains_cross_cipo => ram_equalizer_gains_cross_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+
+ -- SDP Info
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
+
+ -- RING Info
+ reg_ring_info_copi => reg_ring_info_copi,
+ reg_ring_info_cipo => reg_ring_info_cipo,
+
+ -- XSUB
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ -- BF
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi,
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
+ -- SST
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ -- XST
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_xst_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_xst_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_xst_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_xst_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_xst_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_xst_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_xst_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+ reg_tr_10GbE_mac_copi => reg_tr_10GbE_mac_copi,
+ reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
+ reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
+ reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
+
+ -- BST
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ RING_0_TX => RING_0_TX,
+ RING_0_RX => RING_0_RX,
+ RING_1_TX => RING_1_TX,
+ RING_1_RX => RING_1_RX,
+
+ -- QSFP serial
+ unb2_board_front_io_serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ unb2_board_front_io_serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ -- QSFP LEDS
+ unb2_board_qsfp_leds_tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ unb2_board_qsfp_leds_tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ unb2_board_qsfp_leds_rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Interface : 10GbE
@@ -983,40 +983,40 @@ begin
-- Front IO
------------
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
------------
-- LEDs
------------
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
-
- tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
- tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
- rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 6f3810e7995a00ec291322808662b30ce927f178..570276ece39e0cd1b25799b1f1f58030ba3c5101 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -20,45 +20,44 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_sdp_station_pkg is
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
type t_lofar2_unb2c_sdp_station_config is record
no_jesd : boolean;
- use_fsub : boolean;
- use_oversample : boolean;
- use_bf : boolean;
- use_bdo_transpose : boolean;
- nof_bdo_destinations_max : natural; -- <= c_sdp_bdo_mm_nof_destinations_max
- use_xsub : boolean;
- use_ring : boolean;
- P_sq : natural;
- end record;
-
- constant c_ait : t_lofar2_unb2c_sdp_station_config := (false, false, false, false, false, 1, false, false, 0);
- constant c_fsub : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, false, false, 0);
- -- use c_bf on one node also to simulate bdo transpose
- -- use c_bf_ring with ring also to simulate bdo identity
- constant c_bf : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, false, false, 0);
- constant c_bf_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, false, 1, false, true, 0);
- constant c_xsub_one : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
- constant c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
- constant c_full_wg : t_lofar2_unb2c_sdp_station_config := (true, true, false, true, true, 1, true, true, 9);
- -- Use c_full for LOFAR2 Station SDP operations
- constant c_full : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, true, true, 9);
- constant c_full_wg_os : t_lofar2_unb2c_sdp_station_config := (true, true, true, true, true, 1, true, true, 9);
- constant c_full_os : t_lofar2_unb2c_sdp_station_config := (false, true, true, true, true, 1, true, true, 9);
+ use_fsub : boolean;
+ use_oversample : boolean;
+ use_bf : boolean;
+ use_bdo_transpose : boolean;
+nof_bdo_destinations_max : natural; -- <= c_sdp_bdo_mm_nof_destinations_max
+ use_xsub : boolean;
+ use_ring : boolean;
+P_sq : natural;
+end record;
- -- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config;
+constant c_ait : t_lofar2_unb2c_sdp_station_config := (false, false, false, false, false, 1, false, false, 0);
+constant c_fsub : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, false, false, 0);
+-- use c_bf on one node also to simulate bdo transpose
+-- use c_bf_ring with ring also to simulate bdo identity
+constant c_bf : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, false, false, 0);
+constant c_bf_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, false, 1, false, true, 0);
+constant c_xsub_one : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, false, 1);
+constant c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (false, true, false, false, false, 1, true, true, 9);
+constant c_full_wg : t_lofar2_unb2c_sdp_station_config := (true, true, false, true, true, 1, true, true, 9);
+-- Use c_full for LOFAR2 Station SDP operations
+constant c_full : t_lofar2_unb2c_sdp_station_config := (false, true, false, true, true, 32, true, true, 9);
+constant c_full_wg_os : t_lofar2_unb2c_sdp_station_config := (true, true, true, true, true, 1, true, true, 9);
+constant c_full_os : t_lofar2_unb2c_sdp_station_config := (false, true, true, true, true, 1, true, true, 9);
+-- Function to select the revision configuration.
+function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config;
end lofar2_unb2c_sdp_station_pkg;
package body lofar2_unb2c_sdp_station_pkg is
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index e7071c6a168d77c91dc93177246f5a8974e43bb2..75a2980123805969219a034dc90d65dfc4802068 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -19,16 +19,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_lofar2_unb2c_sdp_station_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
entity mmm_lofar2_unb2c_sdp_station is
generic (
@@ -143,191 +143,191 @@ entity mmm_lofar2_unb2c_sdp_station is
reg_si_copi : out t_mem_copi;
reg_si_cipo : in t_mem_cipo;
- -- Equalizer gains
- ram_equalizer_gains_copi : out t_mem_copi;
- ram_equalizer_gains_cipo : in t_mem_cipo;
- ram_equalizer_gains_cross_copi : out t_mem_copi;
- ram_equalizer_gains_cross_cipo : in t_mem_cipo;
-
- -- DP Selector
- reg_dp_selector_copi : out t_mem_copi;
- reg_dp_selector_cipo : in t_mem_cipo;
-
- -- SDP Info
- reg_sdp_info_copi : out t_mem_copi;
- reg_sdp_info_cipo : in t_mem_cipo;
-
- -- RING Info
- reg_ring_info_copi : out t_mem_copi;
- reg_ring_info_cipo : in t_mem_cipo;
-
- -- Beamlet Subband Select
- ram_ss_ss_wide_copi : out t_mem_copi;
- ram_ss_ss_wide_cipo : in t_mem_cipo;
-
- -- Local BF bf weights
- ram_bf_weights_copi : out t_mem_copi;
- ram_bf_weights_cipo : in t_mem_cipo;
-
- -- BF bsn aligner_v2
- reg_bsn_align_v2_bf_copi : out t_mem_copi;
- reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
-
- -- BF bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
-
- -- mms_dp_scale Scale Beamlets
- reg_bf_scale_copi : out t_mem_copi;
- reg_bf_scale_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output (BDO) header fields
- -- . single destination, used when revision.nof_bdo_destinations_max = 1
- reg_hdr_dat_copi : out t_mem_copi;
- reg_hdr_dat_cipo : in t_mem_cipo;
- -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
- reg_bdo_destinations_copi : out t_mem_copi;
- reg_bdo_destinations_cipo : in t_mem_cipo;
-
- -- Beamlet Data Output xonoff
- reg_dp_xonoff_copi : out t_mem_copi;
- reg_dp_xonoff_cipo : in t_mem_cipo;
-
- -- BF ring lane info
- reg_ring_lane_info_bf_copi : out t_mem_copi;
- reg_ring_lane_info_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
-
- -- BF ring validate err
- reg_dp_block_validate_err_bf_copi : out t_mem_copi;
- reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
-
- -- BF ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics (BST)
- ram_st_bst_copi : out t_mem_copi;
- ram_st_bst_cipo : in t_mem_cipo;
-
- -- Subband Statistics offload
- reg_stat_enable_sst_copi : out t_mem_copi;
- reg_stat_enable_sst_cipo : in t_mem_cipo;
-
- -- Statistics header info
- reg_stat_hdr_dat_sst_copi : out t_mem_copi;
- reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics offload
- reg_stat_enable_xst_copi : out t_mem_copi;
- reg_stat_enable_xst_cipo : in t_mem_cipo;
-
- -- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_copi : out t_mem_copi;
- reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics offload
- reg_stat_enable_bst_copi : out t_mem_copi;
- reg_stat_enable_bst_cipo : in t_mem_cipo;
-
- -- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_copi : out t_mem_copi;
- reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_crosslets_info_copi : out t_mem_copi;
- reg_crosslets_info_cipo : in t_mem_cipo;
-
- -- crosslets_info
- reg_nof_crosslets_copi : out t_mem_copi;
- reg_nof_crosslets_cipo : in t_mem_cipo;
-
- -- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
- reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
-
- -- st_xsq (XST)
- ram_st_xsq_copi : out t_mem_copi;
- ram_st_xsq_cipo : in t_mem_cipo;
-
- -- 10 GbE mac
- reg_nw_10GbE_mac_copi : out t_mem_copi;
- reg_nw_10GbE_mac_cipo : in t_mem_cipo;
-
- -- 10 GbE eth
- reg_nw_10GbE_eth10g_copi : out t_mem_copi;
- reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2
- reg_bsn_align_v2_xsub_copi : out t_mem_copi;
- reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
-
- -- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
- reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
- reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
-
- -- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
-
- -- BST UDP offload bsn monitor
- reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
-
- -- Beamlet output bsn monitor
- reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
- reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
-
- -- SST UDP offload bsn monitor
- reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
- reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
-
- -- XST ring lane info
- reg_ring_lane_info_xst_copi : out t_mem_copi;
- reg_ring_lane_info_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
-
- -- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
-
- -- XST ring validate err
- reg_dp_block_validate_err_xst_copi : out t_mem_copi;
- reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
-
- -- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
-
- -- XST ring MAC
- reg_tr_10GbE_mac_copi : out t_mem_copi;
- reg_tr_10GbE_mac_cipo : in t_mem_cipo;
-
- -- XST ring ETH
- reg_tr_10GbE_eth10g_copi : out t_mem_copi;
- reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
-
- -- Scrap ram
- ram_scrap_copi : out t_mem_copi;
- ram_scrap_cipo : in t_mem_cipo;
-
- -- Jesd reset control
- jesd_ctrl_copi : out t_mem_copi;
- jesd_ctrl_cipo : in t_mem_cipo
+ -- Equalizer gains
+ ram_equalizer_gains_copi : out t_mem_copi;
+ ram_equalizer_gains_cipo : in t_mem_cipo;
+ ram_equalizer_gains_cross_copi : out t_mem_copi;
+ ram_equalizer_gains_cross_cipo : in t_mem_cipo;
+
+ -- DP Selector
+ reg_dp_selector_copi : out t_mem_copi;
+ reg_dp_selector_cipo : in t_mem_cipo;
+
+ -- SDP Info
+ reg_sdp_info_copi : out t_mem_copi;
+ reg_sdp_info_cipo : in t_mem_cipo;
+
+ -- RING Info
+ reg_ring_info_copi : out t_mem_copi;
+ reg_ring_info_cipo : in t_mem_cipo;
+
+ -- Beamlet Subband Select
+ ram_ss_ss_wide_copi : out t_mem_copi;
+ ram_ss_ss_wide_cipo : in t_mem_cipo;
+
+ -- Local BF bf weights
+ ram_bf_weights_copi : out t_mem_copi;
+ ram_bf_weights_cipo : in t_mem_cipo;
+
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : out t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : in t_mem_cipo;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : in t_mem_cipo;
+
+ -- mms_dp_scale Scale Beamlets
+ reg_bf_scale_copi : out t_mem_copi;
+ reg_bf_scale_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output (BDO) header fields
+ -- . single destination, used when revision.nof_bdo_destinations_max = 1
+ reg_hdr_dat_copi : out t_mem_copi;
+ reg_hdr_dat_cipo : in t_mem_cipo;
+ -- . multiple destinations, used when revision.nof_bdo_destinations_max > 1
+ reg_bdo_destinations_copi : out t_mem_copi;
+ reg_bdo_destinations_cipo : in t_mem_cipo;
+
+ -- Beamlet Data Output xonoff
+ reg_dp_xonoff_copi : out t_mem_copi;
+ reg_dp_xonoff_cipo : in t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : out t_mem_copi;
+ reg_ring_lane_info_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : in t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : in t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics (BST)
+ ram_st_bst_copi : out t_mem_copi;
+ ram_st_bst_cipo : in t_mem_cipo;
+
+ -- Subband Statistics offload
+ reg_stat_enable_sst_copi : out t_mem_copi;
+ reg_stat_enable_sst_cipo : in t_mem_cipo;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics offload
+ reg_stat_enable_xst_copi : out t_mem_copi;
+ reg_stat_enable_xst_cipo : in t_mem_cipo;
+
+ -- Crosslet Statistics header info
+ reg_stat_hdr_dat_xst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics offload
+ reg_stat_enable_bst_copi : out t_mem_copi;
+ reg_stat_enable_bst_cipo : in t_mem_cipo;
+
+ -- Beamlet Statistics header info
+ reg_stat_hdr_dat_bst_copi : out t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_crosslets_info_copi : out t_mem_copi;
+ reg_crosslets_info_cipo : in t_mem_cipo;
+
+ -- crosslets_info
+ reg_nof_crosslets_copi : out t_mem_copi;
+ reg_nof_crosslets_cipo : in t_mem_cipo;
+
+ -- bsn_sync_scheduler_xsub
+ reg_bsn_sync_scheduler_xsub_copi : out t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : in t_mem_cipo;
+
+ -- st_xsq (XST)
+ ram_st_xsq_copi : out t_mem_copi;
+ ram_st_xsq_cipo : in t_mem_cipo;
+
+ -- 10 GbE mac
+ reg_nw_10GbE_mac_copi : out t_mem_copi;
+ reg_nw_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- 10 GbE eth
+ reg_nw_10GbE_eth10g_copi : out t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2
+ reg_bsn_align_v2_xsub_copi : out t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : in t_mem_cipo;
+
+ -- XST bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : in t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : in t_mem_cipo;
+
+ -- XST UDP offload bsn monitor
+ reg_bsn_monitor_v2_xst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : in t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : in t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : in t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : in t_mem_cipo;
+
+ -- XST ring lane info
+ reg_ring_lane_info_xst_copi : out t_mem_copi;
+ reg_ring_lane_info_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_xst_copi: out t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: in t_mem_cipo;
+
+ -- XST ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_xst_copi : out t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : in t_mem_cipo;
+
+ -- XST ring validate err
+ reg_dp_block_validate_err_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : in t_mem_cipo;
+
+ -- XST ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_xst_copi : out t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : in t_mem_cipo;
+
+ -- XST ring MAC
+ reg_tr_10GbE_mac_copi : out t_mem_copi;
+ reg_tr_10GbE_mac_cipo : in t_mem_cipo;
+
+ -- XST ring ETH
+ reg_tr_10GbE_eth10g_copi : out t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : in t_mem_cipo;
+
+ -- Scrap ram
+ ram_scrap_copi : out t_mem_copi;
+ ram_scrap_cipo : in t_mem_cipo;
+
+ -- Jesd reset control
+ jesd_ctrl_copi : out t_mem_copi;
+ jesd_ctrl_cipo : in t_mem_cipo
);
end mmm_lofar2_unb2c_sdp_station;
@@ -341,211 +341,284 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
-- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
- u_mm_file_jesd204b : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
- port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_jesd204b : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
+ port map(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+
+ u_mm_file_pio_jesd_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
+ u_mm_file_reg_dp_shiftram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+
+ u_mm_file_reg_bsn_source_v2 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
- u_mm_file_pio_jesd_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
- port map(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+ u_mm_file_reg_bsn_scheduler : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
- u_mm_file_reg_dp_shiftram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- port map(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
+ u_mm_file_reg_bsn_monitor_input : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
- u_mm_file_reg_bsn_source_v2 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- port map(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
+ u_mm_file_reg_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_reg_bsn_scheduler : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- port map(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
+ u_mm_file_ram_wg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
- u_mm_file_reg_bsn_monitor_input : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- port map(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
- u_mm_file_ram_wg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- port map(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
- u_mm_file_ram_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
- u_mm_file_reg_diag_data_buf_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- port map(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
+ u_mm_file_ram_st_histogram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
+ port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
- u_mm_file_ram_st_histogram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- port map(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
+ u_mm_file_reg_aduh_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
- u_mm_file_reg_aduh_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- port map(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
+ u_mm_file_ram_st_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
- u_mm_file_ram_st_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- port map(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
+ u_mm_file_ram_fil_coefs : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
- u_mm_file_ram_fil_coefs : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- port map(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
+ u_mm_file_reg_si : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
- u_mm_file_reg_si : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- port map(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
+ u_mm_file_ram_equalizer_gains : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
- u_mm_file_ram_equalizer_gains_cross : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
- port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
+ u_mm_file_ram_equalizer_gains_cross : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS_CROSS")
+ port map(mm_rst, mm_clk, ram_equalizer_gains_cross_copi, ram_equalizer_gains_cross_cipo );
- u_mm_file_reg_dp_selector : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
+ u_mm_file_reg_dp_selector : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ port map(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
- u_mm_file_reg_ring_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
- port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
+ u_mm_file_reg_ring_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
+ port map(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
- u_mm_file_ram_ss_ss_wide : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
+ u_mm_file_ram_ss_ss_wide : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
- u_mm_file_ram_bf_weights : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
+ u_mm_file_ram_bf_weights : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ port map(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
- u_mm_file_reg_bf_scale : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
+ u_mm_file_reg_bf_scale : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ port map(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
- u_mm_file_reg_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
+ u_mm_file_reg_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
- u_mm_file_reg_bdo_destinations : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
- port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
+ u_mm_file_reg_bdo_destinations : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BDO_DESTINATIONS")
+ port map(mm_rst, mm_clk, reg_bdo_destinations_copi, reg_bdo_destinations_cipo );
- u_mm_file_reg_dp_xonoff : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
+ u_mm_file_reg_dp_xonoff : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
- u_mm_file_ram_st_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
+ u_mm_file_ram_st_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ port map(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
- u_mm_file_reg_stat_enable_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
+ u_mm_file_reg_stat_enable_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
+ port map(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
- u_mm_file_reg_stat_hdr_info_sst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
+ u_mm_file_reg_stat_hdr_info_sst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
- u_mm_file_reg_stat_enable_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
+ u_mm_file_reg_stat_enable_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
+ port map(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
- u_mm_file_reg_stat_hdr_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
+ u_mm_file_reg_stat_hdr_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
- u_mm_file_reg_stat_enable_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
+ u_mm_file_reg_stat_enable_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
+ port map(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
- u_mm_file_reg_stat_hdr_info_bst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
+ u_mm_file_reg_stat_hdr_info_bst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
+ port map(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
- u_mm_file_reg_crosslets_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
+ u_mm_file_reg_crosslets_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
+ port map(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
- u_mm_file_reg_nof_crosslets : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
+ u_mm_file_reg_nof_crosslets : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
+ port map(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
- u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
+ u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
- u_mm_file_ram_st_xsq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
+ u_mm_file_ram_st_xsq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
+ port map(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
- u_mm_file_reg_nw_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
+ u_mm_file_reg_nw_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
- u_mm_file_reg_nw_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
- u_mm_file_reg_bsn_align_v2_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
+ u_mm_file_reg_bsn_align_v2_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
- u_mm_file_reg_ring_lane_info_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
- port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
+ u_mm_file_reg_ring_lane_info_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
- u_mm_file_reg_dp_block_validate_err_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
- u_mm_file_reg_bsn_align_v2_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
- u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
- u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
- u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ u_mm_file_reg_ring_lane_info_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ port map(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
- u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_XST")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_xst_copi, reg_bsn_monitor_v2_ring_tx_xst_cipo );
- u_mm_file_reg_dp_block_validate_err_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
+ u_mm_file_reg_dp_block_validate_err_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_err_xst_copi, reg_dp_block_validate_err_xst_cipo );
- u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
- port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_xst : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST")
+ port map(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_xst_copi, reg_dp_block_validate_bsn_at_sync_xst_cipo );
- u_mm_file_reg_tr_10GbE_mac : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
- port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
+ u_mm_file_reg_tr_10GbE_mac : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_MAC")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mac_copi, reg_tr_10GbE_mac_cipo );
- u_mm_file_reg_tr_10GbE_eth10g : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
- port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
+ u_mm_file_reg_tr_10GbE_eth10g : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_ETH10G")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -605,8 +678,8 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ -- ToDo: This has changed in the peripherals package
+ -- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
rom_system_info_write_export => rom_unb_system_info_copi.wr,
rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index dbc0101b0999e750773f652e91c5f5be62300636..fdce431c576f29238ab2030bf5ed34d6bbf3042d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -19,554 +19,554 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_sdp_station_pkg is
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
- component qsys_lofar2_unb2c_sdp_station is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_cross_reset_export : out std_logic; -- export
- ram_equalizer_gains_cross_clk_export : out std_logic; -- export
- ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
- ram_equalizer_gains_cross_write_export : out std_logic; -- export
- ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_cross_read_export : out std_logic; -- export
- ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
- reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
- reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_align_v2_bf_write_export : out std_logic; -- export
- reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_bf_read_export : out std_logic; -- export
- reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
- reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
- reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_bf_reset_export : out std_logic; -- export
- reg_ring_lane_info_bf_clk_export : out std_logic; -- export
- reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_lane_info_bf_write_export : out std_logic; -- export
- reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_bf_read_export : out std_logic; -- export
- reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bdo_destinations_reset_export : out std_logic; -- export
- reg_bdo_destinations_clk_export : out std_logic; -- export
- reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
- reg_bdo_destinations_write_export : out std_logic; -- export
- reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bdo_destinations_read_export : out std_logic; -- export
- reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_lofar2_unb2c_sdp_station;
+ component qsys_lofar2_unb2c_sdp_station is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_cross_reset_export : out std_logic; -- export
+ ram_equalizer_gains_cross_clk_export : out std_logic; -- export
+ ram_equalizer_gains_cross_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_equalizer_gains_cross_write_export : out std_logic; -- export
+ ram_equalizer_gains_cross_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_cross_read_export : out std_logic; -- export
+ ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_reset_export : out std_logic; -- export
+ reg_bdo_destinations_clk_export : out std_logic; -- export
+ reg_bdo_destinations_address_export : out std_logic_vector(8 downto 0); -- export
+ reg_bdo_destinations_write_export : out std_logic; -- export
+ reg_bdo_destinations_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bdo_destinations_read_export : out std_logic; -- export
+ reg_bdo_destinations_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_lofar2_unb2c_sdp_station;
end qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 8bdf7bca758f73305d94c939022399788dfe337d..c43be71c8755b8399416b8ff05b216af3539c4f2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -31,20 +31,20 @@
-- c_eth_check_nof_packets = 1 instead of S_pn = 12.
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_lofar2_unb2c_sdp_station is
end tb_lofar2_unb2c_sdp_station;
@@ -69,7 +69,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station is
-- WG
constant c_bsn_start_wg : natural := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- constant c_ampl_sp_0 : natural := 2**(c_sdp_W_adc - 1) / 2; -- in number of lsb
+ constant c_ampl_sp_0 : natural := 2 ** (c_sdp_W_adc - 1) / 2; -- in number of lsb
constant c_subband_sp_0 : real := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
-- 1GbE output
@@ -135,44 +135,44 @@ begin
-- >> DUT <<
u_lofar_unb2c_sdp_station : entity work.lofar2_unb2c_sdp_station
- generic map (
- g_design_name => "lofar2_unb2c_sdp_station_bf",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_wpfb => c_wpfb_sim,
- g_scope_selected_subband => natural(c_subband_sp_0)
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk_slv,
- ETH_SGIN => eth_rxp_slv,
- ETH_SGOUT => eth_txp_slv,
-
- -- LEDs
- QSFP_LED => open,
-
- -- back transceivers
- JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
- JESD204B_REFCLK => JESD204B_REFCLK,
-
- -- jesd204b syncronization signals
- JESD204B_SYSREF => jesd204b_sysref,
- JESD204B_SYNC_N => jesd204b_sync_n
- );
+ generic map (
+ g_design_name => "lofar2_unb2c_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => natural(c_subband_sp_0)
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk_slv,
+ ETH_SGIN => eth_rxp_slv,
+ ETH_SGOUT => eth_txp_slv,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
---------------------------------------------------------------------------------------------------------------------
-- Stimuli
@@ -199,7 +199,7 @@ begin
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2 ** 16 + 1, tb_clk); -- nof_samples, mode calc
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, integer( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, integer(c_subband_sp_0 * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, integer(real(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
@@ -232,12 +232,12 @@ begin
-- >> Verify proper DUT output using Ethernet packet statistics <<
u_eth_statistics : entity eth_lib.eth_statistics
- generic map (
- g_runtime_nof_packets => c_eth_check_nof_packets,
- g_runtime_timeout => c_eth_runtime_timeout
- )
- port map (
- eth_serial_in => eth_txp_slv(0),
- tb_end => eth_done
- );
+ generic map (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout
+ )
+ port map (
+ eth_serial_in => eth_txp_slv(0),
+ tb_end => eth_done
+ );
end tb;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
index c784b9032b3cddb878ec4eb192b2d5252c0787ed..8934524d6f0b079aa65635bc1514ccc898df567d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
generic (
@@ -99,31 +99,31 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping signals
- filled_mem : std_logic;
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping signals
+ filled_mem : std_logic;
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', '0', '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
@@ -136,239 +136,238 @@ begin
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, wr_fifo_usedw, stop_in)
-
variable v : t_reg := c_t_reg_init;
begin
v := q_reg;
v.wr_sosi := inp_sosi;
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.wr_sosi.valid := '1';
-
- if rst = '0' then
- v.state := STOP_READING;
- end if;
-
- when STOP_READING =>
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '0';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
- when WAIT_FOR_SOP =>
- v.dvr_mosi.burstbegin := '0';
- v.rst_ddrctrl_input := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '1';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
- when WRITING =>
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ when RESET =>
+ v := c_t_reg_init;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ v.wr_sosi.valid := '1';
+
+ if rst = '0' then
+ v.state := STOP_READING;
+ end if;
+
+ when STOP_READING =>
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '0';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ when WAIT_FOR_SOP =>
+ v.dvr_mosi.burstbegin := '0';
+ v.rst_ddrctrl_input := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '1';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if inp_adr >= c_pof_ma then
- v.filled_mem := '1';
- end if
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
- when SET_STOP =>
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ when WRITING =>
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
- when STOP_WRITING =>
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if inp_adr >= c_pof_ma then
+ v.filled_mem := '1';
+ end if
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' and v.filled_mem = '1' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ end if;
+
+ when SET_STOP =>
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
- v.state := LAST_WRITE_BURST;
- end if;
-
- when LAST_WRITE_BURST =>
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- if dvr_miso.done = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- when START_READING =>
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
- v.rd_burst_en := '0';
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
- when READING =>
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+ v.ready_for_set_stop := '0';
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w - 1 downto 0)) - TO_UINT(v.last_adr_to_write_to) + 1;
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.dvr_mosi.burstbegin := '0';
end if;
- else
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ else
+ v.state := WRITING;
+ end if;
+
+ when STOP_WRITING =>
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 then
+ v.state := LAST_WRITE_BURST;
+ end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ when LAST_WRITE_BURST =>
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ if dvr_miso.done = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ when START_READING =>
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := TO_UVEC(TO_UINT(inp_sosi.bsn) - g_bim, c_dp_stream_bsn_w);
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize, c_adr_w);
+ v.rd_burst_en := '0';
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
+
+ when READING =>
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index bc766c0ba825314d27c2048578e80d0c06edbc92..a02d77141776fb071301d3ec93c6f7ba0cc2b5cb 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -33,16 +33,16 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use io_ddr_lib.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use io_ddr_lib.all;
entity ddrctrl is
generic (
@@ -97,7 +97,7 @@ architecture str of ddrctrl is
constant c_burstsize : natural := g_tech_ddr.maxburstsize;
constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
+ constant c_max_adr : natural := 2 ** (c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
constant c_adr_per_b : natural := ((g_block_size * g_nof_streams * g_data_w) / c_io_ddr_data_w) + 1; -- rounding error removes the amount of extra addresses.
constant c_bim : natural := natural(floor(real(c_max_adr) / real(c_adr_per_b)));
@@ -148,174 +148,174 @@ begin
-- input to io_ddr
u_ddrctrl_input : entity work.ddrctrl_input
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_max_adr => c_nof_adr,
- g_bim => c_bim,
- g_of_pb => c_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
- in_sosi_arr => in_sosi_arr,
- in_stop => stop,
- out_sosi => out_sosi,
- out_adr => out_adr,
- out_bsn_adr => inp_bsn_adr,
- out_data_stopped => data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_max_adr => c_nof_adr,
+ g_bim => c_bim,
+ g_of_pb => c_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+ in_sosi_arr => in_sosi_arr,
+ in_stop => stop,
+ out_sosi => out_sosi,
+ out_adr => out_adr,
+ out_bsn_adr => inp_bsn_adr,
+ out_data_stopped => data_stopped
+ );
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
u_io_ddr : entity io_ddr_lib.io_ddr
- generic map(
- g_sim_model => g_sim_model,
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_io_ddr_data_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_wr_flush_mode => "VAL",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
+ generic map(
+ g_sim_model => g_sim_model,
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_wr_flush_mode => "VAL",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
)
port map(
- -- DDR reference clock
- ctlr_ref_clk => ctlr_ref_clk,
- ctlr_ref_rst => ctlr_ref_rst,
+ -- DDR reference clock
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_ref_rst => ctlr_ref_rst,
- -- DDR controller clock domain
- ctlr_clk_out => ctrl_clk,
- ctlr_rst_out => ctrl_rst,
+ -- DDR controller clock domain
+ ctlr_clk_out => ctrl_clk,
+ ctlr_rst_out => ctrl_rst,
- ctlr_clk_in => ctrl_clk,
- ctlr_rst_in => ctrl_rst,
+ ctlr_clk_in => ctrl_clk,
+ ctlr_rst_in => ctrl_rst,
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
- state_vec => state_vec,
- ctlr_wr_flush_en_o => ctlr_wr_flush_en,
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+ state_vec => state_vec,
+ ctlr_wr_flush_en_o => ctlr_wr_flush_en,
- -- Driver clock domain
- dvr_clk => clk,
- dvr_rst => rst,
+ -- Driver clock domain
+ dvr_clk => clk,
+ dvr_rst => rst,
- dvr_miso => dvr_miso,
- dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ dvr_mosi => dvr_mosi,
- -- Write FIFO clock domain
- wr_clk => clk,
- wr_rst => rst,
+ -- Write FIFO clock domain
+ wr_clk => clk,
+ wr_rst => rst,
- wr_fifo_usedw => wr_fifo_usedw,
- wr_sosi => wr_sosi,
- wr_siso => open,
+ wr_fifo_usedw => wr_fifo_usedw,
+ wr_sosi => wr_sosi,
+ wr_siso => open,
- -- Read FIFO clock domain
- rd_clk => clk,
- rd_rst => rst,
+ -- Read FIFO clock domain
+ rd_clk => clk,
+ rd_rst => rst,
- rd_fifo_usedw => rd_fifo_usedw,
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
+ rd_fifo_usedw => rd_fifo_usedw,
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
- term_ctrl_out => term_ctrl_out,
- term_ctrl_in => term_ctrl_in,
+ term_ctrl_out => term_ctrl_out,
+ term_ctrl_in => term_ctrl_in,
- -- DDR3 PHY external interface
- phy3_in => phy3_in,
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
+ -- DDR3 PHY external interface
+ phy3_in => phy3_in,
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
- -- DDR4 PHY external interface
- phy4_in => phy4_in,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ -- DDR4 PHY external interface
+ phy4_in => phy4_in,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
-- reading ddr memory
u_ddrctrl_output : entity work.ddrctrl_output
- generic map(
- g_technology => g_technology,
- g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model,
- g_in_data_w => c_io_ddr_data_w,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_block_size => g_block_size,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- in_sosi => rd_sosi,
- in_bsn => bsn_co,
-
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
- out_ready => rd_ready
- );
+ generic map(
+ g_technology => g_technology,
+ g_tech_ddr => g_tech_ddr,
+ g_sim_model => g_sim_model,
+ g_in_data_w => c_io_ddr_data_w,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_block_size => g_block_size,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ in_sosi => rd_sosi,
+ in_bsn => bsn_co,
+
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+ out_ready => rd_ready
+ );
-- controller of ddrctrl
u_ddrctrl_controller : entity work.ddrctrl_controller
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_stop_percentage => g_stop_percentage,
- g_nof_streams => g_nof_streams,
- g_out_data_w => g_data_w,
- g_wr_data_w => c_io_ddr_data_w,
- g_rd_fifo_depth => c_rd_fifo_depth,
- g_rd_data_w => c_io_ddr_data_w,
- g_block_size => g_block_size,
- g_wr_fifo_uw_w => c_wr_fifo_uw_w,
- g_rd_fifo_uw_w => c_rd_fifo_uw_w,
- g_max_adr => c_nof_adr,
- g_burstsize => c_burstsize,
- g_last_burstsize => c_last_burstsize,
- g_adr_per_b => c_adr_per_b,
- g_bim => c_bim
- )
- port map(
- clk => clk,
- rst => rst,
-
- -- ddrctrl_input
- inp_of => out_of,
- inp_sosi => out_sosi,
- inp_adr => out_adr,
- inp_bsn_adr => inp_bsn_adr,
- inp_data_stopped => data_stopped,
- rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
-
- -- io_ddr
- dvr_mosi => dvr_mosi,
- dvr_miso => dvr_miso,
- wr_sosi => wr_sosi,
- wr_siso => c_dp_siso_rdy,
- wr_fifo_usedw => wr_fifo_usedw,
- rd_fifo_usedw => rd_fifo_usedw,
- ctlr_wr_flush_en => ctlr_wr_flush_en,
- flush_state => state_vec,
-
- -- ddrctrl_output
- outp_bsn => bsn_co,
-
- -- ddrctrl_controller
- stop_in => stop_in,
- stop_out => stop,
- ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_stop_percentage => g_stop_percentage,
+ g_nof_streams => g_nof_streams,
+ g_out_data_w => g_data_w,
+ g_wr_data_w => c_io_ddr_data_w,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_io_ddr_data_w,
+ g_block_size => g_block_size,
+ g_wr_fifo_uw_w => c_wr_fifo_uw_w,
+ g_rd_fifo_uw_w => c_rd_fifo_uw_w,
+ g_max_adr => c_nof_adr,
+ g_burstsize => c_burstsize,
+ g_last_burstsize => c_last_burstsize,
+ g_adr_per_b => c_adr_per_b,
+ g_bim => c_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ -- ddrctrl_input
+ inp_of => out_of,
+ inp_sosi => out_sosi,
+ inp_adr => out_adr,
+ inp_bsn_adr => inp_bsn_adr,
+ inp_data_stopped => data_stopped,
+ rst_ddrctrl_input_ac => rst_ddrctrl_input_ac,
+
+ -- io_ddr
+ dvr_mosi => dvr_mosi,
+ dvr_miso => dvr_miso,
+ wr_sosi => wr_sosi,
+ wr_siso => c_dp_siso_rdy,
+ wr_fifo_usedw => wr_fifo_usedw,
+ rd_fifo_usedw => rd_fifo_usedw,
+ ctlr_wr_flush_en => ctlr_wr_flush_en,
+ flush_state => state_vec,
+
+ -- ddrctrl_output
+ outp_bsn => bsn_co,
+
+ -- ddrctrl_controller
+ stop_in => stop_in,
+ stop_out => stop,
+ ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 69b4c10a71d9cde40702755a4709d38f7f538417..13eb452e40c29d6ae58e4424de18c68edc4e97d3 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -28,12 +28,12 @@
--
library IEEE, dp_lib, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_controller is
generic (
@@ -124,34 +124,34 @@ architecture rtl of ddrctrl_controller is
-- record for readability
type t_reg is record
- -- state of program
- state : t_state;
- started : std_logic;
-
- -- stopping flush
- timer : natural;
-
- -- stopping signals
- ready_for_set_stop : std_logic;
- stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
- last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
- stop_burstsize : natural;
- stopped : std_logic;
- rst_ddrctrl_input_ac : std_logic;
-
- -- writing signals
- wr_burst_en : std_logic;
- wr_bursts_ready : natural;
-
- -- reading signals
- outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- read_adr : natural;
- rd_burst_en : std_logic;
-
- -- output
- dvr_mosi : t_mem_ctlr_mosi;
- wr_sosi : t_dp_sosi;
- ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
+ -- state of program
+ state : t_state;
+ started : std_logic;
+
+ -- stopping flush
+ timer : natural;
+
+ -- stopping signals
+ ready_for_set_stop : std_logic;
+ stop_adr : std_logic_vector(c_adr_w - 1 downto 0);
+ last_adr_to_write_to : std_logic_vector(c_adr_w - 1 downto 0);
+ stop_burstsize : natural;
+ stopped : std_logic;
+ rst_ddrctrl_input_ac : std_logic;
+
+ -- writing signals
+ wr_burst_en : std_logic;
+ wr_bursts_ready : natural;
+
+ -- reading signals
+ outp_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ read_adr : natural;
+ rd_burst_en : std_logic;
+
+ -- output
+ dvr_mosi : t_mem_ctlr_mosi;
+ wr_sosi : t_dp_sosi;
+ ddrctrl_ctrl_state : std_logic_vector(32 - 1 downto 0);
end record;
constant c_t_reg_init : t_reg := (RESET, '0', 4, '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (others => '0'));
@@ -164,7 +164,6 @@ begin
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, wr_fifo_usedw, stop_in)
-
variable v : t_reg := c_t_reg_init;
begin
v := q_reg;
@@ -173,276 +172,276 @@ begin
--v.ddrctrl_ctrl_state(c_high_adr_ndx DOWNTO c_low_adr_ndx) := TO_UVEC(inp_adr, 32)(c_adr_ndx_w-1 DOWNTO 0);
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
-
- if rst = '0' and wr_siso.ready = '1' then
- v.state := STOP_FLUSH;
- v.timer := 0;
- end if;
-
- when STOP_FLUSH =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- if flush_state = "10" then
- v.dvr_mosi.burstbegin := '1';
+ when RESET =>
+ v := c_t_reg_init;
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
+
+ if rst = '0' and wr_siso.ready = '1' then
+ v.state := STOP_FLUSH;
+ v.timer := 0;
+ end if;
+
+ when STOP_FLUSH =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ if flush_state = "10" then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
+ v.dvr_mosi.wr := '1';
+ elsif flush_state = "11" and q_reg.timer = 0 then
+ v.wr_sosi.valid := '1';
+ v.timer := 127;
+ end if;
+
+ if q_reg.timer > 0 and rst = '0' then
+ v.timer := q_reg.timer - 1;
+ end if;
+
+ if flush_state = "01" then
+ v.state := WAIT_FOR_SOP;
+ v.stopped := '0';
+ end if;
+
+ when STOP_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
+ -- this is the last read burst, this make sure every data containing word in the memory has been read.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.stopped := '0';
+ v.wr_sosi.valid := '1';
+ v.state := WAIT_FOR_SOP;
+ v.wr_burst_en := '1';
+ v.rst_ddrctrl_input_ac := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
+
+ when WAIT_FOR_SOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
+ v.dvr_mosi.burstbegin := '0';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
v.dvr_mosi.wr := '1';
- elsif flush_state = "11" and q_reg.timer = 0 then
- v.wr_sosi.valid := '1';
- v.timer := 127;
- end if;
-
- if q_reg.timer > 0 and rst = '0' then
- v.timer := q_reg.timer - 1;
- end if;
-
- if flush_state = "01" then
- v.state := WAIT_FOR_SOP;
- v.stopped := '0';
- end if;
-
- when STOP_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
- -- this is the last read burst, this make sure every data containing word in the memory has been read.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.stopped := '0';
- v.wr_sosi.valid := '1';
- v.state := WAIT_FOR_SOP;
- v.wr_burst_en := '1';
- v.rst_ddrctrl_input_ac := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
-
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
-
- when WAIT_FOR_SOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
- v.dvr_mosi.burstbegin := '0';
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := (others => '0');
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
- v.rst_ddrctrl_input_ac := '0';
- if q_reg.started = '0' and inp_sosi.eop = '1' then
- v.wr_sosi.valid := '0';
- elsif inp_sosi.sop = '1' then
- v.state := WRITING;
- else
- v.wr_sosi.valid := '0';
- end if;
-
- when WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
- -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.rd := '0';
+ v.rst_ddrctrl_input_ac := '0';
+ if q_reg.started = '0' and inp_sosi.eop = '1' then
+ v.wr_sosi.valid := '0';
+ elsif inp_sosi.sop = '1' then
+ v.state := WRITING;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.wr_sosi.valid := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
-
- if stop_in = '1' then
- v.ready_for_set_stop := '1';
- end if;
-
- if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
- v.state := SET_STOP;
- elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- end if;
-
- when SET_STOP =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
- -- this state sets a stop address dependend on the g_stop_percentage.
- if inp_adr - c_pof_ma >= 0 then
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
- else
- v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
- end if;
- v.ready_for_set_stop := '0';
- if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
- v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
- else
- v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
- end if;
- v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
-
- -- still a write cyle
- -- if adr mod g_burstsize = 0
- -- this makes sure that only ones every 64 writes a writeburst is started.
- v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ when WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
+ -- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if q_reg.wr_bursts_ready >= 1 and dvr_miso.done = '1' and q_reg.wr_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
- v.state := STOP_WRITING;
- else
- v.state := WRITING;
- end if;
-
- when STOP_WRITING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
- -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
- v.wr_sosi.valid := '0';
- v.dvr_mosi.burstbegin := '0';
- v.stopped := '1';
- v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-
- -- still receiving write data.
- v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
- if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
- v.wr_burst_en := '1';
- elsif q_reg.wr_bursts_ready = 0 then
- v.wr_burst_en := '0';
- end if;
- if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
- v.dvr_mosi.burstbegin := '1';
- v.wr_burst_en := '0';
- if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
- v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+
+ if stop_in = '1' then
+ v.ready_for_set_stop := '1';
+ end if;
+
+ if q_reg.ready_for_set_stop = '1' and inp_sosi.eop = '1' and stop_in = '0' then
+ v.state := SET_STOP;
+ elsif q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
+ end if;
+
+ when SET_STOP =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
+ -- this state sets a stop address dependend on the g_stop_percentage.
+ if inp_adr - c_pof_ma >= 0 then
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr - c_pof_ma, c_adr_w);
else
- v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
- v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.stop_adr(c_adr_w - 1 downto 0) := TO_UVEC(inp_adr + g_max_adr - c_pof_ma, c_adr_w);
end if;
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
- v.state := LAST_WRITE_BURST;
- end if;
-
- when LAST_WRITE_BURST =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
- -- this state stops the writing by generatign one last write burst which empties wr_fifo.
- v.wr_sosi.valid := '0';
- if dvr_miso.done = '1' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.ready_for_set_stop := '0';
+ if v.stop_adr(c_adr_w - 1 downto 0) = c_stop_adr_zeros(c_adr_w - 1 downto 0) then
+ v.last_adr_to_write_to(c_adr_w - 1 downto 0) := TO_UVEC(g_max_adr - g_last_burstsize, c_adr_w);
else
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
- v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
+ end if;
+ v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
+ v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
+
+ -- still a write cyle
+ -- if adr mod g_burstsize = 0
+ -- this makes sure that only ones every 64 writes a writeburst is started.
+ v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.state := START_READING;
- v.rd_burst_en := '1';
- else
- v.dvr_mosi.burstbegin := '0';
- end if;
- v.dvr_mosi.wr := '1';
- v.dvr_mosi.rd := '0';
-
- when START_READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
- -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
- v.dvr_mosi.burstbegin := '0';
- v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
- v.wr_sosi.valid := '0';
-
- if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
- if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
- v.read_adr := g_burstsize;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * (q_reg.wr_bursts_ready - 1)), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
else
- v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
- v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
- v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ v.dvr_mosi.burstbegin := '0';
end if;
- v.dvr_mosi.burstbegin := '1';
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.rd_burst_en := '0';
- end if;
-
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
- v.rd_burst_en := '1';
- v.state := READING;
- end if;
-
- when READING =>
- v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
- v.wr_sosi.valid := '0';
- -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
- if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
- v.dvr_mosi.wr := '0';
- v.dvr_mosi.rd := '1';
- v.dvr_mosi.burstbegin := '1';
- v.rd_burst_en := '0';
- if q_reg.read_adr > g_max_adr - g_burstsize then
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := 0;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if q_reg.stop_adr = TO_UVEC(inp_adr, c_adr_w) then
+ v.state := STOP_WRITING;
else
- v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
- v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
- v.read_adr := q_reg.read_adr + g_burstsize;
+ v.state := WRITING;
end if;
- else
+
+ when STOP_WRITING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
+ -- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
+ v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
- end if;
+ v.stopped := '1';
+ v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
+
+ -- still receiving write data.
+ v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
+ if not (q_reg.wr_bursts_ready = 0) and q_reg.dvr_mosi.burstbegin = '0'THEN
+ v.wr_burst_en := '1';
+ elsif q_reg.wr_bursts_ready = 0 then
+ v.wr_burst_en := '0';
+ end if;
+ if dvr_miso.done = '1' and q_reg.wr_burst_en = '1' then
+ v.dvr_mosi.burstbegin := '1';
+ v.wr_burst_en := '0';
+ if inp_adr < (g_burstsize * q_reg.wr_bursts_ready) - 1 then
+ v.dvr_mosi.address := TO_UVEC(g_max_adr - g_last_burstsize - (g_burstsize * q_reg.wr_bursts_ready - 1), dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address := TO_UVEC(inp_adr - (g_burstsize * q_reg.wr_bursts_ready), dvr_mosi.address'length);
+ v.dvr_mosi.address(c_bitshift_w - 1 downto 0) := c_zeros(c_bitshift_w - 1 downto 0); -- makes sure that a burst is only started on a multiple of g_burstsize
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ if dvr_miso.done = '1' and q_reg.dvr_mosi.burstbegin = '0' and q_reg.wr_burst_en = '0' and q_reg.wr_bursts_ready = 0 and inp_data_stopped = '1' and TO_UINT(wr_fifo_usedw) <= q_reg.stop_burstsize then
+ v.state := LAST_WRITE_BURST;
+ end if;
+
+ when LAST_WRITE_BURST =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
+ -- this state stops the writing by generatign one last write burst which empties wr_fifo.
+ v.wr_sosi.valid := '0';
+ if dvr_miso.done = '1' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) >= g_max_adr then
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ else
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0);
+ v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.state := START_READING;
+ v.rd_burst_en := '1';
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
+ v.dvr_mosi.wr := '1';
+ v.dvr_mosi.rd := '0';
+
+ when START_READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
+ -- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
+ v.dvr_mosi.burstbegin := '0';
+ v.outp_bsn := INCR_UVEC(inp_sosi.bsn, -1 * g_bim);
+ v.wr_sosi.valid := '0';
+
+ if dvr_miso.done = '1' and v.rd_burst_en = '1' and q_reg.dvr_mosi.burstbegin = '0' then
+ if TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + q_reg.stop_burstsize >= g_max_adr then
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := TO_UVEC(0, c_adr_w);
+ v.read_adr := g_burstsize;
+ else
+ v.dvr_mosi.burstsize(dvr_mosi.burstsize'length - 1 downto 0) := TO_UVEC(g_burstsize - q_reg.stop_burstsize, dvr_mosi.burstsize'length);
+ v.dvr_mosi.address(c_adr_w - 1 downto 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0), q_reg.stop_burstsize);
+ v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0)) + g_burstsize;
+ end if;
+ v.dvr_mosi.burstbegin := '1';
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.rd_burst_en := '0';
+ end if;
+
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' and q_reg.rd_burst_en = '0' then
+ v.rd_burst_en := '1';
+ v.state := READING;
+ end if;
+
+ when READING =>
+ v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
+ v.wr_sosi.valid := '0';
+ -- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
+ if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
+ v.dvr_mosi.wr := '0';
+ v.dvr_mosi.rd := '1';
+ v.dvr_mosi.burstbegin := '1';
+ v.rd_burst_en := '0';
+ if q_reg.read_adr > g_max_adr - g_burstsize then
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_last_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := 0;
+ else
+ v.dvr_mosi.address := TO_UVEC(q_reg.read_adr, dvr_mosi.address'length);
+ v.dvr_mosi.burstsize := TO_UVEC(g_burstsize, dvr_mosi.burstsize'length);
+ v.read_adr := q_reg.read_adr + g_burstsize;
+ end if;
+ else
+ v.dvr_mosi.burstbegin := '0';
+ end if;
- -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
- if dvr_miso.done = '0' then
- v.rd_burst_en := '1';
- end if;
+ -- makes sure the fifo is filled before asking for another rd request. to prevent 4 rd burst to happend directly after one another.
+ if dvr_miso.done = '0' then
+ v.rd_burst_en := '1';
+ end if;
- -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
- if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
- v.state := STOP_READING;
- end if;
+ -- goes to STOP_reading when this read burst was from the burstblock before q_reg.stop_adr
+ if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
+ v.state := STOP_READING;
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index a0f0eea2bd54923eddc34d38aa1508fc0997f093..984eb5a6b6e7d056370fc428451987a69dace84d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -33,13 +33,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input is
generic (
@@ -79,47 +79,47 @@ begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_input_pack : entity work.ddrctrl_input_pack
- generic map(
- g_nof_streams => g_nof_streams, -- number of input streams
- g_data_w => g_data_w -- data with of input data vectors
- )
- port map(
- in_sosi_arr => in_sosi_arr, -- input data
- out_sosi => sosi_p_rp -- output data
- );
+ generic map(
+ g_nof_streams => g_nof_streams, -- number of input streams
+ g_data_w => g_data_w -- data with of input data vectors
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr, -- input data
+ out_sosi => sosi_p_rp -- output data
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_input_repack : entity work.ddrctrl_input_repack
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_in_data_w => c_out_data_w, -- the input data with
- g_bim => g_bim,
- g_of_pb => g_of_pb,
- g_block_size => g_block_size
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => sosi_p_rp, -- input data
- in_stop => in_stop,
- out_sosi => sosi_rp_ac, -- output data
- out_data_stopped => data_stopped_rp_ac
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_in_data_w => c_out_data_w, -- the input data with
+ g_bim => g_bim,
+ g_of_pb => g_of_pb,
+ g_block_size => g_block_size
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => sosi_p_rp, -- input data
+ in_stop => in_stop,
+ out_sosi => sosi_rp_ac, -- output data
+ out_data_stopped => data_stopped_rp_ac
+ );
-- creates address by counting input valids
u_ddrctrl_input_address_counter : entity work.ddrctrl_input_address_counter
- generic map(
- g_tech_ddr => g_tech_ddr, -- type of memory
- g_max_adr => g_max_adr
- )
- port map(
- clk => clk,
- rst => rst_ddrctrl_input_ac,
- in_sosi => sosi_rp_ac, -- input data
- in_data_stopped => data_stopped_rp_ac,
- out_sosi => out_sosi, -- output data
- out_adr => adr,
- out_bsn_adr => out_bsn_adr,
- out_data_stopped => out_data_stopped
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr, -- type of memory
+ g_max_adr => g_max_adr
+ )
+ port map(
+ clk => clk,
+ rst => rst_ddrctrl_input_ac,
+ in_sosi => sosi_rp_ac, -- input data
+ in_data_stopped => data_stopped_rp_ac,
+ out_sosi => out_sosi, -- output data
+ out_adr => adr,
+ out_bsn_adr => out_bsn_adr,
+ out_data_stopped => out_data_stopped
+ );
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index d5e7bd5d7ff86b33d07230934432be13e0621f10..99df87192f6b011eebb9c2bf97ebeaec433bc8a2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -30,13 +30,13 @@
-- The maximum value of the address is determend by g_tech_ddr.
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_address_counter is
generic (
@@ -64,14 +64,14 @@ architecture rtl of ddrctrl_input_address_counter is
-- record for readability
type t_reg is record
- state : t_state;
- bsn_passed : std_logic;
- out_sosi : t_dp_sosi;
- out_bsn_adr : natural;
- out_data_stopped : std_logic;
- s_in_sosi : t_dp_sosi;
- s_in_data_stopped : std_logic;
- s_adr : natural;
+ state : t_state;
+ bsn_passed : std_logic;
+ out_sosi : t_dp_sosi;
+ out_bsn_adr : natural;
+ out_data_stopped : std_logic;
+ s_in_sosi : t_dp_sosi;
+ s_in_data_stopped : std_logic;
+ s_adr : natural;
end record;
constant c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
@@ -84,8 +84,7 @@ begin
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
p_adr : process(rst, in_sosi, in_data_stopped, q_reg)
-
- variable v : t_reg;
+ variable v : t_reg;
begin
v := q_reg;
@@ -96,32 +95,32 @@ begin
v.s_in_data_stopped := in_data_stopped;
case q_reg.state is
- when RESET =>
- v := c_t_reg_init;
+ when RESET =>
+ v := c_t_reg_init;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when COUNTING =>
- v.s_adr := q_reg.s_adr + 1;
+ when COUNTING =>
+ v.s_adr := q_reg.s_adr + 1;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when MAX =>
- v.s_adr := 0;
+ when MAX =>
+ v.s_adr := 0;
- if q_reg.s_in_sosi.sop = '1' then
- v.out_bsn_adr := v.s_adr;
- end if;
+ if q_reg.s_in_sosi.sop = '1' then
+ v.out_bsn_adr := v.s_adr;
+ end if;
- when IDLE =>
- -- after a reset wait for a sop so the memory will be filled with whole blocks.
- if in_sosi.sop = '1' then
- v.bsn_passed := '1';
- end if;
+ when IDLE =>
+ -- after a reset wait for a sop so the memory will be filled with whole blocks.
+ if in_sosi.sop = '1' then
+ v.bsn_passed := '1';
+ end if;
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 4895077bd3f1da1a0570e9b981f67a2e1f635842..23aaee61dd8d607b3c559d5ecdb30ab45aaaa34c 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -28,8 +28,8 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_input_pack is
generic (
@@ -46,6 +46,7 @@ architecture rtl of ddrctrl_input_pack is
begin
-- Putting all the data from the different streams into one data vector.
gen_extract_and_pack_data : for I in 0 to g_nof_streams - 1 generate
+
p_generate : process(in_sosi_arr) is
begin
out_sosi.data(g_data_w * (I + 1) - 1 downto g_data_w * I) <= in_sosi_arr(I).data(g_data_w - 1 downto 0);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 2c232e370e4a19cdca0067674e2991ebbd649fbd..4eb53d621e7087f2ef66c15b904de5bed8fd0688 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -30,9 +30,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity ddrctrl_input_repack is
generic (
@@ -63,16 +63,16 @@ architecture rtl of ddrctrl_input_repack is
-- record for readability
type t_reg is record
- state : t_state; -- the state the process is currently in;
- c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
- c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
- q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
- q_sop : std_logic;
- s_input_cnt : natural;
- out_of : natural;
- out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
- out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
- out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
+ state : t_state; -- the state the process is currently in;
+ c_v : std_logic_vector(k_c_v_w - 1 downto 0); -- the vector that stores the input data until the data is put into the output data vector
+ c_v_count : natural; -- the amount of times the c_v vector received data from the input since the last time it was filled completely
+ q_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
+ q_sop : std_logic;
+ s_input_cnt : natural;
+ out_of : natural;
+ out_data_count : std_logic; -- the amount of times the output data vector has been filled since the last time c_v was filled completely
+ out_sosi : t_dp_sosi; -- this is the sosi stream that contains the data
+ out_data_stopped : std_logic; -- this signal is '1' when there is no more data comming form ddrctrl_input_pack
end record;
constant c_t_reg_init : t_reg := (RESET, (others => '0'), 0, (others => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
@@ -85,75 +85,74 @@ begin
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, in_sosi, in_stop)
-
variable v : t_reg;
begin
v := q_reg;
case q_reg.state is
- when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.valid := '0'; -- out_sosi.valid 0
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
- v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := q_reg.q_sop;
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
- v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
- v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
- v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
- v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- v.c_v_count := 0; -- reset counter
- v.out_data_count := '0'; -- reset counter
- v.s_input_cnt := q_reg.s_input_cnt + 1;
- v.q_sop := '0';
- v.out_sosi.sop := '0';
- v.out_sosi.eop := '0';
- v.out_data_stopped := '0';
-
- when BSN =>
-
- v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
- v.out_of := 0;
- if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ when FILL_VECTOR => -- if the input data doesn't exceeds the output data vector width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
+ v.out_sosi.valid := '0'; -- out_sosi.valid 0
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
+ v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- else
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.out_data_count := '1'; -- increase the counter of out_sosi.data with 1
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := q_reg.q_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := q_reg.q_sop;
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
+ v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
+ v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
+ v.c_v(v.out_of - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto g_in_data_w - v.out_of); -- fill the start of c_v untill the out_of
v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
- v.out_sosi.valid := '1'; -- out_sosi.valid 1
- end if;
-
- -- BSN_INPUT
- v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
- v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
- v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
- v.c_v_count := 1; -- increase the counter of c_v with 1
- v.out_data_count := '0';
- v.out_sosi.eop := '1';
-
- when RESET =>
- v := c_t_reg_init;
- v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
-
- when STOP =>
- v.out_sosi.valid := '0';
- v.q_sop := '0';
- v.out_data_stopped := '1';
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ v.c_v_count := 0; -- reset counter
+ v.out_data_count := '0'; -- reset counter
+ v.s_input_cnt := q_reg.s_input_cnt + 1;
+ v.q_sop := '0';
+ v.out_sosi.sop := '0';
+ v.out_sosi.eop := '0';
+ v.out_data_stopped := '0';
+
+ when BSN =>
+
+ v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
+ v.out_of := 0;
+ if ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of < c_out_data_w * 1) then
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(c_out_data_w - 1 downto 0); -- fill out_sosi.data with 1st part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ else
+ v.out_sosi.data(c_out_data_w - 1 downto 0) := v.c_v(k_c_v_w - 1 downto c_out_data_w); -- fill out_sosi.data with 2nd part of c_v
+ v.out_sosi.valid := '1'; -- out_sosi.valid 1
+ end if;
+
+ -- BSN_INPUT
+ v.q_bsn := in_sosi.bsn; -- a bsn number is saved when the bsn changes
+ v.q_sop := '1'; -- a signal which indicates that a bsn is written in this word(576) so the address counter can save the corresponinding address. (there are delay in address counter so in_adr is not the same as the address of the word the data from the bsn is written to)
+ v.c_v(g_in_data_w - 1 downto 0) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
+ v.c_v_count := 1; -- increase the counter of c_v with 1
+ v.out_data_count := '0';
+ v.out_sosi.eop := '1';
+
+ when RESET =>
+ v := c_t_reg_init;
+ v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
+
+ when STOP =>
+ v.out_sosi.valid := '0';
+ v.q_sop := '0';
+ v.out_data_stopped := '1';
end case;
if rst = '1' then
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 69fee61b011b63c1a46bd14c0fb2995ff764d283..19e1fdf7c76893b0ab9e29c3d4b193069dd921b7 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -30,13 +30,13 @@
-- https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
library IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ddrctrl_output is
generic (
@@ -70,77 +70,76 @@ architecture str of ddrctrl_output is
-- signals for connecting the components
signal sosi : t_dp_sosi := c_dp_sosi_init;
signal out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL fifo_snk_in_sosi : t_dp_sosi := c_dp_sosi_init;
signal q_out_siso : t_dp_siso := c_dp_siso_rst;
signal q_q_out_siso : t_dp_siso := c_dp_siso_rst;
signal unpack_state_off : std_logic := '0';
--- SIGNAL siso : t_dp_siso := c_dp_siso_rst;
--- SIGNAL fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
--- SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0) := (OTHERS => '0');
+ -- SIGNAL siso : t_dp_siso := c_dp_siso_rst;
+ -- SIGNAL fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
+ -- SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0) := (OTHERS => '0');
begin
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_output_unpack : entity work.ddrctrl_output_unpack
- generic map(
- g_tech_ddr => g_tech_ddr,
- g_in_data_w => g_in_data_w,
- g_out_data_w => c_out_data_w,
- g_block_size => g_block_size,
- g_bim => g_bim
- )
- port map(
- clk => clk,
- rst => rst,
- in_sosi => in_sosi, -- input data
- in_bsn => in_bsn,
- out_siso => out_siso,
- out_sosi => out_sosi, -- output data
- out_ready => out_ready,
- state_off => unpack_state_off
- );
+ generic map(
+ g_tech_ddr => g_tech_ddr,
+ g_in_data_w => g_in_data_w,
+ g_out_data_w => c_out_data_w,
+ g_block_size => g_block_size,
+ g_bim => g_bim
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ in_sosi => in_sosi, -- input data
+ in_bsn => in_bsn,
+ out_siso => out_siso,
+ out_sosi => out_sosi, -- output data
+ out_ready => out_ready,
+ state_off => unpack_state_off
+ );
-- resizes the input data vector so that the output data vector can be stored into the ddr memory
u_ddrctrl_output_repack : entity work.ddrctrl_output_repack
- generic map(
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w
- )
- port map(
- in_sosi => sosi,
- out_sosi_arr => out_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ port map(
+ in_sosi => sosi,
+ out_sosi_arr => out_sosi_arr
+ );
--- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
--- GENERIC MAP (
--- g_technology => g_technology,
--- g_wr_data_w => c_out_data_w,
--- g_rd_data_w => c_out_data_w,
--- g_use_ctrl => FALSE,
--- g_wr_fifo_size => c_fifo_size,
--- g_wr_fifo_af_margin => 0,
--- g_rd_fifo_rl => 0
--- )
--- PORT MAP (
--- wr_rst => rst,
--- wr_clk => clk,
--- rd_rst => rst,
--- rd_clk => clk,
---
--- snk_out => OPEN,
--- snk_in => fifo_snk_in_sosi,
---
--- wr_ful => OPEN,
--- wr_usedw => fifo_usedw,
--- rd_usedw => OPEN,
--- rd_emp => OPEN,
---
--- src_in => siso,
--- src_out => fifo_src_out_sosi
--- );
+ -- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ -- GENERIC MAP (
+ -- g_technology => g_technology,
+ -- g_wr_data_w => c_out_data_w,
+ -- g_rd_data_w => c_out_data_w,
+ -- g_use_ctrl => FALSE,
+ -- g_wr_fifo_size => c_fifo_size,
+ -- g_wr_fifo_af_margin => 0,
+ -- g_rd_fifo_rl => 0
+ -- )
+ -- PORT MAP (
+ -- wr_rst => rst,
+ -- wr_clk => clk,
+ -- rd_rst => rst,
+ -- rd_clk => clk,
+ --
+ -- snk_out => OPEN,
+ -- snk_in => fifo_snk_in_sosi,
+ --
+ -- wr_ful => OPEN,
+ -- wr_usedw => fifo_usedw,
+ -- rd_usedw => OPEN,
+ -- rd_emp => OPEN,
+ --
+ -- src_in => siso,
+ -- src_out => fifo_src_out_sosi
+ -- );
p_out_siso_ready : process(out_siso, clk, out_sosi, q_out_siso)
-
- variable sosi_valid : std_logic := '0';
+ variable sosi_valid : std_logic := '0';
begin
if out_siso.ready = '0' and not (q_out_siso.ready = out_siso.ready) then
sosi <= out_sosi;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 02b993e2c33a9cd801ae8ba2302f805422317263..87f5bc02f769546da89a9e6478dff052ca605bcb 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -29,9 +29,9 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_repack is
generic (
@@ -54,5 +54,4 @@ begin
out_sosi_arr(I).sop <= in_sosi.sop;
out_sosi_arr(I).eop <= in_sosi.eop;
end generate;
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index b9e56f78f12bcbf809079c757a77e8e3f6f7da34..a8923517d2eb2fbdc519a2629cf730705c92bcd6 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -32,10 +32,10 @@
-- The output vector must be larger than the input vector.
library IEEE, dp_lib, tech_ddr_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use common_lib.common_pkg.all;
entity ddrctrl_output_unpack is
generic (
@@ -65,17 +65,17 @@ architecture rtl of ddrctrl_output_unpack is
-- record for readability
type t_reg is record
- state : t_state;
- a_of : natural;
- op_data_cnt : natural;
- delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
- dd_fresh : std_logic;
- valid_data : std_logic;
- c_v : std_logic_vector(c_v_w - 1 downto 0);
- bsn_cnt : natural;
- out_sosi : t_dp_sosi;
- out_ready : std_logic;
- state_off : std_logic;
+ state : t_state;
+ a_of : natural;
+ op_data_cnt : natural;
+ delay_data : std_logic_vector(g_in_data_w - 1 downto 0);
+ dd_fresh : std_logic;
+ valid_data : std_logic;
+ c_v : std_logic_vector(c_v_w - 1 downto 0);
+ bsn_cnt : natural;
+ out_sosi : t_dp_sosi;
+ out_ready : std_logic;
+ state_off : std_logic;
end record;
constant c_t_reg_init : t_reg := (RESET, 0, 0, (others => '0'), '0', '0', (others => '0'), 0, c_dp_sosi_init, '0', '0');
@@ -88,99 +88,98 @@ begin
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, in_bsn, in_sosi, out_siso)
-
variable v : t_reg;
begin
v := q_reg;
if out_siso.ready = '1' or q_reg.state = OFF or q_reg.state = IDLE or q_reg.state = RESET or rst = '1' then
case q_reg.state is
- when READING =>
- -- generating output from the data already present in c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- v.op_data_cnt := q_reg.op_data_cnt + 1;
-
- if q_reg.out_sosi.eop = '1' then
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
- v.out_sosi.eop := '0';
- v.out_sosi.sop := '1';
- v.bsn_cnt := 0;
- elsif q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
- when OVER_HALF =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
+ when READING =>
+ -- generating output from the data already present in c_v
v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
v.out_sosi.valid := '1';
v.bsn_cnt := q_reg.bsn_cnt + 1;
+ v.op_data_cnt := q_reg.op_data_cnt + 1;
+
+ if q_reg.out_sosi.eop = '1' then
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := INCR_UVEC(q_reg.out_sosi.bsn, 1);
+ v.out_sosi.eop := '0';
+ v.out_sosi.sop := '1';
+ v.bsn_cnt := 0;
+ elsif q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
+
+ when OVER_HALF =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
+ v.op_data_cnt := 0;
+ elsif q_reg.valid_data = '0' then
+ -- there is no data ready.
+ end if;
+
+ if q_reg.out_sosi.sop = '1' then
+ v.out_sosi.sop := '0';
+ end if;
+
+ when FIRST_READ =>
-- put the second half of c_v into the first half of c_v
v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
v.valid_data := '0';
- v.a_of := ((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of) - g_in_data_w;
- v.op_data_cnt := 0;
- elsif q_reg.valid_data = '0' then
- -- there is no data ready.
- end if;
-
- if q_reg.out_sosi.sop = '1' then
- v.out_sosi.sop := '0';
- end if;
-
- when FIRST_READ =>
- -- put the second half of c_v into the first half of c_v
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
-
- -- fills the first half of c_v and generates output from it.
- v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
- v.out_sosi.valid := '1';
- v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
- v.out_sosi.sop := '1';
- v.out_sosi.eop := '0';
- v.bsn_cnt := 0;
- v.op_data_cnt := 1;
-
- when BSN =>
- -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
- v.out_sosi.valid := '0';
- if q_reg.valid_data = '1' then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
- v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- -- put the second half of c_v into the first half of c_v
+
+ -- fills the first half of c_v and generates output from it.
v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
- v.valid_data := '0';
- v.op_data_cnt := 0;
- elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
- -- generate output from the middle of c_v
- v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := v.c_v(g_out_data_w - 1 downto 0);
v.out_sosi.valid := '1';
- v.bsn_cnt := q_reg.bsn_cnt + 1;
- end if;
-
- v.out_sosi.eop := '1';
- v.a_of := 0;
- v.bsn_cnt := q_reg.bsn_cnt + 1;
-
- when RESET =>
- v := c_t_reg_init;
-
- when IDLE =>
- -- the statemachine goes to Idle when its finished or when its waiting on other components.
- v.out_sosi.valid := '0';
-
- when OFF =>
- -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
- v.out_sosi := c_dp_sosi_init;
- v.bsn_cnt := 0;
- v.state_off := '1';
+ v.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0) := in_bsn(c_dp_stream_bsn_w - 1 downto 0);
+ v.out_sosi.sop := '1';
+ v.out_sosi.eop := '0';
+ v.bsn_cnt := 0;
+ v.op_data_cnt := 1;
+
+ when BSN =>
+ -- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
+ v.out_sosi.valid := '0';
+ if q_reg.valid_data = '1' then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ -- put the second half of c_v into the first half of c_v
+ v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
+ v.valid_data := '0';
+ v.op_data_cnt := 0;
+ elsif (g_out_data_w * (v.op_data_cnt + 1)) + q_reg.a_of < g_in_data_w then
+ -- generate output from the middle of c_v
+ v.out_sosi.data(g_out_data_w - 1 downto 0) := q_reg.c_v((g_out_data_w * (q_reg.op_data_cnt + 1)) + q_reg.a_of - 1 downto (g_out_data_w * q_reg.op_data_cnt) + q_reg.a_of);
+ v.out_sosi.valid := '1';
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+ end if;
+
+ v.out_sosi.eop := '1';
+ v.a_of := 0;
+ v.bsn_cnt := q_reg.bsn_cnt + 1;
+
+ when RESET =>
+ v := c_t_reg_init;
+
+ when IDLE =>
+ -- the statemachine goes to Idle when its finished or when its waiting on other components.
+ v.out_sosi.valid := '0';
+
+ when OFF =>
+ -- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
+ v.out_sosi := c_dp_sosi_init;
+ v.bsn_cnt := 0;
+ v.state_off := '1';
end case;
else
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 999afc3545127e74126d91f3c72c52bc67538ed6..cab632421e6b4e6688aca7a7fb24b30f2e5ec670 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -23,15 +23,15 @@
-- > run -a
library IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_ddrctrl is
generic (
@@ -61,14 +61,14 @@ architecture tb of tb_ddrctrl is
-- constants for testbench
constant c_clk_freq : natural := 200; -- clock frequency in MHz
- constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
+ constant c_clk_period : time := (10 ** 6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
constant c_mm_clk_freq : natural := 100; -- mm clock frequency in MHz
- constant c_mm_clk_period : time := (10**6 / c_mm_clk_freq) * 1 ps; -- mm clock period, 10 ns
+ constant c_mm_clk_period : time := (10 ** 6 / c_mm_clk_freq) * 1 ps; -- mm clock period, 10 ns
constant c_stop_value_for_j : natural := 14180;
-- constant for checking output data
constant c_adr_w : natural := func_tech_ddr_ctlr_address_w(c_tech_ddr); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
- constant c_max_adr : natural := 2**(c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
+ constant c_max_adr : natural := 2 ** (c_adr_w) - 1; -- the maximal address that is possible within the vector length of the address
constant c_output_stop_adr : natural := (c_max_adr + 1) - ((((c_max_adr + 1) / 64) * g_stop_percentage / 100) * 64);
constant c_output_ds : natural := 144;
constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (g_block_size * g_nof_streams * g_data_w); -- the amount of whole blocks that fit in memory.
@@ -153,8 +153,7 @@ begin
-- excecuting test
p_test : process
-
- variable out_siso_ready : natural := 0;
+ variable out_siso_ready : natural := 0;
begin
-- start the test
out_siso.ready <= '1';
@@ -250,31 +249,31 @@ begin
-- DUT
u_ddrctrl : entity work.ddrctrl
- generic map (
- g_tech_ddr => c_tech_ddr,
- g_sim_model => c_sim_model,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_stop_percentage => g_stop_percentage,
- g_block_size => g_block_size
- )
- port map (
- clk => clk,
- rst => rst,
- ctlr_ref_clk => clk,
- ctlr_ref_rst => rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- in_sosi_arr => in_sosi_arr,
- stop_in => stop_in,
- out_sosi_arr => out_sosi_arr,
- out_siso => out_siso,
-
- --PHY
- phy3_io => phy3_io,
- phy3_ou => phy3_ou,
- phy4_io => phy4_io,
- phy4_ou => phy4_ou
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr,
+ g_sim_model => c_sim_model,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_stop_percentage => g_stop_percentage,
+ g_block_size => g_block_size
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ ctlr_ref_clk => clk,
+ ctlr_ref_rst => rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ in_sosi_arr => in_sosi_arr,
+ stop_in => stop_in,
+ out_sosi_arr => out_sosi_arr,
+ out_siso => out_siso,
+
+ --PHY
+ phy3_io => phy3_io,
+ phy3_ou => phy3_ou,
+ phy4_io => phy4_io,
+ phy4_ou => phy4_ou
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 107e1a05883b173a0ea9f423426ca1eb60511687..934dbf470f3f709bf48dd529e3b1953b5504854a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -27,13 +27,13 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_adc_input_and_timing is
generic (
@@ -187,35 +187,35 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
- g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_N_sync_jesd,
- g_jesd_freq => c_sdp_jesd204b_freq
- )
- port map(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_jesd,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
- );
+ generic map(
+ g_sim => false, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_sync_n => c_sdp_N_sync_jesd,
+ g_jesd_freq => c_sdp_jesd204b_freq
+ )
+ port map(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_jesd,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
@@ -236,125 +236,126 @@ begin
end process;
u_dp_shiftram : entity dp_lib.dp_shiftram
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc,
- g_use_sync_in => true
- )
- port map (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_words => c_sdp_V_sample_delay,
+ g_data_w => c_sdp_W_adc,
+ g_use_sync_in => true
+ )
+ port map (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- sync_in => bs_sosi.sync,
+ sync_in => bs_sosi.sync,
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
- snk_in_arr => dp_shiftram_snk_in_arr,
+ snk_in_arr => dp_shiftram_snk_in_arr,
- src_out_arr => ant_sosi_arr
- );
+ src_out_arr => ant_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_v2_mosi,
- reg_miso => reg_bsn_source_v2_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi,
-
- bs_restart => rx_bsn_source_restart,
- bs_new_interval => rx_bsn_source_new_interval,
- bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi,
+
+ bs_restart => rx_bsn_source_restart,
+ bs_new_interval => rx_bsn_source_new_interval,
+ bs_nof_clk_per_sync => rx_bsn_source_nof_clk_per_sync
+ );
u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => true,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
+ trigger_out => trigger_wg
+ );
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_cross_clock_domain => true,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_sdp_W_adc
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_cross_clock_domain => true,
+ g_buf_dir => c_wg_buf_directory,
+
+ -- Wideband parameters
+ g_wideband_factor => 1,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => c_wg_buf_dat_w,
+ g_buf_addr_w => c_wg_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => 1,
+ g_calc_dat_w => c_sdp_W_adc
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_wg_mosi,
+ reg_miso => reg_wg_miso,
+
+ buf_mosi => ram_wg_mosi,
+ buf_miso => ram_wg_miso,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+ st_restart => trigger_wg,
+
+ out_sosi_arr => wg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
gen_mux : for I in 0 to c_sdp_S_pn - 1 generate
+
p_sosi : process(ant_sosi_arr(I), wg_sosi_arr(I))
begin
-- Default use the ADC data
@@ -373,6 +374,7 @@ begin
-----------------------------------------------------------------------------
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
+
p_sosi : process(mux_sosi_arr(I), bs_sosi)
begin
st_sosi_arr(I) <= bs_sosi;
@@ -391,101 +393,101 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => c_bs_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => c_bs_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
u_aduh_monitor : entity aduh_lib.mms_aduh_monitor_arr
- generic map (
- g_cross_clock_domain => true,
- g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc,
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => g_bsn_nof_clk_per_sync
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => c_mem_mosi_rst, -- Unused
- buf_miso => OPEN,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_nof_streams => c_sdp_S_pn,
+ g_symbol_w => c_sdp_W_adc,
+ g_nof_symbols_per_data => 1, -- Wideband factor is 1
+ g_nof_accumulations => g_bsn_nof_clk_per_sync
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+ reg_miso => reg_aduh_monitor_miso,
+ buf_mosi => c_mem_mosi_rst, -- Unused
+ buf_miso => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rx_rst,
+ st_clk => rx_clk,
+
+ in_sosi_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- ST Histogram
-----------------------------------------------------------------------------
u_st_histogram : entity st_lib.mmp_st_histogram
- generic map (
- g_nof_instances => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_nof_bins => c_sdp_V_si_histogram,
- g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
- g_nof_data_per_sync_diff => c_sdp_N_fft / 2
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_copi => ram_st_histogram_mosi,
- ram_cipo => ram_st_histogram_miso,
-
- snk_in_arr => st_sosi_arr
- );
+ generic map (
+ g_nof_instances => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_nof_bins => c_sdp_V_si_histogram,
+ g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
+ g_nof_data_per_sync_diff => c_sdp_N_fft / 2
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_copi => ram_st_histogram_mosi,
+ ram_cipo => ram_st_histogram_miso,
+
+ snk_in_arr => st_sosi_arr
+ );
-----------------------------------------------------------------------------
-- Output Stage
@@ -530,36 +532,36 @@ begin
-- in mms_dp_bsn_monitor, and from rx_clk to dp_clk here. No need to go via
-- u_dp_fifo_dc_arr, use common_reg_cross_domain instead to save logic and/or RAM.
u_dp_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => rx_rst,
- in_clk => rx_clk,
- in_dat => rx_bsn_source_nof_clk_per_sync,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_dat => dp_bsn_source_nof_clk_per_sync
- );
+ port map (
+ in_rst => rx_rst,
+ in_clk => rx_clk,
+ in_dat => rx_bsn_source_nof_clk_per_sync,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_dat => dp_bsn_source_nof_clk_per_sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_sdp_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg_wr,
- in_reg => mm_jesd_ctrl_reg_rd
- );
+ generic map (
+ g_reg => c_sdp_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg_wr,
+ in_reg => mm_jesd_ctrl_reg_rd
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index bfdc7b5a694132d4a1999d9175097a2928b54974..0a4822168cae1308a9e09696d89b6e7c57fda3f8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -30,13 +30,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_beamformer is
generic (
@@ -153,74 +153,74 @@ begin
-- Beamlet Subband Select
---------------------------------------------------------------
u_reorder_col_wide : entity reorder_lib.reorder_col_wide
- generic map (
- g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
- g_dsp_data_w => g_subband_raw_dat_w,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
- g_select_file_prefix => c_bf_select_file_prefix,
- g_use_complex => true
- )
- port map(
- input_sosi_arr => in_sosi_arr,
- output_sosi_arr => bsel_sosi_arr,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_wb_factor => c_sdp_P_pfb, -- g_wb_factor is only used for number of parallel streams
+ g_dsp_data_w => g_subband_raw_dat_w,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => c_sdp_S_sub_bf * c_sdp_Q_fft,
+ g_select_file_prefix => c_bf_select_file_prefix,
+ g_use_complex => true
+ )
+ port map(
+ input_sosi_arr => in_sosi_arr,
+ output_sosi_arr => bsel_sosi_arr,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- Local BF
---------------------------------------------------------------
u_sdp_beamformer_local : entity work.sdp_beamformer_local
- generic map (
- g_bf_weights_file_name => c_bf_weights_file_name,
- g_raw_dat_w => g_subband_raw_dat_w,
- g_raw_fraction_w => g_subband_raw_fraction_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
-
- in_sosi_arr => bsel_sosi_arr,
- out_sosi => local_bf_sosi
- );
+ generic map (
+ g_bf_weights_file_name => c_bf_weights_file_name,
+ g_raw_dat_w => g_subband_raw_dat_w,
+ g_raw_fraction_w => g_subband_raw_fraction_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_bf_weights_mosi => ram_bf_weights_mosi,
+ ram_bf_weights_miso => ram_bf_weights_miso,
+
+ in_sosi_arr => bsel_sosi_arr,
+ out_sosi => local_bf_sosi
+ );
---------------------------------------------------------------
-- Remote BF
---------------------------------------------------------------
u_sdp_beamformer_remote : entity work.sdp_beamformer_remote
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- rn_index => rn_index,
- local_bf_sosi => local_bf_sosi,
- from_ri_sosi => from_ri_sosi,
- to_ri_sosi => to_ri_sosi,
- bf_sum_sosi => bf_sum_sosi,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
-
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
-
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
- );
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ rn_index => rn_index,
+ local_bf_sosi => local_bf_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+ bf_sum_sosi => bf_sum_sosi,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
+ );
---------------------------------------------------------------
-- Scale Beamlets
@@ -259,86 +259,86 @@ begin
-- Beamlet Data Output (BDO)
---------------------------------------------------------------
u_sdp_beamformer_output : entity work.sdp_beamformer_output
- generic map(
- g_beamset_id => g_beamset_id,
- g_use_transpose => g_use_bdo_transpose,
- g_nof_destinations_max => g_nof_bdo_destinations_max
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_sosi => bf_out_sosi,
- out_sosi => mon_bf_udp_sosi,
- out_siso => bf_udp_siso,
-
- beamlet_scale => beamlet_scale,
- sdp_info => sdp_info,
- gn_id => gn_id,
-
- eth_src_mac => bdo_eth_src_mac,
- ip_src_addr => bdo_ip_src_addr,
- udp_src_port => bdo_udp_src_port,
-
- hdr_fields_out => bdo_hdr_fields_out,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_destinations_copi => reg_bdo_destinations_copi,
- reg_destinations_cipo => reg_bdo_destinations_cipo,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso
- );
+ generic map(
+ g_beamset_id => g_beamset_id,
+ g_use_transpose => g_use_bdo_transpose,
+ g_nof_destinations_max => g_nof_bdo_destinations_max
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_sosi => bf_out_sosi,
+ out_sosi => mon_bf_udp_sosi,
+ out_siso => bf_udp_siso,
+
+ beamlet_scale => beamlet_scale,
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+
+ eth_src_mac => bdo_eth_src_mac,
+ ip_src_addr => bdo_ip_src_addr,
+ udp_src_port => bdo_udp_src_port,
+
+ hdr_fields_out => bdo_hdr_fields_out,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_destinations_copi => reg_bdo_destinations_copi,
+ reg_destinations_cipo => reg_bdo_destinations_cipo,
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso
+ );
bf_udp_sosi <= mon_bf_udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => c_sdp_N_clk_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr(0) => mon_bf_udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => c_sdp_N_clk_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr(0) => mon_bf_udp_sosi
+ );
---------------------------------------------------------------
-- Beamlet Statistics (BST)
---------------------------------------------------------------
u_beamlet_stats : entity st_lib.st_sst
- generic map(
- g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
- g_in_data_w => c_sdp_W_beamlet_sum,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz,
- g_stat_multiplex => c_sdp_N_pol_bf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_complex => bf_sum_sosi,
- ram_st_sst_mosi => master_mem_mux_mosi,
- ram_st_sst_miso => master_mem_mux_miso
- );
+ generic map(
+ g_nof_stat => c_sdp_S_sub_bf * c_sdp_N_pol_bf,
+ g_in_data_w => c_sdp_W_beamlet_sum,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz,
+ g_stat_multiplex => c_sdp_N_pol_bf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_complex => bf_sum_sosi,
+ ram_st_sst_mosi => master_mem_mux_mosi,
+ ram_st_sst_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- MM master multiplexer
@@ -350,62 +350,62 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- BST UDP offload
---------------------------------------------------------------
u_sdp_bst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "BST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_beamset_id => g_beamset_id
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "BST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_beamset_id => g_beamset_id
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_stat_enable_mosi,
- reg_enable_miso => reg_stat_enable_miso,
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
- in_sosi => bf_sum_sosi,
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => bf_sum_sosi,
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => bst_udp_sosi,
- out_siso => bst_udp_siso,
+ out_sosi => bst_udp_sosi,
+ out_siso => bst_udp_siso,
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
- );
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ );
---------------------------------------------------------------
-- SIGNAL SCOPES
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index d5c96ea99d864ddf79b199ce24fe9c532dc776bf..835686345add696125d64aad44e864df3d7062a8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -32,13 +32,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_correlator is
generic (
@@ -98,16 +98,16 @@ architecture str of node_sdp_correlator is
constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
constant c_data_w : natural := c_sdp_W_crosslet * c_nof_complex;
--- The size for 1 block is probably already enough as the number of blocks received
--- on the remote input of the mux probably have enough gap time in between. Just
--- to be sure to not run into issues in the future, the fifo size is increased to
--- buffer the maximum nof blocks per block period.
- constant c_mux_fifo_size : natural := 2**ceil_log2(g_P_sq * c_block_size_longwords);
--- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
--- repacks from 64bit to 32bit. Chosing 3x to have some room.
- constant c_fifo_fill_size : natural := 2**ceil_log2(3 * c_block_size_longwords);
+ -- The size for 1 block is probably already enough as the number of blocks received
+ -- on the remote input of the mux probably have enough gap time in between. Just
+ -- to be sure to not run into issues in the future, the fifo size is increased to
+ -- buffer the maximum nof blocks per block period.
+ constant c_mux_fifo_size : natural := 2 ** ceil_log2(g_P_sq * c_block_size_longwords);
+ -- c_fifo_fill_size should be at least 2 * c_block_size_longwords as dp_repack_data
+ -- repacks from 64bit to 32bit. Chosing 3x to have some room.
+ constant c_fifo_fill_size : natural := 2 ** ceil_log2(3 * c_block_size_longwords);
--- crosslet statistics offload
+ -- crosslet statistics offload
signal ram_st_offload_copi : t_mem_copi := c_mem_copi_rst;
signal ram_st_offload_cipo : t_mem_cipo := c_mem_cipo_rst;
@@ -146,57 +146,57 @@ begin
---------------------------------------------------------------
gen_requantize : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => g_subband_raw_fraction_w,
- g_lsb_round => true, -- round subband fraction
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 1,
- g_in_dat_w => g_subband_raw_dat_w,
- g_out_dat_w => c_sdp_W_crosslet
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => in_sosi_arr(I),
- src_out => quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => g_subband_raw_fraction_w,
+ g_lsb_round => true, -- round subband fraction
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 1,
+ g_in_dat_w => g_subband_raw_dat_w,
+ g_out_dat_w => c_sdp_W_crosslet
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_sosi_arr(I),
+ src_out => quant_sosi_arr(I)
+ );
end generate;
---------------------------------------------------------------
-- Crosslet Subband Select
---------------------------------------------------------------
u_crosslets_subband_select : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_sdp_N_crosslets_max,
- g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_N_crosslets => c_sdp_N_crosslets_max,
+ g_ctrl_interval_size_min => sel_a_b(g_sim, g_sim_sdp.xst_nof_clk_per_sync_min, c_sdp_xst_nof_clk_per_sync_min)
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_sosi_arr => quant_sosi_arr,
- out_sosi => xsel_sosi,
+ in_sosi_arr => quant_sosi_arr,
+ out_sosi => xsel_sosi,
- new_interval => new_interval,
+ new_interval => new_interval,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_crosslets_info_mosi => reg_crosslets_info_copi,
- reg_crosslets_info_miso => reg_crosslets_info_cipo,
+ reg_crosslets_info_mosi => reg_crosslets_info_copi,
+ reg_crosslets_info_miso => reg_crosslets_info_cipo,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_cipo,
- cur_crosslets_info_rec => OPEN,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ cur_crosslets_info_rec => OPEN,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
-- Use xsel_sosi as local bsn and sync reference since the sync
-- is generated by the bsn_sync_scheduler in sdp_crosslets_subband_select.
@@ -214,110 +214,110 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => c_longword_w / c_data_w,
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 1,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => xsel_data_sosi,
- src_out => local_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => c_longword_w / c_data_w,
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 1,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => xsel_data_sosi,
+ src_out => local_sosi
+ );
---------------------------------------------------------------
-- ring_mux
---------------------------------------------------------------
u_ring_mux : entity ring_lib.ring_mux
- generic map (
- g_bsn_w => c_dp_stream_bsn_w,
- g_data_w => c_longword_w,
- g_channel_w => c_word_w,
- g_use_error => false,
- g_fifo_size => array_init(c_mux_fifo_size, 2)
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- remote_sosi => from_ri_sosi,
- local_sosi => local_sosi,
- mux_sosi => ring_mux_sosi,
- mux_siso => ring_mux_siso
- );
+ generic map (
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_data_w => c_longword_w,
+ g_channel_w => c_word_w,
+ g_use_error => false,
+ g_fifo_size => array_init(c_mux_fifo_size, 2)
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ remote_sosi => from_ri_sosi,
+ local_sosi => local_sosi,
+ mux_sosi => ring_mux_sosi,
+ mux_siso => ring_mux_siso
+ );
to_ri_sosi <= ring_mux_sosi;
-- fill fifo to remove gaps
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_fifo_fill => c_block_size_longwords,
- g_fifo_size => c_fifo_fill_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => ring_mux_siso,
- snk_in => ring_mux_sosi,
-
- src_in => dp_fifo_fill_siso,
- src_out => dp_fifo_fill_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_fifo_fill => c_block_size_longwords,
+ g_fifo_size => c_fifo_fill_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => ring_mux_siso,
+ snk_in => ring_mux_sosi,
+
+ src_in => dp_fifo_fill_siso,
+ src_out => dp_fifo_fill_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 32b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 1,
- g_out_dat_w => c_data_w,
- g_out_nof_words => c_longword_w / c_data_w,
- g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_fill_sosi,
- snk_out => dp_fifo_fill_siso,
- src_out => rx_sosi
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 1,
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => c_longword_w / c_data_w,
+ g_pipeline_ready => true -- Needed for src_in.ready to snk_out.ready.
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_fill_sosi,
+ snk_out => dp_fifo_fill_siso,
+ src_out => rx_sosi
+ );
---------------------------------------------------------------
-- dp_demux
---------------------------------------------------------------
u_dp_demux : entity dp_lib.dp_demux
- generic map (
- g_mode => 0,
- g_nof_output => g_P_sq,
- g_remove_channel_lo => false,
- g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => rx_sosi,
- src_out_arr => dispatch_invert_sosi_arr
- );
+ generic map (
+ g_mode => 0,
+ g_nof_output => g_P_sq,
+ g_remove_channel_lo => false,
+ g_sel_ctrl_invert => true -- TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => rx_sosi,
+ src_out_arr => dispatch_invert_sosi_arr
+ );
dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
@@ -325,72 +325,72 @@ begin
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => g_P_sq,
- g_bsn_latency_max => 2,
- g_nof_aligners_max => 1, -- 1 for Access scheme 3.
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => true,
- g_rd_latency => 1, -- Required for st_xst
- -- for mms_dp_bsn_monitor_v2
- -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub,
- g_nof_input_bsn_monitors => g_P_sq,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => g_P_sq,
+ g_bsn_latency_max => 2,
+ g_nof_aligners_max => 1, -- 1 for Access scheme 3.
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => true,
+ g_rd_latency => 1, -- Required for st_xst
+ -- for mms_dp_bsn_monitor_v2
+ -- Using c_sdp_N_clk_sync_timeout_xsub as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout_xsub,
+ g_nof_input_bsn_monitors => g_P_sq,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
- -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
- mm_sosi => crosslets_sosi,
- mm_copi => crosslets_copi,
- mm_cipo_arr => crosslets_cipo_arr
- );
+ -- Output via local MM interface in dp_clk domain, when g_use_mm_output = TRUE.
+ mm_sosi => crosslets_sosi,
+ mm_copi => crosslets_copi,
+ mm_cipo_arr => crosslets_cipo_arr
+ );
---------------------------------------------------------------
-- Crosslets Statistics (XST)
---------------------------------------------------------------
u_crosslets_stats : entity st_lib.st_xst
- generic map(
- g_nof_streams => g_P_sq,
- g_nof_crosslets => c_sdp_N_crosslets_max,
- g_nof_signal_inputs => c_sdp_S_pn,
- g_in_data_w => c_sdp_W_crosslet,
- g_stat_data_w => c_longword_w,
- g_stat_data_sz => c_longword_sz / c_word_sz
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_sosi => crosslets_sosi,
- mm_mosi => crosslets_copi,
- mm_miso_arr => crosslets_cipo_arr,
-
- ram_st_xsq_mosi => controller_mem_mux_copi,
- ram_st_xsq_miso => controller_mem_mux_cipo
- );
+ generic map(
+ g_nof_streams => g_P_sq,
+ g_nof_crosslets => c_sdp_N_crosslets_max,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_in_data_w => c_sdp_W_crosslet,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz / c_word_sz
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => crosslets_sosi,
+ mm_mosi => crosslets_copi,
+ mm_miso_arr => crosslets_cipo_arr,
+
+ ram_st_xsq_mosi => controller_mem_mux_copi,
+ ram_st_xsq_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- MM controller multiplexer
@@ -402,45 +402,45 @@ begin
ram_st_offload_cipo <= controller_cipo_arr(1);
u_mem_controller_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_controllers,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => controller_copi_arr,
- master_miso_arr => controller_cipo_arr,
- mux_mosi => controller_mem_mux_copi,
- mux_miso => controller_mem_mux_cipo
- );
+ generic map (
+ g_nof_masters => c_nof_controllers,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => controller_copi_arr,
+ master_miso_arr => controller_cipo_arr,
+ mux_mosi => controller_mem_mux_copi,
+ mux_miso => controller_mem_mux_cipo
+ );
---------------------------------------------------------------
-- REG_NOF_CROSSLETS
---------------------------------------------------------------
u_nof_crosslets : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_nof_crosslets
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_nof_crosslets_copi,
- reg_miso => reg_nof_crosslets_cipo,
-
- in_reg => nof_crosslets,
- out_reg => nof_crosslets_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_nof_crosslets
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_nof_crosslets_copi,
+ reg_miso => reg_nof_crosslets_cipo,
+
+ in_reg => nof_crosslets,
+ out_reg => nof_crosslets_reg
+ );
-- Force nof crosslets to max nof crosslets if a higher value is written or to 1 if a lower value is written via MM.
nof_crosslets <= TO_UVEC(1, c_sdp_nof_crosslets_reg_w) when TO_UINT(nof_crosslets_reg) < 1 else
nof_crosslets_reg when TO_UINT(nof_crosslets_reg) <= c_sdp_N_crosslets_max else
- TO_UVEC(c_sdp_N_crosslets_max, c_sdp_nof_crosslets_reg_w);
+ TO_UVEC(c_sdp_N_crosslets_max, c_sdp_nof_crosslets_reg_w);
---------------------------------------------------------------
-- XST UDP offload
@@ -448,48 +448,48 @@ begin
xst_udp_sosi <= mon_xst_udp_sosi_arr(0);
u_sdp_xst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "XST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
- g_P_sq => g_P_sq,
- g_crosslets_direction => 1, -- = lane direction
- g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "XST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time),
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => 1, -- = lane direction
+ g_bsn_monitor_sync_timeout => c_sdp_N_clk_sync_timeout_xsub
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_copi,
- master_miso => ram_st_offload_cipo,
+ master_mosi => ram_st_offload_copi,
+ master_miso => ram_st_offload_cipo,
- reg_enable_mosi => reg_stat_enable_copi,
- reg_enable_miso => reg_stat_enable_cipo,
+ reg_enable_mosi => reg_stat_enable_copi,
+ reg_enable_miso => reg_stat_enable_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
- in_sosi => crosslets_sosi,
- new_interval => new_interval,
+ in_sosi => crosslets_sosi,
+ new_interval => new_interval,
- out_sosi => mon_xst_udp_sosi_arr(0),
- out_siso => xst_udp_siso,
+ out_sosi => mon_xst_udp_sosi_arr(0),
+ out_siso => xst_udp_siso,
- eth_src_mac => stat_eth_src_mac,
- udp_src_port => stat_udp_src_port,
- ip_src_addr => stat_ip_src_addr,
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr,
- gn_index => TO_UINT(gn_id),
- ring_info => ring_info,
- sdp_info => sdp_info,
- weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
+ sdp_info => sdp_info,
+ weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
- nof_crosslets => nof_crosslets, -- from MM
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ nof_crosslets => nof_crosslets, -- from MM
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index 691a5a916f2e60945d2288c84c4eaaf418767720..2ba2eef16f97cce90717f64f3ca69811811bd12e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -53,16 +53,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, rTwoSDF_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_filterbank is
generic (
@@ -126,8 +126,8 @@ architecture str of node_sdp_filterbank is
-- . applications/lofar2/designs/lofar2_unb2c_sdp_station/src/data/
-- Subband gains file can be generated by sdp/src/python/sdp_hex.py
constant c_gains_file_name : string := "data/gains_1024_complex_" &
- natural'image(c_sdp_W_sub_weight) & "b" &
- natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
+ natural'image(c_sdp_W_sub_weight) & "b" &
+ natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
constant c_nof_masters : positive := 2; -- for M&C MM access and for statistics offload MM access
@@ -178,23 +178,23 @@ begin
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -211,42 +211,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -341,7 +341,7 @@ begin
-- SUBBAND STATISTICS
---------------------------------------------------------------
gen_stats_streams: for I in 0 to c_sdp_P_pfb - 1 generate
- u_subband_stats : entity st_lib.st_sst
+ u_subband_stats : entity st_lib.st_sst
generic map(
g_nof_stat => c_sdp_N_sub * c_sdp_Q_fft,
g_in_data_w => c_sdp_W_subband,
@@ -366,16 +366,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -384,18 +384,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -403,41 +403,41 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_quant_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_quant_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 3e9de6c4baba26d5f0883cd46a1de604b0f50b4f..7be9ac95a6a4e4341763520ebd38e5c9710e661a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -37,17 +37,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, rTwoSDF_lib, common_mult_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use filter_lib.fil_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use filter_lib.fil_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.sdp_pkg.all;
entity node_sdp_oversampled_filterbank is
generic (
@@ -105,8 +105,8 @@ architecture str of node_sdp_oversampled_filterbank is
-- See node_sdp_filterbank for location and genetion of hex files
constant c_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
constant c_gains_file_name : string := "data/gains_1024_complex_" &
- natural'image(c_sdp_W_sub_weight) & "b" &
- natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
+ natural'image(c_sdp_W_sub_weight) & "b" &
+ natural'image(c_sdp_W_sub_weight_fraction) & "f_unit";
constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
constant c_fft_complex : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb_complex);
@@ -126,114 +126,116 @@ architecture str of node_sdp_oversampled_filterbank is
-- Use WG as local oscillator, buf contains 16b sin and 16b cos
-- . c_sdp_W_local_oscillator = 16b
-- . c_sdp_W_local_oscillator_fraction = 16b - 1 sign bit = 15b
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2 * c_sdp_N_fft),
- dat_w => c_nof_complex * c_sdp_W_local_oscillator,
- nof_dat => c_sdp_R_os * c_sdp_N_fft,
- init_sl => '0');
-
- constant c_buf_file : string := "data/freq_shift_half_subband_2048x16_im_re.hex";
-
- constant c_wg_ctrl : t_diag_wg := (TO_UVEC(c_diag_wg_mode_repeat, c_diag_wg_mode_w),
- TO_UVEC(c_buf.nof_dat, c_diag_wg_nofsamples_w),
- (others => '0'),
- (others => '0'),
- (others => '0'));
- constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
-
- constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
-
- signal ram_fil_coefs_mosi_arr : t_mem_mosi_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_mosi_rst);
- signal ram_fil_coefs_miso_arr : t_mem_miso_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_miso_rst);
-
- signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
- signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
-
- -- Subband statistics
- signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
-
- signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
- signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
- signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
-
- -- WG as local oscillator (LO)
- signal wg_rddata : std_logic_vector(c_buf.dat_w - 1 downto 0);
- signal wg_rdval : std_logic;
- signal wg_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
- signal wg_rom_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
- signal wg_rd : std_logic;
- signal wg_out_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
-
- -- Spectral Inversion (SI)
- signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal si_sosi_0_piped : t_dp_sosi := c_dp_sosi_rst;
-
- -- Real input FFT
- signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Mixer to shift f_sub/2
- signal mixer_complex_mult_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal mixer_complex_requantize_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Complex input FFT (from LO mixer)
- signal wpfb_unit_complex_in_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_fil_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_unit_complex_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Remove negative frequencies
- signal wpfb_complex_out_resized_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
-
- -- Interleave positive frequencies per factor Q_fft = 2, like with output of real input FFT
- signal wpfb_complex_out_fifo_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
- signal wpfb_complex_out_fifo_siso_arr : t_dp_siso_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_siso_rst);
- signal wpfb_complex_out_resized_sosi_2arr : t_dp_sosi_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_sosi_rst));
- signal wpfb_complex_out_resized_siso_2arr : t_dp_siso_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_siso_rst));
- signal wpfb_complex_out_interleaved_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal subband_equalizer_in_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_selector_pipe_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
-
- signal scope_equalizer_in_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
- signal scope_equalizer_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
-
- signal selector_en : std_logic;
- signal weighted_subbands_flag : std_logic;
-
- signal dp_bsn_source_restart_pipe : std_logic;
- signal dp_bsn_source_restart_delayed : std_logic;
- signal dp_bsn_source_restart_wg : std_logic;
- signal dp_bsn_source_restart_pipe_complex : std_logic;
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2 * c_sdp_N_fft),
+ dat_w => c_nof_complex * c_sdp_W_local_oscillator,
+ nof_dat => c_sdp_R_os * c_sdp_N_fft,
+ init_sl => '0');
+
+ constant c_buf_file : string := "data/freq_shift_half_subband_2048x16_im_re.hex";
+
+ constant c_wg_ctrl : t_diag_wg := (
+ TO_UVEC(c_diag_wg_mode_repeat, c_diag_wg_mode_w),
+ TO_UVEC(c_buf.nof_dat, c_diag_wg_nofsamples_w),
+ (others => '0'),
+ (others => '0'),
+ (others => '0'));
+ constant c_wg_phase_offset : natural := 6; -- Compensate for WG start latency. In nof samples.
+
+ constant c_fil_coefs_mem_addr_w : natural := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+
+ signal ram_fil_coefs_mosi_arr : t_mem_mosi_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_mosi_rst);
+ signal ram_fil_coefs_miso_arr : t_mem_miso_arr(c_sdp_R_os - 1 downto 0) := (others => c_mem_miso_rst);
+
+ signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_mosi_rst);
+ signal ram_st_sst_miso_arr : t_mem_miso_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_mem_miso_rst);
+
+ -- Subband statistics
+ signal ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+ signal master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ signal master_mosi_arr : t_mem_mosi_arr(0 to c_nof_masters - 1) := (others => c_mem_mosi_rst);
+ signal master_miso_arr : t_mem_miso_arr(0 to c_nof_masters - 1) := (others => c_mem_miso_rst);
+
+ -- WG as local oscillator (LO)
+ signal wg_rddata : std_logic_vector(c_buf.dat_w - 1 downto 0);
+ signal wg_rdval : std_logic;
+ signal wg_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
+ signal wg_rom_address : std_logic_vector(c_buf.adr_w - 1 downto 0);
+ signal wg_rd : std_logic;
+ signal wg_out_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
+
+ -- Spectral Inversion (SI)
+ signal si_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal si_sosi_0_piped : t_dp_sosi := c_dp_sosi_rst;
+
+ -- Real input FFT
+ signal wpfb_unit_in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_fil_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Mixer to shift f_sub/2
+ signal mixer_complex_mult_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal mixer_complex_requantize_src_out_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Complex input FFT (from LO mixer)
+ signal wpfb_unit_complex_in_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_fil_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_out_quant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_unit_complex_out_raw_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Remove negative frequencies
+ signal wpfb_complex_out_resized_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ -- Interleave positive frequencies per factor Q_fft = 2, like with output of real input FFT
+ signal wpfb_complex_out_fifo_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal wpfb_complex_out_fifo_siso_arr : t_dp_siso_arr(c_sdp_S_pn - 1 downto 0) := (others => c_dp_siso_rst);
+ signal wpfb_complex_out_resized_sosi_2arr : t_dp_sosi_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_sosi_rst));
+ signal wpfb_complex_out_resized_siso_2arr : t_dp_siso_2arr_2(c_sdp_P_pfb - 1 downto 0) := (others => (others => c_dp_siso_rst));
+ signal wpfb_complex_out_interleaved_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal subband_equalizer_in_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_quant_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal subband_equalizer_raw_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_selector_out_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_selector_pipe_sosi_arr : t_dp_sosi_arr(c_sdp_R_os * c_sdp_P_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+ signal scope_equalizer_in_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
+ signal scope_equalizer_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_R_os * c_sdp_S_pn - 1 downto 0);
+
+ signal selector_en : std_logic;
+ signal weighted_subbands_flag : std_logic;
+
+ signal dp_bsn_source_restart_pipe : std_logic;
+ signal dp_bsn_source_restart_delayed : std_logic;
+ signal dp_bsn_source_restart_wg : std_logic;
+ signal dp_bsn_source_restart_pipe_complex : std_logic;
begin
---------------------------------------------------------------
-- SPECTRAL INVERSION
---------------------------------------------------------------
u_si_arr : entity si_lib.si_arr
- generic map (
- g_nof_streams => c_sdp_S_pn,
- g_pipeline => c_si_pipeline,
- g_dat_w => c_sdp_W_adc
- )
- port map(
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => si_sosi_arr,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst
- );
+ generic map (
+ g_nof_streams => c_sdp_S_pn,
+ g_pipeline => c_si_pipeline,
+ g_dat_w => c_sdp_W_adc
+ )
+ port map(
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => si_sosi_arr,
+
+ reg_si_mosi => reg_si_mosi,
+ reg_si_miso => reg_si_miso,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst
+ );
---------------------------------------------------------------
-- POLY-PHASE FILTERBANK
@@ -251,42 +253,42 @@ begin
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_si_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart,
- out_dat => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_pipeline => c_si_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart,
+ out_dat => dp_bsn_source_restart_pipe
+ );
-- PFB
u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
-
- in_sosi_arr => wpfb_unit_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe
- );
+ generic map (
+ g_wpfb => g_wpfb,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(0),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(0),
+
+ in_sosi_arr => wpfb_unit_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe
+ );
---------------------------------------------------------------
-- POLY-PHASE COMPLEX FILTERBANK
@@ -295,18 +297,18 @@ begin
-- real part is in LSB and imaginary part in MSB.
-- Waveform buffer
u_buf : entity common_lib.common_rom
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- rd_adr => wg_address,
- rd_en => wg_rd,
- rd_val => wg_rdval,
- rd_dat => wg_rddata
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ rd_adr => wg_address,
+ rd_en => wg_rd,
+ rd_val => wg_rdval,
+ rd_dat => wg_rddata
+ );
-- Waveform generator as local oscillator.
p_lo_restart : process(dp_clk, dp_rst)
@@ -327,101 +329,102 @@ begin
end process;
u_lo_wg : entity diag_lib.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_rate_offset => c_wg_phase_offset,
- g_calc_support => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- restart => dp_bsn_source_restart_wg,
-
- buf_rddat => wg_rddata,
- buf_rdval => wg_rdval,
- buf_addr => wg_address,
- buf_rden => wg_rd,
-
- ctrl => c_wg_ctrl,
-
- out_dat => wg_out_dat,
- out_val => open
- );
-
- -- Complex mult
- gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
- u_common_complex_mult : entity common_mult_lib.common_complex_mult
generic map (
- g_in_a_w => c_sdp_W_local_oscillator, -- = 16
- g_in_b_w => c_sdp_W_adc, -- = 14
- g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
- g_conjugate_b => false
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_rate_offset => c_wg_phase_offset,
+ g_calc_support => false
)
port map (
- clk => dp_clk,
- clken => '1',
- rst => dp_rst,
- in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
- in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
- in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
- in_bi => (others => '0'),
- in_val => si_sosi_arr(I).valid,
- out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
- out_val => mixer_complex_mult_src_out_arr(I).valid
+ rst => dp_rst,
+ clk => dp_clk,
+ restart => dp_bsn_source_restart_wg,
+
+ buf_rddat => wg_rddata,
+ buf_rdval => wg_rdval,
+ buf_addr => wg_address,
+ buf_rden => wg_rd,
+
+ ctrl => c_wg_ctrl,
+
+ out_dat => wg_out_dat,
+ out_val => open
);
+ -- Complex mult
+ gen_complex_mult: for I in 0 to c_sdp_S_pn - 1 generate
+ u_common_complex_mult : entity common_mult_lib.common_complex_mult
+ generic map (
+ g_in_a_w => c_sdp_W_local_oscillator, -- = 16
+ g_in_b_w => c_sdp_W_adc, -- = 14
+ g_out_p_w => c_sdp_W_local_oscillator + c_sdp_W_adc, -- = 16 + 14 = 30
+ g_conjugate_b => false
+ )
+ port map (
+ clk => dp_clk,
+ clken => '1',
+ rst => dp_rst,
+ in_ar => wg_out_dat(c_sdp_W_local_oscillator - 1 downto 0),
+ in_ai => wg_out_dat(2 * c_sdp_W_local_oscillator - 1 downto c_sdp_W_local_oscillator),
+ in_br => si_sosi_arr(I).data(c_sdp_W_adc - 1 downto 0),
+ in_bi => (others => '0'),
+ in_val => si_sosi_arr(I).valid,
+ out_pr => mixer_complex_mult_src_out_arr(I).re(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_pi => mixer_complex_mult_src_out_arr(I).im(c_sdp_W_local_oscillator + c_sdp_W_adc - 1 downto 0),
+ out_val => mixer_complex_mult_src_out_arr(I).valid
+ );
+
--requantize
u_dp_requantize : entity dp_lib.dp_requantize
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_local_oscillator_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 0,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
+ g_out_dat_w => c_sdp_W_adc
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => mixer_complex_mult_src_out_arr(I),
+ -- ST source
+ src_out => mixer_complex_requantize_src_out_arr(I)
+ );
+ end generate;
+
+ -- Pipeline to compensate for complex mult and dp_requantize.
+ u_dp_pipeline : entity dp_lib.dp_pipeline
generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_local_oscillator_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true,
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 0,
- g_pipeline_remove_msb => 0,
- g_in_dat_w => c_sdp_W_local_oscillator + c_sdp_W_adc,
- g_out_dat_w => c_sdp_W_adc
+ g_pipeline => c_complex_mult_pipeline
)
port map (
rst => dp_rst,
clk => dp_clk,
-- ST sink
- snk_in => mixer_complex_mult_src_out_arr(I),
+ snk_in => si_sosi_arr(0),
-- ST source
- src_out => mixer_complex_requantize_src_out_arr(I)
+ src_out => si_sosi_0_piped
);
- end generate;
-
- -- Pipeline to compensate for complex mult and dp_requantize.
- u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => si_sosi_arr(0),
- -- ST source
- src_out => si_sosi_0_piped
- );
-- pipeline bsn restart signal to keep dp_bsn_source_restart aligned with si_sosi_arr
u_common_pipeline_sl_cplx : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_complex_mult_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_dat => dp_bsn_source_restart_pipe,
- out_dat => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_pipeline => c_complex_mult_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => dp_bsn_source_restart_pipe,
+ out_dat => dp_bsn_source_restart_pipe_complex
+ );
+
process(mixer_complex_requantize_src_out_arr, si_sosi_0_piped)
begin
for I in 0 to c_sdp_S_pn - 1 loop
@@ -433,30 +436,30 @@ begin
-- PFB complex
u_wpfb_unit_dev_complex : entity wpfb_lib.wpfb_unit_dev
- generic map (
- g_wpfb => g_wpfb_complex,
- g_use_prefilter => true,
- g_stats_ena => false,
- g_use_bg => false,
- g_coefs_file_prefix => c_coefs_file_prefix,
- g_restart_on_valid => false
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
- ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
-
- in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
- fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
- out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
- out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
-
- dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
- );
+ generic map (
+ g_wpfb => g_wpfb_complex,
+ g_use_prefilter => true,
+ g_stats_ena => false,
+ g_use_bg => false,
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => false
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi_arr(1),
+ ram_fil_coefs_miso => ram_fil_coefs_miso_arr(1),
+
+ in_sosi_arr => wpfb_unit_complex_in_sosi_arr,
+ fil_sosi_arr => wpfb_unit_complex_fil_sosi_arr,
+ out_quant_sosi_arr => wpfb_unit_complex_out_quant_sosi_arr,
+ out_raw_sosi_arr => wpfb_unit_complex_out_raw_sosi_arr,
+
+ dp_bsn_source_restart => dp_bsn_source_restart_pipe_complex
+ );
---------------------------------------------------------------
-- Interleave for PFB complex
@@ -493,7 +496,7 @@ begin
snk_in => wpfb_complex_out_resized_sosi_arr(I),
src_out => wpfb_complex_out_fifo_sosi_arr(I),
src_in => wpfb_complex_out_fifo_siso_arr(I)
- );
+ );
end generate;
-- rewire 1d array of 1 X S_pn to 2d array of 2 X P_pfb
@@ -516,7 +519,7 @@ begin
snk_in_arr => wpfb_complex_out_resized_sosi_2arr(I),
snk_out_arr => wpfb_complex_out_resized_siso_2arr(I),
src_out => wpfb_complex_out_interleaved_sosi_arr(I)
- );
+ );
-- Align data width of wpfb_complex output with wpfb_real output as the real wpfb
-- has an extra bit that is used for the FFT seperate function which the complex FFT
@@ -528,7 +531,6 @@ begin
subband_equalizer_in_sosi_arr(c_sdp_P_pfb + I).re <= SHIFT_SVEC(wpfb_complex_out_interleaved_sosi_arr(I).re, c_dat_w_diff);
subband_equalizer_in_sosi_arr(c_sdp_P_pfb + I).im <= SHIFT_SVEC(wpfb_complex_out_interleaved_sosi_arr(I).im, c_dat_w_diff);
end process;
-
end generate;
-- Pipeline to compensate for longer latency of the complex PFB.
@@ -550,16 +552,16 @@ begin
-- COMBINE MEMORY MAPPED INTERFACES OF RAM_FIL_COEFS
---------------------------------------------------------------
u_mem_mux_coef : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os,
- g_mult_addr_w => c_fil_coefs_mem_addr_w
- )
- port map (
- mosi => ram_fil_coefs_mosi,
- miso => ram_fil_coefs_miso,
- mosi_arr => ram_fil_coefs_mosi_arr,
- miso_arr => ram_fil_coefs_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os,
+ g_mult_addr_w => c_fil_coefs_mem_addr_w
+ )
+ port map (
+ mosi => ram_fil_coefs_mosi,
+ miso => ram_fil_coefs_miso,
+ mosi_arr => ram_fil_coefs_mosi_arr,
+ miso_arr => ram_fil_coefs_miso_arr
+ );
---------------------------------------------------------------
-- SUBBAND EQUALIZER
@@ -702,16 +704,16 @@ begin
-- Combine the internal array of mm interfaces for the subband
-- statistics to one array.
u_mem_mux_sst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
- g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
- )
- port map (
- mosi => master_mem_mux_mosi,
- miso => master_mem_mux_miso,
- mosi_arr => ram_st_sst_mosi_arr,
- miso_arr => ram_st_sst_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_R_os * c_sdp_P_pfb,
+ g_mult_addr_w => ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * g_wpfb.stat_data_sz)
+ )
+ port map (
+ mosi => master_mem_mux_mosi,
+ miso => master_mem_mux_miso,
+ mosi_arr => ram_st_sst_mosi_arr,
+ miso_arr => ram_st_sst_miso_arr
+ );
-- Connect 2 mm_masters to the common_mem_mux output
master_mosi_arr(0) <= ram_st_sst_mosi; -- MM access via QSYS MM bus
@@ -720,18 +722,18 @@ begin
ram_st_offload_miso <= master_miso_arr(1);
u_mem_master_mux : entity mm_lib.mm_master_mux
- generic map (
- g_nof_masters => c_nof_masters,
- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
- )
- port map (
- mm_clk => mm_clk,
-
- master_mosi_arr => master_mosi_arr,
- master_miso_arr => master_miso_arr,
- mux_mosi => master_mem_mux_mosi,
- mux_miso => master_mem_mux_miso
- );
+ generic map (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ port map (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- STATISTICS OFFLOAD
@@ -739,41 +741,41 @@ begin
weighted_subbands_flag <= not selector_en when rising_edge(dp_clk);
u_sdp_sst_udp_offload: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => "SST_OS",
- g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_statistics_type => "SST_OS",
+ g_offload_time => sel_a_b(g_sim, g_sim_sdp.offload_time, c_sdp_offload_time)
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- master_mosi => ram_st_offload_mosi,
- master_miso => ram_st_offload_miso,
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
- in_sosi => dp_selector_out_sosi_arr(0),
- new_interval => dp_bsn_source_new_interval,
+ in_sosi => dp_selector_out_sosi_arr(0),
+ new_interval => dp_bsn_source_new_interval,
- out_sosi => sst_udp_sosi,
- out_siso => sst_udp_siso,
+ out_sosi => sst_udp_sosi,
+ out_siso => sst_udp_siso,
- eth_src_mac => eth_src_mac,
- udp_src_port => udp_src_port,
- ip_src_addr => ip_src_addr,
+ eth_src_mac => eth_src_mac,
+ udp_src_port => udp_src_port,
+ ip_src_addr => ip_src_addr,
- gn_index => TO_UINT(gn_id),
- sdp_info => sdp_info,
- weighted_subbands_flag => weighted_subbands_flag
- );
+ gn_index => TO_UINT(gn_id),
+ sdp_info => sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
index 35d4a7135c9afaf6b2d618c5d91cfb62c7fa5c9d..1c8d106ccd74952449ec24a6f41e4c2b0956b341 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_destinations_reg.vhd
@@ -71,108 +71,108 @@ end sdp_bdo_destinations_reg;
architecture str of sdp_bdo_destinations_reg is
constant c_field_arr : t_common_field_arr(c_sdp_bdo_destinations_info_nof_hdr_fields - 1 downto 0) :=
( (field_name_pad("nof_blocks_per_packet"), "RO", 8, field_default(c_sdp_cep_nof_blocks_per_packet)),
- (field_name_pad("nof_destinations_max"), "RO", 8, field_default(g_nof_destinations_max)),
- (field_name_pad("nof_destinations_act"), "RO", 8, field_default(1)),
- (field_name_pad("nof_destinations"), "RW", 8, field_default(1)),
+ (field_name_pad("nof_destinations_max"), "RO", 8, field_default(g_nof_destinations_max)),
+ (field_name_pad("nof_destinations_act"), "RO", 8, field_default(1)),
+ (field_name_pad("nof_destinations"), "RW", 8, field_default(1)),
- (field_name_pad("udp_destination_port_31"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_30"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_29"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_28"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_27"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_26"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_25"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_24"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_23"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_22"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_21"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_20"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_19"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_18"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_17"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_16"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_15"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_14"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_13"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_12"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_11"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_10"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_9"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_8"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_7"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_6"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_5"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_4"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_3"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_2"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_1"), "RW", 16, field_default(0)),
- (field_name_pad("udp_destination_port_0"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_31"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_30"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_29"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_28"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_27"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_26"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_25"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_24"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_23"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_22"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_21"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_20"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_19"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_18"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_17"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_16"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_15"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_14"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_13"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_12"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_11"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_10"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_9"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_8"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_7"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_6"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_5"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_4"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_3"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_2"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_1"), "RW", 16, field_default(0)),
+ (field_name_pad("udp_destination_port_0"), "RW", 16, field_default(0)),
- (field_name_pad("ip_destination_address_31"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_30"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_29"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_28"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_27"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_26"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_25"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_24"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_23"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_22"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_21"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_20"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_19"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_18"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_17"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_16"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_15"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_14"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_13"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_12"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_11"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_10"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_9"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_8"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_7"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_6"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_5"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_4"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_3"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_2"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_1"), "RW", 32, field_default(0)),
- (field_name_pad("ip_destination_address_0"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_31"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_30"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_29"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_28"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_27"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_26"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_25"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_24"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_23"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_22"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_21"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_20"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_19"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_18"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_17"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_16"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_15"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_14"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_13"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_12"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_11"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_10"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_9"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_8"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_7"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_6"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_5"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_4"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_3"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_2"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_1"), "RW", 32, field_default(0)),
+ (field_name_pad("ip_destination_address_0"), "RW", 32, field_default(0)),
- (field_name_pad("eth_destination_mac_31"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_30"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_29"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_28"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_27"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_26"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_25"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_24"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_23"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_22"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_21"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_20"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_19"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_18"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_17"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_16"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_15"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_14"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_13"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_12"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_11"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_10"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_9"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_8"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_7"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_6"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_5"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_4"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_3"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_2"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_1"), "RW", 48, field_default(0)),
- (field_name_pad("eth_destination_mac_0"), "RW", 48, field_default(0)) );
+ (field_name_pad("eth_destination_mac_31"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_30"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_29"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_28"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_27"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_26"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_25"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_24"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_23"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_22"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_21"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_20"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_19"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_18"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_17"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_16"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_15"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_14"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_13"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_12"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_11"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_10"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_9"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_8"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_7"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_6"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_5"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_4"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_3"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_2"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_1"), "RW", 48, field_default(0)),
+ (field_name_pad("eth_destination_mac_0"), "RW", 48, field_default(0)) );
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -186,8 +186,8 @@ begin
destinations_info <= destinations_info_rd;
p_destinations_info_rd : process(destinations_info_wr,
- nof_destinations_act,
- nof_blocks_per_packet)
+ nof_destinations_act,
+ nof_blocks_per_packet)
begin
-- read/write fields
for DI in 0 to g_nof_destinations_max - 1 loop
@@ -207,32 +207,32 @@ begin
end process;
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- -- With g_nof_destinations_max = 31 and mac_w = 48, ip_w = 32, udp_w = 16
- -- the expected logic FF usage is 31 * (48 + 32 + 16) + 4 * 32 ~= 3104 FF.
- -- Use g_cross_clock_domain false to save clock domain crossing logic,
- -- which is about 2/3 of the total logic (~ 6200 FF). This is save,
- -- because the reg fields are set well before they are used, so any meta
- -- stability will have settled long before that.
- g_cross_clock_domain => false,
- g_use_slv_in_val => false, -- use false to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ -- With g_nof_destinations_max = 31 and mac_w = 48, ip_w = 32, udp_w = 16
+ -- the expected logic FF usage is 31 * (48 + 32 + 16) + 4 * 32 ~= 3104 FF.
+ -- Use g_cross_clock_domain false to save clock domain crossing logic,
+ -- which is about 2/3 of the total logic (~ 6200 FF). This is save,
+ -- because the reg fields are set well before they are used, so any meta
+ -- stability will have settled long before that.
+ g_cross_clock_domain => false,
+ g_use_slv_in_val => false, -- use false to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_copi,
- mm_miso => reg_cipo,
+ mm_mosi => reg_copi,
+ mm_miso => reg_cipo,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- add "RO" fields to mm_fields
mm_fields_in(field_hi(c_field_arr, "nof_destinations_act") downto field_lo(c_field_arr, "nof_destinations_act")) <= to_uvec(destinations_info_rd.nof_destinations_act, 8);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_multiple_destinations.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_multiple_destinations.vhd
index ab82c282e39d20b888d25954b11cc0316355a005..63166c695181afca9ec7fc16f86149567758e867 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_multiple_destinations.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_multiple_destinations.vhd
@@ -98,17 +98,17 @@ architecture str of sdp_bdo_multiple_destinations is
-- Look up table constants as function of nof_destinations in range(g_nof_destinations_max)
constant c_m : natural := g_nof_destinations_max;
constant c_reorder_nof_blocks_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_reorder_nof_blocks_look_up_table(c_m);
+ func_sdp_bdo_reorder_nof_blocks_look_up_table(c_m);
constant c_reorder_nof_ch_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_reorder_nof_ch_look_up_table(c_m);
+ func_sdp_bdo_reorder_nof_ch_look_up_table(c_m);
constant c_nof_beamlets_per_block_first_destinations_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_m);
+ func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_m);
constant c_nof_beamlets_per_block_last_destination_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_m);
+ func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_m);
constant c_nof_ch_per_packet_first_destinations_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_nof_ch_per_packet_first_destinations_look_up_table(c_m);
+ func_sdp_bdo_nof_ch_per_packet_first_destinations_look_up_table(c_m);
constant c_nof_ch_per_packet_last_destination_arr : t_natural_arr(1 to c_m) :=
- func_sdp_bdo_nof_ch_per_packet_last_destination_look_up_table(c_m);
+ func_sdp_bdo_nof_ch_per_packet_last_destination_look_up_table(c_m);
constant c_nof_ch_per_packet_max : natural := largest(c_nof_ch_per_packet_first_destinations_arr);
constant c_nof_ch_per_packet_w : natural := ceil_log2(c_nof_ch_per_packet_max + 1);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_one_destination.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_one_destination.vhd
index 4403f42f09f5178ce27b364f7df6218e73bd9adc..0aa1b6a265eb2de6199dbd36333ca05b8c1bab28 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_one_destination.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_one_destination.vhd
@@ -68,13 +68,13 @@ architecture str of sdp_bdo_one_destination is
-- Use c_transpose_indices for func_reorder_transpose() in this sdp_bdo_one_destination,
-- a tb can then use c_transpose_indices_inv to undo the transpose.
constant c_transpose_indices : t_natural_arr(0 to c_nof_ch - 1) :=
- func_reorder_transpose_indices(c_nof_blocks_per_packet,
- c_nof_beamlets_per_block,
- c_nof_words_per_beamlet);
+ func_reorder_transpose_indices(c_nof_blocks_per_packet,
+ c_nof_beamlets_per_block,
+ c_nof_words_per_beamlet);
constant c_transpose_indices_inv : t_natural_arr(0 to c_nof_ch - 1) :=
- func_reorder_transpose_indices(c_nof_beamlets_per_block,
- c_nof_blocks_per_packet,
- c_nof_words_per_beamlet);
+ func_reorder_transpose_indices(c_nof_beamlets_per_block,
+ c_nof_blocks_per_packet,
+ c_nof_words_per_beamlet);
-- Dynamic reorder block size control input
-- . The data consists of 1 word = 1 ch, because 1 word contains 1 dual pol beamlet.
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
index e33f2166ab48f8e3c6b0c3ba91232a8b110323fb..0a2fa53d11c5d8a0e4ff21d882b07e2d14aed1b3 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
@@ -28,9 +28,9 @@
-- . [1] https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Multiple+beamlet+output+destinations
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.sdp_pkg.all;
package sdp_bdo_pkg is
-- Beamlet data output (BDO) for multiple destinations
@@ -62,8 +62,8 @@ package sdp_bdo_pkg is
constant c_sdp_bdo_reorder_nof_blocks_max : natural := 16;
constant c_sdp_bdo_reorder_nof_blocks_w : natural := ceil_log2(c_sdp_bdo_reorder_nof_blocks_max + 1);
constant c_sdp_bdo_reorder_nof_ch_max : natural := c_sdp_bdo_reorder_nof_blocks_max *
- c_sdp_nof_beamlets_per_block *
- c_sdp_nof_words_per_beamlet; -- = 7808
+ c_sdp_nof_beamlets_per_block *
+ c_sdp_nof_words_per_beamlet; -- = 7808
-- 32 * 3 + 4 = 100 fields
constant c_sdp_bdo_destinations_info_nof_hdr_fields : natural := c_sdp_bdo_mm_nof_destinations_max * 3 + 4;
@@ -80,12 +80,12 @@ package sdp_bdo_pkg is
constant c_sdp_bdo_destinations_info_rst : t_sdp_bdo_destinations_info :=
( (others => (others => '0')),
- (others => (others => '0')),
- (others => (others => '0')),
- 1,
- 1,
- 1,
- c_sdp_cep_nof_blocks_per_packet);
+ (others => (others => '0')),
+ (others => (others => '0')),
+ 1,
+ 1,
+ 1,
+ c_sdp_cep_nof_blocks_per_packet);
-- Parse user input to determine actual nof_destinations
function func_sdp_bdo_parse_nof_destinations(nof_destinations, c_nof_destinations_max : natural) return natural;
@@ -111,7 +111,7 @@ end package sdp_bdo_pkg;
package body sdp_bdo_pkg is
function func_sdp_bdo_parse_nof_destinations(nof_destinations, c_nof_destinations_max : natural) return natural is
constant c_last_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_nof_destinations_max);
variable v_DN : natural := 1;
begin
-- Parse input nof_destinations value
@@ -156,7 +156,7 @@ package body sdp_bdo_pkg is
function func_sdp_bdo_reorder_nof_ch_look_up_table(c_nof_destinations_max : natural) return t_natural_arr is
constant c_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
variable v_arr : t_natural_arr(1 to c_nof_destinations_max);
begin
-- Determine reorder nof_ch as function of number of destinations DN.
@@ -188,7 +188,7 @@ package body sdp_bdo_pkg is
function func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_nof_destinations_max : natural) return t_natural_arr is
variable v_first_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
variable v_last_arr : t_natural_arr(1 to c_nof_destinations_max);
variable v_last : integer;
begin
@@ -230,9 +230,9 @@ package body sdp_bdo_pkg is
function func_sdp_bdo_nof_ch_per_packet_first_destinations_look_up_table(c_nof_destinations_max : natural) return t_natural_arr is
constant c_nof_blocks_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
constant c_nof_beamlets_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
variable v_len_arr : t_natural_arr(1 to c_nof_destinations_max);
begin
-- Determine nof_ch per packet for the first 1:DN-1 destinations, as
@@ -257,9 +257,9 @@ package body sdp_bdo_pkg is
function func_sdp_bdo_nof_ch_per_packet_last_destination_look_up_table(c_nof_destinations_max : natural) return t_natural_arr is
constant c_nof_blocks_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
constant c_nof_beamlets_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_last_destination_look_up_table(c_nof_destinations_max);
variable v_len_arr : t_natural_arr(1 to c_nof_destinations_max);
begin
-- Determine nof_ch per packet for the first 1:DN-1 destinations, as
@@ -277,9 +277,9 @@ package body sdp_bdo_pkg is
function func_sdp_bdo_beamlet_index_per_destination_look_up_matrix(c_nof_destinations_max : natural) return t_natural_matrix is
constant c_len_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
variable v_index_mat : t_natural_matrix(1 to c_nof_destinations_max,
- 0 to c_nof_destinations_max - 1);
+ 0 to c_nof_destinations_max - 1);
variable v_beamlet_index : natural;
variable v_step : natural;
begin
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index 8281d80b1bd11b173bc637046d00f1ebb78177cc..8acf80b57a5cb073fbce1c99e3e5b7a23ae49acb 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -31,11 +31,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_local is
generic (
@@ -97,6 +97,7 @@ begin
-- Use short index variables PB (= Polarization Beamlet), I (= Instance)
-- names, to ease recognizing them as loop indices.
gen_pol : for PB in 0 to c_sdp_N_pol_bf - 1 generate
+
gen_pfb : for I in 0 to c_sdp_P_pfb - 1 generate
sub_sosi_arr(PB * c_sdp_P_pfb + I) <= in_sosi_arr(I);
end generate;
@@ -135,17 +136,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_x_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_x_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_x_sosi_arr(I),
- src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_x_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_x_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -153,17 +154,17 @@ begin
---------------------------------------------------------------
gen_deinterleave_y_pol : for I in 0 to c_sdp_P_pfb - 1 generate
u_dp_deinterleave_y_pol : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_nof_outputs => c_sdp_Q_fft
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_weights_y_sosi_arr(I),
- src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
- src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
- );
+ generic map(
+ g_nof_outputs => c_sdp_Q_fft
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_weights_y_sosi_arr(I),
+ src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I),
+ src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft * I + 1)
+ );
end generate;
---------------------------------------------------------------
@@ -171,48 +172,48 @@ begin
---------------------------------------------------------------
gen_interleave : for I in 0 to c_sdp_S_pn - 1 generate
u_dp_interleave : entity dp_lib.dp_interleave_n_to_one
+ generic map(
+ g_nof_inputs => c_sdp_N_pol_bf
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
+ snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
+ src_out => interleave_out_sosi_arr(I)
+ );
+ end generate;
+
+ ---------------------------------------------------------------
+ -- ADD
+ ---------------------------------------------------------------
+ u_dp_complex_add : entity dp_lib.dp_complex_add
generic map(
- g_nof_inputs => c_sdp_N_pol_bf
+ g_nof_inputs => c_sdp_S_pn,
+ g_data_w => c_product_w
)
port map(
rst => dp_rst,
clk => dp_clk,
- snk_in_arr(0) => deinterleaved_x_sosi_arr(I),
- snk_in_arr(1) => deinterleaved_y_sosi_arr(I),
- src_out => interleave_out_sosi_arr(I)
+ snk_in_arr => interleave_out_sosi_arr,
+ src_out => complex_add_out_sosi
);
- end generate;
-
- ---------------------------------------------------------------
- -- ADD
- ---------------------------------------------------------------
- u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_S_pn,
- g_data_w => c_product_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => interleave_out_sosi_arr,
- src_out => complex_add_out_sosi
- );
---------------------------------------------------------------
-- DP PIPELINE IN_SOSI FIELDS
---------------------------------------------------------------
u_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_total_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(0),
- src_out => pipelined_in_sosi
- );
+ generic map (
+ g_pipeline => c_total_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(0),
+ src_out => pipelined_in_sosi
+ );
---------------------------------------------------------------
-- COMBINE OUTPUT WITH PIPELINED IN_SOSI
@@ -228,25 +229,25 @@ begin
-- REQUANTIZE
---------------------------------------------------------------
u_dp_requantize : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => false, -- wrap beamlet overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => 1,
- g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
- g_in_dat_w => c_complex_adder_sum_w,
- g_out_dat_w => c_sdp_W_beamlet_sum
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_requantize_in_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_bf_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => false, -- wrap beamlet overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => 1,
+ g_pipeline_remove_msb => 0, -- no msb clipping, so no need for pipeline
+ g_in_dat_w => c_complex_adder_sum_w,
+ g_out_dat_w => c_sdp_W_beamlet_sum
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_requantize_in_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 32cf827e7379b943f1094e86295de43e4c543b05..22f067725785f58ab39485e9426935ab53a06cf1 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -33,16 +33,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use work.sdp_pkg.all;
-use work.sdp_bdo_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use work.sdp_pkg.all;
+ use work.sdp_bdo_pkg.all;
entity sdp_beamformer_output is
generic (
@@ -109,12 +109,12 @@ architecture str of sdp_beamformer_output is
constant c_nof_destinations_w : natural := ceil_log2(g_nof_destinations_max + 1);
constant c_beamlet_index_per_destination_mat : t_natural_matrix(1 to g_nof_destinations_max, 0 to g_nof_destinations_max - 1) :=
- func_sdp_bdo_beamlet_index_per_destination_look_up_matrix(g_nof_destinations_max);
+ func_sdp_bdo_beamlet_index_per_destination_look_up_matrix(g_nof_destinations_max);
-- . field_sel = '0' for DP (dynamic), '1' for MM (fixed or programmable via MM of dp_offload_tx_v3)
constant c_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) :=
- sel_a_b(g_nof_destinations_max = 1, func_sdp_cep_hdr_field_sel_dst('1'),
- func_sdp_cep_hdr_field_sel_dst('0'));
+ sel_a_b(g_nof_destinations_max = 1, func_sdp_cep_hdr_field_sel_dst('1'),
+ func_sdp_cep_hdr_field_sel_dst('0'));
-- BDO packet size control
-- . One 32b word contains 1 dual pol beamlet of 4 octets (Xre, Xim, Yre, Yim).
@@ -184,7 +184,7 @@ begin
begin
snk_in_concat <= in_sosi;
snk_in_concat.data(c_data_w - 1 downto 0) <= in_sosi.re(c_sdp_W_beamlet - 1 downto 0) &
- in_sosi.im(c_sdp_W_beamlet - 1 downto 0);
+ in_sosi.im(c_sdp_W_beamlet - 1 downto 0);
---------------------------------------------------------------------------
-- synthesis translate_off
@@ -204,7 +204,7 @@ begin
v_ref_time := v_ref_time + c_sdp_block_period * 1 ns;
end if;
elsif NOW > v_ref_time + 1 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns and
- NOW < v_ref_time + 4 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns then
+ NOW < v_ref_time + 4 * c_sdp_cep_nof_blocks_per_packet * c_sdp_block_period * 1 ns then
-- Disturb BSN to cause merged payload error. Expected results for the
-- merged blocks:
-- . index 0 : First merged block bsn ok and payload_error = '0'.
@@ -231,22 +231,22 @@ begin
-- . No need to flow control the source, because repack into wider words
-----------------------------------------------------------------------------
u_dp_repack_data_beamlet : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w, -- = 16b
- g_in_nof_words => c_sdp_N_pol_bf, -- = 2
- g_out_dat_w => c_sdp_W_dual_pol_beamlet, -- = 32b
- g_out_nof_words => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in => snk_in_concat,
- snk_out => OPEN,
-
- src_out => dp_repack_beamlet_src_out,
- src_in => c_dp_siso_rdy
- );
+ generic map (
+ g_in_dat_w => c_data_w, -- = 16b
+ g_in_nof_words => c_sdp_N_pol_bf, -- = 2
+ g_out_dat_w => c_sdp_W_dual_pol_beamlet, -- = 32b
+ g_out_nof_words => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in => snk_in_concat,
+ snk_out => OPEN,
+
+ src_out => dp_repack_beamlet_src_out,
+ src_in => c_dp_siso_rdy
+ );
-- Debug signals for view in Wave window
-- [0:3] = [Xre, Xim, Yre, Yim]
@@ -361,22 +361,22 @@ begin
-- . No need to flow control the source, because repack into wider words
-----------------------------------------------------------------------------
u_dp_repack_data_longword : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_sdp_W_dual_pol_beamlet, -- = 32b
- g_in_nof_words => c_sdp_nof_beamlets_per_longword, -- = 2
- g_out_dat_w => c_longword_w, -- = 64b
- g_out_nof_words => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- snk_in => dp_packet_reorder_src_out,
- snk_out => OPEN,
-
- src_out => dp_repack_longword_src_out,
- src_in => c_dp_siso_rdy
- );
+ generic map (
+ g_in_dat_w => c_sdp_W_dual_pol_beamlet, -- = 32b
+ g_in_nof_words => c_sdp_nof_beamlets_per_longword, -- = 2
+ g_out_dat_w => c_longword_w, -- = 64b
+ g_out_nof_words => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in => dp_packet_reorder_src_out,
+ snk_out => OPEN,
+
+ src_out => dp_repack_longword_src_out,
+ src_in => c_dp_siso_rdy
+ );
dp_repack_longword <= unpack_data(dp_repack_longword_src_out.data(c_longword_w - 1 downto 0));
@@ -386,26 +386,26 @@ begin
-- Pass on dp_repack_longword_src_out.err field not here, but via separate
-- u_common_fifo_err.
u_dp_fifo_data : entity dp_lib.dp_fifo_fill_eop_sc
- generic map (
- g_data_w => c_longword_w,
- g_empty_w => c_byte_w,
- g_use_empty => true,
- g_use_bsn => true,
- g_use_channel => true,
- g_bsn_w => 64,
- g_channel_w => c_nof_destinations_w,
- g_use_sync => true,
- g_fifo_size => c_fifo_size,
- g_fifo_fill => c_fifo_fill,
- g_fifo_rl => 1
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
- snk_in => dp_repack_longword_src_out,
- src_out => dp_fifo_data_src_out,
- src_in => dp_fifo_data_src_in
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_empty_w => c_byte_w,
+ g_use_empty => true,
+ g_use_bsn => true,
+ g_use_channel => true,
+ g_bsn_w => 64,
+ g_channel_w => c_nof_destinations_w,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_rl => 1
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ snk_in => dp_repack_longword_src_out,
+ src_out => dp_fifo_data_src_out,
+ src_in => dp_fifo_data_src_in
+ );
-- FIFO: to store and align payload error bit from eop to sop
-- . The payload error bit is set when dp_packet_merge detects an BSN
@@ -424,34 +424,34 @@ begin
-- because the BDO packets are multiplexed round-robin with fair chance
-- per beamset by the dp_mux in sdp_station.vhd
u_common_fifo_err : entity common_lib.common_fifo_sc
- generic map (
- g_dat_w => 1,
- g_nof_words => c_sdp_N_beamsets + 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat => dp_repack_longword_src_out.err(0 downto 0),
- wr_req => dp_repack_longword_src_out.eop,
- rd_dat => payload_err,
- rd_req => dp_fifo_data_src_out.sop
- );
+ generic map (
+ g_dat_w => 1,
+ g_nof_words => c_sdp_N_beamsets + 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat => dp_repack_longword_src_out.err(0 downto 0),
+ wr_req => dp_repack_longword_src_out.eop,
+ rd_dat => payload_err,
+ rd_req => dp_fifo_data_src_out.sop
+ );
-- Pipeline dp_fifo_data_src_out to align payload_err at dp_pipeline_data_src_out.sop
u_pipeline_data : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_fifo_data_src_in,
- snk_in => dp_fifo_data_src_out,
- -- ST source
- src_in => dp_pipeline_data_src_in,
- src_out => dp_pipeline_data_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_fifo_data_src_in,
+ snk_in => dp_fifo_data_src_out,
+ -- ST source
+ src_in => dp_pipeline_data_src_in,
+ src_out => dp_pipeline_data_src_out
+ );
-----------------------------------------------------------------------------
-- Assemble offload info
@@ -512,8 +512,8 @@ begin
-- DP dp_bsn
p_assemble_offload_info : process(mdi_nof_blocks_per_packet,
- mdi_nof_beamlets_per_block_per_destination,
- mdi_beamlet_index_per_destination)
+ mdi_nof_beamlets_per_block_per_destination,
+ mdi_beamlet_index_per_destination)
begin
if g_nof_destinations_max = 1 then
-- Use constant defaults for beamlet data output to one destination.
@@ -571,87 +571,87 @@ begin
-- dp_offload_tx_v3
-----------------------------------------------------------------------------
u_dp_offload_tx_v3 : entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_hdr_field_sel => c_cep_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
-
- snk_in_arr(0) => dp_pipeline_data_src_out,
- snk_out_arr(0) => dp_pipeline_data_src_in,
-
- src_out_arr(0) => dp_offload_tx_src_out,
- src_in_arr(0) => dp_offload_tx_src_in,
-
- hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
- hdr_fields_out_arr(0) => hdr_fields_out
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_hdr_field_sel => c_cep_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+
+ snk_in_arr(0) => dp_pipeline_data_src_out,
+ snk_out_arr(0) => dp_pipeline_data_src_in,
+
+ src_out_arr(0) => dp_offload_tx_src_out,
+ src_in_arr(0) => dp_offload_tx_src_in,
+
+ hdr_fields_in_arr(0) => dp_offload_tx_hdr_fields,
+ hdr_fields_out_arr(0) => hdr_fields_out
+ );
-----------------------------------------------------------------------------
-- tr_10GbE_ip_checksum
-----------------------------------------------------------------------------
u_tr_10GbE_ip_checksum : entity tr_10GbE_lib.tr_10GbE_ip_checksum
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => dp_offload_tx_src_out,
- snk_out => dp_offload_tx_src_in,
+ snk_in => dp_offload_tx_src_out,
+ snk_out => dp_offload_tx_src_in,
- src_out => ip_checksum_src_out,
- src_in => ip_checksum_src_in
- );
+ src_out => ip_checksum_src_out,
+ src_in => ip_checksum_src_in
+ );
-----------------------------------------------------------------------------
-- dp_pipeline_ready to ease timing closure
-----------------------------------------------------------------------------
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => ip_checksum_src_in,
- snk_in => ip_checksum_src_out,
- src_in => dp_pipeline_ready_src_in,
- src_out => dp_pipeline_ready_src_out
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => ip_checksum_src_in,
+ snk_in => ip_checksum_src_out,
+ src_in => dp_pipeline_ready_src_in,
+ src_out => dp_pipeline_ready_src_out
+ );
-----------------------------------------------------------------------------
-- mms_dp_xonoff
-----------------------------------------------------------------------------
u_mms_dp_xonoff : entity dp_lib.mms_dp_xonoff
- generic map(
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_mosi,
- reg_miso => reg_dp_xonoff_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- ST sinks
- snk_out_arr(0) => dp_pipeline_ready_src_in,
- snk_in_arr(0) => dp_pipeline_ready_src_out,
- -- ST source
- src_in_arr(0) => out_siso,
- src_out_arr(0) => out_sosi
- );
+ generic map(
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_mosi,
+ reg_miso => reg_dp_xonoff_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- ST sinks
+ snk_out_arr(0) => dp_pipeline_ready_src_in,
+ snk_in_arr(0) => dp_pipeline_ready_src_out,
+ -- ST source
+ src_in_arr(0) => out_siso,
+ src_out_arr(0) => out_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 11f74388b5f5cb189b8d17adfe68ea0044199480..1de4f581c7a4466c00295b8d7765368ed33dd77a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -30,11 +30,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_beamformer_remote is
port (
@@ -65,7 +65,7 @@ end sdp_beamformer_remote;
architecture str of sdp_beamformer_remote is
constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet_sum;
constant c_block_size : natural := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
- constant c_fifo_size : natural := 2**ceil_log2((c_block_size * 9) / 16); -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
+ constant c_fifo_size : natural := 2 ** ceil_log2((c_block_size * 9) / 16); -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
signal dispatch_sosi_arr : t_dp_sosi_arr(c_dual - 1 downto 0) := (others => c_dp_sosi_rst); -- 1 for local, 1 for remote.
signal dp_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -87,84 +87,84 @@ begin
-- FIFO
---------------------------------------------------------------
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_longword_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => from_ri_sosi,
- src_in => dp_fifo_siso,
- src_out => dp_fifo_sosi
- );
+ generic map (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => from_ri_sosi,
+ src_in => dp_fifo_siso,
+ src_out => dp_fifo_sosi
+ );
---------------------------------------------------------------
-- Repack 64b to 36b
---------------------------------------------------------------
u_dp_repack_data_rx : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_longword_w,
- g_in_nof_words => 9, -- 9/16 = 36/64
- g_out_dat_w => c_data_w,
- g_out_nof_words => 16, -- 9/16 = 36/64
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_fifo_sosi,
- snk_out => dp_fifo_siso,
- src_out => dispatch_sosi_arr(1)
- );
+ generic map (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 9, -- 9/16 = 36/64
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => 16, -- 9/16 = 36/64
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sosi,
+ snk_out => dp_fifo_siso,
+ src_out => dispatch_sosi_arr(1)
+ );
---------------------------------------------------------------
-- dp_bsn_aligner_v2
---------------------------------------------------------------
u_mmp_dp_bsn_align_v2 : entity dp_lib.mmp_dp_bsn_align_v2
- generic map(
- -- for dp_bsn_align_v2
- g_nof_streams => c_dual,
- g_bsn_latency_max => 2, -- max 2 blocks latency
- g_nof_aligners_max => c_sdp_N_pn_max,
- g_block_size => c_block_size,
- g_data_w => c_data_w,
- g_use_mm_output => false,
- g_rd_latency => 1,
- -- for mms_dp_bsn_monitor_v2
- g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
- g_nof_input_bsn_monitors => c_dual,
- g_use_bsn_output_monitor => true
+ generic map(
+ -- for dp_bsn_align_v2
+ g_nof_streams => c_dual,
+ g_bsn_latency_max => 2, -- max 2 blocks latency
+ g_nof_aligners_max => c_sdp_N_pn_max,
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => false,
+ g_rd_latency => 1,
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => c_dual,
+ g_use_bsn_output_monitor => true
)
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- node_index => rn_index,
+ node_index => rn_index,
- -- Streaming input
- in_sosi_arr => dispatch_sosi_arr,
- out_sosi_arr => beamlets_data_sosi_arr
- );
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
+ out_sosi_arr => beamlets_data_sosi_arr
+ );
-- repacking beamlets data to re/im field.
p_wire_beamlets_sosi : process(beamlets_data_sosi_arr)
@@ -181,17 +181,17 @@ begin
-- ADD local + remote
---------------------------------------------------------------
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_dual,
- g_data_w => c_sdp_W_beamlet_sum
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => beamlets_sosi_arr,
- src_out => i_bf_sum_sosi
- );
+ generic map(
+ g_nof_inputs => c_dual,
+ g_data_w => c_sdp_W_beamlet_sum
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => beamlets_sosi_arr,
+ src_out => i_bf_sum_sosi
+ );
---------------------------------------------------------------
-- Local output
@@ -211,18 +211,18 @@ begin
end process;
u_dp_repack_data_local : entity dp_lib.dp_repack_data
- generic map (
- g_in_dat_w => c_data_w,
- g_in_nof_words => 16, -- 16/9 = 64/36
- g_out_dat_w => c_longword_w,
- g_out_nof_words => 9, -- 16/9 = 64/36
- g_pipeline_ready => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => bf_sum_data_sosi,
- src_out => to_ri_sosi
- );
+ generic map (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 16, -- 16/9 = 64/36
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 9, -- 16/9 = 64/36
+ g_pipeline_ready => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_sum_data_sosi,
+ src_out => to_ri_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 567bc51fb6c9d9c075bebdd60f9523ac9d0f2bdd..154879858c96780576690fe5ececf1884ba976f0 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -35,11 +35,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_bf_weights is
generic (
@@ -112,37 +112,38 @@ begin
end if;
end if;
end process;
+
gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);
---------------------------------------------------------------
-- Gain
---------------------------------------------------------------
u_mms_dp_gain_serial_arr : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
- g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_bf_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_streams => c_sdp_N_pol_bf * c_sdp_P_pfb,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_S_sub_bf,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_bf_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- -- ST interface
- gains_rd_address => gains_rd_address,
+ -- ST interface
+ gains_rd_address => gains_rd_address,
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 9296c034921d37dd48dfd5199116263e881872a5..a26b43953bb268987082c28f1f6b1458a0eaf17f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -45,12 +45,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib, st_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_crosslets_subband_select is
generic (
@@ -130,48 +130,48 @@ begin
-- BSN sync scheduler
---------------------------------------------------------------
u_mmp_dp_bsn_sync_scheduler_arr : entity dp_lib.mmp_dp_bsn_sync_scheduler_arr
- generic map (
- g_nof_streams => c_sdp_P_pfb,
- g_block_size => c_sdp_N_fft,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_miso => reg_bsn_sync_scheduler_xsub_miso,
-
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- out_start => start_trigger,
- out_start_interval => new_interval
- );
+ generic map (
+ g_nof_streams => c_sdp_P_pfb,
+ g_block_size => c_sdp_N_fft,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
+ reg_miso => reg_bsn_sync_scheduler_xsub_miso,
+
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ out_start => start_trigger,
+ out_start_interval => new_interval
+ );
---------------------------------------------------------------
-- Crosslets info
---------------------------------------------------------------
u_crosslets_info : entity common_lib.mms_common_reg
- generic map(
- g_mm_reg => c_sdp_mm_reg_crosslets_info
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- MM bus access in memory-mapped clock domain
- reg_mosi => reg_crosslets_info_mosi,
- reg_miso => reg_crosslets_info_miso,
-
- in_reg => crosslets_info_reg_in,
- out_reg => crosslets_info_reg
- );
+ generic map(
+ g_mm_reg => c_sdp_mm_reg_crosslets_info
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- MM bus access in memory-mapped clock domain
+ reg_mosi => reg_crosslets_info_mosi,
+ reg_miso => reg_crosslets_info_miso,
+
+ in_reg => crosslets_info_reg_in,
+ out_reg => crosslets_info_reg
+ );
p_set_unused_crosslets : process(cur_crosslets_info)
begin
@@ -266,62 +266,62 @@ begin
col_select_mosi <= r.col_select_mosi;
-- pipeline to time row select
u_pipe_row_select : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_row_select_pipeline,
- g_in_dat_w => c_row_select_slv_w,
- g_out_dat_w => c_row_select_slv_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_dat => r.row_select_slv,
- out_dat => row_select_slv
- );
+ generic map(
+ g_pipeline => c_row_select_pipeline,
+ g_in_dat_w => c_row_select_slv_w,
+ g_out_dat_w => c_row_select_slv_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_dat => r.row_select_slv,
+ out_dat => row_select_slv
+ );
---------------------------------------------------------------
-- Crosslet Select
---------------------------------------------------------------
u_reorder_col_wide_select : entity reorder_lib.reorder_col_wide_select
- generic map (
- g_nof_inputs => c_sdp_P_pfb,
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
- g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped
- col_select_mosi => col_select_mosi,
- col_select_miso => col_select_miso,
-
- -- Streaming
- input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
-
- output_sosi_arr => col_sosi_arr
- );
+ generic map (
+ g_nof_inputs => c_sdp_P_pfb,
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_ch_in => c_sdp_N_sub * c_sdp_Q_fft,
+ g_nof_ch_sel => g_N_crosslets * c_sdp_S_pn
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped
+ col_select_mosi => col_select_mosi,
+ col_select_miso => col_select_miso,
+
+ -- Streaming
+ input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
+
+ output_sosi_arr => col_sosi_arr
+ );
u_reorder_row_select : entity reorder_lib.reorder_row_select
- generic map (
- g_dsp_data_w => c_sdp_W_crosslet,
- g_nof_inputs => c_sdp_P_pfb,
- g_nof_outputs => 1,
- g_pipeline_in => 0,
- g_pipeline_in_m => 1,
- g_pipeline_out => 1
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_select => row_select_slv,
-
- -- Streaming
- input_sosi_arr => col_sosi_arr,
-
- output_sosi_arr(0) => row_sosi
- );
+ generic map (
+ g_dsp_data_w => c_sdp_W_crosslet,
+ g_nof_inputs => c_sdp_P_pfb,
+ g_nof_outputs => 1,
+ g_pipeline_in => 0,
+ g_pipeline_in_m => 1,
+ g_pipeline_out => 1
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_select => row_select_slv,
+
+ -- Streaming
+ input_sosi_arr => col_sosi_arr,
+
+ output_sosi_arr(0) => row_sosi
+ );
---------------------------------------------------------------
-- Out Crosslet info pipeline
@@ -334,48 +334,48 @@ begin
-- pipeline for alignment with sync
u_common_pipeline_cur : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => active_crosslets_info,
- out_dat => cur_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => active_crosslets_info,
+ out_dat => cur_crosslets_info
+ );
u_common_pipeline_prev : entity common_lib.common_pipeline
- generic map(
- g_pipeline => c_crosslets_info_dly,
- g_in_dat_w => c_sdp_crosslets_info_reg_w,
- g_out_dat_w => c_sdp_crosslets_info_reg_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- in_en => row_sosi.sync,
- in_dat => cur_crosslets_info,
- out_dat => prev_crosslets_info
- );
+ generic map(
+ g_pipeline => c_crosslets_info_dly,
+ g_in_dat_w => c_sdp_crosslets_info_reg_w,
+ g_out_dat_w => c_sdp_crosslets_info_reg_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_en => row_sosi.sync,
+ in_dat => cur_crosslets_info,
+ out_dat => prev_crosslets_info
+ );
---------------------------------------------------------------
-- Out sosi pipeline
---------------------------------------------------------------
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => c_out_sosi_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => row_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => c_out_sosi_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => row_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
-- Map crosslets_info slv to record for easier view in Wave window
crosslets_info_rec <= func_sdp_map_crosslets_info(crosslets_info_reg);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
index ba93d5bf2405af2d0ccdd5f517f258e1b9a146e6..7af75ff31af2a1c154d471e4c7cccf546660c208 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info is
port (
@@ -65,21 +65,21 @@ architecture str of sdp_info is
signal block_period: std_logic_vector(15 downto 0);
begin
u_mm_fields: entity work.sdp_info_reg
- port map (
+ port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- -- sdp info
- sdp_info_ro => sdp_info_ro,
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info_ro => sdp_info_ro,
+ sdp_info => sdp_info
+ );
-- f_adc : '0' => 160M, '1' => 200M
-- fsub_type: '0' => critical sampled PFB, '1' => oversampled PFB
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index 3feac6001af561964fa7328c52b3505040ee1f55..ff00ecd3b31e9840f95ca53fab94f71090d04bb4 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_info_reg is
port (
@@ -59,15 +59,15 @@ end sdp_info_reg;
architecture str of sdp_info_reg is
constant c_field_arr : t_common_field_arr(8 downto 0) :=
- ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
- (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
- (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
- (field_name_pad("observation_id"), "RW", 32, field_default(0)),
- (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
- (field_name_pad("f_adc"), "RO", 1, field_default(0)),
- (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
- (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
- (field_name_pad("block_period"), "RO", 16, field_default(0)) );
+ ( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
+ (field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
+ (field_name_pad("antenna_band_index"), "RW", 1, field_default(0)),
+ (field_name_pad("observation_id"), "RW", 32, field_default(0)),
+ (field_name_pad("nyquist_zone_index"), "RW", 2, field_default(0)),
+ (field_name_pad("f_adc"), "RO", 1, field_default(0)),
+ (field_name_pad("fsub_type"), "RO", 1, field_default(0)),
+ (field_name_pad("beam_repositioning_flag"), "RW", 1, field_default(0)),
+ (field_name_pad("block_period"), "RO", 16, field_default(0)) );
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -89,25 +89,25 @@ begin
end process;
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
-- add "RO" fields to mm_fields
mm_fields_in(field_hi(c_field_arr, "f_adc") downto field_lo(c_field_arr, "f_adc")) <= slv(sdp_info_rd.f_adc);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 0d029deee5d363a8e1c703dd7712f237de227266..3b81622b61981b5540e75e9790b9f1b3a54a5f92 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -28,18 +28,18 @@
-- . [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+SDP+Parameter+definitions
-------------------------------------------------------------------------------
library IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib, diag_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use rTwoSDF_lib.rTwoSDFPkg.all;
-use fft_lib.fft_pkg.all;
-use filter_lib.fil_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use tech_jesd204b_lib.tech_jesd204b_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use rTwoSDF_lib.rTwoSDFPkg.all;
+ use fft_lib.fft_pkg.all;
+ use filter_lib.fil_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use tech_jesd204b_lib.tech_jesd204b_pkg.all;
package sdp_pkg is
-------------------------------------------------
@@ -59,255 +59,255 @@ package sdp_pkg is
end record;
constant c_sdp_info_rst : t_sdp_info :=
- ( (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
- '0', '0', '0',
- (others => '0') );
-
- -------------------------------------------------
- -- SDP specific parameters as defined in [1]
- constant c_sdp_f_adc_MHz : natural := 200;
- constant c_sdp_N_band : natural := 2; -- 2 antenna bands, LB and HB
- constant c_sdp_N_beamsets : natural := 2; -- = N_beamsets_sdp in doc
- constant c_sdp_N_cross_sets_sdp : natural := 1;
- constant c_sdp_N_crosslets_max : natural := 7;
- constant c_sdp_N_fft : natural := 1024;
- constant c_sdp_N_pn_max : natural := 16; -- max 16 PN per ring = per antenna band
- constant c_sdp_N_pol : natural := 2;
- constant c_sdp_N_pol_bf : natural := 2;
- constant c_sdp_N_rings_sdp : natural := 1;
- constant c_sdp_N_ring_lanes_max : natural := 8; -- = N_lane in doc
- constant c_sdp_N_sub : natural := 512;
- constant c_sdp_N_sync_rcu : natural := 1;
- constant c_sdp_N_taps : natural := 16;
- constant c_sdp_P_sq : natural := 9; -- = N_pn / 2 + 1
- constant c_sdp_Q_fft : natural := 2;
- constant c_sdp_S_pn : natural := 12;
- constant c_sdp_S_rcu : natural := 3;
- constant c_sdp_S_sub_bf : natural := 488;
- constant c_sdp_R_os : natural := 2; -- Oversampling factor of 2 for PFB.
- constant c_sdp_V_ring_pkt_len_max : natural := 48; -- for 16 nodes
- constant c_sdp_V_sample_delay : natural := 4096;
- constant c_sdp_V_si_db : natural := 1024;
- constant c_sdp_V_si_db_large : natural := 131072;
- constant c_sdp_V_si_histogram : natural := 512;
- constant c_sdp_W_adc : natural := 14;
- constant c_sdp_W_adc_jesd : natural := 16;
- constant c_sdp_W_fir_coef : natural := 16;
- constant c_sdp_W_subband : natural := 18;
- constant c_sdp_W_crosslet : natural := 16;
- constant c_sdp_W_beamlet_sum : natural := 18;
- constant c_sdp_W_beamlet : natural := 8;
- constant c_sdp_W_gn_id : natural := 8; -- = UniBoard2 ID[7:0]
- constant c_sdp_W_statistic : natural := 64;
- constant c_sdp_W_statistic_sz : natural := 2; -- = c_sdp_W_statistic / c_word_w
- constant c_sdp_W_sub_weight : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_sub_weight_fraction : natural := 14; -- = p in s(w, p)
- constant c_sdp_W_sub_weight_magnitude : natural := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 1
- constant c_sdp_W_beamlet_scale : natural := 16; -- = w in u(w, p), u = unsigned
- constant c_sdp_W_beamlet_scale_fraction : natural := 15; -- = p in u(w, p)
- constant c_sdp_W_beamlet_scale_magnitude : natural := c_sdp_W_beamlet_scale - c_sdp_W_beamlet_scale_fraction; -- = 1
- constant c_sdp_W_bf_weight : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_bf_weight_fraction : natural := 14; -- = p in s(w, p)
- constant c_sdp_W_bf_weight_magnitude : natural := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1; -- = 1
- constant c_sdp_W_local_oscillator : natural := 16; -- = w in s(w, p), s = signed
- constant c_sdp_W_local_oscillator_fraction : natural := 15; -- = p in s(w, p)
- constant c_sdp_W_local_oscillator_magnitude : natural := c_sdp_W_local_oscillator - c_sdp_W_local_oscillator_fraction - 1; -- = 0
- constant c_sdp_N_ring_nof_mac10g : natural := 3; -- for sdp_station_xsub_ring design.
-
- -- Derived constants
- constant c_sdp_FS_adc : natural := 2**(c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0, will just cause clipping of +FS to +FS-1
- constant c_sdp_wg_ampl_lsb : real := c_diag_wg_ampl_unit / real(c_sdp_FS_adc); -- WG amplitude in number of LSbit resolution steps
- constant c_sdp_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
- constant c_sdp_N_clk_per_second : natural := c_sdp_f_adc_MHz * 10**6; -- Default 200M clock cycles per second
- constant c_sdp_N_clk_per_sync : natural := c_sdp_f_adc_MHz * 10**6; -- Default 200M clock cycles per sync interval of 1 second
- constant c_sdp_N_clk_sync_timeout : natural := c_sdp_f_adc_MHz * 10**6 + c_sdp_f_adc_MHz * 10**5; -- 10% margin.
- constant c_sdp_N_clk_sync_timeout_xsub : natural := 2147483647; -- = 2**31 - 1 = largest value for NATURAL for 10.7 seconds. Do not use 2*31 to avoid Modelsim NATURAL overflow warning.
- constant c_sdp_N_sync_jesd : natural := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
- constant c_sdp_f_sub_Hz : real := real(c_sdp_f_adc_MHz * 10**6) / real(c_sdp_N_fft); -- = 195312.5
- constant c_sdp_N_int : natural := c_sdp_f_adc_MHz * 10**6; -- nof ADC sample periods per 1 s integration interval
- constant c_sdp_N_int_sub : real := c_sdp_f_sub_Hz; -- nof subband sample periods per 1 s integration interval
- constant c_sdp_N_int_sub_lo : natural := natural(FLOOR(c_sdp_N_int_sub)); -- = 195312
- constant c_sdp_N_int_sub_hi : natural := natural(CEIL(c_sdp_N_int_sub)); -- = 195313
- constant c_sdp_A_pn : natural := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
- constant c_sdp_P_pfb : natural := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
- constant c_sdp_T_adc : time := (10**6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
- constant c_sdp_T_sub : time := c_sdp_N_fft * c_sdp_T_adc; -- = 5.12 us @ 200MHz
- constant c_sdp_X_sq : natural := c_sdp_S_pn * c_sdp_S_pn; -- = 144
- constant c_sdp_block_period : natural := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz; -- = 5120 [ns]
- constant c_sdp_N_beamlets_sdp : natural := c_sdp_N_beamsets * c_sdp_S_sub_bf; -- = 976
- constant c_sdp_W_dual_pol_beamlet : natural := c_sdp_N_pol_bf * c_nof_complex * c_sdp_W_beamlet; -- 2 * 2 * 8 = 32b
-
- constant c_sdp_nof_words_per_beamlet : natural := 1; -- 1 dual pol, complex, 8bit beamlet (Xre, Xim, Yre, Yim) per 32b word
- constant c_sdp_nof_beamlets_per_longword : natural := 2; -- 2 dual pol, complex, 8bit beamlets fit in 1 64bit longword
- constant c_sdp_nof_beamlets_per_block : natural := c_sdp_S_sub_bf; -- number of dual pol beamlets per block
- constant c_sdp_nof_beamlets_per_block_w : natural := ceil_log2(c_sdp_nof_beamlets_per_block + 1);
-
- -- . unit weights
- constant c_sdp_unit_sub_weight : natural := 2**c_sdp_W_sub_weight_fraction; -- 2**13, so range +-4.0 for 16 bit signed weight
- constant c_sdp_unit_bf_weight : natural := 2**c_sdp_W_bf_weight_fraction; -- 2**14, so range +-2.0 for 16 bit signed weight
- constant c_sdp_unit_beamlet_scale : natural := 2**c_sdp_W_beamlet_scale_fraction; -- 2**15, so range +-1.0 for 16 bit signed weight
-
- -- One dual polarization beamlet fits in a 32b word:
- -- [0:3] = [Xre, Xim, Yre, Yim] parts of c_sdp_W_beamlet = 8 bit, so
- -- c_sdp_N_pol_bf * c_nof_complex * c_sdp_W_beamlet = 2 * 2 = 4 octets
- subtype t_sdp_dual_pol_beamlet_in_word is t_slv_8_arr(0 to 3);
-
- -- Two dual polarization beamlets fit in a 64b longword:
- -- [0:7] = [0:3,4:7] = [Xre, Xim, Yre, Yim, Xre, Xim, Yre, Yim], so
- -- c_sdp_nof_beamlets_per_longword * c_sdp_N_pol_bf * c_nof_complex = 2 * 2 * 2 = 8 octets
- subtype t_sdp_dual_pol_beamlet_in_longword is t_slv_8_arr(0 to 7);
-
- -----------------------------------------------------------------------------
- -- PFB
- -----------------------------------------------------------------------------
-
- -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1,
- -- therefore these parameters are not explicitly used in calculation of derived constants
- -- LTS 2020_11_23:
- --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
- -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- -- c_sdp_N_taps, 1, c_sdp_W_adc, 16, c_sdp_W_fir_coef,
- -- true, false, true, 16, c_sdp_W_subband, 1, 18, 2, true, 54, 2, 195313,
- -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
-
- -- LTS 2021-02-03, changes based on results from u_wpfb_stage22 in tb_tb_verify_pfb_wg.vhd:
- -- . fil_backoff_w = 0 (was 1)
- -- . fil_out_dat_w = fft_in_dat_w = 17 (was 16)
- -- . g_fft_out_gain_w = 0 (was 1)
- -- . g_fft_stage_dat_w = 22 (was 18)
- -- . g_fft_guard_w = 1 (was 2)
- --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
- -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- -- c_sdp_N_taps, 0, c_sdp_W_adc, 17, c_sdp_W_fir_coef,
- -- true, false, true,
- -- 17, c_sdp_W_subband, 0, 22, 1, true,
- -- 54, c_sdp_W_statistic_sz, 195313,
- -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_lts_2021
-
- -- DTS 2022-04-04, changes based on results from in tb_tb_verify_pfb_wg.vhd:
- -- . fil_backoff_w = 1
- -- . fil_out_dat_w = fft_in_dat_w = 0 (use g_fft_stage_dat_w - g_fft_guard_w)
- -- . g_fft_out_gain_w = 1 (compensate for fil_backoff_w = 1)
- -- . g_fft_stage_dat_w = 24
- -- . g_fft_guard_w = 1
- --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
- -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- -- c_sdp_N_taps, 1, c_sdp_W_adc, 23, c_sdp_W_fir_coef,
- -- true, false, true,
- -- 23, c_sdp_W_subband, 1, 24, 1, true,
- -- 54, c_sdp_W_statistic_sz, 195313,
- -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_dts_18b
-
- -- L2TS
- -- . Use fft_guard_w = 1, instead of 2 to avoid overflow in first FFT stage,
- -- because fil_backoff_w = 1 already provides sufficient FFT input margin
- -- . Use fft_out_gain_w = 1 + 1 = 2. One to compensate for fil_backoff_w
- -- = 1 and one to preserve the W_fft_proc = 5b while using fft_out_dat_w
- -- = c_sdp_W_subband = 18b instead of 19b, to fit a 18x19 multiplier for
- -- SST.
- -- . From hdl/libraries/base/common/python/try_round_weight.py it follows
- -- that using -r = 6 extra internal bits per stage is sufficient to have
- -- < 1% disturbance on the sigma of the subband noise. The disturbance
- -- on the sigma is about proportional to 1/2**r, so with -r = 4 it is
- -- about < 4%. Therefore use fft_stage_dat_w = fft_out_dat_w +
- -- fft_out_gain_w + 6b = 26b.
- -- . The raw_dat_w for FFT output of real input is fft_stage_dat_w + 1,
- -- because the use_separate in the FFT feature does not divide by 2.
- -- This implies that preferrably fft_stage_dat_w <= 26, to fit the 27b
- -- multiplier resources.
- -- . Resource usage for fft_stage_dat_w = 24b, 25b, 26b:
- -- 24b 25b 26b
- -- FFT 6 x 27 M20K, 6 x 27 M20K, 6 x 28 M20K, due to separate
- -- BF 2 x 397 M20K, 2 x 403 M20K, 2 x 403 M20K, due to reorder_col
- -- u_revison 1738 M20K, 1750 M20K, 1756 M20K,
- -- 611 DSP, 611 DSP, 611 DSP, same for all
- -- 332324 FF, 335097 FF, 336262 FF,
- -- where 6 = c_sdp_P_pfb and 2 = c_sdp_N_beamsets.
- -- The total increase for u_revison is:
- -- . for 25b / 24b : 12 m20K = 0.7 % and ~2800 FF = 0.83 %.
- -- . for 26b / 24b : 18 m20K = 1.0 % and ~4000 FF = 1.2 %.
- constant c_sdp_W_fil_backoff : natural := 1;
- constant c_sdp_W_fft_guard : natural := 1;
- constant c_sdp_W_fft_stage_dat : natural := 25;
- constant c_sdp_W_fft_in_dat : natural := c_sdp_W_fft_stage_dat - c_sdp_W_fft_guard;
- constant c_sdp_W_fft_out_gain : natural := 2;
- constant c_sdp_W_stat_data : natural := c_sdp_W_subband * 2 + ceil_log2(c_sdp_N_int_sub_hi); -- = 54
-
- constant c_sdp_wpfb_subbands : t_wpfb :=
- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- c_sdp_N_taps, c_sdp_W_fil_backoff, c_sdp_W_adc, c_sdp_W_fft_in_dat, c_sdp_W_fir_coef,
- true, false, true,
- c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
- c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
-
- constant c_sdp_wpfb_complex_subbands : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_sdp_wpfb_subbands);
-
- -- DC gain of WPFB FIR filter obtained from applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
- -- Not used in RTL, only used in test benches to verify expected suband levels
- constant c_sdp_wpfb_fir_filter_dc_gain : real := c_fil_lofar1_fir_filter_dc_gain; -- = 0.994817, almost unit DC gain
- constant c_sdp_wpfb_subband_sp_ampl_ratio : real := func_wpfb_subband_gain(c_sdp_wpfb_subbands, c_sdp_wpfb_fir_filter_dc_gain);
-
- -----------------------------------------------------------------------------
- -- Subband Equalizer
- -----------------------------------------------------------------------------
- constant c_sdp_subband_equalizer_latency : natural := 11; -- 11 = 3 reverse + 1 sum + 5 weight + 2 requant
-
- -----------------------------------------------------------------------------
- -- Statistics offload
- -----------------------------------------------------------------------------
-
- -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
- -- See NiosII code:
- -- https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
- -- https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
- -- and g_base_ip = x"0A63" in:
- -- https://git.astron.nl/rtsd/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
-
- -- Can use same offload time for all statistics, because 1GbE mux will combine them
- -- see https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+Statistics+offload
- --CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
- constant c_sdp_offload_time : natural := 600000; -- 600000 * 5 ns = 3 ms, so gn 31 starts after 93 ms
-
- -- packet lengths, see ICD SC-SDP
- constant c_sdp_nof_bytes_per_statistic : natural := 8; -- c_sdp_W_statistic_sz * c_word_sz = 2 * 4 = 8
-
- constant c_sdp_stat_app_header_len : natural := 32;
-
- constant c_sdp_stat_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
- constant c_sdp_stat_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in libraries/unb_osy/unbos_eth.h
- constant c_sdp_stat_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
- constant c_sdp_stat_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"0A63"; -- 10.99.xx.yy = g_base_ip in ctrl_unb2#_board.vhd used in libraries/unb_osy/unbos_eth.c
- constant c_sdp_stat_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5001, 16); -- 0x1389 = 5001
- constant c_sdp_sst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- TBC, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
- constant c_sdp_bst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D1"; -- TBC
- constant c_sdp_xst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D2"; -- TBC
-
- constant c_sdp_stat_version_id : natural := 5;
- constant c_sdp_stat_nof_hdr_fields : natural := 1 + 3 + 12 + 4 + 4 + 8 + 7 + 1; -- 608b; 19 32b words
-
- -- hdr_field_sel bit selects where the hdr_field value is set:
- -- . 0 = data path controlled, value is set in sdp_statistics_offload.vhd, so field_default() is not used.
- -- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
- -- sdp_statistics_offload.vhd is not used.
- -- Remarks:
- -- . For constant values it is convenient to use MM controlled, because then the field_default()
- -- is used that can be set here in c_sdp_stat_hdr_field_arr.
- -- . For reserved values it is convenient to use MM controlled, because then in future they
- -- could still be changed via MM without having to recompile the FW.
- -- . Typically only use data path controlled if the value has to be set dynamically, so dependent
- -- on the state of the FW.
- -- . If a data path controlled field is not set in the FW, then it defaults to 0 by declaring
- -- hdr_fields_in_arr with all 0. Hence e.g. udp_checksum = 0 can be achieve via data path
- -- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
- -- eth ip udp app
- constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0"; -- current
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
---CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
-
- -- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed before
- -- statistics offload packets can be send.
- constant c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
+ ( (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
+ '0', '0', '0',
+ (others => '0') );
+
+ -------------------------------------------------
+ -- SDP specific parameters as defined in [1]
+ constant c_sdp_f_adc_MHz : natural := 200;
+ constant c_sdp_N_band : natural := 2; -- 2 antenna bands, LB and HB
+ constant c_sdp_N_beamsets : natural := 2; -- = N_beamsets_sdp in doc
+ constant c_sdp_N_cross_sets_sdp : natural := 1;
+ constant c_sdp_N_crosslets_max : natural := 7;
+ constant c_sdp_N_fft : natural := 1024;
+ constant c_sdp_N_pn_max : natural := 16; -- max 16 PN per ring = per antenna band
+ constant c_sdp_N_pol : natural := 2;
+ constant c_sdp_N_pol_bf : natural := 2;
+ constant c_sdp_N_rings_sdp : natural := 1;
+ constant c_sdp_N_ring_lanes_max : natural := 8; -- = N_lane in doc
+ constant c_sdp_N_sub : natural := 512;
+ constant c_sdp_N_sync_rcu : natural := 1;
+ constant c_sdp_N_taps : natural := 16;
+ constant c_sdp_P_sq : natural := 9; -- = N_pn / 2 + 1
+ constant c_sdp_Q_fft : natural := 2;
+ constant c_sdp_S_pn : natural := 12;
+ constant c_sdp_S_rcu : natural := 3;
+ constant c_sdp_S_sub_bf : natural := 488;
+ constant c_sdp_R_os : natural := 2; -- Oversampling factor of 2 for PFB.
+ constant c_sdp_V_ring_pkt_len_max : natural := 48; -- for 16 nodes
+ constant c_sdp_V_sample_delay : natural := 4096;
+ constant c_sdp_V_si_db : natural := 1024;
+ constant c_sdp_V_si_db_large : natural := 131072;
+ constant c_sdp_V_si_histogram : natural := 512;
+ constant c_sdp_W_adc : natural := 14;
+ constant c_sdp_W_adc_jesd : natural := 16;
+ constant c_sdp_W_fir_coef : natural := 16;
+ constant c_sdp_W_subband : natural := 18;
+ constant c_sdp_W_crosslet : natural := 16;
+ constant c_sdp_W_beamlet_sum : natural := 18;
+ constant c_sdp_W_beamlet : natural := 8;
+ constant c_sdp_W_gn_id : natural := 8; -- = UniBoard2 ID[7:0]
+ constant c_sdp_W_statistic : natural := 64;
+ constant c_sdp_W_statistic_sz : natural := 2; -- = c_sdp_W_statistic / c_word_w
+ constant c_sdp_W_sub_weight : natural := 16; -- = w in s(w, p), s = signed
+ constant c_sdp_W_sub_weight_fraction : natural := 14; -- = p in s(w, p)
+ constant c_sdp_W_sub_weight_magnitude : natural := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 1
+ constant c_sdp_W_beamlet_scale : natural := 16; -- = w in u(w, p), u = unsigned
+ constant c_sdp_W_beamlet_scale_fraction : natural := 15; -- = p in u(w, p)
+ constant c_sdp_W_beamlet_scale_magnitude : natural := c_sdp_W_beamlet_scale - c_sdp_W_beamlet_scale_fraction; -- = 1
+ constant c_sdp_W_bf_weight : natural := 16; -- = w in s(w, p), s = signed
+ constant c_sdp_W_bf_weight_fraction : natural := 14; -- = p in s(w, p)
+ constant c_sdp_W_bf_weight_magnitude : natural := c_sdp_W_bf_weight - c_sdp_W_bf_weight_fraction - 1; -- = 1
+ constant c_sdp_W_local_oscillator : natural := 16; -- = w in s(w, p), s = signed
+ constant c_sdp_W_local_oscillator_fraction : natural := 15; -- = p in s(w, p)
+ constant c_sdp_W_local_oscillator_magnitude : natural := c_sdp_W_local_oscillator - c_sdp_W_local_oscillator_fraction - 1; -- = 0
+ constant c_sdp_N_ring_nof_mac10g : natural := 3; -- for sdp_station_xsub_ring design.
+
+ -- Derived constants
+ constant c_sdp_FS_adc : natural := 2 ** (c_sdp_W_adc - 1); -- full scale FS corresponds to amplitude 1.0, will just cause clipping of +FS to +FS-1
+ constant c_sdp_wg_ampl_lsb : real := c_diag_wg_ampl_unit / real(c_sdp_FS_adc); -- WG amplitude in number of LSbit resolution steps
+ constant c_sdp_wg_subband_freq_unit : real := c_diag_wg_freq_unit / real(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ constant c_sdp_N_clk_per_second : natural := c_sdp_f_adc_MHz * 10 ** 6; -- Default 200M clock cycles per second
+ constant c_sdp_N_clk_per_sync : natural := c_sdp_f_adc_MHz * 10 ** 6; -- Default 200M clock cycles per sync interval of 1 second
+ constant c_sdp_N_clk_sync_timeout : natural := c_sdp_f_adc_MHz * 10 ** 6 + c_sdp_f_adc_MHz * 10 ** 5; -- 10% margin.
+ constant c_sdp_N_clk_sync_timeout_xsub : natural := 2147483647; -- = 2**31 - 1 = largest value for NATURAL for 10.7 seconds. Do not use 2*31 to avoid Modelsim NATURAL overflow warning.
+ constant c_sdp_N_sync_jesd : natural := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
+ constant c_sdp_f_sub_Hz : real := real(c_sdp_f_adc_MHz * 10 ** 6) / real(c_sdp_N_fft); -- = 195312.5
+ constant c_sdp_N_int : natural := c_sdp_f_adc_MHz * 10 ** 6; -- nof ADC sample periods per 1 s integration interval
+ constant c_sdp_N_int_sub : real := c_sdp_f_sub_Hz; -- nof subband sample periods per 1 s integration interval
+ constant c_sdp_N_int_sub_lo : natural := natural(FLOOR(c_sdp_N_int_sub)); -- = 195312
+ constant c_sdp_N_int_sub_hi : natural := natural(CEIL(c_sdp_N_int_sub)); -- = 195313
+ constant c_sdp_A_pn : natural := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
+ constant c_sdp_P_pfb : natural := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
+ constant c_sdp_T_adc : time := (10 ** 6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
+ constant c_sdp_T_sub : time := c_sdp_N_fft * c_sdp_T_adc; -- = 5.12 us @ 200MHz
+ constant c_sdp_X_sq : natural := c_sdp_S_pn * c_sdp_S_pn; -- = 144
+ constant c_sdp_block_period : natural := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz; -- = 5120 [ns]
+ constant c_sdp_N_beamlets_sdp : natural := c_sdp_N_beamsets * c_sdp_S_sub_bf; -- = 976
+ constant c_sdp_W_dual_pol_beamlet : natural := c_sdp_N_pol_bf * c_nof_complex * c_sdp_W_beamlet; -- 2 * 2 * 8 = 32b
+
+ constant c_sdp_nof_words_per_beamlet : natural := 1; -- 1 dual pol, complex, 8bit beamlet (Xre, Xim, Yre, Yim) per 32b word
+ constant c_sdp_nof_beamlets_per_longword : natural := 2; -- 2 dual pol, complex, 8bit beamlets fit in 1 64bit longword
+ constant c_sdp_nof_beamlets_per_block : natural := c_sdp_S_sub_bf; -- number of dual pol beamlets per block
+ constant c_sdp_nof_beamlets_per_block_w : natural := ceil_log2(c_sdp_nof_beamlets_per_block + 1);
+
+ -- . unit weights
+ constant c_sdp_unit_sub_weight : natural := 2 ** c_sdp_W_sub_weight_fraction; -- 2**13, so range +-4.0 for 16 bit signed weight
+ constant c_sdp_unit_bf_weight : natural := 2 ** c_sdp_W_bf_weight_fraction; -- 2**14, so range +-2.0 for 16 bit signed weight
+ constant c_sdp_unit_beamlet_scale : natural := 2 ** c_sdp_W_beamlet_scale_fraction; -- 2**15, so range +-1.0 for 16 bit signed weight
+
+ -- One dual polarization beamlet fits in a 32b word:
+ -- [0:3] = [Xre, Xim, Yre, Yim] parts of c_sdp_W_beamlet = 8 bit, so
+ -- c_sdp_N_pol_bf * c_nof_complex * c_sdp_W_beamlet = 2 * 2 = 4 octets
+ subtype t_sdp_dual_pol_beamlet_in_word is t_slv_8_arr(0 to 3);
+
+ -- Two dual polarization beamlets fit in a 64b longword:
+ -- [0:7] = [0:3,4:7] = [Xre, Xim, Yre, Yim, Xre, Xim, Yre, Yim], so
+ -- c_sdp_nof_beamlets_per_longword * c_sdp_N_pol_bf * c_nof_complex = 2 * 2 * 2 = 8 octets
+ subtype t_sdp_dual_pol_beamlet_in_longword is t_slv_8_arr(0 to 7);
+
+ -----------------------------------------------------------------------------
+ -- PFB
+ -----------------------------------------------------------------------------
+
+ -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1,
+ -- therefore these parameters are not explicitly used in calculation of derived constants
+ -- LTS 2020_11_23:
+ --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
+ -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+ -- c_sdp_N_taps, 1, c_sdp_W_adc, 16, c_sdp_W_fir_coef,
+ -- true, false, true, 16, c_sdp_W_subband, 1, 18, 2, true, 54, 2, 195313,
+ -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+
+ -- LTS 2021-02-03, changes based on results from u_wpfb_stage22 in tb_tb_verify_pfb_wg.vhd:
+ -- . fil_backoff_w = 0 (was 1)
+ -- . fil_out_dat_w = fft_in_dat_w = 17 (was 16)
+ -- . g_fft_out_gain_w = 0 (was 1)
+ -- . g_fft_stage_dat_w = 22 (was 18)
+ -- . g_fft_guard_w = 1 (was 2)
+ --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
+ -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+ -- c_sdp_N_taps, 0, c_sdp_W_adc, 17, c_sdp_W_fir_coef,
+ -- true, false, true,
+ -- 17, c_sdp_W_subband, 0, 22, 1, true,
+ -- 54, c_sdp_W_statistic_sz, 195313,
+ -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_lts_2021
+
+ -- DTS 2022-04-04, changes based on results from in tb_tb_verify_pfb_wg.vhd:
+ -- . fil_backoff_w = 1
+ -- . fil_out_dat_w = fft_in_dat_w = 0 (use g_fft_stage_dat_w - g_fft_guard_w)
+ -- . g_fft_out_gain_w = 1 (compensate for fil_backoff_w = 1)
+ -- . g_fft_stage_dat_w = 24
+ -- . g_fft_guard_w = 1
+ --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
+ -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+ -- c_sdp_N_taps, 1, c_sdp_W_adc, 23, c_sdp_W_fir_coef,
+ -- true, false, true,
+ -- 23, c_sdp_W_subband, 1, 24, 1, true,
+ -- 54, c_sdp_W_statistic_sz, 195313,
+ -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_dts_18b
+
+ -- L2TS
+ -- . Use fft_guard_w = 1, instead of 2 to avoid overflow in first FFT stage,
+ -- because fil_backoff_w = 1 already provides sufficient FFT input margin
+ -- . Use fft_out_gain_w = 1 + 1 = 2. One to compensate for fil_backoff_w
+ -- = 1 and one to preserve the W_fft_proc = 5b while using fft_out_dat_w
+ -- = c_sdp_W_subband = 18b instead of 19b, to fit a 18x19 multiplier for
+ -- SST.
+ -- . From hdl/libraries/base/common/python/try_round_weight.py it follows
+ -- that using -r = 6 extra internal bits per stage is sufficient to have
+ -- < 1% disturbance on the sigma of the subband noise. The disturbance
+ -- on the sigma is about proportional to 1/2**r, so with -r = 4 it is
+ -- about < 4%. Therefore use fft_stage_dat_w = fft_out_dat_w +
+ -- fft_out_gain_w + 6b = 26b.
+ -- . The raw_dat_w for FFT output of real input is fft_stage_dat_w + 1,
+ -- because the use_separate in the FFT feature does not divide by 2.
+ -- This implies that preferrably fft_stage_dat_w <= 26, to fit the 27b
+ -- multiplier resources.
+ -- . Resource usage for fft_stage_dat_w = 24b, 25b, 26b:
+ -- 24b 25b 26b
+ -- FFT 6 x 27 M20K, 6 x 27 M20K, 6 x 28 M20K, due to separate
+ -- BF 2 x 397 M20K, 2 x 403 M20K, 2 x 403 M20K, due to reorder_col
+ -- u_revison 1738 M20K, 1750 M20K, 1756 M20K,
+ -- 611 DSP, 611 DSP, 611 DSP, same for all
+ -- 332324 FF, 335097 FF, 336262 FF,
+ -- where 6 = c_sdp_P_pfb and 2 = c_sdp_N_beamsets.
+ -- The total increase for u_revison is:
+ -- . for 25b / 24b : 12 m20K = 0.7 % and ~2800 FF = 0.83 %.
+ -- . for 26b / 24b : 18 m20K = 1.0 % and ~4000 FF = 1.2 %.
+ constant c_sdp_W_fil_backoff : natural := 1;
+ constant c_sdp_W_fft_guard : natural := 1;
+ constant c_sdp_W_fft_stage_dat : natural := 25;
+ constant c_sdp_W_fft_in_dat : natural := c_sdp_W_fft_stage_dat - c_sdp_W_fft_guard;
+ constant c_sdp_W_fft_out_gain : natural := 2;
+ constant c_sdp_W_stat_data : natural := c_sdp_W_subband * 2 + ceil_log2(c_sdp_N_int_sub_hi); -- = 54
+
+ constant c_sdp_wpfb_subbands : t_wpfb :=
+ (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+ c_sdp_N_taps, c_sdp_W_fil_backoff, c_sdp_W_adc, c_sdp_W_fft_in_dat, c_sdp_W_fir_coef,
+ true, false, true,
+ c_sdp_W_fft_in_dat, c_sdp_W_subband, c_sdp_W_fft_out_gain, c_sdp_W_fft_stage_dat, c_sdp_W_fft_guard, true,
+ c_sdp_W_stat_data, c_sdp_W_statistic_sz, c_sdp_N_int_sub_hi,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_l2ts_18b
+
+ constant c_sdp_wpfb_complex_subbands : t_wpfb := func_wpfb_map_real_input_wpfb_parameters_to_complex_input(c_sdp_wpfb_subbands);
+
+ -- DC gain of WPFB FIR filter obtained from applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
+ -- Not used in RTL, only used in test benches to verify expected suband levels
+ constant c_sdp_wpfb_fir_filter_dc_gain : real := c_fil_lofar1_fir_filter_dc_gain; -- = 0.994817, almost unit DC gain
+ constant c_sdp_wpfb_subband_sp_ampl_ratio : real := func_wpfb_subband_gain(c_sdp_wpfb_subbands, c_sdp_wpfb_fir_filter_dc_gain);
+
+ -----------------------------------------------------------------------------
+ -- Subband Equalizer
+ -----------------------------------------------------------------------------
+ constant c_sdp_subband_equalizer_latency : natural := 11; -- 11 = 3 reverse + 1 sum + 5 weight + 2 requant
+
+ -----------------------------------------------------------------------------
+ -- Statistics offload
+ -----------------------------------------------------------------------------
+
+ -- The statistics offload uses the same 1GbE port as the NiosII for M&C. The 1GbE addresses defined in SW and here in FW.
+ -- See NiosII code:
+ -- https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.h
+ -- https://git.astron.nl/rtsd/hdl/-/blob/master/libraries/unb_osy/unbos_eth.c
+ -- and g_base_ip = x"0A63" in:
+ -- https://git.astron.nl/rtsd/hdl/-/blob/master/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+
+ -- Can use same offload time for all statistics, because 1GbE mux will combine them
+ -- see https://support.astron.nl/confluence/display/L2M/L3+SDP+Testing+Notebook%3A+Statistics+offload
+ --CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
+ constant c_sdp_offload_time : natural := 600000; -- 600000 * 5 ns = 3 ms, so gn 31 starts after 93 ms
+
+ -- packet lengths, see ICD SC-SDP
+ constant c_sdp_nof_bytes_per_statistic : natural := 8; -- c_sdp_W_statistic_sz * c_word_sz = 2 * 4 = 8
+
+ constant c_sdp_stat_app_header_len : natural := 32;
+
+ constant c_sdp_stat_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
+ constant c_sdp_stat_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 00:22:86:08:pp:qq = UNB_ETH_SRC_MAC_BASE in libraries/unb_osy/unbos_eth.h
+ constant c_sdp_stat_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
+ constant c_sdp_stat_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"0A63"; -- 10.99.xx.yy = g_base_ip in ctrl_unb2#_board.vhd used in libraries/unb_osy/unbos_eth.c
+ constant c_sdp_stat_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5001, 16); -- 0x1389 = 5001
+ constant c_sdp_sst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- TBC, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
+ constant c_sdp_bst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D1"; -- TBC
+ constant c_sdp_xst_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D2"; -- TBC
+
+ constant c_sdp_stat_version_id : natural := 5;
+ constant c_sdp_stat_nof_hdr_fields : natural := 1 + 3 + 12 + 4 + 4 + 8 + 7 + 1; -- 608b; 19 32b words
+
+ -- hdr_field_sel bit selects where the hdr_field value is set:
+ -- . 0 = data path controlled, value is set in sdp_statistics_offload.vhd, so field_default() is not used.
+ -- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
+ -- sdp_statistics_offload.vhd is not used.
+ -- Remarks:
+ -- . For constant values it is convenient to use MM controlled, because then the field_default()
+ -- is used that can be set here in c_sdp_stat_hdr_field_arr.
+ -- . For reserved values it is convenient to use MM controlled, because then in future they
+ -- could still be changed via MM without having to recompile the FW.
+ -- . Typically only use data path controlled if the value has to be set dynamically, so dependent
+ -- on the state of the FW.
+ -- . If a data path controlled field is not set in the FW, then it defaults to 0 by declaring
+ -- hdr_fields_in_arr with all 0. Hence e.g. udp_checksum = 0 can be achieve via data path
+ -- and default hdr_fields_in_arr = 0 or via MM controlled and field_default(0).
+ -- eth ip udp app
+ constant c_sdp_stat_hdr_field_sel : std_logic_vector(c_sdp_stat_nof_hdr_fields - 1 downto 0) := "1" & "101" & "111011111001" & "0100" & "0100" & "00000000" & "1000000" & "0"; -- current
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111011111001"&"0101"&"0100"&"00000000"&"0000100"&"0"; -- previous 26 nov 2021
+ --CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"00000000"&"1000000"&"0"; -- initial
+
+ -- Default use destination MAC/IP/UDP = 0, so these have to be MM programmed before
+ -- statistics offload packets can be send.
+ constant c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("word_align" ), "RW", 16, field_default(0) ), -- Tx TSE IP will strip these 2 padding bytes
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_stat_eth_dst_mac
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
@@ -354,96 +354,96 @@ package sdp_pkg is
( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
- constant c_sdp_reg_stat_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
-
- type t_sdp_network_stat_header is record
- sdp_marker : std_logic_vector( 7 downto 0);
- sdp_version_id : std_logic_vector( 7 downto 0);
- sdp_observation_id : std_logic_vector(31 downto 0);
- sdp_station_info : std_logic_vector(15 downto 0);
-
- sdp_source_info_antenna_band_id : std_logic_vector( 0 downto 0);
- sdp_source_info_nyquist_zone_id : std_logic_vector( 1 downto 0);
- sdp_source_info_f_adc : std_logic_vector( 0 downto 0);
- sdp_source_info_fsub_type : std_logic_vector( 0 downto 0);
- sdp_source_info_payload_error : std_logic_vector( 0 downto 0);
- sdp_source_info_beam_repositioning_flag : std_logic_vector( 0 downto 0);
- sdp_source_info_weighted_subbands_flag : std_logic_vector( 0 downto 0);
- sdp_source_info_gn_id : std_logic_vector( 7 downto 0);
-
- sdp_reserved : std_logic_vector( 7 downto 0);
- sdp_integration_interval : std_logic_vector(23 downto 0);
- sdp_data_id : std_logic_vector(31 downto 0);
- sdp_data_id_sst_signal_input_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
- sdp_data_id_bst_beamlet_index : std_logic_vector(15 downto 0); -- sdp_data_id sub field
- sdp_data_id_xst_subband_index : std_logic_vector(24 downto 16); -- sdp_data_id sub field
- sdp_data_id_xst_signal_input_A_index : std_logic_vector(15 downto 8); -- sdp_data_id sub field
- sdp_data_id_xst_signal_input_B_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
- sdp_nof_signal_inputs : std_logic_vector( 7 downto 0);
- sdp_nof_bytes_per_statistic : std_logic_vector( 7 downto 0);
- sdp_nof_statistics_per_packet : std_logic_vector(15 downto 0);
- sdp_block_period : std_logic_vector(15 downto 0);
-
- dp_bsn : std_logic_vector(63 downto 0);
- end record;
-
- type t_sdp_stat_data_id is record
- sst_signal_input_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
- bst_beamlet_index : natural range 0 to 2**16 - 1; -- < 976 = c_sdp_N_beamsets * c_sdp_S_sub_bf
- xst_subband_index : natural range 0 to 2**9 - 1; -- < 512 = c_sdp_N_sub
- xst_signal_input_A_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
- xst_signal_input_B_index : natural range 0 to 2**8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
- end record;
-
- type t_sdp_stat_header is record
- eth : t_network_eth_header;
- ip : t_network_ip_header;
- udp : t_network_udp_header;
- app : t_sdp_network_stat_header;
- end record;
-
- -----------------------------------------------------------------------------
- -- Beamlet data output (BDO) via 10GbE to CEP (= central processor, see ICD STAT-CEP)
- -----------------------------------------------------------------------------
- constant c_sdp_cep_version_id : natural := 5;
- constant c_sdp_marker_beamlets : natural := 98; -- = x"62" = 'b'
-
- constant c_sdp_cep_eth_dst_mac : std_logic_vector(47 downto 0) := x"00074306C700"; -- 00074306C700 = DOP36-eth0
- constant c_sdp_cep_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
- constant c_sdp_cep_ip_dst_addr : std_logic_vector(31 downto 0) := x"C0A80001"; -- C0A80001 = '192.168.0.1' = DOP36-eth0
- constant c_sdp_cep_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"C0A8"; -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy
- constant c_sdp_cep_ip_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7868, 16); -- see ICD STAT-CEP
- constant c_sdp_cep_udp_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7848, 16); -- see ICD STAT-CEP
- constant c_sdp_cep_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5000, 16); -- 0x1388 = 5000
- constant c_sdp_cep_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
-
- constant c_sdp_cep_app_header_len : natural := 32; -- octets, see ICD STAT-CEP
- constant c_sdp_cep_header_len : natural := 14 + 20 + 8 + c_sdp_cep_app_header_len; -- = eth + ip + udp + app = 74 octets, see ICD STAT-CEP
-
- constant c_sdp_cep_nof_blocks_per_packet : natural := 4; -- number of time blocks of beamlets per output packet
- constant c_sdp_cep_nof_beamlets_per_block : natural := c_sdp_nof_beamlets_per_block; -- number of dual pol beamlets (c_sdp_N_pol_bf = 2)
- constant c_sdp_cep_nof_beamlets_per_packet : natural := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block;
- constant c_sdp_cep_payload_nof_longwords : natural := c_sdp_cep_nof_beamlets_per_packet / c_sdp_nof_beamlets_per_longword; -- = 976
- constant c_sdp_cep_packet_nof_longwords : natural := ceil_div(c_sdp_cep_header_len, c_longword_sz) + c_sdp_cep_payload_nof_longwords; -- without tail CRC, the CRC is applied by 10GbE MAC
-
- -- CEP packet header
- constant c_sdp_cep_nof_hdr_fields : natural := 3 + 12 + 4 + 4 + 9 + 6 + 1; -- = 39 fields
- -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
- -- hdr_field_sel bit selects where the hdr_field value is set:
- -- . 0 = data path controlled, value is set in sdp_beamformer_output.vhd, so field_default() is not used.
- -- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
- -- sdp_beamformer_output.vhd is not used.
- -- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
- -- eth ip udp app
- constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100000" & "0"; -- current
---constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0"; -- 18 sep 2023
---constant c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 downto 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
---constant c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 downto 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
-
- -- Default use source MAC/IP/UDP = 0 and destination MAC/IP/UDP = 0, so these have to be MM programmed
- -- before beamlet output packets can be send.
- constant c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
+ );
+ constant c_sdp_reg_stat_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
+
+ type t_sdp_network_stat_header is record
+ sdp_marker : std_logic_vector( 7 downto 0);
+ sdp_version_id : std_logic_vector( 7 downto 0);
+ sdp_observation_id : std_logic_vector(31 downto 0);
+ sdp_station_info : std_logic_vector(15 downto 0);
+
+ sdp_source_info_antenna_band_id : std_logic_vector( 0 downto 0);
+ sdp_source_info_nyquist_zone_id : std_logic_vector( 1 downto 0);
+ sdp_source_info_f_adc : std_logic_vector( 0 downto 0);
+ sdp_source_info_fsub_type : std_logic_vector( 0 downto 0);
+ sdp_source_info_payload_error : std_logic_vector( 0 downto 0);
+ sdp_source_info_beam_repositioning_flag : std_logic_vector( 0 downto 0);
+ sdp_source_info_weighted_subbands_flag : std_logic_vector( 0 downto 0);
+ sdp_source_info_gn_id : std_logic_vector( 7 downto 0);
+
+ sdp_reserved : std_logic_vector( 7 downto 0);
+ sdp_integration_interval : std_logic_vector(23 downto 0);
+ sdp_data_id : std_logic_vector(31 downto 0);
+ sdp_data_id_sst_signal_input_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
+ sdp_data_id_bst_beamlet_index : std_logic_vector(15 downto 0); -- sdp_data_id sub field
+ sdp_data_id_xst_subband_index : std_logic_vector(24 downto 16); -- sdp_data_id sub field
+ sdp_data_id_xst_signal_input_A_index : std_logic_vector(15 downto 8); -- sdp_data_id sub field
+ sdp_data_id_xst_signal_input_B_index : std_logic_vector( 7 downto 0); -- sdp_data_id sub field
+ sdp_nof_signal_inputs : std_logic_vector( 7 downto 0);
+ sdp_nof_bytes_per_statistic : std_logic_vector( 7 downto 0);
+ sdp_nof_statistics_per_packet : std_logic_vector(15 downto 0);
+ sdp_block_period : std_logic_vector(15 downto 0);
+
+ dp_bsn : std_logic_vector(63 downto 0);
+ end record;
+
+ type t_sdp_stat_data_id is record
+ sst_signal_input_index : natural range 0 to 2 ** 8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ bst_beamlet_index : natural range 0 to 2 ** 16 - 1; -- < 976 = c_sdp_N_beamsets * c_sdp_S_sub_bf
+ xst_subband_index : natural range 0 to 2 ** 9 - 1; -- < 512 = c_sdp_N_sub
+ xst_signal_input_A_index : natural range 0 to 2 ** 8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ xst_signal_input_B_index : natural range 0 to 2 ** 8 - 1; -- < 192 = c_sdp_N_pn_max * c_sdp_S_pn
+ end record;
+
+ type t_sdp_stat_header is record
+ eth : t_network_eth_header;
+ ip : t_network_ip_header;
+ udp : t_network_udp_header;
+ app : t_sdp_network_stat_header;
+ end record;
+
+ -----------------------------------------------------------------------------
+ -- Beamlet data output (BDO) via 10GbE to CEP (= central processor, see ICD STAT-CEP)
+ -----------------------------------------------------------------------------
+ constant c_sdp_cep_version_id : natural := 5;
+ constant c_sdp_marker_beamlets : natural := 98; -- = x"62" = 'b'
+
+ constant c_sdp_cep_eth_dst_mac : std_logic_vector(47 downto 0) := x"00074306C700"; -- 00074306C700 = DOP36-eth0
+ constant c_sdp_cep_eth_src_mac_47_16 : std_logic_vector(31 downto 0) := x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
+ constant c_sdp_cep_ip_dst_addr : std_logic_vector(31 downto 0) := x"C0A80001"; -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ constant c_sdp_cep_ip_src_addr_31_16 : std_logic_vector(15 downto 0) := x"C0A8"; -- 31:16, 15:8 = backplane, 7:0 = node + 1 = 192.168.xx.yy
+ constant c_sdp_cep_ip_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7868, 16); -- see ICD STAT-CEP
+ constant c_sdp_cep_udp_total_length : std_logic_vector(15 downto 0) := TO_UVEC(7848, 16); -- see ICD STAT-CEP
+ constant c_sdp_cep_udp_dst_port : std_logic_vector(15 downto 0) := TO_UVEC(5000, 16); -- 0x1388 = 5000
+ constant c_sdp_cep_udp_src_port_15_8 : std_logic_vector( 7 downto 0) := x"D0"; -- 15:8, 7:0 = gn_id (= ID[7:0] = backplane[5:0] & node[1:0])
+
+ constant c_sdp_cep_app_header_len : natural := 32; -- octets, see ICD STAT-CEP
+ constant c_sdp_cep_header_len : natural := 14 + 20 + 8 + c_sdp_cep_app_header_len; -- = eth + ip + udp + app = 74 octets, see ICD STAT-CEP
+
+ constant c_sdp_cep_nof_blocks_per_packet : natural := 4; -- number of time blocks of beamlets per output packet
+ constant c_sdp_cep_nof_beamlets_per_block : natural := c_sdp_nof_beamlets_per_block; -- number of dual pol beamlets (c_sdp_N_pol_bf = 2)
+ constant c_sdp_cep_nof_beamlets_per_packet : natural := c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block;
+ constant c_sdp_cep_payload_nof_longwords : natural := c_sdp_cep_nof_beamlets_per_packet / c_sdp_nof_beamlets_per_longword; -- = 976
+ constant c_sdp_cep_packet_nof_longwords : natural := ceil_div(c_sdp_cep_header_len, c_longword_sz) + c_sdp_cep_payload_nof_longwords; -- without tail CRC, the CRC is applied by 10GbE MAC
+
+ -- CEP packet header
+ constant c_sdp_cep_nof_hdr_fields : natural := 3 + 12 + 4 + 4 + 9 + 6 + 1; -- = 39 fields
+ -- c_sdp_cep_header_len / c_longword_sz = 74 / 8 = 9.25 64b words = 592b
+ -- hdr_field_sel bit selects where the hdr_field value is set:
+ -- . 0 = data path controlled, value is set in sdp_beamformer_output.vhd, so field_default() is not used.
+ -- . 1 = MM controlled, value is set via MM or by the field_default(), so any data path setting in
+ -- sdp_beamformer_output.vhd is not used.
+ -- Remarks: see remarks at c_sdp_stat_nof_hdr_fields.
+ -- eth ip udp app
+ constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100000" & "0"; -- current
+ --constant c_sdp_cep_hdr_field_sel : std_logic_vector(c_sdp_cep_nof_hdr_fields - 1 downto 0) := "111" & "111111111011" & "1110" & "1100" & "100000010" & "100110" & "0"; -- 18 sep 2023
+ --constant c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 downto 0) := "101"&"111111111001"&"0111"&"1100"&"100000010"&"000110"&"0"; -- previous 27 sep 2022
+ --constant c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 downto 0) := "100"&"000000010001"&"0100"&"0100"&"100000000"&"101000"&"0"; -- initial
+
+ -- Default use source MAC/IP/UDP = 0 and destination MAC/IP/UDP = 0, so these have to be MM programmed
+ -- before beamlet output packets can be send.
+ constant c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ), -- c_sdp_cep_eth_dst_mac
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
@@ -489,216 +489,219 @@ package sdp_pkg is
( field_name_pad("sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
- constant c_sdp_reg_cep_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
-
- type t_sdp_network_cep_header is record
- sdp_marker : std_logic_vector( 7 downto 0);
- sdp_version_id : std_logic_vector( 7 downto 0);
- sdp_observation_id : std_logic_vector(31 downto 0);
- sdp_station_info : std_logic_vector(15 downto 0);
-
- sdp_source_info_reserved : std_logic_vector( 4 downto 0);
- sdp_source_info_antenna_band_id : std_logic_vector( 0 downto 0);
- sdp_source_info_nyquist_zone_id : std_logic_vector( 1 downto 0);
- sdp_source_info_f_adc : std_logic_vector( 0 downto 0);
- sdp_source_info_fsub_type : std_logic_vector( 0 downto 0);
- sdp_source_info_payload_error : std_logic_vector( 0 downto 0);
- sdp_source_info_beam_repositioning_flag : std_logic_vector( 0 downto 0);
- sdp_source_info_beamlet_width : std_logic_vector( 3 downto 0);
- sdp_source_info_gn_id : std_logic_vector( 7 downto 0);
-
- sdp_reserved : std_logic_vector(31 downto 0);
- sdp_beamlet_scale : std_logic_vector(15 downto 0);
- sdp_beamlet_index : std_logic_vector(15 downto 0);
- sdp_nof_blocks_per_packet : std_logic_vector( 7 downto 0);
- sdp_nof_beamlets_per_block : std_logic_vector(15 downto 0);
- sdp_block_period : std_logic_vector(15 downto 0);
-
- dp_bsn : std_logic_vector(63 downto 0);
- end record;
-
- type t_sdp_cep_header is record
- eth : t_network_eth_header;
- ip : t_network_ip_header;
- udp : t_network_udp_header;
- app : t_sdp_network_cep_header;
- end record;
-
- -----------------------------------------------------------------------------
- -- MM: address width to fit span of number of 32b words
- -----------------------------------------------------------------------------
- -- BSN monitor V2 address width
- constant c_sdp_reg_bsn_monitor_v2_addr_w : natural := ceil_Log2(7);
- -- BSN align address width
- constant c_sdp_reg_bsn_align_v2_addr_w : natural := ceil_log2(2);
- -- 10GbE MM address widths
- constant c_sdp_reg_bf_hdr_dat_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_cep_hdr_dat_addr_w;
- constant c_sdp_reg_nw_10GbE_mac_addr_w : natural := 13;
- constant c_sdp_reg_nw_10GbE_eth10g_addr_w : natural := 1;
-
- -- JESD204B
- constant c_sdp_jesd204b_freq : string := "200MHz";
- constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0'); -- PIO_JESD_CTRL
-
- -- AIT MM address widths
- constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
- constant c_sdp_jesd_ctrl_addr_w : natural := c_sdp_mm_jesd_ctrl_reg.adr_w; -- = 1
- constant c_sdp_jesd_ctrl_reset_bi : natural := 31;
- constant c_sdp_jesd_ctrl_enable_w : natural := 31;
- constant c_sdp_reg_bsn_monitor_input_addr_w : natural := 8;
- constant c_sdp_reg_wg_addr_w : natural := ceil_log2(c_sdp_S_pn) + 2;
- constant c_sdp_ram_wg_addr_w : natural := ceil_log2(c_sdp_S_pn) + 10;
- constant c_sdp_reg_dp_shiftram_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
- constant c_sdp_reg_bsn_source_v2_addr_w : natural := 3;
- constant c_sdp_reg_bsn_scheduler_addr_w : natural := 1;
- constant c_sdp_ram_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
- constant c_sdp_reg_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
- constant c_sdp_ram_st_histogram_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_histogram);
- constant c_sdp_reg_aduh_monitor_addr_w : natural := ceil_log2(c_sdp_S_pn) + 2;
-
- -- FSUB MM address widths
- constant c_sdp_ram_fil_coefs_addr_w : natural := ceil_log2(c_sdp_R_os) + ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
- constant c_sdp_ram_st_sst_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
- constant c_sdp_reg_si_addr_w : natural := 1; -- enable/disable
- constant c_sdp_ram_equalizer_gains_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft);
- constant c_sdp_reg_dp_selector_addr_w : natural := 1; -- Select input 0 or 1.
- constant c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
-
- -- STAT UDP offload MM address widths
- constant c_sdp_reg_stat_enable_addr_w : natural := 1;
-
- -- BF MM address widths
- constant c_sdp_reg_sdp_info_addr_w : natural := 4;
- constant c_sdp_ram_ss_ss_wide_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- constant c_sdp_ram_bf_weights_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- constant c_sdp_reg_bf_scale_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
- constant c_sdp_reg_dp_xonoff_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
- constant c_sdp_ram_st_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
- constant c_sdp_reg_stat_enable_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
- constant c_sdp_reg_stat_hdr_dat_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_align_v2_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_ring_lane_info_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
- constant c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_dp_block_validate_err_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 4;
- constant c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 2;
- constant c_sdp_reg_bdo_destinations_info_w_one : natural := ceil_log2(256);
- constant c_sdp_reg_bdo_destinations_info_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bdo_destinations_info_w_one;
-
- -- XSUB
- constant c_sdp_crosslets_index_w : natural := ceil_log2(c_sdp_N_sub);
- constant c_sdp_mm_reg_crosslets_info : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_sdp_crosslets_index_w,
- nof_dat => 16, -- 15 offsets + 1 step
- init_sl => '0');
- constant c_sdp_crosslets_info_reg_w : natural := c_sdp_mm_reg_crosslets_info.nof_dat * c_sdp_mm_reg_crosslets_info.dat_w;
- constant c_sdp_crosslets_info_nof_offsets : natural := c_sdp_mm_reg_crosslets_info.nof_dat - 1;
-
- type t_sdp_crosslets_info is record
- offset_arr : t_natural_arr(0 to c_sdp_crosslets_info_nof_offsets - 1);
- step : natural;
- end record;
-
- constant c_sdp_crosslets_info_rst : t_sdp_crosslets_info := (offset_arr => (others => 0), step => 0);
-
- constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
- nof_dat => 1,
- init_sl => '0'); -- Default = 1
- constant c_sdp_nof_crosslets_reg_w : natural := c_sdp_mm_reg_nof_crosslets.nof_dat * c_sdp_mm_reg_nof_crosslets.dat_w;
-
- constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10; -- 0.1 second
-
- -- XSUB MM address widths
- constant c_sdp_reg_crosslets_info_addr_w : natural := c_sdp_mm_reg_crosslets_info.adr_w;
- constant c_sdp_reg_nof_crosslets_addr_w : natural := c_sdp_mm_reg_nof_crosslets.adr_w;
- constant c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : natural := 4;
- constant c_sdp_ram_st_xsq_addr_w : natural := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
- constant c_sdp_ram_st_xsq_arr_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
- constant c_sdp_reg_bsn_align_v2_xsub_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_align_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_ring_lane_info_xst_addr_w : natural := 1;
- constant c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : natural := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : natural := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_dp_block_validate_err_xst_addr_w : natural := 4;
- constant c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : natural := 2;
-
- -- RING MM address widths
- constant c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
- constant c_sdp_reg_ring_lane_info_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
- constant c_sdp_reg_dp_xonoff_lane_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
- constant c_sdp_reg_dp_xonoff_local_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
- constant c_sdp_reg_dp_block_validate_err_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
- constant c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 2;
- constant c_sdp_reg_ring_info_addr_w : natural := 2;
- constant c_sdp_reg_tr_10GbE_mac_addr_w : natural := ceil_log2(c_sdp_N_ring_nof_mac10g) + 13;
- constant c_sdp_reg_tr_10GbE_eth10g_addr_w : natural := ceil_log2(c_sdp_N_ring_nof_mac10g) + 1;
- constant c_sdp_reg_diag_bg_addr_w : natural := 3;
- constant c_sdp_ram_diag_bg_addr_w : natural := 7;
-
- -------------------------------------------------
- -- SDP simulation constants record, to use instead of HW default when g_sim = TRUE
- -------------------------------------------------
- type t_sdp_sim is record
- xst_nof_clk_per_sync_min : natural;
- offload_time : natural; -- select > 0 and gn_index > 0 to see effect of offload_time on statistics offload
- sync_timeout : natural;
- unb_nr : natural;
- node_nr : natural;
- end record;
-
- constant c_sdp_sim : t_sdp_sim := (1, 10, 3 * 1024, 0, 0);
-
- -------------------------------------------------
- -- SDP functions
- -------------------------------------------------
-
- function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural;
- function func_sdp_modulo_N_sub(sub_index : natural) return natural;
-
- function func_sdp_get_stat_marker(g_statistics_type : string) return natural;
- function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural;
-
- -- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
- function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural;
- function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural;
- function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural;
-
- function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_udp_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_ip_total_length(g_statistics_type : string) return natural;
- function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural;
- function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural; -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
-
- function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header;
- function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header;
-
- -- Select header destination MAC, IP, UDP fields from DP (sl = 0) or from MM (sl = '1') in dp_offload_tx_v3
- function func_sdp_cep_hdr_field_sel_dst(sl : std_logic) return std_logic_vector;
-
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id;
- function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector;
-
- function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
- function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
+ );
+ constant c_sdp_reg_cep_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+
+ type t_sdp_network_cep_header is record
+ sdp_marker : std_logic_vector( 7 downto 0);
+ sdp_version_id : std_logic_vector( 7 downto 0);
+ sdp_observation_id : std_logic_vector(31 downto 0);
+ sdp_station_info : std_logic_vector(15 downto 0);
+
+ sdp_source_info_reserved : std_logic_vector( 4 downto 0);
+ sdp_source_info_antenna_band_id : std_logic_vector( 0 downto 0);
+ sdp_source_info_nyquist_zone_id : std_logic_vector( 1 downto 0);
+ sdp_source_info_f_adc : std_logic_vector( 0 downto 0);
+ sdp_source_info_fsub_type : std_logic_vector( 0 downto 0);
+ sdp_source_info_payload_error : std_logic_vector( 0 downto 0);
+ sdp_source_info_beam_repositioning_flag : std_logic_vector( 0 downto 0);
+ sdp_source_info_beamlet_width : std_logic_vector( 3 downto 0);
+ sdp_source_info_gn_id : std_logic_vector( 7 downto 0);
+
+ sdp_reserved : std_logic_vector(31 downto 0);
+ sdp_beamlet_scale : std_logic_vector(15 downto 0);
+ sdp_beamlet_index : std_logic_vector(15 downto 0);
+ sdp_nof_blocks_per_packet : std_logic_vector( 7 downto 0);
+ sdp_nof_beamlets_per_block : std_logic_vector(15 downto 0);
+ sdp_block_period : std_logic_vector(15 downto 0);
+
+ dp_bsn : std_logic_vector(63 downto 0);
+ end record;
+
+ type t_sdp_cep_header is record
+ eth : t_network_eth_header;
+ ip : t_network_ip_header;
+ udp : t_network_udp_header;
+ app : t_sdp_network_cep_header;
+ end record;
+
+ -----------------------------------------------------------------------------
+ -- MM: address width to fit span of number of 32b words
+ -----------------------------------------------------------------------------
+ -- BSN monitor V2 address width
+ constant c_sdp_reg_bsn_monitor_v2_addr_w : natural := ceil_Log2(7);
+ -- BSN align address width
+ constant c_sdp_reg_bsn_align_v2_addr_w : natural := ceil_log2(2);
+ -- 10GbE MM address widths
+ constant c_sdp_reg_bf_hdr_dat_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_cep_hdr_dat_addr_w;
+ constant c_sdp_reg_nw_10GbE_mac_addr_w : natural := 13;
+ constant c_sdp_reg_nw_10GbE_eth10g_addr_w : natural := 1;
+
+ -- JESD204B
+ constant c_sdp_jesd204b_freq : string := "200MHz";
+ constant c_sdp_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0'); -- PIO_JESD_CTRL
+
+ -- AIT MM address widths
+ constant c_sdp_jesd204b_addr_w : natural := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
+ constant c_sdp_jesd_ctrl_addr_w : natural := c_sdp_mm_jesd_ctrl_reg.adr_w; -- = 1
+ constant c_sdp_jesd_ctrl_reset_bi : natural := 31;
+ constant c_sdp_jesd_ctrl_enable_w : natural := 31;
+ constant c_sdp_reg_bsn_monitor_input_addr_w : natural := 8;
+ constant c_sdp_reg_wg_addr_w : natural := ceil_log2(c_sdp_S_pn) + 2;
+ constant c_sdp_ram_wg_addr_w : natural := ceil_log2(c_sdp_S_pn) + 10;
+ constant c_sdp_reg_dp_shiftram_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
+ constant c_sdp_reg_bsn_source_v2_addr_w : natural := 3;
+ constant c_sdp_reg_bsn_scheduler_addr_w : natural := 1;
+ constant c_sdp_ram_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
+ constant c_sdp_reg_diag_data_buf_bsn_addr_w : natural := ceil_log2(c_sdp_S_pn) + 1;
+ constant c_sdp_ram_st_histogram_addr_w : natural := ceil_log2(c_sdp_S_pn) + ceil_log2(c_sdp_V_si_histogram);
+ constant c_sdp_reg_aduh_monitor_addr_w : natural := ceil_log2(c_sdp_S_pn) + 2;
+
+ -- FSUB MM address widths
+ constant c_sdp_ram_fil_coefs_addr_w : natural := ceil_log2(c_sdp_R_os) + ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+ constant c_sdp_ram_st_sst_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
+ constant c_sdp_reg_si_addr_w : natural := 1; -- enable/disable
+ constant c_sdp_ram_equalizer_gains_addr_w : natural := ceil_log2(c_sdp_R_os * c_sdp_P_pfb) + ceil_log2(c_sdp_N_sub * c_sdp_Q_fft);
+ constant c_sdp_reg_dp_selector_addr_w : natural := 1; -- Select input 0 or 1.
+ constant c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
+
+ -- STAT UDP offload MM address widths
+ constant c_sdp_reg_stat_enable_addr_w : natural := 1;
+
+ -- BF MM address widths
+ constant c_sdp_reg_sdp_info_addr_w : natural := 4;
+ constant c_sdp_ram_ss_ss_wide_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ constant c_sdp_ram_bf_weights_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ constant c_sdp_reg_bf_scale_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
+ constant c_sdp_reg_dp_xonoff_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
+ constant c_sdp_ram_st_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
+ constant c_sdp_reg_stat_enable_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
+ constant c_sdp_reg_stat_hdr_dat_bst_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_align_v2_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_ring_lane_info_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 1;
+ constant c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_dp_block_validate_err_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 4;
+ constant c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : natural := ceil_log2(c_sdp_N_beamsets) + 2;
+ constant c_sdp_reg_bdo_destinations_info_w_one : natural := ceil_log2(256);
+ constant c_sdp_reg_bdo_destinations_info_w : natural := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bdo_destinations_info_w_one;
+
+ -- XSUB
+ constant c_sdp_crosslets_index_w : natural := ceil_log2(c_sdp_N_sub);
+ constant c_sdp_mm_reg_crosslets_info : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_sdp_crosslets_index_w,
+ nof_dat => 16, -- 15 offsets + 1 step
+ init_sl => '0');
+ constant c_sdp_crosslets_info_reg_w : natural := c_sdp_mm_reg_crosslets_info.nof_dat * c_sdp_mm_reg_crosslets_info.dat_w;
+ constant c_sdp_crosslets_info_nof_offsets : natural := c_sdp_mm_reg_crosslets_info.nof_dat - 1;
+
+ type t_sdp_crosslets_info is record
+ offset_arr : t_natural_arr(0 to c_sdp_crosslets_info_nof_offsets - 1);
+ step : natural;
+ end record;
+
+ constant c_sdp_crosslets_info_rst : t_sdp_crosslets_info := (offset_arr => (others => 0), step => 0);
+
+ constant c_sdp_mm_reg_nof_crosslets : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => ceil_log2(c_sdp_N_crosslets_max + 1),
+ nof_dat => 1,
+ init_sl => '0'); -- Default = 1
+ constant c_sdp_nof_crosslets_reg_w : natural := c_sdp_mm_reg_nof_crosslets.nof_dat * c_sdp_mm_reg_nof_crosslets.dat_w;
+
+ constant c_sdp_xst_nof_clk_per_sync_min : natural := c_sdp_N_clk_per_sync / 10; -- 0.1 second
+
+ -- XSUB MM address widths
+ constant c_sdp_reg_crosslets_info_addr_w : natural := c_sdp_mm_reg_crosslets_info.adr_w;
+ constant c_sdp_reg_nof_crosslets_addr_w : natural := c_sdp_mm_reg_nof_crosslets.adr_w;
+ constant c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : natural := 4;
+ constant c_sdp_ram_st_xsq_addr_w : natural := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
+ constant c_sdp_ram_st_xsq_arr_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
+ constant c_sdp_reg_bsn_align_v2_xsub_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_align_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w : natural := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : natural := c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_ring_lane_info_xst_addr_w : natural := 1;
+ constant c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : natural := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : natural := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_dp_block_validate_err_xst_addr_w : natural := 4;
+ constant c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : natural := 2;
+
+ -- RING MM address widths
+ constant c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ constant c_sdp_reg_ring_lane_info_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
+ constant c_sdp_reg_dp_xonoff_lane_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
+ constant c_sdp_reg_dp_xonoff_local_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
+ constant c_sdp_reg_dp_block_validate_err_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
+ constant c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + 2;
+ constant c_sdp_reg_ring_info_addr_w : natural := 2;
+ constant c_sdp_reg_tr_10GbE_mac_addr_w : natural := ceil_log2(c_sdp_N_ring_nof_mac10g) + 13;
+ constant c_sdp_reg_tr_10GbE_eth10g_addr_w : natural := ceil_log2(c_sdp_N_ring_nof_mac10g) + 1;
+ constant c_sdp_reg_diag_bg_addr_w : natural := 3;
+ constant c_sdp_ram_diag_bg_addr_w : natural := 7;
+
+ -------------------------------------------------
+ -- SDP simulation constants record, to use instead of HW default when g_sim = TRUE
+ -------------------------------------------------
+ type t_sdp_sim is record
+ xst_nof_clk_per_sync_min : natural;
+ offload_time : natural; -- select > 0 and gn_index > 0 to see effect of offload_time on statistics offload
+ sync_timeout : natural;
+ unb_nr : natural;
+ node_nr : natural;
+ end record;
+
+ constant c_sdp_sim : t_sdp_sim := (1, 10, 3 * 1024, 0, 0);
+
+ -------------------------------------------------
+ -- SDP functions
+ -------------------------------------------------
+
+ function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural;
+ function func_sdp_modulo_N_sub(sub_index : natural) return natural;
+
+ function func_sdp_get_stat_marker(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural;
+
+ -- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
+ function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural;
+
+ function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_udp_total_length(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_ip_total_length(g_statistics_type : string) return natural;
+ function func_sdp_get_stat_udp_src_port(g_statistics_type : string; gn_index : natural) return std_logic_vector;
+ function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural;
+ function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural; -- use c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max
+
+ function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header;
+ function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header;
+
+ -- Select header destination MAC, IP, UDP fields from DP (sl = 0) or from MM (sl = '1') in dp_offload_tx_v3
+ function func_sdp_cep_hdr_field_sel_dst(sl : std_logic) return std_logic_vector;
+
+ function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id;
+ function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_rec : t_sdp_stat_data_id) return std_logic_vector;
+
+ function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info; -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_map_crosslets_info(info_rec : t_sdp_crosslets_info) return std_logic_vector; -- map all c_sdp_N_crosslets_max offsets
+ function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info; -- step all c_sdp_N_crosslets_max offsets
end package sdp_pkg;
package body sdp_pkg is
@@ -741,53 +744,53 @@ package body sdp_pkg is
constant c_marker_xst : natural := 88; -- = 0x58 = 'X'
begin
return sel_a_b(g_statistics_type = "BST", c_marker_bst,
- sel_a_b(g_statistics_type = "XST", c_marker_xst,
- c_marker_sst)); -- SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_marker_xst,
+ c_marker_sst)); -- SST, SST_OS
end func_sdp_get_stat_marker;
function func_sdp_get_stat_nof_signal_inputs(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 0, -- not applicable for BST, so use 0,
- sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
- 1)); -- SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_S_pn,
+ 1)); -- SST, SST_OS
end func_sdp_get_stat_nof_signal_inputs;
function func_sdp_get_stat_from_mm_user_size(g_statistics_type : string) return natural is
- -- see sdp_statistics_offload.vhd for description
+ -- see sdp_statistics_offload.vhd for description
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_W_statistic_sz, -- = 2, so preserve X, Y order
- sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_W_statistic_sz, -- = 2, so preserve Re, Im order
+ c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_user_size;
function func_sdp_get_stat_from_mm_data_size(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_N_pol_bf * c_sdp_W_statistic_sz, -- = 4
- sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
- c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_nof_complex * c_sdp_W_statistic_sz, -- = 4
+ c_sdp_W_statistic_sz)); -- = 2, SST, SST_OS
end func_sdp_get_stat_from_mm_data_size;
function func_sdp_get_stat_from_mm_step_size(g_statistics_type : string) return natural is
constant c_data_size : natural := func_sdp_get_stat_from_mm_data_size(g_statistics_type);
begin
return sel_a_b(g_statistics_type = "BST", c_data_size, -- = 4
- sel_a_b(g_statistics_type = "XST", c_data_size, -- = 4
- c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_data_size, -- = 4
+ c_data_size * c_sdp_Q_fft)); -- = 4, SST, SST_OS
end func_sdp_get_stat_from_mm_step_size;
function func_sdp_get_stat_from_mm_nof_data(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf, -- = 488
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq, -- = 144
+ c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_from_mm_nof_data;
-- nof_statistics_per_packet = mm_nof_data * mm_data_size / c_sdp_W_statistic_sz
function func_sdp_get_stat_nof_statistics_per_packet(g_statistics_type : string) return natural is
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_S_sub_bf * c_sdp_N_pol_bf, -- = 976
- sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
- c_sdp_N_sub)); -- = 512, SST, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_X_sq * c_nof_complex, -- = 288
+ c_sdp_N_sub)); -- = 512, SST, SST_OS
end func_sdp_get_stat_nof_statistics_per_packet;
function func_sdp_get_stat_app_total_length(g_statistics_type : string) return natural is
@@ -824,16 +827,16 @@ package body sdp_pkg is
constant c_gn_index : std_logic_vector(7 downto 0) := TO_UVEC(gn_index, 8);
begin
return sel_a_b(g_statistics_type = "BST", c_sdp_bst_udp_src_port_15_8 & c_gn_index, -- BST = 0xD1 & gn_index
- sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
- c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
+ sel_a_b(g_statistics_type = "XST", c_sdp_xst_udp_src_port_15_8 & c_gn_index, -- XST = 0xD2 & gn_index
+ c_sdp_sst_udp_src_port_15_8 & c_gn_index)); -- SST = 0xD0 & gn_index, SST_OS
end func_sdp_get_stat_udp_src_port;
function func_sdp_get_stat_nof_packets(g_statistics_type : string; S_pn, P_sq, N_crosslets : natural) return natural is
begin
return sel_a_b(g_statistics_type = "BST", 1,
- sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
- sel_a_b(g_statistics_type = "SST", S_pn,
- c_sdp_R_os * S_pn))); -- SST_OS
+ sel_a_b(g_statistics_type = "XST", P_sq * N_crosslets,
+ sel_a_b(g_statistics_type = "SST", S_pn,
+ c_sdp_R_os * S_pn))); -- SST_OS
end func_sdp_get_stat_nof_packets;
function func_sdp_get_stat_nof_packets(g_statistics_type : string) return natural is
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
index d6d46c4f058fdc98860dc875b0817a9e217fd04b..17122b5b1823fc0744fc402fec1d77c337006b85 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
@@ -32,10 +32,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_scope is
generic (
@@ -66,19 +66,20 @@ architecture str of sdp_scope is
signal selected_sosi_arr : t_dp_sosi_arr(g_nof_input * g_n_deinterleave-1 downto 0) := (others => c_dp_sosi_rst);
begin
sim_only : if g_sim = true generate
+
gen_deinterleave : for I in 0 to g_nof_input - 1 generate
u_dp_deinterleave : entity dp_lib.dp_deinterleave_one_to_n
- generic map(
- g_pipeline => 0,
- g_nof_outputs => g_n_deinterleave
- )
- port map(
- rst => rst,
- clk => clk,
+ generic map(
+ g_pipeline => 0,
+ g_nof_outputs => g_n_deinterleave
+ )
+ port map(
+ rst => rst,
+ clk => clk,
- snk_in => sp_sosi_arr(I),
- src_out_arr => deinterleaved_sosi_2arr_n(I)
- );
+ snk_in => sp_sosi_arr(I),
+ src_out_arr => deinterleaved_sosi_2arr_n(I)
+ );
gen_flat : for J in 0 to g_n_deinterleave-1 generate
deinterleaved_sosi_arr(g_n_deinterleave * I + J) <= deinterleaved_sosi_2arr_n(I)(J);
@@ -107,18 +108,18 @@ begin
-- SIGNAL SCOPE
---------------------------------------------------------------
u_dp_wideband_sp_arr_scope : entity dp_lib.dp_wideband_sp_arr_scope
- generic map (
- g_sim => g_sim,
- g_use_sclk => false,
- g_complex => true,
- g_nof_streams => g_nof_input * g_n_deinterleave,
- g_wideband_factor => 1,
- g_dat_w => g_dat_w
- )
- port map (
- DCLK => clk,
- sp_sosi_arr => selected_sosi_arr,
- scope_sosi_arr => scope_sosi_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_use_sclk => false,
+ g_complex => true,
+ g_nof_streams => g_nof_input * g_n_deinterleave,
+ g_wideband_factor => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ DCLK => clk,
+ sp_sosi_arr => selected_sosi_arr,
+ scope_sosi_arr => scope_sosi_arr
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 5cb70ece517fb1fadfc6b05c3e0b9eebfc1ac4bc..223b0344a10b4207d3996da243a38488d16db589 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -38,19 +38,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib, dp_lib, tech_jesd204b_lib, fft_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, nw_10GbE_lib, eth_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use fft_lib.fft_pkg.all;
-use wpfb_lib.wpfb_pkg.all;
-use work.sdp_pkg.all;
-use eth_lib.eth_pkg.all;
-use ring_lib.ring_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use fft_lib.fft_pkg.all;
+ use wpfb_lib.wpfb_pkg.all;
+ use work.sdp_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use ring_lib.ring_pkg.all;
entity sdp_station is
generic (
@@ -89,9 +89,9 @@ entity sdp_station is
-- Transceiver clocks
SA_CLK : in std_logic := '0'; -- Clock 10GbE front (qsfp) and ring lines
- -- back transceivers (Note: numbered from 0)
+ -- back transceivers (Note: numbered from 0)
JESD204B_SERIAL_DATA : in std_logic_vector(c_sdp_S_pn - 1 downto 0);
- -- Connect to the BCK_RX pins in the top wrapper
+ -- Connect to the BCK_RX pins in the top wrapper
JESD204B_REFCLK : in std_logic; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
@@ -625,41 +625,41 @@ begin
xst_udp_src_port <= c_sdp_xst_udp_src_port_15_8 & gn_id;
u_sdp_info : entity work.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_copi,
- reg_miso => reg_sdp_info_cipo,
+ reg_mosi => reg_sdp_info_copi,
+ reg_miso => reg_sdp_info_cipo,
- -- inputs from other blocks
- f_adc => c_f_adc,
- fsub_type => c_fsub_type,
+ -- inputs from other blocks
+ f_adc => c_f_adc,
+ fsub_type => c_fsub_type,
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Ring info
-----------------------------------------------------------------------------
u_ring_info : entity ring_lib.ring_info
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_copi => reg_ring_info_copi,
- reg_cipo => reg_ring_info_cipo,
+ reg_copi => reg_ring_info_copi,
+ reg_cipo => reg_ring_info_cipo,
- ring_info => ring_info
- );
+ ring_info => ring_info
+ );
this_rn <= TO_UVEC(gn_index - TO_UINT(ring_info.O_rn), c_byte_w) when rising_edge(dp_clk); -- Using register to ease timing closure.
@@ -668,111 +668,112 @@ begin
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
-----------------------------------------------------------------------------
u_ait: entity work.node_sdp_adc_input_and_timing
- generic map(
- g_sim => g_sim,
- g_no_jesd => g_no_jesd,
- g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- dp_pps => dp_pps,
-
- -- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_copi,
- jesd_ctrl_miso => jesd_ctrl_cipo,
- jesd204b_mosi => jesd204b_copi,
- jesd204b_miso => jesd204b_cipo,
- reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
- reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
- reg_wg_mosi => reg_wg_copi,
- reg_wg_miso => reg_wg_cipo,
- ram_wg_mosi => ram_wg_copi,
- ram_wg_miso => ram_wg_cipo,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
- ram_st_histogram_mosi => ram_st_histogram_copi,
- ram_st_histogram_miso => ram_st_histogram_cipo,
- reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
- reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
-
- -- Jesd external IOs
- jesd204b_serial_data => JESD204B_SERIAL_DATA,
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC_N,
-
- -- Streaming data output
- out_sosi_arr => ait_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval
- );
+ generic map(
+ g_sim => g_sim,
+ g_no_jesd => g_no_jesd,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_pps => dp_pps,
+
+ -- mm control buses
+ jesd_ctrl_mosi => jesd_ctrl_copi,
+ jesd_ctrl_miso => jesd_ctrl_cipo,
+ jesd204b_mosi => jesd204b_copi,
+ jesd204b_miso => jesd204b_cipo,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
+ reg_wg_mosi => reg_wg_copi,
+ reg_wg_miso => reg_wg_cipo,
+ ram_wg_mosi => ram_wg_copi,
+ ram_wg_miso => ram_wg_cipo,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_mosi => ram_st_histogram_copi,
+ ram_st_histogram_miso => ram_st_histogram_cipo,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => JESD204B_SERIAL_DATA,
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC_N,
+
+ -- Streaming data output
+ out_sosi_arr => ait_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval
+ );
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
gen_use_fsub : if g_use_fsub generate
+
gen_use_no_oversample : if not g_use_oversample generate -- Use normal filterbank
u_fsub : entity work.node_sdp_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
gen_bf_sosi : for I in 0 to c_sdp_N_beamsets - 1 generate
-- Wire same subbands to all beamsets
@@ -785,55 +786,55 @@ begin
-----------------------------------------------------------------------------
gen_use_oversample : if g_use_oversample generate -- use oversampled filterbank instead of normal filterbank
u_fsub : entity work.node_sdp_oversampled_filterbank
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_wpfb => g_wpfb,
- g_wpfb_complex => g_wpfb_complex,
- g_scope_selected_subband => g_scope_selected_subband
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_copi,
- reg_si_miso => reg_si_cipo,
- ram_st_sst_mosi => ram_st_sst_copi,
- ram_st_sst_miso => ram_st_sst_cipo,
- ram_fil_coefs_mosi => ram_fil_coefs_copi,
- ram_fil_coefs_miso => ram_fil_coefs_cipo,
- ram_gains_mosi => ram_equalizer_gains_copi,
- ram_gains_miso => ram_equalizer_gains_cipo,
- ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
- ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
- reg_selector_mosi => reg_dp_selector_copi,
- reg_selector_miso => reg_dp_selector_cipo,
-
- reg_enable_mosi => reg_stat_enable_sst_copi,
- reg_enable_miso => reg_stat_enable_sst_cipo,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
-
- reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
- reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_wpfb => g_wpfb,
+ g_wpfb_complex => g_wpfb_complex,
+ g_scope_selected_subband => g_scope_selected_subband
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ fsub_raw_sosi_arr => fsub_oversampled_raw_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ ram_gains_cross_mosi => ram_equalizer_gains_cross_copi,
+ ram_gains_cross_miso => ram_equalizer_gains_cross_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
+ );
-- Lower part contains normal subbands, higher part contains shifted subbands.
-- . Use normal subbands for subband correlator
@@ -851,60 +852,60 @@ begin
-----------------------------------------------------------------------------
gen_use_xsub : if g_use_xsub generate
u_xsub : entity work.node_sdp_correlator
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_P_sq => g_P_sq,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_arr,
-
- xst_udp_sosi => udp_tx_sosi_arr(1),
- xst_udp_siso => udp_tx_siso_arr(1),
-
- from_ri_sosi => xst_from_ri_sosi,
- to_ri_sosi => xst_to_ri_sosi,
-
- xst_bs_sosi => xst_bs_sosi,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_copi => reg_crosslets_info_copi,
- reg_crosslets_info_cipo => reg_crosslets_info_cipo,
- reg_nof_crosslets_copi => reg_nof_crosslets_copi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
- ram_st_xsq_copi => ram_st_xsq_copi,
- ram_st_xsq_cipo => ram_st_xsq_cipo,
-
- reg_stat_enable_copi => reg_stat_enable_xst_copi,
- reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
- reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
- reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
-
- reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
- reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => xst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_P_sq => g_P_sq,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_arr,
+
+ xst_udp_sosi => udp_tx_sosi_arr(1),
+ xst_udp_siso => udp_tx_siso_arr(1),
+
+ from_ri_sosi => xst_from_ri_sosi,
+ to_ri_sosi => xst_to_ri_sosi,
+
+ xst_bs_sosi => xst_bs_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ reg_stat_enable_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => xst_udp_src_port
+ );
end generate;
-----------------------------------------------------------------------------
@@ -914,245 +915,245 @@ begin
-- Beamformers
gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_bf : entity work.node_sdp_beamformer
- generic map(
- g_sim => g_sim,
- g_sim_sdp => g_sim_sdp,
- g_beamset_id => beamset_id,
- g_use_bdo_transpose => g_use_bdo_transpose,
- g_nof_bdo_destinations_max => g_nof_bdo_destinations_max,
- g_scope_selected_beamlet => g_scope_selected_subband,
- g_subband_raw_dat_w => c_subband_raw_dat_w,
- g_subband_raw_fraction_w => c_subband_raw_fraction_w
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
- from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
- bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
- bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
- bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
-
- dp_bsn_source_new_interval => dp_bsn_source_new_interval,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
- reg_bdo_destinations_copi => reg_bdo_destinations_copi_arr(beamset_id),
- reg_bdo_destinations_cipo => reg_bdo_destinations_cipo_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
- reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
- reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
- reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
- reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
-
- sdp_info => sdp_info,
- ring_info => ring_info,
- gn_id => gn_id,
-
- bdo_eth_src_mac => cep_eth_src_mac,
- bdo_ip_src_addr => cep_ip_src_addr,
- bdo_udp_src_port => cep_udp_src_port,
- bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
-
- stat_eth_src_mac => stat_eth_src_mac,
- stat_ip_src_addr => stat_ip_src_addr,
- stat_udp_src_port => bst_udp_src_port
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_sdp => g_sim_sdp,
+ g_beamset_id => beamset_id,
+ g_use_bdo_transpose => g_use_bdo_transpose,
+ g_nof_bdo_destinations_max => g_nof_bdo_destinations_max,
+ g_scope_selected_beamlet => g_scope_selected_subband,
+ g_subband_raw_dat_w => c_subband_raw_dat_w,
+ g_subband_raw_fraction_w => c_subband_raw_fraction_w
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => fsub_raw_sosi_2arr(beamset_id),
+ from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
+ bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
+ bf_udp_siso => bf_udp_siso_arr(beamset_id),
+ bst_udp_sosi => udp_tx_sosi_arr(2 + beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(2 + beamset_id),
+
+ dp_bsn_source_new_interval => dp_bsn_source_new_interval,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_bdo_destinations_copi => reg_bdo_destinations_copi_arr(beamset_id),
+ reg_bdo_destinations_cipo => reg_bdo_destinations_cipo_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
+ reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
+
+ sdp_info => sdp_info,
+ ring_info => ring_info,
+ gn_id => gn_id,
+
+ bdo_eth_src_mac => cep_eth_src_mac,
+ bdo_ip_src_addr => cep_ip_src_addr,
+ bdo_udp_src_port => cep_udp_src_port,
+ bdo_hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id),
+
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port
+ );
end generate;
-- MM multiplexing
u_mem_mux_ram_ss_ss_wide : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_ss_ss_wide
- )
- port map (
- mosi => ram_ss_ss_wide_copi,
- miso => ram_ss_ss_wide_cipo,
- mosi_arr => ram_ss_ss_wide_copi_arr,
- miso_arr => ram_ss_ss_wide_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_ss_ss_wide
+ )
+ port map (
+ mosi => ram_ss_ss_wide_copi,
+ miso => ram_ss_ss_wide_cipo,
+ mosi_arr => ram_ss_ss_wide_copi_arr,
+ miso_arr => ram_ss_ss_wide_cipo_arr
+ );
u_mem_mux_ram_bf_weights : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_bf_weights
- )
- port map (
- mosi => ram_bf_weights_copi,
- miso => ram_bf_weights_cipo,
- mosi_arr => ram_bf_weights_copi_arr,
- miso_arr => ram_bf_weights_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_bf_weights
+ )
+ port map (
+ mosi => ram_bf_weights_copi,
+ miso => ram_bf_weights_cipo,
+ mosi_arr => ram_bf_weights_copi_arr,
+ miso_arr => ram_bf_weights_cipo_arr
+ );
u_mem_mux_reg_bsn_align_v2_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
- )
- port map (
- mosi => reg_bsn_align_v2_bf_copi,
- miso => reg_bsn_align_v2_bf_cipo,
- mosi_arr => reg_bsn_align_v2_bf_copi_arr,
- miso_arr => reg_bsn_align_v2_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
+ )
+ port map (
+ mosi => reg_bsn_align_v2_bf_copi,
+ miso => reg_bsn_align_v2_bf_cipo,
+ mosi_arr => reg_bsn_align_v2_bf_copi_arr,
+ miso_arr => reg_bsn_align_v2_bf_cipo_arr
+ );
u_mem_mux_reg_bf_scale : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bf_scale
- )
- port map (
- mosi => reg_bf_scale_copi,
- miso => reg_bf_scale_cipo,
- mosi_arr => reg_bf_scale_copi_arr,
- miso_arr => reg_bf_scale_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bf_scale
+ )
+ port map (
+ mosi => reg_bf_scale_copi,
+ miso => reg_bf_scale_cipo,
+ mosi_arr => reg_bf_scale_copi_arr,
+ miso_arr => reg_bf_scale_cipo_arr
+ );
u_mem_mux_reg_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_hdr_dat
- )
- port map (
- mosi => reg_hdr_dat_copi,
- miso => reg_hdr_dat_cipo,
- mosi_arr => reg_hdr_dat_copi_arr,
- miso_arr => reg_hdr_dat_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_hdr_dat
+ )
+ port map (
+ mosi => reg_hdr_dat_copi,
+ miso => reg_hdr_dat_cipo,
+ mosi_arr => reg_hdr_dat_copi_arr,
+ miso_arr => reg_hdr_dat_cipo_arr
+ );
u_mem_mux_reg_bdo_destinations : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bdo_destinations
- )
- port map (
- mosi => reg_bdo_destinations_copi,
- miso => reg_bdo_destinations_cipo,
- mosi_arr => reg_bdo_destinations_copi_arr,
- miso_arr => reg_bdo_destinations_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bdo_destinations
+ )
+ port map (
+ mosi => reg_bdo_destinations_copi,
+ miso => reg_bdo_destinations_cipo,
+ mosi_arr => reg_bdo_destinations_copi_arr,
+ miso_arr => reg_bdo_destinations_cipo_arr
+ );
u_mem_mux_reg_dp_xonoff : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_dp_xonoff
- )
- port map (
- mosi => reg_dp_xonoff_copi,
- miso => reg_dp_xonoff_cipo,
- mosi_arr => reg_dp_xonoff_copi_arr,
- miso_arr => reg_dp_xonoff_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_dp_xonoff
+ )
+ port map (
+ mosi => reg_dp_xonoff_copi,
+ miso => reg_dp_xonoff_cipo,
+ mosi_arr => reg_dp_xonoff_copi_arr,
+ miso_arr => reg_dp_xonoff_cipo_arr
+ );
u_mem_mux_ram_st_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_ram_st_bst
- )
- port map (
- mosi => ram_st_bst_copi,
- miso => ram_st_bst_cipo,
- mosi_arr => ram_st_bst_copi_arr,
- miso_arr => ram_st_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_ram_st_bst
+ )
+ port map (
+ mosi => ram_st_bst_copi,
+ miso => ram_st_bst_cipo,
+ mosi_arr => ram_st_bst_copi_arr,
+ miso_arr => ram_st_bst_cipo_arr
+ );
u_mem_mux_reg_stat_enable_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
- )
- port map (
- mosi => reg_stat_enable_bst_copi,
- miso => reg_stat_enable_bst_cipo,
- mosi_arr => reg_stat_enable_bst_copi_arr,
- miso_arr => reg_stat_enable_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
+ )
+ port map (
+ mosi => reg_stat_enable_bst_copi,
+ miso => reg_stat_enable_bst_cipo,
+ mosi_arr => reg_stat_enable_bst_copi_arr,
+ miso_arr => reg_stat_enable_bst_cipo_arr
+ );
u_mem_mux_reg_stat_hdr_dat_bst : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
- )
- port map (
- mosi => reg_stat_hdr_dat_bst_copi,
- miso => reg_stat_hdr_dat_bst_cipo,
- mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
- miso_arr => reg_stat_hdr_dat_bst_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
+ )
+ port map (
+ mosi => reg_stat_hdr_dat_bst_copi,
+ miso => reg_stat_hdr_dat_bst_cipo,
+ mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_rx_align_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
- miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_aligned_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_aligned_bf_copi,
- miso => reg_bsn_monitor_v2_aligned_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_aligned_bf_copi,
+ miso => reg_bsn_monitor_v2_aligned_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_bst_offload : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_bst_offload_copi,
- miso => reg_bsn_monitor_v2_bst_offload_cipo,
- mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
- miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_bst_offload_copi,
+ miso => reg_bsn_monitor_v2_bst_offload_cipo,
+ mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_beamlet_output : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_beamlet_output_copi,
- miso => reg_bsn_monitor_v2_beamlet_output_cipo,
- mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
- miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+ mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
+ );
-----------------------------------------------------------------------------
-- DP MUX to multiplex the c_sdp_N_beamsets via one beamlet output 10GbE link
@@ -1163,143 +1164,92 @@ begin
nw_10GbE_hdr_fields_in_arr(0) <= bf_10GbE_hdr_fields_out_arr(0);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_nof_input => c_sdp_N_beamsets,
- g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
+ generic map (
+ g_nof_input => c_sdp_N_beamsets,
+ g_sel_ctrl_invert => true,
+ g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
- snk_in_arr => bf_udp_sosi_arr,
- snk_out_arr => bf_udp_siso_arr,
+ snk_in_arr => bf_udp_sosi_arr,
+ snk_out_arr => bf_udp_siso_arr,
- src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
- src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
- );
+ src_out => nw_10gbe_beamlet_output_snk_in_arr(0),
+ src_in => nw_10gbe_beamlet_output_snk_out_arr(0)
+ );
---------------
-- nw_10GbE beamlet output via front_io QSFP[1]
---------------
u_nw_10GbE_beamlet_output: entity nw_10GbE_lib.nw_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_beamlet_output,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
- g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
- g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_xon_backpressure => true
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_beamlet_output,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_beamlet_output,
+ g_tx_fifo_size => c_fifo_tx_size_beamlet_output,
+ g_ip_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_xon_backpressure => true
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_nw_10GbE_mac_copi,
- reg_mac_miso => reg_nw_10GbE_mac_cipo,
+ reg_mac_mosi => reg_nw_10GbE_mac_copi,
+ reg_mac_miso => reg_nw_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
- snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
- snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
+ snk_out_arr => nw_10gbe_beamlet_output_snk_out_arr,
+ snk_in_arr => nw_10gbe_beamlet_output_snk_in_arr,
- src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
- src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
+ src_out_arr => nw_10gbe_beamlet_output_src_out_arr,
+ src_in_arr => nw_10gbe_beamlet_output_src_in_arr,
- -- Serial IO
- serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ -- Serial IO
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr(c_nof_10GbE_beamlet_output + c_quad - 1 downto c_quad),
- hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
- );
+ hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
+ );
end generate;
gen_use_ring : if g_use_ring generate
+
gen_xst_ring : if g_use_xsub generate
u_ring_lane_xst : entity ring_lib.ring_lane
- generic map (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_xst,
- g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
- g_use_dp_layer => true,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout_xst
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => xst_from_ri_sosi,
- to_lane_sosi => xst_to_ri_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => xst_bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
- end generate;
-
- gen_bf_ring : if g_use_bf generate
- bf_bs_sosi <= fsub_raw_sosi_arr(0);
-
- gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
- u_ring_lane_bf : entity ring_lib.ring_lane
generic map (
g_lane_direction => 1, -- transport in positive direction.
g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_packet_length => c_lane_payload_nof_longwords_xst,
g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
g_use_dp_layer => true,
- g_nof_rx_monitors => 1,
- g_nof_tx_monitors => 1,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
g_err_bi => c_err_bi,
g_nof_err_counts => c_nof_err_counts,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
g_validate_channel => c_validate_channel,
g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
+ g_sync_timeout => c_sync_timeout_xst
)
port map (
mm_rst => mm_rst,
@@ -1307,91 +1257,143 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
- from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
- to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
- bs_sosi => bf_bs_sosi, -- used for bsn and sync
-
- reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
- reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+ from_lane_sosi => xst_from_ri_sosi,
+ to_lane_sosi => xst_to_ri_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
+ bs_sosi => xst_bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
this_rn => this_rn,
N_rn => ring_info.N_rn,
rx_select => ring_info.use_cable_to_previous_rn,
tx_select => ring_info.use_cable_to_next_rn
);
+ end generate;
+
+ gen_bf_ring : if g_use_bf generate
+ bf_bs_sosi <= fsub_raw_sosi_arr(0);
+
+ gen_beamset_ring : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
+ u_ring_lane_bf : entity ring_lib.ring_lane
+ generic map (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_payload_nof_longwords_bf,
+ g_lane_total_nof_packets_w => c_lane_total_nof_packets_w,
+ g_use_dp_layer => true,
+ g_nof_rx_monitors => 1,
+ g_nof_tx_monitors => 1,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
+ bs_sosi => bf_bs_sosi, -- used for bsn and sync
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
end generate;
u_mem_mux_reg_ring_lane_info_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
- )
- port map (
- mosi => reg_ring_lane_info_bf_copi,
- miso => reg_ring_lane_info_bf_cipo,
- mosi_arr => reg_ring_lane_info_bf_copi_arr,
- miso_arr => reg_ring_lane_info_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
+ )
+ port map (
+ mosi => reg_ring_lane_info_bf_copi,
+ miso => reg_ring_lane_info_bf_cipo,
+ mosi_arr => reg_ring_lane_info_bf_copi_arr,
+ miso_arr => reg_ring_lane_info_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
+ );
u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
- )
- port map (
- mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
- miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
- mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
- miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_err_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_err_bf_copi,
- miso => reg_dp_block_validate_err_bf_cipo,
- mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
- miso_arr => reg_dp_block_validate_err_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_err_bf_copi,
+ miso => reg_dp_block_validate_err_bf_cipo,
+ mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_err_bf_cipo_arr
+ );
u_mem_mux_reg_dp_block_validate_bsn_at_sync_bf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_sdp_N_beamsets,
- g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
- )
- port map (
- mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
- miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
- mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
- miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
- );
+ generic map (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
+ )
+ port map (
+ mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1415,45 +1417,45 @@ begin
-- tr_10GbE ring via front_io QSFP[0]
-----------------------------------------------------------------------------
u_tr_10GbE_ring: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_ring_nof_mac_ip,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_fifo_tx_fill_ring,
- g_tx_fifo_size => c_fifo_tx_size_ring
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_ring_nof_mac_ip,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_fifo_tx_fill_ring,
+ g_tx_fifo_size => c_fifo_tx_size_ring
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => tr_10gbe_ring_src_out_arr,
- src_in_arr => tr_10gbe_ring_src_in_arr,
+ src_out_arr => tr_10gbe_ring_src_out_arr,
+ src_in_arr => tr_10gbe_ring_src_in_arr,
- snk_out_arr => tr_10gbe_ring_snk_out_arr,
- snk_in_arr => tr_10gbe_ring_snk_in_arr,
+ snk_out_arr => tr_10gbe_ring_snk_out_arr,
+ snk_in_arr => tr_10gbe_ring_snk_in_arr,
- -- Serial IO
- serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
- serial_rx_arr => tr_10gbe_ring_serial_rx_arr
- );
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_ring_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_ring_serial_rx_arr
+ );
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
@@ -1482,14 +1484,14 @@ begin
-- PLL
---------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
------------
-- LEDs
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 858a12ce9f8e979dbd3e1828ce5c5b972007d6fa..784fd68819b7ee6674c188f831b971ecf9def73a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -98,14 +98,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_statistics_offload is
generic (
@@ -517,13 +517,13 @@ begin
v.instance_count := 0; -- only used for XST
v.instance_address := 0; -- only used for XST
- -- The dp_sop = '1' when the packet has been read from statistics memory
- -- and is about to get out of the dp_fifo_fill_eop in
- -- u_dp_block_from_mm_dc. This ensures that the dp_sop identifies the
- -- sop of the offload packet. At the dp_sop:
- -- . the dp_header_info per packet offload can be released
- -- . the next packet offload can be prepared
- --
+ -- The dp_sop = '1' when the packet has been read from statistics memory
+ -- and is about to get out of the dp_fifo_fill_eop in
+ -- u_dp_block_from_mm_dc. This ensures that the dp_sop identifies the
+ -- sop of the offload packet. At the dp_sop:
+ -- . the dp_header_info per packet offload can be released
+ -- . the next packet offload can be prepared
+ --
elsif dp_sop = '1' then
-- Release dp_header_info for current packet offload
v.dp_header_info := dp_header_info;
@@ -564,7 +564,7 @@ begin
v.start_address := r.start_address + c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz; -- continue with next packet in this instance
v.crosslet_count := r.crosslet_count + 1;
if r.crosslet_count = reg_input.nof_crosslets - 1 then
- v.start_address := r.instance_address + 2**c_sdp_ram_st_xsq_addr_w; -- jump to first packet in next instance
+ v.start_address := r.instance_address + 2 ** c_sdp_ram_st_xsq_addr_w; -- jump to first packet in next instance
v.crosslet_count := 0;
v.instance_count := r.instance_count + 1;
v.instance_address := v.start_address; -- use v.start_address to avoid multipier needed in (r.instance_count + 1) * 2**c_sdp_ram_st_xsq_addr_w
@@ -592,48 +592,48 @@ begin
in_trigger <= in_sosi.sync and not reg_new_interval;
u_mms_common_variable_delay : entity common_lib.mms_common_variable_delay
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_enable_mosi => reg_enable_mosi,
- reg_enable_miso => reg_enable_miso,
-
- delay => p.nof_cycles_dly,
- trigger => in_trigger,
- trigger_en => trigger_en,
- trigger_dly => trigger_offload
- );
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_enable_mosi => reg_enable_mosi,
+ reg_enable_miso => reg_enable_miso,
+
+ delay => p.nof_cycles_dly,
+ trigger => in_trigger,
+ trigger_en => trigger_en,
+ trigger_dly => trigger_offload
+ );
u_dp_block_from_mm_dc : entity dp_lib.dp_block_from_mm_dc
- generic map (
- g_user_size => c_mm_user_size,
- g_data_size => c_mm_data_size,
- g_step_size => c_mm_step_size,
- g_nof_data => c_mm_nof_data,
- g_word_w => c_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => c_dp_stream_bsn_w,
- g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
- )
- port map(
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start_pulse => r.start_pulse,
- sync_in => r.start_sync,
- bsn_at_sync => hdr_input.bsn_at_sync,
- start_address => r.start_address,
- mm_mosi => master_mosi,
- mm_miso => master_miso,
- out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
- out_sosi => dp_block_from_mm_src_out,
- out_siso => dp_block_from_mm_src_in
- );
+ generic map (
+ g_user_size => c_mm_user_size,
+ g_data_size => c_mm_data_size,
+ g_step_size => c_mm_step_size,
+ g_nof_data => c_mm_nof_data,
+ g_word_w => c_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_bsn_incr_enable => false -- all offload block have same bsn_at_sync
+ )
+ port map(
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start_pulse => r.start_pulse,
+ sync_in => r.start_sync,
+ bsn_at_sync => hdr_input.bsn_at_sync,
+ start_address => r.start_address,
+ mm_mosi => master_mosi,
+ mm_miso => master_miso,
+ out_sop => dp_sop, -- = dp_block_from_mm_src_out.sop
+ out_sosi => dp_block_from_mm_src_out,
+ out_siso => dp_block_from_mm_src_in
+ );
-- The dp_sop is the sop of the packet that is about to be offloaded by
-- u_dp_offload_tx_v3. The r.dp_header_info must be available at the
@@ -644,16 +644,16 @@ begin
-- u_dp_pipeline_ready.
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => dp_block_from_mm_src_in,
- snk_in => dp_block_from_mm_src_out,
- -- ST source
- src_in => dp_offload_snk_out,
- src_out => dp_offload_snk_in
- );
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => dp_block_from_mm_src_in,
+ snk_in => dp_block_from_mm_src_out,
+ -- ST source
+ src_in => dp_offload_snk_out,
+ src_out => dp_offload_snk_in
+ );
-- The hdr_input.bsn_at_sync is passed on via r.dp_header_info so that
-- u_dp_offload_tx_v3 can put it in the udp_sosi header.
@@ -663,27 +663,27 @@ begin
-- is in fact not used, but useful to have in udp_sosi.sync (e.g. for the
-- tb).
u_dp_offload_tx_v3: entity dp_lib.dp_offload_tx_v3
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_word_w,
- g_symbol_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
- g_pipeline_ready => true
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- snk_in_arr(0) => dp_offload_snk_in,
- snk_out_arr(0) => dp_offload_snk_out,
- src_out_arr(0) => udp_sosi,
- src_in_arr(0) => out_siso,
- hdr_fields_in_arr(0) => r.dp_header_info
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_word_w,
+ g_symbol_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
+ g_pipeline_ready => true
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_hdr_dat_miso,
+ snk_in_arr(0) => dp_offload_snk_in,
+ snk_out_arr(0) => dp_offload_snk_out,
+ src_out_arr(0) => udp_sosi,
+ src_in_arr(0) => out_siso,
+ hdr_fields_in_arr(0) => r.dp_header_info
+ );
-- Debug signal, r_dp_header_rec must be available at the r_dp_header_sop
r_dp_header_sop <= dp_offload_snk_in.sop;
@@ -692,28 +692,28 @@ begin
out_sosi <= udp_sosi;
u_bsn_mon_udp : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bsn_monitor_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_offload_copi,
- reg_miso => reg_bsn_monitor_v2_offload_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => in_sosi.sync,
-
- in_sosi_arr(0) => udp_sosi
- );
+ generic map (
+ g_nof_streams => 1,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bsn_monitor_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_offload_copi,
+ reg_miso => reg_bsn_monitor_v2_offload_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => in_sosi.sync,
+
+ in_sosi_arr(0) => udp_sosi
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index c42b95e49f6a87ace78f6d4f0a6d4566a5d9563d..dbc1d39382c820493a4e0249d6033da19f6402e2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -49,11 +49,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_equalizer is
generic (
@@ -112,18 +112,18 @@ begin
-- g_reverse_len - 1 +
-- g_pipeline_mux_in + g_pipeline_mux_out = 1 + 0 + 2-1 + 0 + 1 = 3
u_pipeline_co_pol : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => 3
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_raw_sosi_arr,
- -- ST source
- src_out_arr => in_pipe_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => 3
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_raw_sosi_arr,
+ -- ST source
+ src_out_arr => in_pipe_raw_sosi_arr
+ );
-- The input subband data order is fsub[S_pn/Q_fft]_[N_sub][Q_fft] and
-- the [Q_fft] = [N_pol] index contains the X and Y polarizations.
@@ -132,23 +132,23 @@ begin
-- in_pipeline_raw_sosi_arr.
gen_cross_pol : for I in 0 to g_nof_streams - 1 generate
u_cross_pol : entity dp_lib.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => 1, -- serial to parallel section
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0, -- parallel to serial section
- g_pipeline_mux_out => 1,
- g_reverse_len => c_sdp_N_pol, -- = 2
- g_data_w => g_raw_dat_w * c_nof_complex,
- g_use_complex => true,
- g_signed => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_pipeline_demux_in => 1, -- serial to parallel section
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0, -- parallel to serial section
+ g_pipeline_mux_out => 1,
+ g_reverse_len => c_sdp_N_pol, -- = 2
+ g_data_w => g_raw_dat_w * c_nof_complex,
+ g_use_complex => true,
+ g_signed => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in => in_raw_sosi_arr(I),
- src_out => in_cross_raw_sosi_arr(I)
- );
+ snk_in => in_raw_sosi_arr(I),
+ src_out => in_cross_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -156,30 +156,30 @@ begin
-----------------------------------------------------------------------------
-- Total pipeline of sdp_subband_weights is: 5
u_sdp_subband_weigths : entity work.sdp_subband_weights
- generic map (
- g_gains_file_name => g_gains_file_name, -- for co polarization
- g_nof_streams => g_nof_streams,
- g_raw_dat_w => g_raw_dat_w
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ generic map (
+ g_gains_file_name => g_gains_file_name, -- for co polarization
+ g_nof_streams => g_nof_streams,
+ g_raw_dat_w => g_raw_dat_w
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- in_raw_sosi_arr => in_pipe_raw_sosi_arr,
- in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
+ in_raw_sosi_arr => in_pipe_raw_sosi_arr,
+ in_cross_raw_sosi_arr => in_cross_raw_sosi_arr,
- weighted_raw_sosi_arr => weighted_raw_sosi_arr,
- weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
+ weighted_raw_sosi_arr => weighted_raw_sosi_arr,
+ weighted_cross_raw_sosi_arr => weighted_cross_raw_sosi_arr,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- ram_gains_cross_mosi => ram_gains_cross_mosi,
- ram_gains_cross_miso => ram_gains_cross_miso
- );
+ ram_gains_cross_mosi => ram_gains_cross_mosi,
+ ram_gains_cross_miso => ram_gains_cross_miso
+ );
-----------------------------------------------------------------------------
-- Sum co + cross
@@ -191,17 +191,17 @@ begin
in_raw_sosi_2arr_2(I)(1) <= weighted_cross_raw_sosi_arr(I);
u_dp_complex_add : entity dp_lib.dp_complex_add
- generic map(
- g_nof_inputs => c_sdp_N_pol,
- g_data_w => c_gain_out_dat_w
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
+ generic map(
+ g_nof_inputs => c_sdp_N_pol,
+ g_data_w => c_gain_out_dat_w
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
- snk_in_arr => in_raw_sosi_2arr_2(I),
- src_out => sum_raw_sosi_arr(I)
- );
+ snk_in_arr => in_raw_sosi_2arr_2(I),
+ src_out => sum_raw_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -216,51 +216,51 @@ begin
-- g_raw_fraction_w, so that the output width remains the same as the input
-- width g_raw_dat_w.
u_dp_requantize_out_raw : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_raw_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_raw_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_raw_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_raw_sosi_arr(I)
+ );
-- For quant output round the entire fraction, so that the output width
-- becomes c_quant_dat_w.
u_dp_requantize_out_quant : entity dp_lib.dp_requantize
- generic map (
- g_complex => true,
- g_representation => "SIGNED",
- g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
- g_lsb_round => true,
- g_lsb_round_clip => false,
- g_msb_clip => true, -- clip subband overflow
- g_msb_clip_symmetric => false,
- g_pipeline_remove_lsb => c_pipeline_remove_lsb,
- g_pipeline_remove_msb => c_pipeline_remove_msb,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => c_quant_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => sum_raw_sosi_arr(I),
- -- ST source
- src_out => out_quant_sosi_arr(I)
- );
+ generic map (
+ g_complex => true,
+ g_representation => "SIGNED",
+ g_lsb_w => c_sdp_W_sub_weight_fraction + g_raw_fraction_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => false,
+ g_msb_clip => true, -- clip subband overflow
+ g_msb_clip_symmetric => false,
+ g_pipeline_remove_lsb => c_pipeline_remove_lsb,
+ g_pipeline_remove_msb => c_pipeline_remove_msb,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => c_quant_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => sum_raw_sosi_arr(I),
+ -- ST source
+ src_out => out_quant_sosi_arr(I)
+ );
end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
index 75cbf8a89d652a8f80617f94658647e4aefb2f6a..51654e7910ae5dce0e1717daabdd23bf9026358e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
@@ -39,11 +39,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.sdp_pkg.all;
entity sdp_subband_weights is
generic (
@@ -123,66 +123,67 @@ begin
end if;
end if;
end process;
+
gains_rd_address <= TO_UVEC(cnt, c_gain_addr_w);
-----------------------------------------------------------------------------
-- Gain
-----------------------------------------------------------------------------
u_gains_co : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => g_gains_file_name
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_raw_sosi_arr,
- out_sosi_arr => weighted_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => g_gains_file_name
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_raw_sosi_arr,
+ out_sosi_arr => weighted_raw_sosi_arr
+ );
u_gains_cross : entity dp_lib.mms_dp_gain_serial_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
- g_complex_data => true,
- g_complex_gain => true,
- g_gain_w => c_sdp_W_sub_weight,
- g_in_dat_w => g_raw_dat_w,
- g_out_dat_w => c_gain_out_dat_w,
- g_gains_file_name => "UNUSED"
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- ram_gains_mosi => ram_gains_cross_mosi,
- ram_gains_miso => ram_gains_cross_miso,
-
- -- ST interface
- gains_rd_address => gains_rd_address,
-
- in_sosi_arr => in_cross_raw_sosi_arr,
- out_sosi_arr => weighted_cross_raw_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_gains => c_sdp_Q_fft * c_sdp_N_sub,
+ g_complex_data => true,
+ g_complex_gain => true,
+ g_gain_w => c_sdp_W_sub_weight,
+ g_in_dat_w => g_raw_dat_w,
+ g_out_dat_w => c_gain_out_dat_w,
+ g_gains_file_name => "UNUSED"
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ ram_gains_mosi => ram_gains_cross_mosi,
+ ram_gains_miso => ram_gains_cross_miso,
+
+ -- ST interface
+ gains_rd_address => gains_rd_address,
+
+ in_sosi_arr => in_cross_raw_sosi_arr,
+ out_sosi_arr => weighted_cross_raw_sosi_arr
+ );
end str;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
index c63631e39f34e9252cd88cef8d4004ec457e68dd..5e3a0e905bc68202f9604281e4c3d79527a6be67 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_output.vhd
@@ -30,17 +30,17 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use work.sdp_pkg.all;
-use work.sdp_bdo_pkg.all;
-use work.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use work.sdp_pkg.all;
+ use work.sdp_bdo_pkg.all;
+ use work.tb_sdp_pkg.all;
entity tb_sdp_beamformer_output is
generic (
@@ -59,40 +59,40 @@ architecture tb of tb_sdp_beamformer_output is
-- Restrict generic values to within supported range
constant c_nof_destinations_max : natural :=
- sel_a_b(g_nof_destinations_max <= c_sdp_bdo_mm_nof_destinations_max,
+ sel_a_b(g_nof_destinations_max <= c_sdp_bdo_mm_nof_destinations_max,
g_nof_destinations_max,
- c_sdp_bdo_mm_nof_destinations_max);
- constant c_nof_destinations : natural :=
- func_sdp_bdo_parse_nof_destinations(g_nof_destinations, c_nof_destinations_max);
+ c_sdp_bdo_mm_nof_destinations_max);
+ constant c_nof_destinations : natural :=
+ func_sdp_bdo_parse_nof_destinations(g_nof_destinations, c_nof_destinations_max);
- constant c_beamlet_mod : natural := 2**c_sdp_W_beamlet;
+ constant c_beamlet_mod : natural := 2**c_sdp_W_beamlet;
constant c_init_re : natural := 0;
constant c_init_im : natural := 1;
constant c_init_bsn : natural := 0;
constant c_bf_block_len : natural := c_sdp_N_pol_bf * c_sdp_S_sub_bf; -- = 2 * 488 = 976
constant c_bf_gap_size : natural := c_sdp_N_fft - c_bf_block_len; -- = 1024 - 976 = 48
- constant c_exp_beamlet_scale : natural := natural(1.0 / 2.0**9 * real(c_sdp_unit_beamlet_scale));
+ constant c_exp_beamlet_scale : natural := natural(1.0 / 2.0 ** 9 * real(c_sdp_unit_beamlet_scale));
constant c_exp_beamlet_scale_slv : std_logic_vector(c_sdp_W_beamlet_scale-1 downto 0) :=
- to_uvec(c_exp_beamlet_scale, c_sdp_W_beamlet_scale);
+ to_uvec(c_exp_beamlet_scale, c_sdp_W_beamlet_scale);
constant c_gn_id : natural := 3;
constant c_gn_id_slv : std_logic_vector(c_sdp_W_gn_id - 1 downto 0) :=
- to_uvec(c_gn_id, c_sdp_W_gn_id);
+ to_uvec(c_gn_id, c_sdp_W_gn_id);
constant c_id : std_logic_vector(7 downto 0) := to_uvec(c_gn_id, 8);
constant c_cep_eth_src_mac : std_logic_vector(47 downto 0) := c_sdp_cep_eth_src_mac_47_16 &
- func_sdp_gn_index_to_mac_15_0(c_gn_id);
+ func_sdp_gn_index_to_mac_15_0(c_gn_id);
constant c_cep_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 &
- func_sdp_gn_index_to_ip_15_0(c_gn_id);
+ func_sdp_gn_index_to_ip_15_0(c_gn_id);
constant c_cep_udp_src_port : std_logic_vector(15 downto 0) := c_sdp_cep_udp_src_port_15_8 & c_id;
constant c_mdi_reorder_nof_blocks_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_reorder_nof_blocks_look_up_table(c_nof_destinations_max);
constant c_mdi_nof_blocks_per_packet : natural := c_mdi_reorder_nof_blocks_arr(c_nof_destinations);
constant c_mdi_nof_beamlets_per_block_first_destinations_arr : t_natural_arr(1 to c_nof_destinations_max) :=
- func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
+ func_sdp_bdo_nof_beamlets_per_block_first_destinations_look_up_table(c_nof_destinations_max);
constant c_mdi_nof_beamlets_per_block_per_destination : natural :=
- c_mdi_nof_beamlets_per_block_first_destinations_arr(c_nof_destinations);
+ c_mdi_nof_beamlets_per_block_first_destinations_arr(c_nof_destinations);
constant c_mdi_nof_beamlets_all_destinations : natural := c_mdi_nof_blocks_per_packet * c_sdp_S_sub_bf;
@@ -101,16 +101,17 @@ architecture tb of tb_sdp_beamformer_output is
constant c_exp_payload_error : std_logic := '0';
constant c_exp_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
- constant c_exp_sdp_info : t_sdp_info := (to_uvec(7, 6), -- antenna_field_index
- to_uvec(601, 10), -- station_id
- '0', -- antenna_band_index
- x"FFFFFFFF", -- observation_id
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
+ constant c_exp_sdp_info : t_sdp_info := ( -- antenna_field_index
+ to_uvec(7, 6),
+ to_uvec(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"FFFFFFFF", -- observation_id
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
signal mm_init : std_logic := '1';
signal tb_end : std_logic := '0';
@@ -281,105 +282,105 @@ begin
end process;
u_bf_sosi : entity dp_lib.dp_stream_stimuli
- generic map (
- -- initializations
- g_sync_period => 10,
- g_sync_offset => 0,
- g_use_complex => true,
- g_re_init => c_init_re,
- g_im_init => c_init_im,
- g_bsn_init => TO_DP_BSN(c_init_bsn),
- g_err_init => 0, -- not used
- g_err_incr => 0, -- not used
- g_channel_init => 0, -- not used
- g_channel_incr => 0, -- not used
- -- specific
- g_in_dat_w => c_sdp_W_beamlet, -- = 8
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => c_bf_block_len,
- g_pkt_gap => c_bf_gap_size,
- g_wait_last_evt => 100
- )
- port map (
- rst => mm_init,
- clk => dp_clk,
-
- -- Generate stimuli
- src_out => bf_sosi,
-
- -- End of stimuli
- last_snk_in => open, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => open, -- trigger verify to verify the last_snk_in
- tb_end => tb_end
- );
+ generic map (
+ -- initializations
+ g_sync_period => 10,
+ g_sync_offset => 0,
+ g_use_complex => true,
+ g_re_init => c_init_re,
+ g_im_init => c_init_im,
+ g_bsn_init => TO_DP_BSN(c_init_bsn),
+ g_err_init => 0, -- not used
+ g_err_incr => 0, -- not used
+ g_channel_init => 0, -- not used
+ g_channel_incr => 0, -- not used
+ -- specific
+ g_in_dat_w => c_sdp_W_beamlet, -- = 8
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => c_bf_block_len,
+ g_pkt_gap => c_bf_gap_size,
+ g_wait_last_evt => 100
+ )
+ port map (
+ rst => mm_init,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_out => bf_sosi,
+
+ -- End of stimuli
+ last_snk_in => open, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => open, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end
+ );
-- Beamlet Data Output (BDO)
u_dut: entity work.sdp_beamformer_output
- generic map (
- g_beamset_id => g_beamset_id,
- g_use_transpose => g_use_transpose,
- g_nof_destinations_max => c_nof_destinations_max,
- g_sim_force_bsn_error => g_sim_force_bsn_error
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- reg_hdr_dat_mosi => hdr_dat_copi,
- reg_hdr_dat_miso => hdr_dat_cipo,
-
- reg_destinations_copi => reg_destinations_copi,
- reg_destinations_cipo => reg_destinations_cipo,
-
- reg_dp_xonoff_mosi => reg_dp_xonoff_copi,
- reg_dp_xonoff_miso => reg_dp_xonoff_cipo,
-
- in_sosi => bf_sosi,
- out_sosi => bdo_sosi,
- out_siso => bdo_siso,
-
- sdp_info => c_exp_sdp_info,
- beamlet_scale => c_exp_beamlet_scale_slv,
- gn_id => c_gn_id_slv,
-
- -- Source MAC/IP/UDP are not used, c_sdp_cep_hdr_field_sel selects MM programmable instead
- eth_src_mac => bdo_eth_src_mac,
- ip_src_addr => bdo_ip_src_addr,
- udp_src_port => bdo_udp_src_port,
-
- hdr_fields_out => open
- );
+ generic map (
+ g_beamset_id => g_beamset_id,
+ g_use_transpose => g_use_transpose,
+ g_nof_destinations_max => c_nof_destinations_max,
+ g_sim_force_bsn_error => g_sim_force_bsn_error
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ reg_hdr_dat_mosi => hdr_dat_copi,
+ reg_hdr_dat_miso => hdr_dat_cipo,
+
+ reg_destinations_copi => reg_destinations_copi,
+ reg_destinations_cipo => reg_destinations_cipo,
+
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo,
+
+ in_sosi => bf_sosi,
+ out_sosi => bdo_sosi,
+ out_siso => bdo_siso,
+
+ sdp_info => c_exp_sdp_info,
+ beamlet_scale => c_exp_beamlet_scale_slv,
+ gn_id => c_gn_id_slv,
+
+ -- Source MAC/IP/UDP are not used, c_sdp_cep_hdr_field_sel selects MM programmable instead
+ eth_src_mac => bdo_eth_src_mac,
+ ip_src_addr => bdo_ip_src_addr,
+ udp_src_port => bdo_udp_src_port,
+
+ hdr_fields_out => open
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_longword_w,
- g_symbol_w => c_octet_w,
- g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => rx_hdr_dat_copi,
- reg_hdr_dat_miso => rx_hdr_dat_cipo,
-
- snk_in_arr(0) => bdo_sosi,
- snk_out_arr(0) => bdo_siso,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_copi,
+ reg_hdr_dat_miso => rx_hdr_dat_cipo,
+
+ snk_in_arr(0) => bdo_sosi,
+ snk_out_arr(0) => bdo_siso,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
-----------------------------------------------------------------------------
-- Beamlet offload packet header
@@ -423,7 +424,7 @@ begin
c_exp_beamlet_index,
c_sdp_cep_nof_blocks_per_packet,
c_sdp_cep_nof_beamlets_per_block,
- exp_dp_bsn);
+ exp_dp_bsn);
p_verify_one_beamlet_header : process
variable v_bool : boolean;
@@ -448,13 +449,13 @@ begin
rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w - 1 downto 0);
proc_sdp_rx_beamlet_octets(dp_clk,
- rx_beamlet_sosi,
- rx_beamlet_cnt,
- rx_beamlet_valid,
- rx_beamlet_arr_re,
- rx_beamlet_arr_im,
- rx_packet_list_re,
- rx_packet_list_im);
+ rx_beamlet_sosi,
+ rx_beamlet_cnt,
+ rx_beamlet_valid,
+ rx_beamlet_arr_re,
+ rx_beamlet_arr_im,
+ rx_packet_list_re,
+ rx_packet_list_im);
p_verify_one_rx_beamlet_list : process
-- Nof complex (= nof re = nof im = c_N) values in t_sdp_beamlet_packet_list
@@ -532,7 +533,7 @@ begin
mdi_exp_beamlet_index,
c_mdi_nof_blocks_per_packet,
mdi_exp_nof_beamlets_per_block,
- mdi_exp_dp_bsn);
+ mdi_exp_dp_bsn);
p_verify_multi_beamlet_header : process
variable v_nof_beamlets : natural;
@@ -575,14 +576,14 @@ begin
rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w - 1 downto 0);
proc_sdp_rx_beamlet_octets(c_mdi_nof_blocks_per_packet,
- dp_clk,
- rx_beamlet_sosi,
- rx_mdi_beamlet_cnt,
- rx_beamlet_valid,
- rx_beamlet_arr_re,
- rx_beamlet_arr_im,
- rx_mdi_packet_list_re,
- rx_mdi_packet_list_im);
+ dp_clk,
+ rx_beamlet_sosi,
+ rx_mdi_beamlet_cnt,
+ rx_beamlet_valid,
+ rx_beamlet_arr_re,
+ rx_beamlet_arr_im,
+ rx_mdi_packet_list_re,
+ rx_mdi_packet_list_im);
p_verify_multi_rx_beamlet_list : process
-- Nof complex (= nof re = nof im = c_N) values in packet_list
@@ -598,11 +599,11 @@ begin
rx_mdi_beamlet_list_re <= func_reorder_transpose_packet(c_sdp_S_sub_bf,
c_mdi_nof_blocks_per_packet,
c_sdp_N_pol_bf,
- rx_mdi_packet_list_re);
+ rx_mdi_packet_list_re);
rx_mdi_beamlet_list_im <= func_reorder_transpose_packet(c_sdp_S_sub_bf,
c_mdi_nof_blocks_per_packet,
c_sdp_N_pol_bf,
- rx_mdi_packet_list_im);
+ rx_mdi_packet_list_im);
rx_mdi_beamlet_list_val <= '1';
-- Wait until rx_beamlet_list is valid
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 39f4fb1d949f32e0ef866fd5d3505dfc7a93635a..6e32afed25be92023855decd5c411642a057ff78 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -33,15 +33,15 @@
-- and cur_crosslets_info of the dut by comparing it to the expected output.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_crosslets_subband_select is
end tb_sdp_crosslets_subband_select;
@@ -163,9 +163,10 @@ begin
-- Data blocks
------------------------------------------------------------------------------
gen_stimuli : for K in 0 to c_sdp_P_pfb - 1 generate
+
p_st_stimuli : process
- variable v_re : natural := 0 + k * 2**5;
- variable v_im : natural := 1 + k * 2**5;
+ variable v_re : natural := 0 + k * 2 ** 5;
+ variable v_im : natural := 1 + k * 2 ** 5;
begin
tb_end <= '0';
st_sosi_arr(K) <= c_dp_sosi_rst;
@@ -249,8 +250,8 @@ begin
exp_sosi.eop <= '1';
end if;
- exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col * c_crosslet_offsets(v_offset) + v_col + v_row * 2**5)(c_sdp_W_crosslet - 1 downto 0));
- exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1 + (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col * c_crosslet_offsets(v_offset) + v_col + v_row * 2**5)(c_sdp_W_crosslet - 1 downto 0));
+ exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col * c_crosslet_offsets(v_offset) + v_col + v_row * 2 ** 5)(c_sdp_W_crosslet - 1 downto 0));
+ exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1 + (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col * c_crosslet_offsets(v_offset) + v_col + v_row * 2 ** 5)(c_sdp_W_crosslet - 1 downto 0));
proc_common_wait_some_cycles(clk, 1);
end loop;
@@ -278,28 +279,28 @@ begin
end process;
u_dut : entity work.sdp_crosslets_subband_select
- generic map (
- g_N_crosslets => c_N_crosslets,
- g_ctrl_interval_size_min => 1
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_crosslets_info_mosi => mm_mosi,
- reg_crosslets_info_miso => mm_miso,
-
- reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
- reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-
- -- Streaming
- in_sosi_arr => in_sosi_arr,
- out_sosi => out_sosi,
-
- cur_crosslets_info_rec => cur_crosslets_info_rec,
- prev_crosslets_info_rec => prev_crosslets_info_rec
- );
+ generic map (
+ g_N_crosslets => c_N_crosslets,
+ g_ctrl_interval_size_min => 1
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => mm_mosi,
+ reg_crosslets_info_miso => mm_miso,
+
+ reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
+ reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
+
+ -- Streaming
+ in_sosi_arr => in_sosi_arr,
+ out_sosi => out_sosi,
+
+ cur_crosslets_info_rec => cur_crosslets_info_rec,
+ prev_crosslets_info_rec => prev_crosslets_info_rec
+ );
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index ef323ac858df135b1b286ed9e8a2a1728705fed4..3255912c7a0259a65b4b24d5d468722ca83c13df 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -34,12 +34,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.sdp_pkg.all;
entity tb_sdp_info is
end tb_sdp_info;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index a6f9b19d3f5f044bee8c7b314f833dac4efd3275..8be443c097b915d09f6147f164f05c6ea31c9735 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -26,13 +26,13 @@
-- Description:
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use work.sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use work.sdp_pkg.all;
package tb_sdp_pkg is
-----------------------------------------------------------------------------
@@ -44,67 +44,74 @@ package tb_sdp_pkg is
-----------------------------------------------------------------------------
-- Statistics offload
-----------------------------------------------------------------------------
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header;
+ function func_sdp_compose_stat_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header;
function func_sdp_verify_stat_header(g_statistics_type : string; in_hdr, exp_hdr : t_sdp_stat_header) return boolean;
-----------------------------------------------------------------------------
-- Beamlet output via 10GbE to CEP (= central processor)
-----------------------------------------------------------------------------
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- nof_blocks_per_packet : natural;
- nof_beamlets_per_block : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- nof_blocks_per_packet : natural;
- nof_beamlets_per_block : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header;
-
- function func_sdp_verify_cep_header(in_hdr : t_sdp_cep_header;
- exp_hdr : t_sdp_cep_header;
- beamlet_index_mod : boolean) return boolean;
- function func_sdp_verify_cep_header(in_hdr : t_sdp_cep_header;
- exp_hdr : t_sdp_cep_header) return boolean;
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ nof_blocks_per_packet : natural;
+ nof_beamlets_per_block : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ nof_blocks_per_packet : natural;
+ nof_beamlets_per_block : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header;
+
+ function func_sdp_verify_cep_header(
+ in_hdr : t_sdp_cep_header;
+ exp_hdr : t_sdp_cep_header;
+ beamlet_index_mod : boolean) return boolean;
+ function func_sdp_verify_cep_header(
+ in_hdr : t_sdp_cep_header;
+ exp_hdr : t_sdp_cep_header) return boolean;
-----------------------------------------------------------------------------
-- Subband equalizer (ESub)
@@ -116,9 +123,10 @@ package tb_sdp_pkg is
-- . sp_weight = (sp_esub_gain, sp_esub_phase)
-- . cross_phasor = (cross_subband_ampl, cross_subband_phase)
-- . cross_weight = (cross_esub_gain, cross_esub_phase)
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
+ function func_sdp_subband_equalizer(
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ return t_real_arr; -- 0:3 = ampl, phase, re, im
-----------------------------------------------------------------------------
-- Beamformer (BF)
@@ -126,10 +134,11 @@ package tb_sdp_pkg is
-- Model the SDP beamformer for one signal input (sp) and nof_rem remnant signal inputs (rem)
-- . for local beamformer on one node use nof_rem = S_pn - 1
-- . for remote beamformer with nof_rn ring nodes use nof_rem = nof_rn * S_pn - 1
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
- return t_real_arr; -- 0:3 = ampl, phase, re, im
+ function func_sdp_beamformer(
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
+ return t_real_arr; -- 0:3 = ampl, phase, re, im
-----------------------------------------------------------------------------
-- Beamlet output packet
@@ -153,25 +162,25 @@ package tb_sdp_pkg is
-- Read beamlet packet octets per re and im parts
procedure proc_sdp_rx_beamlet_octets(
- constant c_nof_blocks_per_packet : in natural;
- signal clk : in std_logic;
- signal rx_beamlet_sosi : in t_dp_sosi;
- signal rx_beamlet_cnt : inout natural;
- signal rx_beamlet_valid : out std_logic;
- signal rx_beamlet_arr_re : out t_sdp_beamlet_part_arr;
- signal rx_beamlet_arr_im : out t_sdp_beamlet_part_arr;
- signal rx_packet_list_re : out t_slv_8_arr;
- signal rx_packet_list_im : out t_slv_8_arr);
+ constant c_nof_blocks_per_packet : in natural;
+ signal clk : in std_logic;
+ signal rx_beamlet_sosi : in t_dp_sosi;
+ signal rx_beamlet_cnt : inout natural;
+ signal rx_beamlet_valid : out std_logic;
+ signal rx_beamlet_arr_re : out t_sdp_beamlet_part_arr;
+ signal rx_beamlet_arr_im : out t_sdp_beamlet_part_arr;
+ signal rx_packet_list_re : out t_slv_8_arr;
+ signal rx_packet_list_im : out t_slv_8_arr);
procedure proc_sdp_rx_beamlet_octets(
- signal clk : in std_logic;
- signal rx_beamlet_sosi : in t_dp_sosi;
- signal rx_beamlet_cnt : inout natural;
- signal rx_beamlet_valid : out std_logic;
- signal rx_beamlet_arr_re : out t_sdp_beamlet_part_arr;
- signal rx_beamlet_arr_im : out t_sdp_beamlet_part_arr;
- signal rx_packet_list_re : out t_sdp_beamlet_packet_list;
- signal rx_packet_list_im : out t_sdp_beamlet_packet_list);
+ signal clk : in std_logic;
+ signal rx_beamlet_sosi : in t_dp_sosi;
+ signal rx_beamlet_cnt : inout natural;
+ signal rx_beamlet_valid : out std_logic;
+ signal rx_beamlet_arr_re : out t_sdp_beamlet_part_arr;
+ signal rx_beamlet_arr_im : out t_sdp_beamlet_part_arr;
+ signal rx_packet_list_re : out t_sdp_beamlet_packet_list;
+ signal rx_packet_list_im : out t_sdp_beamlet_packet_list);
end package tb_sdp_pkg;
package body tb_sdp_pkg is
@@ -191,18 +200,19 @@ package body tb_sdp_pkg is
return c_ip_15_0;
end func_sdp_gn_index_to_ip_15_0;
- function func_sdp_compose_stat_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- g_statistics_type : string;
- weighted_subbands_flag : std_logic;
- gn_index : natural;
- nof_block_per_sync : natural;
- sst_signal_input : natural;
- beamlet_index : natural;
- subband_index : natural;
- xst_signal_input_A : natural;
- xst_signal_input_B : natural;
- dp_bsn : natural) return t_sdp_stat_header is
+ function func_sdp_compose_stat_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ g_statistics_type : string;
+ weighted_subbands_flag : std_logic;
+ gn_index : natural;
+ nof_block_per_sync : natural;
+ sst_signal_input : natural;
+ beamlet_index : natural;
+ subband_index : natural;
+ xst_signal_input_A : natural;
+ xst_signal_input_B : natural;
+ dp_bsn : natural) return t_sdp_stat_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
@@ -347,16 +357,17 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_stat_header;
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- nof_blocks_per_packet : natural;
- nof_beamlets_per_block : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ nof_blocks_per_packet : natural;
+ nof_beamlets_per_block : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_mac_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_mac_15_0(gn_index);
variable v_hdr : t_sdp_cep_header;
@@ -413,78 +424,82 @@ package body tb_sdp_pkg is
return v_hdr;
end func_sdp_compose_cep_header;
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- nof_blocks_per_packet : natural;
- nof_beamlets_per_block : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ nof_blocks_per_packet : natural;
+ nof_beamlets_per_block : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
constant c_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0;
begin
return func_sdp_compose_cep_header(c_ip_src_addr,
- ip_header_checksum,
- sdp_info,
- gn_index,
- payload_error,
- beamlet_scale,
- beamlet_index,
- nof_blocks_per_packet,
- nof_beamlets_per_block,
- dp_bsn);
+ ip_header_checksum,
+ sdp_info,
+ gn_index,
+ payload_error,
+ beamlet_scale,
+ beamlet_index,
+ nof_blocks_per_packet,
+ nof_beamlets_per_block,
+ dp_bsn);
end func_sdp_compose_cep_header;
- function func_sdp_compose_cep_header(ip_src_addr : std_logic_vector;
- ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header(
+ ip_src_addr : std_logic_vector;
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
begin
return func_sdp_compose_cep_header(ip_src_addr,
- ip_header_checksum,
- sdp_info,
- gn_index,
- payload_error,
- beamlet_scale,
- beamlet_index,
- c_sdp_cep_nof_blocks_per_packet,
- c_sdp_cep_nof_beamlets_per_block,
- dp_bsn);
+ ip_header_checksum,
+ sdp_info,
+ gn_index,
+ payload_error,
+ beamlet_scale,
+ beamlet_index,
+ c_sdp_cep_nof_blocks_per_packet,
+ c_sdp_cep_nof_beamlets_per_block,
+ dp_bsn);
end func_sdp_compose_cep_header;
- function func_sdp_compose_cep_header(ip_header_checksum : natural;
- sdp_info : t_sdp_info; -- app header
- gn_index : natural;
- payload_error : std_logic;
- beamlet_scale : natural;
- beamlet_index : natural;
- dp_bsn : natural) return t_sdp_cep_header is
+ function func_sdp_compose_cep_header(
+ ip_header_checksum : natural;
+ sdp_info : t_sdp_info; -- app header
+ gn_index : natural;
+ payload_error : std_logic;
+ beamlet_scale : natural;
+ beamlet_index : natural;
+ dp_bsn : natural) return t_sdp_cep_header is
-- Use sim default dst and src MAC, IP, UDP port from sdp_pkg.vhd and based on gn_index
constant c_ip_15_0 : std_logic_vector(15 downto 0) := func_sdp_gn_index_to_ip_15_0(gn_index);
constant c_ip_src_addr : std_logic_vector(31 downto 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0;
begin
return func_sdp_compose_cep_header(c_ip_src_addr,
- ip_header_checksum,
- sdp_info,
- gn_index,
- payload_error,
- beamlet_scale,
- beamlet_index,
- c_sdp_cep_nof_blocks_per_packet,
- c_sdp_cep_nof_beamlets_per_block,
- dp_bsn);
+ ip_header_checksum,
+ sdp_info,
+ gn_index,
+ payload_error,
+ beamlet_scale,
+ beamlet_index,
+ c_sdp_cep_nof_blocks_per_packet,
+ c_sdp_cep_nof_beamlets_per_block,
+ dp_bsn);
end func_sdp_compose_cep_header;
- function func_sdp_verify_cep_header(in_hdr : t_sdp_cep_header;
- exp_hdr : t_sdp_cep_header;
- beamlet_index_mod : boolean) return boolean is
+ function func_sdp_verify_cep_header(
+ in_hdr : t_sdp_cep_header;
+ exp_hdr : t_sdp_cep_header;
+ beamlet_index_mod : boolean) return boolean is
variable v_beamlet_index : natural;
begin
-- eth header
@@ -544,15 +559,17 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_cep_header;
- function func_sdp_verify_cep_header(in_hdr : t_sdp_cep_header;
- exp_hdr : t_sdp_cep_header) return boolean is
+ function func_sdp_verify_cep_header(
+ in_hdr : t_sdp_cep_header;
+ exp_hdr : t_sdp_cep_header) return boolean is
begin
return func_sdp_verify_cep_header(in_hdr, exp_hdr, false);
end func_sdp_verify_cep_header;
- function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
- cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
+ function func_sdp_subband_equalizer(
+ sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
+ cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
+ return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_cross_ampl, v_cross_phase, v_cross_re, v_cross_im : real;
variable v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : real;
@@ -574,10 +591,11 @@ package body tb_sdp_pkg is
return v_tuple;
end;
- function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
- rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
- nof_rem : natural)
- return t_real_arr is -- 0:3 = ampl, phase, re, im
+ function func_sdp_beamformer(
+ sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
+ nof_rem : natural)
+ return t_real_arr is -- 0:3 = ampl, phase, re, im
variable v_nof_rem : real := real(nof_rem); -- BF for one sp and nof_rem remnant signal inputs
variable v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : real;
variable v_rem_ampl, v_rem_phase, v_rem_re, v_rem_im : real;
@@ -626,9 +644,9 @@ package body tb_sdp_pkg is
variable v_list : t_sdp_beamlet_packet_list;
begin
v_list := func_reorder_transpose_packet(c_sdp_cep_nof_blocks_per_packet,
- c_sdp_cep_nof_beamlets_per_block,
- c_sdp_N_pol_bf,
- packet_list);
+ c_sdp_cep_nof_beamlets_per_block,
+ c_sdp_N_pol_bf,
+ packet_list);
return v_list;
end func_sdp_transpose_beamlet_packet;
@@ -637,9 +655,9 @@ package body tb_sdp_pkg is
variable v_list : t_sdp_beamlet_packet_list;
begin
v_list := func_reorder_transpose_packet(c_sdp_cep_nof_beamlets_per_block,
- c_sdp_cep_nof_blocks_per_packet,
- c_sdp_N_pol_bf,
- packet_list);
+ c_sdp_cep_nof_blocks_per_packet,
+ c_sdp_N_pol_bf,
+ packet_list);
return v_list;
end func_sdp_undo_transpose_beamlet_packet;
@@ -714,14 +732,14 @@ package body tb_sdp_pkg is
signal rx_packet_list_im : out t_sdp_beamlet_packet_list) is
begin
proc_sdp_rx_beamlet_octets(
- c_sdp_cep_nof_blocks_per_packet, -- 4 blocks/packet
- clk,
- rx_beamlet_sosi,
- rx_beamlet_cnt,
- rx_beamlet_valid ,
- rx_beamlet_arr_re,
- rx_beamlet_arr_im,
- rx_packet_list_re,
- rx_packet_list_im);
+ c_sdp_cep_nof_blocks_per_packet, -- 4 blocks/packet
+ clk,
+ rx_beamlet_sosi,
+ rx_beamlet_cnt,
+ rx_beamlet_valid ,
+ rx_beamlet_arr_re,
+ rx_beamlet_arr_im,
+ rx_packet_list_re,
+ rx_packet_list_im);
end proc_sdp_rx_beamlet_octets;
end tb_sdp_pkg;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 235b962b494b04abec47bb73ebe22f026af5bdfa..3f4780a13fadeca533836a0e3a24990e69fce5f6 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -37,24 +37,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, ring_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_str_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ring_lib.ring_pkg.all;
-use work.sdp_pkg.all;
-use work.tb_sdp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ring_lib.ring_pkg.all;
+ use work.sdp_pkg.all;
+ use work.tb_sdp_pkg.all;
entity tb_sdp_statistics_offload is
generic (
-- All
g_fast_mm_clk : boolean := true; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
g_statistics_type : string := "XST";
g_offload_time : natural := 50;
g_reverse_word_order : boolean := true; -- when TRUE then stream LSB word after MSB word.
@@ -98,22 +98,24 @@ architecture tb of tb_sdp_statistics_offload is
constant c_exp_ip_header_checksum : natural := 0; -- 0 in this local tb, calculated by IO eth when used in design
- constant c_exp_sdp_info : t_sdp_info := (TO_UVEC(7, 6), -- antenna_field_index
- TO_UVEC(601, 10), -- station_id
- '0', -- antenna_band_index
- x"FFFFFFFF", -- observation_id
- b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
- '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
- '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
- '0', -- beam_repositioning_flag
- x"1400" -- block_period = 5120
- );
-
- constant c_exp_ring_info : t_ring_info := (TO_UVEC(g_O_rn, 8), -- GN index of first GN in ring
- TO_UVEC(g_N_rn, 8), -- number of GN in ring
- '0', -- use_cable_to_next_rn
- '0' -- use_cable_to_previous_rn
- );
+ constant c_exp_sdp_info : t_sdp_info := ( -- antenna_field_index
+ TO_UVEC(7, 6),
+ TO_UVEC(601, 10), -- station_id
+ '0', -- antenna_band_index
+ x"FFFFFFFF", -- observation_id
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
+
+ constant c_exp_ring_info : t_ring_info := ( -- GN index of first GN in ring
+ TO_UVEC(g_O_rn, 8),
+ TO_UVEC(g_N_rn, 8), -- number of GN in ring
+ '0', -- use_cable_to_next_rn
+ '0' -- use_cable_to_previous_rn
+ );
constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf;
@@ -133,7 +135,7 @@ architecture tb of tb_sdp_statistics_offload is
constant c_ram_size : natural := c_packet_size * c_nof_packets_max;
constant c_ram_w : natural := ceil_log2(c_ram_size);
--CONSTANT c_ram_buf : t_c_mem := (c_mem_ram_rd_latency, c_ram_w, 32, 2**c_ram_w, 'X');
- constant c_ram_buf : t_c_mem := (1, c_ram_w, 32, 2**c_ram_w, 'X');
+ constant c_ram_buf : t_c_mem := (1, c_ram_w, 32, 2 ** c_ram_w, 'X');
-- RAM dimensions
-- . nof_statistics_per_packet = c_mm_nof_data * c_mm_data_size / c_sdp_W_statistic_sz
@@ -144,7 +146,7 @@ architecture tb of tb_sdp_statistics_offload is
constant c_mm_ram_size : natural := c_mm_nof_data * c_mm_data_size * c_nof_packets_max; -- = c_ram_size
constant c_mm_nof_step : natural := c_mm_step_size / c_mm_data_size;
- constant c_mm_Xsq_span : natural := 2**ceil_log2(c_sdp_N_crosslets_max * c_packet_size); -- XST: 2**ceil_log2(7 * 576) = 4096
+ constant c_mm_Xsq_span : natural := 2 ** ceil_log2(c_sdp_N_crosslets_max * c_packet_size); -- XST: 2**ceil_log2(7 * 576) = 4096
-- Define block timing.
constant c_bsn_init : natural := 0;
@@ -406,7 +408,7 @@ begin
exp_subband_index,
exp_xst_signal_input_A,
exp_xst_signal_input_B,
- exp_dp_bsn);
+ exp_dp_bsn);
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
@@ -488,7 +490,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1024 32bit Words
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 512 Statistic values
D := S; -- range c_mm_nof_data = 512 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 1
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 1
U := S; -- range c_sdp_N_sub = 512 SST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
@@ -520,7 +522,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 1952
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 976 Statistic values
D := S / c_sdp_N_pol_bf; -- range c_mm_nof_data = 488 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
B := D; -- range c_sdp_S_sub_bf = 488 dual polarization BST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = 1 packet
@@ -561,7 +563,7 @@ begin
W := rx_valid_cnt; -- range c_packet_size = 576
S := W / c_sdp_W_statistic_sz; -- range c_nof_statistics_per_packet = 288 Statistic values
D := S / c_nof_complex; -- range c_mm_nof_data = 144 Data values, because
- -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
+ -- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
X := D; -- range c_sdp_X_sq = 144 complex XST values
I := W mod c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
P := rx_packet_cnt mod c_rx_nof_packets; -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
@@ -595,100 +597,100 @@ begin
end process;
u_ram: entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- -- MM write port clock domain.
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_wr_en,
- wr_dat_a => ram_wr_data,
- adr_a => ram_wr_addr,
-
- -- DP read only port clock domain.
- rst_b => mm_rst,
- clk_b => mm_clk,
- adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_en_b => master_mosi.rd,
- rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val_b => master_miso.rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ -- MM write port clock domain.
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_wr_en,
+ wr_dat_a => ram_wr_data,
+ adr_a => ram_wr_addr,
+
+ -- DP read only port clock domain.
+ rst_b => mm_rst,
+ clk_b => mm_clk,
+ adr_b => master_mosi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_en_b => master_mosi.rd,
+ rd_dat_b => master_miso.rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val_b => master_miso.rdval
+ );
u_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => c_word_w,
- g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
-
- snk_in_arr(0) => sdp_offload_sosi,
- snk_out_arr(0) => sdp_offload_siso,
-
- src_out_arr(0) => rx_offload_sosi,
-
- hdr_fields_out_arr(0) => rx_hdr_fields_out,
- hdr_fields_raw_arr(0) => rx_hdr_fields_raw
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => c_word_w,
+ g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+
+ snk_in_arr(0) => sdp_offload_sosi,
+ snk_out_arr(0) => sdp_offload_siso,
+
+ src_out_arr(0) => rx_offload_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
-- SDP info
u_dut: entity work.sdp_statistics_offload
- generic map (
- g_statistics_type => g_statistics_type,
- g_offload_time => g_offload_time,
- g_reverse_word_order => g_reverse_word_order,
- g_beamset_id => g_beamset_id,
- g_P_sq => g_P_sq,
- g_crosslets_direction => g_crosslets_direction
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- MM
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- reg_enable_mosi => enable_mosi,
- reg_enable_miso => enable_miso,
-
- reg_hdr_dat_mosi => hdr_dat_mosi,
- reg_hdr_dat_miso => hdr_dat_miso,
-
- -- ST
- in_sosi => in_sosi,
- new_interval => new_interval,
-
- out_sosi => sdp_offload_sosi,
- out_siso => sdp_offload_siso,
-
- -- Inputs from other blocks
- eth_src_mac => c_node_eth_src_mac,
- udp_src_port => c_node_udp_src_port,
- ip_src_addr => c_node_ip_src_addr,
-
- gn_index => gn_index,
- ring_info => c_exp_ring_info,
- sdp_info => c_exp_sdp_info,
- weighted_subbands_flag => weighted_subbands_flag,
-
- nof_crosslets => c_mm_nof_crosslets,
- prev_crosslets_info_rec => in_crosslets_info_rec
- );
+ generic map (
+ g_statistics_type => g_statistics_type,
+ g_offload_time => g_offload_time,
+ g_reverse_word_order => g_reverse_word_order,
+ g_beamset_id => g_beamset_id,
+ g_P_sq => g_P_sq,
+ g_crosslets_direction => g_crosslets_direction
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- MM
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ reg_enable_mosi => enable_mosi,
+ reg_enable_miso => enable_miso,
+
+ reg_hdr_dat_mosi => hdr_dat_mosi,
+ reg_hdr_dat_miso => hdr_dat_miso,
+
+ -- ST
+ in_sosi => in_sosi,
+ new_interval => new_interval,
+
+ out_sosi => sdp_offload_sosi,
+ out_siso => sdp_offload_siso,
+
+ -- Inputs from other blocks
+ eth_src_mac => c_node_eth_src_mac,
+ udp_src_port => c_node_udp_src_port,
+ ip_src_addr => c_node_ip_src_addr,
+
+ gn_index => gn_index,
+ ring_info => c_exp_ring_info,
+ sdp_info => c_exp_sdp_info,
+ weighted_subbands_flag => weighted_subbands_flag,
+
+ nof_crosslets => c_mm_nof_crosslets,
+ prev_crosslets_info_rec => in_crosslets_info_rec
+ );
-- Verify crosslets_info functions
assert c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv) report "Error in func_sdp_map_crosslets_info()" severity FAILURE;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_beamformer_output.vhd
index 4f6652e9d9122117ba3cc823d696246877d71052..99dce287491be21caeb77dfecc7fa09ae232b14b 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_beamformer_output.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_sdp_beamformer_output is
end tb_tb_sdp_beamformer_output;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index c325ba9be21b0f986b274e1060af40f0e48548b3..8e3b09a1a56baab607a1dcedfaac54dfd43ea924 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -28,7 +28,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_sdp_statistics_offload is
end tb_tb_sdp_statistics_offload;
@@ -36,22 +36,22 @@ end tb_tb_sdp_statistics_offload;
architecture tb of tb_tb_sdp_statistics_offload is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- -- All
--- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
--- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
--- g_statistics_type : STRING := "SST";
--- g_offload_time : NATURAL := 500;
--- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
--- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
--- g_nof_sync : NATURAL := 3;
--- -- BST
--- g_beamset_id : NATURAL := 0;
--- -- XST
--- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
--- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
--- g_P_sq : NATURAL := c_sdp_P_sq
--- g_nof_crosslets : NATURAL := 1;
--- g_crosslets_direction : INTEGER := 1; -- +1 or -1
+ -- -- All
+ -- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ -- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ -- g_statistics_type : STRING := "SST";
+ -- g_offload_time : NATURAL := 500;
+ -- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
+ -- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
+ -- g_nof_sync : NATURAL := 3;
+ -- -- BST
+ -- g_beamset_id : NATURAL := 0;
+ -- -- XST
+ -- g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
+ -- g_N_rn : NATURAL := 16; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
+ -- g_P_sq : NATURAL := c_sdp_P_sq
+ -- g_nof_crosslets : NATURAL := 1;
+ -- g_crosslets_direction : INTEGER := 1; -- +1 or -1
u_sst : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, true, 3, 3);
u_sst_no_reverse : entity work.tb_sdp_statistics_offload generic map( true, "SST", 50, false, 3, 3);
diff --git a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_eth_tester_wrapper.vhd b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_eth_tester_wrapper.vhd
index 9c83af4c58457be7465f5226897c41d57e9a33a0..4bf08f44ce9ffa842673c191df071a4543c68551 100644
--- a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_eth_tester_wrapper.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_eth_tester_wrapper.vhd
@@ -31,16 +31,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_generator_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_generator_pkg.all;
entity rdma_generator_eth_tester_wrapper is
port (
@@ -147,7 +147,7 @@ entity rdma_generator_eth_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_generator_eth_tester_wrapper;
architecture str of rdma_generator_eth_tester_wrapper is
@@ -183,91 +183,91 @@ architecture str of rdma_generator_eth_tester_wrapper is
signal st_rst : std_logic := '0';
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => false,
- g_use_dp_header => true,
- g_hdr_field_arr => c_rdma_generator_dp_hdr_field_arr,
- g_hdr_field_sel => c_rdma_generator_dp_hdr_field_sel,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => false,
+ g_use_dp_header => true,
+ g_hdr_field_arr => c_rdma_generator_dp_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_generator_dp_hdr_field_sel,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
diff --git a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_pkg.vhd b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_pkg.vhd
index 4c5ec3f221a9597d10aaf16a0a6afb05c9bc4bd5..c9429451dcaea5608424a16a495ebe4c5182f46e 100644
--- a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_pkg.vhd
@@ -23,11 +23,11 @@
-- Description:
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
package rdma_generator_pkg is
constant c_rdma_generator_nof_octet_generate_100gbe : natural := 64;
@@ -55,13 +55,13 @@ package rdma_generator_pkg is
constant c_rdma_generator_dp_hdr_field_sel : std_logic_vector(c_rdma_generator_dp_nof_hdr_fields - 1 downto 0) := "0100";
constant c_rdma_generator_dp_hdr_field_arr : t_common_field_arr(c_rdma_generator_dp_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
- );
+ ( field_name_pad("dp_length" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved"), "RW", 15, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
+ );
constant c_rdma_generator_dp_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_generator_dp_hdr_field_arr, c_word_w));
- constant c_rdma_generator_dp_reg_hdr_dat_addr_span : natural := 2**c_rdma_generator_dp_reg_hdr_dat_addr_w;
+ constant c_rdma_generator_dp_reg_hdr_dat_addr_span : natural := 2 ** c_rdma_generator_dp_reg_hdr_dat_addr_w;
constant c_rdma_generator_dp_app_hdr_len : natural := 12; -- octets
@@ -71,46 +71,46 @@ package rdma_generator_pkg is
constant c_rdma_generator_roce_hdr_field_sel : std_logic_vector(c_rdma_generator_roce_nof_hdr_fields - 1 downto 0) := "111011111001" & "0100" & "1111111111111" & "111" & "1";
constant c_rdma_generator_roce_hdr_field_arr : t_common_field_arr(c_rdma_generator_roce_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(0) ), -- c_eth_tester_ip_dst_addr
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- c_eth_tester_udp_dst_port
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(0) ), -- depends on BG block size, so set by data path
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
- ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
- ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
- ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
- ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
- ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
- ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("bth_opcode" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("bth_se" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_m" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_pad" ), "RW", 2, field_default(0) ),
+ ( field_name_pad("bth_tver" ), "RW", 4, field_default(0) ),
+ ( field_name_pad("bth_partition_key" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_fres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_bres" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_a" ), "RW", 6, field_default(0) ),
+ ( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
- ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
+ ( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
- ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
- );
+ ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
+ );
constant c_rdma_generator_roce_reg_hdr_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_generator_roce_hdr_field_arr, c_word_w));
- constant c_rdma_generator_roce_reg_hdr_dat_addr_span : natural := 2**c_rdma_generator_roce_reg_hdr_dat_addr_w;
+ constant c_rdma_generator_roce_reg_hdr_dat_addr_span : natural := 2 ** c_rdma_generator_roce_reg_hdr_dat_addr_w;
constant c_rdma_generator_roce_hdr_len : natural := 32; -- octets
constant c_rdma_generator_roce_icrc_len : natural := 4; -- octets
diff --git a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester.vhd b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester.vhd
index 638a8d10df007b71d3bc7c68d9aaba7fc0334d2d..5629b3bd012aea09df41a7338be31179367c7212 100644
--- a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester.vhd
@@ -32,15 +32,15 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_external_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_generator_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_generator_pkg.all;
entity rdma_generator_roce_tester is
port (
@@ -77,7 +77,7 @@ entity rdma_generator_roce_tester is
ip_src_addr : in std_logic_vector(c_network_ip_addr_w - 1 downto 0);
udp_src_port : in std_logic_vector(c_network_udp_port_w - 1 downto 0)
- );
+ );
end rdma_generator_roce_tester;
architecture str of rdma_generator_roce_tester is
@@ -85,71 +85,68 @@ architecture str of rdma_generator_roce_tester is
constant c_reverse_byte_order : boolean := false;
signal eth_tester_tx_sosi_arr : t_dp_sosi_arr(0 downto 0) := (others => c_dp_sosi_rst);
signal eth_tester_tx_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => true,
- g_use_dp_header => false,
- g_hdr_calc_ip_crc => true,
- g_hdr_field_arr => c_rdma_generator_roce_hdr_field_arr,
- g_hdr_field_sel => c_rdma_generator_roce_hdr_field_sel,
- -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
- g_hdr_app_len => c_rdma_generator_roce_hdr_len + c_rdma_generator_roce_icrc_len,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => eth_tester_tx_sosi_arr,
- tx_udp_siso_arr => eth_tester_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => true,
+ g_use_dp_header => false,
+ g_hdr_calc_ip_crc => true,
+ g_hdr_field_arr => c_rdma_generator_roce_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_generator_roce_hdr_field_sel,
+ -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
+ g_hdr_app_len => c_rdma_generator_roce_hdr_len + c_rdma_generator_roce_icrc_len,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => eth_tester_tx_sosi_arr,
+ tx_udp_siso_arr => eth_tester_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
u_icrc_append : entity rdma_icrc_external_lib.append_crc_dp_wrapper
- port map (
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- out_dp_sosi => tx_udp_sosi_arr(0),
- out_dp_siso => tx_udp_siso_arr(0),
- in_dp_sosi => eth_tester_tx_sosi_arr(0),
- in_dp_siso => eth_tester_tx_siso_arr(0)
- );
-
+ port map (
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ out_dp_sosi => tx_udp_sosi_arr(0),
+ out_dp_siso => tx_udp_siso_arr(0),
+ in_dp_sosi => eth_tester_tx_sosi_arr(0),
+ in_dp_siso => eth_tester_tx_siso_arr(0)
+ );
end str;
diff --git a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester_wrapper.vhd b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester_wrapper.vhd
index 9af4401c2a2a6b512247f622dfa4dab1dbc2a3fb..6f362d4994528c7054908e4ae0bdb46dcc46feb8 100644
--- a/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester_wrapper.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester_wrapper.vhd
@@ -32,16 +32,16 @@
-- vivado using the AXI AMM Bridge IP.
library IEEE, common_lib, dp_lib, axi4_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use axi4_lib.axi4_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use work.rdma_generator_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use work.rdma_generator_pkg.all;
entity rdma_generator_roce_tester_wrapper is
port (
@@ -148,7 +148,7 @@ entity rdma_generator_roce_tester_wrapper is
reg_strobe_total_count_rx_avs_write : in std_logic;
reg_strobe_total_count_rx_avs_writedata : in std_logic_vector(32 - 1 downto 0)
- );
+ );
end rdma_generator_roce_tester_wrapper;
architecture str of rdma_generator_roce_tester_wrapper is
@@ -185,94 +185,94 @@ architecture str of rdma_generator_roce_tester_wrapper is
signal st_rst : std_logic := '0';
begin
u_eth_tester : entity eth_lib.eth_tester
- generic map (
- g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
- g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
- g_use_eth_header => false,
- g_use_ip_udp_header => true,
- g_use_dp_header => false,
- g_hdr_calc_ip_crc => true,
- g_hdr_field_arr => c_rdma_generator_roce_hdr_field_arr,
- g_hdr_field_sel => c_rdma_generator_roce_hdr_field_sel,
- -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
- g_hdr_app_len => c_rdma_generator_roce_hdr_len + c_rdma_generator_roce_icrc_len,
- g_remove_crc => false
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => eth_src_mac,
- ip_src_addr => ip_src_addr,
- udp_src_port => udp_src_port,
-
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
-
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
+ generic map (
+ g_nof_octet_generate => c_rdma_generator_nof_octet_generate_100gbe,
+ g_nof_octet_output => c_rdma_generator_nof_octet_output_100gbe,
+ g_use_eth_header => false,
+ g_use_ip_udp_header => true,
+ g_use_dp_header => false,
+ g_hdr_calc_ip_crc => true,
+ g_hdr_field_arr => c_rdma_generator_roce_hdr_field_arr,
+ g_hdr_field_sel => c_rdma_generator_roce_hdr_field_sel,
+ -- Add icrc length here as g_hdr_app_len is used to calculate the total packet length.
+ g_hdr_app_len => c_rdma_generator_roce_hdr_len + c_rdma_generator_roce_icrc_len,
+ g_remove_crc => false
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => eth_src_mac,
+ ip_src_addr => ip_src_addr,
+ udp_src_port => udp_src_port,
+
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
-- DP to AXI4
u_axi4_tx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- dp_rst => st_rst,
-
- dp_in_sosi => tx_udp_sosi_arr(0),
- dp_in_siso => tx_udp_siso_arr(0),
-
- axi4_out_sosi => tx_udp_axi4_sosi,
- axi4_out_siso => tx_udp_axi4_siso
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ dp_rst => st_rst,
+
+ dp_in_sosi => tx_udp_sosi_arr(0),
+ dp_in_siso => tx_udp_siso_arr(0),
+
+ axi4_out_sosi => tx_udp_axi4_sosi,
+ axi4_out_siso => tx_udp_axi4_siso
+ );
u_axi4_rx_udp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_axi4_rl => 0,
- g_dp_rl => 1,
- g_active_low_rst => true
- )
- port map (
- in_clk => st_clk,
- in_rst => aresetn,
-
- axi4_in_sosi => rx_udp_axi4_sosi,
- axi4_in_siso => rx_udp_axi4_siso,
-
- dp_out_sosi => rx_udp_sosi_arr(0),
- dp_out_siso => rx_udp_siso_arr(0)
- );
+ generic map (
+ g_axi4_rl => 0,
+ g_dp_rl => 1,
+ g_active_low_rst => true
+ )
+ port map (
+ in_clk => st_clk,
+ in_rst => aresetn,
+
+ axi4_in_sosi => rx_udp_axi4_sosi,
+ axi4_in_siso => rx_udp_axi4_siso,
+
+ dp_out_sosi => rx_udp_sosi_arr(0),
+ dp_out_siso => rx_udp_siso_arr(0)
+ );
-- Wire Records to IN/OUT ports.
-- tx_udp
@@ -297,6 +297,7 @@ begin
-- reverse order of bytes
gen_reverse_bytes : if c_reverse_byte_order generate
+
gen_tx_data : for I in 0 to c_nof_byte - 1 generate
tx_udp_tdata( (I + 1) * c_octet_w - 1 downto I * c_octet_w) <= tx_udp_axi4_sosi.tdata((c_nof_byte - I) * c_octet_w - 1 downto (c_nof_byte - 1 - I) * c_octet_w);
tx_udp_tkeep(I) <= tx_udp_axi4_sosi.tkeep(c_nof_byte - 1 - I);
diff --git a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
index 905fe77cabb4212ad3c36883ef568ab13f7b68f2..73110b092c4f1932143172a4e328d32e548d21c0 100644
--- a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
@@ -34,23 +34,23 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
library IEEE, common_lib, dp_lib, diag_lib, technology_lib, tech_tse_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_components_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use eth_lib.tb_eth_tester_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_components_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use eth_lib.tb_eth_tester_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_rdma_generator is
generic (
@@ -82,11 +82,11 @@ end tb_rdma_generator;
architecture tb of tb_rdma_generator is
-- use to distinguish logging from tb instances in tb_tb
- constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
+ constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
constant mm_clk_period : time := 10 ns; -- 100 MHz
- constant c_nof_st_clk_per_s : natural := 200 * 10**6;
- constant st_clk_period : time := (10**9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
+ constant c_nof_st_clk_per_s : natural := 200 * 10 ** 6;
+ constant st_clk_period : time := (10 ** 9 / c_nof_st_clk_per_s) * 1 ns; -- 5 ns, 200 MHz
constant c_bg_block_len_first : natural := ceil_div(g_bg_ctrl_first.samples_per_packet, g_nof_octet_generate);
constant c_bg_block_len_others : natural := ceil_div(g_bg_ctrl_others.samples_per_packet, g_nof_octet_generate);
@@ -101,7 +101,6 @@ architecture tb of tb_rdma_generator is
-- Use REAL to avoid NATURAL overflow in bps calculation
-
constant c_bg_nof_bps_first : real := real(c_bg_block_len_first * c_octet_w) * real(c_nof_st_clk_per_s) / real(c_bg_slot_len_first);
constant c_bg_nof_bps_others : real := real(c_bg_block_len_others * c_octet_w) * real(c_nof_st_clk_per_s) / real(c_bg_slot_len_others);
constant c_bg_nof_bps_total : real := c_bg_nof_bps_first + real(g_nof_streams - 1) * c_bg_nof_bps_others;
@@ -259,11 +258,11 @@ begin
proc_mem_mm_bus_wr(v_offset + 16#7#, v_udp_dst_port + I, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
-- use signed to fit 32 b in INTEGER
proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr),
- mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)),
- mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)),
- mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
end loop;
---------------------------------------------------------------------------
@@ -275,8 +274,8 @@ begin
proc_mem_mm_bus_wr(I * 2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
-- Prepare the BG
- proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate),
- mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate),
+ mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 2, bg_ctrl_arr(I).blocks_per_sync, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 4, bg_ctrl_arr(I).mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
@@ -301,7 +300,7 @@ begin
end loop;
-- Wait until Tx FIFOs have emptied for all streams
- while unsigned(tx_fifo_rd_emp_arr(g_nof_streams - 1 downto 0)) /= 2**g_nof_streams - 1 loop
+ while unsigned(tx_fifo_rd_emp_arr(g_nof_streams - 1 downto 0)) /= 2 ** g_nof_streams - 1 loop
proc_common_wait_some_cycles(st_clk, 1);
end loop;
proc_common_wait_some_cycles(st_clk, c_bg_sync_period_max);
@@ -315,18 +314,18 @@ begin
for I in g_nof_streams - 1 downto 0 loop
if I = 0 then
print_str(c_tb_str &
- "ETH bit rate (" & natural'image(I) & ") :" &
- " c_bg_nof_bps_first = " & real'image(c_bg_nof_bps_first) & " bps");
+ "ETH bit rate (" & natural'image(I) & ") :" &
+ " c_bg_nof_bps_first = " & real'image(c_bg_nof_bps_first) & " bps");
else
print_str(c_tb_str &
- "ETH bit rate (" & natural'image(I) & ") :" &
- " c_bg_nof_bps_others = " & real'image(c_bg_nof_bps_others) & " bps");
+ "ETH bit rate (" & natural'image(I) & ") :" &
+ " c_bg_nof_bps_others = " & real'image(c_bg_nof_bps_others) & " bps");
end if;
end loop;
if g_nof_streams > 1 then
- print_str(c_tb_str &
- "ETH bit rate total :" &
- " c_bg_nof_bps_total = " & real'image(c_bg_nof_bps_total) & " bps");
+ print_str(c_tb_str &
+ "ETH bit rate total :" &
+ " c_bg_nof_bps_total = " & real'image(c_bg_nof_bps_total) & " bps");
end if;
-------------------------------------------------------------------------
@@ -355,49 +354,49 @@ begin
-- Print logging
print_str(c_tb_str &
- "Tx total counts monitor(" & natural'image(I) & ") :" &
- " nof_packet = " & natural'image(tx_total_count_nof_packet_arr(I)));
+ "Tx total counts monitor(" & natural'image(I) & ") :" &
+ " nof_packet = " & natural'image(tx_total_count_nof_packet_arr(I)));
print_str(c_tb_str &
- "Rx total counts monitor(" & natural'image(I) & ") :" &
- " nof_packet = " & natural'image(rx_total_count_nof_packet_arr(I)) &
- ", nof_valid = " & natural'image(rx_total_count_nof_valid_arr(I)) &
- ", nof_corrupted = " & natural'image(rx_total_count_nof_corrupted_arr(I)));
+ "Rx total counts monitor(" & natural'image(I) & ") :" &
+ " nof_packet = " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ ", nof_valid = " & natural'image(rx_total_count_nof_valid_arr(I)) &
+ ", nof_corrupted = " & natural'image(rx_total_count_nof_corrupted_arr(I)));
-- Verify, only log when wrong
- if c_bg_nof_bps_total < 10.0**9 then
+ if c_bg_nof_bps_total < 10.0 ** 9 then
assert tx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
- " = Expected count" severity ERROR;
+ "Wrong Tx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ " = Expected count" severity ERROR;
assert rx_total_count_nof_packet_arr(I) = exp_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Rx total nof packets count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
- " = Expected count" severity ERROR;
+ "Wrong Rx total nof packets count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(exp_total_count_nof_packet_arr(I)) &
+ " = Expected count" severity ERROR;
assert rx_total_count_nof_valid_arr(I) = rx_exp_total_count_nof_valid_arr(I) report c_tb_str &
- "Wrong Rx total nof valids count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
- " = Expected count" severity ERROR;
+ "Wrong Rx total nof valids count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_valid_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_valid_arr(I)) &
+ " = Expected count" severity ERROR;
assert rx_total_count_nof_corrupted_arr(I) = rx_exp_total_count_nof_corrupted_arr(I) report c_tb_str &
- "Wrong Rx total nof corrupted count(" & natural'image(I) &
- "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
- " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
- " = Expected count" severity ERROR;
+ "Wrong Rx total nof corrupted count(" & natural'image(I) &
+ "), Rx count = " & natural'image(rx_total_count_nof_corrupted_arr(I)) &
+ " /= " & natural'image(rx_exp_total_count_nof_corrupted_arr(I)) &
+ " = Expected count" severity ERROR;
else
-- Verify that Tx total nof packets = Rx total nof packets, also when
-- BG experiences siso.xon block level flow control, to stay below
-- 1 Gbps of the 1GbE link rate.
assert tx_total_count_nof_packet_arr(I) = rx_total_count_nof_packet_arr(I) report c_tb_str &
- "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
- "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
- " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
- " = Rx count" severity ERROR;
+ "Wrong Tx-Rx total nof packets count(" & natural'image(I) &
+ "), Tx count = " & natural'image(tx_total_count_nof_packet_arr(I)) &
+ " /= " & natural'image(rx_total_count_nof_packet_arr(I)) &
+ " = Rx count" severity ERROR;
end if;
end loop;
@@ -422,28 +421,28 @@ begin
-- Print logging
print_str(c_tb_str &
- "Tx BSN monitor(" & natural'image(I) & ") :" &
- " nof_sop = " & natural'image(tx_mon_nof_sop_arr(I)) &
- ", nof_valid = " & natural'image(tx_mon_nof_valid_arr(I)) &
- ", latency = " & natural'image(tx_mon_latency_arr(I)));
+ "Tx BSN monitor(" & natural'image(I) & ") :" &
+ " nof_sop = " & natural'image(tx_mon_nof_sop_arr(I)) &
+ ", nof_valid = " & natural'image(tx_mon_nof_valid_arr(I)) &
+ ", latency = " & natural'image(tx_mon_latency_arr(I)));
- if c_bg_nof_bps_total < 10.0**9 then
+ if c_bg_nof_bps_total < 10.0 ** 9 then
-- Verify BSN monitors only when the BG sync interval is stable, so
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
if I = 0 then
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report
- c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report
- c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report
+ c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report
+ c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
else
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report
- c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report
- c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report
+ c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report
+ c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
end if;
- assert tx_mon_latency_arr(I) = c_tx_exp_latency report
- c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
+ assert tx_mon_latency_arr(I) = c_tx_exp_latency report
+ c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
-- exact Rx latency is therefore hard to predetermine. The actual
@@ -451,7 +450,7 @@ begin
-- the latency when it is more or less fixed.
if c_rx_exp_latency_en then
assert almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 10) report
- c_tb_str & "Wrong rx latency using st interface (" & natural'image(I) & ")" severity ERROR;
+ c_tb_str & "Wrong rx latency using st interface (" & natural'image(I) & ")" severity ERROR;
end if;
end if;
end loop;
@@ -465,45 +464,45 @@ begin
end process;
dut : entity work.rdma_generator_roce_tester
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- st_pps => st_pps,
-
- -- UDP transmit interface
- eth_src_mac => c_gn_eth_src_mac,
- ip_src_addr => c_gn_ip_src_addr,
- udp_src_port => c_gn_udp_src_port,
- tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
-
- tx_udp_sosi_arr => tx_udp_sosi_arr,
- tx_udp_siso_arr => tx_udp_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => rx_udp_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_bg_ctrl_copi,
- reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
- reg_dp_split_copi => reg_dp_split_copi,
- reg_dp_split_cipo => reg_dp_split_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
- );
-
- -- Loop back at streaming sosi level
- rx_udp_sosi_arr <= tx_udp_sosi_arr;
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_pps => st_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => c_gn_eth_src_mac,
+ ip_src_addr => c_gn_ip_src_addr,
+ udp_src_port => c_gn_udp_src_port,
+ tx_fifo_rd_emp_arr => tx_fifo_rd_emp_arr,
+
+ tx_udp_sosi_arr => tx_udp_sosi_arr,
+ tx_udp_siso_arr => tx_udp_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => rx_udp_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_bg_ctrl_copi,
+ reg_bg_ctrl_cipo => reg_bg_ctrl_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_cipo,
+ reg_dp_split_copi => reg_dp_split_copi,
+ reg_dp_split_cipo => reg_dp_split_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
+ );
+
+ -- Loop back at streaming sosi level
+ rx_udp_sosi_arr <= tx_udp_sosi_arr;
end tb;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1024.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1024.vhd
index 28f7f81a9e1fe0e7ab5bb6cf463c26ef983d2f6d..4528290f17d461b01990ca7f883919e44627f02a 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1024.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1024.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D1024 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
@@ -25,20 +25,19 @@ package PCK_CRC32_D1024 is
-- convention: the first serial bit is D[1023]
function nextCRC32_D1024
(Data: std_logic_vector(1023 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D1024;
-
package body PCK_CRC32_D1024 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 1024
-- convention: the first serial bit is D[1023]
function nextCRC32_D1024
- (Data: std_logic_vector(1023 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(1023 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(1023 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D128.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D128.vhd
index 56e2add6cfc4b7570ba4a13baa3e0959c8e8bf71..da817e7703e4dc1409d68b7abca6a0d1d18f0f06 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D128.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D128.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D128 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
@@ -25,20 +25,19 @@ package PCK_CRC32_D128 is
-- convention: the first serial bit is D[127]
function nextCRC32_D128
(Data: std_logic_vector(127 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D128;
-
package body PCK_CRC32_D128 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 128
-- convention: the first serial bit is D[127]
function nextCRC32_D128
- (Data: std_logic_vector(127 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(127 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(127 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D16.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D16.vhd
index 3358f8acec98611a7da6a43d59da8b30bb1c01ad..d7d75453d48f9c1e55b63ce92dfb797c4dcf5d81 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D16.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D16.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D16 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
@@ -25,20 +25,19 @@ package PCK_CRC32_D16 is
-- convention: the first serial bit is D[15]
function nextCRC32_D16
(Data: std_logic_vector(15 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D16;
-
package body PCK_CRC32_D16 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
-- data width: 16
-- convention: the first serial bit is D[15]
function nextCRC32_D16
- (Data: std_logic_vector(15 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(15 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(15 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1_reversed.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1_reversed.vhd
index 842d62dddb1f4f52826b2593bebb1c946e7d6664..f0daf17b440cc509bb5c289d97a215bfd9c3e848 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1_reversed.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D1_reversed.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D1_reversed is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
@@ -25,20 +25,19 @@ package PCK_CRC32_D1_reversed is
-- convention: the first serial bit is D[0]
function prevCRC32_D1
(Data : std_logic;
- crc : std_logic_vector(31 downto 0))
+ crc : std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D1_reversed;
-
package body PCK_CRC32_D1_reversed is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
-- data width: 1
-- convention: the first serial bit is D[0]
function prevCRC32_D1
- (Data : std_logic;
+ (Data : std_logic;
crc : std_logic_vector(31 downto 0))
- return std_logic_vector is
+ return std_logic_vector is
variable d : std_logic_vector(0 downto 0);
variable c : std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D256.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D256.vhd
index f85ee6fb9b24e349ad101eb728827b99442b4bb4..d02e0989ac95af24fce14044f50f1b3004ddf410 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D256.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D256.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D256 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
@@ -25,20 +25,19 @@ package PCK_CRC32_D256 is
-- convention: the first serial bit is D[255]
function nextCRC32_D256
(Data: std_logic_vector(255 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D256;
-
package body PCK_CRC32_D256 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
-- data width: 256
-- convention: the first serial bit is D[255]
function nextCRC32_D256
- (Data: std_logic_vector(255 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(255 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(255 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D32.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D32.vhd
index 1b30aa6c4f9976d3e2db4262d6fee75ed41ad196..03f646f026f827991f197ad32034d51e7383a159 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D32.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D32.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D32 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
@@ -25,20 +25,19 @@ package PCK_CRC32_D32 is
-- convention: the first serial bit is D[31]
function nextCRC32_D32
(Data: std_logic_vector(31 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D32;
-
package body PCK_CRC32_D32 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
-- data width: 32
-- convention: the first serial bit is D[31]
function nextCRC32_D32
- (Data: std_logic_vector(31 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(31 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(31 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D512.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D512.vhd
index 88b555b11b8200b1cc6b23aa7f97fe2e5c3427f6..d08173b82e5dd6406ff8a052ba48dc46319c6d82 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D512.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D512.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D512 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
@@ -25,20 +25,19 @@ package PCK_CRC32_D512 is
-- convention: the first serial bit is D[511]
function nextCRC32_D512
(Data: std_logic_vector(511 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D512;
-
package body PCK_CRC32_D512 is
-- polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
-- data width: 512
-- convention: the first serial bit is D[511]
function nextCRC32_D512
- (Data: std_logic_vector(511 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(511 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(511 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D64.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D64.vhd
index ec12fcb9560852b235b2bcc7649c61dc8b053360..e5172c42aa468f706fffe0243f7638a4f079e06e 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D64.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D64.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D64 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
@@ -25,20 +25,19 @@ package PCK_CRC32_D64 is
-- convention: the first serial bit is D[63]
function nextCRC32_D64
(Data: std_logic_vector(63 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D64;
-
package body PCK_CRC32_D64 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 64
-- convention: the first serial bit is D[63]
function nextCRC32_D64
- (Data: std_logic_vector(63 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(63 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(63 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D8.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D8.vhd
index 8b75ac54dd356da7919b857c394fb72810b202c3..19bffeffc5868e27ae0aa866aa8f721d56499a5a 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D8.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/PCK_CRC32_D8.vhd
@@ -17,7 +17,7 @@
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
package PCK_CRC32_D8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
@@ -25,20 +25,19 @@ package PCK_CRC32_D8 is
-- convention: the first serial bit is D[7]
function nextCRC32_D8
(Data: std_logic_vector(7 downto 0);
- crc: std_logic_vector(31 downto 0))
+ crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D8;
-
package body PCK_CRC32_D8 is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[7]
function nextCRC32_D8
- (Data: std_logic_vector(7 downto 0);
- crc: std_logic_vector(31 downto 0))
- return std_logic_vector is
+ (Data: std_logic_vector(7 downto 0);
+ crc: std_logic_vector(31 downto 0))
+ return std_logic_vector is
variable d: std_logic_vector(7 downto 0);
variable c: std_logic_vector(31 downto 0);
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc.vhd
index ecb99832d95303a0af431c139d882d1460d99dbf..5ba589bd779c3e2aba9ffeb80ba8d358497b13ac 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc.vhd
@@ -20,68 +20,64 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
-use work.AXI4_pkg.keep_to_empty;
-use work.crc_pkg.all;
-use work.misc_tools_pkg.all; -- bit_swap
+ use work.AXI4_pkg.keep_to_empty;
+ use work.crc_pkg.all;
+ use work.misc_tools_pkg.all; -- bit_swap
-use work.bit_width_config_pkg.all;
+ use work.bit_width_config_pkg.all;
entity append_crc is
-
- generic (
- g_AREA_SPEED_TRADEOFF_FACTOR : natural range 1 to 32 := 1; -- defines the parallelisation of the implementation. Larger = more area, but more speed.
- g_INIT_CRC : std_logic_vector := (31 downto 0 => '1'); -- Initial value of the CRC calc.
- g_BIT_REVERSE_IN : boolean := true;
- g_BIT_REVERSE_OUT : boolean := true;
- g_XOR_CRC_OUT : std_logic_vector := (31 downto 0 => '1');
- g_NAND_MASK : std_logic_vector := ""; -- Bits set to '1' will be cleared to '0' for the CRC calulation.
- g_OR_MASK : std_logic_vector := ""; -- Bits set to '1' will be set to '1' for the CRC calulation.
- g_INVALID_CYCLES_BETWEEN_PACKETS : natural := 0 -- guaranteed number of cycles between packets.
- );
-
- port (
- i_clk : in std_logic;
- i_clk_reset : in std_logic;
-
- i_stream : in AXI4_STREAMING_RDMA_t;
- o_stream_stop : out std_logic;
- o_stream : out AXI4_STREAMING_RDMA_t;
- i_stream_stop : in std_logic
- );
-
+ generic (
+ g_AREA_SPEED_TRADEOFF_FACTOR : natural range 1 to 32 := 1; -- defines the parallelisation of the implementation. Larger = more area, but more speed.
+ g_INIT_CRC : std_logic_vector := (31 downto 0 => '1'); -- Initial value of the CRC calc.
+ g_BIT_REVERSE_IN : boolean := true;
+ g_BIT_REVERSE_OUT : boolean := true;
+ g_XOR_CRC_OUT : std_logic_vector := (31 downto 0 => '1');
+ g_NAND_MASK : std_logic_vector := ""; -- Bits set to '1' will be cleared to '0' for the CRC calulation.
+ g_OR_MASK : std_logic_vector := ""; -- Bits set to '1' will be set to '1' for the CRC calulation.
+ g_INVALID_CYCLES_BETWEEN_PACKETS : natural := 0 -- guaranteed number of cycles between packets.
+ );
+ port (
+ i_clk : in std_logic;
+ i_clk_reset : in std_logic;
+
+ i_stream : in AXI4_STREAMING_RDMA_t;
+ o_stream_stop : out std_logic;
+ o_stream : out AXI4_STREAMING_RDMA_t;
+ i_stream_stop : in std_logic
+ );
end entity append_crc;
architecture rtl of append_crc is
-
- function f_padded_mask (
- constant mask : std_logic_vector;
- constant mask_len : natural
+ function f_padded_mask (
+ constant mask : std_logic_vector;
+ constant mask_len : natural
)
return std_logic_vector is
- constant top : integer := mask_len - 1;
- constant bot : integer := top - mask'length;
- variable padded_mask : std_logic_vector(top downto 0);
+ constant top : integer := mask_len - 1;
+ constant bot : integer := top - mask'length;
+ variable padded_mask : std_logic_vector(top downto 0);
begin
- padded_mask(top downto bot + 1) := mask;
- padded_mask(bot downto 0) := (others => '0');
- return padded_mask;
+ padded_mask(top downto bot + 1) := mask;
+ padded_mask(bot downto 0) := (others => '0');
+ return padded_mask;
end function f_padded_mask;
constant c_MASK_LEN : natural := round_up(maximum(g_OR_MASK'length, g_NAND_MASK'length), i_stream.data'length);
constant c_OR_MASK : std_logic_vector := f_padded_mask(g_OR_MASK, c_MASK_LEN);
constant c_NAND_MASK : std_logic_vector := f_padded_mask(g_NAND_MASK, c_MASK_LEN);
- constant c_MASK_CYCLES : natural := c_MASK_LEN/i_stream.data'length;
+ constant c_MASK_CYCLES : natural := c_MASK_LEN / i_stream.data'length;
function f_CRC_MASK_DELAY return natural is
begin
- if c_MASK_CYCLES > 0 then
- return 4;
- else
- return 3;
- end if;
+ if c_MASK_CYCLES > 0 then
+ return 4;
+ else
+ return 3;
+ end if;
end function f_CRC_MASK_DELAY;
signal masked_stream : AXI4_Streaming_RDMA_t;
@@ -92,152 +88,149 @@ architecture rtl of append_crc is
signal stream_delayed_slv : AXI4_Streaming_RDMA_t_slv;
signal crc_save : std_logic_vector(crc'range);
- signal crc_keep : std_logic_vector(crc'length/8-1 downto 0);
+ signal crc_keep : std_logic_vector(crc'length / 8 - 1 downto 0);
signal append_crc : std_logic;
signal error_save : std_logic;
-
begin
-
- G_MASK : if c_MASK_CYCLES > 0 generate
- signal mask_cycle_cnt : unsigned(ceil_log2(c_MASK_CYCLES) downto 0);
+ G_MASK : if c_MASK_CYCLES > 0 generate
+ signal mask_cycle_cnt : unsigned(ceil_log2(c_MASK_CYCLES) downto 0);
begin
- P_MASK_VARIANT_HEADER_FIELDS : process (i_clk)
- variable v_fb : unsigned(mask_cycle_cnt'range);
- variable v_dec : unsigned(mask_cycle_cnt'range);
- variable v_cyc : natural range 0 to c_MASK_CYCLES -1;
- variable v_validated_data : std_logic_vector(i_stream.data'range);
- begin
- if rising_edge(i_clk) then
- if (not mask_cycle_cnt(mask_cycle_cnt'high)) and i_stream.valid and not i_stream.last then
- v_dec := to_unsigned(1, v_dec'length);
- else
- v_dec := to_unsigned(0, v_dec'length);
- end if;
- if i_stream.last and i_stream.valid then
- v_fb := to_unsigned(c_MASK_CYCLES - 1, v_fb'length);
- else
- v_fb := mask_cycle_cnt;
- end if;
- mask_cycle_cnt <= v_fb - v_dec;
-
- for byte in i_stream.keep'range loop
- v_validated_data(byte*8+7 downto byte*8+0) := i_stream.data(byte*8+7 downto byte*8+0) and i_stream.keep(byte);
- end loop;
-
- masked_stream <= i_stream;
- if mask_cycle_cnt(mask_cycle_cnt'high) then
- -- Payload
- masked_stream.data <= v_validated_data;
- else
- v_cyc := to_integer(mask_cycle_cnt);
- -- Headers, some fields get masked off (replaced with '1's or '0's).
- masked_stream.data <= (v_validated_data
- or c_OR_MASK(v_cyc*i_stream.data'length + i_stream.data'high downto v_cyc*i_stream.data'length + 0))
- and (not c_NAND_MASK(v_cyc*i_stream.data'length + i_stream.data'high downto v_cyc*i_stream.data'length + 0));
- end if;
- if i_clk_reset then
- mask_cycle_cnt <= to_unsigned(c_MASK_CYCLES - 1, v_fb'length);
- end if;
- end if;
- end process;
- end generate G_MASK;
-
- G_NO_MASK : if c_MASK_CYCLES <= 0 generate
- masked_stream <= i_stream;
- end generate;
-
- E_CRC : entity work.crc_generator
- generic map (
- g_AREA_SPEED_TRADEOFF_FACTOR => g_AREA_SPEED_TRADEOFF_FACTOR,
- g_INIT_CRC => g_INIT_CRC,
- g_BIT_REVERSE_IN => g_BIT_REVERSE_IN,
- g_BIT_REVERSE_OUT => g_BIT_REVERSE_OUT,
- g_XOR_CRC_OUT => g_XOR_CRC_OUT,
- g_INVALID_CYCLES_BETWEEN_PACKETS => g_INVALID_CYCLES_BETWEEN_PACKETS
- )
- port map (
- i_clk => i_clk,
- i_clk_reset => i_clk_reset,
- i_stream => masked_stream,
- o_stop => o_stream_stop,
- o_crc => crc,
- o_crc_vld => crc_vld,
- i_stop2 => i_stream_stop
- );
-
- -- delay to match that of E_CRC and masking.
- E_DELAY_CRC : entity work.pipeline_delay_ram
- generic map (
- g_CYCLES_DELAY => f_CRC_MASK_DELAY,
- g_FORCE_USE_FLOPS => false,
- g_FLOPS_BEFORE_RAM => 1,
- g_FLOPS_AFTER_RAM => 1
- )
- port map (
- i_clk => i_clk,
- i_bus => to_slv(i_stream),
- o_bus => stream_delayed_slv
- );
+ P_MASK_VARIANT_HEADER_FIELDS : process (i_clk)
+ variable v_fb : unsigned(mask_cycle_cnt'range);
+ variable v_dec : unsigned(mask_cycle_cnt'range);
+ variable v_cyc : natural range 0 to c_MASK_CYCLES - 1;
+ variable v_validated_data : std_logic_vector(i_stream.data'range);
+ begin
+ if rising_edge(i_clk) then
+ if (not mask_cycle_cnt(mask_cycle_cnt'high)) and i_stream.valid and not i_stream.last then
+ v_dec := to_unsigned(1, v_dec'length);
+ else
+ v_dec := to_unsigned(0, v_dec'length);
+ end if;
+ if i_stream.last and i_stream.valid then
+ v_fb := to_unsigned(c_MASK_CYCLES - 1, v_fb'length);
+ else
+ v_fb := mask_cycle_cnt;
+ end if;
+ mask_cycle_cnt <= v_fb - v_dec;
- stream_delayed <= from_slv(stream_delayed_slv);
+ for byte in i_stream.keep'range loop
+ v_validated_data(byte * 8 + 7 downto byte * 8 + 0) := i_stream.data(byte * 8 + 7 downto byte * 8 + 0) and i_stream.keep(byte);
+ end loop;
- P_APPEND_CRC : process (i_clk)
- variable v_crc_rotate : std_logic_vector(ceil_log2(crc'length/8)-1 downto 0);
- variable v_rotated_crc : unsigned(crc'range);
- begin
- if rising_edge(i_clk) then
- if stream_delayed.valid then
- assert stream_delayed.last = crc_vld
- report "CRC output and end of packet are not aligned. Try adjusting the E_DELAY_CRC.g_CYCLES_DELAY generic."
- severity error;
- end if;
- o_stream <= stream_delayed;
-
- -- Pre-rotate the crc value so the first byte of the crc will end up in the byte position after the last data byte.
- v_crc_rotate := keep_to_empty(to_01(stream_delayed.keep))(1 downto 0);
- v_rotated_crc := rotate_left(unsigned(crc), 8*to_integer(unsigned(v_crc_rotate)));
-
- for slice in stream_delayed.data'length/crc'length-1 downto 0 loop
- -- Insert the CRC everywhere there are available bytes. Will select the correct one with valid and keep.
- -- Should only really be at the last cycle of a packet (also inserted into invalid cycles, including the one after the packet).
- for byte in crc'length/8-1 downto 0 loop
- if not stream_delayed.keep(slice*4+byte) then
- o_stream.data(slice*32+byte*8+7 downto slice*32+byte*8) <=
- std_logic_vector(v_rotated_crc(byte*8+7 downto byte*8));
- end if;
- end loop;
- end loop;
-
- append_crc <= '0';
- crc_keep <= (others => '1');
- crc_save <= std_logic_vector(v_rotated_crc);
- error_save <= stream_delayed.error;
- if stream_delayed.last and stream_delayed.valid then
- if stream_delayed.keep(crc'length/8-1) then
- -- Was not enough room in the current cycle.
- -- Some or all of the CRC must be inserted on the next cycle.
- o_stream.last <= '0';
- append_crc <= '1';
- crc_keep <= stream_delayed.keep(crc_keep'range);
- end if;
- end if;
- -- Wherever the crc ended up, rotate the keep to validate the first instance of the crc.
- o_stream.keep <= crc_keep & stream_delayed.keep(stream_delayed.keep'high downto crc_keep'length);
-
- if append_crc then
- assert stream_delayed.valid = '0'
- report "Wanted to insert the CRC into this cycle but it was not invalid." &
- " Expecting an invalid cycle between all incoming packets."
- severity error;
- o_stream.last <= '1';
- o_stream.valid <= '1';
- o_stream.data <= (others => '-');
- o_stream.data(o_stream.data'high downto o_stream.data'length - crc'length) <= crc_save;
- o_stream.keep <= crc_keep & (stream_delayed.keep'high downto crc_keep'length => '0');
- o_stream.error <= error_save;
- end if;
+ masked_stream <= i_stream;
+ if mask_cycle_cnt(mask_cycle_cnt'high) then
+ -- Payload
+ masked_stream.data <= v_validated_data;
+ else
+ v_cyc := to_integer(mask_cycle_cnt);
+ -- Headers, some fields get masked off (replaced with '1's or '0's).
+ masked_stream.data <= (v_validated_data
+ or c_OR_MASK(v_cyc*i_stream.data'length + i_stream.data'high downto v_cyc*i_stream.data'length + 0))
+ and (not c_NAND_MASK(v_cyc*i_stream.data'length + i_stream.data'high downto v_cyc*i_stream.data'length + 0));
end if;
+ if i_clk_reset then
+ mask_cycle_cnt <= to_unsigned(c_MASK_CYCLES - 1, v_fb'length);
+ end if;
+ end if;
end process;
+ end generate G_MASK;
+
+ G_NO_MASK : if c_MASK_CYCLES <= 0 generate
+ masked_stream <= i_stream;
+ end generate;
+
+ E_CRC : entity work.crc_generator
+ generic map (
+ g_AREA_SPEED_TRADEOFF_FACTOR => g_AREA_SPEED_TRADEOFF_FACTOR,
+ g_INIT_CRC => g_INIT_CRC,
+ g_BIT_REVERSE_IN => g_BIT_REVERSE_IN,
+ g_BIT_REVERSE_OUT => g_BIT_REVERSE_OUT,
+ g_XOR_CRC_OUT => g_XOR_CRC_OUT,
+ g_INVALID_CYCLES_BETWEEN_PACKETS => g_INVALID_CYCLES_BETWEEN_PACKETS
+ )
+ port map (
+ i_clk => i_clk,
+ i_clk_reset => i_clk_reset,
+ i_stream => masked_stream,
+ o_stop => o_stream_stop,
+ o_crc => crc,
+ o_crc_vld => crc_vld,
+ i_stop2 => i_stream_stop
+ );
+ -- delay to match that of E_CRC and masking.
+ E_DELAY_CRC : entity work.pipeline_delay_ram
+ generic map (
+ g_CYCLES_DELAY => f_CRC_MASK_DELAY,
+ g_FORCE_USE_FLOPS => false,
+ g_FLOPS_BEFORE_RAM => 1,
+ g_FLOPS_AFTER_RAM => 1
+ )
+ port map (
+ i_clk => i_clk,
+ i_bus => to_slv(i_stream),
+ o_bus => stream_delayed_slv
+ );
+
+ stream_delayed <= from_slv(stream_delayed_slv);
+
+ P_APPEND_CRC : process (i_clk)
+ variable v_crc_rotate : std_logic_vector(ceil_log2(crc'length / 8) - 1 downto 0);
+ variable v_rotated_crc : unsigned(crc'range);
+ begin
+ if rising_edge(i_clk) then
+ if stream_delayed.valid then
+ assert stream_delayed.last = crc_vld
+ report "CRC output and end of packet are not aligned. Try adjusting the E_DELAY_CRC.g_CYCLES_DELAY generic."
+ severity error;
+ end if;
+ o_stream <= stream_delayed;
+
+ -- Pre-rotate the crc value so the first byte of the crc will end up in the byte position after the last data byte.
+ v_crc_rotate := keep_to_empty(to_01(stream_delayed.keep))(1 downto 0);
+ v_rotated_crc := rotate_left(unsigned(crc), 8 * to_integer(unsigned(v_crc_rotate)));
+
+ for slice in stream_delayed.data'length / crc'length - 1 downto 0 loop
+ -- Insert the CRC everywhere there are available bytes. Will select the correct one with valid and keep.
+ -- Should only really be at the last cycle of a packet (also inserted into invalid cycles, including the one after the packet).
+ for byte in crc'length / 8 - 1 downto 0 loop
+ if not stream_delayed.keep(slice * 4 + byte) then
+ o_stream.data(slice * 32 + byte * 8 + 7 downto slice * 32 + byte * 8) <=
+ std_logic_vector(v_rotated_crc(byte*8+7 downto byte*8));
+ end if;
+ end loop;
+ end loop;
+
+ append_crc <= '0';
+ crc_keep <= (others => '1');
+ crc_save <= std_logic_vector(v_rotated_crc);
+ error_save <= stream_delayed.error;
+ if stream_delayed.last and stream_delayed.valid then
+ if stream_delayed.keep(crc'length / 8 - 1) then
+ -- Was not enough room in the current cycle.
+ -- Some or all of the CRC must be inserted on the next cycle.
+ o_stream.last <= '0';
+ append_crc <= '1';
+ crc_keep <= stream_delayed.keep(crc_keep'range);
+ end if;
+ end if;
+ -- Wherever the crc ended up, rotate the keep to validate the first instance of the crc.
+ o_stream.keep <= crc_keep & stream_delayed.keep(stream_delayed.keep'high downto crc_keep'length);
+
+ if append_crc then
+ assert stream_delayed.valid = '0'
+ report "Wanted to insert the CRC into this cycle but it was not invalid." &
+ " Expecting an invalid cycle between all incoming packets."
+ severity error;
+ o_stream.last <= '1';
+ o_stream.valid <= '1';
+ o_stream.data <= (others => '-');
+ o_stream.data(o_stream.data'high downto o_stream.data'length - crc'length) <= crc_save;
+ o_stream.keep <= crc_keep & (stream_delayed.keep'high downto crc_keep'length => '0');
+ o_stream.error <= error_save;
+ end if;
+ end if;
+ end process;
end architecture rtl;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_dp_wrapper.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_dp_wrapper.vhd
index 532954c55cba07ed4b8e28b8566f3518ee8988a7..e14cd647a96794e24170a5b783b61b071ab79076 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_dp_wrapper.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_dp_wrapper.vhd
@@ -22,21 +22,21 @@
-- the AXI4 interfaces using axi4_stream_dp_bridge.
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+ use IEEE.std_logic_1164.all;
library axi4_lib, dp_lib;
-use axi4_lib.axi4_stream_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use axi4_lib.axi4_stream_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-use work.crc_pkg.all;
-use work.bit_width_config_pkg.all;
-use work.rdma_pkg.all;
+ use work.crc_pkg.all;
+ use work.bit_width_config_pkg.all;
+ use work.rdma_pkg.all;
entity append_crc_dp_wrapper is
- port (
+ port (
dp_clk : in std_logic;
dp_rst : in std_logic;
-
+
out_dp_sosi : out t_dp_sosi := c_dp_sosi_rst;
out_dp_siso : in t_dp_siso := c_dp_siso_rdy;
@@ -46,20 +46,17 @@ entity append_crc_dp_wrapper is
end append_crc_dp_wrapper;
architecture str of append_crc_dp_wrapper is
-
signal i_stream_stop : std_logic;
signal o_stream_stop : std_logic;
-
+
signal o_stream : AXI4_Streaming_RDMA_t := AXI4_Streaming_RDMA_t_ZERO;
signal i_stream : AXI4_Streaming_RDMA_t := AXI4_Streaming_RDMA_t_ZERO;
-
+
signal o_stream_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
signal o_stream_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
signal i_stream_axi4_sosi : t_axi4_sosi := c_axi4_sosi_rst;
signal i_stream_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
-
-
-begin
+begin
-- Wire Records to IN/OUT ports.
-- o_stream
i_stream_stop <= not o_stream_axi4_siso.tready;
@@ -68,66 +65,65 @@ begin
o_stream_axi4_sosi.tlast <= o_stream.last;
o_stream_axi4_sosi.tdata <= o_stream.data;
o_stream_axi4_sosi.tkeep <= o_stream.keep;
-
+
-- i_stream
i_stream_axi4_siso.tready <= not o_stream_stop;
- i_stream.valid <= i_stream_axi4_sosi.tvalid;
+ i_stream.valid <= i_stream_axi4_sosi.tvalid;
i_stream.last <= i_stream_axi4_sosi.tlast;
i_stream.data <= i_stream_axi4_sosi.tdata;
i_stream.keep <= i_stream_axi4_sosi.tkeep;
-
+
u_dp_to_axi : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_use_empty => true,
- g_axi4_rl => 1,
- g_dp_rl => 1
- )
- port map (
- in_clk => dp_clk,
- in_rst => dp_rst,
-
- axi4_out_sosi => i_stream_axi4_sosi,
- axi4_out_siso => i_stream_axi4_siso,
-
- dp_in_sosi => in_dp_sosi,
- dp_in_siso => in_dp_siso
- );
+ generic map (
+ g_use_empty => true,
+ g_axi4_rl => 1,
+ g_dp_rl => 1
+ )
+ port map (
+ in_clk => dp_clk,
+ in_rst => dp_rst,
+
+ axi4_out_sosi => i_stream_axi4_sosi,
+ axi4_out_siso => i_stream_axi4_siso,
+
+ dp_in_sosi => in_dp_sosi,
+ dp_in_siso => in_dp_siso
+ );
u_axi4_to_dp : entity axi4_lib.axi4_stream_dp_bridge
- generic map (
- g_use_empty => true,
- g_axi4_rl => 1,
- g_dp_rl => 1
- )
- port map (
- in_clk => dp_clk,
- in_rst => dp_rst,
-
- axi4_in_sosi => o_stream_axi4_sosi,
- axi4_in_siso => o_stream_axi4_siso,
-
- dp_out_sosi => out_dp_sosi,
- dp_out_siso => out_dp_siso
- );
-
-u_append_crc : entity work.append_crc
- generic map(
- g_AREA_SPEED_TRADEOFF_FACTOR => 4,
- g_INIT_CRC => f_ICRC_INIT,
- g_BIT_REVERSE_IN => true,
- g_BIT_REVERSE_OUT => true,
- g_XOR_CRC_OUT => (31 downto 0 => '1'),
- g_OR_MASK => to_slv(c_RoCEv2_HEADER_INVARIANT_MASK),
- g_INVALID_CYCLES_BETWEEN_PACKETS => 1
- )
- port map(
- i_clk => dp_clk,
- i_clk_reset => dp_rst,
- i_stream => i_stream,
- o_stream_stop => o_stream_stop,
- o_stream => o_stream,
- i_stream_stop => i_stream_stop
- );
-
+ generic map (
+ g_use_empty => true,
+ g_axi4_rl => 1,
+ g_dp_rl => 1
+ )
+ port map (
+ in_clk => dp_clk,
+ in_rst => dp_rst,
+
+ axi4_in_sosi => o_stream_axi4_sosi,
+ axi4_in_siso => o_stream_axi4_siso,
+
+ dp_out_sosi => out_dp_sosi,
+ dp_out_siso => out_dp_siso
+ );
+
+ u_append_crc : entity work.append_crc
+ generic map(
+ g_AREA_SPEED_TRADEOFF_FACTOR => 4,
+ g_INIT_CRC => f_ICRC_INIT,
+ g_BIT_REVERSE_IN => true,
+ g_BIT_REVERSE_OUT => true,
+ g_XOR_CRC_OUT => (31 downto 0 => '1'),
+ g_OR_MASK => to_slv(c_RoCEv2_HEADER_INVARIANT_MASK),
+ g_INVALID_CYCLES_BETWEEN_PACKETS => 1
+ )
+ port map(
+ i_clk => dp_clk,
+ i_clk_reset => dp_rst,
+ i_stream => i_stream,
+ o_stream_stop => o_stream_stop,
+ o_stream => o_stream,
+ i_stream_stop => i_stream_stop
+ );
end str;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_wrapper.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_wrapper.vhd
index f53339b72e45a5f622b74b2b113bd97c259de490..bef0ed61fc7cb6055feb95805518473fb0d5933b 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_wrapper.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_wrapper.vhd
@@ -1,26 +1,25 @@
----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
+-- Company:
+-- Engineer:
+--
-- Create Date: 06/27/2023 10:50:24 AM
--- Design Name:
+-- Design Name:
-- Module Name: append_crc_wrapper - Behavioral
--- Project Name:
--- Target Devices:
--- Tool Versions:
--- Description:
---
--- Dependencies:
---
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---
+--
----------------------------------------------------------------------------------
-
library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+ use IEEE.std_logic_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
@@ -30,46 +29,44 @@ use IEEE.STD_LOGIC_1164.ALL;
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-use work.crc_pkg.all;
-use work.bit_width_config_pkg.all;
-use work.rdma_pkg.all;
+ use work.crc_pkg.all;
+ use work.bit_width_config_pkg.all;
+ use work.rdma_pkg.all;
entity append_crc_wrapper is
- Port (
- i_clk : in std_logic;
- i_clk_reset : in std_logic;
-
- -- o_stream
- -- Source In and Sink Out
- o_stream_tready : in std_logic;
-
- -- Source Out and Sink In
- o_stream_tvalid : out std_logic;
- o_stream_tdata : out std_logic_vector(512 - 1 downto 0);
- o_stream_tkeep : out std_logic_vector(512 / 8 - 1 downto 0);
- o_stream_tlast : out std_logic;
-
- -- i_stream
- -- Source In and Sink Out
- i_stream_tready : out std_logic;
-
- -- Source Out and Sink In
- i_stream_tvalid : in std_logic;
- i_stream_tdata : in std_logic_vector(512 - 1 downto 0);
- i_stream_tkeep : in std_logic_vector(512 / 8 - 1 downto 0);
- i_stream_tlast : in std_logic
- );
+ port (
+ i_clk : in std_logic;
+ i_clk_reset : in std_logic;
+
+ -- o_stream
+ -- Source In and Sink Out
+ o_stream_tready : in std_logic;
+
+ -- Source Out and Sink In
+ o_stream_tvalid : out std_logic;
+ o_stream_tdata : out std_logic_vector(512 - 1 downto 0);
+ o_stream_tkeep : out std_logic_vector(512 / 8 - 1 downto 0);
+ o_stream_tlast : out std_logic;
+
+ -- i_stream
+ -- Source In and Sink Out
+ i_stream_tready : out std_logic;
+
+ -- Source Out and Sink In
+ i_stream_tvalid : in std_logic;
+ i_stream_tdata : in std_logic_vector(512 - 1 downto 0);
+ i_stream_tkeep : in std_logic_vector(512 / 8 - 1 downto 0);
+ i_stream_tlast : in std_logic
+ );
end append_crc_wrapper;
architecture Behavioral of append_crc_wrapper is
-
signal i_stream_stop : std_logic;
signal o_stream_stop : std_logic;
-
+
signal o_stream : AXI4_Streaming_RDMA_t;
signal i_stream : AXI4_Streaming_RDMA_t;
-
-begin
+begin
-- Wire Records to IN/OUT ports.
-- o_stream
i_stream_stop <= not o_stream_tready;
@@ -78,32 +75,31 @@ begin
o_stream_tlast <= o_stream.last;
o_stream_tdata <= o_stream.data;
o_stream_tkeep <= o_stream.keep;
-
+
-- i_stream
i_stream_tready <= not o_stream_stop;
- i_stream.valid <= i_stream_tvalid;
+ i_stream.valid <= i_stream_tvalid;
i_stream.last <= i_stream_tlast;
i_stream.data <= i_stream_tdata;
i_stream.keep <= i_stream_tkeep;
-
-u_append_crc : entity work.append_crc
- generic map(
- g_AREA_SPEED_TRADEOFF_FACTOR => 32,
- g_INIT_CRC => f_ICRC_INIT,
- g_BIT_REVERSE_IN => true,
- g_BIT_REVERSE_OUT => true,
- g_XOR_CRC_OUT => (31 downto 0 => '1'),
- g_OR_MASK => to_slv(c_RoCEv2_HEADER_INVARIANT_MASK),
- g_INVALID_CYCLES_BETWEEN_PACKETS => 1
- )
- port map(
- i_clk => i_clk,
- i_clk_reset => i_clk_reset,
- i_stream => i_stream,
- o_stream_stop => o_stream_stop,
- o_stream => o_stream,
- i_stream_stop => i_stream_stop
- );
-
+
+ u_append_crc : entity work.append_crc
+ generic map(
+ g_AREA_SPEED_TRADEOFF_FACTOR => 32,
+ g_INIT_CRC => f_ICRC_INIT,
+ g_BIT_REVERSE_IN => true,
+ g_BIT_REVERSE_OUT => true,
+ g_XOR_CRC_OUT => (31 downto 0 => '1'),
+ g_OR_MASK => to_slv(c_RoCEv2_HEADER_INVARIANT_MASK),
+ g_INVALID_CYCLES_BETWEEN_PACKETS => 1
+ )
+ port map(
+ i_clk => i_clk,
+ i_clk_reset => i_clk_reset,
+ i_stream => i_stream,
+ o_stream_stop => o_stream_stop,
+ o_stream => o_stream,
+ i_stream_stop => i_stream_stop
+ );
end Behavioral;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/bit_width_config_pkg.512b.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/bit_width_config_pkg.512b.vhd
index eb3356e056510b2033b9b84fe80becfae5cae408..473dd68b34385eaa9d289fb05510376d46d5dfeb 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/bit_width_config_pkg.512b.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/bit_width_config_pkg.512b.vhd
@@ -19,42 +19,40 @@
-- on revision history.
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
-use work.AXI4_pkg.all;
+ use work.AXI4_pkg.all;
package bit_width_config_pkg is
-
- subtype AXI4_streaming_RDMA_t is AXI4_Streaming_512_t;
- subtype AXI4_streaming_RDMA_t_a is AXI4_Streaming_512_t_a;
- subtype AXI4_streaming_RDMA_t_slv is AXI4_Streaming_512_t_slv;
-
- constant AXI4_Streaming_RDMA_t_slv_width : natural := AXI4_Streaming_512_t_slv_width;
- constant AXI4_Streaming_RDMA_t_ZERO : AXI4_streaming_RDMA_t := AXI4_Streaming_512_t_ZERO;
- constant AXI4_Streaming_RDMA_t_DONT_CARE : AXI4_streaming_RDMA_t := AXI4_Streaming_512_t_DONT_CARE;
-
- function to_slv (rec : AXI4_Streaming_RDMA_t) return AXI4_Streaming_RDMA_t_slv;
- function from_slv (slv : AXI4_Streaming_RDMA_t_slv) return AXI4_Streaming_RDMA_t;
- function from_slv (slv : std_logic_vector; vld : std_logic) return AXI4_Streaming_RDMA_t;
-
+ subtype AXI4_streaming_RDMA_t is AXI4_Streaming_512_t;
+ subtype AXI4_streaming_RDMA_t_a is AXI4_Streaming_512_t_a;
+ subtype AXI4_streaming_RDMA_t_slv is AXI4_Streaming_512_t_slv;
+
+ constant AXI4_Streaming_RDMA_t_slv_width : natural := AXI4_Streaming_512_t_slv_width;
+ constant AXI4_Streaming_RDMA_t_ZERO : AXI4_streaming_RDMA_t := AXI4_Streaming_512_t_ZERO;
+ constant AXI4_Streaming_RDMA_t_DONT_CARE : AXI4_streaming_RDMA_t := AXI4_Streaming_512_t_DONT_CARE;
+
+ function to_slv (rec : AXI4_Streaming_RDMA_t) return AXI4_Streaming_RDMA_t_slv;
+ function from_slv (slv : AXI4_Streaming_RDMA_t_slv) return AXI4_Streaming_RDMA_t;
+ function from_slv (slv : std_logic_vector; vld : std_logic) return AXI4_Streaming_RDMA_t;
end package;
package body bit_width_config_pkg is
- function to_slv (rec : AXI4_Streaming_RDMA_t) return AXI4_Streaming_RDMA_t_slv is
- begin
- return work.AXI4_pkg.to_slv(rec);
- end function;
-
- function from_slv (slv : AXI4_Streaming_RDMA_t_slv) return AXI4_Streaming_RDMA_t is
- begin
- return work.AXI4_pkg.from_slv(slv);
- end function;
-
- function from_slv (slv : std_logic_vector; vld : std_logic) return AXI4_Streaming_RDMA_t is
- begin
- return work.AXI4_pkg.from_slv(slv, vld);
- end function;
-
+ function to_slv (rec : AXI4_Streaming_RDMA_t) return AXI4_Streaming_RDMA_t_slv is
+ begin
+ return work.AXI4_pkg.to_slv(rec);
+ end function;
+
+ function from_slv (slv : AXI4_Streaming_RDMA_t_slv) return AXI4_Streaming_RDMA_t is
+ begin
+ return work.AXI4_pkg.from_slv(slv);
+ end function;
+
+ function from_slv (slv : std_logic_vector; vld : std_logic) return AXI4_Streaming_RDMA_t is
+ begin
+ return work.AXI4_pkg.from_slv(slv, vld);
+ end function;
+
end package body;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/common_types_pkg.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/common_types_pkg.vhd
index 7a2914fd81667017a597d15e7b38cc47f6cc1ffc..53fe529d597618fb5288eea70d68899f2d6a6a06 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/common_types_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/common_types_pkg.vhd
@@ -1,126 +1,124 @@
--------------------------------------------------------------------------------
--- Title : Common Type Declarations
--- Project :
--------------------------------------------------------------------------------
--- File : common_types_pkg.vhd
--- Author : William Kamp <william.kamp@aut.ac.nz>
--- Company : High Performance Computing Research Lab, Auckland University of Technology
--- Created : 2015-12-07
--- Last update: 2018-01-01
--- Platform :
--- Standard : VHDL'93/02
--------------------------------------------------------------------------------
--- Description:
--------------------------------------------------------------------------------
--- Copyright (c) 2015 High Performance Computing Research Lab, Auckland University of Technology
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2015-12-07 1.0 wkamp Created
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.fixed_pkg.all;
-
-package common_types_pkg is
-
- type t_natural_a is array (integer range<>) of natural;
- type t_integer_a is array (integer range<>) of integer;
- type t_boolean_a is array (integer range<>) of boolean;
-
- type slv_a is array (natural range <>) of std_logic_vector;
- -- Standard powers of two
- subtype slv_1_a is slv_a (open)(0 downto 0);
- subtype slv_2_a is slv_a (open)(1 downto 0);
- subtype slv_4_a is slv_a (open)(3 downto 0);
- subtype slv_8_a is slv_a (open)(7 downto 0);
- subtype slv_16_a is slv_a (open)(15 downto 0);
- subtype slv_32_a is slv_a (open)(31 downto 0);
- subtype slv_64_a is slv_a (open)(63 downto 0);
- subtype slv_128_a is slv_a (open)(127 downto 0);
- subtype slv_256_a is slv_a (open)(255 downto 0);
-
- type unsigned_a is array (natural range <>) of unsigned;
- -- Unsigned powers of two vectors
- subtype unsigned_1_a is unsigned_a (open)(0 downto 0);
- subtype unsigned_2_a is unsigned_a (open)(1 downto 0);
- subtype unsigned_4_a is unsigned_a (open)(3 downto 0);
- subtype unsigned_8_a is unsigned_a (open)(7 downto 0);
- subtype unsigned_16_a is unsigned_a (open)(15 downto 0);
- subtype unsigned_32_a is unsigned_a (open)(31 downto 0);
- subtype unsigned_64_a is unsigned_a (open)(63 downto 0);
- subtype unsigned_128_a is unsigned_a (open)(127 downto 0);
- subtype unsigned_256_a is unsigned_a (open)(255 downto 0);
-
- type signed_a is array (natural range <>) of signed;
- -- signed powers of two vectors
- subtype signed_1_a is signed_a (open)(0 downto 0);
- subtype signed_2_a is signed_a (open)(1 downto 0);
- subtype signed_4_a is signed_a (open)(3 downto 0);
- subtype signed_8_a is signed_a (open)(7 downto 0);
- subtype signed_16_a is signed_a (open)(15 downto 0);
- subtype signed_32_a is signed_a (open)(31 downto 0);
- subtype signed_64_a is signed_a (open)(63 downto 0);
- subtype signed_128_a is signed_a (open)(127 downto 0);
- subtype signed_256_a is signed_a (open)(255 downto 0);
-
- type sfixed_a is array (natural range <>) of sfixed;
- type ufixed_a is array (natural range <>) of ufixed;
-
- -- Stratix5 transceiver interfaces.
- subtype slv_80_a is slv_a (open)(79 downto 0);
- subtype slv_92_a is slv_a (open)(91 downto 0);
- subtype slv_140_a is slv_a (open)(139 downto 0);
-
- function to_slv(slv_array : slv_a; big_endian : boolean := true) return std_logic_vector;
- function from_slv(slv : std_logic_vector; width : natural := 64; big_endian : boolean := true) return slv_a;
-
-end package common_types_pkg;
-
-package body common_types_pkg is
-
- function to_slv(
- slv_array : slv_a;
- big_endian : boolean := true)
- return std_logic_vector is
- variable slv : std_logic_vector(slv_array'length * slv_array(slv_array'left)'length - 1 downto 0);
- variable hi : integer;
- constant stride : natural := slv_array(slv_array'left)'length;
- begin
- hi := slv'high;
- for idx in slv_array'range loop
- if big_endian then
- slv(hi downto hi + 1 - stride) := slv_array(idx);
- hi := hi - stride;
- else
- slv(idx * stride + stride - 1 downto idx * stride) := slv_array(idx);
- end if;
- end loop;
- return slv;
- end function to_slv;
-
- function from_slv(
- slv : std_logic_vector;
- width : natural := 64;
- big_endian : boolean := true)
- return slv_a is
- variable slvz : std_logic_vector(slv'length - 1 downto 0);
- variable slv_array : slv_a(0 to slv'length / width - 1)(width - 1 downto 0);
- variable hi : integer;
- begin
- slvz := slv;
- hi := slvz'high;
- for idx in slv_array'range loop
- if big_endian then
- slv_array(idx) := slvz(hi downto hi + 1 - width);
- hi := hi - width;
- else
- slv_array(idx) := slvz(idx*width + width - 1 downto idx*width);
- end if;
- end loop;
- return slv_array;
- end function from_slv;
-
-end package body common_types_pkg;
\ No newline at end of file
+-------------------------------------------------------------------------------
+-- Title : Common Type Declarations
+-- Project :
+-------------------------------------------------------------------------------
+-- File : common_types_pkg.vhd
+-- Author : William Kamp <william.kamp@aut.ac.nz>
+-- Company : High Performance Computing Research Lab, Auckland University of Technology
+-- Created : 2015-12-07
+-- Last update: 2018-01-01
+-- Platform :
+-- Standard : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2015 High Performance Computing Research Lab, Auckland University of Technology
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2015-12-07 1.0 wkamp Created
+-------------------------------------------------------------------------------
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use ieee.fixed_pkg.all;
+
+package common_types_pkg is
+ type t_natural_a is array (integer range <>) of natural;
+ type t_integer_a is array (integer range <>) of integer;
+ type t_boolean_a is array (integer range <>) of boolean;
+
+ type slv_a is array (natural range <>) of std_logic_vector;
+ -- Standard powers of two
+ subtype slv_1_a is slv_a (open)(0 downto 0);
+ subtype slv_2_a is slv_a (open)(1 downto 0);
+ subtype slv_4_a is slv_a (open)(3 downto 0);
+ subtype slv_8_a is slv_a (open)(7 downto 0);
+ subtype slv_16_a is slv_a (open)(15 downto 0);
+ subtype slv_32_a is slv_a (open)(31 downto 0);
+ subtype slv_64_a is slv_a (open)(63 downto 0);
+ subtype slv_128_a is slv_a (open)(127 downto 0);
+ subtype slv_256_a is slv_a (open)(255 downto 0);
+
+ type unsigned_a is array (natural range <>) of unsigned;
+ -- Unsigned powers of two vectors
+ subtype unsigned_1_a is unsigned_a (open)(0 downto 0);
+ subtype unsigned_2_a is unsigned_a (open)(1 downto 0);
+ subtype unsigned_4_a is unsigned_a (open)(3 downto 0);
+ subtype unsigned_8_a is unsigned_a (open)(7 downto 0);
+ subtype unsigned_16_a is unsigned_a (open)(15 downto 0);
+ subtype unsigned_32_a is unsigned_a (open)(31 downto 0);
+ subtype unsigned_64_a is unsigned_a (open)(63 downto 0);
+ subtype unsigned_128_a is unsigned_a (open)(127 downto 0);
+ subtype unsigned_256_a is unsigned_a (open)(255 downto 0);
+
+ type signed_a is array (natural range <>) of signed;
+ -- signed powers of two vectors
+ subtype signed_1_a is signed_a (open)(0 downto 0);
+ subtype signed_2_a is signed_a (open)(1 downto 0);
+ subtype signed_4_a is signed_a (open)(3 downto 0);
+ subtype signed_8_a is signed_a (open)(7 downto 0);
+ subtype signed_16_a is signed_a (open)(15 downto 0);
+ subtype signed_32_a is signed_a (open)(31 downto 0);
+ subtype signed_64_a is signed_a (open)(63 downto 0);
+ subtype signed_128_a is signed_a (open)(127 downto 0);
+ subtype signed_256_a is signed_a (open)(255 downto 0);
+
+ type sfixed_a is array (natural range <>) of sfixed;
+ type ufixed_a is array (natural range <>) of ufixed;
+
+ -- Stratix5 transceiver interfaces.
+ subtype slv_80_a is slv_a (open)(79 downto 0);
+ subtype slv_92_a is slv_a (open)(91 downto 0);
+ subtype slv_140_a is slv_a (open)(139 downto 0);
+
+ function to_slv(slv_array : slv_a; big_endian : boolean := true) return std_logic_vector;
+ function from_slv(slv : std_logic_vector; width : natural := 64; big_endian : boolean := true) return slv_a;
+end package common_types_pkg;
+
+package body common_types_pkg is
+
+ function to_slv(
+ slv_array : slv_a;
+ big_endian : boolean := true)
+ return std_logic_vector is
+ variable slv : std_logic_vector(slv_array'length * slv_array(slv_array'left)'length - 1 downto 0);
+ variable hi : integer;
+ constant stride : natural := slv_array(slv_array'left)'length;
+ begin
+ hi := slv'high;
+ for idx in slv_array'range loop
+ if big_endian then
+ slv(hi downto hi + 1 - stride) := slv_array(idx);
+ hi := hi - stride;
+ else
+ slv(idx * stride + stride - 1 downto idx * stride) := slv_array(idx);
+ end if;
+ end loop;
+ return slv;
+ end function to_slv;
+
+ function from_slv(
+ slv : std_logic_vector;
+ width : natural := 64;
+ big_endian : boolean := true)
+ return slv_a is
+ variable slvz : std_logic_vector(slv'length - 1 downto 0);
+ variable slv_array : slv_a(0 to slv'length / width - 1)(width - 1 downto 0);
+ variable hi : integer;
+ begin
+ slvz := slv;
+ hi := slvz'high;
+ for idx in slv_array'range loop
+ if big_endian then
+ slv_array(idx) := slvz(hi downto hi + 1 - width);
+ hi := hi - width;
+ else
+ slv_array(idx) := slvz(idx * width + width - 1 downto idx * width);
+ end if;
+ end loop;
+ return slv_array;
+ end function from_slv;
+
+end package body common_types_pkg;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_generator.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_generator.vhd
index 24d295a67fb03e6da7b5e96d6990fdcb45e958dc..98294b812ea3dd121d00ec4217b53344e82ddc0c 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_generator.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_generator.vhd
@@ -71,185 +71,180 @@
-------------------------------------------------------------------------------
library ieee;
- use ieee.std_logic_1164.all;
- use work.crc_pkg.all;
- use work.PCK_CRC32_D1_reversed.all; -- prevCRC32_D1
- use work.misc_tools_pkg.all; -- bit_swap, byte_swap
+ use ieee.std_logic_1164.all;
+ use work.crc_pkg.all;
+ use work.PCK_CRC32_D1_reversed.all; -- prevCRC32_D1
+ use work.misc_tools_pkg.all; -- bit_swap, byte_swap
-use work.bit_width_config_pkg.all;
+ use work.bit_width_config_pkg.all;
-- vsg_off entity_008 entity_012
entity crc_generator is
- generic (
- G_AREA_SPEED_TRADEOFF_FACTOR : natural range 1 to 32 := 1;
- -- defines the parallelisation of the implementation. Larger = more area, but more speed.
- G_INIT_CRC : std_logic_vector := (31 downto 0 => '1');
- -- Initial value of the CRC calc.
- G_BIT_REVERSE_IN : boolean := true;
- -- Reverse the bit order within each input byte before applying CRC.
- G_BIT_REVERSE_OUT : boolean := true;
- -- Reverse the bit order within each CRC output byte,
- G_XOR_CRC_OUT : std_logic_vector := (31 downto 0 => '1');
- -- XOR the CRC output with this value.
- G_INVALID_CYCLES_BETWEEN_PACKETS : natural := 0
- -- guaranteed number of cycles between packets.
- );
- port (
- i_clk : in std_logic;
- i_clk_reset : in std_logic;
-
- i_stream : in AXI4_STREAMING_RDMA_t;
- o_stop : out std_logic;
- o_crc : out std_logic_vector;
- o_crc_vld : out std_logic;
- i_stop2 : in std_logic
- );
+ generic (
+ G_AREA_SPEED_TRADEOFF_FACTOR : natural range 1 to 32 := 1;
+ -- defines the parallelisation of the implementation. Larger = more area, but more speed.
+ G_INIT_CRC : std_logic_vector := (31 downto 0 => '1');
+ -- Initial value of the CRC calc.
+ G_BIT_REVERSE_IN : boolean := true;
+ -- Reverse the bit order within each input byte before applying CRC.
+ G_BIT_REVERSE_OUT : boolean := true;
+ -- Reverse the bit order within each CRC output byte,
+ G_XOR_CRC_OUT : std_logic_vector := (31 downto 0 => '1');
+ -- XOR the CRC output with this value.
+ G_INVALID_CYCLES_BETWEEN_PACKETS : natural := 0
+ -- guaranteed number of cycles between packets.
+ );
+ port (
+ i_clk : in std_logic;
+ i_clk_reset : in std_logic;
+
+ i_stream : in AXI4_STREAMING_RDMA_t;
+ o_stop : out std_logic;
+ o_crc : out std_logic_vector;
+ o_crc_vld : out std_logic;
+ i_stop2 : in std_logic
+ );
end entity crc_generator;
architecture rtl of crc_generator is
+ constant C_TOTAL_WIDTH : natural := i_stream.data'length;
+ constant C_CRC_WIDTH : natural := o_crc'length;
- constant C_TOTAL_WIDTH : natural := i_stream.data'length;
- constant C_CRC_WIDTH : natural := o_crc'length;
-
- function f_slice_width (
- constant slice_idx : natural)
+ function f_slice_width (
+ constant slice_idx : natural)
return natural is
begin
- -- calculates irregular divisions of the bus width, e.g. by 3.
- return (c_TOTAL_WIDTH + slice_idx) / g_AREA_SPEED_TRADEOFF_FACTOR;
+ -- calculates irregular divisions of the bus width, e.g. by 3.
+ return (c_TOTAL_WIDTH + slice_idx) / g_AREA_SPEED_TRADEOFF_FACTOR;
end function f_slice_width;
function f_slice_lo (
constant slice_idx : natural)
- return natural is
+ return natural is
variable v_lo : natural;
- begin -- function f_slice_lo
+ begin -- function f_slice_lo
v_lo := 0;
for i in 1 to slice_idx loop
- v_lo := v_lo + f_slice_width(i);
+ v_lo := v_lo + f_slice_width(i);
end loop;
return v_lo;
- end function f_slice_lo;
+ end function f_slice_lo;
- type t_slv_crc_a is array (natural range <>) of std_logic_vector(o_crc'range);
- signal part_crc : t_slv_crc_a(g_AREA_SPEED_TRADEOFF_FACTOR - 1 downto 0);
- signal part_crc_vld : std_logic_vector(g_AREA_SPEED_TRADEOFF_FACTOR - 1 downto 0);
- signal part_keep : std_logic_vector(i_stream.keep'range);
- signal err_fwd : std_logic;
-
- signal crc_combined : std_logic_vector(o_crc'range);
- signal crc_combined_vld : std_logic;
- signal comb_keep : std_logic_vector(i_stream.keep'range);
+ type t_slv_crc_a is array (natural range <>) of std_logic_vector(o_crc'range);
+ signal part_crc : t_slv_crc_a(g_AREA_SPEED_TRADEOFF_FACTOR - 1 downto 0);
+ signal part_crc_vld : std_logic_vector(g_AREA_SPEED_TRADEOFF_FACTOR - 1 downto 0);
+ signal part_keep : std_logic_vector(i_stream.keep'range);
+ signal err_fwd : std_logic;
+ signal crc_combined : std_logic_vector(o_crc'range);
+ signal crc_combined_vld : std_logic;
+ signal comb_keep : std_logic_vector(i_stream.keep'range);
begin -- architecture rtl
-
- o_stop <= i_stop2;
-
- G_SLICE : for idx in 0 to g_AREA_SPEED_TRADEOFF_FACTOR - 1 generate
- -- calculate the range of a slice of the data. This will cope with irregular divisors.
- constant C_SLICE_WIDTH : natural := f_slice_width(idx);
- constant C_SLICE_LO : natural := f_slice_lo(idx);
- constant C_SLICE_HI : natural := C_SLICE_LO + C_SLICE_WIDTH - 1;
- signal slice_crc : std_logic_vector(o_crc'range);
- signal sop : std_logic;
+ o_stop <= i_stop2;
+
+ G_SLICE : for idx in 0 to g_AREA_SPEED_TRADEOFF_FACTOR - 1 generate
+ -- calculate the range of a slice of the data. This will cope with irregular divisors.
+ constant C_SLICE_WIDTH : natural := f_slice_width(idx);
+ constant C_SLICE_LO : natural := f_slice_lo(idx);
+ constant C_SLICE_HI : natural := C_SLICE_LO + C_SLICE_WIDTH - 1;
+ signal slice_crc : std_logic_vector(o_crc'range);
+ signal sop : std_logic;
begin
- P_CRC : process (i_clk) is
- variable v_data : std_logic_vector(i_stream.data'range);
- variable v_crc_fb : std_logic_vector(o_crc'range);
- begin -- process
- if rising_edge(i_clk) then
- v_data := (others => '0');
- for byte in C_SLICE_HI / 8 downto C_SLICE_LO / 8 loop
- -- extract a slice of the data bus.
- -- validate each byte using keep, set to zero if invalid.
- v_data(byte * 8 + 7 downto byte * 8) := i_stream.data(byte * 8 + 7 downto byte * 8)
- and i_stream.keep(byte);
- end loop;
- if g_BIT_REVERSE_IN then
- v_data := byte_swap(bit_swap(v_data));
- end if;
- if i_stream.valid then
- sop <= i_stream.last;
- if sop then
- v_crc_fb := g_INIT_CRC when C_SLICE_HI = i_stream.data'high
- else (others => '0');
- else
- v_crc_fb := slice_crc;
- end if;
- -- compute the slice_crc for this slice.
- slice_crc <= f_next_crc(v_data, v_crc_fb);
- end if;
- part_crc_vld(idx) <= i_stream.valid and i_stream.last;
- if i_clk_reset then
- sop <= '1';
- end if;
- end if;
- end process P_CRC;
-
- part_crc(idx) <= slice_crc;
-
- end generate G_SLICE;
-
- P_PIPE_CONTROL : process (i_clk) is
+ P_CRC : process (i_clk) is
+ variable v_data : std_logic_vector(i_stream.data'range);
+ variable v_crc_fb : std_logic_vector(o_crc'range);
begin -- process
- if rising_edge(i_clk) then
- err_fwd <= i_stream.error;
- part_keep <= i_stream.keep;
+ if rising_edge(i_clk) then
+ v_data := (others => '0');
+ for byte in C_SLICE_HI / 8 downto C_SLICE_LO / 8 loop
+ -- extract a slice of the data bus.
+ -- validate each byte using keep, set to zero if invalid.
+ v_data(byte * 8 + 7 downto byte * 8) := i_stream.data(byte * 8 + 7 downto byte * 8)
+ and i_stream.keep(byte);
+ end loop;
+ if g_BIT_REVERSE_IN then
+ v_data := byte_swap(bit_swap(v_data));
end if;
- end process P_PIPE_CONTROL;
-
- -- XOR all the part CRC together.
- -- If this is large (g_AREA_SPEED_TRADEOFF_FACTOR > 5), could add a pipeline or two.
- P_COMBINE : process (i_clk) is
- variable v_crc_comb : std_logic_vector(o_crc'range);
- begin -- process
- if rising_edge(i_clk) then
- v_crc_comb := (others => err_fwd); -- Invert the result of the CRC.
- for idx in 0 to g_AREA_SPEED_TRADEOFF_FACTOR - 1 loop
- v_crc_comb := part_crc(idx) xor v_crc_comb;
- end loop;
- crc_combined <= v_crc_comb;
- crc_combined_vld <= part_crc_vld(0);
- comb_keep <= part_keep;
+ if i_stream.valid then
+ sop <= i_stream.last;
+ if sop then
+ v_crc_fb := g_INIT_CRC when C_SLICE_HI = i_stream.data'high
+ else (others => '0');
+ else
+ v_crc_fb := slice_crc;
+ end if;
+ -- compute the slice_crc for this slice.
+ slice_crc <= f_next_crc(v_data, v_crc_fb);
end if;
- end process P_COMBINE;
-
- -- CRC has been calculated to the full width of the bus.
- -- Now roll back the extra zero bytes that were left over.
- -- To achieve more speed, possibly should do this in each slice before combining the part CRCs.
- P_ROLLBACK : process (i_clk) is
- variable v_rb_crc : std_logic_vector(o_crc'range);
- variable v_xor_crc : std_logic_vector(o_crc'range);
- begin
- if rising_edge(i_clk) then
- v_rb_crc := crc_combined;
- if crc_combined_vld then
- for byte in comb_keep'low to comb_keep'high loop
- if not comb_keep(byte) then
- for b in 0 to 7 loop
- v_rb_crc := prevCRC32_D1('0', v_rb_crc);
- end loop; -- b
- else
- assert (and comb_keep(comb_keep'high downto byte))
- report "Expected the high bits of the keep to all be the same. Got: " & to_string(comb_keep)
- severity error;
- exit; -- exit loop prematurely.
- end if;
- end loop; --byte
- end if;
-
- v_xor_crc := v_rb_crc xor g_XOR_CRC_OUT;
-
- if g_BIT_REVERSE_OUT then
- o_crc <= byte_swap(bit_swap(v_xor_crc));
- else
- o_crc <= v_xor_crc;
- end if;
-
- o_crc_vld <= crc_combined_vld;
+ part_crc_vld(idx) <= i_stream.valid and i_stream.last;
+ if i_clk_reset then
+ sop <= '1';
end if;
- end process P_ROLLBACK;
-
+ end if;
+ end process P_CRC;
+
+ part_crc(idx) <= slice_crc;
+ end generate G_SLICE;
+
+ P_PIPE_CONTROL : process (i_clk) is
+ begin -- process
+ if rising_edge(i_clk) then
+ err_fwd <= i_stream.error;
+ part_keep <= i_stream.keep;
+ end if;
+ end process P_PIPE_CONTROL;
+
+ -- XOR all the part CRC together.
+ -- If this is large (g_AREA_SPEED_TRADEOFF_FACTOR > 5), could add a pipeline or two.
+ P_COMBINE : process (i_clk) is
+ variable v_crc_comb : std_logic_vector(o_crc'range);
+ begin -- process
+ if rising_edge(i_clk) then
+ v_crc_comb := (others => err_fwd); -- Invert the result of the CRC.
+ for idx in 0 to g_AREA_SPEED_TRADEOFF_FACTOR - 1 loop
+ v_crc_comb := part_crc(idx) xor v_crc_comb;
+ end loop;
+ crc_combined <= v_crc_comb;
+ crc_combined_vld <= part_crc_vld(0);
+ comb_keep <= part_keep;
+ end if;
+ end process P_COMBINE;
+
+ -- CRC has been calculated to the full width of the bus.
+ -- Now roll back the extra zero bytes that were left over.
+ -- To achieve more speed, possibly should do this in each slice before combining the part CRCs.
+ P_ROLLBACK : process (i_clk) is
+ variable v_rb_crc : std_logic_vector(o_crc'range);
+ variable v_xor_crc : std_logic_vector(o_crc'range);
+ begin
+ if rising_edge(i_clk) then
+ v_rb_crc := crc_combined;
+ if crc_combined_vld then
+ for byte in comb_keep'low to comb_keep'high loop
+ if not comb_keep(byte) then
+ for b in 0 to 7 loop
+ v_rb_crc := prevCRC32_D1('0', v_rb_crc);
+ end loop; -- b
+ else
+ assert (and comb_keep(comb_keep'high downto byte))
+ report "Expected the high bits of the keep to all be the same. Got: " & to_string(comb_keep)
+ severity error;
+ exit; -- exit loop prematurely.
+ end if;
+ end loop; --byte
+ end if;
+
+ v_xor_crc := v_rb_crc xor g_XOR_CRC_OUT;
+
+ if g_BIT_REVERSE_OUT then
+ o_crc <= byte_swap(bit_swap(v_xor_crc));
+ else
+ o_crc <= v_xor_crc;
+ end if;
+
+ o_crc_vld <= crc_combined_vld;
+ end if;
+ end process P_ROLLBACK;
end architecture RTL;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_pkg.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_pkg.vhd
index 364aad859eab6f97fe5011c322c6dc3fe003cd38..47cd16414eb5e00b505a51e5cd272c8db97a0836 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/crc_pkg.vhd
@@ -20,25 +20,23 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
library work;
-use work.PCK_CRC32_D8.all;
-use work.PCK_CRC32_D16.all;
-use work.PCK_CRC32_D32.all;
-use work.PCK_CRC32_D64.all;
-use work.PCK_CRC32_D128.all;
-use work.PCK_CRC32_D256.all;
-use work.PCK_CRC32_D512.all;
-use work.PCK_CRC32_D1024.all;
+ use work.PCK_CRC32_D8.all;
+ use work.PCK_CRC32_D16.all;
+ use work.PCK_CRC32_D32.all;
+ use work.PCK_CRC32_D64.all;
+ use work.PCK_CRC32_D128.all;
+ use work.PCK_CRC32_D256.all;
+ use work.PCK_CRC32_D512.all;
+ use work.PCK_CRC32_D1024.all;
package crc_pkg is
-
function f_next_crc (
- data : std_logic_vector;
- crc : std_logic_vector)
+ data : std_logic_vector;
+ crc : std_logic_vector)
return std_logic_vector;
-
end package crc_pkg;
package body crc_pkg is
@@ -46,7 +44,7 @@ package body crc_pkg is
function f_next_crc (
data : std_logic_vector;
crc : std_logic_vector)
- return std_logic_vector is
+ return std_logic_vector is
begin
case crc'length is
when 32 =>
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/lfsr_pkg.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/lfsr_pkg.vhd
index 3ccbc23c8f618d7b65ffcd8d07131f43aea9152b..44c34ed4451b7b0cb7db01c521f61341483e4849 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/lfsr_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/lfsr_pkg.vhd
@@ -1,16 +1,16 @@
-------------------------------------------------------------------------------
-- Title : Linear Feedback Shift Register Package
--- Project :
+-- Project :
-------------------------------------------------------------------------------
-- File : lfsr_pkg.vhd
-- Author : William Kamp <william.kamp@aut.ac.nz>
-- Company : High Performance Computing Research Lab, Auckland University of Technology
-- Created : 2018-06-29
-- Last update: 2018-07-02
--- Platform :
+-- Platform :
-- Standard : VHDL
-------------------------------------------------------------------------------
--- Description:
+-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018 High Performance Computing Research Lab, Auckland University of Technology
-------------------------------------------------------------------------------
@@ -20,384 +20,382 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
library work;
package lfsr_pkg is
+ type t_int_a is array (natural range <>) of integer;
+ type t_taps_a is array (natural range <>) of t_int_a(0 to 3);
- type t_int_a is array (natural range <>) of integer;
- type t_taps_a is array (natural range <>) of t_int_a(0 to 3);
+ --Table of Linear Feedback Shift Registers
+ --Roy Ward, Tim Molteno; Department of Physics, University of Otago, Box 56, Dunedin, New Zealand
+ --October 26, 2007
+ --Retrieved 02-07-2018 from https://web.archive.org/web/20161007061934/http://courses.cse.tamu.edu/csce680/walker/lfsr_table.pdf
+ --above reference gives taps for LFSRs for 2-786, 1024, 2048, 4096.
+ --First page, 2-67 reproduced below.
+ constant xnor_taps : t_taps_a(2 to 4096) := (
+ -- page 1
+ 2 => (2, 1, -1, -1), 24 => (24, 23, 21, 20), 46 => (46, 40, 39, 38),
+ 3 => (3, 2, -1, -1), 25 => (25, 24, 23, 22), 47 => (47, 46, 43, 42),
+ 4 => (4, 3, -1, -1), 26 => (26, 25, 24, 20), 48 => (48, 44, 41, 39),
+ 5 => (5, 4, 3, 2), 27 => (27, 26, 25, 22), 49 => (49, 45, 44, 43),
+ 6 => (6, 5, 3, 2), 28 => (28, 27, 24, 22), 50 => (50, 48, 47, 46),
+ 7 => (7, 6, 5, 4), 29 => (29, 28, 27, 25), 51 => (51, 50, 48, 45),
+ 8 => (8, 6, 5, 4), 30 => (30, 29, 26, 24), 52 => (52, 51, 49, 46),
+ 9 => (9, 8, 6, 5), 31 => (31, 30, 29, 28), 53 => (53, 52, 51, 47),
+ 10 => (10, 9, 7, 6), 32 => (32, 30, 26, 25), 54 => (54, 51, 48, 46),
+ 11 => (11, 10, 9, 7), 33 => (33, 32, 29, 27), 55 => (55, 54, 53, 49),
+ 12 => (12, 11, 8, 6), 34 => (34, 31, 30, 26), 56 => (56, 54, 52, 49),
+ 13 => (13, 12, 10, 9), 35 => (35, 34, 28, 27), 57 => (57, 55, 54, 52),
+ 14 => (14, 13, 11, 9), 36 => (36, 35, 29, 28), 58 => (58, 57, 53, 52),
+ 15 => (15, 14, 13, 11), 37 => (37, 36, 33, 31), 59 => (59, 57, 55, 52),
+ 16 => (16, 14, 13, 11), 38 => (38, 37, 33, 32), 60 => (60, 58, 56, 55),
+ 17 => (17, 16, 15, 14), 39 => (39, 38, 35, 32), 61 => (61, 60, 59, 56),
+ 18 => (18, 17, 16, 13), 40 => (40, 37, 36, 35), 62 => (62, 59, 57, 56),
+ 19 => (19, 18, 17, 14), 41 => (41, 40, 39, 38), 63 => (63, 62, 59, 58),
+ 20 => (20, 19, 16, 14), 42 => (42, 40, 37, 35), 64 => (64, 63, 61, 60),
+ 21 => (21, 20, 19, 16), 43 => (43, 42, 38, 37), 65 => (65, 64, 62, 61),
+ 22 => (22, 19, 18, 17), 44 => (44, 42, 39, 38), 66 => (66, 60, 58, 57),
+ 23 => (23, 22, 20, 18), 45 => (45, 44, 42, 41), 67 => (67, 66, 65, 62),
+ -- page 2
+ 68 => (68, 67, 63, 61), 120 => (120, 118, 114, 111), 172 => (172, 169, 165, 161),
+ 69 => (69, 67, 64, 63), 121 => (121, 120, 116, 113), 173 => (173, 171, 168, 165),
+ 70 => (70, 69, 67, 65), 122 => (122, 121, 120, 116), 174 => (174, 169, 166, 165),
+ 71 => (71, 70, 68, 66), 123 => (123, 122, 119, 115), 175 => (175, 173, 171, 169),
+ 72 => (72, 69, 63, 62), 124 => (124, 119, 118, 117), 176 => (176, 167, 165, 164),
+ 73 => (73, 71, 70, 69), 125 => (125, 120, 119, 118), 177 => (177, 175, 174, 172),
+ 74 => (74, 71, 70, 67), 126 => (126, 124, 122, 119), 178 => (178, 176, 171, 170),
+ 75 => (75, 74, 72, 69), 127 => (127, 126, 124, 120), 179 => (179, 178, 177, 175),
+ 76 => (76, 74, 72, 71), 128 => (128, 127, 126, 121), 180 => (180, 173, 170, 168),
+ 77 => (77, 75, 72, 71), 129 => (129, 128, 125, 124), 181 => (181, 180, 175, 174),
+ 78 => (78, 77, 76, 71), 130 => (130, 129, 128, 125), 182 => (182, 181, 176, 174),
+ 79 => (79, 77, 76, 75), 131 => (131, 129, 128, 123), 183 => (183, 179, 176, 175),
+ 80 => (80, 78, 76, 71), 132 => (132, 130, 127, 123), 184 => (184, 177, 176, 175),
+ 81 => (81, 79, 78, 75), 133 => (133, 131, 125, 124), 185 => (185, 184, 182, 177),
+ 82 => (82, 78, 76, 73), 134 => (134, 133, 129, 127), 186 => (186, 180, 178, 177),
+ 83 => (83, 81, 79, 76), 135 => (135, 132, 131, 129), 187 => (187, 182, 181, 180),
+ 84 => (84, 83, 77, 75), 136 => (136, 134, 133, 128), 188 => (188, 186, 183, 182),
+ 85 => (85, 84, 83, 77), 137 => (137, 136, 133, 126), 189 => (189, 187, 184, 183),
+ 86 => (86, 84, 81, 80), 138 => (138, 137, 131, 130), 190 => (190, 188, 184, 177),
+ 87 => (87, 86, 82, 80), 139 => (139, 136, 134, 131), 191 => (191, 187, 185, 184),
+ 88 => (88, 80, 79, 77), 140 => (140, 139, 136, 132), 192 => (192, 190, 178, 177),
+ 89 => (89, 86, 84, 83), 141 => (141, 140, 135, 128), 193 => (193, 189, 186, 184),
+ 90 => (90, 88, 87, 85), 142 => (142, 141, 139, 132), 194 => (194, 192, 191, 190),
+ 91 => (91, 90, 86, 83), 143 => (143, 141, 140, 138), 195 => (195, 193, 192, 187),
+ 92 => (92, 90, 87, 86), 144 => (144, 142, 140, 137), 196 => (196, 194, 187, 185),
+ 93 => (93, 91, 90, 87), 145 => (145, 144, 140, 139), 197 => (197, 195, 193, 188),
+ 94 => (94, 93, 89, 88), 146 => (146, 144, 143, 141), 198 => (198, 193, 190, 183),
+ 95 => (95, 94, 90, 88), 147 => (147, 145, 143, 136), 199 => (199, 198, 195, 190),
+ 96 => (96, 90, 87, 86), 148 => (148, 145, 143, 141), 200 => (200, 198, 197, 195),
+ 97 => (97, 95, 93, 91), 149 => (149, 142, 140, 139), 201 => (201, 199, 198, 195),
+ 98 => (98, 97, 91, 90), 150 => (150, 148, 147, 142), 202 => (202, 198, 196, 195),
+ 99 => (99, 95, 94, 92), 151 => (151, 150, 149, 148), 203 => (203, 202, 196, 195),
+ 100 => (100, 98, 93, 92), 152 => (152, 150, 149, 146), 204 => (204, 201, 200, 194),
+ 101 => (101, 100, 95, 94), 153 => (153, 149, 148, 145), 205 => (205, 203, 200, 196),
+ 102 => (102, 99, 97, 96), 154 => (154, 153, 149, 145), 206 => (206, 201, 197, 196),
+ 103 => (103, 102, 99, 94), 155 => (155, 151, 150, 148), 207 => (207, 206, 201, 198),
+ 104 => (104, 103, 94, 93), 156 => (156, 153, 151, 147), 208 => (208, 207, 205, 199),
+ 105 => (105, 104, 99, 98), 157 => (157, 155, 152, 151), 209 => (209, 207, 206, 204),
+ 106 => (106, 105, 101, 100), 158 => (158, 153, 152, 150), 210 => (210, 207, 206, 198),
+ 107 => (107, 105, 99, 98), 159 => (159, 156, 153, 148), 211 => (211, 203, 201, 200),
+ 108 => (108, 103, 97, 96), 160 => (160, 158, 157, 155), 212 => (212, 209, 208, 205),
+ 109 => (109, 107, 105, 104), 161 => (161, 159, 158, 155), 213 => (213, 211, 208, 207),
+ 110 => (110, 109, 106, 104), 162 => (162, 158, 155, 154), 214 => (214, 213, 211, 209),
+ 111 => (111, 109, 107, 104), 163 => (163, 160, 157, 156), 215 => (215, 212, 210, 209),
+ 112 => (112, 108, 106, 101), 164 => (164, 159, 158, 152), 216 => (216, 215, 213, 209),
+ 113 => (113, 111, 110, 108), 165 => (165, 162, 157, 156), 217 => (217, 213, 212, 211),
+ 114 => (114, 113, 112, 103), 166 => (166, 164, 163, 156), 218 => (218, 217, 211, 210),
+ 115 => (115, 110, 108, 107), 167 => (167, 165, 163, 161), 219 => (219, 218, 215, 211),
+ 116 => (116, 114, 111, 110), 168 => (168, 162, 159, 152), 220 => (220, 211, 210, 208),
+ 117 => (117, 116, 115, 112), 169 => (169, 164, 163, 161), 221 => (221, 219, 215, 213),
+ 118 => (118, 116, 113, 112), 170 => (170, 169, 166, 161), 222 => (222, 220, 217, 214),
+ 119 => (119, 116, 111, 110), 171 => (171, 169, 166, 165), 223 => (223, 221, 219, 218),
+ -- page 3
+ 224 => (224, 222, 217, 212), 276 => (276, 275, 273, 270), 328 => (328, 323, 321, 319),
+ 225 => (225, 224, 220, 215), 277 => (277, 274, 271, 265), 329 => (329, 326, 323, 321),
+ 226 => (226, 223, 219, 216), 278 => (278, 277, 274, 273), 330 => (330, 328, 323, 322),
+ 227 => (227, 223, 218, 217), 279 => (279, 278, 275, 274), 331 => (331, 329, 325, 321),
+ 228 => (228, 226, 217, 216), 280 => (280, 278, 275, 271), 332 => (332, 325, 321, 320),
+ 229 => (229, 228, 225, 219), 281 => (281, 280, 277, 272), 333 => (333, 331, 329, 325),
+ 230 => (230, 224, 223, 222), 282 => (282, 278, 277, 272), 334 => (334, 333, 330, 327),
+ 231 => (231, 229, 227, 224), 283 => (283, 278, 276, 271), 335 => (335, 333, 328, 325),
+ 232 => (232, 228, 223, 221), 284 => (284, 279, 278, 276), 336 => (336, 335, 332, 329),
+ 233 => (233, 232, 229, 224), 285 => (285, 280, 278, 275), 337 => (337, 336, 331, 327),
+ 234 => (234, 232, 225, 223), 286 => (286, 285, 276, 271), 338 => (338, 336, 335, 332),
+ 235 => (235, 234, 229, 226), 287 => (287, 285, 282, 281), 339 => (339, 332, 329, 323),
+ 236 => (236, 229, 228, 226), 288 => (288, 287, 278, 277), 340 => (340, 337, 336, 329),
+ 237 => (237, 236, 233, 230), 289 => (289, 286, 285, 277), 341 => (341, 336, 330, 327),
+ 238 => (238, 237, 236, 233), 290 => (290, 288, 287, 285), 342 => (342, 341, 340, 331),
+ 239 => (239, 238, 232, 227), 291 => (291, 286, 280, 279), 343 => (343, 338, 335, 333),
+ 240 => (240, 237, 235, 232), 292 => (292, 291, 289, 285), 344 => (344, 338, 334, 333),
+ 241 => (241, 237, 233, 232), 293 => (293, 292, 287, 282), 345 => (345, 343, 341, 337),
+ 242 => (242, 241, 236, 231), 294 => (294, 292, 291, 285), 346 => (346, 344, 339, 335),
+ 243 => (243, 242, 238, 235), 295 => (295, 293, 291, 290), 347 => (347, 344, 337, 336),
+ 244 => (244, 243, 240, 235), 296 => (296, 292, 287, 285), 348 => (348, 344, 341, 340),
+ 245 => (245, 244, 241, 239), 297 => (297, 296, 293, 292), 349 => (349, 347, 344, 343),
+ 246 => (246, 245, 244, 235), 298 => (298, 294, 290, 287), 350 => (350, 340, 337, 336),
+ 247 => (247, 245, 243, 238), 299 => (299, 295, 293, 288), 351 => (351, 348, 345, 343),
+ 248 => (248, 238, 234, 233), 300 => (300, 290, 288, 287), 352 => (352, 346, 341, 339),
+ 249 => (249, 248, 245, 242), 301 => (301, 299, 296, 292), 353 => (353, 349, 346, 344),
+ 250 => (250, 247, 245, 240), 302 => (302, 297, 293, 290), 354 => (354, 349, 341, 340),
+ 251 => (251, 249, 247, 244), 303 => (303, 297, 291, 290), 355 => (355, 354, 350, 349),
+ 252 => (252, 251, 247, 241), 304 => (304, 303, 302, 293), 356 => (356, 349, 347, 346),
+ 253 => (253, 252, 247, 246), 305 => (305, 303, 299, 298), 357 => (357, 355, 347, 346),
+ 254 => (254, 253, 252, 247), 306 => (306, 305, 303, 299), 358 => (358, 351, 350, 344),
+ 255 => (255, 253, 252, 250), 307 => (307, 305, 303, 299), 359 => (359, 358, 352, 350),
+ 256 => (256, 254, 251, 246), 308 => (308, 306, 299, 293), 360 => (360, 359, 335, 334),
+ 257 => (257, 255, 251, 250), 309 => (309, 307, 302, 299), 361 => (361, 360, 357, 354),
+ 258 => (258, 254, 252, 249), 310 => (310, 309, 305, 302), 362 => (362, 360, 351, 344),
+ 259 => (259, 257, 253, 249), 311 => (311, 308, 306, 304), 363 => (363, 362, 356, 355),
+ 260 => (260, 253, 252, 250), 312 => (312, 307, 302, 301), 364 => (364, 363, 359, 352),
+ 261 => (261, 257, 255, 254), 313 => (313, 312, 310, 306), 365 => (365, 360, 359, 356),
+ 262 => (262, 258, 254, 253), 314 => (314, 311, 305, 300), 366 => (366, 362, 359, 352),
+ 263 => (263, 261, 258, 252), 315 => (315, 314, 306, 305), 367 => (367, 365, 363, 358),
+ 264 => (264, 263, 255, 254), 316 => (316, 309, 305, 304), 368 => (368, 361, 359, 351),
+ 265 => (265, 263, 262, 260), 317 => (317, 315, 313, 310), 369 => (369, 367, 359, 358),
+ 266 => (266, 265, 260, 259), 318 => (318, 313, 312, 310), 370 => (370, 368, 367, 365),
+ 267 => (267, 264, 261, 259), 319 => (319, 318, 317, 308), 371 => (371, 369, 368, 363),
+ 268 => (268, 267, 264, 258), 320 => (320, 319, 317, 316), 372 => (372, 369, 365, 357),
+ 269 => (269, 268, 263, 262), 321 => (321, 319, 316, 314), 373 => (373, 371, 366, 365),
+ 270 => (270, 267, 263, 260), 322 => (322, 321, 320, 305), 374 => (374, 369, 368, 366),
+ 271 => (271, 265, 264, 260), 323 => (323, 322, 320, 313), 375 => (375, 374, 368, 367),
+ 272 => (272, 270, 266, 263), 324 => (324, 321, 320, 318), 376 => (376, 371, 369, 368),
+ 273 => (273, 272, 271, 266), 325 => (325, 323, 320, 315), 377 => (377, 376, 374, 369),
+ 274 => (274, 272, 267, 265), 326 => (326, 325, 323, 316), 378 => (378, 374, 365, 363),
+ 275 => (275, 266, 265, 264), 327 => (327, 325, 322, 319), 379 => (379, 375, 370, 369),
+ -- page 4
+ 380 => (380, 377, 374, 366), 432 => (432, 429, 428, 419), 484 => (484, 483, 482, 470),
+ 381 => (381, 380, 379, 376), 433 => (433, 430, 428, 422), 485 => (485, 479, 469, 468),
+ 382 => (382, 379, 375, 364), 434 => (434, 429, 423, 422), 486 => (486, 481, 478, 472),
+ 383 => (383, 382, 378, 374), 435 => (435, 430, 426, 423), 487 => (487, 485, 483, 478),
+ 384 => (384, 378, 369, 368), 436 => (436, 432, 431, 430), 488 => (488, 487, 485, 484),
+ 385 => (385, 383, 381, 379), 437 => (437, 436, 435, 431), 489 => (489, 484, 483, 480),
+ 386 => (386, 381, 380, 376), 438 => (438, 436, 432, 421), 490 => (490, 485, 483, 481),
+ 387 => (387, 385, 379, 378), 439 => (439, 437, 436, 431), 491 => (491, 488, 485, 480),
+ 388 => (388, 387, 385, 374), 440 => (440, 439, 437, 436), 492 => (492, 491, 485, 484),
+ 389 => (389, 384, 380, 379), 441 => (441, 440, 433, 430), 493 => (493, 490, 488, 483),
+ 390 => (390, 388, 380, 377), 442 => (442, 440, 437, 435), 494 => (494, 493, 489, 481),
+ 391 => (391, 390, 389, 385), 443 => (443, 442, 437, 433), 495 => (495, 494, 486, 480),
+ 392 => (392, 386, 382, 379), 444 => (444, 435, 432, 431), 496 => (496, 494, 491, 480),
+ 393 => (393, 392, 391, 386), 445 => (445, 441, 439, 438), 497 => (497, 493, 488, 486),
+ 394 => (394, 392, 387, 386), 446 => (446, 442, 439, 431), 498 => (498, 495, 489, 487),
+ 395 => (395, 390, 389, 384), 447 => (447, 446, 441, 438), 499 => (499, 494, 493, 488),
+ 396 => (396, 392, 390, 389), 448 => (448, 444, 442, 437), 500 => (500, 499, 494, 490),
+ 397 => (397, 392, 387, 385), 449 => (449, 446, 440, 438), 501 => (501, 499, 497, 496),
+ 398 => (398, 393, 392, 384), 450 => (450, 443, 438, 434), 502 => (502, 498, 497, 494),
+ 399 => (399, 397, 390, 388), 451 => (451, 450, 441, 435), 503 => (503, 502, 501, 500),
+ 400 => (400, 398, 397, 395), 452 => (452, 448, 447, 446), 504 => (504, 502, 490, 483),
+ 401 => (401, 399, 392, 389), 453 => (453, 449, 447, 438), 505 => (505, 500, 497, 493),
+ 402 => (402, 399, 398, 393), 454 => (454, 449, 445, 444), 506 => (506, 501, 494, 491),
+ 403 => (403, 398, 395, 394), 455 => (455, 453, 449, 444), 507 => (507, 504, 501, 494),
+ 404 => (404, 400, 398, 397), 456 => (456, 454, 445, 433), 508 => (508, 505, 500, 495),
+ 405 => (405, 398, 397, 388), 457 => (457, 454, 449, 446), 509 => (509, 506, 502, 501),
+ 406 => (406, 402, 397, 393), 458 => (458, 453, 448, 445), 510 => (510, 501, 500, 498),
+ 407 => (407, 402, 400, 398), 459 => (459, 457, 454, 447), 511 => (511, 509, 503, 501),
+ 408 => (408, 407, 403, 401), 460 => (460, 459, 455, 451), 512 => (512, 510, 507, 504),
+ 409 => (409, 406, 404, 402), 461 => (461, 460, 455, 454), 513 => (513, 505, 503, 500),
+ 410 => (410, 407, 406, 400), 462 => (462, 457, 451, 450), 514 => (514, 511, 509, 507),
+ 411 => (411, 408, 401, 399), 463 => (463, 456, 455, 452), 515 => (515, 511, 508, 501),
+ 412 => (412, 409, 404, 401), 464 => (464, 460, 455, 441), 516 => (516, 514, 511, 509),
+ 413 => (413, 407, 406, 403), 465 => (465, 463, 462, 457), 517 => (517, 515, 507, 505),
+ 414 => (414, 405, 401, 398), 466 => (466, 460, 455, 452), 518 => (518, 516, 515, 507),
+ 415 => (415, 413, 411, 406), 467 => (467, 466, 461, 456), 519 => (519, 517, 511, 507),
+ 416 => (416, 414, 411, 407), 468 => (468, 464, 459, 453), 520 => (520, 509, 507, 503),
+ 417 => (417, 416, 414, 407), 469 => (469, 467, 464, 460), 521 => (521, 519, 514, 512),
+ 418 => (418, 417, 415, 403), 470 => (470, 468, 462, 461), 522 => (522, 518, 509, 507),
+ 419 => (419, 415, 414, 404), 471 => (471, 469, 468, 465), 523 => (523, 521, 517, 510),
+ 420 => (420, 412, 410, 407), 472 => (472, 470, 469, 461), 524 => (524, 523, 519, 515),
+ 421 => (421, 419, 417, 416), 473 => (473, 470, 467, 465), 525 => (525, 524, 521, 519),
+ 422 => (422, 421, 416, 412), 474 => (474, 465, 463, 456), 526 => (526, 525, 521, 517),
+ 423 => (423, 420, 418, 414), 475 => (475, 471, 467, 466), 527 => (527, 526, 520, 518),
+ 424 => (424, 422, 417, 415), 476 => (476, 475, 468, 466), 528 => (528, 526, 522, 517),
+ 425 => (425, 422, 421, 418), 477 => (477, 470, 462, 461), 529 => (529, 528, 525, 522),
+ 426 => (426, 415, 414, 412), 478 => (478, 477, 474, 472), 530 => (530, 527, 523, 520),
+ 427 => (427, 422, 421, 416), 479 => (479, 475, 472, 470), 531 => (531, 529, 525, 519),
+ 428 => (428, 426, 425, 417), 480 => (480, 473, 467, 464), 532 => (532, 529, 528, 522),
+ 429 => (429, 422, 421, 419), 481 => (481, 480, 472, 471), 533 => (533, 531, 530, 529),
+ 430 => (430, 419, 417, 415), 482 => (482, 477, 476, 473), 534 => (534, 533, 529, 527),
+ 431 => (431, 430, 428, 426), 483 => (483, 479, 477, 474), 535 => (535, 533, 529, 527),
+ -- page 5
+ 536 => (536, 533, 531, 529), 588 => (588, 577, 572, 571), 640 => (640, 638, 637, 626),
+ 537 => (537, 536, 535, 527), 589 => (589, 586, 585, 579), 641 => (641, 640, 636, 622),
+ 538 => (538, 537, 536, 533), 590 => (590, 588, 587, 578), 642 => (642, 636, 633, 632),
+ 539 => (539, 535, 534, 529), 591 => (591, 587, 585, 582), 643 => (643, 641, 640, 632),
+ 540 => (540, 537, 534, 529), 592 => (592, 591, 573, 568), 644 => (644, 634, 633, 632),
+ 541 => (541, 537, 531, 528), 593 => (593, 588, 585, 584), 645 => (645, 641, 637, 634),
+ 542 => (542, 540, 539, 533), 594 => (594, 586, 584, 583), 646 => (646, 635, 634, 633),
+ 543 => (543, 538, 536, 532), 595 => (595, 594, 593, 586), 647 => (647, 646, 643, 642),
+ 544 => (544, 538, 535, 531), 596 => (596, 592, 591, 590), 648 => (648, 647, 626, 625),
+ 545 => (545, 539, 537, 532), 597 => (597, 588, 585, 583), 649 => (649, 648, 644, 638),
+ 546 => (546, 545, 544, 538), 598 => (598, 597, 592, 591), 650 => (650, 644, 635, 632),
+ 547 => (547, 543, 540, 534), 599 => (599, 593, 591, 590), 651 => (651, 646, 638, 637),
+ 548 => (548, 545, 543, 538), 600 => (600, 599, 590, 589), 652 => (652, 647, 643, 641),
+ 549 => (549, 546, 545, 533), 601 => (601, 600, 597, 589), 653 => (653, 646, 645, 643),
+ 550 => (550, 546, 533, 529), 602 => (602, 596, 594, 591), 654 => (654, 649, 643, 640),
+ 551 => (551, 550, 547, 542), 603 => (603, 600, 599, 597), 655 => (655, 653, 639, 638),
+ 552 => (552, 550, 547, 532), 604 => (604, 600, 598, 589), 656 => (656, 646, 638, 637),
+ 553 => (553, 550, 549, 542), 605 => (605, 600, 598, 595), 657 => (657, 656, 650, 649),
+ 554 => (554, 551, 546, 543), 606 => (606, 602, 599, 591), 658 => (658, 651, 648, 646),
+ 555 => (555, 551, 546, 545), 607 => (607, 600, 598, 595), 659 => (659, 657, 655, 644),
+ 556 => (556, 549, 546, 540), 608 => (608, 606, 602, 585), 660 => (660, 657, 656, 648),
+ 557 => (557, 552, 551, 550), 609 => (609, 601, 600, 597), 661 => (661, 657, 650, 649),
+ 558 => (558, 553, 549, 544), 610 => (610, 602, 600, 599), 662 => (662, 659, 656, 650),
+ 559 => (559, 557, 552, 550), 611 => (611, 609, 607, 601), 663 => (663, 655, 652, 649),
+ 560 => (560, 554, 551, 549), 612 => (612, 607, 602, 598), 664 => (664, 662, 660, 649),
+ 561 => (561, 558, 552, 550), 613 => (613, 609, 603, 594), 665 => (665, 661, 659, 654),
+ 562 => (562, 560, 558, 551), 614 => (614, 613, 612, 607), 666 => (666, 664, 659, 656),
+ 563 => (563, 561, 554, 549), 615 => (615, 614, 609, 608), 667 => (667, 664, 660, 649),
+ 564 => (564, 563, 561, 558), 616 => (616, 614, 602, 597), 668 => (668, 658, 656, 651),
+ 565 => (565, 564, 559, 554), 617 => (617, 612, 608, 607), 669 => (669, 667, 665, 664),
+ 566 => (566, 564, 561, 560), 618 => (618, 615, 604, 598), 670 => (670, 669, 665, 664),
+ 567 => (567, 563, 557, 556), 619 => (619, 614, 611, 610), 671 => (671, 669, 665, 662),
+ 568 => (568, 558, 557, 551), 620 => (620, 619, 618, 611), 672 => (672, 667, 666, 661),
+ 569 => (569, 568, 559, 557), 621 => (621, 616, 615, 609), 673 => (673, 666, 664, 663),
+ 570 => (570, 563, 558, 552), 622 => (622, 612, 610, 605), 674 => (674, 671, 665, 660),
+ 571 => (571, 569, 566, 561), 623 => (623, 614, 613, 612), 675 => (675, 674, 672, 669),
+ 572 => (572, 571, 564, 560), 624 => (624, 617, 615, 612), 676 => (676, 675, 671, 664),
+ 573 => (573, 569, 567, 563), 625 => (625, 620, 617, 613), 677 => (677, 674, 673, 669),
+ 574 => (574, 569, 565, 560), 626 => (626, 623, 621, 613), 678 => (678, 675, 673, 663),
+ 575 => (575, 572, 570, 569), 627 => (627, 622, 617, 613), 679 => (679, 676, 667, 661),
+ 576 => (576, 573, 572, 563), 628 => (628, 626, 617, 616), 680 => (680, 679, 650, 645),
+ 577 => (577, 575, 574, 569), 629 => (629, 627, 624, 623), 681 => (681, 678, 672, 670),
+ 578 => (578, 562, 556, 555), 630 => (630, 628, 626, 623), 682 => (682, 681, 679, 675),
+ 579 => (579, 572, 570, 567), 631 => (631, 625, 623, 617), 683 => (683, 682, 677, 672),
+ 580 => (580, 579, 576, 574), 632 => (632, 629, 619, 613), 684 => (684, 681, 671, 666),
+ 581 => (581, 575, 574, 568), 633 => (633, 632, 631, 626), 685 => (685, 684, 682, 681),
+ 582 => (582, 579, 576, 571), 634 => (634, 631, 629, 627), 686 => (686, 684, 674, 673),
+ 583 => (583, 581, 577, 575), 635 => (635, 631, 625, 621), 687 => (687, 682, 675, 673),
+ 584 => (584, 581, 571, 570), 636 => (636, 632, 628, 623), 688 => (688, 682, 674, 669),
+ 585 => (585, 583, 582, 577), 637 => (637, 636, 628, 623), 689 => (689, 686, 683, 681),
+ 586 => (586, 584, 581, 579), 638 => (638, 637, 633, 632), 690 => (690, 687, 683, 680),
+ 587 => (587, 586, 581, 576), 639 => (639, 636, 635, 629), 691 => (691, 689, 685, 678),
+ -- page 6
+ 692 => (692, 687, 686, 678), 725 => (725, 720, 719, 716), 758 => (758, 757, 746, 741),
+ 693 => (693, 691, 685, 678), 726 => (726, 725, 722, 721), 759 => (759, 757, 756, 750),
+ 694 => (694, 691, 681, 677), 727 => (727, 721, 719, 716), 760 => (760, 757, 747, 734),
+ 695 => (695, 694, 691, 686), 728 => (728, 726, 725, 724), 761 => (761, 760, 759, 758),
+ 696 => (696, 694, 686, 673), 729 => (729, 726, 724, 718), 762 => (762, 761, 755, 745),
+ 697 => (697, 689, 685, 681), 730 => (730, 726, 715, 711), 763 => (763, 754, 749, 747),
+ 698 => (698, 690, 689, 688), 731 => (731, 729, 725, 723), 764 => (764, 761, 759, 758),
+ 699 => (699, 698, 689, 684), 732 => (732, 729, 728, 725), 765 => (765, 760, 755, 754),
+ 700 => (700, 698, 695, 694), 733 => (733, 731, 726, 725), 766 => (766, 757, 747, 744),
+ 701 => (701, 699, 697, 685), 734 => (734, 724, 721, 720), 767 => (767, 763, 760, 759),
+ 702 => (702, 701, 699, 695), 735 => (735, 733, 728, 727), 768 => (768, 764, 751, 749),
+ 703 => (703, 702, 696, 691), 736 => (736, 730, 728, 723), 769 => (769, 763, 762, 760),
+ 704 => (704, 701, 699, 692), 737 => (737, 736, 733, 732), 770 => (770, 768, 765, 756),
+ 705 => (705, 704, 698, 697), 738 => (738, 730, 729, 727), 771 => (771, 765, 756, 754),
+ 706 => (706, 697, 695, 692), 739 => (739, 731, 723, 721), 772 => (772, 767, 766, 764),
+ 707 => (707, 702, 699, 692), 740 => (740, 737, 728, 716), 773 => (773, 767, 765, 763),
+ 708 => (708, 706, 704, 703), 741 => (741, 738, 733, 732), 774 => (774, 767, 760, 758),
+ 709 => (709, 708, 706, 705), 742 => (742, 741, 738, 730), 775 => (775, 771, 769, 768),
+ 710 => (710, 709, 696, 695), 743 => (743, 742, 731, 730), 776 => (776, 773, 764, 759),
+ 711 => (711, 704, 703, 700), 744 => (744, 743, 733, 731), 777 => (777, 776, 767, 761),
+ 712 => (712, 709, 708, 707), 745 => (745, 740, 738, 737), 778 => (778, 775, 762, 759),
+ 713 => (713, 706, 703, 696), 746 => (746, 738, 733, 728), 779 => (779, 776, 771, 769),
+ 714 => (714, 709, 707, 701), 747 => (747, 743, 741, 737), 780 => (780, 775, 772, 764),
+ 715 => (715, 714, 711, 708), 748 => (748, 744, 743, 733), 781 => (781, 779, 765, 764),
+ 716 => (716, 706, 705, 704), 749 => (749, 748, 743, 742), 782 => (782, 780, 779, 773),
+ 717 => (717, 716, 710, 701), 750 => (750, 746, 741, 734), 783 => (783, 782, 776, 773),
+ 718 => (718, 717, 716, 713), 751 => (751, 750, 748, 740), 784 => (784, 778, 775, 771),
+ 719 => (719, 711, 710, 707), 752 => (752, 749, 732, 731), 785 => (785, 780, 776, 775),
+ 720 => (720, 718, 712, 709), 753 => (753, 748, 745, 740), 786 => (786, 782, 780, 771),
+ 721 => (721, 720, 713, 712), 754 => (754, 742, 740, 735), 1024 => (1024, 1015, 1002, 1001),
+ 722 => (722, 721, 718, 707), 755 => (755, 754, 745, 743), 2048 => (2048, 2035, 2034, 2029),
+ 723 => (723, 717, 710, 707), 756 => (756, 755, 747, 740), 4096 => (4096, 4095, 4081, 4069),
+ 724 => (724, 719, 716, 711), 757 => (757, 756, 751, 750), others => (-1, -1, -1, -1)
+ );
- --Table of Linear Feedback Shift Registers
- --Roy Ward, Tim Molteno; Department of Physics, University of Otago, Box 56, Dunedin, New Zealand
- --October 26, 2007
- --Retrieved 02-07-2018 from https://web.archive.org/web/20161007061934/http://courses.cse.tamu.edu/csce680/walker/lfsr_table.pdf
- --above reference gives taps for LFSRs for 2-786, 1024, 2048, 4096.
- --First page, 2-67 reproduced below.
- constant xnor_taps : t_taps_a(2 to 4096) := (
- -- page 1
- 2 => (2, 1, -1, -1), 24 => (24, 23, 21, 20), 46 => (46, 40, 39, 38),
- 3 => (3, 2, -1, -1), 25 => (25, 24, 23, 22), 47 => (47, 46, 43, 42),
- 4 => (4, 3, -1, -1), 26 => (26, 25, 24, 20), 48 => (48, 44, 41, 39),
- 5 => (5, 4, 3, 2), 27 => (27, 26, 25, 22), 49 => (49, 45, 44, 43),
- 6 => (6, 5, 3, 2), 28 => (28, 27, 24, 22), 50 => (50, 48, 47, 46),
- 7 => (7, 6, 5, 4), 29 => (29, 28, 27, 25), 51 => (51, 50, 48, 45),
- 8 => (8, 6, 5, 4), 30 => (30, 29, 26, 24), 52 => (52, 51, 49, 46),
- 9 => (9, 8, 6, 5), 31 => (31, 30, 29, 28), 53 => (53, 52, 51, 47),
- 10 => (10, 9, 7, 6), 32 => (32, 30, 26, 25), 54 => (54, 51, 48, 46),
- 11 => (11, 10, 9, 7), 33 => (33, 32, 29, 27), 55 => (55, 54, 53, 49),
- 12 => (12, 11, 8, 6), 34 => (34, 31, 30, 26), 56 => (56, 54, 52, 49),
- 13 => (13, 12, 10, 9), 35 => (35, 34, 28, 27), 57 => (57, 55, 54, 52),
- 14 => (14, 13, 11, 9), 36 => (36, 35, 29, 28), 58 => (58, 57, 53, 52),
- 15 => (15, 14, 13, 11), 37 => (37, 36, 33, 31), 59 => (59, 57, 55, 52),
- 16 => (16, 14, 13, 11), 38 => (38, 37, 33, 32), 60 => (60, 58, 56, 55),
- 17 => (17, 16, 15, 14), 39 => (39, 38, 35, 32), 61 => (61, 60, 59, 56),
- 18 => (18, 17, 16, 13), 40 => (40, 37, 36, 35), 62 => (62, 59, 57, 56),
- 19 => (19, 18, 17, 14), 41 => (41, 40, 39, 38), 63 => (63, 62, 59, 58),
- 20 => (20, 19, 16, 14), 42 => (42, 40, 37, 35), 64 => (64, 63, 61, 60),
- 21 => (21, 20, 19, 16), 43 => (43, 42, 38, 37), 65 => (65, 64, 62, 61),
- 22 => (22, 19, 18, 17), 44 => (44, 42, 39, 38), 66 => (66, 60, 58, 57),
- 23 => (23, 22, 20, 18), 45 => (45, 44, 42, 41), 67 => (67, 66, 65, 62),
- -- page 2
- 68 => (68, 67, 63, 61), 120 => (120, 118, 114, 111), 172 => (172, 169, 165, 161),
- 69 => (69, 67, 64, 63), 121 => (121, 120, 116, 113), 173 => (173, 171, 168, 165),
- 70 => (70, 69, 67, 65), 122 => (122, 121, 120, 116), 174 => (174, 169, 166, 165),
- 71 => (71, 70, 68, 66), 123 => (123, 122, 119, 115), 175 => (175, 173, 171, 169),
- 72 => (72, 69, 63, 62), 124 => (124, 119, 118, 117), 176 => (176, 167, 165, 164),
- 73 => (73, 71, 70, 69), 125 => (125, 120, 119, 118), 177 => (177, 175, 174, 172),
- 74 => (74, 71, 70, 67), 126 => (126, 124, 122, 119), 178 => (178, 176, 171, 170),
- 75 => (75, 74, 72, 69), 127 => (127, 126, 124, 120), 179 => (179, 178, 177, 175),
- 76 => (76, 74, 72, 71), 128 => (128, 127, 126, 121), 180 => (180, 173, 170, 168),
- 77 => (77, 75, 72, 71), 129 => (129, 128, 125, 124), 181 => (181, 180, 175, 174),
- 78 => (78, 77, 76, 71), 130 => (130, 129, 128, 125), 182 => (182, 181, 176, 174),
- 79 => (79, 77, 76, 75), 131 => (131, 129, 128, 123), 183 => (183, 179, 176, 175),
- 80 => (80, 78, 76, 71), 132 => (132, 130, 127, 123), 184 => (184, 177, 176, 175),
- 81 => (81, 79, 78, 75), 133 => (133, 131, 125, 124), 185 => (185, 184, 182, 177),
- 82 => (82, 78, 76, 73), 134 => (134, 133, 129, 127), 186 => (186, 180, 178, 177),
- 83 => (83, 81, 79, 76), 135 => (135, 132, 131, 129), 187 => (187, 182, 181, 180),
- 84 => (84, 83, 77, 75), 136 => (136, 134, 133, 128), 188 => (188, 186, 183, 182),
- 85 => (85, 84, 83, 77), 137 => (137, 136, 133, 126), 189 => (189, 187, 184, 183),
- 86 => (86, 84, 81, 80), 138 => (138, 137, 131, 130), 190 => (190, 188, 184, 177),
- 87 => (87, 86, 82, 80), 139 => (139, 136, 134, 131), 191 => (191, 187, 185, 184),
- 88 => (88, 80, 79, 77), 140 => (140, 139, 136, 132), 192 => (192, 190, 178, 177),
- 89 => (89, 86, 84, 83), 141 => (141, 140, 135, 128), 193 => (193, 189, 186, 184),
- 90 => (90, 88, 87, 85), 142 => (142, 141, 139, 132), 194 => (194, 192, 191, 190),
- 91 => (91, 90, 86, 83), 143 => (143, 141, 140, 138), 195 => (195, 193, 192, 187),
- 92 => (92, 90, 87, 86), 144 => (144, 142, 140, 137), 196 => (196, 194, 187, 185),
- 93 => (93, 91, 90, 87), 145 => (145, 144, 140, 139), 197 => (197, 195, 193, 188),
- 94 => (94, 93, 89, 88), 146 => (146, 144, 143, 141), 198 => (198, 193, 190, 183),
- 95 => (95, 94, 90, 88), 147 => (147, 145, 143, 136), 199 => (199, 198, 195, 190),
- 96 => (96, 90, 87, 86), 148 => (148, 145, 143, 141), 200 => (200, 198, 197, 195),
- 97 => (97, 95, 93, 91), 149 => (149, 142, 140, 139), 201 => (201, 199, 198, 195),
- 98 => (98, 97, 91, 90), 150 => (150, 148, 147, 142), 202 => (202, 198, 196, 195),
- 99 => (99, 95, 94, 92), 151 => (151, 150, 149, 148), 203 => (203, 202, 196, 195),
- 100 => (100, 98, 93, 92), 152 => (152, 150, 149, 146), 204 => (204, 201, 200, 194),
- 101 => (101, 100, 95, 94), 153 => (153, 149, 148, 145), 205 => (205, 203, 200, 196),
- 102 => (102, 99, 97, 96), 154 => (154, 153, 149, 145), 206 => (206, 201, 197, 196),
- 103 => (103, 102, 99, 94), 155 => (155, 151, 150, 148), 207 => (207, 206, 201, 198),
- 104 => (104, 103, 94, 93), 156 => (156, 153, 151, 147), 208 => (208, 207, 205, 199),
- 105 => (105, 104, 99, 98), 157 => (157, 155, 152, 151), 209 => (209, 207, 206, 204),
- 106 => (106, 105, 101, 100), 158 => (158, 153, 152, 150), 210 => (210, 207, 206, 198),
- 107 => (107, 105, 99, 98), 159 => (159, 156, 153, 148), 211 => (211, 203, 201, 200),
- 108 => (108, 103, 97, 96), 160 => (160, 158, 157, 155), 212 => (212, 209, 208, 205),
- 109 => (109, 107, 105, 104), 161 => (161, 159, 158, 155), 213 => (213, 211, 208, 207),
- 110 => (110, 109, 106, 104), 162 => (162, 158, 155, 154), 214 => (214, 213, 211, 209),
- 111 => (111, 109, 107, 104), 163 => (163, 160, 157, 156), 215 => (215, 212, 210, 209),
- 112 => (112, 108, 106, 101), 164 => (164, 159, 158, 152), 216 => (216, 215, 213, 209),
- 113 => (113, 111, 110, 108), 165 => (165, 162, 157, 156), 217 => (217, 213, 212, 211),
- 114 => (114, 113, 112, 103), 166 => (166, 164, 163, 156), 218 => (218, 217, 211, 210),
- 115 => (115, 110, 108, 107), 167 => (167, 165, 163, 161), 219 => (219, 218, 215, 211),
- 116 => (116, 114, 111, 110), 168 => (168, 162, 159, 152), 220 => (220, 211, 210, 208),
- 117 => (117, 116, 115, 112), 169 => (169, 164, 163, 161), 221 => (221, 219, 215, 213),
- 118 => (118, 116, 113, 112), 170 => (170, 169, 166, 161), 222 => (222, 220, 217, 214),
- 119 => (119, 116, 111, 110), 171 => (171, 169, 166, 165), 223 => (223, 221, 219, 218),
- -- page 3
- 224 => (224, 222, 217, 212), 276 => (276, 275, 273, 270), 328 => (328, 323, 321, 319),
- 225 => (225, 224, 220, 215), 277 => (277, 274, 271, 265), 329 => (329, 326, 323, 321),
- 226 => (226, 223, 219, 216), 278 => (278, 277, 274, 273), 330 => (330, 328, 323, 322),
- 227 => (227, 223, 218, 217), 279 => (279, 278, 275, 274), 331 => (331, 329, 325, 321),
- 228 => (228, 226, 217, 216), 280 => (280, 278, 275, 271), 332 => (332, 325, 321, 320),
- 229 => (229, 228, 225, 219), 281 => (281, 280, 277, 272), 333 => (333, 331, 329, 325),
- 230 => (230, 224, 223, 222), 282 => (282, 278, 277, 272), 334 => (334, 333, 330, 327),
- 231 => (231, 229, 227, 224), 283 => (283, 278, 276, 271), 335 => (335, 333, 328, 325),
- 232 => (232, 228, 223, 221), 284 => (284, 279, 278, 276), 336 => (336, 335, 332, 329),
- 233 => (233, 232, 229, 224), 285 => (285, 280, 278, 275), 337 => (337, 336, 331, 327),
- 234 => (234, 232, 225, 223), 286 => (286, 285, 276, 271), 338 => (338, 336, 335, 332),
- 235 => (235, 234, 229, 226), 287 => (287, 285, 282, 281), 339 => (339, 332, 329, 323),
- 236 => (236, 229, 228, 226), 288 => (288, 287, 278, 277), 340 => (340, 337, 336, 329),
- 237 => (237, 236, 233, 230), 289 => (289, 286, 285, 277), 341 => (341, 336, 330, 327),
- 238 => (238, 237, 236, 233), 290 => (290, 288, 287, 285), 342 => (342, 341, 340, 331),
- 239 => (239, 238, 232, 227), 291 => (291, 286, 280, 279), 343 => (343, 338, 335, 333),
- 240 => (240, 237, 235, 232), 292 => (292, 291, 289, 285), 344 => (344, 338, 334, 333),
- 241 => (241, 237, 233, 232), 293 => (293, 292, 287, 282), 345 => (345, 343, 341, 337),
- 242 => (242, 241, 236, 231), 294 => (294, 292, 291, 285), 346 => (346, 344, 339, 335),
- 243 => (243, 242, 238, 235), 295 => (295, 293, 291, 290), 347 => (347, 344, 337, 336),
- 244 => (244, 243, 240, 235), 296 => (296, 292, 287, 285), 348 => (348, 344, 341, 340),
- 245 => (245, 244, 241, 239), 297 => (297, 296, 293, 292), 349 => (349, 347, 344, 343),
- 246 => (246, 245, 244, 235), 298 => (298, 294, 290, 287), 350 => (350, 340, 337, 336),
- 247 => (247, 245, 243, 238), 299 => (299, 295, 293, 288), 351 => (351, 348, 345, 343),
- 248 => (248, 238, 234, 233), 300 => (300, 290, 288, 287), 352 => (352, 346, 341, 339),
- 249 => (249, 248, 245, 242), 301 => (301, 299, 296, 292), 353 => (353, 349, 346, 344),
- 250 => (250, 247, 245, 240), 302 => (302, 297, 293, 290), 354 => (354, 349, 341, 340),
- 251 => (251, 249, 247, 244), 303 => (303, 297, 291, 290), 355 => (355, 354, 350, 349),
- 252 => (252, 251, 247, 241), 304 => (304, 303, 302, 293), 356 => (356, 349, 347, 346),
- 253 => (253, 252, 247, 246), 305 => (305, 303, 299, 298), 357 => (357, 355, 347, 346),
- 254 => (254, 253, 252, 247), 306 => (306, 305, 303, 299), 358 => (358, 351, 350, 344),
- 255 => (255, 253, 252, 250), 307 => (307, 305, 303, 299), 359 => (359, 358, 352, 350),
- 256 => (256, 254, 251, 246), 308 => (308, 306, 299, 293), 360 => (360, 359, 335, 334),
- 257 => (257, 255, 251, 250), 309 => (309, 307, 302, 299), 361 => (361, 360, 357, 354),
- 258 => (258, 254, 252, 249), 310 => (310, 309, 305, 302), 362 => (362, 360, 351, 344),
- 259 => (259, 257, 253, 249), 311 => (311, 308, 306, 304), 363 => (363, 362, 356, 355),
- 260 => (260, 253, 252, 250), 312 => (312, 307, 302, 301), 364 => (364, 363, 359, 352),
- 261 => (261, 257, 255, 254), 313 => (313, 312, 310, 306), 365 => (365, 360, 359, 356),
- 262 => (262, 258, 254, 253), 314 => (314, 311, 305, 300), 366 => (366, 362, 359, 352),
- 263 => (263, 261, 258, 252), 315 => (315, 314, 306, 305), 367 => (367, 365, 363, 358),
- 264 => (264, 263, 255, 254), 316 => (316, 309, 305, 304), 368 => (368, 361, 359, 351),
- 265 => (265, 263, 262, 260), 317 => (317, 315, 313, 310), 369 => (369, 367, 359, 358),
- 266 => (266, 265, 260, 259), 318 => (318, 313, 312, 310), 370 => (370, 368, 367, 365),
- 267 => (267, 264, 261, 259), 319 => (319, 318, 317, 308), 371 => (371, 369, 368, 363),
- 268 => (268, 267, 264, 258), 320 => (320, 319, 317, 316), 372 => (372, 369, 365, 357),
- 269 => (269, 268, 263, 262), 321 => (321, 319, 316, 314), 373 => (373, 371, 366, 365),
- 270 => (270, 267, 263, 260), 322 => (322, 321, 320, 305), 374 => (374, 369, 368, 366),
- 271 => (271, 265, 264, 260), 323 => (323, 322, 320, 313), 375 => (375, 374, 368, 367),
- 272 => (272, 270, 266, 263), 324 => (324, 321, 320, 318), 376 => (376, 371, 369, 368),
- 273 => (273, 272, 271, 266), 325 => (325, 323, 320, 315), 377 => (377, 376, 374, 369),
- 274 => (274, 272, 267, 265), 326 => (326, 325, 323, 316), 378 => (378, 374, 365, 363),
- 275 => (275, 266, 265, 264), 327 => (327, 325, 322, 319), 379 => (379, 375, 370, 369),
- -- page 4
- 380 => (380, 377, 374, 366), 432 => (432, 429, 428, 419), 484 => (484, 483, 482, 470),
- 381 => (381, 380, 379, 376), 433 => (433, 430, 428, 422), 485 => (485, 479, 469, 468),
- 382 => (382, 379, 375, 364), 434 => (434, 429, 423, 422), 486 => (486, 481, 478, 472),
- 383 => (383, 382, 378, 374), 435 => (435, 430, 426, 423), 487 => (487, 485, 483, 478),
- 384 => (384, 378, 369, 368), 436 => (436, 432, 431, 430), 488 => (488, 487, 485, 484),
- 385 => (385, 383, 381, 379), 437 => (437, 436, 435, 431), 489 => (489, 484, 483, 480),
- 386 => (386, 381, 380, 376), 438 => (438, 436, 432, 421), 490 => (490, 485, 483, 481),
- 387 => (387, 385, 379, 378), 439 => (439, 437, 436, 431), 491 => (491, 488, 485, 480),
- 388 => (388, 387, 385, 374), 440 => (440, 439, 437, 436), 492 => (492, 491, 485, 484),
- 389 => (389, 384, 380, 379), 441 => (441, 440, 433, 430), 493 => (493, 490, 488, 483),
- 390 => (390, 388, 380, 377), 442 => (442, 440, 437, 435), 494 => (494, 493, 489, 481),
- 391 => (391, 390, 389, 385), 443 => (443, 442, 437, 433), 495 => (495, 494, 486, 480),
- 392 => (392, 386, 382, 379), 444 => (444, 435, 432, 431), 496 => (496, 494, 491, 480),
- 393 => (393, 392, 391, 386), 445 => (445, 441, 439, 438), 497 => (497, 493, 488, 486),
- 394 => (394, 392, 387, 386), 446 => (446, 442, 439, 431), 498 => (498, 495, 489, 487),
- 395 => (395, 390, 389, 384), 447 => (447, 446, 441, 438), 499 => (499, 494, 493, 488),
- 396 => (396, 392, 390, 389), 448 => (448, 444, 442, 437), 500 => (500, 499, 494, 490),
- 397 => (397, 392, 387, 385), 449 => (449, 446, 440, 438), 501 => (501, 499, 497, 496),
- 398 => (398, 393, 392, 384), 450 => (450, 443, 438, 434), 502 => (502, 498, 497, 494),
- 399 => (399, 397, 390, 388), 451 => (451, 450, 441, 435), 503 => (503, 502, 501, 500),
- 400 => (400, 398, 397, 395), 452 => (452, 448, 447, 446), 504 => (504, 502, 490, 483),
- 401 => (401, 399, 392, 389), 453 => (453, 449, 447, 438), 505 => (505, 500, 497, 493),
- 402 => (402, 399, 398, 393), 454 => (454, 449, 445, 444), 506 => (506, 501, 494, 491),
- 403 => (403, 398, 395, 394), 455 => (455, 453, 449, 444), 507 => (507, 504, 501, 494),
- 404 => (404, 400, 398, 397), 456 => (456, 454, 445, 433), 508 => (508, 505, 500, 495),
- 405 => (405, 398, 397, 388), 457 => (457, 454, 449, 446), 509 => (509, 506, 502, 501),
- 406 => (406, 402, 397, 393), 458 => (458, 453, 448, 445), 510 => (510, 501, 500, 498),
- 407 => (407, 402, 400, 398), 459 => (459, 457, 454, 447), 511 => (511, 509, 503, 501),
- 408 => (408, 407, 403, 401), 460 => (460, 459, 455, 451), 512 => (512, 510, 507, 504),
- 409 => (409, 406, 404, 402), 461 => (461, 460, 455, 454), 513 => (513, 505, 503, 500),
- 410 => (410, 407, 406, 400), 462 => (462, 457, 451, 450), 514 => (514, 511, 509, 507),
- 411 => (411, 408, 401, 399), 463 => (463, 456, 455, 452), 515 => (515, 511, 508, 501),
- 412 => (412, 409, 404, 401), 464 => (464, 460, 455, 441), 516 => (516, 514, 511, 509),
- 413 => (413, 407, 406, 403), 465 => (465, 463, 462, 457), 517 => (517, 515, 507, 505),
- 414 => (414, 405, 401, 398), 466 => (466, 460, 455, 452), 518 => (518, 516, 515, 507),
- 415 => (415, 413, 411, 406), 467 => (467, 466, 461, 456), 519 => (519, 517, 511, 507),
- 416 => (416, 414, 411, 407), 468 => (468, 464, 459, 453), 520 => (520, 509, 507, 503),
- 417 => (417, 416, 414, 407), 469 => (469, 467, 464, 460), 521 => (521, 519, 514, 512),
- 418 => (418, 417, 415, 403), 470 => (470, 468, 462, 461), 522 => (522, 518, 509, 507),
- 419 => (419, 415, 414, 404), 471 => (471, 469, 468, 465), 523 => (523, 521, 517, 510),
- 420 => (420, 412, 410, 407), 472 => (472, 470, 469, 461), 524 => (524, 523, 519, 515),
- 421 => (421, 419, 417, 416), 473 => (473, 470, 467, 465), 525 => (525, 524, 521, 519),
- 422 => (422, 421, 416, 412), 474 => (474, 465, 463, 456), 526 => (526, 525, 521, 517),
- 423 => (423, 420, 418, 414), 475 => (475, 471, 467, 466), 527 => (527, 526, 520, 518),
- 424 => (424, 422, 417, 415), 476 => (476, 475, 468, 466), 528 => (528, 526, 522, 517),
- 425 => (425, 422, 421, 418), 477 => (477, 470, 462, 461), 529 => (529, 528, 525, 522),
- 426 => (426, 415, 414, 412), 478 => (478, 477, 474, 472), 530 => (530, 527, 523, 520),
- 427 => (427, 422, 421, 416), 479 => (479, 475, 472, 470), 531 => (531, 529, 525, 519),
- 428 => (428, 426, 425, 417), 480 => (480, 473, 467, 464), 532 => (532, 529, 528, 522),
- 429 => (429, 422, 421, 419), 481 => (481, 480, 472, 471), 533 => (533, 531, 530, 529),
- 430 => (430, 419, 417, 415), 482 => (482, 477, 476, 473), 534 => (534, 533, 529, 527),
- 431 => (431, 430, 428, 426), 483 => (483, 479, 477, 474), 535 => (535, 533, 529, 527),
- -- page 5
- 536 => (536, 533, 531, 529), 588 => (588, 577, 572, 571), 640 => (640, 638, 637, 626),
- 537 => (537, 536, 535, 527), 589 => (589, 586, 585, 579), 641 => (641, 640, 636, 622),
- 538 => (538, 537, 536, 533), 590 => (590, 588, 587, 578), 642 => (642, 636, 633, 632),
- 539 => (539, 535, 534, 529), 591 => (591, 587, 585, 582), 643 => (643, 641, 640, 632),
- 540 => (540, 537, 534, 529), 592 => (592, 591, 573, 568), 644 => (644, 634, 633, 632),
- 541 => (541, 537, 531, 528), 593 => (593, 588, 585, 584), 645 => (645, 641, 637, 634),
- 542 => (542, 540, 539, 533), 594 => (594, 586, 584, 583), 646 => (646, 635, 634, 633),
- 543 => (543, 538, 536, 532), 595 => (595, 594, 593, 586), 647 => (647, 646, 643, 642),
- 544 => (544, 538, 535, 531), 596 => (596, 592, 591, 590), 648 => (648, 647, 626, 625),
- 545 => (545, 539, 537, 532), 597 => (597, 588, 585, 583), 649 => (649, 648, 644, 638),
- 546 => (546, 545, 544, 538), 598 => (598, 597, 592, 591), 650 => (650, 644, 635, 632),
- 547 => (547, 543, 540, 534), 599 => (599, 593, 591, 590), 651 => (651, 646, 638, 637),
- 548 => (548, 545, 543, 538), 600 => (600, 599, 590, 589), 652 => (652, 647, 643, 641),
- 549 => (549, 546, 545, 533), 601 => (601, 600, 597, 589), 653 => (653, 646, 645, 643),
- 550 => (550, 546, 533, 529), 602 => (602, 596, 594, 591), 654 => (654, 649, 643, 640),
- 551 => (551, 550, 547, 542), 603 => (603, 600, 599, 597), 655 => (655, 653, 639, 638),
- 552 => (552, 550, 547, 532), 604 => (604, 600, 598, 589), 656 => (656, 646, 638, 637),
- 553 => (553, 550, 549, 542), 605 => (605, 600, 598, 595), 657 => (657, 656, 650, 649),
- 554 => (554, 551, 546, 543), 606 => (606, 602, 599, 591), 658 => (658, 651, 648, 646),
- 555 => (555, 551, 546, 545), 607 => (607, 600, 598, 595), 659 => (659, 657, 655, 644),
- 556 => (556, 549, 546, 540), 608 => (608, 606, 602, 585), 660 => (660, 657, 656, 648),
- 557 => (557, 552, 551, 550), 609 => (609, 601, 600, 597), 661 => (661, 657, 650, 649),
- 558 => (558, 553, 549, 544), 610 => (610, 602, 600, 599), 662 => (662, 659, 656, 650),
- 559 => (559, 557, 552, 550), 611 => (611, 609, 607, 601), 663 => (663, 655, 652, 649),
- 560 => (560, 554, 551, 549), 612 => (612, 607, 602, 598), 664 => (664, 662, 660, 649),
- 561 => (561, 558, 552, 550), 613 => (613, 609, 603, 594), 665 => (665, 661, 659, 654),
- 562 => (562, 560, 558, 551), 614 => (614, 613, 612, 607), 666 => (666, 664, 659, 656),
- 563 => (563, 561, 554, 549), 615 => (615, 614, 609, 608), 667 => (667, 664, 660, 649),
- 564 => (564, 563, 561, 558), 616 => (616, 614, 602, 597), 668 => (668, 658, 656, 651),
- 565 => (565, 564, 559, 554), 617 => (617, 612, 608, 607), 669 => (669, 667, 665, 664),
- 566 => (566, 564, 561, 560), 618 => (618, 615, 604, 598), 670 => (670, 669, 665, 664),
- 567 => (567, 563, 557, 556), 619 => (619, 614, 611, 610), 671 => (671, 669, 665, 662),
- 568 => (568, 558, 557, 551), 620 => (620, 619, 618, 611), 672 => (672, 667, 666, 661),
- 569 => (569, 568, 559, 557), 621 => (621, 616, 615, 609), 673 => (673, 666, 664, 663),
- 570 => (570, 563, 558, 552), 622 => (622, 612, 610, 605), 674 => (674, 671, 665, 660),
- 571 => (571, 569, 566, 561), 623 => (623, 614, 613, 612), 675 => (675, 674, 672, 669),
- 572 => (572, 571, 564, 560), 624 => (624, 617, 615, 612), 676 => (676, 675, 671, 664),
- 573 => (573, 569, 567, 563), 625 => (625, 620, 617, 613), 677 => (677, 674, 673, 669),
- 574 => (574, 569, 565, 560), 626 => (626, 623, 621, 613), 678 => (678, 675, 673, 663),
- 575 => (575, 572, 570, 569), 627 => (627, 622, 617, 613), 679 => (679, 676, 667, 661),
- 576 => (576, 573, 572, 563), 628 => (628, 626, 617, 616), 680 => (680, 679, 650, 645),
- 577 => (577, 575, 574, 569), 629 => (629, 627, 624, 623), 681 => (681, 678, 672, 670),
- 578 => (578, 562, 556, 555), 630 => (630, 628, 626, 623), 682 => (682, 681, 679, 675),
- 579 => (579, 572, 570, 567), 631 => (631, 625, 623, 617), 683 => (683, 682, 677, 672),
- 580 => (580, 579, 576, 574), 632 => (632, 629, 619, 613), 684 => (684, 681, 671, 666),
- 581 => (581, 575, 574, 568), 633 => (633, 632, 631, 626), 685 => (685, 684, 682, 681),
- 582 => (582, 579, 576, 571), 634 => (634, 631, 629, 627), 686 => (686, 684, 674, 673),
- 583 => (583, 581, 577, 575), 635 => (635, 631, 625, 621), 687 => (687, 682, 675, 673),
- 584 => (584, 581, 571, 570), 636 => (636, 632, 628, 623), 688 => (688, 682, 674, 669),
- 585 => (585, 583, 582, 577), 637 => (637, 636, 628, 623), 689 => (689, 686, 683, 681),
- 586 => (586, 584, 581, 579), 638 => (638, 637, 633, 632), 690 => (690, 687, 683, 680),
- 587 => (587, 586, 581, 576), 639 => (639, 636, 635, 629), 691 => (691, 689, 685, 678),
- -- page 6
- 692 => (692, 687, 686, 678), 725 => (725, 720, 719, 716), 758 => (758, 757, 746, 741),
- 693 => (693, 691, 685, 678), 726 => (726, 725, 722, 721), 759 => (759, 757, 756, 750),
- 694 => (694, 691, 681, 677), 727 => (727, 721, 719, 716), 760 => (760, 757, 747, 734),
- 695 => (695, 694, 691, 686), 728 => (728, 726, 725, 724), 761 => (761, 760, 759, 758),
- 696 => (696, 694, 686, 673), 729 => (729, 726, 724, 718), 762 => (762, 761, 755, 745),
- 697 => (697, 689, 685, 681), 730 => (730, 726, 715, 711), 763 => (763, 754, 749, 747),
- 698 => (698, 690, 689, 688), 731 => (731, 729, 725, 723), 764 => (764, 761, 759, 758),
- 699 => (699, 698, 689, 684), 732 => (732, 729, 728, 725), 765 => (765, 760, 755, 754),
- 700 => (700, 698, 695, 694), 733 => (733, 731, 726, 725), 766 => (766, 757, 747, 744),
- 701 => (701, 699, 697, 685), 734 => (734, 724, 721, 720), 767 => (767, 763, 760, 759),
- 702 => (702, 701, 699, 695), 735 => (735, 733, 728, 727), 768 => (768, 764, 751, 749),
- 703 => (703, 702, 696, 691), 736 => (736, 730, 728, 723), 769 => (769, 763, 762, 760),
- 704 => (704, 701, 699, 692), 737 => (737, 736, 733, 732), 770 => (770, 768, 765, 756),
- 705 => (705, 704, 698, 697), 738 => (738, 730, 729, 727), 771 => (771, 765, 756, 754),
- 706 => (706, 697, 695, 692), 739 => (739, 731, 723, 721), 772 => (772, 767, 766, 764),
- 707 => (707, 702, 699, 692), 740 => (740, 737, 728, 716), 773 => (773, 767, 765, 763),
- 708 => (708, 706, 704, 703), 741 => (741, 738, 733, 732), 774 => (774, 767, 760, 758),
- 709 => (709, 708, 706, 705), 742 => (742, 741, 738, 730), 775 => (775, 771, 769, 768),
- 710 => (710, 709, 696, 695), 743 => (743, 742, 731, 730), 776 => (776, 773, 764, 759),
- 711 => (711, 704, 703, 700), 744 => (744, 743, 733, 731), 777 => (777, 776, 767, 761),
- 712 => (712, 709, 708, 707), 745 => (745, 740, 738, 737), 778 => (778, 775, 762, 759),
- 713 => (713, 706, 703, 696), 746 => (746, 738, 733, 728), 779 => (779, 776, 771, 769),
- 714 => (714, 709, 707, 701), 747 => (747, 743, 741, 737), 780 => (780, 775, 772, 764),
- 715 => (715, 714, 711, 708), 748 => (748, 744, 743, 733), 781 => (781, 779, 765, 764),
- 716 => (716, 706, 705, 704), 749 => (749, 748, 743, 742), 782 => (782, 780, 779, 773),
- 717 => (717, 716, 710, 701), 750 => (750, 746, 741, 734), 783 => (783, 782, 776, 773),
- 718 => (718, 717, 716, 713), 751 => (751, 750, 748, 740), 784 => (784, 778, 775, 771),
- 719 => (719, 711, 710, 707), 752 => (752, 749, 732, 731), 785 => (785, 780, 776, 775),
- 720 => (720, 718, 712, 709), 753 => (753, 748, 745, 740), 786 => (786, 782, 780, 771),
- 721 => (721, 720, 713, 712), 754 => (754, 742, 740, 735), 1024 => (1024, 1015, 1002, 1001),
- 722 => (722, 721, 718, 707), 755 => (755, 754, 745, 743), 2048 => (2048, 2035, 2034, 2029),
- 723 => (723, 717, 710, 707), 756 => (756, 755, 747, 740), 4096 => (4096, 4095, 4081, 4069),
- 724 => (724, 719, 716, 711), 757 => (757, 756, 751, 750), others => (-1, -1, -1, -1)
- );
+ -- Compute the next state of the LFSR sequence
+ -- Uses the XNOR construction, so
+ -- "0000" is a valid state as per the usual startup state of an FPGA's registers.
+ -- "1111" is the unreachable/invalid/stable/locked-up state.
+ function lfsr (
+ state : std_logic_vector;
+ constant permit_locked_state : boolean := false)
+ return std_logic_vector;
-
- -- Compute the next state of the LFSR sequence
- -- Uses the XNOR construction, so
- -- "0000" is a valid state as per the usual startup state of an FPGA's registers.
- -- "1111" is the unreachable/invalid/stable/locked-up state.
function lfsr (
- state : std_logic_vector;
- constant permit_locked_state : boolean := false)
- return std_logic_vector;
-
- function lfsr (
- state : unsigned;
- constant permit_locked_state : boolean := false)
- return unsigned;
+ state : unsigned;
+ constant permit_locked_state : boolean := false)
+ return unsigned;
- -- Compute the state several steps ahead.
- function lfsr_advance (
+ -- Compute the state several steps ahead.
+ function lfsr_advance (
state : std_logic_vector;
constant by : natural;
constant permit_locked_state : boolean := false)
- return std_logic_vector;
+ return std_logic_vector;
- function lfsr_advance (
- state : unsigned;
- constant by : natural;
- constant permit_locked_state : boolean := false)
- return unsigned;
+ function lfsr_advance (
+ state : unsigned;
+ constant by : natural;
+ constant permit_locked_state : boolean := false)
+ return unsigned;
-end package lfsr_pkg;
+ end package lfsr_pkg;
package body lfsr_pkg is
- function lfsr (
- state : std_logic_vector;
- constant permit_locked_state : boolean := false
- )
- return std_logic_vector is
- variable current_state : std_logic_vector(state'length downto 1);
- variable tap : integer;
- variable bit0 : std_logic;
+ function lfsr (
+ state : std_logic_vector;
+ constant permit_locked_state : boolean := false
+ )
+ return std_logic_vector is
+ variable current_state : std_logic_vector(state'length downto 1);
+ variable tap : integer;
+ variable bit0 : std_logic;
begin -- function lfsr
- assert state'length >= 2
- report "LFSRs of length less than 2 are undefined"
- severity failure;
- assert xnor_taps(state'length)(0) = state'length
- report "LFSR taps for length " & to_string(state'length) & " are not defined in the package."
- severity failure;
- assert permit_locked_state or state /= (state'range => '1')
- report "lfsr state input in the invalid (locked up/stable) state of all '1's." severity warning;
- current_state := state; -- convert to slv with known indicies.
- bit0 := current_state(current_state'high);
- for idx in 1 to 3 loop
- tap := xnor_taps(state'length)(idx);
- if tap > 0 then
- bit0 := bit0 xor current_state(tap);
- end if;
- end loop; -- idx
- return current_state(current_state'high-1 downto current_state'low) & not bit0;
- end function lfsr;
+ assert state'length >= 2
+ report "LFSRs of length less than 2 are undefined"
+ severity failure;
+ assert xnor_taps(state'length)(0) = state'length
+ report "LFSR taps for length " & to_string(state'length) & " are not defined in the package."
+ severity failure;
+ assert permit_locked_state or state /= (state'range => '1')
+ report "lfsr state input in the invalid (locked up/stable) state of all '1's." severity warning;
+ current_state := state; -- convert to slv with known indicies.
+ bit0 := current_state(current_state'high);
+ for idx in 1 to 3 loop
+ tap := xnor_taps(state'length)(idx);
+ if tap > 0 then
+ bit0 := bit0 xor current_state(tap);
+ end if;
+ end loop; -- idx
+ return current_state(current_state'high-1 downto current_state'low) & not bit0;
+end function lfsr;
- function lfsr (
- state : unsigned;
- constant permit_locked_state : boolean := false)
- return unsigned is
- begin
- return unsigned(lfsr(std_logic_vector(state)));
- end function lfsr;
+function lfsr (
+ state : unsigned;
+ constant permit_locked_state : boolean := false)
+ return unsigned is
+ begin
+ return unsigned(lfsr(std_logic_vector(state)));
+end function lfsr;
- function lfsr_advance (
- state : std_logic_vector;
- constant by : natural;
- constant permit_locked_state : boolean := false)
- return std_logic_vector is
- variable next_state : std_logic_vector(state'range);
- begin -- function lfsr_advance
- next_state := state;
- -- should build a tree of XORs, that hopefully the compiler optimises down.
- for cnt in 1 to by loop
- next_state := lfsr(next_state, permit_locked_state);
- end loop; -- cnt
- return next_state;
- end function lfsr_advance;
+function lfsr_advance (
+ state : std_logic_vector;
+ constant by : natural;
+ constant permit_locked_state : boolean := false)
+ return std_logic_vector is
+ variable next_state : std_logic_vector(state'range);
+ begin -- function lfsr_advance
+ next_state := state;
+ -- should build a tree of XORs, that hopefully the compiler optimises down.
+ for cnt in 1 to by loop
+ next_state := lfsr(next_state, permit_locked_state);
+ end loop; -- cnt
+ return next_state;
+end function lfsr_advance;
- function lfsr_advance (
- state : unsigned;
- constant by : natural;
- constant permit_locked_state : boolean := false)
- return unsigned is
- begin
- return unsigned(lfsr_advance(std_logic_vector(state), by));
- end function lfsr_advance;
+function lfsr_advance (
+ state : unsigned;
+ constant by : natural;
+ constant permit_locked_state : boolean := false)
+ return unsigned is
+ begin
+ return unsigned(lfsr_advance(std_logic_vector(state), by));
+end function lfsr_advance;
end package body lfsr_pkg;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/misc_tools_pkg.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/misc_tools_pkg.vhd
index 59bd422b8f8d907d95aa64315d71d8133ced25ba..6640ada7adfb21998d7d8b07c283cd998902080e 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/misc_tools_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/misc_tools_pkg.vhd
@@ -1,492 +1,530 @@
--------------------------------------------------------------------------------
--- Title : Miscellaneous Tools Package
--- Project :
--------------------------------------------------------------------------------
--- File : misc_tools_pkg.vhd
--- Author : William Kamp
--- Company : High Performance Computing Research Lab, Auckland University of Technology
--- Created : 2015-10-13
--- Last update: 2018-07-10
--- Platform :
--- Standard : VHDL'2008
--------------------------------------------------------------------------------
--- Description:
--------------------------------------------------------------------------------
--- Copyright (c) 2015 High Performance Computing Research Lab, Auckland University of Technology
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2015-10-13 1.0 wkamp Created
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.common_types_pkg.all;
-
-package misc_tools_pkg is
-
- function wired_or (slv : std_logic_vector) return std_logic;
- function wired_and (slv : std_logic_vector) return std_logic;
- function shift_left (slv : std_logic_vector;
- constant amount : natural := 1;
- constant fill : std_logic := '-') return std_logic_vector;
- function shift_right (slv : std_logic_vector;
- constant amount : natural := 1;
- constant fill : std_logic := '-') return std_logic_vector;
-
- -- floor(log_b(n))
- function floor_log(val, base : positive)
- return natural;
-
- -- ceiling(log_b(n))
- function ceil_log(val, base : positive)
- return natural;
-
- -- floor(log2(n))
- function floor_log2(val : positive)
- return natural;
-
- -- ceiling(log2(n))
- function ceil_log2(val : natural)
- return natural;
-
- -- Round val up to the nearest multiple.
- function round_up (val : natural; multiple: natural := 1)
- return natural;
-
- -- Number of bits needed to represent a number n in binary
- function bit_width(val : natural)
- return natural;
-
- -- Number of bits needed to encode n items
- function encoding_width(val : positive)
- return natural;
-
- function power_of_2 (power : unsigned;
- constant len : natural)
- return unsigned;
-
- -- Returns the next power of two greater than or equal val
- function ceil_pow2 (val : natural)
- return natural;
-
- function is_pow_2 (val : natural)
- return boolean;
-
- function maximum (constant a : natural;
- constant b : natural)
- return natural;
-
- function bit_swap (slv : std_logic_vector;
- constant slice_width : natural := 1) -- size of the groups to swap. e.g swap order of bytes = 8.
- return std_logic_vector;
-
- function byte_swap(slv : std_logic_vector)
- return std_logic_vector;
-
- function byte_swap(slv : unsigned)
- return unsigned;
-
- -- Convert a one-hot vector into an unsigned value.
- function from_onehot(slv : std_logic_vector;
- allow_zero_hot : boolean := false)
- return unsigned;
-
- function to_onehot(val : unsigned;
- constant c_width : natural)
- return std_logic_vector;
-
- function count_ones (slv : std_logic_vector)
- return unsigned;
-
- function count_trailing_zeros (val : std_logic_vector)
- return unsigned;
-
- function count_leading_zeros (val : std_logic_vector)
- return unsigned;
-
- procedure p_sum_carry (
- a : in unsigned;
- b : in unsigned;
- carry_in : in std_logic := '0';
- sum_out : out unsigned;
- carry_out : out std_logic);
-
- function f_count (
- accum : signed;
- start : signed := "00";
- by : signed := "01";
- reset : std_logic := '0';
- cnt : std_logic := '0';
- by_1 : std_logic := '0'
- ) return signed;
-
- function f_count (
- accum : unsigned;
- start : integer := 0;
- by : integer := 1;
- cnt : std_logic := '0';
- by_1 : std_logic := '0';
- reset : std_logic := '0'
- ) return unsigned;
-
- function f_count (
- accum : unsigned;
- start : unsigned := "00";
- by : unsigned := "01";
- reset : std_logic := '0';
- cnt : std_logic := '0';
- by_1 : std_logic := '0'
- ) return unsigned;
-
-end package misc_tools_pkg;
-
-package body misc_tools_pkg is
-
- -- purpose: OR all bits together
- function wired_or (slv : std_logic_vector)
- return std_logic is
- variable ored : std_logic := '0';
- begin -- function wired_or
- if slv = (slv'range => '0') then
- return '0';
- else
- return '1';
- end if;
- end function wired_or;
-
- function wired_and (slv : std_logic_vector)
- return std_logic is
- variable ored : std_logic := '0';
- begin -- function wired_or
- if slv = (slv'range => '1') then
- return '1';
- else
- return '0';
- end if;
- end function wired_and;
-
- -- purpose: shift a std_logic_vector left an <amount> and shift in bits with value <fill>.
- function shift_left (slv : std_logic_vector;
- constant amount : natural := 1;
- constant fill : std_logic := '-')
- return std_logic_vector is
- begin
- return slv(slv'high-amount downto slv'low) & (amount-1 downto 0 => fill);
- end function shift_left;
-
- function shift_right (slv : std_logic_vector;
- constant amount : natural := 1;
- constant fill : std_logic := '-')
- return std_logic_vector is
- begin
- return (amount-1 downto 0 => fill) & slv(slv'high downto slv'low+amount);
- end function shift_right;
-
- function floor_log(val, base : positive)
- return natural is
- variable log, residual : natural;
- begin
- residual := val;
- log := 0;
- while residual > (base - 1) loop
- residual := residual / base;
- log := log + 1;
- end loop;
- return log;
- end function;
-
- function ceil_log(val, base : positive)
- return natural is
- variable log, residual : natural;
- begin
- residual := val - 1;
- log := 0;
- while residual > 0 loop
- residual := residual / base;
- log := log + 1;
- end loop;
- return log;
- end function;
-
- function floor_log2(val : positive)
- return natural is
- begin
- return floor_log(val, 2);
- end function;
-
- function ceil_log2(val : natural)
- return natural is
- begin
- if val < 1 then
- return 0;
- end if;
- return ceil_log(val, 2);
- end function;
-
- -- Round val up to the nearest multiple.
- function round_up (val : natural; multiple: natural := 1)
- return natural is
- begin
- return ((val + multiple - 1) / multiple) * multiple;
- end function;
-
- function bit_width(val : natural)
- return natural is
- begin
- if val = 0 then
- return 1;
- else
- return floor_log2(val) + 1;
- end if;
- end function;
-
- function encoding_width(val : positive)
- return natural is
- begin
- if val = 1 then
- return 1;
- else
- return ceil_log2(val);
- end if;
- end function;
-
- function power_of_2 (power : unsigned;
- constant len : natural)
- return unsigned is
- variable res : unsigned(len -1 downto 0) := (others => '0');
- begin
- res(to_integer(power)) := '1';
- return res;
- end function power_of_2;
-
- -- Returns the next power of two.
- function ceil_pow2 (val : natural)
- return natural is
- variable res : natural;
- begin -- function ceil_pow2
- if val = 0 then
- return 0;
- end if;
- res := 1;
- while res < val loop
- res := res * 2;
- end loop;
- return res;
- end function ceil_pow2;
-
- function is_pow_2 (
- val : natural)
- return boolean is
- variable test : natural;
- begin -- function is_pow_2
- test := val;
- while test mod 2 = 0 loop
- test := test/2;
- end loop;
- return test = 1;
- end function is_pow_2;
-
- function maximum (constant a : natural;
- constant b : natural)
- return natural is
- begin -- function maximum
- if a > b then
- return a;
- else
- return b;
- end if;
- end function maximum;
-
- function bit_swap (slv : std_logic_vector;
- constant slice_width : natural := 1) -- size of the groups to swap. e.g swap order of bytes = 8.
- return std_logic_vector is
- variable out_slv : std_logic_vector(slv'range);
- variable lo, hi : natural;
- begin
- assert slv'length mod slice_width = 0
- report "std_logic_vector input length (" & natural'image(slv'length) & ") is not a multiple of the slice_width (" & natural'image(slice_width) & ")."
- severity failure;
- for idx in 0 to slv'length/slice_width - 1 loop
- lo := out_slv'low + idx * slice_width;
- hi := slv'high - idx * slice_width;
- out_slv(lo+slice_width-1 downto lo) := slv(hi downto hi-slice_width+1);
- end loop;
- return out_slv;
- end function bit_swap;
-
- function byte_swap(slv : std_logic_vector)
- return std_logic_vector is
- begin
- return bit_swap(slv, 8);
- end function byte_swap;
-
- function byte_swap(slv : unsigned)
- return unsigned is
- begin
- return unsigned(bit_swap(std_logic_vector(slv), 8));
- end function byte_swap;
-
- constant c_OHOT_MASK : slv_64_a := (0 => x"AAAAAAAA_AAAAAAAA",
- 1 => x"CCCCCCCC_CCCCCCCC",
- 2 => x"F0F0F0F0_F0F0F0F0",
- 3 => x"FF00FF00_FF00FF00",
- 4 => x"FFFF0000_FFFF0000",
- 5 => x"FFFFFFFF_00000000");
-
- function from_onehot(slv : std_logic_vector;
- allow_zero_hot : boolean := false)
- return unsigned is
- variable val : unsigned(5 downto 0);
- variable mask : std_logic_vector(slv'range);
- begin
- assert slv'length < 65
- report "misc_tools_pkg.from_onehot function currently only supports up to 64 bit vectors."
- severity failure;
- assert slv /= (slv'range => '0') or allow_zero_hot
- report "Argument to misc_tools_pkg.from_onehot function is zero-hot."
- severity error;
- val := to_unsigned(0, val'length);
- for pow in val'range loop
- mask := c_OHOT_MASK(pow)(slv'range);
- val(pow) := wired_or(slv and mask);
- end loop;
- return val(ceil_log2(slv'length)-1 downto 0);
- end function;
-
- function to_onehot(
- val : unsigned;
- constant c_width : natural)
- return std_logic_vector is
- variable ohot : std_logic_vector(c_width-1 downto 0);
- begin
- for idx in ohot'range loop
- ohot(idx) := '1' when idx = val else '0';
- end loop;
- return ohot;
- end function;
-
- function count_ones (
- slv : std_logic_vector
- ) return unsigned is
- variable res : unsigned(ceil_log2(slv'length+1)-1 downto 0);
- variable slv_dt : std_logic_vector(slv'length-1 downto 0);
- variable mid : integer;
- begin
- slv_dt := slv;
- if slv_dt'length <= 1 then
- res := unsigned(slv_dt);
- else
- mid := slv_dt'length / 2;
- res := resize(count_ones(slv_dt(slv_dt'high downto mid)), res'length) +
- resize(count_ones(slv_dt(mid-1 downto slv_dt'low)), res'length);
- end if;
- return res;
- end function count_ones;
-
- function count_trailing_zeros (
- val : std_logic_vector)
- return unsigned is
- variable ohot : signed(val'length-1 downto 0);
- variable idx : unsigned(ceil_log2(val'length)-1 downto 0);
- begin -- function count_trailing_zeros
- ohot := signed(val) and -signed(val); -- AND itself with its two's complement.
- idx := unsigned(from_onehot(std_logic_vector(ohot), true));
- return idx;
- end function count_trailing_zeros;
-
- function count_leading_zeros (
- val : std_logic_vector)
- return unsigned is
- variable rev : std_logic_vector(val'length-1 downto 0);
- begin -- function count_leading_zeros
- for idx in rev'range loop
- rev(idx) := val(val'high - idx);
- end loop;
- return count_trailing_zeros(rev);
- end function count_leading_zeros;
-
-
- procedure p_sum_carry (
- a : in unsigned;
- b : in unsigned;
- carry_in : in std_logic := '0';
- sum_out : out unsigned;
- carry_out : out std_logic) is
- variable opa : unsigned(a'length+1 downto 0);
- variable opb : unsigned(b'length+1 downto 0);
- variable sum : unsigned(opa'range);
- begin -- procedure p_sum_carry
- opa := '0' & a & carry_in;
- opb := '0' & b & '1';
- sum := opa + opb;
- carry_out := sum(sum'high);
- sum_out := sum_out(sum_out'high-1 downto 1);
- end procedure p_sum_carry;
-
- function f_count (
- accum : signed;
- start : signed := "00";
- by : signed := "01";
- reset : std_logic := '0';
- cnt : std_logic := '0';
- by_1 : std_logic := '0'
- ) return signed is
- -- extra bit on top for sign bit and bottom for carry-in.
- variable fb : signed(accum'high + 1 downto 0);
- variable incr : signed(accum'high + 1 downto 0);
- variable sum : signed(accum'high + 1 downto 0);
- begin
- fb := resize(start, accum) & '1' when reset else accum & '1'; -- set lowest bit (half of carry_in) to '1'
- incr := resize(by , accum) & '0' when cnt else to_signed(0, accum) & '0';
- incr(0) := by_1; -- use the carry-in to give an additional independent increment input.
- sum := fb + incr;
- return sum(accum'high + 1 downto 1); -- shift by 1 to lose the carry-in bit.
- end function;
-
- function f_count (
- accum : unsigned;
- start : integer := 0;
- by : integer := 1;
- cnt : std_logic := '0';
- by_1 : std_logic := '0';
- reset : std_logic := '0'
- ) return unsigned is
- begin
- return unsigned(
- f_count(
- accum => signed(accum),
- start => to_signed(start, accum'length),
- by => to_signed(by, accum'length),
- reset => reset,
- cnt => cnt,
- by_1 => by_1
- )
- );
- end function;
-
- function f_count (
- accum : unsigned;
- start : unsigned := "00";
- by : unsigned := "01";
- reset : std_logic := '0';
- cnt : std_logic := '0';
- by_1 : std_logic := '0'
- ) return unsigned is
- begin
- return unsigned(
- f_count(
- accum => signed(accum),
- start => signed(start),
- by => signed(by),
- reset => reset,
- cnt => cnt,
- by_1 => by_1
- )
- );
- end function;
-
-end package body misc_tools_pkg;
+-------------------------------------------------------------------------------
+-- Title : Miscellaneous Tools Package
+-- Project :
+-------------------------------------------------------------------------------
+-- File : misc_tools_pkg.vhd
+-- Author : William Kamp
+-- Company : High Performance Computing Research Lab, Auckland University of Technology
+-- Created : 2015-10-13
+-- Last update: 2018-07-10
+-- Platform :
+-- Standard : VHDL'2008
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2015 High Performance Computing Research Lab, Auckland University of Technology
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2015-10-13 1.0 wkamp Created
+-------------------------------------------------------------------------------
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.common_types_pkg.all;
+
+package misc_tools_pkg is
+ function wired_or (slv : std_logic_vector) return std_logic;
+ function wired_and (slv : std_logic_vector) return std_logic;
+ function shift_left (
+ slv : std_logic_vector;
+ constant amount : natural := 1;
+ constant fill : std_logic := '-') return std_logic_vector;
+ function shift_right (
+ slv : std_logic_vector;
+ constant amount : natural := 1;
+ constant fill : std_logic := '-') return std_logic_vector;
+
+ -- floor(log_b(n))
+ function floor_log(
+ val, base : positive)
+ return natural;
+
+ -- ceiling(log_b(n))
+ function ceil_log(
+ val, base : positive)
+ return natural;
+
+ -- floor(log2(n))
+ function floor_log2(
+ val : positive)
+ return natural;
+
+ -- ceiling(log2(n))
+ function ceil_log2(
+ val : natural)
+ return natural;
+
+ -- Round val up to the nearest multiple.
+ function round_up (
+ val : natural; multiple: natural := 1)
+ return natural;
+
+ -- Number of bits needed to represent a number n in binary
+ function bit_width(
+ val : natural)
+ return natural;
+
+ -- Number of bits needed to encode n items
+ function encoding_width(
+ val : positive)
+ return natural;
+
+ function power_of_2 (
+ power : unsigned;
+ constant len : natural)
+ return unsigned;
+
+ -- Returns the next power of two greater than or equal val
+ function ceil_pow2 (
+ val : natural)
+ return natural;
+
+ function is_pow_2 (
+ val : natural)
+ return boolean;
+
+ function maximum (
+ constant a : natural;
+ constant b : natural)
+ return natural;
+
+ function bit_swap (
+ slv : std_logic_vector;
+ constant slice_width : natural := 1) -- size of the groups to swap. e.g swap order of bytes = 8.
+ return std_logic_vector;
+
+ function byte_swap(
+ slv : std_logic_vector)
+ return std_logic_vector;
+
+ function byte_swap(
+ slv : unsigned)
+ return unsigned;
+
+ -- Convert a one-hot vector into an unsigned value.
+ function from_onehot(
+ slv : std_logic_vector;
+ allow_zero_hot : boolean := false)
+ return unsigned;
+
+ function to_onehot(
+ val : unsigned;
+ constant c_width : natural)
+ return std_logic_vector;
+
+ function count_ones (
+ slv : std_logic_vector)
+ return unsigned;
+
+ function count_trailing_zeros (
+ val : std_logic_vector)
+ return unsigned;
+
+ function count_leading_zeros (
+ val : std_logic_vector)
+ return unsigned;
+
+ procedure p_sum_carry (
+ a : in unsigned;
+ b : in unsigned;
+ carry_in : in std_logic := '0';
+ sum_out : out unsigned;
+ carry_out : out std_logic);
+
+ function f_count (
+ accum : signed;
+ start : signed := "00";
+ by : signed := "01";
+ reset : std_logic := '0';
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0'
+ ) return signed;
+
+ function f_count (
+ accum : unsigned;
+ start : integer := 0;
+ by : integer := 1;
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0';
+ reset : std_logic := '0'
+ ) return unsigned;
+
+ function f_count (
+ accum : unsigned;
+ start : unsigned := "00";
+ by : unsigned := "01";
+ reset : std_logic := '0';
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0'
+ ) return unsigned;
+
+ end package misc_tools_pkg;
+
+package body misc_tools_pkg is
+
+ -- purpose: OR all bits together
+ function wired_or (
+ slv : std_logic_vector)
+ return std_logic is
+ variable ored : std_logic := '0';
+ begin -- function wired_or
+ if slv = (slv'range => '0') then
+ return '0';
+ else
+ return '1';
+ end if;
+ end function wired_or;
+
+ function wired_and (
+ slv : std_logic_vector)
+ return std_logic is
+ variable ored : std_logic := '0';
+ begin -- function wired_or
+ if slv = (slv'range => '1') then
+ return '1';
+ else
+ return '0';
+ end if;
+ end function wired_and;
+
+ -- purpose: shift a std_logic_vector left an <amount> and shift in bits with value <fill>.
+ function shift_left (
+ slv : std_logic_vector;
+ constant amount : natural := 1;
+ constant fill : std_logic := '-')
+ return std_logic_vector is
+ begin
+ return slv(slv'high-amount downto slv'low) & (amount-1 downto 0 => fill);
+ end function shift_left;
+
+ function shift_right (
+ slv : std_logic_vector;
+ constant amount : natural := 1;
+ constant fill : std_logic := '-')
+ return std_logic_vector is
+ begin
+ return (amount-1 downto 0 => fill) & slv(slv'high downto slv'low+amount);
+ end function shift_right;
+
+ function floor_log(
+ val, base : positive)
+ return natural is
+ variable log, residual : natural;
+ begin
+ residual := val;
+ log := 0;
+ while residual > (base - 1) loop
+ residual := residual / base;
+ log := log + 1;
+ end loop;
+ return log;
+ end function;
+
+ function ceil_log(
+ val, base : positive)
+ return natural is
+ variable log, residual : natural;
+ begin
+ residual := val - 1;
+ log := 0;
+ while residual > 0 loop
+ residual := residual / base;
+ log := log + 1;
+ end loop;
+ return log;
+ end function;
+
+ function floor_log2(
+ val : positive)
+ return natural is
+ begin
+ return floor_log(val, 2);
+ end function;
+
+ function ceil_log2(
+ val : natural)
+ return natural is
+ begin
+ if val < 1 then
+ return 0;
+ end if;
+ return ceil_log(val, 2);
+ end function;
+
+ -- Round val up to the nearest multiple.
+ function round_up (
+ val : natural; multiple: natural := 1)
+ return natural is
+ begin
+ return ((val + multiple - 1) / multiple) * multiple;
+ end function;
+
+ function bit_width(
+ val : natural)
+ return natural is
+ begin
+ if val = 0 then
+ return 1;
+ else
+ return floor_log2(val) + 1;
+ end if;
+ end function;
+
+ function encoding_width(
+ val : positive)
+ return natural is
+ begin
+ if val = 1 then
+ return 1;
+ else
+ return ceil_log2(val);
+ end if;
+ end function;
+
+ function power_of_2 (
+ power : unsigned;
+ constant len : natural)
+ return unsigned is
+ variable res : unsigned(len - 1 downto 0) := (others => '0');
+ begin
+ res(to_integer(power)) := '1';
+ return res;
+ end function power_of_2;
+
+ -- Returns the next power of two.
+ function ceil_pow2 (
+ val : natural)
+ return natural is
+ variable res : natural;
+ begin -- function ceil_pow2
+ if val = 0 then
+ return 0;
+ end if;
+ res := 1;
+ while res < val loop
+ res := res * 2;
+ end loop;
+ return res;
+ end function ceil_pow2;
+
+ function is_pow_2 (
+ val : natural)
+ return boolean is
+ variable test : natural;
+ begin -- function is_pow_2
+ test := val;
+ while test mod 2 = 0 loop
+ test := test / 2;
+ end loop;
+ return test = 1;
+ end function is_pow_2;
+
+ function maximum (
+ constant a : natural;
+ constant b : natural)
+ return natural is
+ begin -- function maximum
+ if a > b then
+ return a;
+ else
+ return b;
+ end if;
+ end function maximum;
+
+ function bit_swap (
+ slv : std_logic_vector;
+ constant slice_width : natural := 1) -- size of the groups to swap. e.g swap order of bytes = 8.
+ return std_logic_vector is
+ variable out_slv : std_logic_vector(slv'range);
+ variable lo, hi : natural;
+ begin
+ assert slv'length mod slice_width = 0
+ report "std_logic_vector input length (" & natural'image(slv'length) & ") is not a multiple of the slice_width (" & natural'image(slice_width) & ")."
+ severity failure;
+ for idx in 0 to slv'length / slice_width - 1 loop
+ lo := out_slv'low + idx * slice_width;
+ hi := slv'high - idx * slice_width;
+ out_slv(lo + slice_width - 1 downto lo) := slv(hi downto hi - slice_width + 1);
+ end loop;
+ return out_slv;
+ end function bit_swap;
+
+ function byte_swap(
+ slv : std_logic_vector)
+ return std_logic_vector is
+ begin
+ return bit_swap(slv, 8);
+ end function byte_swap;
+
+ function byte_swap(
+ slv : unsigned)
+ return unsigned is
+ begin
+ return unsigned(bit_swap(std_logic_vector(slv), 8));
+ end function byte_swap;
+
+ constant c_OHOT_MASK : slv_64_a := (
+ 0 => x"AAAAAAAA_AAAAAAAA",
+ 1 => x"CCCCCCCC_CCCCCCCC",
+ 2 => x"F0F0F0F0_F0F0F0F0",
+ 3 => x"FF00FF00_FF00FF00",
+ 4 => x"FFFF0000_FFFF0000",
+ 5 => x"FFFFFFFF_00000000");
+
+ function from_onehot(
+ slv : std_logic_vector;
+ allow_zero_hot : boolean := false)
+ return unsigned is
+ variable val : unsigned(5 downto 0);
+ variable mask : std_logic_vector(slv'range);
+ begin
+ assert slv'length < 65
+ report "misc_tools_pkg.from_onehot function currently only supports up to 64 bit vectors."
+ severity failure;
+ assert slv /= (slv'range => '0') or allow_zero_hot
+ report "Argument to misc_tools_pkg.from_onehot function is zero-hot."
+ severity error;
+ val := to_unsigned(0, val'length);
+ for pow in val'range loop
+ mask := c_OHOT_MASK(pow)(slv'range);
+ val(pow) := wired_or(slv and mask);
+ end loop;
+ return val(ceil_log2(slv'length)-1 downto 0);
+ end function;
+
+ function to_onehot(
+ val : unsigned;
+ constant c_width : natural)
+ return std_logic_vector is
+ variable ohot : std_logic_vector(c_width - 1 downto 0);
+ begin
+ for idx in ohot'range loop
+ ohot(idx) := '1' when idx = val else '0';
+ end loop;
+ return ohot;
+ end function;
+
+ function count_ones (
+ slv : std_logic_vector
+ ) return unsigned is
+ variable res : unsigned(ceil_log2(slv'length+1)-1 downto 0);
+ variable slv_dt : std_logic_vector(slv'length - 1 downto 0);
+ variable mid : integer;
+ begin
+ slv_dt := slv;
+ if slv_dt'length <= 1 then
+ res := unsigned(slv_dt);
+ else
+ mid := slv_dt'length / 2;
+ res := resize(count_ones(slv_dt(slv_dt'high downto mid)), res'length) +
+ resize(count_ones(slv_dt(mid - 1 downto slv_dt'low)), res'length);
+ end if;
+ return res;
+ end function count_ones;
+
+ function count_trailing_zeros (
+ val : std_logic_vector)
+ return unsigned is
+ variable ohot : signed(val'length-1 downto 0);
+ variable idx : unsigned(ceil_log2(val'length) - 1 downto 0);
+ begin -- function count_trailing_zeros
+ ohot := signed(val) and - signed(val); -- AND itself with its two's complement.
+ idx := unsigned(from_onehot(std_logic_vector(ohot), true));
+ return idx;
+ end function count_trailing_zeros;
+
+ function count_leading_zeros (
+ val : std_logic_vector)
+ return unsigned is
+ variable rev : std_logic_vector(val'length-1 downto 0);
+ begin -- function count_leading_zeros
+ for idx in rev'range loop
+ rev(idx) := val(val'high - idx);
+ end loop;
+ return count_trailing_zeros(rev);
+ end function count_leading_zeros;
+
+ procedure p_sum_carry (
+ a : in unsigned;
+ b : in unsigned;
+ carry_in : in std_logic := '0';
+ sum_out : out unsigned;
+ carry_out : out std_logic) is
+ variable opa : unsigned(a'length + 1 downto 0);
+ variable opb : unsigned(b'length + 1 downto 0);
+ variable sum : unsigned(opa'range);
+ begin -- procedure p_sum_carry
+ opa := '0' & a & carry_in;
+ opb := '0' & b & '1';
+ sum := opa + opb;
+ carry_out := sum(sum'high);
+ sum_out := sum_out(sum_out'high - 1 downto 1);
+ end procedure p_sum_carry;
+
+ function f_count (
+ accum : signed;
+ start : signed := "00";
+ by : signed := "01";
+ reset : std_logic := '0';
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0'
+ ) return signed is
+ -- extra bit on top for sign bit and bottom for carry-in.
+ variable fb : signed(accum'high + 1 downto 0);
+ variable incr : signed(accum'high + 1 downto 0);
+ variable sum : signed(accum'high + 1 downto 0);
+ begin
+ fb := resize(start, accum) & '1' when reset else accum & '1'; -- set lowest bit (half of carry_in) to '1'
+ incr := resize(by , accum) & '0' when cnt else to_signed(0, accum) & '0';
+ incr(0) := by_1; -- use the carry-in to give an additional independent increment input.
+ sum := fb + incr;
+ return sum(accum'high + 1 downto 1); -- shift by 1 to lose the carry-in bit.
+ end function;
+
+ function f_count (
+ accum : unsigned;
+ start : integer := 0;
+ by : integer := 1;
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0';
+ reset : std_logic := '0'
+ ) return unsigned is
+ begin
+ return unsigned(
+ f_count(
+ accum => signed(accum),
+ start => to_signed(start, accum'length),
+ by => to_signed(by, accum'length),
+ reset => reset,
+ cnt => cnt,
+ by_1 => by_1
+ )
+ );
+ end function;
+
+ function f_count (
+ accum : unsigned;
+ start : unsigned := "00";
+ by : unsigned := "01";
+ reset : std_logic := '0';
+ cnt : std_logic := '0';
+ by_1 : std_logic := '0'
+ ) return unsigned is
+ begin
+ return unsigned(
+ f_count(
+ accum => signed(accum),
+ start => signed(start),
+ by => signed(by),
+ reset => reset,
+ cnt => cnt,
+ by_1 => by_1
+ )
+ );
+ end function;
+
+ end package body misc_tools_pkg;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/pipeline_delay_ram.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/pipeline_delay_ram.vhd
index c5d5c17348280df94d7e869c95f15f866af18732..535fe810dca4af414de2e91d41c46571cb859ec2 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/pipeline_delay_ram.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/pipeline_delay_ram.vhd
@@ -23,144 +23,139 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
library work;
-use work.misc_tools_pkg.all; -- ceil_log2
+ use work.misc_tools_pkg.all; -- ceil_log2
library work;
-use work.lfsr_pkg.all; -- lfsr, lfsr_advance
+ use work.lfsr_pkg.all; -- lfsr, lfsr_advance
entity pipeline_delay_ram is
-
- generic (
- g_CYCLES_DELAY : natural;
- g_FORCE_USE_FLOPS : boolean := false; -- Implement the delay using only FLOPs.
- g_FLOPS_BEFORE_RAM : natural := 0; -- number of input flops.
- g_FLOPS_AFTER_RAM : natural := 0 -- number of output flops.
- );
-
- port (
- i_clk : in std_logic;
- i_clk_ena : in std_logic := '1';
- i_bus : in std_logic_vector;
- i_bus_vld : in std_logic := '1';
- o_bus_stop : out std_logic;
- o_bus : out std_logic_vector;
- o_bus_vld : out std_logic;
- i_bus_stop : in std_logic := '0'
- );
-
+ generic (
+ g_CYCLES_DELAY : natural;
+ g_FORCE_USE_FLOPS : boolean := false; -- Implement the delay using only FLOPs.
+ g_FLOPS_BEFORE_RAM : natural := 0; -- number of input flops.
+ g_FLOPS_AFTER_RAM : natural := 0 -- number of output flops.
+ );
+ port (
+ i_clk : in std_logic;
+ i_clk_ena : in std_logic := '1';
+ i_bus : in std_logic_vector;
+ i_bus_vld : in std_logic := '1';
+ o_bus_stop : out std_logic;
+ o_bus : out std_logic_vector;
+ o_bus_vld : out std_logic;
+ i_bus_stop : in std_logic := '0'
+ );
end entity pipeline_delay_ram;
architecture rtl of pipeline_delay_ram is
+ constant c_RAM_CYCLES : integer := g_CYCLES_DELAY - g_FLOPS_BEFORE_RAM - g_FLOPS_AFTER_RAM;
- constant c_RAM_CYCLES : integer := g_CYCLES_DELAY - g_FLOPS_BEFORE_RAM - g_FLOPS_AFTER_RAM;
-
- type t_delay is array (natural range <>) of std_logic_vector(i_bus'range);
+ type t_delay is array (natural range <>) of std_logic_vector(i_bus'range);
- signal delay_line : t_delay(g_CYCLES_DELAY downto 0);
- signal delay_line_vld : std_logic_vector(g_CYCLES_DELAY downto 0);
-
- function f_ASRR (constant FORCE_USE_FLOPS : boolean) return string is
- begin
- if FORCE_USE_FLOPS then
- return "off";
- end if;
- return "on";
- end function;
+ signal delay_line : t_delay(g_CYCLES_DELAY downto 0);
+ signal delay_line_vld : std_logic_vector(g_CYCLES_DELAY downto 0);
- -- Prevent large pipelines from going into memory-based altshift_taps, since that won't take advantage of Hyper-Registers
- attribute altera_attribute : string;
- attribute altera_attribute of delay_line : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION " & f_ASRR(g_FORCE_USE_FLOPS);
- attribute altera_attribute of delay_line_vld : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION " & f_ASRR(g_FORCE_USE_FLOPS);
+ function f_ASRR (constant FORCE_USE_FLOPS : boolean) return string is
+ begin
+ if FORCE_USE_FLOPS then
+ return "off";
+ end if;
+ return "on";
+ end function;
+ -- Prevent large pipelines from going into memory-based altshift_taps, since that won't take advantage of Hyper-Registers
+ attribute altera_attribute : string;
+ attribute altera_attribute of delay_line : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION " & f_ASRR(g_FORCE_USE_FLOPS);
+ attribute altera_attribute of delay_line_vld : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION " & f_ASRR(g_FORCE_USE_FLOPS);
begin -- architecture rtl
-
- o_bus_stop <= i_bus_stop;
-
- -- Here we implement a zero delay.
- delay_line(0) <= i_bus;
- delay_line_vld(0) <= i_bus_vld;
- o_bus <= delay_line(g_CYCLES_DELAY);
- o_bus_vld <= delay_line_vld(g_CYCLES_DELAY) and i_clk_ena;
-
- -- Here delays greater than or equal to 4 using a RAM.
- G_DELAY : if c_RAM_CYCLES >= 4 and not g_FORCE_USE_FLOPS generate
- signal wr_addr : unsigned(ceil_log2(c_RAM_CYCLES)-1 downto 0) := (others => '0');
- signal rd_addr : unsigned(wr_addr'range) := (others => '0');
-
- signal wr_data : std_logic_vector(i_bus'range);
- signal wr_vld : std_logic;
- signal rd_vld : std_logic;
- signal rd_data : std_logic_vector(wr_data'range);
+ o_bus_stop <= i_bus_stop;
+
+ -- Here we implement a zero delay.
+ delay_line(0) <= i_bus;
+ delay_line_vld(0) <= i_bus_vld;
+ o_bus <= delay_line(g_CYCLES_DELAY);
+ o_bus_vld <= delay_line_vld(g_CYCLES_DELAY) and i_clk_ena;
+
+ -- Here delays greater than or equal to 4 using a RAM.
+ G_DELAY : if c_RAM_CYCLES >= 4 and not g_FORCE_USE_FLOPS generate
+ signal wr_addr : unsigned(ceil_log2(c_RAM_CYCLES) - 1 downto 0) := (others => '0');
+ signal rd_addr : unsigned(wr_addr'range) := (others => '0');
+
+ signal wr_data : std_logic_vector(i_bus'range);
+ signal wr_vld : std_logic;
+ signal rd_vld : std_logic;
+ signal rd_data : std_logic_vector(wr_data'range);
begin
- P_ADDR_GEN : process (i_clk) is
- begin
- if rising_edge(i_clk) then
- if i_clk_ena then
- -- Note that in using an LFSR one address (highest address) in RAM goes unused!
- wr_addr <= lfsr(wr_addr);
- rd_addr <= lfsr_advance(wr_addr, 2**wr_addr'length - (c_RAM_CYCLES - 2));
- -- minus 2 for RAM latency.
-
- if g_FLOPS_BEFORE_RAM > 0 then
- delay_line(g_FLOPS_BEFORE_RAM downto 1) <= delay_line(g_FLOPS_BEFORE_RAM-1 downto 0);
- end if;
-
- -- data_vld delay line implemented in flops (may be converted to alt-shift-taps)
- -- so that it can be used as a write_enable and read_enable for the data RAM.
- -- This is done to reduce the dynamic power of the RAM by disabling the address
- -- logic when it is not needed.
- delay_line_vld(g_CYCLES_DELAY downto 1) <= delay_line_vld(g_CYCLES_DELAY-1 downto 0);
- end if;
- assert i_clk_ena report "i_clk_ena is only currently supported with g_FORCE_USE_FLOPS = true. To fix E_SDP_DATA_RAM needs a clk_enable port added." severity failure;
- end if;
- end process;
-
- wr_data <= delay_line(g_FLOPS_BEFORE_RAM);
- wr_vld <= delay_line_vld(g_FLOPS_BEFORE_RAM) and i_clk_ena;
- rd_vld <= delay_line_vld(g_FLOPS_BEFORE_RAM+c_RAM_CYCLES-2); -- minus 2 for RAM latency.
-
- E_SDP_DATA_RAM : entity work.sdp_ram
- generic map (
- g_REG_OUTPUT => true) -- [boolean]
- port map (
- i_clk => i_clk, -- [std_logic]
- i_clk_reset => '0', -- [std_logic]
- i_wr_addr => wr_addr, -- [unsigned]
- i_wr_en => wr_vld, -- [std_logic]
- i_wr_data => wr_data, -- [std_logic_vector]
- i_rd_addr => rd_addr, -- [unsigned]
- i_rd_en => rd_vld, -- [std_logic]
- o_rd_data => rd_data); -- [std_logic_vector]
-
- delay_line(g_FLOPS_BEFORE_RAM+c_RAM_CYCLES) <= rd_data;
+ P_ADDR_GEN : process (i_clk) is
+ begin
+ if rising_edge(i_clk) then
+ if i_clk_ena then
+ -- Note that in using an LFSR one address (highest address) in RAM goes unused!
+ wr_addr <= lfsr(wr_addr);
+ rd_addr <= lfsr_advance(wr_addr, 2 ** wr_addr'length - (c_RAM_CYCLES - 2));
+ -- minus 2 for RAM latency.
+
+ if g_FLOPS_BEFORE_RAM > 0 then
+ delay_line(g_FLOPS_BEFORE_RAM downto 1) <= delay_line(g_FLOPS_BEFORE_RAM - 1 downto 0);
+ end if;
+
+ -- data_vld delay line implemented in flops (may be converted to alt-shift-taps)
+ -- so that it can be used as a write_enable and read_enable for the data RAM.
+ -- This is done to reduce the dynamic power of the RAM by disabling the address
+ -- logic when it is not needed.
+ delay_line_vld(g_CYCLES_DELAY downto 1) <= delay_line_vld(g_CYCLES_DELAY - 1 downto 0);
+ end if;
+ assert i_clk_ena report "i_clk_ena is only currently supported with g_FORCE_USE_FLOPS = true. to fix E_SDP_DATA_RAM needs a clk_enable port added." severity failure;
+ end if;
+ end process;
+
+ wr_data <= delay_line(g_FLOPS_BEFORE_RAM);
+ wr_vld <= delay_line_vld(g_FLOPS_BEFORE_RAM) and i_clk_ena;
+ rd_vld <= delay_line_vld(g_FLOPS_BEFORE_RAM + c_RAM_CYCLES - 2); -- minus 2 for RAM latency.
+
+ E_SDP_DATA_RAM : entity work.sdp_ram
+ generic map (
+ g_REG_OUTPUT => true) -- [boolean]
+ port map (
+ i_clk => i_clk, -- [std_logic]
+ i_clk_reset => '0', -- [std_logic]
+ i_wr_addr => wr_addr, -- [unsigned]
+ i_wr_en => wr_vld, -- [std_logic]
+ i_wr_data => wr_data, -- [std_logic_vector]
+ i_rd_addr => rd_addr, -- [unsigned]
+ i_rd_en => rd_vld, -- [std_logic]
+ o_rd_data => rd_data); -- [std_logic_vector]
+
+ delay_line(g_FLOPS_BEFORE_RAM + c_RAM_CYCLES) <= rd_data;
P_OUT_FLOPS : process (i_clk) is
begin
- if rising_edge(i_clk) then
- if i_clk_ena then
- if g_FLOPS_AFTER_RAM > 0 then
- delay_line(g_CYCLES_DELAY downto g_FLOPS_BEFORE_RAM+c_RAM_CYCLES+1) <=
- delay_line(g_CYCLES_DELAY-1 downto g_FLOPS_BEFORE_RAM+c_RAM_CYCLES);
- end if;
- end if;
+ if rising_edge(i_clk) then
+ if i_clk_ena then
+ if g_FLOPS_AFTER_RAM > 0 then
+ delay_line(g_CYCLES_DELAY downto g_FLOPS_BEFORE_RAM + c_RAM_CYCLES + 1) <=
+ delay_line(g_CYCLES_DELAY-1 downto g_FLOPS_BEFORE_RAM+c_RAM_CYCLES);
+ end if;
end if;
+ end if;
end process;
- -- Here short delays using just flops.
- elsif g_CYCLES_DELAY > 0 generate
- P_DELAY : process (i_clk) is
- begin
+ -- Here short delays using just flops.
+ elsif g_CYCLES_DELAY > 0 generate
+
+ P_DELAY : process (i_clk) is
+ begin
if rising_edge(i_clk) then
- if i_clk_ena then
- delay_line(g_CYCLES_DELAY downto 1) <= delay_line(g_CYCLES_DELAY-1 downto 0);
- delay_line_vld(g_CYCLES_DELAY downto 1) <= delay_line_vld(g_CYCLES_DELAY-1 downto 0);
- end if;
+ if i_clk_ena then
+ delay_line(g_CYCLES_DELAY downto 1) <= delay_line(g_CYCLES_DELAY - 1 downto 0);
+ delay_line_vld(g_CYCLES_DELAY downto 1) <= delay_line_vld(g_CYCLES_DELAY - 1 downto 0);
+ end if;
end if;
- end process;
- end generate;
+ end process;
+ end generate;
-end architecture rtl;
+ end architecture rtl;
diff --git a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/sdp_ram.vhd b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/sdp_ram.vhd
index 53eade3f30bf0cfbbffed4b5e9cd80a6ad66b576..eb390177313bc37ad41a43c31df11817d56e0ec9 100755
--- a/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/sdp_ram.vhd
+++ b/applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/sdp_ram.vhd
@@ -1,66 +1,64 @@
--------------------------------------------------------------------------------
---
--- Copyright 2023
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
--- Author: R. van der Walle
--- Purpose: Wrapper for a simple dual port RAM
-
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-library common_lib;
- use common_lib.common_mem_pkg.all;
-
-entity sdp_ram is
- generic (
- g_REG_OUTPUT : boolean := false;
- g_INIT_FILE : string := "UNUSED"
- );
- port (
- i_clk : in std_logic;
- i_clk_reset : in std_logic;
- i_wr_addr : in unsigned;
- i_wr_en : in std_logic;
- i_wr_data : in std_logic_vector;
- i_rd_addr : in unsigned;
- i_rd_en : in std_logic;
- o_rd_data : out std_logic_vector
- );
-end entity sdp_ram;
-
-architecture str of sdp_ram is
-
- constant c_ram : t_c_mem := (c_mem_ram_rd_latency, i_wr_addr'length, i_wr_data'length, 2**i_wr_addr'length, '0');
-
-begin
- u_common_ram_r_w : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram,
- g_init_file => g_INIT_FILE
- )
- port map (
- rst => i_clk_reset,
- clk => i_clk,
- wr_en => i_wr_en,
- wr_adr => std_logic_vector(i_wr_addr),
- wr_dat => i_wr_data,
- rd_en => i_rd_en,
- rd_adr => std_logic_vector(i_rd_addr),
- rd_dat => o_rd_data
- );
-end str;
+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Wrapper for a simple dual port RAM
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library common_lib;
+ use common_lib.common_mem_pkg.all;
+
+entity sdp_ram is
+ generic (
+ g_REG_OUTPUT : boolean := false;
+ g_INIT_FILE : string := "UNUSED"
+ );
+ port (
+ i_clk : in std_logic;
+ i_clk_reset : in std_logic;
+ i_wr_addr : in unsigned;
+ i_wr_en : in std_logic;
+ i_wr_data : in std_logic_vector;
+ i_rd_addr : in unsigned;
+ i_rd_en : in std_logic;
+ o_rd_data : out std_logic_vector
+ );
+end entity sdp_ram;
+
+architecture str of sdp_ram is
+ constant c_ram : t_c_mem := (c_mem_ram_rd_latency, i_wr_addr'length, i_wr_data'length, 2 ** i_wr_addr'length, '0');
+begin
+ u_common_ram_r_w : entity common_lib.common_ram_r_w
+ generic map (
+ g_ram => c_ram,
+ g_init_file => g_INIT_FILE
+ )
+ port map (
+ rst => i_clk_reset,
+ clk => i_clk,
+ wr_en => i_wr_en,
+ wr_adr => std_logic_vector(i_wr_addr),
+ wr_dat => i_wr_data,
+ rd_en => i_rd_en,
+ rd_adr => std_logic_vector(i_rd_addr),
+ rd_dat => o_rd_data
+ );
+end str;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
index 174ff8d1db16f1bf22543c970650bb26f7b38552..965d0cc3c4128ebbc34bd20df791444604ed5552 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
@@ -105,7 +105,7 @@ architecture str of rdma_packetiser_assemble_header is
constant c_ip_udp_app_mid_hdr_len : natural := c_network_ip_header_len + c_udp_app_mid_hdr_len;
constant c_ip_udp_app_last_hdr_len : natural := c_network_ip_header_len + c_udp_app_last_hdr_len;
constant c_ip_udp_app_wo_hdr_len : natural := c_network_ip_header_len + c_udp_app_wo_hdr_len;
- constant c_nof_offload : natural := 4;
+ constant c_nof_offload : natural := 4;
type t_state is (s_first, s_middle, s_last);
type t_reg is record -- record to keep the registers organized.
@@ -161,115 +161,115 @@ architecture str of rdma_packetiser_assemble_header is
signal dp_offload_wo_src_out : t_dp_sosi := c_dp_sosi_rst;
signal dp_offload_wo_src_in : t_dp_siso := c_dp_siso_rdy;
signal dp_pipeline_src_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
- immediate_data <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "immediate_data" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "immediate_data" ));
- use_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_immediate" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_immediate" )));
- use_msg_cnt_as_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate") downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate")));
- nof_packets_in_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ));
- nof_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ));
- dma_len <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ));
- start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" ));
-
- -- State machine to derive RDMA header fields.
- q <= d when rising_edge(st_clk);
- p_comb : process(st_rst, q, snk_in, nof_packets_in_msg, start_address, nof_msg, immediate_data, dma_len, block_len, use_immediate)
- variable v : t_reg;
- begin
- v := q;
- if snk_in.sop = '1' then
- v.psn := resize_uvec(snk_in.bsn, c_word_w);
- v.p_cnt := q.p_cnt + 1;
- case q.state is
- when s_first => -- wait to start a new message and set the first opcode.
- v.p_cnt := 1;
- if q.p_cnt >= v.nof_packets_in_msg then -- (re)set message counter and virtual address.
- if q.msg_cnt >= to_uint(nof_msg) - 1 then
- v.msg_cnt := 0;
- else
- v.msg_cnt := q.msg_cnt + 1;
- v.virtual_address := q.virtual_address + q.dma_len;
- end if;
+ immediate_data <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "immediate_data" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "immediate_data" ));
+ use_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_immediate" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_immediate" )));
+ use_msg_cnt_as_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate") downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate")));
+nof_packets_in_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ));
+nof_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ));
+dma_len <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ));
+start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" ));
+
+-- State machine to derive RDMA header fields.
+q <= d when rising_edge(st_clk);
+
+p_comb : process(st_rst, q, snk_in, nof_packets_in_msg, start_address, nof_msg, immediate_data, dma_len, block_len, use_immediate)
+ variable v : t_reg;
+begin
+ v := q;
+ if snk_in.sop = '1' then
+ v.psn := resize_uvec(snk_in.bsn, c_word_w);
+ v.p_cnt := q.p_cnt + 1;
+ case q.state is
+ when s_first => -- wait to start a new message and set the first opcode.
+ v.p_cnt := 1;
+ if q.p_cnt >= v.nof_packets_in_msg then -- (re)set message counter and virtual address.
+ if q.msg_cnt >= to_uint(nof_msg) - 1 then
+ v.msg_cnt := 0;
+ else
+ v.msg_cnt := q.msg_cnt + 1;
+ v.virtual_address := q.virtual_address + q.dma_len;
end if;
-
- if v.nof_packets_in_msg = 1 then -- set opcode to write_only.
- v.opcode := c_rdma_packetiser_opcode_uc_write_only;
- v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
- v.sel_ctrl := 0;
- if use_immediate = '1' then -- set opcode to write_only with immediate data.
- v.opcode := c_rdma_packetiser_opcode_uc_write_only_imm;
- v.udp_total_length := c_udp_app_wo_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_wo_hdr_len + to_uint(block_len);
+ end if;
+
+ if v.nof_packets_in_msg = 1 then -- set opcode to write_only.
+ v.opcode := c_rdma_packetiser_opcode_uc_write_only;
+ v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
+ v.sel_ctrl := 0;
+ if use_immediate = '1' then -- set opcode to write_only with immediate data.
+ v.opcode := c_rdma_packetiser_opcode_uc_write_only_imm;
+ v.udp_total_length := c_udp_app_wo_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_wo_hdr_len + to_uint(block_len);
v.sel_ctrl := 3;
- end if;
- elsif v.nof_packets_in_msg = 2 then -- set opcode to write_first.
- v.state := s_last; -- next state is last as there are only 2 packets.
- v.opcode := c_rdma_packetiser_opcode_uc_write_first;
- v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
-
- v.sel_ctrl := 0;
- elsif v.nof_packets_in_msg > 2 then
- v.state := s_middle;
- v.opcode := c_rdma_packetiser_opcode_uc_write_first;
- v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
-
- v.sel_ctrl := 0;
end if;
+ elsif v.nof_packets_in_msg = 2 then -- set opcode to write_first.
+ v.state := s_last; -- next state is last as there are only 2 packets.
+ v.opcode := c_rdma_packetiser_opcode_uc_write_first;
+ v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
+
+ v.sel_ctrl := 0;
+ elsif v.nof_packets_in_msg > 2 then
+ v.state := s_middle;
+ v.opcode := c_rdma_packetiser_opcode_uc_write_first;
+ v.udp_total_length := c_udp_app_first_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_first_hdr_len + to_uint(block_len);
+
+ v.sel_ctrl := 0;
+ end if;
+
+ when s_middle => -- wait unitl the first packet is done and set next opcode.
+ v.opcode := c_rdma_packetiser_opcode_uc_write_middle;
+ v.udp_total_length := c_udp_app_mid_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_mid_hdr_len + to_uint(block_len);
+ v.sel_ctrl := 1;
+ if q.p_cnt >= v.nof_packets_in_msg - 2 then -- wait until last middle packet
+ v.state := s_last;
+ end if;
+
+ when s_last => -- next packet must be last packet, set opcode.
+ v.state := s_first;
+ v.opcode := c_rdma_packetiser_opcode_uc_write_last;
+ v.udp_total_length := c_udp_app_mid_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_mid_hdr_len + to_uint(block_len);
+ v.sel_ctrl := 1;
+ if use_immediate = '1' then -- set opcode to write_last with immediate data
+ v.opcode := c_rdma_packetiser_opcode_uc_write_last_imm;
+ v.udp_total_length := c_udp_app_last_hdr_len + to_uint(block_len);
+ v.ip_total_length := c_ip_udp_app_last_hdr_len + to_uint(block_len);
+ v.sel_ctrl := 2;
+ end if;
+ end case;
+ end if;
+
+ if v.msg_cnt = 0 then -- set on new message
+ v.virtual_address := unsigned(start_address);
+ v.dma_len := unsigned(dma_len);
+ v.nof_packets_in_msg := to_uint(nof_packets_in_msg);
+ end if;
+
+ if st_rst = '1' then
+ v := c_reg_rst;
+ end if;
+
+ d <= v;
+end process;
- when s_middle => -- wait unitl the first packet is done and set next opcode.
- v.opcode := c_rdma_packetiser_opcode_uc_write_middle;
- v.udp_total_length := c_udp_app_mid_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_mid_hdr_len + to_uint(block_len);
- v.sel_ctrl := 1;
- if q.p_cnt >= v.nof_packets_in_msg - 2 then -- wait until last middle packet
- v.state := s_last;
- end if;
+-------------------------------------------------------------------------------
+-- Wire the header fields
+-------------------------------------------------------------------------------
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "ip_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "ip_total_length" )) <= TO_UVEC(q.ip_total_length, 16);
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "udp_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "udp_total_length" )) <= TO_UVEC(q.udp_total_length, 16);
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "bth_opcode" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "bth_opcode" )) <= q.opcode;
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "bth_psn" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "bth_psn" )) <= q.psn;
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "reth_virtual_address") downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_virtual_address")) <= std_logic_vector(q.virtual_address);
+hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" )) <= std_logic_vector(q.dma_len);
- when s_last => -- next packet must be last packet, set opcode.
- v.state := s_first;
- v.opcode := c_rdma_packetiser_opcode_uc_write_last;
- v.udp_total_length := c_udp_app_mid_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_mid_hdr_len + to_uint(block_len);
- v.sel_ctrl := 1;
- if use_immediate = '1' then -- set opcode to write_last with immediate data
- v.opcode := c_rdma_packetiser_opcode_uc_write_last_imm;
- v.udp_total_length := c_udp_app_last_hdr_len + to_uint(block_len);
- v.ip_total_length := c_ip_udp_app_last_hdr_len + to_uint(block_len);
- v.sel_ctrl := 2;
- end if;
- end case;
- end if;
-
- if v.msg_cnt = 0 then -- set on new message
- v.virtual_address := unsigned(start_address);
- v.dma_len := unsigned(dma_len);
- v.nof_packets_in_msg := to_uint(nof_packets_in_msg);
- end if;
-
- if st_rst = '1' then
- v := c_reg_rst;
- end if;
-
- d <= v;
- end process;
-
- -------------------------------------------------------------------------------
- -- Wire the header fields
- -------------------------------------------------------------------------------
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "ip_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "ip_total_length" )) <= TO_UVEC(q.ip_total_length, 16);
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "udp_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "udp_total_length" )) <= TO_UVEC(q.udp_total_length, 16);
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "bth_opcode" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "bth_opcode" )) <= q.opcode;
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "bth_psn" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "bth_psn" )) <= q.psn;
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "reth_virtual_address") downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_virtual_address")) <= std_logic_vector(q.virtual_address);
- hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" )) <= std_logic_vector(q.dma_len);
-
- -------------------------------------------------------------------------------
- -- demux to guide the incoming stream to the correct dp_offload_tx_v3
- -------------------------------------------------------------------------------
- u_dp_demux : entity dp_lib.dp_demux
+-------------------------------------------------------------------------------
+-- demux to guide the incoming stream to the correct dp_offload_tx_v3
+-------------------------------------------------------------------------------
+u_dp_demux : entity dp_lib.dp_demux
generic map (
g_mode => 2,
g_nof_output => c_nof_offload,
@@ -282,53 +282,53 @@ begin
clk => st_clk,
sel_ctrl => q.sel_ctrl,
-
+
snk_in => snk_in,
snk_out => snk_out,
-
+
src_out_arr => dp_demux_src_out_arr,
src_in_arr => dp_demux_src_in_arr
);
- -- Wire demux outputs to dp_offload inputs.
- dp_offload_first_snk_in <= dp_demux_src_out_arr(0);
- dp_offload_mid_snk_in <= dp_demux_src_out_arr(1);
- dp_offload_last_snk_in <= dp_demux_src_out_arr(2);
- dp_offload_wo_snk_in <= dp_demux_src_out_arr(3);
- dp_demux_src_in_arr(0) <= dp_offload_first_snk_out;
- dp_demux_src_in_arr(1) <= dp_offload_mid_snk_out;
- dp_demux_src_in_arr(2) <= dp_offload_last_snk_out;
- dp_demux_src_in_arr(3) <= dp_offload_wo_snk_out;
-
- -- Wire header fields for every do_offload
- p_wire_headers : process(hdr_fields_slv_out_mm, use_msg_cnt_as_immediate, q)
- begin
- -- set headers.
- hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
- hdr_fields_slv_out_mm);
- hdr_fields_slv_in_mid <= field_select_subset(c_rdma_packetiser_mid_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
- hdr_fields_slv_out_mm);
- hdr_fields_slv_in_last <= field_select_subset(c_rdma_packetiser_last_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
- hdr_fields_slv_out_mm);
- hdr_fields_slv_in_wo <= field_select_subset(c_rdma_packetiser_wo_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
- hdr_fields_slv_out_mm);
-
- if use_msg_cnt_as_immediate = '1' then -- set immediate data to msg_cnt when use_msg_cnt_as_immediate = '1'
- hdr_fields_slv_in_last(field_hi(c_rdma_packetiser_last_hdr_field_arr, "immediate_data") downto
- field_lo(c_rdma_packetiser_last_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
- hdr_fields_slv_in_wo( field_hi(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data") downto
- field_lo(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
- end if;
- end process;
-
- -------------------------------------------------------------------------------
- -- Header for first packets or write only without immediate data
- -------------------------------------------------------------------------------
- u_dp_offload_first : entity dp_lib.dp_offload_tx_v3
+-- Wire demux outputs to dp_offload inputs.
+dp_offload_first_snk_in <= dp_demux_src_out_arr(0);
+dp_offload_mid_snk_in <= dp_demux_src_out_arr(1);
+dp_offload_last_snk_in <= dp_demux_src_out_arr(2);
+dp_offload_wo_snk_in <= dp_demux_src_out_arr(3);
+dp_demux_src_in_arr(0) <= dp_offload_first_snk_out;
+dp_demux_src_in_arr(1) <= dp_offload_mid_snk_out;
+dp_demux_src_in_arr(2) <= dp_offload_last_snk_out;
+dp_demux_src_in_arr(3) <= dp_offload_wo_snk_out;
+
+-- Wire header fields for every do_offload
+p_wire_headers : process(hdr_fields_slv_out_mm, use_msg_cnt_as_immediate, q)
+begin
+ -- set headers.
+ hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_out_mm);
+ hdr_fields_slv_in_mid <= field_select_subset(c_rdma_packetiser_mid_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_out_mm);
+ hdr_fields_slv_in_last <= field_select_subset(c_rdma_packetiser_last_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_out_mm);
+ hdr_fields_slv_in_wo <= field_select_subset(c_rdma_packetiser_wo_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_out_mm);
+
+ if use_msg_cnt_as_immediate = '1' then -- set immediate data to msg_cnt when use_msg_cnt_as_immediate = '1'
+ hdr_fields_slv_in_last(field_hi(c_rdma_packetiser_last_hdr_field_arr, "immediate_data") downto
+ field_lo(c_rdma_packetiser_last_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
+ hdr_fields_slv_in_wo( field_hi(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data") downto
+ field_lo(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
+ end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- Header for first packets or write only without immediate data
+-------------------------------------------------------------------------------
+u_dp_offload_first : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => g_data_w,
@@ -347,10 +347,10 @@ begin
hdr_fields_in_arr(0) => hdr_fields_slv_in_first
);
- -------------------------------------------------------------------------------
- -- Header for middle or last without immediate data (no RETH, no immediate data)
- -------------------------------------------------------------------------------
- u_dp_offload_mid : entity dp_lib.dp_offload_tx_v3
+-------------------------------------------------------------------------------
+-- Header for middle or last without immediate data (no RETH, no immediate data)
+-------------------------------------------------------------------------------
+u_dp_offload_mid : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => g_data_w,
@@ -369,10 +369,10 @@ begin
hdr_fields_in_arr(0) => hdr_fields_slv_in_mid
);
- -------------------------------------------------------------------------------
- -- Header for last packets with immediate data
- -------------------------------------------------------------------------------
- u_dp_offload_last : entity dp_lib.dp_offload_tx_v3
+-------------------------------------------------------------------------------
+-- Header for last packets with immediate data
+-------------------------------------------------------------------------------
+u_dp_offload_last : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => g_data_w,
@@ -388,13 +388,13 @@ begin
snk_out_arr(0) => dp_offload_last_snk_out,
src_out_arr(0) => dp_offload_last_src_out,
src_in_arr(0) => dp_offload_last_src_in,
- hdr_fields_in_arr(0) => hdr_fields_slv_in_last
+ hdr_fields_in_arr(0) => hdr_fields_slv_in_last
);
- -------------------------------------------------------------------------------
- -- Header for write only packets with immediate data
- -------------------------------------------------------------------------------
- u_dp_offload_wo : entity dp_lib.dp_offload_tx_v3
+-------------------------------------------------------------------------------
+-- Header for write only packets with immediate data
+-------------------------------------------------------------------------------
+u_dp_offload_wo : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => g_data_w,
@@ -413,11 +413,11 @@ begin
hdr_fields_in_arr(0) => hdr_fields_slv_in_wo
);
- -------------------------------------------------------------------------------
- -- Using extra dp_offload_tx_v3 only for MM that contains all headers + config register
- -------------------------------------------------------------------------------
- -- DP pipeline to correct for state machine latency
- u_dp_pipeline : entity dp_lib.dp_pipeline
+-------------------------------------------------------------------------------
+-- Using extra dp_offload_tx_v3 only for MM that contains all headers + config register
+-------------------------------------------------------------------------------
+-- DP pipeline to correct for state machine latency
+u_dp_pipeline : entity dp_lib.dp_pipeline
port map (
rst => st_rst,
clk => st_clk,
@@ -426,8 +426,8 @@ begin
src_out => dp_pipeline_src_out
);
- -- dp_offload_tx_v3
- u_dp_offload_tx : entity dp_lib.dp_offload_tx_v3
+-- dp_offload_tx_v3
+u_dp_offload_tx : entity dp_lib.dp_offload_tx_v3
generic map (
g_nof_streams => 1,
g_data_w => g_data_w,
@@ -441,27 +441,27 @@ begin
mm_clk => mm_clk,
dp_rst => st_rst,
dp_clk => st_clk,
- reg_hdr_dat_mosi => reg_hdr_dat_copi,
- reg_hdr_dat_miso => reg_hdr_dat_cipo,
+ reg_hdr_dat_mosi => reg_hdr_dat_copi,
+ reg_hdr_dat_miso => reg_hdr_dat_cipo,
snk_in_arr(0) => dp_pipeline_src_out,
hdr_fields_in_arr(0) => hdr_fields_slv_in,
hdr_fields_out_arr(0) => hdr_fields_slv_out_mm
);
- -------------------------------------------------------------------------------
- -- Mux to merge the packets from the different dp_offload_tx_v3
- -------------------------------------------------------------------------------
- -- Wire demux outputs to dp_offload inputs.
- dp_mux_snk_in_arr(0) <= dp_offload_first_src_out;
- dp_mux_snk_in_arr(1) <= dp_offload_mid_src_out;
- dp_mux_snk_in_arr(2) <= dp_offload_last_src_out;
- dp_mux_snk_in_arr(3) <= dp_offload_wo_src_out;
- dp_offload_first_src_in <= dp_mux_snk_out_arr(0);
- dp_offload_mid_src_in <= dp_mux_snk_out_arr(1);
- dp_offload_last_src_in <= dp_mux_snk_out_arr(2);
- dp_offload_wo_src_in <= dp_mux_snk_out_arr(3);
-
- u_dp_mux : entity dp_lib.dp_mux
+-------------------------------------------------------------------------------
+-- Mux to merge the packets from the different dp_offload_tx_v3
+-------------------------------------------------------------------------------
+-- Wire demux outputs to dp_offload inputs.
+dp_mux_snk_in_arr(0) <= dp_offload_first_src_out;
+dp_mux_snk_in_arr(1) <= dp_offload_mid_src_out;
+dp_mux_snk_in_arr(2) <= dp_offload_last_src_out;
+dp_mux_snk_in_arr(3) <= dp_offload_wo_src_out;
+dp_offload_first_src_in <= dp_mux_snk_out_arr(0);
+dp_offload_mid_src_in <= dp_mux_snk_out_arr(1);
+dp_offload_last_src_in <= dp_mux_snk_out_arr(2);
+dp_offload_wo_src_in <= dp_mux_snk_out_arr(3);
+
+u_dp_mux : entity dp_lib.dp_mux
generic map (
g_mode => 2,
g_nof_input => c_nof_offload,
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
index b66da5f7dc56ef1eb9d137d0c2bca9c350c5bc0f..db971f30c90ef22a48367a52cd5ac957cd9cedcd 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
@@ -142,11 +142,9 @@ package rdma_packetiser_pkg is
( field_name_pad("config_nof_packets_in_msg" ), "RW", 32, field_default(0) ), -- set by M&C
( field_name_pad("config_nof_msg" ), "RW", 32, field_default(0) ), -- set by M&C
( field_name_pad("config_start_address" ), "RW", 64, field_default(0) ) -- set by M&C
- );
+ );
constant c_rdma_packetiser_reg_mm_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_packetiser_mm_field_arr, c_word_w));
- constant c_rdma_packetiser_reg_mm_dat_addr_span : natural := 2**c_rdma_packetiser_reg_mm_dat_addr_w;
-
-
+ constant c_rdma_packetiser_reg_mm_dat_addr_span : natural := 2 ** c_rdma_packetiser_reg_mm_dat_addr_w;
-- RoCEv2 header for first packets and write only packets without immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH)
@@ -156,7 +154,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_first_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_first_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
@@ -189,13 +187,13 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) )
+ ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) )
- );
+ );
-- RoCEv2 header for middle packets and last packets without immediate data.
-- ETH + IP + UDP + Base Transport Header (BTH)
@@ -205,7 +203,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_mid_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_mid_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
@@ -238,8 +236,8 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) )
- );
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) )
+ );
-- RoCEv2 header for last packets with immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + immediate data
@@ -249,7 +247,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_last_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_last_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
@@ -285,7 +283,7 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
- );
+ );
-- RoCEv2 header for write only packets with immediate data
-- ETH + IP + UDP + Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) + immediate data
@@ -295,7 +293,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_wo_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_wo_nof_hdr_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
@@ -329,13 +327,13 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
-
+
( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
- ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
- );
+ ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
+ );
constant c_rdma_packetiser_bth_len : natural := 12; -- octets
constant c_rdma_packetiser_reth_len : natural := 16; -- octets
@@ -402,7 +400,7 @@ package body rdma_packetiser_pkg is
v.bth.ack_req := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_ack_req") downto field_lo(c_hdr_field_arr, "bth_ack_req"));
v.bth.reserved_b := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_reserved_b") downto field_lo(c_hdr_field_arr, "bth_reserved_b"));
v.bth.psn := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_psn") downto field_lo(c_hdr_field_arr, "bth_psn"));
-
+
-- reth header (optional)
v.reth := ((others => '0'), (others => '0'),(others => '0'));
if field_exists(c_hdr_field_arr, "reth_virtual_address") then -- reth header exists
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
index 66b41e714ef9bdf1ecf9cdc54577d267667194cc..3d4fe84ee8423a421cb598a20b1235cb3a6b116a 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
@@ -113,7 +113,6 @@ architecture tb of tb_rdma_packetiser_assemble_header is
signal reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
signal reg_hdr_dat_cipo : t_mem_cipo;
-
begin
dp_rst <= '1', '0' after c_dp_clk_period * 7;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
@@ -153,7 +152,6 @@ begin
wait;
end process;
-
-- check if values in rdma_packetiser_assemble_header match with expected values
p_verify_rdma_header : process
variable v_exp_ip_total_length : natural;
@@ -165,7 +163,6 @@ begin
variable v_exp_immediate_data : std_logic_vector(c_word_w - 1 downto 0);
variable v_p, v_m : natural := 0;
begin
-
proc_common_wait_until_high(dp_clk, mm_done); -- wait mm setup
for rep in 0 to g_nof_rep - 1 loop
@@ -195,18 +192,18 @@ begin
-- calculate expected lengths
v_exp_udp_total_length := c_network_udp_header_len + c_rdma_packetiser_bth_len + to_uint(block_len) + c_rdma_packetiser_icrc_len;
v_exp_reth_virtual_address := (others => '0');
- v_exp_reth_dma_length := 0;
+ v_exp_reth_dma_length := 0;
if v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_first or
- v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only or
- v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only_imm then
+ v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only or
+ v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only_imm then
v_exp_udp_total_length := v_exp_udp_total_length + c_rdma_packetiser_reth_len;
v_exp_reth_virtual_address := g_start_address + to_unsigned((v_m mod g_nof_msg) * c_dma_len, c_longword_w);
v_exp_reth_dma_length := c_dma_len;
end if;
if v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only_imm or
- v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_last_imm then
+ v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_last_imm then
v_exp_udp_total_length := v_exp_udp_total_length + c_rdma_packetiser_imm_len;
end if;
@@ -214,11 +211,11 @@ begin
-- select header based on expected opcode
if v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_first or
- v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only then
+ v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only then
rx_rdma_header <= func_rdma_packetiser_map_header(first_hdr_fields_arr, c_rdma_packetiser_first_hdr_field_arr);
v_exp_immediate_data := (others => '0'); -- does not exist in this header
elsif v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_middle or
- v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_last then
+ v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_last then
rx_rdma_header <= func_rdma_packetiser_map_header(mid_hdr_fields_arr, c_rdma_packetiser_mid_hdr_field_arr);
v_exp_immediate_data := (others => '0'); -- does not exist in this header
elsif v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_last_imm then
@@ -268,7 +265,6 @@ begin
wait;
end process;
-
u_dut: entity work.rdma_packetiser_assemble_header
generic map (
g_data_w => g_data_w
@@ -284,7 +280,7 @@ begin
snk_in => snk_in,
snk_out => snk_out,
-
+
src_out => src_out,
src_in => src_in,
@@ -292,79 +288,79 @@ begin
);
-------------------------------------------------------------------------------
- -- Header for first packets or write only without immediate data
+ -- Header for first packets or write only without immediate data
-------------------------------------------------------------------------------
u_dp_offload_first: entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_rdma_packetiser_first_hdr_field_arr
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- snk_in_arr(0) => src_out,
- hdr_fields_raw_arr(0) => first_hdr_fields_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_rdma_packetiser_first_hdr_field_arr
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ snk_in_arr(0) => src_out,
+ hdr_fields_raw_arr(0) => first_hdr_fields_arr
+ );
-------------------------------------------------------------------------------
-- Header for middle or last without immediate data (no RETH, no immediate data)
-------------------------------------------------------------------------------
u_dp_offload_mid: entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_rdma_packetiser_mid_hdr_field_arr
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- snk_in_arr(0) => src_out,
- hdr_fields_raw_arr(0) => mid_hdr_fields_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_rdma_packetiser_mid_hdr_field_arr
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ snk_in_arr(0) => src_out,
+ hdr_fields_raw_arr(0) => mid_hdr_fields_arr
+ );
-------------------------------------------------------------------------------
-- Header for last packets with immediate data
-------------------------------------------------------------------------------
u_dp_offload_last: entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_rdma_packetiser_last_hdr_field_arr
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- snk_in_arr(0) => src_out,
- hdr_fields_raw_arr(0) => last_hdr_fields_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_rdma_packetiser_last_hdr_field_arr
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ snk_in_arr(0) => src_out,
+ hdr_fields_raw_arr(0) => last_hdr_fields_arr
+ );
-------------------------------------------------------------------------------
- -- Header for write only packets with immediate data
+ -- Header for write only packets with immediate data
-------------------------------------------------------------------------------
u_dp_offload_wo: entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_field_arr => c_rdma_packetiser_wo_hdr_field_arr
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- snk_in_arr(0) => src_out,
- src_out_arr(0) => sop_sosi,
- hdr_fields_raw_arr(0) => wo_hdr_fields_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_field_arr => c_rdma_packetiser_wo_hdr_field_arr
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ snk_in_arr(0) => src_out,
+ src_out_arr(0) => sop_sosi,
+ hdr_fields_raw_arr(0) => wo_hdr_fields_arr
+ );
end tb;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
index 2a800a776a368365f0f07dfd6609436e0cccb3ba..9527eeef22627f1535e8ee934886f5315c722d1a 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
@@ -53,11 +53,11 @@ begin
u_lo_addr : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_low_start_addr, 4, 5);
u_hi_addr : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 4, 5);
u_no_mid : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 2, 5);
- u_wr_only : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 1, 5);
+ u_wr_only : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 1, 5);
u_large : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 10, 2000, c_low_start_addr, 3, 1);
u_no_imm_cnt : entity work.tb_rdma_packetiser_assemble_header generic map( 32, false, true, 50, 15, c_low_start_addr, 4, 5);
u_no_cnt : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, false, 50, 15, c_low_start_addr, 4, 5);
u_no_imm : entity work.tb_rdma_packetiser_assemble_header generic map( 32, false, false, 50, 7, c_high_start_addr, 3, 5);
- u_wide : entity work.tb_rdma_packetiser_assemble_header generic map( 1024, true, true, 50, 6, c_low_start_addr, 1, 5);
- u_many : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 600, 7, c_low_start_addr, 100, 5);
+ u_wide : entity work.tb_rdma_packetiser_assemble_header generic map( 1024, true, true, 50, 6, c_low_start_addr, 1, 5);
+ u_many : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 600, 7, c_low_start_addr, 100, 5);
end tb;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index 6dd67461421825c623cf4ea6fe6d758361b640e0..d4418343842604fcff79560f36c2d8c6bc03667e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -22,9 +22,9 @@
-- . Collection of functions for the ring design
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package ring_pkg is
function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
index 34b1424f815182181ca35334120e421656f29c93..2582727afbf942af3a403bb7b576a63723360e99 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -49,18 +49,18 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use diag_lib.diag_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
entity tb_lofar2_unb2b_ring_bsp is
end tb_lofar2_unb2b_ring_bsp;
@@ -154,56 +154,56 @@ begin
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_ring_bsp : entity work.top
- generic map (
- g_design_name => "lofar2_unb2b_ring_bsp",
- g_design_note => "",
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => c_version,
- ID => c_id,
- TESTIO => open,
-
- -- I2C Interface to Sensors
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- PMBUS_SC => pmbus_scl,
- PMBUS_SD => pmbus_sda,
- PMBUS_ALERT => open,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- -- front transceivers
- QSFP_0_RX => si_lpbk_0,
- QSFP_0_TX => si_lpbk_0,
- -- ring transceivers
- RING_0_RX => si_lpbk_2,
- RING_0_TX => si_lpbk_1,
- RING_1_RX => si_lpbk_1,
- RING_1_TX => si_lpbk_2,
-
- -- LEDs
- QSFP_LED => open
-
- );
-
- u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
+ generic map (
+ g_design_name => "lofar2_unb2b_ring_bsp",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_0_TX => si_lpbk_0,
+ -- ring transceivers
+ RING_0_RX => si_lpbk_2,
+ RING_0_TX => si_lpbk_1,
+ RING_1_RX => si_lpbk_1,
+ RING_1_TX => si_lpbk_2,
+
+ -- LEDs
+ QSFP_LED => open
+
+ );
+
+ u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
port map (
refclk_644 => SA_CLK,
rst_in => pps_rst,
@@ -213,7 +213,7 @@ begin
rst_312 => open
);
- u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
+ u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_sim => true,
g_sim_level => 1,
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index d13377d1b35d1ea75891924f3ed24f8a476641eb..38e4f3b1eed7380e5f2fcaf798aa6272535d5a82 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -31,19 +31,19 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use lofar2_sdp_lib.sdp_pkg.all;
-use work.ring_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use lofar2_sdp_lib.sdp_pkg.all;
+ use work.ring_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -396,21 +396,21 @@ begin
QSFP_0_TX <= i_QSFP_TX(0);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
- --QSFP_LED => QSFP_LED
- );
+ --QSFP_LED => QSFP_LED
+ );
------------------------
-- qsfp LEDs controller
@@ -418,21 +418,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(0).xon <= ta2_unb2b_10GbE_qsfp_snk_out_arr(0).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -448,6 +448,7 @@ begin
RING_1_TX <= i_RING_TX(1);
gen_wire_bus : for i in 0 to c_nof_ring_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_ring_bus_w - 1 generate
i_RING_TX(i)(j) <= unb2b_board_ring_io_serial_tx_arr(i * c_ring_bus_w + j);
unb2b_board_ring_io_serial_rx_arr(i * c_ring_bus_w + j) <= i_RING_RX(i)(j);
@@ -458,17 +459,17 @@ begin
-- PLL
--------
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => clk_156,
- clk_312 => clk_312,
- rst_156 => rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => clk_156,
+ clk_312 => clk_312,
+ rst_156 => rst_156,
+ rst_312 => open
+ );
----------
-- 10GbE
@@ -511,128 +512,128 @@ begin
-- tr_10GbE
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_max_nof_mac,
- g_use_err => true,
- g_use_pll => true
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
-
- clk_ref_r => SA_CLK,
-
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ generic map (
+ g_nof_mac => c_max_nof_mac,
+ g_use_err => true,
+ g_use_pll => true
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
+
+ clk_ref_r => SA_CLK,
+
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
-
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
- );
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
+
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for from/to lane sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_lanes : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
- dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for bs sosi
-----------------------------------------------------------------------------
u_ta2_channel_cross_bs_sosi : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => 1,
- g_nof_bytes => c_word_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- dp_snk_in_arr(0) => bs_sosi,
- kernel_src_out_arr(0) => kernel_bs_sosi
- );
+ generic map(
+ g_nof_streams => 1,
+ g_nof_bytes => c_word_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ dp_snk_in_arr(0) => bs_sosi,
+ kernel_src_out_arr(0) => kernel_bs_sosi
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for rx_monitors
-----------------------------------------------------------------------------
u_ta2_channel_cross_rx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- kernel clock crossing for tx_monitors
@@ -643,30 +644,31 @@ begin
end generate;
u_ta2_channel_cross_tx_monitor : entity ta2_channel_cross_lib.ta2_channel_cross
- generic map(
- g_nof_streams => g_nof_lanes,
- g_nof_bytes => c_longword_sz,
- g_reverse_bytes => true,
- g_use_bsn => true,
- g_use_sync => true,
- g_use_channel => true
- )
- port map(
- dp_clk => st_clk,
- dp_rst => st_rst,
-
- dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
- dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
-
- kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
- kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => true,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_use_channel => true
+ )
+ port map(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0),
+ dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes - 1 downto 0),
+ kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
rx_monitor_siso_arr <= dp_demux_rx_monitor_siso_arr;
tx_monitor_siso_arr <= dp_demux_tx_monitor_siso_arr;
+
p_calc_source_rn : process(tx_monitor_sosi_arr, rx_monitor_sosi_arr)
begin
dp_demux_rx_monitor_sosi_arr <= rx_monitor_sosi_arr;
@@ -683,189 +685,189 @@ begin
-- demux rx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_rx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_rx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_demux_rx_monitor_siso_arr(I),
- snk_in => dp_demux_rx_monitor_sosi_arr(I),
-
- src_in_arr => rx_monitor_siso_2arr(I),
- src_out_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_output => g_nof_rx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_demux_rx_monitor_siso_arr(I),
+ snk_in => dp_demux_rx_monitor_sosi_arr(I),
+
+ src_in_arr => rx_monitor_siso_2arr(I),
+ src_out_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- rx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_rx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_rx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => rx_monitor_siso_2arr(I),
- in_sosi_arr => rx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_rx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => rx_monitor_siso_2arr(I),
+ in_sosi_arr => rx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- demux tx_monitor inputs
-----------------------------------------------------------------------------
u_dp_demux_tx_monitor : entity dp_lib.dp_demux
- generic map(
- g_nof_output => g_nof_tx_monitors,
- g_sel_ctrl_invert => true
- )
- port map(
- rst => st_rst,
- clk => st_clk,
+ generic map(
+ g_nof_output => g_nof_tx_monitors,
+ g_sel_ctrl_invert => true
+ )
+ port map(
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_demux_tx_monitor_siso_arr(I),
- snk_in => dp_demux_tx_monitor_sosi_arr(I),
+ snk_out => dp_demux_tx_monitor_siso_arr(I),
+ snk_in => dp_demux_tx_monitor_sosi_arr(I),
- src_in_arr => tx_monitor_siso_2arr(I),
- src_out_arr => tx_monitor_sosi_2arr(I)
- );
+ src_in_arr => tx_monitor_siso_2arr(I),
+ src_out_arr => tx_monitor_sosi_2arr(I)
+ );
-----------------------------------------------------------------------------
-- tx_monitors
-----------------------------------------------------------------------------
u_mms_dp_bsn_monitor_v2_tx : entity dp_lib.mms_dp_bsn_monitor_v2
- generic map(
- g_nof_streams => g_nof_tx_monitors
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
- reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- ref_sync => bs_sosi.sync,
-
- in_siso_arr => tx_monitor_siso_2arr(I),
- in_sosi_arr => tx_monitor_sosi_2arr(I)
- );
+ generic map(
+ g_nof_streams => g_nof_tx_monitors
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => tx_monitor_siso_2arr(I),
+ in_sosi_arr => tx_monitor_sosi_2arr(I)
+ );
end generate;
u_common_mem_mux_rx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_rx_mosi,
- miso => reg_bsn_monitor_v2_rx_miso,
- mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_rx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_rx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_rx_mosi,
+ miso => reg_bsn_monitor_v2_rx_miso,
+ mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_miso_arr
+ );
u_common_mem_mux_tx_monitors : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_lanes,
- g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
- )
- port map (
- mosi => reg_bsn_monitor_v2_tx_mosi,
- miso => reg_bsn_monitor_v2_tx_miso,
- mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
- miso_arr => reg_bsn_monitor_v2_tx_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_tx_monitors) + 3
+ )
+ port map (
+ mosi => reg_bsn_monitor_v2_tx_mosi,
+ miso => reg_bsn_monitor_v2_tx_miso,
+ mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_tx_miso_arr
+ );
-----------------------------------------------------------------------------
-- Design part, mms_diag_block_gen
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_nof_lanes,
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => 32, -- BG is limited to 32 bits data
- g_buf_addr_w => 7,
- g_file_name_prefix => "data/bf_in_data"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
- en_sync => st_pps,
-
- -- MM interface
- reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
- reg_bg_ctrl_miso => reg_bg_ctrl_miso,
- ram_bg_data_mosi => ram_bg_data_mosi,
- ram_bg_data_miso => ram_bg_data_miso,
-
- -- ST interface
- out_siso_arr => local_siso_arr,
- out_sosi_arr => local_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => 32, -- BG is limited to 32 bits data
+ g_buf_addr_w => 7,
+ g_file_name_prefix => "data/bf_in_data"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ en_sync => st_pps,
+
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
+ reg_bg_ctrl_miso => reg_bg_ctrl_miso,
+ ram_bg_data_mosi => ram_bg_data_mosi,
+ ram_bg_data_miso => ram_bg_data_miso,
+
+ -- ST interface
+ out_siso_arr => local_siso_arr,
+ out_sosi_arr => local_sosi_arr
+ );
bs_sosi <= local_sosi_arr(0);
u_mms_dp_xonoff_bg : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '0'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_bg_mosi,
- reg_miso => reg_dp_xonoff_bg_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => local_siso_arr,
- snk_in_arr => local_sosi_arr,
- -- ST source
- src_in_arr => dp_xonoff_bg_siso_arr,
- src_out_arr => dp_xonoff_bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '0'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_bg_mosi,
+ reg_miso => reg_dp_xonoff_bg_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => local_siso_arr,
+ snk_in_arr => local_sosi_arr,
+ -- ST source
+ src_in_arr => dp_xonoff_bg_siso_arr,
+ src_out_arr => dp_xonoff_bg_sosi_arr
+ );
u_mms_dp_xonoff_from_lane : entity dp_lib.mms_dp_xonoff
- generic map(
- g_nof_streams => g_nof_lanes,
- g_combine_streams => false,
- g_default_value => '1'
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_from_lane_mosi,
- reg_miso => reg_dp_xonoff_from_lane_miso,
-
- -- Streaming clock domain
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- -- ST sinks
- snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
- -- ST source
- src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
- src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
- );
+ generic map(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => false,
+ g_default_value => '1'
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_from_lane_mosi,
+ reg_miso => reg_dp_xonoff_from_lane_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ snk_in_arr => from_lane_sosi_arr(g_nof_lanes - 1 downto 0),
+ -- ST source
+ src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes - 1 downto 0),
+ src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
+ );
gen_streams : for I in 0 to g_nof_lanes - 1 generate
-- Multiplex the inputs:
@@ -878,28 +880,28 @@ begin
mux_snk_in_2arr_2(I)(1) <= dp_xonoff_bg_sosi_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 0,
- g_nof_input => 2,
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => to_lane_siso_arr(I),
- src_out => to_lane_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 0,
+ g_nof_input => 2,
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => to_lane_siso_arr(I),
+ src_out => to_lane_sosi_arr(I)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -908,263 +910,263 @@ begin
gn_index <= TO_UINT(ID(c_sdp_W_gn_id - 1 downto 0));
this_rn_id <= TO_UVEC(gn_index - TO_UINT(sdp_info.O_rn), c_sdp_W_gn_id);
u_sdp_info : entity lofar2_sdp_lib.sdp_info
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
- dp_clk => st_clk,
- dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_rst => st_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
- -- inputs from other blocks
- gn_index => gn_index,
- f_adc => '1',
- fsub_type => '0',
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => '1',
+ fsub_type => '0',
- -- sdp info
- sdp_info => sdp_info
- );
+ -- sdp info
+ sdp_info => sdp_info
+ );
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
gen_opencl: if g_sim = false generate
- freeze_wrapper_inst : freeze_wrapper
- port map(
- board_kernel_clk_clk => board_kernel_clk_clk,
- board_kernel_clk2x_clk => board_kernel_clk2x_clk,
- board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
- board_kernel_irq_irq => board_kernel_irq_irq,
- board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- board_kernel_cra_readdata => board_kernel_cra_readdata,
- board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- board_kernel_cra_burstcount => board_kernel_cra_burstcount,
- board_kernel_cra_writedata => board_kernel_cra_writedata,
- board_kernel_cra_address => board_kernel_cra_address,
- board_kernel_cra_write => board_kernel_cra_write,
- board_kernel_cra_read => board_kernel_cra_read,
- board_kernel_cra_byteenable => board_kernel_cra_byteenable,
- board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- board_kernel_register_mem_address => board_kernel_register_mem_address,
- board_kernel_register_mem_clken => board_kernel_register_mem_clken,
- board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- board_kernel_register_mem_write => board_kernel_register_mem_write,
- board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
-
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
- board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
- board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
-
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
- board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
- board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
-
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
- board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
- board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
-
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
- board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
- board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
-
- board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
- board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
-
- board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
- board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
- board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
- board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
-
- board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
- board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
- board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
- board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
-
- board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
- board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
- board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
- board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
-
- board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
- board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
- board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
- board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
-
- board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
- board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
- board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
- board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
-
- board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
- board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
- board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
- board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
-
- board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
- board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
- board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
- board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
-
- board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
- board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
- board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
- board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
-
- board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
- board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
- board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
-
- board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
- board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
- board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
-
- board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
- board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
- board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
-
- board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
- board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
- board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
-
- board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
- board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
- board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
-
- board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
- board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
- board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
-
- board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
- board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
- board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
-
- board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
- board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
- board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
- board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
-
- board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
- board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
- board_kernel_stream_src_bs_ready => OPEN,
-
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
- board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
- board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
- board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
- board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
+ freeze_wrapper_inst : freeze_wrapper
+ port map(
+ board_kernel_clk_clk => board_kernel_clk_clk,
+ board_kernel_clk2x_clk => board_kernel_clk2x_clk,
+ board_kernel_reset_reset_n => board_kernel_reset_reset_n_in,
+ board_kernel_irq_irq => board_kernel_irq_irq,
+ board_kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ board_kernel_cra_readdata => board_kernel_cra_readdata,
+ board_kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ board_kernel_cra_burstcount => board_kernel_cra_burstcount,
+ board_kernel_cra_writedata => board_kernel_cra_writedata,
+ board_kernel_cra_address => board_kernel_cra_address,
+ board_kernel_cra_write => board_kernel_cra_write,
+ board_kernel_cra_read => board_kernel_cra_read,
+ board_kernel_cra_byteenable => board_kernel_cra_byteenable,
+ board_kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ board_kernel_register_mem_address => board_kernel_register_mem_address,
+ board_kernel_register_mem_clken => board_kernel_register_mem_clken,
+ board_kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ board_kernel_register_mem_write => board_kernel_register_mem_write,
+ board_kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
+ board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
+ board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
+
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
+ board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
+ board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
+
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
+ board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
+ board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
+
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
+ board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
+ board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w - 1 downto 0),
+ board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
+ board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
+ board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
+ board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
+
+ board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
+ board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
+ board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
+ board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
+
+ board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
+ board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
+ board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
+ board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
+
+ board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
+ board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
+ board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
+ board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
+
+ board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
+ board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
+ board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
+ board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
+
+ board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
+ board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
+ board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
+ board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
+
+ board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
+ board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
+ board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
+ board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
+
+ board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
+ board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
+ board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
+ board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
+
+ board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
+ board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
+
+ board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
+ board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
+
+ board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
+ board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
+
+ board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
+ board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
+
+ board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
+ board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
+
+ board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
+ board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
+
+ board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
+ board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
+
+ board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
+ board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
+
+ board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
+ board_kernel_stream_src_bs_ready => OPEN,
+
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w - 1 downto 0),
+ board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
+ board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w - 1 downto 0),
+ board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
+ board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
- );
+ );
i_kernel_rst <= not board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
end generate;
@@ -1173,164 +1175,175 @@ begin
i_kernel_rst <= not i_reset_n;
board_kernel_clk_clk <= st_clk;
- u_mm_file_reg_sdp_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
- u_mm_file_reg_dp_xonoff_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
- port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
- u_mm_file_reg_dp_xonoff_from_lane: mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
- port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
- u_mm_file_reg_bsn_monitor_rx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
- u_mm_file_reg_bsn_monitor_tx : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
- u_mm_file_reg_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
- port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+ u_mm_file_reg_sdp_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ port map(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+
+ u_mm_file_reg_dp_xonoff_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+
+ u_mm_file_reg_dp_xonoff_from_lane: mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
+ port map(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+
+ u_mm_file_reg_bsn_monitor_rx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+
+ u_mm_file_reg_bsn_monitor_tx : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+
+ u_mm_file_reg_bg_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
+ port map(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
end generate;
i_reset_n <= not mm_rst; -- First reset OpenCL components in qsys (board)
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
-- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
------------------------------------------------------------------------------
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
+ -----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- RAM scrap
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- RAM scrap
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
gen_board: if g_sim = false generate
- board_inst : board
- port map (
+ board_inst : board
+ port map (
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
@@ -1513,6 +1526,6 @@ begin
reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
- );
+ );
end generate;
end str;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index deca506ed84e4395f8ee499a9cfd70dd56c8925f..5ce7c1400b58480578f729fbdbfdbd974d555b8f 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -25,212 +25,212 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
- reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_ring_reset_export : out std_logic; -- export
- ram_diag_bg_ring_clk_export : out std_logic; -- export
- ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_ring_write_export : out std_logic; -- export
- ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ring_read_export : out std_logic; -- export
- ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ring_reset_export : out std_logic; -- export
- reg_diag_bg_ring_clk_export : out std_logic; -- export
- reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ring_write_export : out std_logic; -- export
- reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ring_read_export : out std_logic; -- export
- reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_bg_reset_export : out std_logic; -- export
- reg_dp_xonoff_bg_clk_export : out std_logic; -- export
- reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_bg_write_export : out std_logic; -- export
- reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_bg_read_export : out std_logic; -- export
- reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
- reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ring_reset_export : out std_logic; -- export
+ ram_diag_bg_ring_clk_export : out std_logic; -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ring_write_export : out std_logic; -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ring_read_export : out std_logic; -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ring_reset_export : out std_logic; -- export
+ reg_diag_bg_ring_clk_export : out std_logic; -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ring_write_export : out std_logic; -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ring_read_export : out std_logic; -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_bg_reset_export : out std_logic; -- export
+ reg_dp_xonoff_bg_clk_export : out std_logic; -- export
+ reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_bg_write_export : out std_logic; -- export
+ reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_bg_read_export : out std_logic; -- export
+ reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -463,7 +463,6 @@ package top_components_pkg is
board_kernel_stream_snk_mm_io_data : out std_logic_vector(31 downto 0);
board_kernel_stream_snk_mm_io_valid : out std_logic;
board_kernel_stream_snk_mm_io_ready : out std_logic
- );
+ );
end component freeze_wrapper;
-
end top_components_pkg;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index 3af8c3fc2f25ce9d61ac987021c64ef9694a7b2a..8194075076a66fcf911d1e5e6bf66683369a34a3 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -32,17 +32,17 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, tech_ddr_lib, ta2_unb2b_40GbE_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_1gbe_lib, ta2_unb2b_mm_io_lib, ta2_unb2b_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
-use work.top_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use work.top_components_pkg.all;
entity top is
generic (
@@ -104,7 +104,7 @@ entity top is
RING_1_RX : in std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
- -- back transceivers
+ -- back transceivers
BCK_RX : in std_logic_vector(0 downto 0);
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -302,10 +302,10 @@ architecture str of top is
signal board_kernel_mem0_read : std_logic; -- := 'X'; -- write
signal board_kernel_mem0_byteenable : std_logic_vector(63 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_mem0_debugaccess : std_logic; -- := 'X'; -- write
--- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
--- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
--- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
+ -- SIGNAL amm_readdata : std_logic_vector(575 downto 0); -- readdata
+ -- SIGNAL amm_burstcount : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_writedata : std_logic_vector(575 downto 0); -- := (others => 'X'); -- address
+ -- SIGNAL amm_byteenable : std_logic_vector(71 downto 0); -- := (others => 'X'); -- byteenable
signal board_kernel_register_mem_address : std_logic_vector(6 downto 0); -- := (others => 'X'); -- address
signal board_kernel_register_mem_clken : std_logic; -- := 'X'; -- clken
@@ -356,21 +356,21 @@ begin
QSFP_1_TX <= i_QSFP_TX(1);
u_unb2b_board_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_front_io_serial_rx_arr,
- --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX -- ,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX -- ,
- --QSFP_LED => QSFP_LED
- );
+ --QSFP_LED => QSFP_LED
+ );
------------------------
-- qsfp LEDs controller
@@ -382,21 +382,21 @@ begin
unb2b_board_qsfp_leds_tx_src_in_arr(12).xon <= ta2_unb2b_40GbE_snk_out_arr(2).xon;
u_unb2b_board_qsfp_leds : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus + c_nof_ring_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_src_in_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus + c_nof_ring_bus - 1 downto 0)
+ );
gen_leds : for i in 0 to c_nof_qsfp_bus + c_nof_ring_bus - 1 generate
QSFP_LED(i * 2) <= qsfp_green_led_arr(i);
@@ -412,15 +412,15 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2b_board_lib.unb2b_board_ring_io
- generic map (
- g_nof_ring_bus => c_nof_ring_bus
- )
- port map (
- serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
+ generic map (
+ g_nof_ring_bus => c_nof_ring_bus
+ )
+ port map (
+ serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
+ serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
+ );
---------
-- 40GbE
@@ -438,26 +438,26 @@ begin
ta2_unb2b_40GbE_rx_serial_r(11 downto 8) <= unb2b_board_ring_io_serial_rx_arr(3 + c_ring_bus_w downto c_ring_bus_w);
u_ta2_unb2b_40GbE : entity ta2_unb2b_40GbE_lib.ta2_unb2b_40GbE
- generic map (
- g_nof_mac => c_nof_40GbE_IP
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_40GbE_IP
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_40GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_40GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_40GbE_src_out_arr,
- src_in_arr => ta2_unb2b_40GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_40GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_40GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_40GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_40GbE_snk_in_arr
+ );
----------
-- 10GbE
@@ -467,100 +467,100 @@ begin
ta2_unb2b_10GbE_rx_serial_r(0) <= unb2b_board_front_io_serial_rx_arr(0);
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- generic map (
- g_nof_mac => c_nof_10GbE_IP
- )
- port map (
- mm_clk => '0', -- mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_nof_mac => c_nof_10GbE_IP
+ )
+ port map (
+ mm_clk => '0', -- mm_clk,
+ mm_rst => mm_rst,
- clk_ref_r => SA_CLK,
+ clk_ref_r => SA_CLK,
- tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
- rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_10GbE_src_out_arr,
- src_in_arr => ta2_unb2b_10GbE_src_in_arr,
- snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
- snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
- );
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
+ );
-----------------------------
-- 1GbE Monitoring & Control
-----------------------------
u_ta2_unb2b_1GbE : entity ta2_unb2b_1GbE_lib.ta2_unb2b_1GbE
- port map (
- st_clk => st_clk,
- st_rst => st_rst,
+ port map (
+ st_clk => st_clk,
+ st_rst => st_rst,
- udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
- udp_tx_siso => eth1g_udp_tx_siso_arr(0),
- udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
- udp_rx_siso => eth1g_udp_rx_siso_arr(0),
+ udp_tx_sosi => eth1g_udp_tx_sosi_arr(0),
+ udp_tx_siso => eth1g_udp_tx_siso_arr(0),
+ udp_rx_sosi => eth1g_udp_rx_sosi_arr(0),
+ udp_rx_siso => eth1g_udp_rx_siso_arr(0),
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out => ta2_unb2b_1GbE_src_out,
- src_in => ta2_unb2b_1GbE_src_in,
- snk_out => ta2_unb2b_1GbE_snk_out,
- snk_in => ta2_unb2b_1GbE_snk_in
- );
+ src_out => ta2_unb2b_1GbE_src_out,
+ src_in => ta2_unb2b_1GbE_src_in,
+ snk_out => ta2_unb2b_1GbE_snk_out,
+ snk_in => ta2_unb2b_1GbE_snk_in
+ );
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
u_ta2_unb2b_mm_io : entity ta2_unb2b_mm_io_lib.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => true
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_opencl => true
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- mm_mosi => reg_ta2_unb2b_mm_io_mosi,
- mm_miso => reg_ta2_unb2b_mm_io_miso,
+ mm_mosi => reg_ta2_unb2b_mm_io_mosi,
+ mm_miso => reg_ta2_unb2b_mm_io_miso,
- snk_in => ta2_unb2b_mm_io_snk_in,
- snk_out => ta2_unb2b_mm_io_snk_out,
- src_out => ta2_unb2b_mm_io_src_out,
- src_in => ta2_unb2b_mm_io_src_in
+ snk_in => ta2_unb2b_mm_io_snk_in,
+ snk_out => ta2_unb2b_mm_io_snk_out,
+ src_out => ta2_unb2b_mm_io_src_out,
+ src_in => ta2_unb2b_mm_io_src_in
- );
+ );
----------
-- ADC
----------
u_ta2_unb2b_jesd204b : entity ta2_unb2b_jesd204b_lib.ta2_unb2b_jesd204b
- generic map(
- g_nof_streams => c_nof_ADC
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_nof_streams => c_nof_ADC
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
- jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
+ jesd204b_mosi => reg_ta2_unb2b_jesd204b_mosi,
+ jesd204b_miso => reg_ta2_unb2b_jesd204b_miso,
- -- JESD204B external signals
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => JESD204B_SYNC,
+ -- JESD204B external signals
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => JESD204B_SYNC,
- serial_rx_arr => BCK_RX,
+ serial_rx_arr => BCK_RX,
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_ADC_src_out_arr,
- src_in_arr => ta2_unb2b_ADC_src_in_arr
- );
+ src_out_arr => ta2_unb2b_ADC_src_out_arr,
+ src_in_arr => ta2_unb2b_ADC_src_in_arr
+ );
----------
-- DDR4
@@ -695,340 +695,340 @@ begin
-- Kernel should start later than BSP
u_common_areset : entity common_lib.common_areset
- generic map (
- g_rst_level => '0',
- g_delay_len => 9
- )
- port map (
- in_rst => i_kernel_rst,
- clk => board_kernel_clk_clk,
- out_rst => board_kernel_reset_reset_n_in
- );
+ generic map (
+ g_rst_level => '0',
+ g_delay_len => 9
+ )
+ port map (
+ in_rst => i_kernel_rst,
+ clk => board_kernel_clk_clk,
+ out_rst => board_kernel_reset_reset_n_in
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_udp_offload => c_use_1GbE_udp_offload,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- RAM scrap
- ram_scrap_mosi => c_mem_mosi_rst,
- ram_scrap_miso => OPEN,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_udp_offload => c_use_1GbE_udp_offload,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- RAM scrap
+ ram_scrap_mosi => c_mem_mosi_rst,
+ ram_scrap_miso => OPEN,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
board_inst : board
port map (
- clk_clk => mm_clk,
- reset_reset_n => i_reset_n,
-
- kernel_clk_clk => board_kernel_clk_clk,
- kernel_clk2x_clk => board_kernel_clk2x_clk,
- kernel_reset_reset_n => board_kernel_reset_reset_n,
-
- kernel_interface_sw_reset_in_reset => mm_rst,
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
- pio_wdi_external_connection_export => pout_wdi,
-
- avs_eth_0_reset_export => eth1g_mm_rst,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
- avs_eth_0_irq_export => eth1g_reg_interrupt,
-
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
-
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
-
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
-
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
-
- reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
-
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
-
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
-
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
-
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- reg_ta2_unb2b_jesd204b_address_export => reg_ta2_unb2b_jesd204b_mosi.address(7 downto 0),
- reg_ta2_unb2b_jesd204b_read_export => reg_ta2_unb2b_jesd204b_mosi.rd,
- reg_ta2_unb2b_jesd204b_readdata_export => reg_ta2_unb2b_jesd204b_miso.rddata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_jesd204b_write_export => reg_ta2_unb2b_jesd204b_mosi.wr,
- reg_ta2_unb2b_jesd204b_writedata_export => reg_ta2_unb2b_jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_jesd204b_waitrequest_export => reg_ta2_unb2b_jesd204b_miso.waitrequest,
-
- kernel_cra_waitrequest => board_kernel_cra_waitrequest,
- kernel_cra_readdata => board_kernel_cra_readdata,
- kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
- kernel_cra_burstcount => board_kernel_cra_burstcount,
- kernel_cra_writedata => board_kernel_cra_writedata,
- kernel_cra_address => board_kernel_cra_address,
- kernel_cra_write => board_kernel_cra_write,
- kernel_cra_read => board_kernel_cra_read,
- kernel_cra_byteenable => board_kernel_cra_byteenable,
- kernel_cra_debugaccess => board_kernel_cra_debugaccess,
-
- kernel_irq_irq => board_kernel_irq_irq,
-
- kernel_register_mem_address => board_kernel_register_mem_address,
- kernel_register_mem_clken => board_kernel_register_mem_clken,
- kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
- kernel_register_mem_write => board_kernel_register_mem_write,
- kernel_register_mem_readdata => board_kernel_register_mem_readdata,
- kernel_register_mem_writedata => board_kernel_register_mem_writedata,
- kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
-
- reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 downto 0),
- reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
- reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
- reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
- reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest,
-
- kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
- kernel_mem0_readdata => board_kernel_mem0_readdata,
- kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
- kernel_mem0_burstcount => board_kernel_mem0_burstcount,
- kernel_mem0_writedata => board_kernel_mem0_writedata,
- kernel_mem0_address => board_kernel_mem0_address,
- kernel_mem0_write => board_kernel_mem0_write,
- kernel_mem0_read => board_kernel_mem0_read,
- kernel_mem0_byteenable => board_kernel_mem0_byteenable,
- kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
-
- ddr4a_pll_ref_clk => MB_I_REF_CLK,
- ddr4a_oct_oct_rzqin => MB_I_IN.oct_rzqin,
- ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
- ddr4a_mem_ck_n => MB_I_OU.ck_n(g_tech_ddr.ck_w - 1 downto 0),
- ddr4a_mem_a => MB_I_OU.a(g_tech_ddr.a_w - 1 downto 0),
- sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
- ddr4a_mem_ba => MB_I_OU.ba(g_tech_ddr.ba_w - 1 downto 0),
- ddr4a_mem_bg => MB_I_OU.bg(g_tech_ddr.bg_w - 1 downto 0),
- ddr4a_mem_cke => MB_I_OU.cke(g_tech_ddr.cke_w - 1 downto 0),
- ddr4a_mem_cs_n => MB_I_OU.cs_n(g_tech_ddr.cs_w - 1 downto 0),
- ddr4a_mem_odt => MB_I_OU.odt(g_tech_ddr.odt_w - 1 downto 0),
- sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
- sl(ddr4a_mem_par) => MB_I_OU.par,
- ddr4a_mem_alert_n => slv(MB_I_IN.alert_n),
- ddr4a_mem_dqs => MB_I_IO.dqs(g_tech_ddr.dqs_w - 1 downto 0),
- ddr4a_mem_dqs_n => MB_I_IO.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
- ddr4a_mem_dq => MB_I_IO.dq(g_tech_ddr.dq_w - 1 downto 0),
- ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
+ clk_clk => mm_clk,
+ reset_reset_n => i_reset_n,
+
+ kernel_clk_clk => board_kernel_clk_clk,
+ kernel_clk2x_clk => board_kernel_clk2x_clk,
+ kernel_reset_reset_n => board_kernel_reset_reset_n,
+
+ kernel_interface_sw_reset_in_reset => mm_rst,
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
+ pio_wdi_external_connection_export => pout_wdi,
+
+ avs_eth_0_reset_export => eth1g_mm_rst,
+ avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+ avs_eth_0_irq_export => eth1g_reg_interrupt,
+
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w - 1 downto 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w - 1 downto 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w - 1 downto 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w - 1 downto 0),
+
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 4 downto 0), -- temp fix
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+
+ pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 2 downto 0), -- temp fix
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_wdi_address_export => reg_wdi_mosi.address(0 downto 0),
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ reg_remu_write_export => reg_remu_mosi.wr,
+ reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_remu_read_export => reg_remu_mosi.rd,
+ reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ reg_epcs_write_export => reg_epcs_mosi.wr,
+ reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_epcs_read_export => reg_epcs_mosi.rd,
+ reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 downto 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 downto 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 downto 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 downto 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ reg_ta2_unb2b_jesd204b_address_export => reg_ta2_unb2b_jesd204b_mosi.address(7 downto 0),
+ reg_ta2_unb2b_jesd204b_read_export => reg_ta2_unb2b_jesd204b_mosi.rd,
+ reg_ta2_unb2b_jesd204b_readdata_export => reg_ta2_unb2b_jesd204b_miso.rddata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_jesd204b_write_export => reg_ta2_unb2b_jesd204b_mosi.wr,
+ reg_ta2_unb2b_jesd204b_writedata_export => reg_ta2_unb2b_jesd204b_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_jesd204b_waitrequest_export => reg_ta2_unb2b_jesd204b_miso.waitrequest,
+
+ kernel_cra_waitrequest => board_kernel_cra_waitrequest,
+ kernel_cra_readdata => board_kernel_cra_readdata,
+ kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
+ kernel_cra_burstcount => board_kernel_cra_burstcount,
+ kernel_cra_writedata => board_kernel_cra_writedata,
+ kernel_cra_address => board_kernel_cra_address,
+ kernel_cra_write => board_kernel_cra_write,
+ kernel_cra_read => board_kernel_cra_read,
+ kernel_cra_byteenable => board_kernel_cra_byteenable,
+ kernel_cra_debugaccess => board_kernel_cra_debugaccess,
+
+ kernel_irq_irq => board_kernel_irq_irq,
+
+ kernel_register_mem_address => board_kernel_register_mem_address,
+ kernel_register_mem_clken => board_kernel_register_mem_clken,
+ kernel_register_mem_chipselect => board_kernel_register_mem_chipselect,
+ kernel_register_mem_write => board_kernel_register_mem_write,
+ kernel_register_mem_readdata => board_kernel_register_mem_readdata,
+ kernel_register_mem_writedata => board_kernel_register_mem_writedata,
+ kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
+
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 downto 0),
+ reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
+ reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
+ reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest,
+
+ kernel_mem0_waitrequest => board_kernel_mem0_waitrequest,
+ kernel_mem0_readdata => board_kernel_mem0_readdata,
+ kernel_mem0_readdatavalid => board_kernel_mem0_readdatavalid,
+ kernel_mem0_burstcount => board_kernel_mem0_burstcount,
+ kernel_mem0_writedata => board_kernel_mem0_writedata,
+ kernel_mem0_address => board_kernel_mem0_address,
+ kernel_mem0_write => board_kernel_mem0_write,
+ kernel_mem0_read => board_kernel_mem0_read,
+ kernel_mem0_byteenable => board_kernel_mem0_byteenable,
+ kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
+
+ ddr4a_pll_ref_clk => MB_I_REF_CLK,
+ ddr4a_oct_oct_rzqin => MB_I_IN.oct_rzqin,
+ ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
+ ddr4a_mem_ck_n => MB_I_OU.ck_n(g_tech_ddr.ck_w - 1 downto 0),
+ ddr4a_mem_a => MB_I_OU.a(g_tech_ddr.a_w - 1 downto 0),
+ sl(ddr4a_mem_act_n) => MB_I_OU.act_n,
+ ddr4a_mem_ba => MB_I_OU.ba(g_tech_ddr.ba_w - 1 downto 0),
+ ddr4a_mem_bg => MB_I_OU.bg(g_tech_ddr.bg_w - 1 downto 0),
+ ddr4a_mem_cke => MB_I_OU.cke(g_tech_ddr.cke_w - 1 downto 0),
+ ddr4a_mem_cs_n => MB_I_OU.cs_n(g_tech_ddr.cs_w - 1 downto 0),
+ ddr4a_mem_odt => MB_I_OU.odt(g_tech_ddr.odt_w - 1 downto 0),
+ sl(ddr4a_mem_reset_n) => MB_I_OU.reset_n,
+ sl(ddr4a_mem_par) => MB_I_OU.par,
+ ddr4a_mem_alert_n => slv(MB_I_IN.alert_n),
+ ddr4a_mem_dqs => MB_I_IO.dqs(g_tech_ddr.dqs_w - 1 downto 0),
+ ddr4a_mem_dqs_n => MB_I_IO.dqs_n(g_tech_ddr.dqs_w - 1 downto 0),
+ ddr4a_mem_dq => MB_I_IO.dq(g_tech_ddr.dq_w - 1 downto 0),
+ ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
);
end str;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index fa7090c8ba2cab2ffc8a579323e373cdef3c2eb5..fef9aaaf263f57e3693946a817d59f0e1ef22f71 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -25,199 +25,199 @@
-- . Contains components instantiated by top.vhd
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package top_components_pkg is
- component board is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
- kernel_register_mem_clken : in std_logic := 'X'; -- clken
- kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
- kernel_register_mem_write : in std_logic := 'X'; -- write
- kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
- kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
- kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_mem0_waitrequest : out std_logic; -- waitrequest
- kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
- kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
- kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
- kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
- kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
- kernel_mem0_write : in std_logic := 'X'; -- write
- kernel_mem0_read : in std_logic := 'X'; -- read
- kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
- ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
- ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
- ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
- reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
- reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component board;
+ component board is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ kernel_register_mem_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
+ kernel_register_mem_clken : in std_logic := 'X'; -- clken
+ kernel_register_mem_chipselect : in std_logic := 'X'; -- chipselect
+ kernel_register_mem_write : in std_logic := 'X'; -- write
+ kernel_register_mem_readdata : out std_logic_vector(255 downto 0); -- readdata
+ kernel_register_mem_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
+ kernel_register_mem_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_mem0_waitrequest : out std_logic; -- waitrequest
+ kernel_mem0_readdata : out std_logic_vector(511 downto 0); -- readdata
+ kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
+ kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
+ kernel_mem0_writedata : in std_logic_vector(511 downto 0) := (others => 'X'); -- writedata
+ kernel_mem0_address : in std_logic_vector(32 downto 0) := (others => 'X'); -- address
+ kernel_mem0_write : in std_logic := 'X'; -- write
+ kernel_mem0_read : in std_logic := 'X'; -- read
+ kernel_mem0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ ddr4a_pll_ref_clk : in std_logic := 'X'; -- clk
+ ddr4a_oct_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ ddr4a_mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ ddr4a_mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ ddr4a_mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ ddr4a_mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ ddr4a_mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ ddr4a_mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ ddr4a_mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ ddr4a_mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ ddr4a_mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ ddr4a_mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ ddr4a_mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ ddr4a_mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ ddr4a_mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
+ ddr4a_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
+ ddr4a_mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
+ ddr4a_mem_dbi_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dbi_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_jesd204b_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_read_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_jesd204b_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_waitrequest_export : in std_logic := 'X'; -- export
+ reg_ta2_unb2b_jesd204b_write_export : out std_logic; -- export
+ reg_ta2_unb2b_jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component board;
component freeze_wrapper is
port (
@@ -300,7 +300,6 @@ package top_components_pkg is
board_kernel_stream_src_ADC_data : in std_logic_vector(15 downto 0);
board_kernel_stream_src_ADC_valid : in std_logic;
board_kernel_stream_src_ADC_ready : out std_logic
- );
+ );
end component freeze_wrapper;
-
end top_components_pkg;
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 931a44d84138702620f0ed221b2c0a8252067b5c..74e9294fbc47cd73cce1ec96bbe1d420d3ae8b11 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -61,10 +61,10 @@
-- in mind that IO channels must be a multiple of 8 bits (bytes).
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity ta2_channel_cross is
generic (
@@ -128,69 +128,70 @@ begin
assert g_nof_bytes <= 32 report "g_nof_bytes of ta2_channel_cross is configured higher than 32" severity ERROR;
gen_streams: for stream in 0 to g_nof_streams - 1 generate
- -- dp_snk_in -> kernel_src_out
+ -- dp_snk_in -> kernel_src_out
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> kernel_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => dp_rst,
- wr_clk => dp_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_snk_out_arr(stream),
- snk_in => dp_snk_in_arr(stream),
-
- src_in => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_snk_in_arr(stream)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => dp_rst,
+ wr_clk => dp_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_snk_out_arr(stream),
+ snk_in => dp_snk_in_arr(stream),
+
+ src_in => dp_latency_adapter_tx_snk_out_arr(stream),
+ src_out => dp_latency_adapter_tx_snk_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => dp_latency_adapter_tx_src_out_arr(stream),
- src_in => dp_latency_adapter_tx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(stream),
+ src_in => dp_latency_adapter_tx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Data mapping
----------------------------------------------------------------------------
-- Reverse byte order
gen_reverse_rx_bytes : if g_reverse_bytes generate
+
gen_rx_bytes: for I in 0 to g_nof_bytes - 1 generate
kernel_src_out_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
end generate;
gen_no_reverse_rx_bytes : if not g_reverse_bytes generate
- kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
+ kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
end generate;
-- Assign control signals to correct data fields.
@@ -221,6 +222,7 @@ begin
----------------------------------------------------------------------------
-- Reverse byte order to correct for endianess
gen_reverse_tx_bytes : if g_reverse_bytes generate
+
gen_tx_bytes: for I in 0 to g_nof_bytes - 1 generate
dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= kernel_snk_in_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
@@ -255,49 +257,49 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
- snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: kernel_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_bsn_w,
- g_empty_w => c_empty_w,
- g_channel_w => c_channel_w,
- g_error_w => c_err_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => true,
- g_use_channel => g_use_channel,
- g_use_error => g_use_err,
- g_use_sync => g_use_sync,
- g_fifo_size => g_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
-
- snk_out => dp_latency_adapter_rx_src_in_arr(stream),
- snk_in => dp_latency_adapter_rx_src_out_arr(stream),
-
- src_in => dp_src_in_arr(stream),
- src_out => dp_src_out_arr(stream)
- );
- end generate;
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
+ g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => true,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+
+ snk_out => dp_latency_adapter_rx_src_in_arr(stream),
+ snk_in => dp_latency_adapter_rx_src_out_arr(stream),
+
+ src_in => dp_src_in_arr(stream),
+ src_out => dp_src_out_arr(stream)
+ );
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index be705c1148968cb8f78a3d0045ceaec9f8fe07a8..d04bd12819297d8827419a1c5443ed23850f3f5f 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -54,12 +54,12 @@
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_eth_10g_lib, tech_mac_10g_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
entity ta2_unb2b_10GbE is
generic (
@@ -137,17 +137,17 @@ begin
--------
g_pll : if g_use_pll generate
u_tech_pll_xgmii_mac_clocks : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg
- )
- port map (
- refclk_644 => clk_ref_r,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg
+ )
+ port map (
+ refclk_644 => clk_ref_r,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
end generate;
gen_no_pll : if not g_use_pll generate
@@ -161,32 +161,32 @@ begin
---------------------------------------------------------------------------------------
-- Apply the clocks from top level down such that they have their rising_edge() aligned without any delta-delay
u_tech_eth_10g_clocks : entity tech_eth_10g_lib.tech_eth_10g_clocks
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_nof_channels => g_nof_mac
- )
- port map (
- -- Input clocks
- -- . Reference
- tr_ref_clk_644 => clk_ref_r,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- Output clocks
- -- . Reference
- eth_ref_clk_644 => eth_ref_clk_644,
- eth_ref_clk_312 => eth_ref_clk_312,
- eth_ref_clk_156 => eth_ref_clk_156,
- eth_ref_rst_156 => eth_ref_rst_156,
-
- -- . Data
- eth_tx_clk_arr => eth_tx_clk_arr,
- eth_tx_rst_arr => eth_tx_rst_arr,
-
- eth_rx_clk_arr => eth_rx_clk_arr,
- eth_rx_rst_arr => eth_rx_rst_arr
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_nof_channels => g_nof_mac
+ )
+ port map (
+ -- Input clocks
+ -- . Reference
+ tr_ref_clk_644 => clk_ref_r,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- Output clocks
+ -- . Reference
+ eth_ref_clk_644 => eth_ref_clk_644,
+ eth_ref_clk_312 => eth_ref_clk_312,
+ eth_ref_clk_156 => eth_ref_clk_156,
+ eth_ref_rst_156 => eth_ref_rst_156,
+
+ -- . Data
+ eth_tx_clk_arr => eth_tx_clk_arr,
+ eth_tx_rst_arr => eth_tx_rst_arr,
+
+ eth_rx_clk_arr => eth_rx_clk_arr,
+ eth_rx_rst_arr => eth_rx_rst_arr
+ );
gen_mac: for mac in 0 to g_nof_mac - 1 generate
----------------------------------------------------------------------------
@@ -213,104 +213,104 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
+ snk_in => dp_latency_adapter_tx_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_snk_out_arr(mac),
- src_out => dp_latency_adapter_tx_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_src_in_arr(mac)
+ );
-----------------------------------------------------------------------------
-- RX XON frame control
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in_arr(mac),
- in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac)
- );
+ out_siso => dp_xonoff_src_in_arr(mac),
+ out_sosi => dp_xonoff_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- FIFO FILL with fill level/eop trigger so we can deliver packets to the MAC fast enough
---------------------------------------------------------------------------------------
u_dp_fifo_fill_tx_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_use_dual_clock => true,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_fill => c_tx_fifo_fill,
- g_fifo_size => c_tx_fifo_size
- )
- port map (
- wr_rst => kernel_reset,
- wr_clk => kernel_clk,
- rd_rst => eth_tx_rst_arr(mac),
- rd_clk => eth_tx_clk_arr(mac),
-
- snk_out => dp_xonoff_src_in_arr(mac),
- snk_in => dp_xonoff_src_out_arr(mac),
-
- src_in => dp_fifo_fill_tx_src_in_arr(mac),
- src_out => dp_fifo_fill_tx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_use_dual_clock => true,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_fill => c_tx_fifo_fill,
+ g_fifo_size => c_tx_fifo_size
+ )
+ port map (
+ wr_rst => kernel_reset,
+ wr_clk => kernel_clk,
+ rd_rst => eth_tx_rst_arr(mac),
+ rd_clk => eth_tx_clk_arr(mac),
+
+ snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+
+ src_in => dp_fifo_fill_tx_src_in_arr(mac),
+ src_out => dp_fifo_fill_tx_src_out_arr(mac)
+ );
---------------------------------------------------------------------------------------
-- RX FIFO: rx_clk -> dp_clk
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => c_xgmii_data_w,
- g_empty_w => c_tech_mac_10g_empty_w,
- g_use_empty => true,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => eth_rx_rst_arr(mac),
- wr_clk => eth_rx_clk_arr(mac),
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => mac_10g_src_in_arr(mac),
- snk_in => mac_10g_src_out_arr(mac),
-
- src_in => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_fifo_dc_rx_src_out_arr(mac)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => c_xgmii_data_w,
+ g_empty_w => c_tech_mac_10g_empty_w,
+ g_use_empty => true,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => eth_rx_rst_arr(mac),
+ wr_clk => eth_rx_clk_arr(mac),
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => mac_10g_src_in_arr(mac),
+ snk_in => mac_10g_src_out_arr(mac),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(mac),
+ src_out => dp_fifo_dc_rx_src_out_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_rx_src_out_arr(mac),
- snk_out => dp_fifo_dc_rx_src_in_arr(mac),
+ snk_in => dp_fifo_dc_rx_src_out_arr(mac),
+ snk_out => dp_fifo_dc_rx_src_in_arr(mac),
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -331,41 +331,41 @@ begin
src_out_arr(mac).valid <= dp_latency_adapter_rx_src_out_arr(mac).valid;
dp_latency_adapter_rx_src_in_arr(mac).ready <= src_in_arr(mac).ready;
dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
- end generate;
+ end generate;
---------------------------------------------------------------------------------------
-- ETH MAC + PHY
---------------------------------------------------------------------------------------
u_tech_eth_10g : entity tech_eth_10g_lib.tech_eth_10g
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
- g_nof_channels => g_nof_mac,
- g_direction => "TX_RX",
- g_pre_header_padding => false
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM
- mm_clk => '0',
- mm_rst => '0',
-
- -- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
-
- rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
- rx_src_in_arr => mac_10g_src_in_arr,
-
- -- PHY serial IO
- -- . 10GBASE-R (single lane)
- serial_tx_arr => tx_serial_r,
- serial_rx_arr => rx_serial_r
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => c_sim,
+ g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels => g_nof_mac,
+ g_direction => "TX_RX",
+ g_pre_header_padding => false
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM
+ mm_clk => '0',
+ mm_rst => '0',
+
+ -- ST
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
+
+ rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ rx_src_in_arr => mac_10g_src_in_arr,
+
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => tx_serial_r,
+ serial_rx_arr => rx_serial_r
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index cd1da9699604da0e661e12c8a19e9b5af176e786..2c70b0b5d0c96434a1a74f4a8b7301c22cd53f14 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -44,11 +44,11 @@
-- | [38:39] | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_1GbE is
port (
@@ -92,8 +92,8 @@ architecture str of ta2_unb2b_1GbE is
signal dp_xonoff_src_out : t_dp_sosi;
signal dp_xonoff_src_in : t_dp_siso;
begin
--------------------------------------------------------
- -- Mapping Data from OpenCL kernel to 1GbE Interface --
+ -------------------------------------------------------
+ -- Mapping Data from OpenCL kernel to 1GbE Interface --
-------------------------------------------------------
----------------------------------------------------------------------------
@@ -116,42 +116,42 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_latency_adapter_tx_snk_in,
- snk_out => dp_latency_adapter_tx_snk_out,
-
- src_out => dp_latency_adapter_tx_src_out,
- src_in => dp_latency_adapter_tx_src_in
- );
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_latency_adapter_tx_snk_in,
+ snk_out => dp_latency_adapter_tx_snk_out,
+
+ src_out => dp_latency_adapter_tx_src_out,
+ src_in => dp_latency_adapter_tx_src_in
+ );
-----------------------------------------------------------------------------
-- TX XON frame control
-----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- rst => kernel_reset,
- clk => kernel_clk,
+ port map (
+ rst => kernel_reset,
+ clk => kernel_clk,
- in_siso => dp_latency_adapter_tx_src_in,
- in_sosi => dp_latency_adapter_tx_src_out,
+ in_siso => dp_latency_adapter_tx_src_in,
+ in_sosi => dp_latency_adapter_tx_src_out,
- out_siso => dp_xonoff_src_in,
- out_sosi => dp_xonoff_src_out
- );
+ out_siso => dp_xonoff_src_in,
+ out_sosi => dp_xonoff_src_out
+ );
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_tx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -172,14 +172,14 @@ begin
src_out => udp_tx_sosi
);
--------------------------------------------------------
- -- Mapping Data from 1GbE Interface to OpenCL kernel --
+ -------------------------------------------------------
+ -- Mapping Data from 1GbE Interface to OpenCL kernel --
-------------------------------------------------------
-----------------------------------------------------------------------------
-- TX dual clock FIFO
-----------------------------------------------------------------------------
- u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_word_w,
@@ -204,20 +204,20 @@ begin
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
-
- snk_in => dp_fifo_dc_rx_src_out,
- snk_out => dp_fifo_dc_rx_src_in,
-
- src_out => dp_latency_adapter_rx_src_out,
- src_in => dp_latency_adapter_rx_src_in
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
+
+ snk_in => dp_fifo_dc_rx_src_out,
+ snk_out => dp_fifo_dc_rx_src_in,
+
+ src_out => dp_latency_adapter_rx_src_out,
+ src_in => dp_latency_adapter_rx_src_in
+ );
----------------------------------------------------------------------------
-- Data mapping
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 1083a6bc1589f0b8464b7266b90955fc2250ec08..a312fdb2f606fad568501f66ee98b00a8c9d0282 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_1GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_1GbE_ip_wrapper is
port (
@@ -66,68 +66,68 @@ architecture str of ta2_unb2b_1GbE_ip_wrapper is
-- ta2_unb2b_1GbE Component
----------------------------------------------------------------------------
component ta2_unb2b_1GbE is
- port (
- st_clk : in std_logic;
- st_rst : in std_logic;
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_data : out std_logic_vector(39 downto 0);
- udp_tx_sosi_valid : out std_logic;
- udp_tx_sosi_sop : out std_logic;
- udp_tx_sosi_eop : out std_logic;
- udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
- udp_tx_siso_ready : in std_logic;
- udp_tx_siso_xon : in std_logic;
-
- udp_rx_sosi_data : in std_logic_vector(39 downto 0);
- udp_rx_sosi_valid : in std_logic;
- udp_rx_sosi_sop : in std_logic;
- udp_rx_sosi_eop : in std_logic;
- udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
- udp_rx_siso_ready : out std_logic;
- udp_rx_siso_xon : out std_logic;
-
- kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
- kernel_reset : in std_logic;
-
- kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
- kernel_src_valid : out std_logic; -- RX data valid signal to kernel
- kernel_src_ready : in std_logic; -- Flow control from kernel
-
- kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
- kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
- kernel_snk_ready : out std_logic -- Flow control towards kernel
- );
+ port (
+ st_clk : in std_logic;
+ st_rst : in std_logic;
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_data : out std_logic_vector(39 downto 0);
+ udp_tx_sosi_valid : out std_logic;
+ udp_tx_sosi_sop : out std_logic;
+ udp_tx_sosi_eop : out std_logic;
+ udp_tx_sosi_empty : out std_logic_vector(1 downto 0);
+ udp_tx_siso_ready : in std_logic;
+ udp_tx_siso_xon : in std_logic;
+
+ udp_rx_sosi_data : in std_logic_vector(39 downto 0);
+ udp_rx_sosi_valid : in std_logic;
+ udp_rx_sosi_sop : in std_logic;
+ udp_rx_sosi_eop : in std_logic;
+ udp_rx_sosi_empty : in std_logic_vector(1 downto 0);
+ udp_rx_siso_ready : out std_logic;
+ udp_rx_siso_xon : out std_logic;
+
+ kernel_clk : in std_logic; -- Kernel clock (runs the kernel_* I/O below)
+ kernel_reset : in std_logic;
+
+ kernel_src_data : out std_logic_vector(39 downto 0); -- RX Data to kernel
+ kernel_src_valid : out std_logic; -- RX data valid signal to kernel
+ kernel_src_ready : in std_logic; -- Flow control from kernel
+
+ kernel_snk_data : in std_logic_vector(39 downto 0); -- TX Data from kernel
+ kernel_snk_valid : in std_logic; -- TX data valid signal from kernel
+ kernel_snk_ready : out std_logic -- Flow control towards kernel
+ );
end component ta2_unb2b_1GbE;
begin
u_ta2_unb2b_1GbE : ta2_unb2b_1GbE
- port map (
- st_clk => st_clk,
- st_rst => st_rst,
-
- udp_tx_sosi_data => udp_tx_sosi_data,
- udp_tx_sosi_valid => udp_tx_sosi_valid,
- udp_tx_sosi_sop => udp_tx_sosi_sop,
- udp_tx_sosi_eop => udp_tx_sosi_eop,
- udp_tx_sosi_empty => udp_tx_sosi_empty,
- udp_tx_siso_ready => udp_tx_siso_ready,
- udp_tx_siso_xon => udp_tx_siso_xon,
-
- udp_rx_sosi_data => udp_rx_sosi_data,
- udp_rx_sosi_valid => udp_rx_sosi_valid,
- udp_rx_sosi_sop => udp_rx_sosi_sop,
- udp_rx_sosi_eop => udp_rx_sosi_eop,
- udp_rx_sosi_empty => udp_rx_sosi_empty,
- udp_rx_siso_ready => udp_rx_siso_ready,
- udp_rx_siso_xon => udp_rx_siso_xon,
-
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
- kernel_src_data => kernel_src_data ,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready,
- kernel_snk_data => kernel_snk_data,
- kernel_snk_valid => kernel_snk_valid,
- kernel_snk_ready => kernel_snk_ready
- );
+ port map (
+ st_clk => st_clk,
+ st_rst => st_rst,
+
+ udp_tx_sosi_data => udp_tx_sosi_data,
+ udp_tx_sosi_valid => udp_tx_sosi_valid,
+ udp_tx_sosi_sop => udp_tx_sosi_sop,
+ udp_tx_sosi_eop => udp_tx_sosi_eop,
+ udp_tx_sosi_empty => udp_tx_sosi_empty,
+ udp_tx_siso_ready => udp_tx_siso_ready,
+ udp_tx_siso_xon => udp_tx_siso_xon,
+
+ udp_rx_sosi_data => udp_rx_sosi_data,
+ udp_rx_sosi_valid => udp_rx_sosi_valid,
+ udp_rx_sosi_sop => udp_rx_sosi_sop,
+ udp_rx_sosi_eop => udp_rx_sosi_eop,
+ udp_rx_sosi_empty => udp_rx_sosi_empty,
+ udp_rx_siso_ready => udp_rx_siso_ready,
+ udp_rx_siso_xon => udp_rx_siso_xon,
+
+ kernel_clk => kernel_clk,
+ kernel_reset => kernel_reset,
+ kernel_src_data => kernel_src_data ,
+ kernel_src_valid => kernel_src_valid,
+ kernel_src_ready => kernel_src_ready,
+ kernel_snk_data => kernel_snk_data,
+ kernel_snk_valid => kernel_snk_valid,
+ kernel_snk_ready => kernel_snk_ready
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 44b951b237f233c191c40d984a4b9a66e3091ff4..01b59b5b6417ec807c188694caaac68929eed9e7 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -51,9 +51,9 @@
-- | 259:263 | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity ta2_unb2b_40GbE is
generic (
@@ -152,118 +152,118 @@ architecture str of ta2_unb2b_40GbE is
-- ATX PLL Component
----------------------------------------------------------------------------
component arria10_40g_atx_pll is
- port (
- pll_cal_busy : out std_logic; -- pll_cal_busy
- pll_locked : out std_logic; -- pll_locked
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_clk : out std_logic -- clk
- );
+ port (
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ pll_locked : out std_logic; -- pll_locked
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_clk : out std_logic -- clk
+ );
end component arria10_40g_atx_pll;
----------------------------------------------------------------------------
-- 40G ETH IP Component
----------------------------------------------------------------------------
component arria10_40g_mac is
- port (
- l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
- l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
- l4_rx_valid : out std_logic; -- l4_rx_valid
- l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
- l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
- l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
- l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
- l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
- l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
- l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
- l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
- l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
- l4_tx_ready : out std_logic; -- l4_tx_ready
- l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
- l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
- l4_tx_error : in std_logic := 'X'; -- l4_tx_error
- clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
- clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
- clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
- clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
- reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
- reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
- reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
- reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
- reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
- reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
- reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
- reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
- reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
- reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
- rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
- rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
- rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
- rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
- rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
- rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
- rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
- rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
- rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
- rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
- rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
- rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
- rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
- rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
- rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
- rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
- rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
- rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
- rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
- rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
- rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
- rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
- rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
- rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
- rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
- rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
- rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
- rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
- rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
- rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
- rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
- status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
- status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
- status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
- status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
- status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
- status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
- status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
- status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
- tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
- tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
- tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
- tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
- tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
- tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
- tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
- tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
- tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
- tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
- tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
- tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
- tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
- tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
- tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
- tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
- tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
- tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
- tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
- tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
- tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
- tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
- tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
- tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
- tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
- tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
- tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
- tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
- );
+ port (
+ l4_rx_error : out std_logic_vector(5 downto 0); -- l4_rx_error
+ l4_rx_status : out std_logic_vector(2 downto 0); -- l4_rx_status
+ l4_rx_valid : out std_logic; -- l4_rx_valid
+ l4_rx_startofpacket : out std_logic; -- l4_rx_startofpacket
+ l4_rx_endofpacket : out std_logic; -- l4_rx_endofpacket
+ l4_rx_data : out std_logic_vector(255 downto 0); -- l4_rx_data
+ l4_rx_empty : out std_logic_vector(4 downto 0); -- l4_rx_empty
+ l4_rx_fcs_error : out std_logic; -- l4_rx_fcs_error
+ l4_rx_fcs_valid : out std_logic; -- l4_rx_fcs_valid
+ l4_tx_startofpacket : in std_logic := 'X'; -- l4_tx_startofpacket
+ l4_tx_endofpacket : in std_logic := 'X'; -- l4_tx_endofpacket
+ l4_tx_valid : in std_logic := 'X'; -- l4_tx_valid
+ l4_tx_ready : out std_logic; -- l4_tx_ready
+ l4_tx_empty : in std_logic_vector(4 downto 0) := (others => 'X'); -- l4_tx_empty
+ l4_tx_data : in std_logic_vector(255 downto 0) := (others => 'X'); -- l4_tx_data
+ l4_tx_error : in std_logic := 'X'; -- l4_tx_error
+ clk_ref : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_ref
+ clk_rxmac : out std_logic_vector(0 downto 0); -- clk_rxmac
+ clk_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk_status
+ clk_txmac : out std_logic_vector(0 downto 0); -- clk_txmac
+ reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- reconfig_address
+ reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_clk
+ reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_read
+ reconfig_readdata : out std_logic_vector(31 downto 0); -- reconfig_readdata
+ reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_reset
+ reconfig_waitrequest : out std_logic_vector(0 downto 0); -- reconfig_waitrequest
+ reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- reconfig_write
+ reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- reconfig_writedata
+ reset_async : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_async
+ reset_status : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset_status
+ rx_pcs_ready : out std_logic_vector(0 downto 0); -- rx_pcs_ready
+ rx_serial : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_serial
+ rx_inc_octetsOK : out std_logic_vector(15 downto 0); -- rx_inc_octetsOK
+ rx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- rx_inc_octetsOK_valid
+ rx_inc_runt : out std_logic_vector(0 downto 0); -- rx_inc_runt
+ rx_inc_64 : out std_logic_vector(0 downto 0); -- rx_inc_64
+ rx_inc_127 : out std_logic_vector(0 downto 0); -- rx_inc_127
+ rx_inc_255 : out std_logic_vector(0 downto 0); -- rx_inc_255
+ rx_inc_511 : out std_logic_vector(0 downto 0); -- rx_inc_511
+ rx_inc_1023 : out std_logic_vector(0 downto 0); -- rx_inc_1023
+ rx_inc_1518 : out std_logic_vector(0 downto 0); -- rx_inc_1518
+ rx_inc_max : out std_logic_vector(0 downto 0); -- rx_inc_max
+ rx_inc_over : out std_logic_vector(0 downto 0); -- rx_inc_over
+ rx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_err
+ rx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_mcast_data_ok
+ rx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_err
+ rx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_bcast_data_ok
+ rx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_err
+ rx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- rx_inc_ucast_data_ok
+ rx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl
+ rx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl
+ rx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl
+ rx_inc_pause : out std_logic_vector(0 downto 0); -- rx_inc_pause
+ rx_inc_fcs_err : out std_logic_vector(0 downto 0); -- rx_inc_fcs_err
+ rx_inc_fragment : out std_logic_vector(0 downto 0); -- rx_inc_fragment
+ rx_inc_jabber : out std_logic_vector(0 downto 0); -- rx_inc_jabber
+ rx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0); -- rx_inc_sizeok_fcserr
+ rx_inc_pause_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_pause_ctrl_err
+ rx_inc_mcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_mcast_ctrl_err
+ rx_inc_bcast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_bcast_ctrl_err
+ rx_inc_ucast_ctrl_err : out std_logic_vector(0 downto 0); -- rx_inc_ucast_ctrl_err
+ status_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_write
+ status_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- status_read
+ status_addr : in std_logic_vector(15 downto 0) := (others => 'X'); -- status_addr
+ status_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- status_writedata
+ status_readdata : out std_logic_vector(31 downto 0); -- status_readdata
+ status_readdata_valid : out std_logic_vector(0 downto 0); -- status_readdata_valid
+ status_waitrequest : out std_logic_vector(0 downto 0); -- status_waitrequest
+ status_read_timeout : out std_logic_vector(0 downto 0); -- status_read_timeout
+ tx_lanes_stable : out std_logic_vector(0 downto 0); -- tx_lanes_stable
+ tx_pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_pll_locked
+ tx_serial : out std_logic_vector(3 downto 0); -- tx_serial
+ tx_serial_clk : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_serial_clk
+ tx_inc_octetsOK : out std_logic_vector(15 downto 0); -- tx_inc_octetsOK
+ tx_inc_octetsOK_valid : out std_logic_vector(0 downto 0); -- tx_inc_octetsOK_valid
+ tx_inc_64 : out std_logic_vector(0 downto 0); -- tx_inc_64
+ tx_inc_127 : out std_logic_vector(0 downto 0); -- tx_inc_127
+ tx_inc_255 : out std_logic_vector(0 downto 0); -- tx_inc_255
+ tx_inc_511 : out std_logic_vector(0 downto 0); -- tx_inc_511
+ tx_inc_1023 : out std_logic_vector(0 downto 0); -- tx_inc_1023
+ tx_inc_1518 : out std_logic_vector(0 downto 0); -- tx_inc_1518
+ tx_inc_max : out std_logic_vector(0 downto 0); -- tx_inc_max
+ tx_inc_over : out std_logic_vector(0 downto 0); -- tx_inc_over
+ tx_inc_mcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_err
+ tx_inc_mcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_mcast_data_ok
+ tx_inc_bcast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_err
+ tx_inc_bcast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_bcast_data_ok
+ tx_inc_ucast_data_err : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_err
+ tx_inc_ucast_data_ok : out std_logic_vector(0 downto 0); -- tx_inc_ucast_data_ok
+ tx_inc_mcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_mcast_ctrl
+ tx_inc_bcast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_bcast_ctrl
+ tx_inc_ucast_ctrl : out std_logic_vector(0 downto 0); -- tx_inc_ucast_ctrl
+ tx_inc_pause : out std_logic_vector(0 downto 0); -- tx_inc_pause
+ tx_inc_fcs_err : out std_logic_vector(0 downto 0); -- tx_inc_fcs_err
+ tx_inc_fragment : out std_logic_vector(0 downto 0); -- tx_inc_fragment
+ tx_inc_jabber : out std_logic_vector(0 downto 0); -- tx_inc_jabber
+ tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
+ );
end component arria10_40g_mac;
begin
gen_mac: for mac in 0 to g_nof_mac - 1 generate
@@ -287,84 +287,84 @@ begin
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (downstream).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_a : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 0,
- g_out_latency => 1
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 0,
+ g_out_latency => 1
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
- snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
+ snk_in => dp_latency_adapter_tx_a_snk_in_arr(mac),
+ snk_out => dp_latency_adapter_tx_a_snk_out_arr(mac),
- src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_a_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_a_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- dp_xonoff: discard all TX frames until 40G MAC TX side is ready
----------------------------------------------------------------------------
u_dp_xonoff : entity dp_lib.dp_xonoff
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
- in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
+ in_sosi => dp_latency_adapter_tx_a_src_out_arr(mac),
+ in_siso => dp_latency_adapter_tx_a_src_in_arr(mac),
- out_sosi => dp_xonoff_src_out_arr(mac),
- out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
- );
+ out_sosi => dp_xonoff_src_out_arr(mac),
+ out_siso => dp_xonoff_src_in_arr(mac) -- flush control via out_siso.xon
+ );
----------------------------------------------------------------------------
-- TX FIFO
----------------------------------------------------------------------------
u_dp_fifo_fill_eop : entity dp_lib.dp_fifo_fill_eop
- generic map (
- g_data_w => c_data_w,
- g_use_dual_clock => true,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_tx_fifo_size,
- g_fifo_fill => c_tx_fifo_fill
- )
- port map (
- wr_clk => kernel_clk,
- wr_rst => kernel_reset,
+ generic map (
+ g_data_w => c_data_w,
+ g_use_dual_clock => true,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_tx_fifo_size,
+ g_fifo_fill => c_tx_fifo_fill
+ )
+ port map (
+ wr_clk => kernel_clk,
+ wr_rst => kernel_reset,
- rd_clk => clk_txmac_arr(mac),
- rd_rst => rst_txmac_arr(mac),
+ rd_clk => clk_txmac_arr(mac),
+ rd_rst => rst_txmac_arr(mac),
- snk_in => dp_xonoff_src_out_arr(mac),
- snk_out => dp_xonoff_src_in_arr(mac),
+ snk_in => dp_xonoff_src_out_arr(mac),
+ snk_out => dp_xonoff_src_in_arr(mac),
- src_out => dp_fifo_fill_eop_src_out_arr(mac),
- src_in => dp_fifo_fill_eop_src_in_arr(mac)
- );
+ src_out => dp_fifo_fill_eop_src_out_arr(mac),
+ src_in => dp_fifo_fill_eop_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (upstream) to RL=0 (MAC TX interface).
----------------------------------------------------------------------------
u_dp_latency_adapter_tx_b : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => clk_txmac_arr(mac),
- rst => rst_txmac_arr(mac),
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => clk_txmac_arr(mac),
+ rst => rst_txmac_arr(mac),
- snk_in => dp_fifo_fill_eop_src_out_arr(mac),
- snk_out => dp_fifo_fill_eop_src_in_arr(mac),
+ snk_in => dp_fifo_fill_eop_src_out_arr(mac),
+ snk_out => dp_fifo_fill_eop_src_in_arr(mac),
- src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
- src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_tx_b_src_out_arr(mac),
+ src_in => dp_latency_adapter_tx_b_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- 40G MAC IP
@@ -373,112 +373,112 @@ begin
dp_latency_adapter_tx_b_src_in_arr(mac) <= l4_tx_siso_arr(mac);
u_arria10_40g_mac : arria10_40g_mac
- port map (
- reset_async(0) => mm_rst,
- clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
- clk_ref(0) => clk_ref_r,
- rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
-
- tx_serial_clk => serial_clk_2arr(mac),
- tx_pll_locked(0) => pll_locked_arr(mac),
-
- clk_status(0) => mm_clk,
- reset_status(0) => mm_rst,
- status_addr => (others => '0'),
- status_read => (others => '0'),
- status_write => (others => '0'),
- status_writedata => (others => '0'),
--- status_readdata => status_readdata_eth,
--- status_read_timeout => status_read_timeout,
--- status_readdata_valid => status_readdata_valid_eth,
-
- reconfig_clk(0) => mm_clk,
- reconfig_reset(0) => mm_rst,
- reconfig_write => (others => '0'),
- reconfig_read => (others => '0'),
- reconfig_address => (others => '0'),
- reconfig_writedata => (others => '0'),
--- reconfig_readdata => reco_readdata[31:0],
--- reconfig_waitrequest => reco_waitrequest,
-
- l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
- l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
- l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
- l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
- l4_tx_ready => l4_tx_siso_arr(mac).ready,
- l4_tx_valid => l4_tx_sosi_arr(mac).valid,
- l4_tx_error => '0',
-
- l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
- l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
- l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
- l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
- -- l4_rx_error => ,
- l4_rx_valid => l4_rx_sosi_arr(mac).valid,
-
- -- l4_rx_status (),
- -- l4_rx_fcs_error (),
- -- l4_rx_fcs_valid (),
- -- rx_inc_octetsOK (),
- -- rx_inc_octetsOK_valid (),
- -- rx_inc_runt (),
- -- rx_inc_64 (),
- -- rx_inc_127 (),
- -- rx_inc_255 (),
- -- rx_inc_511 (),
- -- rx_inc_1023 (),
- -- rx_inc_1518 (),
- -- rx_inc_max (),
- -- rx_inc_over (),
- -- rx_inc_mcast_data_err (),
- -- rx_inc_mcast_data_ok (),
- -- rx_inc_bcast_data_err (),
- -- rx_inc_bcast_data_ok (),
- -- rx_inc_ucast_data_err (),
- -- rx_inc_ucast_data_ok (),
- -- rx_inc_mcast_ctrl (),
- -- rx_inc_bcast_ctrl (),
- -- rx_inc_ucast_ctrl (),
- -- rx_inc_pause (),
- -- rx_inc_fcs_err (),
- -- rx_inc_fragment (),
- -- rx_inc_jabber (),
- -- rx_inc_sizeok_fcserr (),
- -- rx_inc_pause_ctrl_err (),
- -- rx_inc_mcast_ctrl_err (),
- -- rx_inc_bcast_ctrl_err (),
- -- rx_inc_ucast_ctrl_err (),
- -- status_waitrequest (),
- tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
- -- tx_inc_octetsOK (),
- -- tx_inc_octetsOK_valid (),
- -- tx_inc_64 (),
- -- tx_inc_127 (),
- -- tx_inc_255 (),
- -- tx_inc_511 (),
- -- tx_inc_1023 (),
- -- tx_inc_1518 (),
- -- tx_inc_max (),
- -- tx_inc_over (),
- -- tx_inc_mcast_data_err (),
- -- tx_inc_mcast_data_ok (),
- -- tx_inc_bcast_data_err (),
- -- tx_inc_bcast_data_ok (),
- -- tx_inc_ucast_data_err (),
- -- tx_inc_ucast_data_ok (),
- -- tx_inc_mcast_ctrl (),
- -- tx_inc_bcast_ctrl (),
- -- tx_inc_ucast_ctrl (),
- -- tx_inc_pause (),
- -- tx_inc_fcs_err (),
- -- tx_inc_fragment (),
- -- tx_inc_jabber (),
- -- tx_inc_sizeok_fcserr (),
-
- tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
- rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
- );
+ port map (
+ reset_async(0) => mm_rst,
+ clk_txmac(0) => clk_txmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_rxmac(0) => clk_rxmac_arr(mac), -- MAC + PCS clock - at least 312.5Mhz
+ clk_ref(0) => clk_ref_r,
+ rx_pcs_ready(0) => rx_pcs_ready_arr(mac),
+
+ tx_serial_clk => serial_clk_2arr(mac),
+ tx_pll_locked(0) => pll_locked_arr(mac),
+
+ clk_status(0) => mm_clk,
+ reset_status(0) => mm_rst,
+ status_addr => (others => '0'),
+ status_read => (others => '0'),
+ status_write => (others => '0'),
+ status_writedata => (others => '0'),
+ -- status_readdata => status_readdata_eth,
+ -- status_read_timeout => status_read_timeout,
+ -- status_readdata_valid => status_readdata_valid_eth,
+
+ reconfig_clk(0) => mm_clk,
+ reconfig_reset(0) => mm_rst,
+ reconfig_write => (others => '0'),
+ reconfig_read => (others => '0'),
+ reconfig_address => (others => '0'),
+ reconfig_writedata => (others => '0'),
+ -- reconfig_readdata => reco_readdata[31:0],
+ -- reconfig_waitrequest => reco_waitrequest,
+
+ l4_tx_data => l4_tx_sosi_arr(mac).data(255 downto 0),
+ l4_tx_empty => l4_tx_sosi_arr(mac).empty(4 downto 0),
+ l4_tx_startofpacket => l4_tx_sosi_arr(mac).sop,
+ l4_tx_endofpacket => l4_tx_sosi_arr(mac).eop,
+ l4_tx_ready => l4_tx_siso_arr(mac).ready,
+ l4_tx_valid => l4_tx_sosi_arr(mac).valid,
+ l4_tx_error => '0',
+
+ l4_rx_data => l4_rx_sosi_arr(mac).data(255 downto 0),
+ l4_rx_empty => l4_rx_sosi_arr(mac).empty(4 downto 0),
+ l4_rx_startofpacket => l4_rx_sosi_arr(mac).sop,
+ l4_rx_endofpacket => l4_rx_sosi_arr(mac).eop,
+ -- l4_rx_error => ,
+ l4_rx_valid => l4_rx_sosi_arr(mac).valid,
+
+ -- l4_rx_status (),
+ -- l4_rx_fcs_error (),
+ -- l4_rx_fcs_valid (),
+ -- rx_inc_octetsOK (),
+ -- rx_inc_octetsOK_valid (),
+ -- rx_inc_runt (),
+ -- rx_inc_64 (),
+ -- rx_inc_127 (),
+ -- rx_inc_255 (),
+ -- rx_inc_511 (),
+ -- rx_inc_1023 (),
+ -- rx_inc_1518 (),
+ -- rx_inc_max (),
+ -- rx_inc_over (),
+ -- rx_inc_mcast_data_err (),
+ -- rx_inc_mcast_data_ok (),
+ -- rx_inc_bcast_data_err (),
+ -- rx_inc_bcast_data_ok (),
+ -- rx_inc_ucast_data_err (),
+ -- rx_inc_ucast_data_ok (),
+ -- rx_inc_mcast_ctrl (),
+ -- rx_inc_bcast_ctrl (),
+ -- rx_inc_ucast_ctrl (),
+ -- rx_inc_pause (),
+ -- rx_inc_fcs_err (),
+ -- rx_inc_fragment (),
+ -- rx_inc_jabber (),
+ -- rx_inc_sizeok_fcserr (),
+ -- rx_inc_pause_ctrl_err (),
+ -- rx_inc_mcast_ctrl_err (),
+ -- rx_inc_bcast_ctrl_err (),
+ -- rx_inc_ucast_ctrl_err (),
+ -- status_waitrequest (),
+ tx_lanes_stable(0) => l4_tx_siso_arr(mac).xon,
+ -- tx_inc_octetsOK (),
+ -- tx_inc_octetsOK_valid (),
+ -- tx_inc_64 (),
+ -- tx_inc_127 (),
+ -- tx_inc_255 (),
+ -- tx_inc_511 (),
+ -- tx_inc_1023 (),
+ -- tx_inc_1518 (),
+ -- tx_inc_max (),
+ -- tx_inc_over (),
+ -- tx_inc_mcast_data_err (),
+ -- tx_inc_mcast_data_ok (),
+ -- tx_inc_bcast_data_err (),
+ -- tx_inc_bcast_data_ok (),
+ -- tx_inc_ucast_data_err (),
+ -- tx_inc_ucast_data_ok (),
+ -- tx_inc_mcast_ctrl (),
+ -- tx_inc_bcast_ctrl (),
+ -- tx_inc_ucast_ctrl (),
+ -- tx_inc_pause (),
+ -- tx_inc_fcs_err (),
+ -- tx_inc_fragment (),
+ -- tx_inc_jabber (),
+ -- tx_inc_sizeok_fcserr (),
+
+ tx_serial => tx_serial_r(4 * (mac + 1) - 1 downto 4 * mac),
+ rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
+ );
-- No latency adapter needed as the RX MAC does not have a ready input
----------------------------------------------------------------------------
@@ -486,48 +486,48 @@ begin
----------------------------------------------------------------------------
rst_rxmac_arr(mac) <= not rx_pcs_ready_arr(mac);
u_dp_fifo_dc : entity dp_lib.dp_fifo_dc
- generic map (
- g_data_w => c_data_w,
- g_empty_w => 8,
- g_use_empty => true,
- g_use_bsn => false,
- g_bsn_w => 64,
- g_use_channel => false,
- g_use_sync => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_clk => clk_rxmac_arr(mac),
- wr_rst => rst_rxmac_arr(mac),
+ generic map (
+ g_data_w => c_data_w,
+ g_empty_w => 8,
+ g_use_empty => true,
+ g_use_bsn => false,
+ g_bsn_w => 64,
+ g_use_channel => false,
+ g_use_sync => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_clk => clk_rxmac_arr(mac),
+ wr_rst => rst_rxmac_arr(mac),
- rd_clk => kernel_clk,
- rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+ rd_rst => kernel_reset,
- snk_in => l4_rx_sosi_arr(mac),
- snk_out => OPEN,
+ snk_in => l4_rx_sosi_arr(mac),
+ snk_out => OPEN,
- src_out => dp_fifo_dc_src_out_arr(mac),
- src_in => dp_fifo_dc_src_in_arr(mac)
- );
+ src_out => dp_fifo_dc_src_out_arr(mac),
+ src_in => dp_fifo_dc_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_src_out_arr(mac),
- snk_out => dp_fifo_dc_src_in_arr(mac),
+ snk_in => dp_fifo_dc_src_out_arr(mac),
+ snk_out => dp_fifo_dc_src_in_arr(mac),
- src_out => dp_latency_adapter_rx_src_out_arr(mac),
- src_in => dp_latency_adapter_rx_src_in_arr(mac)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(mac),
+ src_in => dp_latency_adapter_rx_src_in_arr(mac)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -550,15 +550,15 @@ begin
-------------------------------------------------------------------------------
u_common_areset_txmac : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => kernel_reset,
- clk => clk_txmac_arr(mac),
- out_rst => rst_txmac_arr(mac)
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => kernel_reset,
+ clk => clk_txmac_arr(mac),
+ out_rst => rst_txmac_arr(mac)
+ );
-------------------------------------------------------------------------------
-- PLL for clock generation, every mac needs its own, due to clock nework limitations
@@ -575,6 +575,5 @@ begin
gen_serial_clk_arr : for i in 0 to 3 generate
serial_clk_2arr(mac)(i) <= serial_clk_arr(mac);
end generate;
-
end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 4e29874e8d21f7e36ed70ea57ab2fdc582c7b927..4c50bdaf67c24c1fb9d9f4eafabe0a5a65958420 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -32,11 +32,11 @@
-- . This core was developed for use on the Uniboard2b.
-- . The curret implementation only works with ddr4_8g_1600m
library IEEE, common_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_component_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_component_pkg.all;
entity ta2_unb2b_ddr is
generic (
@@ -194,154 +194,154 @@ architecture str of ta2_unb2b_ddr is
-- MM Pipe stage component
component ta2_unb2b_ddr_pipe_stage is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- PIPELINE_COMMAND : integer := 1;
- PIPELINE_RESPONSE : integer := 1;
- SYNC_RESET : integer := 0
- );
- port (
- clk : in std_logic := 'X'; -- clk
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X' -- debugaccess
- );
- end component ta2_unb2b_ddr_pipe_stage;
-
- -- MM clock cross component
- component ta2_unb2b_ddr_clock_cross is
- generic (
- DATA_WIDTH : integer := 32;
- SYMBOL_WIDTH : integer := 8;
- HDL_ADDR_WIDTH : integer := 10;
- BURSTCOUNT_WIDTH : integer := 1;
- COMMAND_FIFO_DEPTH : integer := 4;
- RESPONSE_FIFO_DEPTH : integer := 4;
- MASTER_SYNC_DEPTH : integer := 2;
- SLAVE_SYNC_DEPTH : integer := 2
- );
- port (
- m0_waitrequest : in std_logic := 'X'; -- waitrequest
- m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
- m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
- m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
- m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
- m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
- m0_write : out std_logic; -- write
- m0_read : out std_logic; -- read
- m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
- m0_debugaccess : out std_logic; -- debugaccess
- m0_clk : in std_logic := 'X'; -- clk
- m0_reset : in std_logic := 'X'; -- reset
- s0_waitrequest : out std_logic; -- waitrequest
- s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
- s0_readdatavalid : out std_logic; -- readdatavalid
- s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
- s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
- s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
- s0_write : in std_logic := 'X'; -- write
- s0_read : in std_logic := 'X'; -- read
- s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
- s0_debugaccess : in std_logic := 'X'; -- debugaccess
- s0_clk : in std_logic := 'X'; -- clk
- s0_reset : in std_logic := 'X' -- reset
- );
- end component ta2_unb2b_ddr_clock_cross;
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ PIPELINE_COMMAND : integer := 1;
+ PIPELINE_RESPONSE : integer := 1;
+ SYNC_RESET : integer := 0
+ );
+ port (
+ clk : in std_logic := 'X'; -- clk
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X' -- debugaccess
+ );
+ end component ta2_unb2b_ddr_pipe_stage;
+
+ -- MM clock cross component
+ component ta2_unb2b_ddr_clock_cross is
+ generic (
+ DATA_WIDTH : integer := 32;
+ SYMBOL_WIDTH : integer := 8;
+ HDL_ADDR_WIDTH : integer := 10;
+ BURSTCOUNT_WIDTH : integer := 1;
+ COMMAND_FIFO_DEPTH : integer := 4;
+ RESPONSE_FIFO_DEPTH : integer := 4;
+ MASTER_SYNC_DEPTH : integer := 2;
+ SLAVE_SYNC_DEPTH : integer := 2
+ );
+ port (
+ m0_waitrequest : in std_logic := 'X'; -- waitrequest
+ m0_readdata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- readdata
+ m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0); -- burstcount
+ m0_writedata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- writedata
+ m0_address : out std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0); -- address
+ m0_write : out std_logic; -- write
+ m0_read : out std_logic; -- read
+ m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable
+ m0_debugaccess : out std_logic; -- debugaccess
+ m0_clk : in std_logic := 'X'; -- clk
+ m0_reset : in std_logic := 'X'; -- reset
+ s0_waitrequest : out std_logic; -- waitrequest
+ s0_readdata : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- readdata
+ s0_readdatavalid : out std_logic; -- readdatavalid
+ s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH - 1 downto 0) := (others => 'X'); -- burstcount
+ s0_writedata : in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); -- writedata
+ s0_address : in std_logic_vector(HDL_ADDR_WIDTH - 1 downto 0) := (others => 'X'); -- address
+ s0_write : in std_logic := 'X'; -- write
+ s0_read : in std_logic := 'X'; -- read
+ s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
+ s0_debugaccess : in std_logic := 'X'; -- debugaccess
+ s0_clk : in std_logic := 'X'; -- clk
+ s0_reset : in std_logic := 'X' -- reset
+ );
+ end component ta2_unb2b_ddr_clock_cross;
begin
gen_MB_I : if g_use_MB_I generate
u_mb_I_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
- m0_readdata => mb_I_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_s0_burstcount,
- m0_writedata => mb_I_pipe_stage_s0_writedata,
- m0_address => mb_I_pipe_stage_s0_address,
- m0_write => mb_I_pipe_stage_s0_write,
- m0_read => mb_I_pipe_stage_s0_read,
- m0_byteenable => mb_I_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
- m0_clk => mb_I_emif_usr_clk,
- m0_reset => mb_I_emif_usr_reset,
- s0_waitrequest => mem0_waitrequest,
- s0_readdata => mem0_readdata,
- s0_readdatavalid => mem0_readdatavalid,
- s0_burstcount => mem0_burstcount,
- s0_writedata => mem0_writedata,
- s0_address => mem0_address,
- s0_write => mem0_write,
- s0_read => mem0_read,
- s0_byteenable => mem0_byteenable,
- s0_debugaccess => mem0_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_I_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_s0_burstcount,
+ m0_writedata => mb_I_pipe_stage_s0_writedata,
+ m0_address => mb_I_pipe_stage_s0_address,
+ m0_write => mb_I_pipe_stage_s0_write,
+ m0_read => mb_I_pipe_stage_s0_read,
+ m0_byteenable => mb_I_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_s0_debugaccess,
+ m0_clk => mb_I_emif_usr_clk,
+ m0_reset => mb_I_emif_usr_reset,
+ s0_waitrequest => mem0_waitrequest,
+ s0_readdata => mem0_readdata,
+ s0_readdatavalid => mem0_readdatavalid,
+ s0_burstcount => mem0_burstcount,
+ s0_writedata => mem0_writedata,
+ s0_address => mem0_address,
+ s0_write => mem0_write,
+ s0_read => mem0_read,
+ s0_byteenable => mem0_byteenable,
+ s0_debugaccess => mem0_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_I_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_I_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
- m0_readdata => mb_I_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_I_pipe_stage_m0_burstcount,
- m0_writedata => mb_I_pipe_stage_m0_writedata,
- m0_address => mb_I_pipe_stage_m0_address,
- m0_write => mb_I_pipe_stage_m0_write,
- m0_read => mb_I_pipe_stage_m0_read,
- m0_byteenable => mb_I_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
- reset => mb_I_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_I_pipe_stage_s0_address, -- .address
- s0_write => mb_I_pipe_stage_s0_write, -- .write
- s0_read => mb_I_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_I_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_I_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_I_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_I_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_I_pipe_stage_m0_burstcount,
+ m0_writedata => mb_I_pipe_stage_m0_writedata,
+ m0_address => mb_I_pipe_stage_m0_address,
+ m0_write => mb_I_pipe_stage_m0_write,
+ m0_read => mb_I_pipe_stage_m0_read,
+ m0_byteenable => mb_I_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_I_pipe_stage_m0_debugaccess,
+ reset => mb_I_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_I_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_I_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_I_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_I_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_I_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_I_pipe_stage_s0_address, -- .address
+ s0_write => mb_I_pipe_stage_s0_write, -- .write
+ s0_read => mb_I_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_I_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_I_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_I_pipe_stage_m0_waitrequest <= not mb_I_amm_ready_0;
mb_I_pipe_stage_m0_readdatavalid <= mb_I_amm_readdatavalid_0;
@@ -375,14 +375,14 @@ begin
mem_ck => mb_I_ou.ck(g_ddr_MB_I.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
mem_ck_n => mb_I_ou.ck_n(g_ddr_MB_I.ck_w - 1 downto 0), -- .mem_ck_n
mem_a => mb_I_ou.a(g_ddr_MB_I.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
+ sl(mem_act_n) => mb_I_ou.act_n, -- .mem_act_n
mem_ba => mb_I_ou.ba(g_ddr_MB_I.ba_w - 1 downto 0), -- .mem_ba
mem_bg => mb_I_ou.bg(g_ddr_MB_I.bg_w - 1 downto 0), -- .mem_bg
mem_cke => mb_I_ou.cke(g_ddr_MB_I.cke_w - 1 downto 0), -- .mem_cke
mem_cs_n => mb_I_ou.cs_n(g_ddr_MB_I.cs_w - 1 downto 0), -- .mem_cs_n
mem_odt => mb_I_ou.odt(g_ddr_MB_I.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_I_ou.par, -- .mem_par
+ sl(mem_reset_n) => mb_I_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_I_ou.par, -- .mem_par
mem_alert_n => slv(mb_I_in.alert_n), -- .mem_alert_n
mem_dqs => mb_I_io.dqs(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs
mem_dqs_n => mb_I_io.dqs_n(g_ddr_MB_I.dqs_w - 1 downto 0), -- .mem_dqs_n
@@ -394,82 +394,81 @@ begin
local_cal_fail => open -- .local_cal_fail
);
end generate;
-
end generate;
gen_MB_II : if g_use_MB_II generate
u_mb_II_clock_cross : ta2_unb2b_ddr_clock_cross
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- COMMAND_FIFO_DEPTH => c_command_fifo_depth,
- RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
- MASTER_SYNC_DEPTH => c_master_sync_depth,
- SLAVE_SYNC_DEPTH => c_slave_sync_depth
- )
- port map (
- m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
- m0_readdata => mb_II_pipe_stage_s0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_s0_burstcount,
- m0_writedata => mb_II_pipe_stage_s0_writedata,
- m0_address => mb_II_pipe_stage_s0_address,
- m0_write => mb_II_pipe_stage_s0_write,
- m0_read => mb_II_pipe_stage_s0_read,
- m0_byteenable => mb_II_pipe_stage_s0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
- m0_clk => mb_II_emif_usr_clk,
- m0_reset => mb_II_emif_usr_reset,
- s0_waitrequest => mem1_waitrequest,
- s0_readdata => mem1_readdata,
- s0_readdatavalid => mem1_readdatavalid,
- s0_burstcount => mem1_burstcount,
- s0_writedata => mem1_writedata,
- s0_address => mem1_address,
- s0_write => mem1_write,
- s0_read => mem1_read,
- s0_byteenable => mem1_byteenable,
- s0_debugaccess => mem1_debugaccess,
- s0_clk => kernel_clk,
- s0_reset => kernel_reset
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ COMMAND_FIFO_DEPTH => c_command_fifo_depth,
+ RESPONSE_FIFO_DEPTH => c_response_fifo_depth,
+ MASTER_SYNC_DEPTH => c_master_sync_depth,
+ SLAVE_SYNC_DEPTH => c_slave_sync_depth
+ )
+ port map (
+ m0_waitrequest => mb_II_pipe_stage_s0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_s0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_s0_burstcount,
+ m0_writedata => mb_II_pipe_stage_s0_writedata,
+ m0_address => mb_II_pipe_stage_s0_address,
+ m0_write => mb_II_pipe_stage_s0_write,
+ m0_read => mb_II_pipe_stage_s0_read,
+ m0_byteenable => mb_II_pipe_stage_s0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_s0_debugaccess,
+ m0_clk => mb_II_emif_usr_clk,
+ m0_reset => mb_II_emif_usr_reset,
+ s0_waitrequest => mem1_waitrequest,
+ s0_readdata => mem1_readdata,
+ s0_readdatavalid => mem1_readdatavalid,
+ s0_burstcount => mem1_burstcount,
+ s0_writedata => mem1_writedata,
+ s0_address => mem1_address,
+ s0_write => mem1_write,
+ s0_read => mem1_read,
+ s0_byteenable => mem1_byteenable,
+ s0_debugaccess => mem1_debugaccess,
+ s0_clk => kernel_clk,
+ s0_reset => kernel_reset
+ );
u_mb_II_pipe_stage : ta2_unb2b_ddr_pipe_stage
- generic map (
- DATA_WIDTH => c_data_w,
- SYMBOL_WIDTH => c_symbol_w,
- HDL_ADDR_WIDTH => c_addr_w,
- BURSTCOUNT_WIDTH => c_burstcount_w,
- PIPELINE_COMMAND => c_pipeline_command,
- PIPELINE_RESPONSE => c_pipeline_response,
- SYNC_RESET => c_sync_reset
- )
- port map (
- clk => mb_II_emif_usr_clk, -- clk.clk
- m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
- m0_readdata => mb_II_pipe_stage_m0_readdata,
- m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
- m0_burstcount => mb_II_pipe_stage_m0_burstcount,
- m0_writedata => mb_II_pipe_stage_m0_writedata,
- m0_address => mb_II_pipe_stage_m0_address,
- m0_write => mb_II_pipe_stage_m0_write,
- m0_read => mb_II_pipe_stage_m0_read,
- m0_byteenable => mb_II_pipe_stage_m0_byteenable,
- m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
- reset => mb_II_emif_usr_reset, -- reset.reset
- s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
- s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
- s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
- s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
- s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
- s0_address => mb_II_pipe_stage_s0_address, -- .address
- s0_write => mb_II_pipe_stage_s0_write, -- .write
- s0_read => mb_II_pipe_stage_s0_read, -- .read
- s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
- s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
- );
+ generic map (
+ DATA_WIDTH => c_data_w,
+ SYMBOL_WIDTH => c_symbol_w,
+ HDL_ADDR_WIDTH => c_addr_w,
+ BURSTCOUNT_WIDTH => c_burstcount_w,
+ PIPELINE_COMMAND => c_pipeline_command,
+ PIPELINE_RESPONSE => c_pipeline_response,
+ SYNC_RESET => c_sync_reset
+ )
+ port map (
+ clk => mb_II_emif_usr_clk, -- clk.clk
+ m0_waitrequest => mb_II_pipe_stage_m0_waitrequest,
+ m0_readdata => mb_II_pipe_stage_m0_readdata,
+ m0_readdatavalid => mb_II_pipe_stage_m0_readdatavalid,
+ m0_burstcount => mb_II_pipe_stage_m0_burstcount,
+ m0_writedata => mb_II_pipe_stage_m0_writedata,
+ m0_address => mb_II_pipe_stage_m0_address,
+ m0_write => mb_II_pipe_stage_m0_write,
+ m0_read => mb_II_pipe_stage_m0_read,
+ m0_byteenable => mb_II_pipe_stage_m0_byteenable,
+ m0_debugaccess => mb_II_pipe_stage_m0_debugaccess,
+ reset => mb_II_emif_usr_reset, -- reset.reset
+ s0_waitrequest => mb_II_pipe_stage_s0_waitrequest, -- s0.waitrequest
+ s0_readdata => mb_II_pipe_stage_s0_readdata, -- .readdata
+ s0_readdatavalid => mb_II_pipe_stage_s0_readdatavalid, -- .readdatavalid
+ s0_burstcount => mb_II_pipe_stage_s0_burstcount, -- .burstcount
+ s0_writedata => mb_II_pipe_stage_s0_writedata, -- .writedata
+ s0_address => mb_II_pipe_stage_s0_address, -- .address
+ s0_write => mb_II_pipe_stage_s0_write, -- .write
+ s0_read => mb_II_pipe_stage_s0_read, -- .read
+ s0_byteenable => mb_II_pipe_stage_s0_byteenable, -- .byteenable
+ s0_debugaccess => mb_II_pipe_stage_s0_debugaccess -- .debugaccess
+ );
mb_II_pipe_stage_m0_waitrequest <= not mb_II_amm_ready_0;
mb_II_pipe_stage_m0_readdatavalid <= mb_II_amm_readdatavalid_0;
@@ -503,14 +502,14 @@ begin
mem_ck => mb_II_ou.ck(g_ddr_MB_II.ck_w - 1 downto 0), -- mem_conduit_end.mem_ck
mem_ck_n => mb_II_ou.ck_n(g_ddr_MB_II.ck_w - 1 downto 0), -- .mem_ck_n
mem_a => mb_II_ou.a(g_ddr_MB_II.a_w - 1 downto 0), -- .mem_a
- sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
+ sl(mem_act_n) => mb_II_ou.act_n, -- .mem_act_n
mem_ba => mb_II_ou.ba(g_ddr_MB_II.ba_w - 1 downto 0), -- .mem_ba
mem_bg => mb_II_ou.bg(g_ddr_MB_II.bg_w - 1 downto 0), -- .mem_bg
mem_cke => mb_II_ou.cke(g_ddr_MB_II.cke_w - 1 downto 0), -- .mem_cke
mem_cs_n => mb_II_ou.cs_n(g_ddr_MB_II.cs_w - 1 downto 0), -- .mem_cs_n
mem_odt => mb_II_ou.odt(g_ddr_MB_II.odt_w - 1 downto 0), -- .mem_odt
- sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
- sl(mem_par) => mb_II_ou.par, -- .mem_par
+ sl(mem_reset_n) => mb_II_ou.reset_n, -- .mem_reset_n
+ sl(mem_par) => mb_II_ou.par, -- .mem_par
mem_alert_n => slv(mb_II_in.alert_n), -- .mem_alert_n
mem_dqs => mb_II_io.dqs(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs
mem_dqs_n => mb_II_io.dqs_n(g_ddr_MB_II.dqs_w - 1 downto 0), -- .mem_dqs_n
@@ -522,6 +521,5 @@ begin
local_cal_fail => open -- .local_cal_fail
);
end generate;
-
end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index c5d1073de0edb6f9d4e164f6c0f7834f51b5a02d..30f37f49070c451dfa14f7ca3084dfb0ec23940f 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -42,12 +42,12 @@
-- | [0:15] | payload | ADC channel 0 sample |
-- +-----------+---------+--------------------------------------------------------+
library IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_jesd204b is
generic (
@@ -105,32 +105,32 @@ begin
jesd204b_disable_arr <= (others => '0');
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => c_sim,
- g_nof_streams => c_nof_streams_jesd204b
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- rx_sosi_arr => jesd204b_rx_sosi_arr,
- rx_clk => jesd204b_rx_clk,
- rx_rst => jesd204b_rx_rst,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_rx_arr
- );
+ generic map(
+ g_sim => c_sim,
+ g_nof_streams => c_nof_streams_jesd204b
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => i_jesd204b_sync_n_arr,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ rx_sosi_arr => jesd204b_rx_sosi_arr,
+ rx_clk => jesd204b_rx_clk,
+ rx_rst => jesd204b_rx_rst,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_rx_arr
+ );
gen_streams: for stream in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
@@ -143,45 +143,45 @@ begin
dp_fifo_dc_rx_snk_in_arr(stream).valid <= dp_fifo_dc_rx_snk_out_arr(stream).ready and jesd204b_rx_sosi_arr(stream).valid;
u_dp_fifo_dc_rx : entity dp_lib.dp_fifo_dc
- generic map (
- g_technology => c_tech_arria10_e1sg,
- g_data_w => 16,
- g_empty_w => 1,
- g_use_empty => false,
- g_use_ctrl => false,
- g_fifo_size => c_rx_fifo_size
- )
- port map (
- wr_rst => jesd204b_rx_rst,
- wr_clk => jesd204b_rx_clk,
- rd_rst => kernel_reset,
- rd_clk => kernel_clk,
-
- snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
- snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
-
- src_in => dp_fifo_dc_rx_src_in_arr(stream),
- src_out => dp_fifo_dc_rx_src_out_arr(stream)
- );
+ generic map (
+ g_technology => c_tech_arria10_e1sg,
+ g_data_w => 16,
+ g_empty_w => 1,
+ g_use_empty => false,
+ g_use_ctrl => false,
+ g_fifo_size => c_rx_fifo_size
+ )
+ port map (
+ wr_rst => jesd204b_rx_rst,
+ wr_clk => jesd204b_rx_clk,
+ rd_rst => kernel_reset,
+ rd_clk => kernel_clk,
+
+ snk_out => dp_fifo_dc_rx_snk_out_arr(stream),
+ snk_in => dp_fifo_dc_rx_snk_in_arr(stream),
+
+ src_in => dp_fifo_dc_rx_src_in_arr(stream),
+ src_out => dp_fifo_dc_rx_src_out_arr(stream)
+ );
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
u_dp_latency_adapter_rx : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- clk => kernel_clk,
- rst => kernel_reset,
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ clk => kernel_clk,
+ rst => kernel_reset,
- snk_in => dp_fifo_dc_rx_src_out_arr(stream),
- snk_out => dp_fifo_dc_rx_src_in_arr(stream),
+ snk_in => dp_fifo_dc_rx_src_out_arr(stream),
+ snk_out => dp_fifo_dc_rx_src_in_arr(stream),
- src_out => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_latency_adapter_rx_src_in_arr(stream)
- );
+ src_out => dp_latency_adapter_rx_src_out_arr(stream),
+ src_in => dp_latency_adapter_rx_src_in_arr(stream)
+ );
----------------------------------------------------------------------------
-- Data mapping
@@ -196,5 +196,4 @@ begin
dp_latency_adapter_rx_src_in_arr(stream).ready <= src_in_arr(stream).ready;
dp_latency_adapter_rx_src_in_arr(stream).xon <= '1';
end generate;
-
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index 102c3f0ec1dcab780df235063bfcf51bbc7a36f8..4c38c3384d00f2019c6770bd37685a4f3add24a5 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -24,7 +24,7 @@
-- Purpose:
-- . Instantiates ta2_unb2b_10GbE component
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity ta2_unb2b_jesd204b_ip_wrapper is
port (
@@ -91,23 +91,23 @@ architecture str of ta2_unb2b_jesd204b_ip_wrapper is
end component ta2_unb2b_jesd204b;
begin
u_ta2_unb2b_jesd204b : ta2_unb2b_jesd204b
- port map (
- config_clk => config_clk,
- config_reset => config_reset,
- jesd204b_mosi_address => jesd204b_mosi_address,
- jesd204b_mosi_wrdata => jesd204b_mosi_wrdata,
- jesd204b_mosi_wr => jesd204b_mosi_wr,
- jesd204b_mosi_rd => jesd204b_mosi_rd,
- jesd204b_miso_rddata => jesd204b_miso_rddata,
- jesd204b_miso_waitrequest => jesd204b_miso_waitrequest,
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- serial_rx_arr => serial_rx_arr,
- kernel_clk => kernel_clk,
- kernel_reset => kernel_reset,
- kernel_src_data => kernel_src_data,
- kernel_src_valid => kernel_src_valid,
- kernel_src_ready => kernel_src_ready
- );
+ port map (
+ config_clk => config_clk,
+ config_reset => config_reset,
+ jesd204b_mosi_address => jesd204b_mosi_address,
+ jesd204b_mosi_wrdata => jesd204b_mosi_wrdata,
+ jesd204b_mosi_wr => jesd204b_mosi_wr,
+ jesd204b_mosi_rd => jesd204b_mosi_rd,
+ jesd204b_miso_rddata => jesd204b_miso_rddata,
+ jesd204b_miso_waitrequest => jesd204b_miso_waitrequest,
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n_arr,
+ serial_rx_arr => serial_rx_arr,
+ kernel_clk => kernel_clk,
+ kernel_reset => kernel_reset,
+ kernel_src_data => kernel_src_data,
+ kernel_src_valid => kernel_src_valid,
+ kernel_src_ready => kernel_src_ready
+ );
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index f73837193b44a6a43ee128f28d0b03de0a8b2ff2..2d15d2b3ef5e79e6ce52f6770c71b9fd2c6b3791 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -61,12 +61,12 @@
-- registers are rddata = wrdata.
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
entity ta2_unb2b_mm_io is
generic (
@@ -146,7 +146,7 @@ begin
-----------------------------------------------------------------------------
-- dual clock FIFOs
-----------------------------------------------------------------------------
- u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_wr : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_wr_data_w,
@@ -169,7 +169,7 @@ begin
src_out => out_sosi
);
- u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
+ u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
g_data_w => c_rd_data_w,
@@ -192,68 +192,67 @@ begin
src_out => rd_sosi
);
-gen_no_opencl : if not g_use_opencl generate
- -- simulate an OpenCL kernel response (rl=0)
- p_is_reading : process(kernel_clk)
- begin
- if rising_edge(kernel_clk) then
- if cnt >= c_cnt_max then
- cnt <= 0;
- is_reading <= false;
- else
- cnt <= cnt + 1;
- end if;
- if in_sosi.valid = '1' then
- is_reading <= true;
- cnt <= 0;
+ gen_no_opencl : if not g_use_opencl generate
+ -- simulate an OpenCL kernel response (rl=0)
+ p_is_reading : process(kernel_clk)
+ begin
+ if rising_edge(kernel_clk) then
+ if cnt >= c_cnt_max then
+ cnt <= 0;
+ is_reading <= false;
+ else
+ cnt <= cnt + 1;
+ end if;
+ if in_sosi.valid = '1' then
+ is_reading <= true;
+ cnt <= 0;
+ end if;
end if;
- end if;
- end process;
+ end process;
- p_stim_st : process(out_sosi, in_siso, is_reading)
- begin
- in_sosi.valid <= '0';
- if out_sosi.valid = '1' then
- if out_sosi.data(64) = '1' then -- Write request
- if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- reg_a <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- reg_c <= out_sosi.data(31 downto 0);
- elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
- end if;
- out_siso.ready <= '1';
- else -- read request
- if not is_reading then
- out_siso.ready <= '1';
- in_sosi.valid <= '1';
+ p_stim_st : process(out_sosi, in_siso, is_reading)
+ begin
+ in_sosi.valid <= '0';
+ if out_sosi.valid = '1' then
+ if out_sosi.data(64) = '1' then -- Write request
if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
- in_sosi.data(31 downto 0) <= reg_a;
+ reg_a <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
- in_sosi.data(31 downto 0) <= reg_b;
+ reg_b <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 1, 8) & out_sosi.data(23 downto 0); -- wrdata +1 to make distinguishable
elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
- in_sosi.data(31 downto 0) <= reg_c;
+ reg_c <= out_sosi.data(31 downto 0);
elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
- in_sosi.data(31 downto 0) <= reg_d;
- else
- in_sosi.data(31 downto 0) <= (others => '0');
+ reg_d <= TO_UVEC(TO_UINT(out_sosi.data(31 downto 24)) + 2, 8) & out_sosi.data(23 downto 0); -- wrdata +2 to make distinguishable
+ end if;
+ out_siso.ready <= '1';
+ else -- read request
+ if not is_reading then
+ out_siso.ready <= '1';
+ in_sosi.valid <= '1';
+ if TO_UINT(out_sosi.data(63 downto 56)) = 0 then
+ in_sosi.data(31 downto 0) <= reg_a;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 1 then
+ in_sosi.data(31 downto 0) <= reg_b;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 2 then
+ in_sosi.data(31 downto 0) <= reg_c;
+ elsif TO_UINT(out_sosi.data(63 downto 56)) = 3 then
+ in_sosi.data(31 downto 0) <= reg_d;
+ else
+ in_sosi.data(31 downto 0) <= (others => '0');
+ end if;
end if;
end if;
end if;
- end if;
- end process;
-
- src_out <= c_dp_sosi_rst;
- snk_out <= c_dp_siso_rdy;
-end generate;
+ end process;
-gen_opencl : if g_use_opencl generate
- src_out <= out_sosi;
- out_siso <= src_in;
- snk_out <= in_siso;
- in_sosi <= snk_in;
-end generate;
+ src_out <= c_dp_sosi_rst;
+ snk_out <= c_dp_siso_rdy;
+ end generate;
+ gen_opencl : if g_use_opencl generate
+ src_out <= out_sosi;
+ out_siso <= src_in;
+ snk_out <= in_siso;
+ in_sosi <= snk_in;
+ end generate;
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 262dbfdd93d69f7675bdc385c283003192bdcf92..062957000eb5371fe2dbddad8543250084e10737 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -27,15 +27,15 @@
-- . Usage -> as 10; run -a
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_ta2_unb2b_mm_io is
end tb_ta2_unb2b_mm_io;
@@ -72,28 +72,28 @@ begin
end process;
u_dut : entity work.ta2_unb2b_mm_io
- generic map(
- g_use_opencl => false
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
-
- -- Streaming clock domain
- kernel_reset => rst,
- kernel_clk => clk,
-
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map(
+ g_use_opencl => false
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+
+ -- Streaming clock domain
+ kernel_reset => rst,
+ kernel_clk => clk,
+
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
p_stim_mm : process
begin
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index e669d24a75b5631580f001a171f9755e4784b363..05c62f612555b1bb0124941898cd5beea163593b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -27,16 +27,16 @@
-- the MM interface
library IEEE, common_lib, unb1_board_lib, dp_lib, i2c_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use i2c_lib.i2c_commander_aduh_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use i2c_lib.i2c_commander_aduh_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity node_unb1_bn_capture is
generic (
@@ -187,129 +187,129 @@ begin
-- . input from 4 signal paths A, B, C and D of 8b @ 800 MSps each
-- . output 4 signal streams via sp_sosi_arr with 4 samples per 32b data word
u_input: entity work.unb1_bn_capture_input
- generic map (
- g_sim => g_sim,
- g_bn_capture => g_bn_capture,
- g_use_phy => g_use_phy,
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator ports [A, B, C, B]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path data monitors [A, B, C, B]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => i_sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_bn_capture => g_bn_capture,
+ g_use_phy => g_use_phy,
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator ports [A, B, C, B]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path data monitors [A, B, C, B]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => i_sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
------------------------------------------------------------------------------
-- 2a) I2C control for ADU AB
------------------------------------------------------------------------------
u_i2c_adu_ab : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(0),
- commander_miso => reg_commander_miso_arr(0),
- protocol_mosi => ram_protocol_mosi_arr(0),
- protocol_miso => ram_protocol_miso_arr(0),
- result_mosi => ram_result_mosi_arr(0),
- result_miso => ram_result_miso_arr(0),
-
- -- I2C interface
- scl => ADC_AB_SCL,
- sda => ADC_AB_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(0),
+ commander_miso => reg_commander_miso_arr(0),
+ protocol_mosi => ram_protocol_mosi_arr(0),
+ protocol_miso => ram_protocol_miso_arr(0),
+ result_mosi => ram_result_mosi_arr(0),
+ result_miso => ram_result_miso_arr(0),
+
+ -- I2C interface
+ scl => ADC_AB_SCL,
+ sda => ADC_AB_SDA
+ );
------------------------------------------------------------------------------
-- 2b) I2C control for ADU CD
------------------------------------------------------------------------------
u_i2c_adu_cd : entity i2c_lib.i2c_commander
- generic map (
- g_sim => g_sim,
- g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
- g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
- g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
- g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
- g_use_result_ram => c_use_result_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- sync => '1',
-
- -- Memory Mapped slave interfaces
- commander_mosi => reg_commander_mosi_arr(1),
- commander_miso => reg_commander_miso_arr(1),
- protocol_mosi => ram_protocol_mosi_arr(1),
- protocol_miso => ram_protocol_miso_arr(1),
- result_mosi => ram_result_mosi_arr(1),
- result_miso => ram_result_miso_arr(1),
-
- -- I2C interface
- scl => ADC_CD_SCL,
- sda => ADC_CD_SDA
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_cmdr => c_i2c_cmdr_aduh_protocol_commander,
+ g_i2c_mm => func_i2c_sel_a_b(g_sim, c_i2c_cmdr_aduh_i2c_mm_sim, c_i2c_cmdr_aduh_i2c_mm), -- use full address range in sim to avoid warnings
+ g_i2c_phy => func_i2c_calculate_phy(g_bn_capture.mm_clk_freq / 10**6),
+ g_protocol_ram_init_file => "data/adu_protocol_ram_init.hex",
+ g_use_result_ram => c_use_result_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ sync => '1',
+
+ -- Memory Mapped slave interfaces
+ commander_mosi => reg_commander_mosi_arr(1),
+ commander_miso => reg_commander_miso_arr(1),
+ protocol_mosi => ram_protocol_mosi_arr(1),
+ protocol_miso => ram_protocol_miso_arr(1),
+ result_mosi => ram_result_mosi_arr(1),
+ result_miso => ram_result_miso_arr(1),
+
+ -- I2C interface
+ scl => ADC_CD_SCL,
+ sda => ADC_CD_SDA
+ );
------------------------------------------------------------------------------
-- 3) Feed each SP through a flusher that is controlled by a scheduler
@@ -317,79 +317,79 @@ begin
gen_flushers: for i in 0 to g_ai.nof_sp - 1 generate
u_dp_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => true,
- g_framed_xoff => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => i_sp_sosi_arr(i),
- snk_out => sp_siso_arr(i),
- -- ST source
- src_in => scheduled_sp_siso_arr(i),
- src_out => scheduled_sp_sosi_arr(i),
- -- Enable flush
- flush_en => sp_flush_en
- );
+ generic map (
+ g_framed_xon => true,
+ g_framed_xoff => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => i_sp_sosi_arr(i),
+ snk_out => sp_siso_arr(i),
+ -- ST source
+ src_in => scheduled_sp_siso_arr(i),
+ src_out => scheduled_sp_sosi_arr(i),
+ -- Enable flush
+ flush_en => sp_flush_en
+ );
end generate;
-- Convert the schedulers trigger on/off pulses to flush disable/enable level
u_sp_flush_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- switch_high => dp_bsn_trigger_sp_off,
- switch_low => dp_bsn_trigger_sp_on,
- out_level => sp_flush_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ switch_high => dp_bsn_trigger_sp_off,
+ switch_low => dp_bsn_trigger_sp_on,
+ out_level => sp_flush_en
+ );
u_bsn_trigger_sp_on : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_miso => reg_bsn_scheduler_sp_on_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_on
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_miso => reg_bsn_scheduler_sp_on_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_on
+ );
u_bsn_trigger_sp_off : entity dp_lib.mms_dp_bsn_scheduler
- generic map (
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_miso => reg_bsn_scheduler_sp_off_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
- trigger_out => dp_bsn_trigger_sp_off
- );
+ generic map (
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_miso => reg_bsn_scheduler_sp_off_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
+ trigger_out => dp_bsn_trigger_sp_off
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index 39f0e51e1884df2cdb6217cc4ab4c3e7354038a8..e972dbe38c73fd8c0a79910ac8ba3efc76a92933 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -22,18 +22,18 @@
-- Purpose: Capture ADC samples from ADU on a BN
library IEEE, common_lib, unb1_board_lib, dp_lib, ppsh_lib, eth_lib, tech_tse_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use work.unb1_bn_capture_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use work.unb1_bn_capture_pkg.all;
entity unb1_bn_capture is
generic (
@@ -192,547 +192,547 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_capture
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_source
- coe_clk_export_from_the_reg_bsn_source => OPEN,
- coe_reset_export_from_the_reg_bsn_source => OPEN,
- coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_wg
- coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
- coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adc_quad
- coe_clk_export_from_the_reg_adc_quad => OPEN,
- coe_reset_export_from_the_reg_adc_quad => OPEN,
- coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
- coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
- coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_0
- coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
- coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_1
- coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
- coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_2
- coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
- coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_wg_3
- coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
- coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
- coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_0
- coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
- coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_1
- coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
- coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_2
- coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
- coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_wg_3
- coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
- coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
- coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_shiftram
- coe_clk_export_from_the_reg_dp_shiftram => OPEN,
- coe_reset_export_from_the_reg_dp_shiftram => OPEN,
- coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
- coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
- coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_0
- coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_1
- coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_2
- coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_aduh_mon_3
- coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
- coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_0
- coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_1
- coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_2
- coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
- coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
- coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_aduh_mon_3
- coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
- coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
- coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
- coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_ab
- coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_adu_i2c_commander_cd
- coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
- coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_ab
- coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_protocol_cd
- coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_ab
- coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_adu_i2c_result_cd
- coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
- coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
- coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
- coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_on
- coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_scheduler_sp_off
- coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
- coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
- coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 50 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => OPEN, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_source
+ coe_clk_export_from_the_reg_bsn_source => OPEN,
+ coe_reset_export_from_the_reg_bsn_source => OPEN,
+ coe_address_export_from_the_reg_bsn_source => reg_bsn_source_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_source_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_bsn_source => reg_bsn_source_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_source => reg_bsn_source_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_source => reg_bsn_source_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_wg
+ coe_clk_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_wg => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.address(0), -- reg_bsn_scheduler_adr_w = 1
+ coe_read_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_wg => reg_bsn_scheduler_wg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adc_quad
+ coe_clk_export_from_the_reg_adc_quad => OPEN,
+ coe_reset_export_from_the_reg_adc_quad => OPEN,
+ coe_address_export_from_the_reg_adc_quad => reg_adc_quad_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_adc_quad_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adc_quad => reg_adc_quad_mosi.rd,
+ coe_readdata_export_to_the_reg_adc_quad => reg_adc_quad_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wr,
+ coe_writedata_export_from_the_reg_adc_quad => reg_adc_quad_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_0
+ coe_clk_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_0 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_diag_wg_0 => reg_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_diag_wg_0 => reg_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_1
+ coe_clk_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_1 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_diag_wg_1 => reg_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_diag_wg_1 => reg_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_2
+ coe_clk_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_2 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_diag_wg_2 => reg_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_diag_wg_2 => reg_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_wg_3
+ coe_clk_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_reg_diag_wg_3 => OPEN,
+ coe_address_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_diag_wg_3 => reg_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_diag_wg_3 => reg_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_0
+ coe_clk_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_0 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_diag_wg_0 => ram_wg_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_diag_wg_0 => ram_wg_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_1
+ coe_clk_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_1 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_diag_wg_1 => ram_wg_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_diag_wg_1 => ram_wg_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_2
+ coe_clk_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_2 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_diag_wg_2 => ram_wg_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_diag_wg_2 => ram_wg_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_wg_3
+ coe_clk_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_reset_export_from_the_ram_diag_wg_3 => OPEN,
+ coe_address_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_diag_wg_3 => ram_wg_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_diag_wg_3 => ram_wg_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_shiftram
+ coe_clk_export_from_the_reg_dp_shiftram => OPEN,
+ coe_reset_export_from_the_reg_dp_shiftram => OPEN,
+ coe_address_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.address(c_reg_dp_shiftram_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_shiftram => reg_dp_shiftram_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_shiftram => reg_dp_shiftram_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_0
+ coe_clk_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_0 => reg_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_0 => reg_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_1
+ coe_clk_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_1 => reg_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_1 => reg_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_2
+ coe_clk_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_2 => reg_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_2 => reg_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_aduh_mon_3
+ coe_clk_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_reg_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.reg_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_reg_aduh_mon_3 => reg_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_reg_aduh_mon_3 => reg_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_0
+ coe_clk_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_0 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_0 => ram_mon_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_0 => ram_mon_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_1
+ coe_clk_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_1 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_1 => ram_mon_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_1 => ram_mon_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_2
+ coe_clk_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_2 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_2 => ram_mon_miso_arr(2).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_2 => ram_mon_mosi_arr(2).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_aduh_mon_3
+ coe_clk_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_reset_export_from_the_ram_aduh_mon_3 => OPEN,
+ coe_address_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).address(c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).rd,
+ coe_readdata_export_to_the_ram_aduh_mon_3 => ram_mon_miso_arr(3).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wr,
+ coe_writedata_export_from_the_ram_aduh_mon_3 => ram_mon_mosi_arr(3).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_ab
+ coe_clk_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_ab => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_ab => reg_commander_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_ab => reg_commander_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_adu_i2c_commander_cd
+ coe_clk_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_reset_export_from_the_reg_adu_i2c_commander_cd => OPEN,
+ coe_address_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.reg_i2c_commander_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).rd,
+ coe_readdata_export_to_the_reg_adu_i2c_commander_cd => reg_commander_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wr,
+ coe_writedata_export_from_the_reg_adu_i2c_commander_cd => reg_commander_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_ab
+ coe_clk_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_ab => ram_protocol_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_ab => ram_protocol_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_protocol_cd
+ coe_clk_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_protocol_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_protocol_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_protocol_cd => ram_protocol_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_protocol_cd => ram_protocol_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_ab
+ coe_clk_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_ab => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_ab => ram_result_miso_arr(0).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_ab => ram_result_mosi_arr(0).wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_adu_i2c_result_cd
+ coe_clk_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_reset_export_from_the_ram_adu_i2c_result_cd => OPEN,
+ coe_address_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).address(c_unb1_board_peripherals_mm_reg_default.ram_i2c_result_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).rd,
+ coe_readdata_export_to_the_ram_adu_i2c_result_cd => ram_result_miso_arr(1).rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wr,
+ coe_writedata_export_from_the_ram_adu_i2c_result_cd => ram_result_mosi_arr(1).wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_on
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_on => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_on => reg_bsn_scheduler_sp_on_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_scheduler_sp_off
+ coe_clk_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_reset_export_from_the_reg_bsn_scheduler_sp_off => OPEN,
+ coe_address_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.address(0),
+ coe_read_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_scheduler_sp_off => reg_bsn_scheduler_sp_off_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
--- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
--- GENERIC MAP (
--- -- General
--- g_sim => g_sim,
--- g_design_name => g_design_name,
--- g_fw_version => g_fw_version,
--- g_stamp_date => g_stamp_date,
--- g_stamp_time => g_stamp_time,
--- g_stamp_svn => g_stamp_svn,
--- g_design_note => g_design_note,
--- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
--- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
--- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
--- -- Use PHY Interface
--- g_use_phy => g_use_phy,
--- -- Auxiliary Interface
--- g_aux => g_aux
--- )
+ -- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
+ -- GENERIC MAP (
+ -- -- General
+ -- g_sim => g_sim,
+ -- g_design_name => g_design_name,
+ -- g_fw_version => g_fw_version,
+ -- g_stamp_date => g_stamp_date,
+ -- g_stamp_time => g_stamp_time,
+ -- g_stamp_svn => g_stamp_svn,
+ -- g_design_note => g_design_note,
+ -- g_mm_clk_freq => g_bn_capture.mm_clk_freq, -- must match PLL setting in sopc_bn_capture
+ -- g_dp_clk_freq => g_bn_capture.dp_clk_freq,
+ -- g_dp_phs_clk_vec_w => g_nof_dp_phs_clk,
+ -- -- Use PHY Interface
+ -- g_use_phy => g_use_phy,
+ -- -- Auxiliary Interface
+ -- g_aux => g_aux
+ -- )
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
- g_dp_clk_use_pll => c_dp_clk_use_pll,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
-
- this_chip_id => this_chip_id,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- ppsh
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_phs_clk_vec_w => c_nof_dp_phs_clk,
+ g_dp_clk_use_pll => c_dp_clk_use_pll,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec, -- divided and phase shifted dp_clk
+
+ this_chip_id => this_chip_id,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- ppsh
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Specific node function
-----------------------------------------------------------------------------
u_node : entity work.node_unb1_bn_capture
- generic map (
- -- General
- g_sim => g_sim,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => c_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- ext_clk => CLK,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM DP shiftram
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
-
- -- MM signal path monitors for [A, B, C, D]
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- MM registers [0,1] for I2C access with ADUs [AB,CD]
- reg_commander_mosi_arr => reg_commander_mosi_arr,
- reg_commander_miso_arr => reg_commander_miso_arr,
- ram_protocol_mosi_arr => ram_protocol_mosi_arr,
- ram_protocol_miso_arr => ram_protocol_miso_arr,
- ram_result_mosi_arr => ram_result_mosi_arr,
- ram_result_miso_arr => ram_result_miso_arr,
-
- -- MM registers to enable and disable signal path
- reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
- reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
- --
- -- >>> Node FPGA pins
- --
- -- ADC Interface
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK,
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK,
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
- ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => c_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ ext_clk => CLK,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM DP shiftram
+ reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_miso,
+
+ -- MM signal path monitors for [A, B, C, D]
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- MM registers [0,1] for I2C access with ADUs [AB,CD]
+ reg_commander_mosi_arr => reg_commander_mosi_arr,
+ reg_commander_miso_arr => reg_commander_miso_arr,
+ ram_protocol_mosi_arr => ram_protocol_mosi_arr,
+ ram_protocol_miso_arr => ram_protocol_miso_arr,
+ ram_result_mosi_arr => ram_result_mosi_arr,
+ ram_result_miso_arr => ram_result_miso_arr,
+
+ -- MM registers to enable and disable signal path
+ reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
+ reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
+ --
+ -- >>> Node FPGA pins
+ --
+ -- ADC Interface
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK,
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST,
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK,
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST,
+ ADC_AB_SCL => ADC_AB_SCL, -- I2C AB
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
+ ADC_CD_SDA => ADC_CD_SDA
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 79c2b1400580a02c5830e985980641183a1f83f2..21d59af5fcdb207ef7bc4193713341126651b096 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -22,17 +22,17 @@
-- Purpose: Capture input from two ADU or use WG data and attach timestamp.
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, ppsh_lib, aduh_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.unb1_bn_capture_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.unb1_bn_capture_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
entity unb1_bn_capture_input is
generic (
@@ -143,49 +143,49 @@ begin
aduh_sosi_arr <= (others => c_dp_sosi_rst);
end generate;
- use_adc : if g_use_phy.adc /= 0 generate
+ use_adc : if g_use_phy.adc /= 0 generate
u_aduh_quad : entity aduh_lib.mms_aduh_quad
- generic map (
- -- General
- g_sim => g_sim,
- g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
- -- ADC Interface
- g_nof_dp_phs_clk => g_nof_dp_phs_clk,
- g_ai => g_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => ADC_BI_A,
- ADC_BI_B => ADC_BI_B,
- ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
- ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
-
- -- . ADU_CD
- ADC_BI_C => ADC_BI_C,
- ADC_BI_D => ADC_BI_D,
- ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
- ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
-
- -- MM clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_adc_quad_mosi,
- reg_miso => reg_adc_quad_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
-
- -- . data
- aduh_sosi_arr => aduh_sosi_arr
- );
- end generate;
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
+ -- ADC Interface
+ g_nof_dp_phs_clk => g_nof_dp_phs_clk,
+ g_ai => g_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => ADC_BI_A,
+ ADC_BI_B => ADC_BI_B,
+ ADC_BI_A_CLK => ADC_BI_A_CLK, -- lvds clock from ADU_AB
+ ADC_BI_A_CLK_RST => ADC_BI_A_CLK_RST, -- release synchronises ADU_AB DCLK divider
+
+ -- . ADU_CD
+ ADC_BI_C => ADC_BI_C,
+ ADC_BI_D => ADC_BI_D,
+ ADC_BI_D_CLK => ADC_BI_D_CLK, -- lvds clock from ADU_CD
+ ADC_BI_D_CLK_RST => ADC_BI_D_CLK_RST, -- release synchronises ADU_CD DCLK divider
+
+ -- MM clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_adc_quad_mosi,
+ reg_miso => reg_adc_quad_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+
+ -- . data
+ aduh_sosi_arr => aduh_sosi_arr
+ );
+ end generate;
- gen_wg : for I in 0 to g_ai.nof_sp - 1 generate
- u_sp : entity diag_lib.mms_diag_wg_wideband
+gen_wg : for I in 0 to g_ai.nof_sp - 1 generate
+ u_sp : entity diag_lib.mms_diag_wg_wideband
generic map (
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
g_buf_dir => c_wg_buf_directory,
@@ -222,57 +222,58 @@ begin
out_sync => wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )
);
- -- wires
- -- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
- -- . if one of the wideband sample has overflow, then set the overflow error, so use vector_or()
- wg_sosi_arr(I).data <= RESIZE_DP_SDATA(wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w));
- wg_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
- wg_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
- wg_sosi_arr(I).err <= TO_DP_ERROR(c_unb1_board_ok) when
+ -- wires
+ -- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
+ -- . if one of the wideband sample has overflow, then set the overflow error, so use vector_or()
+ wg_sosi_arr(I).data <= RESIZE_DP_SDATA(wg_dat( (I + 1) * c_wideband_factor * c_wg_buf_dat_w - 1 downto I * c_wideband_factor * c_wg_buf_dat_w));
+ wg_sosi_arr(I).valid <= vector_or(wg_val( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
+ wg_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor ));
+ wg_sosi_arr(I).err <= TO_DP_ERROR(c_unb1_board_ok) when
vector_or(wg_ovr( (I + 1) * c_wideband_factor - 1 downto I * c_wideband_factor )) = '0' else
- TO_DP_ERROR(2**c_unb1_board_error_adc_bi); -- pass ADC or WG overflow info on as an error signal
- end generate;
+ TO_DP_ERROR(2**c_unb1_board_error_adc_bi); -- pass ADC or WG overflow info on as an error signal
+end generate;
- -----------------------------------------------------------------------------
- -- WG / ADU mux
- -----------------------------------------------------------------------------
- gen_mux : for I in 0 to g_ai.nof_sp - 1 generate
- p_sosi : process(aduh_sosi_arr, wg_sosi_arr)
- begin
- -- Valid is forced to '1' here for dp_shiftram.
- nxt_mux_sosi_arr(I).valid <= '1';
-
- -- Default use the ADUH data
- nxt_mux_sosi_arr(I).data <= aduh_sosi_arr(I).data;
- if wg_sosi_arr(I).valid = '1' then
- -- Valid WG data overrules ADUH data
- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
- end if;
- end process;
- end generate;
+-----------------------------------------------------------------------------
+-- WG / ADU mux
+-----------------------------------------------------------------------------
+gen_mux : for I in 0 to g_ai.nof_sp - 1 generate
- p_reg_mux : process(dp_rst, dp_clk)
+ p_sosi : process(aduh_sosi_arr, wg_sosi_arr)
begin
- if dp_rst = '1' then
- mux_sosi_arr <= (others => c_dp_sosi_rst);
- elsif rising_edge(dp_clk) then
- mux_sosi_arr <= nxt_mux_sosi_arr;
+ -- Valid is forced to '1' here for dp_shiftram.
+ nxt_mux_sosi_arr(I).valid <= '1';
+
+ -- Default use the ADUH data
+ nxt_mux_sosi_arr(I).data <= aduh_sosi_arr(I).data;
+ if wg_sosi_arr(I).valid = '1' then
+ -- Valid WG data overrules ADUH data
+ nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
end if;
end process;
+end generate;
- -----------------------------------------------------------------------------
- -- Time delay: dp_shiftram
- -- . dp_shiftram uses DOWNTO range arrays internally vs. TO ranges used here.
- -- func_dp_stream_arr_reverse_range is used to reverse the ranges so
- -- the MM control stream indices are correct.
- -- . The 4 streams are treated individually by the shiftram. This is fine,
- -- because it leaves full control to the LCU via the MM interface.
- -- For Apertif typically the LCU will write the same delay setting to all
- -- 4 streams and in fact to all 64 streams in the PAF.
- -- . The written delay setting must be applied synchronously at the sync, this
- -- is ensured by g_use_sync_in=TRUE and bs_sosi.sync.
- -----------------------------------------------------------------------------
- u_dp_shiftram : entity dp_lib.dp_shiftram
+p_reg_mux : process(dp_rst, dp_clk)
+begin
+ if dp_rst = '1' then
+ mux_sosi_arr <= (others => c_dp_sosi_rst);
+ elsif rising_edge(dp_clk) then
+ mux_sosi_arr <= nxt_mux_sosi_arr;
+ end if;
+end process;
+
+-----------------------------------------------------------------------------
+-- Time delay: dp_shiftram
+-- . dp_shiftram uses DOWNTO range arrays internally vs. TO ranges used here.
+-- func_dp_stream_arr_reverse_range is used to reverse the ranges so
+-- the MM control stream indices are correct.
+-- . The 4 streams are treated individually by the shiftram. This is fine,
+-- because it leaves full control to the LCU via the MM interface.
+-- For Apertif typically the LCU will write the same delay setting to all
+-- 4 streams and in fact to all 64 streams in the PAF.
+-- . The written delay setting must be applied synchronously at the sync, this
+-- is ensured by g_use_sync_in=TRUE and bs_sosi.sync.
+-----------------------------------------------------------------------------
+u_dp_shiftram : entity dp_lib.dp_shiftram
generic map (
g_nof_streams => g_ai.nof_sp, -- 4 signal paths
g_nof_words => 2048,
@@ -296,10 +297,10 @@ begin
func_dp_stream_arr_reverse_range(src_out_arr) => dp_shiftram_src_out_arr
);
- -----------------------------------------------------------------------------
- -- Timestamp
- -----------------------------------------------------------------------------
- u_bsn_sosi : entity dp_lib.mms_dp_bsn_source
+-----------------------------------------------------------------------------
+-- Timestamp
+-----------------------------------------------------------------------------
+u_bsn_sosi : entity dp_lib.mms_dp_bsn_source
generic map (
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
g_block_size => c_bs_block_size,
@@ -322,7 +323,7 @@ begin
bs_sosi => bs_sosi
);
- u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
+u_bsn_trigger_wg : entity dp_lib.mms_dp_bsn_scheduler
generic map (
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
g_bsn_w => c_bs_bsn_w
@@ -343,32 +344,33 @@ begin
trigger_out => dp_bsn_trigger_wg
);
- gen_sosi_ctrl : for I in 0 to g_ai.nof_sp - 1 generate
- p_sosi : process(dp_shiftram_src_out_arr, bs_sosi)
- begin
- -- BS sets the sosi sync, bsn, valid, sop and eop for all signal paths
- nxt_dp_shiftram_src_out_timestamped_arr(I) <= bs_sosi;
- nxt_dp_shiftram_src_out_timestamped_arr(I).data <= dp_shiftram_src_out_arr(I).data;
- end process;
- end generate;
+gen_sosi_ctrl : for I in 0 to g_ai.nof_sp - 1 generate
- p_reg_timestamps : process(dp_rst, dp_clk)
+ p_sosi : process(dp_shiftram_src_out_arr, bs_sosi)
begin
- if dp_rst = '1' then
- dp_shiftram_src_out_timestamped_arr <= (others => c_dp_sosi_rst);
- elsif rising_edge(dp_clk) then
- dp_shiftram_src_out_timestamped_arr <= nxt_dp_shiftram_src_out_timestamped_arr;
- end if;
+ -- BS sets the sosi sync, bsn, valid, sop and eop for all signal paths
+ nxt_dp_shiftram_src_out_timestamped_arr(I) <= bs_sosi;
+ nxt_dp_shiftram_src_out_timestamped_arr(I).data <= dp_shiftram_src_out_arr(I).data;
end process;
+end generate;
- -----------------------------------------------------------------------------
- -- Add SISO flow control to otherwise uninterruptible mux output
- -----------------------------------------------------------------------------
- gen_sp_siso_rdy : for I in 0 to g_ai.nof_sp - 1 generate
- u_dp_ready : entity dp_lib.dp_ready
- generic map (
+p_reg_timestamps : process(dp_rst, dp_clk)
+begin
+ if dp_rst = '1' then
+ dp_shiftram_src_out_timestamped_arr <= (others => c_dp_sosi_rst);
+ elsif rising_edge(dp_clk) then
+ dp_shiftram_src_out_timestamped_arr <= nxt_dp_shiftram_src_out_timestamped_arr;
+ end if;
+end process;
+
+-----------------------------------------------------------------------------
+-- Add SISO flow control to otherwise uninterruptible mux output
+-----------------------------------------------------------------------------
+gen_sp_siso_rdy : for I in 0 to g_ai.nof_sp - 1 generate
+ u_dp_ready : entity dp_lib.dp_ready
+ generic map (
g_ready_latency => 1
- )
+ )
port map (
rst => dp_rst,
clk => dp_clk,
@@ -377,14 +379,14 @@ begin
src_out => sp_sosi_arr(I),
src_in => sp_siso_arr(I)
- );
- end generate;
+ );
+end generate;
- -----------------------------------------------------------------------------
- -- Monitor ADU/WG output
- -----------------------------------------------------------------------------
- gen_mon : for I in 0 to g_ai.nof_sp - 1 generate
- u_sp : entity aduh_lib.mms_aduh_monitor
+-----------------------------------------------------------------------------
+-- Monitor ADU/WG output
+-----------------------------------------------------------------------------
+gen_mon : for I in 0 to g_ai.nof_sp - 1 generate
+ u_sp : entity aduh_lib.mms_aduh_monitor
generic map (
g_cross_clock_domain => c_bn_capture_mm_cross_clock_domain,
g_symbol_w => g_ai.port_w,
@@ -409,12 +411,12 @@ begin
in_sosi => dp_shiftram_src_out_timestamped_arr(I)
);
- end generate;
+end generate;
- -----------------------------------------------------------------------------
- -- Scope monitor for Wave Window
- -----------------------------------------------------------------------------
- u_quad_scope : entity aduh_lib.aduh_quad_scope
+-----------------------------------------------------------------------------
+-- Scope monitor for Wave Window
+-----------------------------------------------------------------------------
+u_quad_scope : entity aduh_lib.aduh_quad_scope
generic map (
g_sim => g_sim,
g_ai => g_ai
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index c6706e2421ec5038f0025dda055ce0ad451a2c4a..cce61474f69563cd73a3502771df53e5937c0929 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -22,10 +22,10 @@
-- Purpose: Multiplex the 4 signal streams into 1 wide stream
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity bn_capture_mux is
generic (
@@ -43,69 +43,69 @@ entity bn_capture_mux is
-- ST sinks (input signal paths)
in_siso_arr : out t_dp_siso_arr(0 to g_nof_input - 1);
in_sosi_arr : in t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A[31:0], B[31:0], C[31:0], D[31:0]]
- -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
+ -- and e.g. A[31:0] = [A(t0), A(t1), A(t2), A(t3)], so 4 8b samples in time per one 32b word
-- ST source (multiplexed output signal paths)
mux_wide_siso : in t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : out t_dp_sosi -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
);
end bn_capture_mux;
architecture str of bn_capture_mux is
signal wide_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A,B,C,D]
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
begin
gen_fifo : for I in 0 to g_nof_input - 1 generate
u_n2w : entity dp_lib.dp_fifo_dc_mixed_widths
+ generic map (
+ g_wr_data_w => g_in_data_w,
+ g_rd_data_w => g_mux_data_w,
+ g_use_ctrl => true,
+ g_wr_fifo_size => g_in_fifo_size,
+ g_rd_fifo_rl => 1
+ )
+ port map (
+ wr_rst => in_rst,
+ wr_clk => in_clk,
+ rd_rst => mux_wide_rst,
+ rd_clk => mux_wide_clk,
+ -- ST sink
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- Monitor FIFO filling
+ wr_usedw => OPEN,
+ rd_usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST source
+ src_in => wide_siso_arr(I),
+ src_out => wide_sosi_arr(I)
+ );
+ end generate;
+
+ gen_mux : entity dp_lib.dp_mux
generic map (
- g_wr_data_w => g_in_data_w,
- g_rd_data_w => g_mux_data_w,
- g_use_ctrl => true,
- g_wr_fifo_size => g_in_fifo_size,
- g_rd_fifo_rl => 1
+ g_data_w => g_mux_data_w,
+ g_empty_w => 1,
+ g_in_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_in_channel => false,
+ g_use_error => false,
+ g_mode => 1,
+ g_nof_input => g_nof_input,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
)
port map (
- wr_rst => in_rst,
- wr_clk => in_clk,
- rd_rst => mux_wide_rst,
- rd_clk => mux_wide_clk,
- -- ST sink
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- Monitor FIFO filling
- wr_usedw => OPEN,
- rd_usedw => OPEN,
- rd_emp => OPEN,
+ rst => mux_wide_rst,
+ clk => mux_wide_clk,
+ -- ST sinks
+ snk_out_arr => wide_siso_arr,
+ snk_in_arr => wide_sosi_arr,
-- ST source
- src_in => wide_siso_arr(I),
- src_out => wide_sosi_arr(I)
+ src_in => mux_wide_siso,
+ src_out => mux_wide_sosi
);
- end generate;
-
- gen_mux : entity dp_lib.dp_mux
- generic map (
- g_data_w => g_mux_data_w,
- g_empty_w => 1,
- g_in_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_in_channel => false,
- g_use_error => false,
- g_mode => 1,
- g_nof_input => g_nof_input,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- dummy value must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_input) -- dummy value must match g_nof_input
- )
- port map (
- rst => mux_wide_rst,
- clk => mux_wide_clk,
- -- ST sinks
- snk_out_arr => wide_siso_arr,
- snk_in_arr => wide_sosi_arr,
- -- ST source
- src_in => mux_wide_siso,
- src_out => mux_wide_sosi
- );
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
index ced8c5739b7c1d50b097614e358faaf035293607..89d8f95bbbe3789803ccb0a442a030ae92ef7010 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
package unb1_bn_capture_pkg is
-- Signal path input
@@ -46,10 +46,10 @@ package unb1_bn_capture_pkg is
sp : t_c_bn_capture_sp;
end record;
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M, -- must match PLL setting in sopc_bn_capture
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp);
-
+ constant c_bn_capture : t_c_bn_capture := ( -- must match PLL setting in sopc_bn_capture
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp);
end unb1_bn_capture_pkg;
package body unb1_bn_capture_pkg is
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 97a864cc1cca127daca023931905f7daa081c719..9d338747e9f982eab6bef94ce51a4f08be42b03b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -22,12 +22,12 @@
-- Purpose: Store the 4 multiplexed signal streams into one DDR3 and readback
library IEEE, common_lib, unb_common_lib, dp_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage is
generic (
@@ -57,7 +57,7 @@ entity bn_capture_storage is
-- ST sink (multiplexed input signal paths)
mux_wide_siso : out t_dp_siso := c_dp_siso_rdy;
mux_wide_sosi : in t_dp_sosi; -- = Signal Paths A[255:0], B[255:0], C[255:0], D[255:0] multiplexed in time
- -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
+ -- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 8b samples in time per one 256b word
-- MM registers
ctrl_mosi : in t_mem_mosi := c_mem_mosi_rst;
ctrl_miso : out t_mem_miso;
@@ -110,56 +110,56 @@ begin
phy_rst <= i_phy_rst;
u_ddr3 : entity ddr3_lib.ddr3
- generic map(
- g_sim => g_sim,
- g_phy => 0,
- g_ddr => g_ddr,
- g_mts => 800,
- g_wr_data_w => c_ddr3_ctlr_data_w,
- g_rd_data_w => c_word_w,
- g_wr_fifo_depth => c_wr_fifo_depth,
- g_rd_fifo_depth => c_rd_fifo_depth / 8,
- g_wr_use_ctrl => true
- )
- port map (
- ctlr_ref_clk => ext_clk,
- ctlr_rst => dp_rst,
-
- ctlr_gen_clk => i_phy_clk,
- ctlr_gen_rst => i_phy_rst,
- ctlr_gen_clk_2x => phy_clk_2x,
- ctlr_gen_rst_2x => phy_rst_2x,
-
- ctlr_init_done => ctlr_init_done,
- ctlr_rdy => ctlr_rdy,
-
- dvr_start_addr => dvr_start_addr,
- dvr_end_addr => dvr_end_addr,
-
- dvr_en => dvr_en,
- dvr_wr_not_rd => dvr_wr_not_rd,
- dvr_done => dvr_done,
- --dvr_flush => dvr_flush,
-
- wr_clk => dp_clk,
- wr_rst => dp_rst,
-
- wr_sosi => mux_wide_sosi,
- wr_siso => mux_wide_siso,
-
- -- ddr3 rd FIFO ST interface to the dp->mm adapter
- rd_sosi => rd_sosi,
- rd_siso => rd_siso,
-
- rd_clk => mm_clk,
- rd_rst => mm_rst,
-
- rd_fifo_usedw => rd_usedw,
-
- phy_in => ddr3_in,
- phy_io => ddr3_io,
- phy_ou => ddr3_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_phy => 0,
+ g_ddr => g_ddr,
+ g_mts => 800,
+ g_wr_data_w => c_ddr3_ctlr_data_w,
+ g_rd_data_w => c_word_w,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth / 8,
+ g_wr_use_ctrl => true
+ )
+ port map (
+ ctlr_ref_clk => ext_clk,
+ ctlr_rst => dp_rst,
+
+ ctlr_gen_clk => i_phy_clk,
+ ctlr_gen_rst => i_phy_rst,
+ ctlr_gen_clk_2x => phy_clk_2x,
+ ctlr_gen_rst_2x => phy_rst_2x,
+
+ ctlr_init_done => ctlr_init_done,
+ ctlr_rdy => ctlr_rdy,
+
+ dvr_start_addr => dvr_start_addr,
+ dvr_end_addr => dvr_end_addr,
+
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => dvr_done,
+ --dvr_flush => dvr_flush,
+
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_sosi => mux_wide_sosi,
+ wr_siso => mux_wide_siso,
+
+ -- ddr3 rd FIFO ST interface to the dp->mm adapter
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
+
+ rd_clk => mm_clk,
+ rd_rst => mm_rst,
+
+ rd_fifo_usedw => rd_usedw,
+
+ phy_in => ddr3_in,
+ phy_io => ddr3_io,
+ phy_ou => ddr3_ou
+ );
-- Flush ddr3 module's FIFO (keep sinking the stream but simply discard the
-- data) after reset to prevent ddr3 write fifo from filling up - which would
@@ -200,51 +200,51 @@ begin
end process;
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
-
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
+ generic map(
+ g_fifo_size => c_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
+
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
);
- -- DDR3 streaming read output to mm bus
- data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
- data_miso.rdval <= mm_rd_val;
- mm_rd <= data_mosi.rd;
+-- DDR3 streaming read output to mm bus
+data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
+data_miso.rdval <= mm_rd_val;
+mm_rd <= data_mosi.rd;
- u_storage_reg : entity work.bn_capture_storage_reg
+u_storage_reg : entity work.bn_capture_storage_reg
generic map(
g_ddr => g_ddr
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => i_phy_rst,
- st_clk => i_phy_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => i_phy_rst,
+ st_clk => i_phy_clk,
- sla_in => ctrl_mosi,
- sla_out => ctrl_miso,
+ sla_in => ctrl_mosi,
+ sla_out => ctrl_miso,
- st_en_evt => dvr_en,
- st_wr_not_rd => dvr_wr_not_rd,
+ st_en_evt => dvr_en,
+ st_wr_not_rd => dvr_wr_not_rd,
- st_start_addr => dvr_start_addr,
- st_end_addr => dvr_end_addr,
+ st_start_addr => dvr_start_addr,
+ st_end_addr => dvr_end_addr,
- st_done => dvr_done,
- st_init_done => ctlr_init_done,
- st_ctlr_rdy => ctlr_rdy,
+ st_done => dvr_done,
+ st_init_done => ctlr_init_done,
+ st_ctlr_rdy => ctlr_rdy,
- mm_rd_usedw => mm_rd_usedw
+ mm_rd_usedw => mm_rd_usedw
);
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index ded28ec91ca04a869ec6d7e2dbe80d9210eced4b..9bcf591b43bc74051894f9e23d6ee72afe68e415 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity bn_capture_storage_reg is
generic (
g_ddr : t_c_ddr3_phy
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -53,28 +53,29 @@ entity bn_capture_storage_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end bn_capture_storage_reg;
architecture rtl of bn_capture_storage_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_en_evt : std_logic;
- signal mm_wr_not_rd : std_logic;
-
- signal mm_start_address : std_logic_vector(31 downto 0);
- signal mm_end_address : std_logic_vector(31 downto 0);
-
- signal st_start_address : std_logic_vector(31 downto 0);
- signal st_end_address : std_logic_vector(31 downto 0);
-
- signal mm_done : std_logic;
- signal mm_init_done : std_logic;
- signal mm_ctlr_rdy : std_logic;
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0');
+ -- Registers in mm_clk domain
+ signal mm_en_evt : std_logic;
+ signal mm_wr_not_rd : std_logic;
+
+ signal mm_start_address : std_logic_vector(31 downto 0);
+ signal mm_end_address : std_logic_vector(31 downto 0);
+
+ signal st_start_address : std_logic_vector(31 downto 0);
+ signal st_end_address : std_logic_vector(31 downto 0);
+
+ signal mm_done : std_logic;
+ signal mm_init_done : std_logic;
+ signal mm_ctlr_rdy : std_logic;
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -104,7 +105,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_en_evt <= sla_in.wrdata(0);
when 1 =>
@@ -116,12 +117,12 @@ begin
when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 2 =>
sla_out.rddata(0) <= mm_done;
when 3 =>
@@ -154,59 +155,59 @@ begin
------------------------------------------------------------------------------
u_spulse_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_en_evt,
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => st_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_en_evt,
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => st_en_evt
+ );
u_async_wr_not_rd : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_wr_not_rd,
- dout => st_wr_not_rd
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_wr_not_rd,
+ dout => st_wr_not_rd
+ );
u_async_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_done,
- dout => mm_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_done,
+ dout => mm_done
+ );
u_async_init_done : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_init_done,
- dout => mm_init_done
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_init_done,
+ dout => mm_init_done
+ );
u_async_rdy : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_ctlr_rdy,
- dout => mm_ctlr_rdy
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_ctlr_rdy,
+ dout => mm_ctlr_rdy
+ );
-- Address range should be set before asserting the DDR3 enable bit.
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 6c96281275b7a849cd9deb61c52e1a746606a05e..daba861db0e169b833d49de7800ea6421f55bff8 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -40,22 +40,22 @@
-- proves that the tb has run.
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, aduh_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use i2c_lib.i2c_commander_pkg.all;
-use i2c_lib.i2c_commander_aduh_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use i2c_lib.i2c_commander_pkg.all;
+ use i2c_lib.i2c_commander_aduh_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity tb_node_unb1_bn_capture is
generic (
@@ -82,9 +82,10 @@ architecture tb of tb_node_unb1_bn_capture is
constant c_fw_version : t_unb1_board_fw_version := (1, 0);
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp_sim);
constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
constant c_mm_clk_period : time := 20 ns; -- 50 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
@@ -99,8 +100,8 @@ architecture tb of tb_node_unb1_bn_capture is
constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
constant c_wideband_factor : natural := c_dp_factor; -- = 4
- constant c_sample_freq : natural := c_wideband_factor * c_unb1_board_ext_clk_freq_200M / 10**6; -- 800 MSps
- constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps; -- 1250 ns
+ constant c_sample_freq : natural := c_wideband_factor * c_unb1_board_ext_clk_freq_200M / 10 ** 6; -- 800 MSps
+ constant c_sample_period : time := (10 ** 6 / c_sample_freq) * 1 ps; -- 1250 ns
constant c_ext_clk_freq : natural := c_unb1_board_ext_clk_freq_200M; -- 200 MHz external reference clock for data path processing
constant c_ext_clk_period : time := c_wideband_factor * c_sample_period; -- 200 MHz
@@ -282,10 +283,10 @@ begin
-- . phase[15:0]
-- . freq[30:0]
-- . ampl[16:0]
- proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(0)); -- mode repeat, nof_sample
- proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(1));
- proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(2));
- proc_mem_mm_bus_wr(0, 2 + 1024 * 2**16, mm_clk, reg_wg_mosi_arr(3));
+ proc_mem_mm_bus_wr(0, 2 + 1024 * 2 ** 16, mm_clk, reg_wg_mosi_arr(0)); -- mode repeat, nof_sample
+ proc_mem_mm_bus_wr(0, 2 + 1024 * 2 ** 16, mm_clk, reg_wg_mosi_arr(1));
+ proc_mem_mm_bus_wr(0, 2 + 1024 * 2 ** 16, mm_clk, reg_wg_mosi_arr(2));
+ proc_mem_mm_bus_wr(0, 2 + 1024 * 2 ** 16, mm_clk, reg_wg_mosi_arr(3));
proc_common_wait_some_cycles(mm_clk, 10);
-- Read current BSN
@@ -351,7 +352,7 @@ begin
cmdr_result_error_cnt(c_A) <= TO_UINT(reg_commander_miso_arr(c_A).rddata);
proc_common_wait_some_cycles(mm_clk, 1);
assert cmdr_result_error_cnt(c_A) = 0
- report "The result error count is not 0" severity ERROR;
+ report "The result error count is not 0" severity ERROR;
-- Read commander result data
for J in 0 to c_i2c_cmdr_aduh_nof_result_data_arr(c_P) - 1 loop
@@ -383,134 +384,134 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => c_sim,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_bn_capture.mm_clk_freq,
- g_dp_clk_freq => c_bn_capture.dp_clk_freq,
- g_use_phy => g_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- -- Clock an reset signals
- -- System
- cs_sim => OPEN,
- xo_clk => OPEN,
- xo_rst_n => OPEN,
-
- mm_clk => mm_clk, -- 50 MHz
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- 200 MHz from CLK system clock
- dp_pps => dp_pps, -- PPS in dp_clk domain
- dp_rst_in => dp_rst, -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in => dp_clk, -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- eth1g
- eth1g_tse_clk => '0',
- eth1g_mm_rst => '1',
- eth1g_tse_mosi => c_mem_mosi_rst,
- eth1g_tse_miso => OPEN,
- eth1g_reg_mosi => c_mem_mosi_rst,
- eth1g_reg_miso => OPEN,
- eth1g_reg_interrupt => OPEN,
- eth1g_ram_mosi => c_mem_mosi_rst,
- eth1g_ram_miso => OPEN,
-
- -- FPGA pins
- -- . General
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp
- );
+ generic map (
+ g_sim => c_sim,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_bn_capture.mm_clk_freq,
+ g_dp_clk_freq => c_bn_capture.dp_clk_freq,
+ g_use_phy => g_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ -- Clock an reset signals
+ -- System
+ cs_sim => OPEN,
+ xo_clk => OPEN,
+ xo_rst_n => OPEN,
+
+ mm_clk => mm_clk, -- 50 MHz
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- 200 MHz from CLK system clock
+ dp_pps => dp_pps, -- PPS in dp_clk domain
+ dp_rst_in => dp_rst, -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_clk_in => dp_clk, -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- eth1g
+ eth1g_tse_clk => '0',
+ eth1g_mm_rst => '1',
+ eth1g_tse_mosi => c_mem_mosi_rst,
+ eth1g_tse_miso => OPEN,
+ eth1g_reg_mosi => c_mem_mosi_rst,
+ eth1g_reg_miso => OPEN,
+ eth1g_reg_interrupt => OPEN,
+ eth1g_ram_mosi => c_mem_mosi_rst,
+ eth1g_ram_miso => OPEN,
+
+ -- FPGA pins
+ -- . General
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp
+ );
u_node : entity work.node_unb1_bn_capture
- generic map (
- -- General
- g_sim => c_sim,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- ADC Interface
- g_ai => c_ai
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
-
- ext_clk => ext_clk,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM registers [0,1,2,3] for wideband waveform generators [A,B,C,D]
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM registers [0,1] for I2C access with ADU AB and with ADU CD
- reg_commander_mosi_arr => reg_commander_mosi_arr,
- reg_commander_miso_arr => reg_commander_miso_arr,
- ram_protocol_mosi_arr => ram_protocol_mosi_arr,
- ram_protocol_miso_arr => ram_protocol_miso_arr,
- ram_result_mosi_arr => ram_result_mosi_arr,
- ram_result_miso_arr => ram_result_miso_arr,
-
- -- MM registers to enable and disable signal path
- reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
- reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
- reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
- reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
-
- -- ADC Interface
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- ADC_AB_SCL => ADC_AB_SCL,
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL,
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => g_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- ADC Interface
+ g_ai => c_ai
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+
+ ext_clk => ext_clk,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM registers [0,1,2,3] for wideband waveform generators [A,B,C,D]
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM registers [0,1] for I2C access with ADU AB and with ADU CD
+ reg_commander_mosi_arr => reg_commander_mosi_arr,
+ reg_commander_miso_arr => reg_commander_miso_arr,
+ ram_protocol_mosi_arr => ram_protocol_mosi_arr,
+ ram_protocol_miso_arr => ram_protocol_miso_arr,
+ ram_result_mosi_arr => ram_result_mosi_arr,
+ ram_result_miso_arr => ram_result_miso_arr,
+
+ -- MM registers to enable and disable signal path
+ reg_bsn_scheduler_sp_on_mosi => reg_bsn_scheduler_sp_on_mosi,
+ reg_bsn_scheduler_sp_on_miso => reg_bsn_scheduler_sp_on_miso,
+ reg_bsn_scheduler_sp_off_mosi => reg_bsn_scheduler_sp_off_mosi,
+ reg_bsn_scheduler_sp_off_miso => reg_bsn_scheduler_sp_off_miso,
+
+ -- ADC Interface
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ ADC_AB_SCL => ADC_AB_SCL,
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL,
+ ADC_CD_SDA => ADC_CD_SDA
+ );
-----------------------------------------------------------------------------
-- ADU0 model and ADU1 model for BN port A,B and C,D
@@ -529,36 +530,36 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- OVR => DIG_OVR_AB,
- SCL => ADC_AB_SCL,
- SDA => ADC_AB_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ OVR => DIG_OVR_AB,
+ SCL => ADC_AB_SCL,
+ SDA => ADC_AB_SDA,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- OVR => DIG_OVR_CD,
- SCL => ADC_CD_SCL,
- SDA => ADC_CD_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ OVR => DIG_OVR_CD,
+ SCL => ADC_CD_SCL,
+ SDA => ADC_CD_SDA,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- 1GbE Loopback model
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
index 1cf7b5d6fb00cd64f696b1d5682bb1bcfb73bf9b..8f0ee2fcd9e589e6141f931cb9b2f500261b96f3 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
@@ -35,20 +35,20 @@
-- . Set g_use_phy = (0, 0, 0, 0, 1, 0, 1, 0)
library IEEE, common_lib, dp_lib, i2c_lib, unb1_board_lib, diag_lib, aduh_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
-use i2c_lib.i2c_dev_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
+ use i2c_lib.i2c_dev_unb_pkg.all;
entity tb_bn_capture is
generic (
@@ -74,9 +74,10 @@ architecture tb of tb_bn_capture is
constant c_fw_version : t_unb_fw_version := (1, 0);
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 1024 * 1024, 1024, true); -- 800 MSps, block size 1024 samples, nof blocks per sync interval, monitor buffer nof samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb_mm_clk_freq_50M,
- c_unb_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb_mm_clk_freq_50M,
+ c_unb_ext_clk_freq_200M,
+ c_bn_capture_sp_sim);
constant c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g; -- use c_ddr3_phy_4g or c_ddr3_phy_1g dependent on what was generated with the MegaWizard
@@ -94,8 +95,8 @@ architecture tb of tb_bn_capture is
constant c_dp_factor : natural := c_ai.rx_factor * c_ai.dd_factor;
constant c_wideband_factor : natural := c_dp_factor; -- = 4
- constant c_sample_freq : natural := c_wideband_factor * c_unb_ext_clk_freq_200M / 10**6; -- 800 MSps
- constant c_sample_period : time := (10**6 / c_sample_freq) * 1 ps; -- 1250 ns
+ constant c_sample_freq : natural := c_wideband_factor * c_unb_ext_clk_freq_200M / 10 ** 6; -- 800 MSps
+ constant c_sample_period : time := (10 ** 6 / c_sample_freq) * 1 ps; -- 1250 ns
constant c_ext_clk_freq : natural := c_unb_ext_clk_freq_200M; -- 200 MHz external reference clock for data path processing
constant c_ext_clk_period : time := c_wideband_factor * c_sample_period; -- 200 MHz
@@ -171,14 +172,14 @@ begin
sens_sda <= 'H'; -- pull up
u_sens_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_max1618_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_max1618_temp
- );
+ generic map (
+ g_address => c_max1618_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_max1618_temp
+ );
VERSION <= c_version;
ID <= c_id_bn0;
@@ -188,69 +189,69 @@ begin
------------------------------------------------------------------------------
dut : entity work.bn_capture
- generic map (
- -- General
- g_sim => c_sim,
- g_fw_version => c_fw_version,
- -- BN capture specific
- g_bn_capture => c_bn_capture,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => c_unb_aux,
- -- DDR3 Interface
- g_ddr => c_ddr,
- -- ADC Interface
- g_nof_dp_phs_clk => c_nof_dp_phs_clk,
- g_ai => c_ai
- )
- port map (
- -- GENERAL
- CLK => ext_clk,
- PPS => ext_pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou,
-
- -- SO-DIMM Memory Bank II = ddr3_II
- MB_II_IN => MB_II_in,
- MB_II_IO => MB_II_io,
- MB_II_OU => MB_II_ou,
-
- -- ADC Interface
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- ADC_AB_SCL => ADC_AB_SCL,
- ADC_AB_SDA => ADC_AB_SDA,
- ADC_CD_SCL => ADC_CD_SCL,
- ADC_CD_SDA => ADC_CD_SDA
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_fw_version => c_fw_version,
+ -- BN capture specific
+ g_bn_capture => c_bn_capture,
+ -- Use PHY Interface
+ g_use_phy => g_use_phy,
+ -- Auxiliary Interface
+ g_aux => c_unb_aux,
+ -- DDR3 Interface
+ g_ddr => c_ddr,
+ -- ADC Interface
+ g_nof_dp_phs_clk => c_nof_dp_phs_clk,
+ g_ai => c_ai
+ )
+ port map (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou,
+
+ -- SO-DIMM Memory Bank II = ddr3_II
+ MB_II_IN => MB_II_in,
+ MB_II_IO => MB_II_io,
+ MB_II_OU => MB_II_ou,
+
+ -- ADC Interface
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ ADC_AB_SCL => ADC_AB_SCL,
+ ADC_AB_SDA => ADC_AB_SDA,
+ ADC_CD_SCL => ADC_CD_SCL,
+ ADC_CD_SDA => ADC_CD_SDA
+ );
-----------------------------------------------------------------------------
-- ADU0 model and ADU1 model for BN port A,B and C,D
@@ -272,36 +273,36 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- OVR => DIG_OVR_AB,
- SCL => ADC_AB_SCL,
- SDA => ADC_AB_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ OVR => DIG_OVR_AB,
+ SCL => ADC_AB_SCL,
+ SDA => ADC_AB_SDA,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- AOVR => ANA_OVR,
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- OVR => DIG_OVR_CD,
- SCL => ADC_CD_SCL,
- SDA => ADC_CD_SDA,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ AOVR => ANA_OVR,
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ OVR => DIG_OVR_CD,
+ SCL => ADC_CD_SCL,
+ SDA => ADC_CD_SDA,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- 1GbE Loopback model
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index 3c4226b3cc4c4723d29f664c07f4f5ac68d708a4..9eb689f4540a2ead58da4c2d39fa161096a0bd33 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -49,19 +49,19 @@
-- that the tb has run.
library IEEE, common_lib, dp_lib, diag_lib, aduh_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use work.unb1_bn_capture_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use aduh_lib.aduh_dd_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use work.unb1_bn_capture_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use aduh_lib.aduh_dd_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity tb_unb1_bn_capture_input is
end tb_unb1_bn_capture_input;
@@ -70,14 +70,15 @@ architecture tb of tb_unb1_bn_capture_input is
constant c_sim : boolean := true;
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
- constant c_bn_capture : t_c_bn_capture := (c_unb1_board_mm_clk_freq_50M,
- c_unb1_board_ext_clk_freq_200M,
- c_bn_capture_sp_sim);
+ constant c_bn_capture : t_c_bn_capture := (
+ c_unb1_board_mm_clk_freq_50M,
+ c_unb1_board_ext_clk_freq_200M,
+ c_bn_capture_sp_sim);
constant c_ram_wg_dat_w : natural := c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
- constant c_ram_wg_size : natural := 2**c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
+ constant c_ram_wg_size : natural := 2 ** c_unb1_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
constant c_ram_mon_dat_w : natural := c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_dat_w;
- constant c_ram_mon_size : natural := 2**c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w;
+ constant c_ram_mon_size : natural := 2 ** c_unb1_board_peripherals_mm_reg_default.ram_aduh_mon_adr_w;
constant c_nof_block_per_sync : natural := c_bn_capture.sp.nof_samples_per_sync / c_bn_capture.sp.nof_samples_per_block;
constant c_nof_block_per_monitor_buffer : natural := c_bn_capture.sp.monitor_buffer_nof_samples / c_bn_capture.sp.nof_samples_per_block;
@@ -264,10 +265,10 @@ begin
-- . phase[15:0]
-- . freq[30:0]
-- . ampl[16:0]
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(1));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(2));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(3));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(1));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(2));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(3));
proc_mem_mm_bus_wr(1, integer( 0.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(0)); -- phase offset in degrees
proc_mem_mm_bus_wr(1, integer( 90.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(1));
proc_mem_mm_bus_wr(1, integer(180.0 * c_diag_wg_phase_unit), mm_clk, reg_wg_mosi_arr(2));
@@ -296,10 +297,10 @@ begin
----------------------------------------------------------------------------
-- Enable calc mode
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(0)); -- mode calc, nof_sample
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(1));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(2));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 1, mm_clk, reg_wg_mosi_arr(3));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 1, mm_clk, reg_wg_mosi_arr(0)); -- mode calc, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 1, mm_clk, reg_wg_mosi_arr(1));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 1, mm_clk, reg_wg_mosi_arr(2));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 1, mm_clk, reg_wg_mosi_arr(3));
-- Write BSN scheduler to trigger start of WG at specific block
v_bsn := c_bsn_schedule_wg_on;
@@ -355,10 +356,10 @@ begin
end loop;
-- Disable WG takes effect immediatly
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(1));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(2));
- proc_mem_mm_bus_wr(0, 1024 * 2**16 + 0, mm_clk, reg_wg_mosi_arr(3));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(0)); -- mode off, nof_sample
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(1));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(2));
+ proc_mem_mm_bus_wr(0, 1024 * 2 ** 16 + 0, mm_clk, reg_wg_mosi_arr(3));
-- Write scheduler BSN to trigger WG at specific block (no effect, because WG off already takes effect immediatly)
v_bsn := TO_UINT(current_bsn) + 2;
@@ -456,7 +457,7 @@ begin
-- Read ADUH monitor buffer at BSN
for K in 0 to c_bsn_schedule_nof_events - 1 loop
while unsigned(current_bsn) < c_bsn_schedule_aduh_monitor + K * c_nof_block_per_sync loop
- proc_common_wait_some_cycles(mm_clk, 1);
+ proc_common_wait_some_cycles(mm_clk, 1);
end loop;
-- Read the RAM waveform buffer for all 4 wideband waveform generators
@@ -513,90 +514,90 @@ begin
-- National ADC
u_adc_AB : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_A),
- AQ => TO_SINT(ANA_B),
- CLK => SCLK,
- DCLK => DCLK_AB,
- DCLK_RST => DCLK_RST_AB,
- DI => DIG_A,
- DQ => DIG_B,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_A),
+ AQ => TO_SINT(ANA_B),
+ CLK => SCLK,
+ DCLK => DCLK_AB,
+ DCLK_RST => DCLK_RST_AB,
+ DI => DIG_A,
+ DQ => DIG_B,
+ test_pattern_en => test_pattern_en
+ );
u_adc_CD : entity aduh_lib.adu_half
- port map (
- AI => TO_SINT(ANA_C),
- AQ => TO_SINT(ANA_D),
- CLK => SCLK,
- DCLK => DCLK_CD,
- DCLK_RST => DCLK_RST_CD,
- DI => DIG_C,
- DQ => DIG_D,
- test_pattern_en => test_pattern_en
- );
+ port map (
+ AI => TO_SINT(ANA_C),
+ AQ => TO_SINT(ANA_D),
+ CLK => SCLK,
+ DCLK => DCLK_CD,
+ DCLK_RST => DCLK_RST_CD,
+ DI => DIG_C,
+ DQ => DIG_D,
+ test_pattern_en => test_pattern_en
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
dut : entity work.unb1_bn_capture_input
- generic map (
- g_sim => c_sim,
- g_bn_capture => c_bn_capture,
- g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
- g_ai => c_ai
- )
- port map (
- -- ADC Interface
- -- . ADU_AB
- ADC_BI_A => DIG_A,
- ADC_BI_B => DIG_B,
- ADC_BI_A_CLK => DCLK_AB,
- ADC_BI_A_CLK_RST => DCLK_RST_AB,
-
- -- . ADU_CD
- ADC_BI_C => DIG_C,
- ADC_BI_D => DIG_D,
- ADC_BI_D_CLK => DCLK_CD,
- ADC_BI_D_CLK_RST => DCLK_RST_CD,
-
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_phs_clk_vec => dp_phs_clk_vec,
- dp_pps => dp_pps,
-
- -- MM bsn source
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
-
- -- MM bsn schedule WG
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
-
- -- MM aduh quad
- reg_adc_quad_mosi => reg_adc_quad_mosi,
- reg_adc_quad_miso => reg_adc_quad_miso,
-
- -- MM waveform generators
- reg_wg_mosi_arr => reg_wg_mosi_arr,
- reg_wg_miso_arr => reg_wg_miso_arr,
- ram_wg_mosi_arr => ram_wg_mosi_arr,
- ram_wg_miso_arr => ram_wg_miso_arr,
-
- -- MM signal path monitors
- reg_mon_mosi_arr => reg_mon_mosi_arr,
- reg_mon_miso_arr => reg_mon_miso_arr,
- ram_mon_mosi_arr => ram_mon_mosi_arr,
- ram_mon_miso_arr => ram_mon_miso_arr,
-
- -- Streaming output (can be from ADU or from internal WG)
- sp_sosi_arr => sp_sosi_arr,
- sp_siso_arr => sp_siso_arr
- );
+ generic map (
+ g_sim => c_sim,
+ g_bn_capture => c_bn_capture,
+ g_nof_dp_phs_clk => dp_phs_clk_vec'LENGTH,
+ g_ai => c_ai
+ )
+ port map (
+ -- ADC Interface
+ -- . ADU_AB
+ ADC_BI_A => DIG_A,
+ ADC_BI_B => DIG_B,
+ ADC_BI_A_CLK => DCLK_AB,
+ ADC_BI_A_CLK_RST => DCLK_RST_AB,
+
+ -- . ADU_CD
+ ADC_BI_C => DIG_C,
+ ADC_BI_D => DIG_D,
+ ADC_BI_D_CLK => DCLK_CD,
+ ADC_BI_D_CLK_RST => DCLK_RST_CD,
+
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_phs_clk_vec => dp_phs_clk_vec,
+ dp_pps => dp_pps,
+
+ -- MM bsn source
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+
+ -- MM bsn schedule WG
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
+
+ -- MM aduh quad
+ reg_adc_quad_mosi => reg_adc_quad_mosi,
+ reg_adc_quad_miso => reg_adc_quad_miso,
+
+ -- MM waveform generators
+ reg_wg_mosi_arr => reg_wg_mosi_arr,
+ reg_wg_miso_arr => reg_wg_miso_arr,
+ ram_wg_mosi_arr => ram_wg_mosi_arr,
+ ram_wg_miso_arr => ram_wg_miso_arr,
+
+ -- MM signal path monitors
+ reg_mon_mosi_arr => reg_mon_mosi_arr,
+ reg_mon_miso_arr => reg_mon_miso_arr,
+ ram_mon_mosi_arr => ram_mon_mosi_arr,
+ ram_mon_miso_arr => ram_mon_miso_arr,
+
+ -- Streaming output (can be from ADU or from internal WG)
+ sp_sosi_arr => sp_sosi_arr,
+ sp_siso_arr => sp_siso_arr
+ );
------------------------------------------------------------------------------
-- Verify
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index f1ac60af9ffc42bc825a84959c8143f0e40f447b..6af13d88d994a4e781c622f2e7217cc9091a7582 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity node_unb1_bn_terminal_bg is
generic(
@@ -133,28 +133,28 @@ begin
-----------------------------------------------------------------------------
gen_bg : if g_use_bg = true generate
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_usr_nof_streams,
- g_buf_dat_w => g_usr_data_w,
- g_buf_addr_w => ceil_log2(g_usr_block_len),
- g_file_name_prefix => "UNUSED"
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_usr_nof_streams,
+ g_buf_dat_w => g_usr_data_w,
+ g_buf_addr_w => ceil_log2(g_usr_block_len),
+ g_file_name_prefix => "UNUSED"
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
end generate;
no_bg : if g_use_bg = false generate
@@ -166,6 +166,7 @@ begin
-- Map the 16 BG streams into 4*4 streams; 4 streams for each UniBoard 3..0.
-----------------------------------------------------------------------------
gen_bg_unb : for i in 0 to c_unb1_board_nof_uniboard - 1 generate
+
gen_bg_st : for j in 0 to c_back_usr_nof_input - 1 generate
bg_siso_arr(i * c_back_usr_nof_input + j) <= bg_siso_2arr(i)(j);
bg_sosi_2arr(i)(j) <= bg_sosi_arr(i * c_back_usr_nof_input + j);
@@ -191,55 +192,55 @@ begin
back_tx_usr_sosi_2arr <= bg_sosi_2arr;
u_terminals_back: entity unb1_board_lib.unb1_board_terminals_back
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_back_nof_serial,
- g_phy_gx_mbps => g_back_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- -- Tx
- g_tx_input_use_fifo => true,
- -- Rx
- g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_timeout_w => c_rx_timeout_w
- )
- port map (
- bck_id => bck_id,
-
- tr_clk => tr_back_clk,
- cal_clk => cal_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User I/O side (4 uniboards)(4 i/o streams)
- tx_usr_siso_2arr => back_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
- rx_usr_siso_2arr => back_rx_usr_siso_2arr,
- rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => back_tx_serial_2arr, -- Tx
- rx_serial_2arr => back_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_diagnostics_miso => reg_back_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_nof_bus => c_unb1_board_nof_uniboard, -- = 4 Uniboard in subrack, this UniBoard and 3 other UniBoards, so each UniBoard can be indexed by logical index 3:0
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_back_nof_serial,
+ g_phy_gx_mbps => g_back_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ -- Tx
+ g_tx_input_use_fifo => true,
+ -- Rx
+ g_rx_output_use_fifo => false, -- no need for Rx output FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_timeout_w => c_rx_timeout_w
+ )
+ port map (
+ bck_id => bck_id,
+
+ tr_clk => tr_back_clk,
+ cal_clk => cal_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User I/O side (4 uniboards)(4 i/o streams)
+ tx_usr_siso_2arr => back_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => back_tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => back_rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => back_rx_usr_sosi_2arr,
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => back_tx_serial_2arr, -- Tx
+ rx_serial_2arr => back_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_diagnostics_miso => reg_back_diagnostics_miso
+ );
-----------------------------------------------------------------------------
-- Back terminals -> transpose -> mesh terminals
@@ -253,63 +254,62 @@ begin
-----------------------------------------------------------------------------
gen_mesh: if g_use_mesh = true generate
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_bn,
- g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_mesh_usr_nof_input,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => true, -- user Tx must be TRUE for BG in BN,
- g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
- -- Rx
- g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
- g_rx_output_use_fifo => false, -- no user Rx
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
- tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
-
- -- Serial mesh interface (tr_nonbonded)
- tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
- rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
-
- -- MM Control
- reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
-
- reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_bn,
+ g_nof_bus => c_unb1_board_nof_fn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_mesh_usr_nof_input,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_bram_m9k_fifo_depth,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => true, -- user Tx must be TRUE for BG in BN,
+ g_tx_input_use_fifo => true, -- Tx input uses FIFO to create slack for inserting DP Packet and Uthernet frame headers
+ -- Rx
+ g_use_rx => g_mesh_use_rx, -- optionally do support diag Rx
+ g_rx_output_use_fifo => false, -- no user Rx
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => mesh_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => mesh_tx_usr_sosi_2arr, -- Tx (user Rx from FN to BN is unused)
+
+ -- Serial mesh interface (tr_nonbonded)
+ tx_serial_2arr => mesh_tx_serial_2arr, -- Tx
+ rx_serial_2arr => mesh_rx_serial_2arr, -- Rx
+
+ -- MM Control
+ reg_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+
+ reg_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index a5254c63ff944c2e7aa6b0f5e8f60ce9605a1a86..51e18087288e93a284f6a026a7c98a921735f4f5 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb1_bn_terminal_bg is
generic (
@@ -40,7 +40,7 @@ entity unb1_bn_terminal_bg is
g_stamp_svn : natural := 0 -- SVN revision
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -86,17 +86,17 @@ end unb1_bn_terminal_bg;
architecture str of unb1_bn_terminal_bg is
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 1, 0, 0, 0, 1);
-- Transceivers Interface
constant c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
@@ -147,7 +147,7 @@ architecture str of unb1_bn_terminal_bg is
signal rom_unb_system_info_mosi : t_mem_mosi;
signal rom_unb_system_info_miso : t_mem_miso;
- -- WDI override
+ -- WDI override
signal reg_wdi_mosi : t_mem_mosi;
signal reg_wdi_miso : t_mem_miso;
@@ -205,304 +205,304 @@ begin
-----------------------------------------------------------------------------
u_sopc : entity work.sopc_unb1_bn_terminal_bg
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_back
- coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_back
- coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_back => OPEN,
- coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_back => OPEN,
- coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_mesh_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_mesh_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_mesh_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_back
+ coe_address_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_back => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_back => reg_back_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_back
+ coe_address_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_back => OPEN,
+ coe_read_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_back => reg_back_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_back => OPEN,
+ coe_write_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_back => reg_back_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => this_bck_id,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => this_bck_id,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- Design function
-----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity work.node_unb1_bn_terminal_bg
- generic map(
- g_sim => g_sim,
- -- Application interface
- g_use_bg => true,
- g_usr_nof_streams => c_usr_nof_streams,
- g_usr_block_len => c_usr_block_len,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_use_back => g_rev_multi_unb,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_gx_mbps => c_mesh_gx_mbps,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- g_mesh_ena_reorder => true,
- -- Auxiliary Interface
- g_aux => c_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- tr_back_clk => SA_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id,
-
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ -- Application interface
+ g_use_bg => true,
+ g_usr_nof_streams => c_usr_nof_streams,
+ g_usr_block_len => c_usr_block_len,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_use_back => g_rev_multi_unb,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_gx_mbps => c_mesh_gx_mbps,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ g_mesh_ena_reorder => true,
+ -- Auxiliary Interface
+ g_aux => c_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ tr_back_clk => SA_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id,
+
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Wires
@@ -514,42 +514,41 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => mesh_tx_serial_2arr,
- rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => mesh_tx_serial_2arr,
+ rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
gen_tr_back : if c_use_phy.tr_back /= 0 generate
u_back_io : entity unb1_board_lib.unb1_board_back_io
- generic map (
- g_bus_w => c_tr_back.bus_w
- )
- port map (
- tx_serial_2arr => back_tx_serial_2arr,
- rx_serial_2arr => back_rx_serial_2arr,
-
- -- Serial I/O
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX
- );
+ generic map (
+ g_bus_w => c_tr_back.bus_w
+ )
+ port map (
+ tx_serial_2arr => back_tx_serial_2arr,
+ rx_serial_2arr => back_rx_serial_2arr,
+
+ -- Serial I/O
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX
+ );
end generate;
-
end;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index 65c1746710ca576d7336ad7f67c21868b6746d2e..eb4021da1a06e5eae8f95bd129df506fb24321a5 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -28,17 +28,17 @@
-- behaviour in the Wave window.
library IEEE, common_lib, dp_lib, diag_lib, bf_lib, unb1_board_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diagnostics_lib.tb_diagnostics_trnb_pkg.all;
entity tb_node_unb1_bn_terminal_bg is
generic (
@@ -115,7 +115,7 @@ architecture tb of tb_node_unb1_bn_terminal_bg is
-- TRNB diagnostics
constant c_nof_gx : natural := g_mesh_nof_serial * c_unb1_board_nof_node; -- = 12 = 3 * 4
- constant c_nof_gx_mask : natural := 2**c_nof_gx - 1;
+ constant c_nof_gx_mask : natural := 2 ** c_nof_gx - 1;
constant c_gx_link_delay : real := 3.0; -- unit us
signal i_tb_end : std_logic;
@@ -213,27 +213,27 @@ begin
-- GENERATE BLOCK GENERATOR FOR STIMULI ON SOSI PORT
---------------------------------------------------------------
u_block_generator : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => g_bf.nof_input_streams,
- g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
- g_file_index_arr => g_bg_data_file_index_arr,
- g_file_name_prefix => g_bg_data_file_name
- )
- port map(
- -- Clocks and Reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => '1',
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => open,
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => open,
- out_siso_arr => in_siso_arr,
- out_sosi_arr => in_sosi_arr
- );
+ generic map(
+ g_nof_streams => g_bf.nof_input_streams,
+ g_buf_dat_w => c_nof_complex * g_bf.in_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
+ g_file_index_arr => g_bg_data_file_index_arr,
+ g_file_name_prefix => g_bg_data_file_name
+ )
+ port map(
+ -- Clocks and Reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => '1',
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => open,
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => open,
+ out_siso_arr => in_siso_arr,
+ out_sosi_arr => in_sosi_arr
+ );
----------------------------------------------------------------------------
-- Stimuli for TRNB diagnostics
@@ -257,15 +257,15 @@ begin
while true loop
proc_diagnostics_trnb_run_and_verify(g_chip_id,
- c_nof_gx,
- c_nof_gx_mask,
- c_gx_link_delay,
- g_diagnostics_on_interval,
- g_diagnostics_off_interval,
- c_mm_clk_1us,
- mm_clk,
- reg_mesh_diagnostics_miso,
- reg_mesh_diagnostics_mosi);
+ c_nof_gx,
+ c_nof_gx_mask,
+ c_gx_link_delay,
+ g_diagnostics_on_interval,
+ g_diagnostics_off_interval,
+ c_mm_clk_1us,
+ mm_clk,
+ reg_mesh_diagnostics_miso,
+ reg_mesh_diagnostics_mosi);
end loop;
end if;
@@ -277,73 +277,73 @@ begin
------------------------------------------------------------------------------
u_dut : entity work.node_unb1_bn_terminal_bg
- generic map (
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- -- Application interface
- g_use_bg => g_use_bg,
--- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
--- g_bg_data_file_prefix => g_bg_data_file_name,
- g_use_back => g_use_back,
-
- -- Terminals interface
- g_mesh_nof_serial => g_mesh_nof_serial,
- g_mesh_use_rx => g_mesh_use_rx,
- g_mesh_gx_mbps => g_mesh_gx_mbps,
- g_mesh_mon_select => g_mesh_mon_select,
- g_mesh_mon_nof_words => g_mesh_mon_nof_words,
- g_mesh_mon_use_sync => g_mesh_mon_use_sync,
- g_mesh_ena_reorder => g_mesh_ena_reorder,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map (
- -- System
- chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
- bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- tr_back_clk => tr_clk,
- cal_clk => cal_clk,
-
- -- Streaming data input
- in_sosi_arr => in_sosi_arr,
- in_siso_arr => in_siso_arr,
-
- -- MM registers
- -- . block generator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- -- . tr_nonbonded
- reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
- reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
- reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
- reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
-
- reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
- reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
- reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
- reg_back_diagnostics_miso => reg_back_diagnostics_miso,
-
- -- . rx terminals monitor buffers
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr,
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => back_tx_serial_2arr,
- back_rx_serial_2arr => back_rx_serial_2arr
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ -- Application interface
+ g_use_bg => g_use_bg,
+ -- g_bg_data_file_index_arr => g_bg_data_file_index_arr,
+ -- g_bg_data_file_prefix => g_bg_data_file_name,
+ g_use_back => g_use_back,
+
+ -- Terminals interface
+ g_mesh_nof_serial => g_mesh_nof_serial,
+ g_mesh_use_rx => g_mesh_use_rx,
+ g_mesh_gx_mbps => g_mesh_gx_mbps,
+ g_mesh_mon_select => g_mesh_mon_select,
+ g_mesh_mon_nof_words => g_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => g_mesh_mon_use_sync,
+ g_mesh_ena_reorder => g_mesh_ena_reorder,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- System
+ chip_id => TO_UVEC(g_chip_id, c_unb1_board_nof_chip_w), -- BN chip ID 4, 5, 6, 7
+ bck_id => TO_UVEC(g_bck_id, c_unb1_board_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ tr_back_clk => tr_clk,
+ cal_clk => cal_clk,
+
+ -- Streaming data input
+ in_sosi_arr => in_sosi_arr,
+ in_siso_arr => in_siso_arr,
+
+ -- MM registers
+ -- . block generator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ -- . tr_nonbonded
+ reg_mesh_tr_nonbonded_mosi => reg_mesh_tr_nonbonded_mosi,
+ reg_mesh_tr_nonbonded_miso => reg_mesh_tr_nonbonded_miso,
+ reg_mesh_diagnostics_mosi => reg_mesh_diagnostics_mosi,
+ reg_mesh_diagnostics_miso => reg_mesh_diagnostics_miso,
+
+ reg_back_tr_nonbonded_mosi => reg_back_tr_nonbonded_mosi,
+ reg_back_tr_nonbonded_miso => reg_back_tr_nonbonded_miso,
+ reg_back_diagnostics_mosi => reg_back_diagnostics_mosi,
+ reg_back_diagnostics_miso => reg_back_diagnostics_miso,
+
+ -- . rx terminals monitor buffers
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr,
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => back_tx_serial_2arr,
+ back_rx_serial_2arr => back_rx_serial_2arr
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index b521c00a23e2e0e0dbfa5383d9f9316d6aa5322c..0b6b3c5956516a4b840d3a7ac29af533aa55eae7 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -32,12 +32,12 @@
-- Observe in Wave window that rx_usr_sosi_2arr is delayed tx_usr_sosi_2arr
library IEEE, common_lib, dp_lib, bf_lib, unb_common_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
entity tb_tb_node_bn_terminal_bg is
generic (
@@ -63,33 +63,33 @@ architecture tb of tb_tb_node_bn_terminal_bg is
signal mesh_rx_serial_2arr : t_unb_mesh_sl_2arr;
begin
u_tb_node_bn_terminal_bg : entity work.tb_node_bn_terminal_bg
- generic map (
- -- Tb
- g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
- g_nof_sync => g_nof_sync,
- g_chip_id => 4,
- -- Application
- g_bf => c_bf,
- g_bg_data_file_index_arr => array_init(0, 16, 1),
- g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
- -- Diagnostics - TRNB
- g_diagnostics_en => g_diagnostics_en,
- -- Terminals interface
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_rx,
- g_mesh_ena_reorder => c_mesh_ena_reorder
- )
- port map (
- tb_clk => tb_clk,
- tb_end => tb_end,
-
- -- Timing
- dp_pps => dp_pps,
-
- -- Serial (tr_nonbonded)
- mesh_tx_serial_2arr => mesh_tx_serial_2arr,
- mesh_rx_serial_2arr => mesh_rx_serial_2arr
- );
+ generic map (
+ -- Tb
+ g_sim_level => 1, -- 0 = simulate GX IP, 1 = use fast serial behavioural model
+ g_nof_sync => g_nof_sync,
+ g_chip_id => 4,
+ -- Application
+ g_bf => c_bf,
+ g_bg_data_file_index_arr => array_init(0, 16, 1),
+ g_bg_data_file_name => "../../../../../../modules/Lofar/diag/src/data/bf_in_data",
+ -- Diagnostics - TRNB
+ g_diagnostics_en => g_diagnostics_en,
+ -- Terminals interface
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_rx,
+ g_mesh_ena_reorder => c_mesh_ena_reorder
+ )
+ port map (
+ tb_clk => tb_clk,
+ tb_end => tb_end,
+
+ -- Timing
+ dp_pps => dp_pps,
+
+ -- Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => mesh_tx_serial_2arr,
+ mesh_rx_serial_2arr => mesh_rx_serial_2arr
+ );
------------------------------------------------------------------------------
-- External PPS
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index 45beb6d4fd0ed4fb8bb98b369acc4cd213d51c4c..7a3817a8169e36d6ad19632c6bf48eb90d3cc007 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -20,19 +20,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, eth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3 is
generic (
@@ -141,7 +141,7 @@ architecture str of mmm_unb1_ddr3 is
constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"002286080001";
signal eth_psc_access : std_logic;
- constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_dut_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal i_eth1g_reg_mosi : t_mem_mosi;
signal i_eth1g_reg_miso : t_mem_miso;
@@ -167,41 +167,53 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
- u_mm_file_reg_diag_bg_ctrl : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_CTRL")
- port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
+ u_mm_file_reg_diag_bg_ctrl : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_CTRL")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_ctrl_mosi, reg_diag_bg_ctrl_miso );
- u_mm_file_ram_diag_bg_data : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DATA")
- port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
+ u_mm_file_ram_diag_bg_data : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_DATA")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_data_mosi, ram_diag_bg_data_miso );
- u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ u_mm_file_reg_diag_tx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
- u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ u_mm_file_reg_diag_rx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -243,152 +255,152 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3
- port map (
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg_data
- coe_clk_export_from_the_ram_diag_bg_data => OPEN,
- coe_reset_export_from_the_ram_diag_bg_data => OPEN,
- coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf
- coe_clk_export_from_the_ram_diag_data_buf => OPEN,
- coe_reset_export_from_the_ram_diag_data_buf => OPEN,
- coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg_ctrl
- coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
- coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf
- coe_clk_export_from_the_reg_diag_data_buf => OPEN,
- coe_reset_export_from_the_reg_diag_data_buf => OPEN,
- coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => i_cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => pout_debug_wave,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg_data
+ coe_clk_export_from_the_ram_diag_bg_data => OPEN,
+ coe_reset_export_from_the_ram_diag_bg_data => OPEN,
+ coe_address_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.address(c_mm_ram_diag_bg_data_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg_data => ram_diag_bg_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg_data => ram_diag_bg_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf
+ coe_clk_export_from_the_ram_diag_data_buf => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buf => OPEN,
+ coe_address_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.address(c_mm_ram_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buf => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buf => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg_ctrl
+ coe_clk_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_reset_export_from_the_reg_diag_bg_ctrl => OPEN,
+ coe_address_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.address(c_mm_reg_diag_bg_ctrl_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg_ctrl => reg_diag_bg_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf
+ coe_clk_export_from_the_reg_diag_data_buf => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buf => OPEN,
+ coe_address_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.address(c_mm_reg_diag_data_buf_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buf => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buf => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_mm_reg_diag_rx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_mm_reg_diag_tx_seq_addr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index 4467803f06ffb303fe56e6f532d212f62415c01b..e3175650c1e650011e73336f904552022203dbf9 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diagnostics_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity node_unb1_ddr3 is
generic (
@@ -111,77 +111,77 @@ architecture str of node_unb1_ddr3 is
signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
begin
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => g_st_dat_w,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => g_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk,
- ctlr_rst_out => ddr_out_rst,
-
- ctlr_clk_in => dp_clk,
- ctlr_rst_in => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on termination control from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_in,
- phy3_io => MB_I_io,
- phy3_ou => MB_I_ou,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso
- );
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => g_st_dat_w,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => g_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk,
+ ctlr_rst_out => ddr_out_rst,
+
+ ctlr_clk_in => dp_clk,
+ ctlr_rst_in => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on termination control from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_in,
+ phy3_io => MB_I_io,
+ phy3_ou => MB_I_ou,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 80af69d3f773ad7d65ac0ba8e4e2be97b3efcab4..6518fb09df826f557ec64458010fc89f82fe9182 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, io_ddr_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3 is
generic (
@@ -76,17 +76,17 @@ architecture str of unb1_ddr3 is
constant c_design_name : string := "unb1_ddr3";
constant c_design_note : string := "DDR3 reference design";
constant c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
+ -- Use PHY Interface
+ -- TYPE t_c_unb_use_phy IS RECORD
+ -- eth1g : NATURAL;
+ -- tr_front: NATURAL;
+ -- tr_mesh : NATURAL;
+ -- tr_back : NATURAL;
+ -- ddr3_I : NATURAL;
+ -- ddr3_II : NATURAL;
+ -- adc : NATURAL;
+ -- wdi : NATURAL;
+ -- END RECORD;
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
constant c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
constant c_app_led_en : boolean := true;
@@ -142,9 +142,9 @@ architecture str of unb1_ddr3 is
signal eth1g_reg_interrupt : std_logic; -- Interrupt
signal eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
signal eth1g_ram_miso : t_mem_miso;
--- SIGNAL eth1g_led : t_tech_tse_led;
+ -- SIGNAL eth1g_led : t_tech_tse_led;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -174,243 +174,243 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => c_design_name,
- g_design_note => c_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN,
- dp_clk => OPEN,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- --
- -- >>> Ctrl FPGA pins
- --
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => c_design_name,
+ g_design_note => c_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN,
+ dp_clk => OPEN,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- DDR3
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- DDR3
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3
- generic map (
- g_sim => g_sim,
- g_technology => c_technology,
- g_tech_ddr => c_tech_ddr,
- g_st_dat_w => g_st_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK,
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Block Generator Control
- reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
- reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
-
- -- Block Generator Data
- ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
- ram_diag_bg_data_miso => ram_diag_bg_data_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => c_technology,
+ g_tech_ddr => c_tech_ddr,
+ g_st_dat_w => g_st_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK,
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Block Generator Control
+ reg_diag_bg_ctrl_mosi => reg_diag_bg_ctrl_mosi,
+ reg_diag_bg_ctrl_miso => reg_diag_bg_ctrl_miso,
+
+ -- Block Generator Data
+ ram_diag_bg_data_mosi => ram_diag_bg_data_mosi,
+ ram_diag_bg_data_miso => ram_diag_bg_data_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 55751e463fe336cd8e7c907f3eb39d0f8ab65e8f..53af01aa6c8c3436e03131060ac29f00fe39a2bf 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -31,20 +31,20 @@
-- > python tc_unb1_ddr3_seq.py --sim --unb 0 --fn 3 --rep 3
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, tech_ddr_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
entity tb_unb1_ddr3 is
generic (
@@ -71,7 +71,7 @@ architecture tb of tb_unb1_ddr3 is
constant c_ext_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
- -- SO-DIMM Memory Bank I = ddr3_I
+ -- SO-DIMM Memory Bank I = ddr3_I
signal MB_I_in : t_tech_ddr3_phy_in;
signal MB_I_io : t_tech_ddr3_phy_io;
signal MB_I_ou : t_tech_ddr3_phy_ou;
@@ -96,7 +96,7 @@ architecture tb of tb_unb1_ddr3 is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
begin
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
clk <= not clk after c_ext_clk_period / 2; -- External clock (200 MHz)
@@ -123,51 +123,51 @@ begin
------------------------------------------------------------------------------
dut : entity work.unb1_ddr3
- generic map (
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_st_dat_w => c_st_dat_w
-
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_IN => MB_I_in,
- MB_I_IO => MB_I_io,
- MB_I_OU => MB_I_ou
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
+ g_st_dat_w => c_st_dat_w
+
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_IN => MB_I_in,
+ MB_I_IO => MB_I_io,
+ MB_I_OU => MB_I_ou
+ );
------------------------------------------------------------------------------
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr
- )
- port map (
- mem3_in => MB_I_ou,
- mem3_io => MB_I_io,
- mem3_ou => MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_ddr
+ )
+ port map (
+ mem3_in => MB_I_ou,
+ mem3_io => MB_I_io,
+ mem3_ou => MB_I_in
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
index f2880d95fff355bf58535b3d9a1d9652632edff7..d57b0475cf8fcc6d558896c571574049a3d74e77 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_dual_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_dual_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_dual_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master
+ );
end tb_unb1_ddr3_reorder_dual_rank;
architecture tb of tb_unb1_ddr3_reorder_dual_rank is
@@ -45,5 +45,5 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 5622c88c07a81536c2dbca7c7e0000626c3627c6..d1197505855407245696c78ba1576a958ff30057 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_dual_rank is
generic (
@@ -73,35 +73,35 @@ end unb1_ddr3_reorder_dual_rank;
architecture str of unb1_ddr3_reorder_dual_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
index 01306cde2b28d4f27ece81f4888cd13afadf67e7..f72f1cf4358d4c2663eaebf365d60b0869c0210d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
@@ -20,20 +20,20 @@
--
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb1_ddr3_reorder_single_rank is
- generic (
- g_design_name : string := "unb1_ddr3_reorder_single_rank";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder_single_rank";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder_single_rank;
architecture tb of tb_unb1_ddr3_reorder_single_rank is
@@ -45,5 +45,5 @@ begin
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
- );
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index 5bd73002e062806ac18d0eb832e82573ea720246..79dae4235c6dfb050cf82d4e4fb52007e4ded230 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_ddr3_reorder_single_rank is
generic (
@@ -73,35 +73,35 @@ end unb1_ddr3_reorder_single_rank;
architecture str of unb1_ddr3_reorder_single_rank is
begin
u_revision : entity work.unb1_ddr3_reorder
- generic map(
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_aux => g_aux
- )
- port map(
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ generic map(
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_aux => g_aux
+ )
+ port map(
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index 34532416bb3622692dba4d69c0881e639d640e6c..114c838af08d820e5adcd48c50c736194d6db449 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, dp_lib, reorder_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use reorder_lib.reorder_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use reorder_lib.reorder_pkg.all;
+ use technology_lib.technology_select_pkg.all;
--USE tech_ddr_lib.tech_ddr_pkg.ALL;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity mmm_unb1_ddr3_reorder is
generic (
@@ -46,7 +46,7 @@ entity mmm_unb1_ddr3_reorder is
g_sim_node_nr : natural := 0;
g_nof_streams : natural := 4;
g_reorder_seq : t_reorder_seq := c_reorder_seq
- );
+ );
port (
-- GENERAL
xo_clk : in std_logic;
@@ -148,7 +148,7 @@ architecture str of mmm_unb1_ddr3_reorder is
signal i_tse_clk : std_logic := '1';
signal i_cal_clk : std_logic := '1';
- constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_dut_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal i_eth1g_reg_mosi : t_mem_mosi;
signal i_eth1g_reg_miso : t_mem_miso;
@@ -174,47 +174,61 @@ begin
i_cal_clk <= not i_cal_clk after c_cal_clk_period / 2;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_reg_diag_tx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
+ u_mm_file_reg_diag_tx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_tx_seq_mosi, reg_diag_tx_seq_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
- u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
- port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
+ u_mm_file_reg_diag_rx_seq : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
+ port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
- u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso);
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -238,10 +252,10 @@ begin
p_switch : process(mm_bus_switch, eth1g_reg_proc_mosi, i_eth1g_reg_mosi)
begin
if mm_bus_switch = '1' then
- eth1g_reg_mosi <= eth1g_reg_proc_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= eth1g_reg_proc_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -256,170 +270,169 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_ddr3_reorder
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => i_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
- coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
- coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
- coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
- coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
- coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
- coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
- coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf: register space for the databuffer
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf: ram space for the databuffer
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => i_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_rx_seq: entry for the register space of the rx sequencer
+ coe_clk_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_rx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.address(c_reg_diag_rx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_rx_seq => reg_diag_rx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_rx_seq => reg_diag_rx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_tx_seq: entry for the register space of the tx sequencer
+ coe_clk_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_reset_export_from_the_reg_diag_tx_seq => OPEN,
+ coe_address_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.address(c_reg_diag_tx_seq_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_tx_seq => reg_diag_tx_seq_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_tx_seq => reg_diag_tx_seq_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf: register space for the databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf: ram space for the databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_ram_diag_data_buf_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(3 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index 2af884041ac29abf351f5c7214a288db05772a54..95f652be5a27689a31091b241cbf69b1b8b464b4 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity node_unb1_ddr3_reorder is
generic (
@@ -43,7 +43,7 @@ entity node_unb1_ddr3_reorder is
g_frame_size_out : natural := 176;
g_reorder_seq : t_reorder_seq := c_reorder_seq
);
-port (
+ port (
-- System
mm_rst : in std_logic;
mm_clk : in std_logic;
@@ -139,27 +139,27 @@ architecture str of node_unb1_ddr3_reorder is
signal bsn_sosi_arr : t_dp_sosi_arr(3 downto 0) := (others => c_dp_sosi_rst);
begin
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= to_mem_sosi;
@@ -170,113 +170,113 @@ begin
-- TRANSPOSE UNIT
------------------------------------------------------------------------------
u_transpose: entity reorder_lib.reorder_transpose
- generic map(
- g_nof_streams => g_nof_streams,
- g_in_dat_w => g_in_dat_w,
- g_frame_size_in => g_frame_size_in,
- g_frame_size_out => g_frame_size_out,
- g_use_complex => c_use_complex,
- g_ena_pre_transp => g_ena_pre_transp,
- g_reorder_seq => g_reorder_seq
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
-
- -- ST sink
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
-
- -- ST source
- src_in_arr => db_siso_arr,
- src_out_arr => db_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Control interface to the external memory
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Data interface to the external memory
- to_mem_src_out => to_mem_sosi,
- to_mem_src_in => to_mem_siso,
-
- from_mem_snk_in => from_mem_sosi,
- from_mem_snk_out => from_mem_siso
-
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_in_dat_w => g_in_dat_w,
+ g_frame_size_in => g_frame_size_in,
+ g_frame_size_out => g_frame_size_out,
+ g_use_complex => c_use_complex,
+ g_ena_pre_transp => g_ena_pre_transp,
+ g_reorder_seq => g_reorder_seq
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+
+ -- ST sink
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+
+ -- ST source
+ src_in_arr => db_siso_arr,
+ src_out_arr => db_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Control interface to the external memory
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Data interface to the external memory
+ to_mem_src_out => to_mem_sosi,
+ to_mem_src_in => to_mem_siso,
+
+ from_mem_snk_in => from_mem_sosi,
+ from_mem_snk_out => from_mem_siso
+
+ );
------------------------------------------------------------------------------
-- DDR3 MODULE 0, MB_I
------------------------------------------------------------------------------
u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
- generic map(
- g_technology => g_tech_select_default,
- g_tech_ddr => g_tech_ddr,
- g_cross_domain_dvr_ctlr => false,
- g_wr_data_w => c_data_w,
- g_wr_fifo_depth => c_fifo_depth,
- g_rd_fifo_depth => c_fifo_depth,
- g_rd_data_w => c_data_w,
- g_wr_flush_mode => "SYN",
- g_wr_flush_use_channel => false,
- g_wr_flush_start_channel => 0,
- g_wr_flush_nof_channels => 1
- )
- port map (
- -- DDR reference clock
- ctlr_ref_clk => ddr_ref_clk,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
- ctlr_rst_out => ddr_out_rst_i,
-
- ctlr_clk_in => ddr_out_clk_i,
- ctlr_rst_in => ddr_out_rst_i,
-
- -- MM clock + reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- MM register map for DDR controller status info
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Driver clock domain
- dvr_clk => ddr_out_clk_i,
- dvr_rst => ddr_out_rst_i,
-
- dvr_miso => ctlr_dvr_miso,
- dvr_mosi => ctlr_dvr_mosi,
-
- -- Write FIFO clock domain
- wr_clk => ddr_out_clk_i,
- wr_rst => ddr_out_rst_i,
-
- wr_fifo_usedw => OPEN,
- wr_sosi => to_mem_sosi,
- wr_siso => to_mem_siso,
-
- -- Read FIFO clock domain
- rd_clk => ddr_out_clk_i,
- rd_rst => ddr_out_rst_i,
-
- rd_fifo_usedw => OPEN,
- rd_sosi => from_mem_sosi,
- rd_siso => from_mem_siso,
-
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU
- );
+ generic map(
+ g_technology => g_tech_select_default,
+ g_tech_ddr => g_tech_ddr,
+ g_cross_domain_dvr_ctlr => false,
+ g_wr_data_w => c_data_w,
+ g_wr_fifo_depth => c_fifo_depth,
+ g_rd_fifo_depth => c_fifo_depth,
+ g_rd_data_w => c_data_w,
+ g_wr_flush_mode => "SYN",
+ g_wr_flush_use_channel => false,
+ g_wr_flush_start_channel => 0,
+ g_wr_flush_nof_channels => 1
+ )
+ port map (
+ -- DDR reference clock
+ ctlr_ref_clk => ddr_ref_clk,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_out_clk_i, -- output clock of the ddr controller is used as DP clk.
+ ctlr_rst_out => ddr_out_rst_i,
+
+ ctlr_clk_in => ddr_out_clk_i,
+ ctlr_rst_in => ddr_out_rst_i,
+
+ -- MM clock + reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM register map for DDR controller status info
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Driver clock domain
+ dvr_clk => ddr_out_clk_i,
+ dvr_rst => ddr_out_rst_i,
+
+ dvr_miso => ctlr_dvr_miso,
+ dvr_mosi => ctlr_dvr_mosi,
+
+ -- Write FIFO clock domain
+ wr_clk => ddr_out_clk_i,
+ wr_rst => ddr_out_rst_i,
+
+ wr_fifo_usedw => OPEN,
+ wr_sosi => to_mem_sosi,
+ wr_siso => to_mem_siso,
+
+ -- Read FIFO clock domain
+ rd_clk => ddr_out_clk_i,
+ rd_rst => ddr_out_rst_i,
+
+ rd_fifo_usedw => OPEN,
+ rd_sosi => from_mem_sosi,
+ rd_siso => from_mem_siso,
+
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU
+ );
ddr_out_clk <= ddr_out_clk_i;
ddr_out_rst <= ddr_out_rst_i;
@@ -285,68 +285,68 @@ begin
-- DIAG Block Generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- -- Generate configurations
- g_use_usr_input => false,
- g_use_bg => true,
- g_use_tx_seq => true,
- -- General
- g_nof_streams => g_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => false,
- -- Tx_seq
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_usr_input => false,
+ g_use_bg => true,
+ g_use_tx_seq => true,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => false,
+ -- Tx_seq
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
-----------------------------------------------------------------------------
-- DIAG Rx seq with optional Data Buffer
-----------------------------------------------------------------------------
u_mms_diag_data_buffer: entity diag_lib.mms_diag_data_buffer
- generic map (
- -- Generate configurations
- g_use_db => c_use_db,
- g_use_rx_seq => c_use_rx_seq,
- -- General
- g_nof_streams => g_nof_streams,
- -- DB settings
- g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
- g_data_w => c_data_w,
- g_buf_nof_data => c_buf_nof_data,
- g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
- -- Rx_seq
- g_use_steps => c_use_steps,
- g_seq_dat_w => c_data_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => ddr_out_rst_i,
- dp_clk => ddr_out_clk_i,
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- ST interface
- in_sosi_arr => db_sosi_arr
- );
+ generic map (
+ -- Generate configurations
+ g_use_db => c_use_db,
+ g_use_rx_seq => c_use_rx_seq,
+ -- General
+ g_nof_streams => g_nof_streams,
+ -- DB settings
+ g_data_type => e_data, -- define the sosi field that gets stored: e_data=data, e_complex=im&re, e_real=re, e_imag=im,
+ g_data_w => c_data_w,
+ g_buf_nof_data => c_buf_nof_data,
+ g_buf_use_sync => c_buf_use_sync, -- when TRUE start filling the buffer at the in_sync, else after the last word was read,
+ -- Rx_seq
+ g_use_steps => c_use_steps,
+ g_seq_dat_w => c_data_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => ddr_out_rst_i,
+ dp_clk => ddr_out_clk_i,
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- ST interface
+ in_sosi_arr => db_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index a0f4448402a1c0f8d47f6c28dde9d61eeb5aca0d..9dac90343e097414a8ddae9de7192f5c9f3c439e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity unb1_ddr3_reorder is
generic (
@@ -95,12 +95,13 @@ architecture str of unb1_ddr3_reorder is
constant c_nof_blocks : natural := sel_a_b(g_sim, 16, 800000);
constant c_nof_streams : natural := 1;
constant c_in_dat_w : natural := 64;
- constant c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_rd_interval,
- c_gapsize,
- c_nof_blocks);
+ constant c_reorder_seq_conf : t_reorder_seq := (
+ c_wr_chunksize,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_rd_interval,
+ c_gapsize,
+ c_nof_blocks);
-- System
signal cs_sim : std_logic;
@@ -173,7 +174,7 @@ architecture str of unb1_ddr3_reorder is
signal reg_io_ddr_mosi : t_mem_mosi;
signal reg_io_ddr_miso : t_mem_miso;
- -- . UniBoard I2C sens
+ -- . UniBoard I2C sens
signal reg_unb_sens_mosi : t_mem_mosi;
signal reg_unb_sens_miso : t_mem_miso;
@@ -192,262 +193,262 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- -- General
- g_sim => g_sim,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_use_pll => false,
- g_app_led_red => c_app_led_en,
- g_app_led_green => c_app_led_en,
- g_use_phy => c_use_phy,
- g_aux => c_aux
- )
- port map (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
- this_bck_id => OPEN,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ -- General
+ g_sim => g_sim,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_use_pll => false,
+ g_app_led_red => c_app_led_en,
+ g_app_led_green => c_app_led_en,
+ g_use_phy => c_use_phy,
+ g_aux => c_aux
+ )
+ port map (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk, -- dp_clk is now generated in the DDR controller
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+ this_bck_id => OPEN,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- PIOs
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
u_mmm : entity work.mmm_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map (
- -- GENERAL
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Databuffers
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map (
+ -- GENERAL
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => '0',
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => '0',
+ out_rst => ddr_ref_rst
+ );
u_node : entity work.node_unb1_ddr3_reorder
- generic map(
- g_sim => g_sim,
- g_use_MB_I => g_use_MB_I,
- g_tech_ddr => g_tech_ddr,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_in_dat_w,
- g_ena_pre_transp => c_ena_pre_transp,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_reorder_seq => c_reorder_seq_conf
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
- ddr_ref_rst => ddr_ref_rst,
-
- -- Clock outputs
- ddr_out_clk => dp_clk,
- ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
-
- -- IO DDR register map
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- -- Reorder transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Data Buffer Control
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- Data Buffer Data
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-
- -- Blockgenerator Control
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- -- Blockgenerator Data
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- TX Sequencer
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
-
- -- RX Sequencer
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
-
- -- SO-DIMM Memory Bank I = ddr3_I
- MB_I_in => MB_I_IN,
- MB_I_io => MB_I_IO,
- MB_I_ou => MB_I_OU
- );
+ generic map(
+ g_sim => g_sim,
+ g_use_MB_I => g_use_MB_I,
+ g_tech_ddr => g_tech_ddr,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_in_dat_w,
+ g_ena_pre_transp => c_ena_pre_transp,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_reorder_seq => c_reorder_seq_conf
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
+ ddr_ref_rst => ddr_ref_rst,
+
+ -- Clock outputs
+ ddr_out_clk => dp_clk,
+ ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
+
+ -- IO DDR register map
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ -- Reorder transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Data Buffer Control
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- Data Buffer Data
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+
+ -- Blockgenerator Control
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ -- Blockgenerator Data
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- TX Sequencer
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_miso,
+
+ -- RX Sequencer
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ -- SO-DIMM Memory Bank I = ddr3_I
+ MB_I_in => MB_I_IN,
+ MB_I_io => MB_I_IO,
+ MB_I_ou => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
index 013700e86659870ff590f0e9f647e4980b63fb64..56ec351ac96b4f07d5b3b3d29bae1ff967e3dcee 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
@@ -27,29 +27,29 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, dp_lib, io_ddr_lib, eth_lib, technology_lib, tech_ddr_lib, diag_lib, reorder_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use reorder_lib.reorder_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use reorder_lib.reorder_pkg.all;
entity tb_unb1_ddr3_reorder is
- generic (
- g_design_name : string := "unb1_ddr3_reorder";
- g_design_note : string := "Reference Reorder";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7; -- Back node 3
- g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
- );
+ generic (
+ g_design_name : string := "unb1_ddr3_reorder";
+ g_design_note : string := "Reference Reorder";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7; -- Back node 3
+ g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_single_rank_800m_master
+ );
end tb_unb1_ddr3_reorder;
architecture tb of tb_unb1_ddr3_reorder is
@@ -123,7 +123,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= transport eth_txp after c_cable_delay;
@@ -171,50 +171,50 @@ begin
-- DDR3 memory model
------------------------------------------------------------------------------
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => g_tech_ddr
- )
- port map (
- mem3_in => phy_ou,
- mem3_io => phy_io,
- mem3_ou => phy_in
- );
+ generic map (
+ g_tech_ddr => g_tech_ddr
+ )
+ port map (
+ mem3_in => phy_ou,
+ mem3_io => phy_io,
+ mem3_ou => phy_in
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 6687a715a0fd68ff9c0a2484c21174f5fc74d032..e66462326b8cdd7861833c786185bff528485a7f 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use common_lib.common_field_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity mmm_unb_ddr3_transpose is
generic (
@@ -135,51 +135,66 @@ begin
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_ram_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+ u_mm_file_ram_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_RE")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
- u_mm_file_reg_diag_data_buf_re : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+ u_mm_file_reg_diag_data_buf_re : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_RE")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
- u_mm_file_ram_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+ u_mm_file_ram_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_IM")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
- u_mm_file_reg_diag_data_buf_im : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+ u_mm_file_reg_diag_data_buf_im : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_IM")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
- u_mm_file_ram_ss_ss_transp : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_ram_ss_ss_transp : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ port map(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
- u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
- port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+ u_mm_file_reg_io_ddr : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ port map(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -193,169 +208,169 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb_ddr3_transpose
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg: entry for the register space of the block generator
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg: entry for the ram space of the block generator
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buf_re: register space for the real databuffer
- coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buf_re: ram space for the real databuffer
- coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
- coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_ss_ss_transp: ram space for the subband select unit
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_io_ddr
- coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
- coe_clk_export_from_the_reg_io_ddr => OPEN,
- coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
- coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_io_ddr => OPEN,
- coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
- coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb_common.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg: entry for the register space of the block generator
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg: entry for the ram space of the block generator
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_im: register space for the imaginary databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.address(c_reg_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_im => reg_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_im: ram space for the imaginary databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_im => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.address(c_ram_diag_data_buf_im_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_im => ram_diag_data_buf_im_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buf_re: register space for the real databuffer
+ coe_clk_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_reg_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.address(c_reg_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer_re => reg_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buf_re: ram space for the real databuffer
+ coe_clk_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_reset_export_from_the_ram_diag_data_buffer_re => OPEN,
+ coe_address_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.address(c_ram_diag_data_buf_re_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_re => ram_diag_data_buf_re_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_ss_ss_transp: ram space for the subband select unit
+ coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
+ coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_adr_w - 1 downto 0),
+ coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.rd,
+ coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_transp_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wr,
+ coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_transp_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_io_ddr
+ coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(1 downto 0),
+ coe_clk_export_from_the_reg_io_ddr => OPEN,
+ coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
+ coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_io_ddr => OPEN,
+ coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
+ coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(1 + c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 1f1463d40ddf153677f593cf22140353f94e8eb3..6501e3bee6ae5889bc47e5ff54d50d7fa4377ff4 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, eth_lib, diag_lib, dp_lib, ddr3_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use eth_lib.eth_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity unb1_ddr3_transpose is
generic (
@@ -88,12 +88,13 @@ architecture str of unb1_ddr3_transpose is
constant c_gapsize : natural := sel_a_b(g_sim, 0, 0); -- 0);
constant c_nof_blocks : positive := sel_a_b(g_sim, 4, 4); -- 16);
- constant c_ddr3_seq_conf : t_ddr3_seq := (c_wr_chunksize,
- c_wr_nof_chunks,
- c_rd_chunksize,
- c_rd_nof_chunks,
- c_gapsize,
- c_nof_blocks);
+ constant c_ddr3_seq_conf : t_ddr3_seq := (
+ c_wr_chunksize,
+ c_wr_nof_chunks,
+ c_rd_chunksize,
+ c_rd_nof_chunks,
+ c_gapsize,
+ c_nof_blocks);
constant c_blocksize : positive := c_wr_nof_chunks * c_wr_chunksize;
@@ -215,333 +216,333 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_dp_clk_use_pll => false,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => OPEN, -- dp_rst,
- dp_clk => OPEN, -- dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- -- . system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_dp_clk_use_pll => false,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => OPEN, -- dp_rst,
+ dp_clk => OPEN, -- dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ -- . system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb_ddr3_transpose
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_frame_size_in => c_frame_size_in,
- g_nof_streams => c_nof_streams,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- Blockgenerator
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
-
- -- DDR3 transpose
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- -- Databuffers
- ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
- ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
- reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
- reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
- ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
- ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
- reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
- reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
-
- -- BSN monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso
-
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_frame_size_in => c_frame_size_in,
+ g_nof_streams => c_nof_streams,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Blockgenerator
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+
+ -- DDR3 transpose
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ -- Databuffers
+ ram_diag_data_buf_im_mosi => ram_diag_data_buf_im_mosi,
+ ram_diag_data_buf_im_miso => ram_diag_data_buf_im_miso,
+ reg_diag_data_buf_im_mosi => reg_diag_data_buf_im_mosi,
+ reg_diag_data_buf_im_miso => reg_diag_data_buf_im_miso,
+ ram_diag_data_buf_re_mosi => ram_diag_data_buf_re_mosi,
+ ram_diag_data_buf_re_miso => ram_diag_data_buf_re_miso,
+ reg_diag_data_buf_re_mosi => reg_diag_data_buf_re_mosi,
+ reg_diag_data_buf_re_miso => reg_diag_data_buf_re_miso,
+
+ -- BSN monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
+
+ );
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 2, -- Check one input and one output stream
- g_cross_clock_domain => true,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => bsn_sosi_arr
- );
+ generic map (
+ g_nof_streams => 2, -- Check one input and one output stream
+ g_cross_clock_domain => true,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => bsn_sosi_arr
+ );
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= out_sosi_arr(0);
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
u_ddr3_T: entity ddr3_lib.ddr3_transpose
- generic map(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams,
- g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
- g_frame_size_in => c_frame_size_in,
- g_frame_size_out => c_frame_size_out,
- g_nof_blk_per_sync => c_nof_blk_per_sync,
- g_use_complex => true,
- g_ena_pre_transp => c_ena_pre_transpose,
- g_phy => c_phy,
- g_mts => c_mts,
- g_ddr3_seq => c_ddr3_seq_conf
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_ref_clk => CLK,
- dp_ref_rst => ddr_ref_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- dp_out_clk => dp_clk,
- dp_out_rst => dp_rst,
-
- reg_io_ddr_mosi => reg_io_ddr_mosi,
- reg_io_ddr_miso => reg_io_ddr_miso,
-
- snk_out_arr => bg_siso_arr,
- snk_in_arr => bg_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
-
- ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-
- ser_term_ctrl_out => OPEN,
- par_term_ctrl_out => OPEN,
-
- ser_term_ctrl_in => OPEN,
- par_term_ctrl_in => OPEN,
-
- phy_in => MB_I_in,
- phy_io => MB_I_io,
- phy_ou => MB_I_ou
- );
+ generic map(
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams,
+ g_in_dat_w => c_bg_buf_dat_w / c_nof_complex,
+ g_frame_size_in => c_frame_size_in,
+ g_frame_size_out => c_frame_size_out,
+ g_nof_blk_per_sync => c_nof_blk_per_sync,
+ g_use_complex => true,
+ g_ena_pre_transp => c_ena_pre_transpose,
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_ref_clk => CLK,
+ dp_ref_rst => ddr_ref_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ dp_out_clk => dp_clk,
+ dp_out_rst => dp_rst,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ ser_term_ctrl_out => OPEN,
+ par_term_ctrl_out => OPEN,
+
+ ser_term_ctrl_in => OPEN,
+ par_term_ctrl_in => OPEN,
+
+ phy_in => MB_I_in,
+ phy_io => MB_I_io,
+ phy_ou => MB_I_ou
+ );
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
- ram_data_buf_miso => ram_diag_data_buf_re_miso,
- reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
- reg_data_buf_miso => reg_diag_data_buf_re_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_type => c_db_data_type_im,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
- ram_data_buf_miso => ram_diag_data_buf_im_miso,
- reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
- reg_data_buf_miso => reg_diag_data_buf_im_miso,
- -- ST interface
- in_sync => OPEN,
- in_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index 3d8ecf213a834d8c9206e1a9f6204949b944cf1e..f6340f2f6f07997c2406a8aef4c8181d530e2e9e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -25,13 +25,13 @@
-- that are used on hardware.
library IEEE, tech_ddr_lib, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use ddr3_lib.ddr3_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use ddr3_lib.ddr3_pkg.all;
entity tb_unb1_ddr3_transpose is
end tb_unb1_ddr3_transpose;
@@ -73,7 +73,7 @@ architecture tb of tb_unb1_ddr3_transpose is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
- -- Signals to interface with the DDR3 memory model.
+ -- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
signal phy_ou : t_tech_ddr3_phy_ou;
@@ -153,47 +153,47 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
-- DDR3 Model
u_tech_ddr_memory_model : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_tech_ddr
- )
- port map (
- -- DDR3 PHY interface
- mem3_in => phy_ou,
- mem3_io => phy_io
- );
+ generic map (
+ g_tech_ddr => c_tech_ddr
+ )
+ port map (
+ -- DDR3 PHY interface
+ mem3_in => phy_ou,
+ mem3_io => phy_io
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index 02d12daee571723b79912c82f1427aafe8dfcaa0..abf8e95ac5aaba7aecaeb8690997383fa50b3d90 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -20,21 +20,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_fn_terminal_db is
generic (
@@ -105,7 +105,7 @@ entity mmm_unb1_fn_terminal_db is
end mmm_unb1_fn_terminal_db;
architecture str of mmm_unb1_fn_terminal_db is
- -- Simulation
+ -- Simulation
constant c_mm_clk_period : time := 100 ps;
constant c_tse_clk_period : time := 8 ns;
@@ -128,7 +128,7 @@ architecture str of mmm_unb1_fn_terminal_db is
signal eth1g_reg_proc_miso : t_mem_miso;
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -148,38 +148,49 @@ begin
i_tse_clk <= not i_tse_clk after c_tse_clk_period / 2;
eth1g_mm_rst <= '1', '0' after c_tse_clk_period * 5;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ u_mm_file_reg_tr_nonbonded : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+ port map(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
- u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ u_mm_file_reg_diagnostics : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ port map(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
- u_mm_file_ram_diag_data_buf_mesh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_MESH")
- port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buf_mesh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_MESH")
+ port map(mm_rst, i_mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso);
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -204,10 +215,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -225,138 +236,138 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_fn_terminal_db
- port map (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer_mesh
- coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ -- 1) global signals:
+ clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
+ cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
+
+ -- the_altpll_0
+ areset_to_the_altpll_0 => '0',
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_tr_nonbonded_mesh
+ coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
+ coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diagnostics_mesh
+ coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
+ coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer_mesh
+ coe_address_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer_mesh => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer_mesh => ram_mesh_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc510062859aa916d7f5743157ee601e5a717..a01f04a0fbcdf13efd1fb1111c393d66e1afeb71 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -123,13 +123,13 @@
-- advantage is that it
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
@@ -238,7 +238,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -249,67 +249,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -328,6 +328,7 @@ begin
-- From 2d to 1d array
---------------------------------------------------------------------------------------
gen_i : for I in 0 to c_unb1_board_nof_bn - 1 generate
+
gen_j : for J in 0 to c_usr_nof_streams_per_bus - 1 generate
rx_rew_siso_2arr(I)(J) <= rx_usr_siso_arr(I * c_usr_nof_streams_per_bus + J);
rx_usr_sosi_arr(I * c_usr_nof_streams_per_bus + J) <= rx_rew_sosi_2arr(I)(J);
@@ -345,51 +346,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -402,27 +403,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index c3b0cd899761a0826b370b36ba22671b8825cdff..74846364dc12c40e5d8a0f6826c78e7acf71802a 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_fn_terminal_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_fn_terminal_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -172,204 +172,204 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_fn_terminal_db
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
-
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- cal_clk => cal_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
-
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
- );
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ cal_clk => cal_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+
+ );
-----------------------------------------------------------------------------
-- Node functioon: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_unb1_fn_terminal_db : entity unb1_board_lib.node_unb1_fn_terminal_db
- generic map(
- g_multi_unb => g_rev_multi_unb,
- -- Terminals interface
- g_use_mesh => c_use_mesh,
- g_mesh_mon_select => c_mesh_mon_select,
- g_mesh_mon_nof_words => c_mesh_mon_nof_words,
- g_mesh_mon_use_sync => c_mesh_mon_use_sync,
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- chip_id => this_chip_id,
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- -- . bsn_monitor
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Mesh interface
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_multi_unb => g_rev_multi_unb,
+ -- Terminals interface
+ g_use_mesh => c_use_mesh,
+ g_mesh_mon_select => c_mesh_mon_select,
+ g_mesh_mon_nof_words => c_mesh_mon_nof_words,
+ g_mesh_mon_use_sync => c_mesh_mon_use_sync,
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ chip_id => this_chip_id,
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Mesh interface
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -380,23 +380,22 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
-
end;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 25bd96f7d89711519fc854a42162f667075a8031..64e7bd1cb28f096283dafb34202fc1dc7a92b621 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -73,17 +73,17 @@
--
library IEEE, common_lib, unb_common_lib, bn_terminal_bg_lib, mm_lib, bf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use unb_common_lib.unb_common_pkg.all;
-use unb_common_lib.tb_unb_common_pkg.all;
-use bf_lib.bf_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use unb_common_lib.tb_unb_common_pkg.all;
+ use bf_lib.bf_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
entity tb_mmf_node_fn_terminal_db is
generic (
@@ -96,7 +96,7 @@ architecture tb of tb_mmf_node_fn_terminal_db is
constant c_sim : boolean := true;
constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false); -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
- -- this loops back each back node's BN_BI_TX to BN_BI_RX.
+ -- this loops back each back node's BN_BI_TX to BN_BI_RX.
constant c_ena_mesh_reorder : boolean := true;
constant c_mesh_use_bidir : boolean := false;
constant c_mesh_nof_serial : natural := 3; -- default only use the 3 full featured transceivers in the mesh (out of maximal 4), using only 2 is not enough
@@ -220,6 +220,7 @@ begin
-- DUTs and their MM buses
----------------------------------------------------------------------------
gen_unb : for UNB in 0 to g_unb_sys.nof_unb - 1 generate
+
gen_bn: for BN in 0 to g_unb_sys.nof_bn - 1 generate
----------------------------------------------------------------------------
-- bn_terminal_bg: MM <-> file I/O
@@ -227,11 +228,13 @@ begin
--u_mm_file_reg_diagnostics_back : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAGNOSTICS_BACK")
-- PORT MAP(mm_rst, mm_clk, bn_reg_diagnostics_back_mosi_2arr(UNB)(BN), bn_reg_diagnostics_back_miso_2arr(UNB)(BN) );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, bn_reg_diag_bg_mosi_2arr(UNB)(BN), bn_reg_diag_bg_miso_2arr(UNB)(BN) );
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(UNB, BN, "BN") & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, bn_ram_diag_bg_mosi_2arr(UNB)(BN), bn_ram_diag_bg_miso_2arr(UNB)(BN) );
--u_mm_file_reg_tr_nonbonded_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, BN, "BN") & "REG_TR_NONBONDED_MESH")
-- PORT MAP(mm_rst, mm_clk, bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN), bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN) );
@@ -252,58 +255,58 @@ begin
-- bn_terminal_bg: Node function: block generator & terminals
----------------------------------------------------------------------------
u_node_bn_terminal_bg : entity bn_terminal_bg_lib.node_bn_terminal_bg
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_back => c_use_back,
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_rx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_CLK,
- tr_back_clk => tr_CLK,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
- bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
-
- -- MM interface
- -- . block generator
- reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
- reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
- ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
- ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
- -- . tr_nonbonded mesh
- reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
- reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
- reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
- -- . tr_nonbonded back
- reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
- reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
- reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
- reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
- -- . diag_data_buffer mesh
- ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
- ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
- mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
-
- -- Back interface level
- -- . Serial (tr_nonbonded)
- back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
- back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_back => c_use_back,
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_rx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_CLK,
+ tr_back_clk => tr_CLK,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(BN + 4, c_unb_nof_chip_w), -- BN chip ID 4,5,6,7
+ bck_id => TO_UVEC(UNB, c_unb_nof_uniboard_w), -- Backplane ID 0,1,2,3
+
+ -- MM interface
+ -- . block generator
+ reg_diag_bg_mosi => bn_reg_diag_bg_mosi_2arr(UNB)(BN),
+ reg_diag_bg_miso => bn_reg_diag_bg_miso_2arr(UNB)(BN),
+ ram_diag_bg_mosi => bn_ram_diag_bg_mosi_2arr(UNB)(BN),
+ ram_diag_bg_miso => bn_ram_diag_bg_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded mesh
+ reg_mesh_tr_nonbonded_mosi => bn_reg_tr_nonbonded_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_tr_nonbonded_miso => bn_reg_tr_nonbonded_mesh_miso_2arr(UNB)(BN),
+ reg_mesh_diagnostics_mosi => bn_reg_diagnostics_mesh_mosi_2arr(UNB)(BN),
+ reg_mesh_diagnostics_miso => bn_reg_diagnostics_mesh_miso_2arr(UNB)(BN),
+ -- . tr_nonbonded back
+ reg_back_tr_nonbonded_mosi => bn_reg_tr_nonbonded_back_mosi_2arr(UNB)(BN),
+ reg_back_tr_nonbonded_miso => bn_reg_tr_nonbonded_back_miso_2arr(UNB)(BN),
+ reg_back_diagnostics_mosi => bn_reg_diagnostics_back_mosi_2arr(UNB)(BN),
+ reg_back_diagnostics_miso => bn_reg_diagnostics_back_miso_2arr(UNB)(BN),
+ -- . diag_data_buffer mesh
+ ram_mesh_diag_data_buf_mosi => bn_ram_diag_data_buf_mesh_mosi_2arr(UNB)(BN),
+ ram_mesh_diag_data_buf_miso => bn_ram_diag_data_buf_mesh_miso_2arr(UNB)(BN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ mesh_tx_serial_2arr => bn_out_mesh_serial_4arr(UNB)(BN),
+ mesh_rx_serial_2arr => bn_in_mesh_serial_4arr(UNB)(BN),
+
+ -- Back interface level
+ -- . Serial (tr_nonbonded)
+ back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
+ back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
+ );
end generate;
gen_fn: for FN in 0 to g_unb_sys.nof_fn - 1 generate
@@ -316,11 +319,13 @@ begin
--u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAGNOSTICS_MESH")
-- PORT MAP(mm_rst, mm_clk, fn_reg_diagnostics_mosi_2arr(UNB)(FN), fn_reg_diagnostics_miso_2arr(UNB)(FN) );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, fn_ram_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_diag_data_buf_miso_2arr(UNB)(FN) );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(UNB, FN, "FN") & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, fn_reg_diag_data_buf_mosi_2arr(UNB)(FN), fn_reg_diag_data_buf_miso_2arr(UNB)(FN) );
--u_mm_file_ram_diag_data_buf_mesh : mm_file GENERIC MAP(mmf_unb_file_prefix(UNB, FN, "FN") & "RAM_DIAG_DATA_BUFFER_MESH")
-- PORT MAP(mm_rst, mm_clk, fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN), fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN) );
@@ -335,52 +340,52 @@ begin
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_node_fn_terminal_db : entity work.node_unb1_fn_terminal_db
- generic map(
- g_sim => c_sim,
- g_sim_level => g_sim_level,
- g_use_bsn_align => true,
- g_use_data_buf => true,
- -- Terminals interface
- g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
- g_mesh_nof_serial => c_mesh_nof_serial,
- g_mesh_use_tx => c_mesh_use_bidir,
- g_mesh_ena_reorder => c_ena_mesh_reorder
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => tr_clk,
- cal_clk => cal_rec_clk,
-
- chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
-
- -- MM interface
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
- reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
- reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
- reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
- reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
- reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
- -- . diag_data_buffer_mesh
- ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
- ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
- -- . bsn_monitor
- reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
- reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
-
- -- Mesh interface level
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
- rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
- );
+ generic map(
+ g_sim => c_sim,
+ g_sim_level => g_sim_level,
+ g_use_bsn_align => true,
+ g_use_data_buf => true,
+ -- Terminals interface
+ g_multi_unb => sel_a_b(g_unb_sys.nof_unb > 1, true, false),
+ g_mesh_nof_serial => c_mesh_nof_serial,
+ g_mesh_use_tx => c_mesh_use_bidir,
+ g_mesh_ena_reorder => c_ena_mesh_reorder
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => tr_clk,
+ cal_clk => cal_rec_clk,
+
+ chip_id => TO_UVEC(FN, c_unb_nof_chip_w), -- FN chip ID 0,1,2,3
+
+ -- MM interface
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => fn_reg_tr_nonbonded_mosi_2arr(UNB)(FN),
+ reg_tr_nonbonded_miso => fn_reg_tr_nonbonded_miso_2arr(UNB)(FN),
+ reg_diagnostics_mosi => fn_reg_diagnostics_mosi_2arr(UNB)(FN),
+ reg_diagnostics_miso => fn_reg_diagnostics_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => fn_ram_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_diag_data_buf_miso => fn_ram_diag_data_buf_miso_2arr(UNB)(FN),
+ reg_diag_data_buf_mosi => fn_reg_diag_data_buf_mosi_2arr(UNB)(FN),
+ reg_diag_data_buf_miso => fn_reg_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . diag_data_buffer_mesh
+ ram_mesh_diag_data_buf_mosi => fn_ram_mesh_diag_data_buf_mosi_2arr(UNB)(FN),
+ ram_mesh_diag_data_buf_miso => fn_ram_mesh_diag_data_buf_miso_2arr(UNB)(FN),
+ -- . bsn_monitor
+ reg_bsn_monitor_mosi => fn_reg_bsn_monitor_mosi_2arr(UNB)(FN),
+ reg_bsn_monitor_miso => fn_reg_bsn_monitor_miso_2arr(UNB)(FN),
+
+ -- Mesh interface level
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
+ rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
+ );
end generate;
------------------------------------------------------------------------------
@@ -399,38 +404,36 @@ begin
-- Mesh model
gen_mesh : if g_unb_sys.nof_bn > 1 or g_unb_sys.nof_fn > 1 generate
u_mesh_model_serial : entity unb_common_lib.unb_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
- bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
- fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_4arr(UNB),
+ bn_rx_sl_3arr => bn_in_mesh_serial_4arr(UNB),
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_4arr(UNB),
+ fn_rx_sl_3arr => fn_in_mesh_serial_4arr(UNB)
+ );
end generate;
-
end generate;
- ------------------------------------------------------------------------------
- -- Instantiate a backplane model that interconnects all UniBoards...
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- Instantiate a backplane model that interconnects all UniBoards...
+ ------------------------------------------------------------------------------
gen_backplane : if c_use_back = true generate
gen_model : entity unb_common_lib.unb_back_model_sl
- port map (
- backplane_in_serial_4arr => bn_out_back_serial_4arr,
- backplane_out_serial_4arr => bn_in_back_serial_4arr
- );
+ port map (
+ backplane_in_serial_4arr => bn_out_back_serial_4arr,
+ backplane_out_serial_4arr => bn_in_back_serial_4arr
+ );
end generate;
- ------------------------------------------------------------------------------
- -- ...or loop back serial TX to RX in case of a single UniBoard.
- ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- ...or loop back serial TX to RX in case of a single UniBoard.
+ ------------------------------------------------------------------------------
no_backplane: if c_use_back = false generate
bn_in_back_serial_4arr <= bn_out_back_serial_4arr;
end generate;
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 78bdc17f233b68281ae52a27903f3657d6d7e08d..4b8748e8199df066c3be6c1acd6c9b6f4ddc7329 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_heater_pkg.all;
entity mmm_unb1_heater is
generic (
@@ -126,31 +126,42 @@ begin
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, i_mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -171,7 +182,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -307,7 +318,6 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 6ab5775f35323f6cb09dd41e5a6b51e08d93a79a..55ce65f0128cbe798048adb978776bd5d99b30c8 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -20,129 +20,128 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
-
- component qsys_unb1_heater is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb1_heater;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb1_heater is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb1_heater;
end qsys_unb1_heater_pkg;
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 8187b73626611866ff1ac6d01ecd72c65c2b4ffa..6852518ebd753a5ea08b5e09624a39504bc70070 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb1_heater is
generic (
@@ -148,201 +148,201 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- g_nof_mac4 => 315
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_mac4 => 315
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index 42cf774fa0baec99a5258e50fc374fe297a965b7..54df0f2df3f37e42cf268ab8b877469a302bc24d 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_heater is
- generic (
- g_design_name : string := "unb1_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_heater;
architecture tb of tb_unb1_heater is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
index 158c2a2617ea08a4d6399a911ab2548a4f1643b3..946b566c5f42086eab555e8fe178183bab04414d 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_mm_arbiter is
end tb_unb1_minimal_mm_arbiter;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_mm_arbiter;
architecture tb of tb_unb1_minimal_mm_arbiter is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_mm_arbiter",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_mm_arbiter",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 94b8a71585d0c48b2e788098e0449a91a2a51c3c..ead6369fbe3cdb3935cefe3e71ceddfaa3c1b05a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_mm_arbiter is
generic (
@@ -62,36 +62,36 @@ end unb1_minimal_mm_arbiter;
architecture str of unb1_minimal_mm_arbiter is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
index 86785da2a3dbbdaa2ff1b05e30d779402650090d..49536e63dcf65d488d6806041fe6a52dffd4f3b7 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_qsys is
end tb_unb1_minimal_qsys;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_qsys;
architecture tb of tb_unb1_minimal_qsys is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_qsys",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_qsys",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
index 984cbc8b4cea62a341335896d2d437aa93d8cfde..22f2f6a69d1a2ef3ea159ae623f5ac291a8890c0 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
@@ -44,13 +44,13 @@
-- > run 100 us
--
library IEEE, common_lib, mm_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity tb_unb1_minimal_qsys_stimuli is
end tb_unb1_minimal_qsys_stimuli;
@@ -188,38 +188,38 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- MM slave accesses via file IO
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 0f6289c4b140bd78a6f0543e7a32a0b2e5d2a06e..d00dcf4cfea4361fd29bb336c476ca22129ca8f7 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys is
generic (
@@ -62,36 +62,36 @@ end unb1_minimal_qsys;
architecture str of unb1_minimal_qsys is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 225991915478557e0526f302a2ea6e41550bec83..435b2501ede2eac50562682ca9075102fa87273c 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -20,24 +20,24 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_wo_pll_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_wo_pll_unb1_minimal_pkg.all;
entity mmm_unb1_minimal_qsys_wo_pll is
generic (
@@ -106,7 +106,7 @@ architecture str of mmm_unb1_minimal_qsys_wo_pll is
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -121,28 +121,39 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -184,7 +195,7 @@ begin
----------------------------------------------------------------------------
gen_qsys : if g_sim = false generate
signal mm_rst_n : std_logic;
- begin
+ begin
mm_rst_n <= not (mm_rst);
u_qsys : qsys_wo_pll_unb1_minimal
@@ -314,7 +325,6 @@ begin
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
index 142125fe43a2877ae7f01bfc3caab67d082ade0a..584bbdba8ad5365cf379b6e907cd999fdd322eb8 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
@@ -20,116 +20,115 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_wo_pll_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_wo_pll_unb1_minimal is
-
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
- end component qsys_wo_pll_unb1_minimal;
+ component qsys_wo_pll_unb1_minimal is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
+ end component qsys_wo_pll_unb1_minimal;
end qsys_wo_pll_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 0359b319110d7ccfaa3794a5b6938ae577521101..8e11840aaae65f20c514b10bde7ad4bdadaa996b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal_qsys_wo_pll is
- generic (
- g_design_name : string := "unb1_minimal_qsys_wo_pll";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal_qsys_wo_pll";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal_qsys_wo_pll;
architecture tb of tb_unb1_minimal_qsys_wo_pll is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index 408c4bc506017ca1d924566a62823f2e48154beb..4017e4ddd1a7d48287b93cf3d121f895cdb7b297 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_qsys_wo_pll is
generic (
@@ -141,186 +141,186 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_dp_clk_freq => c_unb1_board_ext_clk_freq_200M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal_qsys_wo_pll
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
-----------------------------------------------------------------------------
-- Node function
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
index 73b74d631423c98f5bfca6e7ad9ff68548eadaf6..38a87df6a6fd2ccd7f44e371ad9a527d27b895c1 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_minimal
library IEEE, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_minimal_sopc is
end tb_unb1_minimal_sopc;
@@ -32,8 +32,8 @@ end tb_unb1_minimal_sopc;
architecture tb of tb_unb1_minimal_sopc is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
- generic map (
- g_design_name => "unb1_minimal_sopc",
- g_sim_node_nr => 7 -- BN3
- );
+ generic map (
+ g_design_name => "unb1_minimal_sopc",
+ g_sim_node_nr => 7 -- BN3
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 31d891bafd689e7910b4bd57833a04e0d9393a30..abe161a3e94a1373aece1ea9a12eba5877f9f691 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, unb1_board_lib, unb1_minimal_lib;
-use IEEE.std_logic_1164.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal_sopc is
generic (
@@ -62,35 +62,35 @@ end unb1_minimal_sopc;
architecture str of unb1_minimal_sopc is
begin
u_revision : entity unb1_minimal_lib.unb1_minimal
- generic map (
- g_design_name => g_design_name,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index d0dbf2fd6e39c1f69358d620fdbd979b401fc58f..08da2c1d9981c034d79eadd1028125f14bb27fcb 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb1_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb1_minimal_pkg.all;
entity mmm_unb1_minimal is
generic (
@@ -155,28 +155,38 @@ begin
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, i_mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, i_mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -190,140 +200,140 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false and g_use_sopc = true generate
u_sopc : entity work.sopc_unb1_minimal
- port map (
- clk_0 => xo_clk,
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk,
- tse_clk => eth1g_tse_clk,
- epcs_clk => i_epcs_clk,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_pps
- coe_clk_export_from_the_pio_pps => OPEN,
- coe_reset_export_from_the_pio_pps => OPEN,
- coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
- coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
- coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
- coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_dpmm_data
- coe_clk_export_from_the_reg_dpmm_data => OPEN,
- coe_reset_export_from_the_reg_dpmm_data => OPEN,
- coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dpmm_ctrl
- coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
- coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_data
- coe_clk_export_from_the_reg_mmdp_data => OPEN,
- coe_reset_export_from_the_reg_mmdp_data => OPEN,
- coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_mmdp_ctrl
- coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
- coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
- coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
- coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
- coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_epcs
- coe_clk_export_from_the_reg_epcs => OPEN,
- coe_reset_export_from_the_reg_epcs => OPEN,
- coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
- coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
- coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_remu
- coe_clk_export_from_the_reg_remu => OPEN,
- coe_reset_export_from_the_reg_remu => OPEN,
- coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
- coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
- coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
+ port map (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk,
+ tse_clk => eth1g_tse_clk,
+ epcs_clk => i_epcs_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_pps
+ coe_clk_export_from_the_pio_pps => OPEN,
+ coe_reset_export_from_the_pio_pps => OPEN,
+ coe_address_export_from_the_pio_pps => reg_ppsh_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_ppsh_adr_w - 1), -- 1 bit address width so must use (0) instead of (0 DOWNTO 0)
+ coe_read_export_from_the_pio_pps => reg_ppsh_mosi.rd,
+ coe_readdata_export_to_the_pio_pps => reg_ppsh_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_pps => reg_ppsh_mosi.wr,
+ coe_writedata_export_from_the_pio_pps => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb1_board.
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_dpmm_data
+ coe_clk_export_from_the_reg_dpmm_data => OPEN,
+ coe_reset_export_from_the_reg_dpmm_data => OPEN,
+ coe_address_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_data => reg_dpmm_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_data => reg_dpmm_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dpmm_ctrl
+ coe_clk_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_reset_export_from_the_reg_dpmm_ctrl => OPEN,
+ coe_address_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_dpmm_ctrl => reg_dpmm_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_dpmm_ctrl => reg_dpmm_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_data
+ coe_clk_export_from_the_reg_mmdp_data => OPEN,
+ coe_reset_export_from_the_reg_mmdp_data => OPEN,
+ coe_address_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_data => reg_mmdp_data_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_data => reg_mmdp_data_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_mmdp_ctrl
+ coe_clk_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_reset_export_from_the_reg_mmdp_ctrl => OPEN,
+ coe_address_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.address(0),
+ coe_read_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.rd,
+ coe_readdata_export_to_the_reg_mmdp_ctrl => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
+ coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_epcs
+ coe_clk_export_from_the_reg_epcs => OPEN,
+ coe_reset_export_from_the_reg_epcs => OPEN,
+ coe_address_export_from_the_reg_epcs => reg_epcs_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_epcs_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_epcs => reg_epcs_mosi.rd,
+ coe_readdata_export_to_the_reg_epcs => reg_epcs_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_epcs => reg_epcs_mosi.wr,
+ coe_writedata_export_from_the_reg_epcs => reg_epcs_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_remu
+ coe_clk_export_from_the_reg_remu => OPEN,
+ coe_reset_export_from_the_reg_remu => OPEN,
+ coe_address_export_from_the_reg_remu => reg_remu_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_remu_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_remu => reg_remu_mosi.rd,
+ coe_readdata_export_to_the_reg_remu => reg_remu_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_remu => reg_remu_mosi.wr,
+ coe_writedata_export_from_the_reg_remu => reg_remu_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
@@ -336,7 +346,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -463,14 +473,13 @@ begin
coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-----------------------------------------------------------------------------
-- MM arbiter experiment
-----------------------------------------------------------------------------
gen_mm_arbiter : if g_use_qsys = false and g_use_sopc = false generate -- Still a QSYS actually....bus a minimal one.
-
-----------------------------------------------------------------------------
-- MM master: a minimal QSYS (for now)
-----------------------------------------------------------------------------
@@ -482,7 +491,7 @@ begin
tse_clk => eth1g_tse_clk,
epcs_clk => i_epcs_clk,
- -- the_altpll_0
+ -- the_altpll_0
locked_from_the_altpll_0 => mm_locked,
phasedone_from_the_altpll_0 => OPEN,
areset_to_the_altpll_0 => xo_rst,
@@ -531,21 +540,21 @@ begin
-- MM arbiter
-----------------------------------------------------------------------------
u_mm_arbiter : entity mm_lib.mm_arbiter
- generic map (
- g_nof_slaves => c_nof_slaves,
- g_slave_base_arr => c_slave_base_arr,
- g_slave_high_arr => c_slave_high_arr
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => mm_rst,
-
- master_mosi => master_mosi,
- master_miso => master_miso,
-
- slave_mosi_arr => slave_mosi_arr,
- slave_miso_arr => slave_miso_arr
- );
+ generic map (
+ g_nof_slaves => c_nof_slaves,
+ g_slave_base_arr => c_slave_base_arr,
+ g_slave_high_arr => c_slave_high_arr
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => mm_rst,
+
+ master_mosi => master_mosi,
+ master_miso => master_miso,
+
+ slave_mosi_arr => slave_mosi_arr,
+ slave_miso_arr => slave_miso_arr
+ );
-----------------------------------------------------------------------------
-- Connect slave array to individually names MM buses
@@ -557,7 +566,7 @@ begin
slave_miso_arr(1) <= rom_unb_system_info_miso;
-- pio_system_info; still needed within QSYS, so not connected here.
--- reg_unb_system_info_mosi <= slave_mosi_arr(2);
+ -- reg_unb_system_info_mosi <= slave_mosi_arr(2);
slave_miso_arr(2) <= c_mem_miso_rst;
reg_ppsh_mosi <= slave_mosi_arr(3);
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 63e5d9c4da7458d9ab0c6208a30252181f8406be..4bae2113c9fdeae5c7042046dc07b4a402e215cb 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -20,171 +20,170 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
- component qsys_unb1_minimal is
+ component qsys_unb1_minimal is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- mm_clk : out std_logic; -- clk
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- coe_read_export_from_the_reg_remu : out std_logic -- export
- );
- end component qsys_unb1_minimal;
-
- component qsys_unb1_minimal_mm_arbiter is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- mm_clk : out std_logic; -- clk
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- phasedone_from_the_altpll_0 : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- clk_0 : in std_logic := 'X'; -- clk
- tse_clk : out std_logic; -- clk
- epcs_clk : out std_logic; -- clk
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- areset_to_the_altpll_0 : in std_logic := 'X'; -- export
- locked_from_the_altpll_0 : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- c3_from_the_altpll_0 : out std_logic; -- export
- to_mm_arbiter_reset_export : out std_logic; -- export
- to_mm_arbiter_clk_export : out std_logic; -- export
- to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
- to_mm_arbiter_write_export : out std_logic; -- export
- to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
- to_mm_arbiter_read_export : out std_logic; -- export
- to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_minimal_mm_arbiter;
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ mm_clk : out std_logic; -- clk
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic; -- _vector(0 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic; -- _vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic; -- _vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ coe_read_export_from_the_reg_remu : out std_logic -- export
+ );
+ end component qsys_unb1_minimal;
+ component qsys_unb1_minimal_mm_arbiter is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ mm_clk : out std_logic; -- clk
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ phasedone_from_the_altpll_0 : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ tse_clk : out std_logic; -- clk
+ epcs_clk : out std_logic; -- clk
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ areset_to_the_altpll_0 : in std_logic := 'X'; -- export
+ locked_from_the_altpll_0 : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ c3_from_the_altpll_0 : out std_logic; -- export
+ to_mm_arbiter_reset_export : out std_logic; -- export
+ to_mm_arbiter_clk_export : out std_logic; -- export
+ to_mm_arbiter_address_export : out std_logic_vector(10 downto 0); -- export
+ to_mm_arbiter_write_export : out std_logic; -- export
+ to_mm_arbiter_writedata_export : out std_logic_vector(31 downto 0); -- export
+ to_mm_arbiter_read_export : out std_logic; -- export
+ to_mm_arbiter_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_minimal_mm_arbiter;
end qsys_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index fbb7e941a498c245f4b613ce475fb52afcdcbf16..4cb860275229d169d6a71734be42795a7c409d09 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
entity unb1_minimal is
generic (
@@ -144,186 +144,186 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_epcs_protect_addr_range => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- epcs_clk => epcs_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_epcs_protect_addr_range => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ epcs_clk => epcs_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_use_qsys => c_use_qsys,
- g_use_sopc => c_use_sopc
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- epcs_clk => epcs_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_use_qsys => c_use_qsys,
+ g_use_sopc => c_use_sopc
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ epcs_clk => epcs_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
-----------------------------------------------------------------------------
-- Node function
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index 4ffbccca21578df961a7fefa384f08dd05e2bbd5..b0961594ee6158be0523f39d1c083e01bf865f94 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_minimal is
- generic (
- g_design_name : string := "unb1_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_minimal;
architecture tb of tb_unb1_minimal is
@@ -163,36 +163,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 438450102620f3443679561df9df3d0682264f75..663c9e6dd3b451a01ac0edac6822418a0982e429 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -66,23 +66,23 @@
-- );
--
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_terminal_bg_mesh_db is
generic (
@@ -135,7 +135,7 @@ architecture str of mmm_unb1_terminal_bg_mesh_db is
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -267,38 +267,70 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
- u_mm_file_reg_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
- u_mm_file_ram_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
- port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
- u_mm_file_reg_diagnostics : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
- port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
- u_mm_file_reg_tr_nonbonded : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
- port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
- u_mm_file_ram_mesh_diag_data_buf : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
- port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+
+ u_mm_file_reg_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso );
+
+ u_mm_file_ram_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso );
+
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
+
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
+
+ u_mm_file_reg_diagnostics : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ port map(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+
+ u_mm_file_reg_tr_nonbonded : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+ port map(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+
+ u_mm_file_ram_mesh_diag_data_buf : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_MESH_DIAG_DATA_BUF")
+ port map(mm_rst, mm_clk, ram_mesh_diag_data_buf_mosi, ram_mesh_diag_data_buf_miso );
+
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -339,7 +371,7 @@ begin
mm_rst_n <= not(mm_rst);
u_qsys_unb1_terminal_bg_mesh_db : qsys_unb1_terminal_bg_mesh_db
- port map(
+ port map(
clk_in_clk => mm_clk,
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_mm_clk_export => OPEN,
@@ -456,5 +488,4 @@ begin
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index f70200f9e086dfadf9bf9f00fef0540ef1e0761b..c98af06b0176054fbdc10fb15da5ca21578df172 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -29,13 +29,13 @@
-- Some more remarks:
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_terminal_bg_mesh_db is
generic(
@@ -72,12 +72,12 @@ entity node_unb1_terminal_bg_mesh_db is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -197,6 +197,7 @@ begin
-- From 2d to 1d array. Input port to input BG.
---------------------------------------------------------------------------------------
gen_i_a : for I in 0 to g_nof_bus - 1 generate
+
gen_j_a : for J in 0 to g_usr_nof_streams - 1 generate
bg_snk_in_arr(I * g_usr_nof_streams + J) <= tx_usr_sosi_2arr(I)(J);
tx_usr_siso_2arr(I)(J) <= bg_snk_out_arr(I * g_usr_nof_streams + J);
@@ -207,45 +208,46 @@ begin
-- Block Generator
---------------------------------------------------------------------------------------
u_bg : entity diag_lib.mms_diag_block_gen
- generic map(
- -- Generate configurations
- g_use_usr_input => c_use_usr_input,
- g_use_bg => g_use_bg,
- g_use_tx_seq => false,
- -- General
- g_nof_streams => c_bg_nof_streams,
- -- BG settings
- g_use_bg_buffer_ram => true,
- g_buf_dat_w => c_nof_complex * c_in_dat_w,
- g_buf_addr_w => c_bg_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- -- User input multiplexer option
- g_usr_bypass_xonoff => false
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
-
- -- ST interface
- usr_siso_arr => bg_snk_out_arr,
- usr_sosi_arr => bg_snk_in_arr,
- out_siso_arr => bg_src_in_arr,
- out_sosi_arr => bg_src_out_arr
- );
+ generic map(
+ -- Generate configurations
+ g_use_usr_input => c_use_usr_input,
+ g_use_bg => g_use_bg,
+ g_use_tx_seq => false,
+ -- General
+ g_nof_streams => c_bg_nof_streams,
+ -- BG settings
+ g_use_bg_buffer_ram => true,
+ g_buf_dat_w => c_nof_complex * c_in_dat_w,
+ g_buf_addr_w => c_bg_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ -- User input multiplexer option
+ g_usr_bypass_xonoff => false
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+
+ -- ST interface
+ usr_siso_arr => bg_snk_out_arr,
+ usr_sosi_arr => bg_snk_in_arr,
+ out_siso_arr => bg_src_in_arr,
+ out_sosi_arr => bg_src_out_arr
+ );
---------------------------------------------------------------------------------------
-- From 1d to 2d array. Output BG to input Mesh
---------------------------------------------------------------------------------------
gen_i_b : for I in 0 to g_nof_bus - 1 generate
+
gen_j_b : for J in 0 to g_usr_nof_streams - 1 generate
bg_src_in_arr(I * g_usr_nof_streams + J) <= bg_out_siso_2arr(I)(J);
bg_out_sosi_2arr(I)(J) <= bg_src_out_arr(I * g_usr_nof_streams + J);
@@ -253,80 +255,81 @@ begin
end generate;
u_mesh_terminal : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => g_node_type,
- g_nof_bus => g_nof_bus,
- -- User
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- g_usr_nof_streams => g_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- g_phy_gx_mbps => g_phy_gx_mbps,
- g_phy_rx_fifo_size => g_phy_rx_fifo_size,
- g_phy_ena_reorder => g_phy_ena_reorder,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
-
- -- Monitoring
- g_mon_select => g_mon_select,
- g_mon_nof_words => g_mon_nof_words,
- g_mon_use_sync => g_mon_use_sync,
-
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => bg_out_siso_2arr,
- tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
- rx_usr_siso_2arr => rx_usr_i_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
-
- -- Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . monitor data buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => g_node_type,
+ g_nof_bus => g_nof_bus,
+ -- User
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ g_usr_nof_streams => g_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ g_phy_gx_mbps => g_phy_gx_mbps,
+ g_phy_rx_fifo_size => g_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_phy_ena_reorder,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+
+ -- Monitoring
+ g_mon_select => g_mon_select,
+ g_mon_nof_words => g_mon_nof_words,
+ g_mon_use_sync => g_mon_use_sync,
+
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => bg_out_siso_2arr,
+ tx_usr_sosi_2arr => bg_out_sosi_2arr, -- <== Data to the Mesh
+ rx_usr_siso_2arr => rx_usr_i_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_i_sosi_2arr, -- ==> Data from the Mesh
+
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . monitor data buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- From 2d to 1d array. Input port to input BG.
---------------------------------------------------------------------------------------
gen_i_c : for I in 0 to g_nof_bus - 1 generate
+
gen_j_c : for J in 0 to g_usr_nof_streams - 1 generate
bsn_align_snk_in_arr(I * g_usr_nof_streams + J) <= rx_usr_i_sosi_2arr(I)(J);
rx_usr_i_siso_2arr(I)(J) <= bsn_align_snk_out_arr(I * g_usr_nof_streams + J);
@@ -338,25 +341,25 @@ begin
-----------------------------------------------------------------------------
gen_bsn_align : if g_use_bsn_align generate
u_dp_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => c_block_size,
- g_block_period => c_block_period,
- g_nof_input => c_bsn_align_nof_streams,
- g_xoff_timeout => c_bsn_align_xoff_timeout,
- g_sop_timeout => c_bsn_align_sop_timeout,
- g_bsn_latency => c_bsn_align_latency,
- g_bsn_request_pipeline => 2
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => bsn_align_snk_out_arr,
- snk_in_arr => bsn_align_snk_in_arr,
-
- src_in_arr => bsn_align_src_in_arr,
- src_out_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_bsn_align_nof_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => bsn_align_snk_out_arr,
+ snk_in_arr => bsn_align_snk_in_arr,
+
+ src_in_arr => bsn_align_src_in_arr,
+ src_out_arr => bsn_align_src_out_arr
+ );
end generate;
gen_no_bsn_align : if not(g_use_bsn_align) generate
@@ -368,55 +371,56 @@ begin
-- BSN monitors at the output of the BSN aligner
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_bsn_mon_nof_streams,
- g_sync_timeout => c_bsn_sync_time_out,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => bsn_mon_snk_out_arr,
- in_sosi_arr => bsn_mon_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_bsn_mon_nof_streams,
+ g_sync_timeout => c_bsn_sync_time_out,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => bsn_mon_snk_out_arr,
+ in_sosi_arr => bsn_mon_snk_in_arr
+ );
bsn_mon_snk_in_arr <= bsn_align_src_out_arr(c_bsn_mon_nof_streams - 1 downto 0);
bsn_mon_snk_out_arr <= bsn_align_src_in_arr(c_bsn_mon_nof_streams - 1 downto 0);
gen_data_buf : if g_use_data_buf generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => c_db_nof_data,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bsn_align_src_out_arr(0).sync,
- in_sosi_arr => bsn_align_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => c_db_nof_data,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bsn_align_src_out_arr(0).sync,
+ in_sosi_arr => bsn_align_src_out_arr
+ );
end generate;
---------------------------------------------------------------------------------------
-- From 1d to 2d array. Output BSN Aligner to port output
---------------------------------------------------------------------------------------
gen_i_d : for I in 0 to g_nof_bus - 1 generate
+
gen_j_d : for J in 0 to g_usr_nof_streams - 1 generate
bsn_align_src_in_arr(I * g_usr_nof_streams + J) <= rx_usr_siso_2arr(I)(J);
rx_usr_sosi_2arr(I)(J) <= bsn_align_src_out_arr(I * g_usr_nof_streams + J);
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index ec6f3afdfdca813569388e2c23ac27861bc3f7d1..0f714e74abb9a80dfb0ccccfa97f73360cd174ad 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -20,18 +20,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity unb1_terminal_bg_mesh_db is
generic (
@@ -47,7 +47,7 @@ entity unb1_terminal_bg_mesh_db is
g_stamp_svn : natural := 0 -- SVN revision -- set by QSF
);
port (
- -- GENERAL
+ -- GENERAL
CLK : in std_logic; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
@@ -212,238 +212,238 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_sim_flash_model => not(g_sim),
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_sim_flash_model => not(g_sim),
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_inst_mmm_unb1_terminal_bg_mesh_db : entity work.mmm_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
-----------------------------------------------------------------------------
-- Node function: Terminals and data buffer
-----------------------------------------------------------------------------
u_terminal_mesh : entity work.node_unb1_terminal_bg_mesh_db
- generic map(
- g_sim => g_sim,
- g_sim_level => g_sim_level,
-
- -- BLOCK GENERATOR
- g_use_bg => c_use_bg,
-
- -- MESH TERMINAL
- -- System
- g_node_type => c_node_type,
- g_nof_bus => c_nof_bus,
- -- User
- g_usr_use_complex => c_usr_use_complex,
- g_usr_data_w => c_usr_data_w,
- g_usr_frame_len => c_usr_frame_len,
- g_usr_nof_streams => c_usr_nof_streams,
- -- Phy
- g_phy_nof_serial => c_phy_nof_serial,
- g_phy_gx_mbps => c_phy_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => c_phy_ena_reorder,
- -- Tx
- g_use_tx => c_use_tx,
- g_tx_input_use_fifo => c_tx_input_use_fifo,
- g_tx_input_fifo_size => c_tx_input_fifo_size,
- g_tx_input_fifo_fill => c_tx_input_fifo_fill,
- -- Rx
- g_use_rx => c_use_rx,
- g_rx_output_use_fifo => c_rx_output_use_fifo,
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => c_mon_select,
- g_mon_nof_words => c_mon_nof_words,
- g_mon_use_sync => c_mon_use_sync,
- -- UTH
- g_uth_len_max => c_uth_len_max,
- g_uth_typ_ofs => c_uth_typ_ofs,
-
- -- Auxiliary Interface
- g_aux => c_unb1_board_aux,
- -- BSN ALIGNER
- g_use_bsn_align => c_use_bsn_align,
- -- DATA BUFFER
- g_use_data_buf => c_use_data_buf
- )
- port map(
- -- System
- chip_id => this_chip_id,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- tr_mesh_clk => SB_CLK,
- cal_clk => cal_clk,
-
- -- MM interface
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
- ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- -- Datapath User interface (4 nodes)(4 input streams)
- tx_usr_siso_2arr => tx_usr_siso_2arr,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
-
- -- Mesh serial interface (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+
+ -- BLOCK GENERATOR
+ g_use_bg => c_use_bg,
+
+ -- MESH TERMINAL
+ -- System
+ g_node_type => c_node_type,
+ g_nof_bus => c_nof_bus,
+ -- User
+ g_usr_use_complex => c_usr_use_complex,
+ g_usr_data_w => c_usr_data_w,
+ g_usr_frame_len => c_usr_frame_len,
+ g_usr_nof_streams => c_usr_nof_streams,
+ -- Phy
+ g_phy_nof_serial => c_phy_nof_serial,
+ g_phy_gx_mbps => c_phy_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => c_phy_ena_reorder,
+ -- Tx
+ g_use_tx => c_use_tx,
+ g_tx_input_use_fifo => c_tx_input_use_fifo,
+ g_tx_input_fifo_size => c_tx_input_fifo_size,
+ g_tx_input_fifo_fill => c_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => c_use_rx,
+ g_rx_output_use_fifo => c_rx_output_use_fifo,
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => c_mon_select,
+ g_mon_nof_words => c_mon_nof_words,
+ g_mon_use_sync => c_mon_use_sync,
+ -- UTH
+ g_uth_len_max => c_uth_len_max,
+ g_uth_typ_ofs => c_uth_typ_ofs,
+
+ -- Auxiliary Interface
+ g_aux => c_unb1_board_aux,
+ -- BSN ALIGNER
+ g_use_bsn_align => c_use_bsn_align,
+ -- DATA BUFFER
+ g_use_data_buf => c_use_data_buf
+ )
+ port map(
+ -- System
+ chip_id => this_chip_id,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_clk,
+
+ -- MM interface
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ ram_mesh_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_mesh_diag_data_buf_miso => ram_mesh_diag_data_buf_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ -- Datapath User interface (4 nodes)(4 input streams)
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+
+ -- Mesh serial interface (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+ );
-----------------------------------------------------------------------------
-- Mesh I/O
@@ -454,23 +454,22 @@ begin
gen_tr_mesh : if c_use_phy.tr_mesh /= 0 generate
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
end generate;
-
end;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
index 4069b5616d5cc8fc41c9b8f6975c3b1cf71290bd..8dcf47793a7078a4ed413e662883a6eb96987512 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -28,12 +28,12 @@
-- > run 10 us
library IEEE, common_lib, unb1_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.tb_unb1_board_pkg.all;
entity tb_unb1_terminal_bg_mesh_db is
end tb_unb1_terminal_bg_mesh_db;
@@ -115,134 +115,134 @@ begin
------------------------------------------------------------------------------
gen_bn: for BN in 0 to c_nof_bn - 1 generate
u_bn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => (BN + 4)
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(BN + c_nof_fn),
- ETH_SGOUT => eth_txp(BN + c_nof_fn),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => (BN + 4)
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(BN + 4, c_unb1_board_aux.id_w), -- BN chip ID 4,5,6,7
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(BN + c_nof_fn),
+ ETH_SGOUT => eth_txp(BN + c_nof_fn),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_TX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_RX_arr(BN + c_nof_fn)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
- rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
- FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
- FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
- FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
- FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
- FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
- FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
- FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => bn_in_mesh_serial_3arr(BN),
+ rx_serial_2arr => bn_out_mesh_serial_3arr(BN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(BN + c_nof_fn),
+ FN_BN_0_RX => FN_BN_0_TX_arr(BN + c_nof_fn),
+ FN_BN_1_TX => FN_BN_1_RX_arr(BN + c_nof_fn),
+ FN_BN_1_RX => FN_BN_1_TX_arr(BN + c_nof_fn),
+ FN_BN_2_TX => FN_BN_2_RX_arr(BN + c_nof_fn),
+ FN_BN_2_RX => FN_BN_2_TX_arr(BN + c_nof_fn),
+ FN_BN_3_TX => FN_BN_3_RX_arr(BN + c_nof_fn),
+ FN_BN_3_RX => FN_BN_3_TX_arr(BN + c_nof_fn)
+ );
end generate;
gen_fn: for FN in 0 to c_nof_fn - 1 generate
u_fn : entity work.unb1_terminal_bg_mesh_db
- generic map (
- -- General
- g_sim => c_sim,
- g_sim_level => c_sim_level,
- g_sim_unb_nr => c_sim_unb_nr,
- g_sim_node_nr => FN
- )
- port map (
- -- GENERAL
- WDI => WDI,
- CLK => ext_clk,
- PPS => ext_pps,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
- ETH_SGIN => eth_rxp(FN),
- ETH_SGOUT => eth_txp(FN),
-
- -- Transceiver clocks
- SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
-
- -- Mesh serial I/O
- FN_BN_0_TX => FN_BN_0_TX_arr(FN),
- FN_BN_0_RX => FN_BN_0_RX_arr(FN),
- FN_BN_1_TX => FN_BN_1_TX_arr(FN),
- FN_BN_1_RX => FN_BN_1_RX_arr(FN),
- FN_BN_2_TX => FN_BN_2_TX_arr(FN),
- FN_BN_2_RX => FN_BN_2_RX_arr(FN),
- FN_BN_3_TX => FN_BN_3_TX_arr(FN),
- FN_BN_3_RX => FN_BN_3_RX_arr(FN)
- );
+ generic map (
+ -- General
+ g_sim => c_sim,
+ g_sim_level => c_sim_level,
+ g_sim_unb_nr => c_sim_unb_nr,
+ g_sim_node_nr => FN
+ )
+ port map (
+ -- GENERAL
+ WDI => WDI,
+ CLK => ext_clk,
+ PPS => ext_pps,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => TO_UVEC(FN, c_unb1_board_aux.id_w), -- FN chip ID 0,1,2,3,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk, -- ETH reference clock also used for system reference clock
+ ETH_SGIN => eth_rxp(FN),
+ ETH_SGOUT => eth_txp(FN),
+
+ -- Transceiver clocks
+ SB_CLK => tr_clk, -- TR clock FN-BN(mesh)
+
+ -- Mesh serial I/O
+ FN_BN_0_TX => FN_BN_0_TX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_RX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_TX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_RX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_TX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_RX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_TX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_RX_arr(FN)
+ );
-- Use mesh_io block to create 3arr format for the mesh model.
u_mesh_io : entity unb1_board_lib.unb1_board_mesh_io
- generic map (
- g_bus_w => c_unb1_board_tr_mesh.bus_w
- )
- port map (
- tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
- rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_RX_arr(FN),
- FN_BN_0_RX => FN_BN_0_TX_arr(FN),
- FN_BN_1_TX => FN_BN_1_RX_arr(FN),
- FN_BN_1_RX => FN_BN_1_TX_arr(FN),
- FN_BN_2_TX => FN_BN_2_RX_arr(FN),
- FN_BN_2_RX => FN_BN_2_TX_arr(FN),
- FN_BN_3_TX => FN_BN_3_RX_arr(FN),
- FN_BN_3_RX => FN_BN_3_TX_arr(FN)
- );
+ generic map (
+ g_bus_w => c_unb1_board_tr_mesh.bus_w
+ )
+ port map (
+ tx_serial_2arr => fn_in_mesh_serial_3arr(FN),
+ rx_serial_2arr => fn_out_mesh_serial_3arr(FN),
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_RX_arr(FN),
+ FN_BN_0_RX => FN_BN_0_TX_arr(FN),
+ FN_BN_1_TX => FN_BN_1_RX_arr(FN),
+ FN_BN_1_RX => FN_BN_1_TX_arr(FN),
+ FN_BN_2_TX => FN_BN_2_RX_arr(FN),
+ FN_BN_2_RX => FN_BN_2_TX_arr(FN),
+ FN_BN_3_TX => FN_BN_3_RX_arr(FN),
+ FN_BN_3_RX => FN_BN_3_TX_arr(FN)
+ );
end generate;
-- Direct interconnect BN0<->FN0.
@@ -254,18 +254,17 @@ begin
-- Mesh model
gen_mesh : if c_nof_bn > 1 or c_nof_fn > 1 generate
u_mesh_model_serial : entity unb1_board_lib.unb1_board_mesh_model_sl
- generic map(
- g_reorder => c_ena_mesh_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
- bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
- fn_rx_sl_3arr => fn_in_mesh_serial_3arr
- );
+ generic map(
+ g_reorder => c_ena_mesh_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_out_mesh_serial_3arr,
+ bn_rx_sl_3arr => bn_in_mesh_serial_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_out_mesh_serial_3arr,
+ fn_rx_sl_3arr => fn_in_mesh_serial_3arr
+ );
end generate;
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index e81056c6c6ca96cf753ae4d3907cf9546c9b5151..86f421d10ddd9507b40f3d3364307044574aafaf 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE is
end tb_unb1_test_10GbE;
@@ -32,9 +32,9 @@ end tb_unb1_test_10GbE;
architecture tb of tb_unb1_test_10GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index b0979cb122226b362df92eefb5f996545d98235f..ba739c6a8c504be6e043a7cccd6e59c7fd3ed388 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE is
generic (
@@ -92,64 +92,64 @@ end unb1_test_10GbE;
architecture str of unb1_test_10GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
index d5bd19a9c3283e8b1302638e11c1c0abae86ce6b..6086164b665da983eacf08de9919814010655a62 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_10GbE_tx_only is
end tb_unb1_test_10GbE_tx_only;
@@ -32,9 +32,9 @@ end tb_unb1_test_10GbE_tx_only;
architecture tb of tb_unb1_test_10GbE_tx_only is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_10GbE_tx_only",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_10GbE_tx_only",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index 3043972db629a52b6dfa4e96c2b9864da10aad4b..7f08e40e553eb6693ee5ddba22175da844d33a18 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_10GbE_tx_only is
generic (
@@ -84,55 +84,55 @@ end unb1_test_10GbE_tx_only;
architecture str of unb1_test_10GbE_tx_only is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index c56b4f415af6b3b865a88031151e7d205b25a345..a7f611f4d00796b68fa800f97bb630dcfbf8ba25 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_1GbE is
end tb_unb1_test_1GbE;
@@ -32,9 +32,9 @@ end tb_unb1_test_1GbE;
architecture tb of tb_unb1_test_1GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_1GbE",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_1GbE",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index 4ce67372f9f115a50cea341e785b020925f39eac..34e5900286675a4c1109a08eb10a3f29904d102e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity unb1_test_1GbE is
generic (
@@ -64,36 +64,36 @@ end unb1_test_1GbE;
architecture str of unb1_test_1GbE is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index c5dc616e081843f7d741d75432356777dfec2b9b..96328fc53d7c67589c02544086aa127bdc39309e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_all is
end tb_unb1_test_all;
@@ -32,9 +32,9 @@ end tb_unb1_test_all;
architecture tb of tb_unb1_test_all is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_all",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_all",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index d17bc71fa1fbc013fdfabeb004a906d400dbeb87..10748b84a64565af33aca09c539c240fb27a8519 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_all is
generic (
@@ -103,72 +103,72 @@ end unb1_test_all;
architecture str of unb1_test_all is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
+ BN_BI_0_TX => BN_BI_0_TX,
+ BN_BI_0_RX => BN_BI_0_RX,
+ BN_BI_1_TX => BN_BI_1_TX,
+ BN_BI_1_RX => BN_BI_1_RX,
+ BN_BI_2_TX => BN_BI_2_TX,
+ BN_BI_2_RX => BN_BI_2_RX,
+ BN_BI_3_TX => BN_BI_3_TX,
+ BN_BI_3_RX => BN_BI_3_RX,
+
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 969c0768bd86ee7176b7cc6d416635f8877f0eeb..877558e130393cf6a5c7c4a0c99d675038fb105b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr is
end tb_unb1_test_ddr;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr;
architecture tb of tb_unb1_test_ddr is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index df41e0d91aa2d46276cfdedd4fe24ed6c6f178dd..c59916401d75f1716164b98d3aed0739b5d10f48 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr is
generic (
@@ -70,44 +70,44 @@ end unb1_test_ddr;
architecture str of unb1_test_ddr is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
--- MB_II_IN => MB_II_IN,
--- MB_II_IO => MB_II_IO,
--- MB_II_OU => MB_II_OU
- );
+ -- MB_II_IN => MB_II_IN,
+ -- MB_II_IO => MB_II_IO,
+ -- MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
index 3dac8535f14e5439141cc3f0b2c24c215e38af24..d506dbc63d71f861688163ea55b1158f090d5404 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I is
end tb_unb1_test_ddr_16g_MB_I;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_I;
architecture tb of tb_unb1_test_ddr_16g_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 6f4ce8542b20eef5ee2826a2341f7f82603ee915..9804c3b49c21c44286f8b3eb393c83cdfcc549ae 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I is
generic (
@@ -70,41 +70,41 @@ end unb1_test_ddr_16g_MB_I;
architecture str of unb1_test_ddr_16g_MB_I is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
- );
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
index 51e1bc635bf8462d08ea93c8bbf96c7da5a43486..3a0dda9a63b4b12a0874acece098d1e673ca78ef 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_II is
end tb_unb1_test_ddr_16g_MB_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_II;
architecture tb of tb_unb1_test_ddr_16g_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index af5925eda507c7a76e0257690a9d885df47dcd9a..bb1795b5a73e59a71cb074c3f606bb51bcb39f21 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_II is
generic (
@@ -70,41 +70,41 @@ end unb1_test_ddr_16g_MB_II;
architecture str of unb1_test_ddr_16g_MB_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
index 29cb419b28d29b88ebc26bac8a44f34c3f0c40d6..c4020b9b5cd355e02a6ed5763b69916ac05b2797 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_16g_MB_I_II is
end tb_unb1_test_ddr_16g_MB_I_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_16g_MB_I_II;
architecture tb of tb_unb1_test_ddr_16g_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_16g_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_16g_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 8b8d0ee03e1c1620edc7073b57d164521b6a46de..a1c054a46b98b5c46c0feea770cb414b04c55ed3 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_16g_MB_I_II is
generic (
@@ -75,46 +75,46 @@ end unb1_test_ddr_16g_MB_I_II;
architecture str of unb1_test_ddr_16g_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
index 12ef1917691d1dd94bf1796d79807d0c7e2395c7..3fd67acfea479b3db6f499e622b99d56a13e9d75 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I is
end tb_unb1_test_ddr_MB_I;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_I;
architecture tb of tb_unb1_test_ddr_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
index dda6de35318a4df53541a3050cad7b0e003989ec..631e141bfe949ff91bff4ba15bc1388a753a6642 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_II is
end tb_unb1_test_ddr_MB_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_II;
architecture tb of tb_unb1_test_ddr_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 0 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 0 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
index c1f597d928df224812b1fc30abae65f8fe69fae1..c18c9608a325a1b8bb6a743068fbce1496f93f2f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
@@ -24,7 +24,7 @@
-- Description: see tb_unb1_test
library IEEE, unb1_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb1_test_ddr_MB_I_II is
end tb_unb1_test_ddr_MB_I_II;
@@ -32,9 +32,9 @@ end tb_unb1_test_ddr_MB_I_II;
architecture tb of tb_unb1_test_ddr_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
- generic map (
- g_design_name => "unb1_test_ddr_MB_I_II",
- --g_sim_node_nr => 7 -- BN3
- g_sim_node_nr => 1 -- FN0
- );
+ generic map (
+ g_design_name => "unb1_test_ddr_MB_I_II",
+ --g_sim_node_nr => 7 -- BN3
+ g_sim_node_nr => 1 -- FN0
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index f5524185b2b14002e0a574f0c58d1e38e60e3e3c..9eead96dc43b4a36669eb5cf61fdf035b6363dbc 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb1_test_ddr_MB_I_II is
generic (
@@ -75,46 +75,46 @@ end unb1_test_ddr_MB_I_II;
architecture str of unb1_test_ddr_MB_I_II is
begin
u_revision : entity unb1_test_lib.unb1_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU
- );
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 7e468fa82dd68c100cdca0d5f9bdb6d5d6a42c56..03a00769e82aef1afbef654b2909e076fb4d132b 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb1_test_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb1_test_pkg.all;
+ use work.unb1_test_pkg.all;
entity mmm_unb1_test is
generic (
@@ -242,7 +242,7 @@ architecture str of mmm_unb1_test is
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -258,103 +258,165 @@ begin
gen_mm_file_io : if g_sim = true generate
eth1g_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
-
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
-
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
- u_mm_file_reg_dp_offload_tx_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
- u_mm_file_reg_dp_offload_tx_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
-
- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
- u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
-
- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
- u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
- port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-
- u_mm_file_eth1g_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_eth1g_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
- port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
- u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
- port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
-
- u_mm_file_reg_tr_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
-
- u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
- port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
+
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ u_mm_file_reg_dp_offload_tx_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+
+ u_mm_file_reg_dp_offload_tx_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_mosi, reg_dp_offload_tx_10GbE_miso);
+
+ u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_dp_offload_tx_10GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_10GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_tx_10GbE_hdr_dat_mosi, reg_dp_offload_tx_10GbE_hdr_dat_miso);
+
+ u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
+
+ u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
+ port map(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
+
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
+
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_eth1g_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+
+ u_mm_file_eth1g_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_RAM")
+ port map(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+
+ u_mm_file_eth1g_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
+ port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+
+ u_mm_file_reg_tr_10GbE : mm_file -- , c_mm_clk_period, FALSE, 0)
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
+
+ u_mm_file_reg_tr_xaui : mm_file -- , c_mm_clk_period, FALSE, 0)
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
+ port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -379,10 +441,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -796,7 +858,6 @@ begin
ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 3c257fae3c3952152f5c7f2c4966ff5fd449cf8c..97e831ec1145e03c53627ecba724bea8f8544b5c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -20,340 +20,339 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb1_test_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb1_test is
- port (
- coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
- coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
- coe_reset_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_reg_wdi : out std_logic; -- export
- coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_clk_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
- coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
- coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_read_export_from_the_reg_wdi : out std_logic; -- export
- coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
- coe_clk_export_from_the_pio_pps : out std_logic; -- export
- coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_pio_system_info : out std_logic; -- export
- coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
- coe_write_export_from_the_pio_pps : out std_logic; -- export
- coe_write_export_from_the_rom_system_info : out std_logic; -- export
- coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_read_export_from_the_rom_system_info : out std_logic; -- export
- coe_reset_export_from_the_reg_epcs : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- clk_0 : in std_logic := 'X'; -- clk
- coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
- coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
- coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
- coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
- coe_reset_export_from_the_pio_system_info : out std_logic; -- export
- coe_read_export_from_the_pio_system_info : out std_logic; -- export
- coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_clk_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_epcs : out std_logic; -- export
- coe_write_export_from_the_reg_remu : out std_logic; -- export
- coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
- out_port_from_the_pio_wdi : out std_logic; -- export
- coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_clk_export_from_the_reg_remu : out std_logic; -- export
- coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
- coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
- coe_write_export_from_the_reg_epcs : out std_logic; -- export
- coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
- coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_wdi : out std_logic; -- export
- coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
- coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_read_export_from_the_pio_pps : out std_logic; -- export
- coe_clk_export_from_the_pio_system_info : out std_logic; -- export
- coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
- coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
- coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
- coe_reset_export_from_the_rom_system_info : out std_logic; -- export
- coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
- coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
- coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
- coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
- coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
- coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
- coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
- coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
- coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
- coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
- coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
- coe_read_export_from_the_reg_remu : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
- reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb1_test;
-
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb1_test is
+ port (
+ coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_address_export_from_the_pio_system_info : out std_logic_vector(4 downto 0); -- export
+ coe_address_export_from_the_pio_pps : out std_logic_vector(0 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_10GbE : in std_logic := 'X'; -- export
+ coe_reset_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_reg_epcs : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_pio_pps : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_pio_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_reset_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_tse_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_tr_xaui : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_reg_wdi : out std_logic; -- export
+ coe_readdata_export_to_the_reg_dpmm_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_mmdp_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_clk_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_write_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_clk_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_unb_sens : out std_logic; -- export
+ coe_reg_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_tr_xaui : out std_logic_vector(10 downto 0); -- export
+ coe_readdata_export_to_the_reg_dpmm_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_read_export_from_the_reg_wdi : out std_logic; -- export
+ coe_reg_write_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_mmdp_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_reg_remu : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_readdata_export_to_the_reg_unb_sens : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_waitrequest_export_to_the_reg_tr_xaui : in std_logic := 'X'; -- export
+ coe_clk_export_from_the_pio_pps : out std_logic; -- export
+ coe_readdata_export_to_the_pio_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_rom_system_info : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_dpmm_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_tr_10GbE : out std_logic_vector(14 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_wdi : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_pio_system_info : out std_logic; -- export
+ coe_tse_address_export_from_the_avs_eth_0 : out std_logic_vector(9 downto 0); -- export
+ coe_write_export_from_the_pio_pps : out std_logic; -- export
+ coe_write_export_from_the_rom_system_info : out std_logic; -- export
+ coe_irq_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_read_export_from_the_rom_system_info : out std_logic; -- export
+ coe_reset_export_from_the_reg_epcs : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ coe_tse_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_clk_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_ram_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_tse_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ clk_0 : in std_logic := 'X'; -- clk
+ coe_read_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_tr_xaui : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_writedata_export_from_the_reg_remu : out std_logic_vector(31 downto 0); -- export
+ coe_write_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_unb_sens : out std_logic_vector(31 downto 0); -- export
+ coe_writedata_export_from_the_reg_tr_10GbE : out std_logic_vector(31 downto 0); -- export
+ coe_reg_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_tse_read_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_data : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_writedata_export_from_the_reg_wdi : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export_from_the_pio_system_info : out std_logic; -- export
+ coe_read_export_from_the_pio_system_info : out std_logic; -- export
+ coe_clk_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_epcs : out std_logic; -- export
+ coe_write_export_from_the_reg_remu : out std_logic; -- export
+ coe_ram_readdata_export_to_the_avs_eth_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_writedata_export_from_the_reg_epcs : out std_logic_vector(31 downto 0); -- export
+ out_port_from_the_pio_wdi : out std_logic; -- export
+ coe_reset_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_clk_export_from_the_reg_remu : out std_logic; -- export
+ coe_read_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_clk_export_from_the_avs_eth_0 : out std_logic; -- export
+ coe_address_export_from_the_reg_mmdp_ctrl : out std_logic_vector(0 downto 0); -- export
+ coe_write_export_from_the_reg_epcs : out std_logic; -- export
+ coe_readdata_export_to_the_rom_system_info : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reset_export_from_the_reg_mmdp_ctrl : out std_logic; -- export
+ coe_readdata_export_to_the_reg_mmdp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_wdi : out std_logic; -- export
+ coe_clk_export_from_the_reg_tr_xaui : out std_logic; -- export
+ coe_readdata_export_to_the_reg_wdi : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_read_export_from_the_pio_pps : out std_logic; -- export
+ coe_clk_export_from_the_pio_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_pio_pps : out std_logic_vector(31 downto 0); -- export
+ coe_address_export_from_the_reg_epcs : out std_logic_vector(2 downto 0); -- export
+ coe_read_export_from_the_reg_dpmm_data : out std_logic; -- export
+ coe_reset_export_from_the_rom_system_info : out std_logic; -- export
+ coe_writedata_export_from_the_reg_dpmm_ctrl : out std_logic_vector(31 downto 0); -- export
+ coe_tse_waitrequest_export_to_the_avs_eth_0 : in std_logic := 'X'; -- export
+ coe_address_export_from_the_reg_mmdp_data : out std_logic_vector(0 downto 0); -- export
+ coe_address_export_from_the_reg_unb_sens : out std_logic_vector(2 downto 0); -- export
+ coe_address_export_from_the_rom_system_info : out std_logic_vector(9 downto 0); -- export
+ coe_clk_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reg_address_export_from_the_avs_eth_0 : out std_logic_vector(3 downto 0); -- export
+ coe_write_export_from_the_reg_mmdp_data : out std_logic; -- export
+ coe_address_export_from_the_reg_remu : out std_logic_vector(2 downto 0); -- export
+ coe_readdata_export_to_the_reg_tr_10GbE : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_write_export_from_the_reg_dpmm_ctrl : out std_logic; -- export
+ coe_reset_export_from_the_reg_tr_10GbE : out std_logic; -- export
+ coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
+ coe_read_export_from_the_reg_remu : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb1_test;
end qsys_unb1_test_pkg;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index 2d696a1218f996dd3a87688ac3367ed18405558d..f5b18dc26c7faba51af03d42eaab9d4cb634fac5 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -21,18 +21,18 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb1_test_pkg.all;
entity udp_stream is
generic (
@@ -100,14 +100,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable (disabled by default)
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" & "111011111100" & "0001" & "101111111";
constant c_nof_crc_words : natural := 1;
@@ -149,124 +150,124 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
--- reg_mosi => reg_dp_offload_tx_mosi,
--- reg_miso => reg_dp_offload_tx_miso,
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ -- reg_mosi => reg_dp_offload_tx_mosi,
+ -- reg_miso => reg_dp_offload_tx_miso,
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -287,50 +288,50 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 428faa733ef9d0cd312c91c357cf64025323e96e..799c0e8a629340be8e9218aa8e1747d7e9925729 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -21,21 +21,21 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb1_test_pkg.all;
entity unb1_test is
generic (
@@ -115,20 +115,21 @@ architecture str of unb1_test is
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 2);
- -- Select the according revision record based on the design name.
+ -- Select the according revision record based on the design name.
constant c_revision_select : t_unb1_test_config := func_unb1_test_sel_revision_rec(g_design_name);
-- ddr
constant c_nof_MB : natural := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- constant c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
- c_revision_select.use_front, 0,
- c_revision_select.use_back,
- c_revision_select.use_ddr_MB_I,
- c_revision_select.use_ddr_MB_II,
- 0,
- 1);
+ constant c_use_phy : t_c_unb1_board_use_phy := (
+ sel_a_b(c_revision_select.use_streaming_1GbE, 1, 0),
+ c_revision_select.use_front, 0,
+ c_revision_select.use_back,
+ c_revision_select.use_ddr_MB_I,
+ c_revision_select.use_ddr_MB_II,
+ 0,
+ 1);
constant c_nof_streams_10GbE : natural := c_revision_select.use_nof_streams_10GbE;
constant c_nof_streams_1GbE : natural := c_revision_select.use_nof_streams_1GbE;
@@ -334,7 +335,7 @@ architecture str of unb1_test is
signal reg_io_ddr_MB_II_mosi : t_mem_mosi;
signal reg_io_ddr_MB_II_miso : t_mem_miso;
- -- DDR3 pass on termination control from master to slave controller
+ -- DDR3 pass on termination control from master to slave controller
signal term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
signal term_ctrl_in : t_tech_ddr3_phy_terminationcontrol;
@@ -344,412 +345,412 @@ architecture str of unb1_test is
signal MB_II_ctlr_rst : std_logic;
begin
u_areset_ddr_ref_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 40
- )
- port map(
- clk => CLK,
- in_rst => mm_rst,
- out_rst => ddr_ref_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 40
+ )
+ port map(
+ clk => CLK,
+ in_rst => mm_rst,
+ out_rst => ddr_ref_rst
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_udp_offload => c_revision_select.use_streaming_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_rec_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
--- END GENERATE;
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_125M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_udp_offload => c_revision_select.use_streaming_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_rec_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_1GbE_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_1GbE_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_1GbE_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+ -- END GENERATE;
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb1_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams_1GbE => c_nof_streams_1GbE,
- g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
- g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
- g_bg_block_size => c_bg_block_size
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-
- -- dp_offload_rx
- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- tr_10GbE
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
-
- -- DDR3 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
-
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
-
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR3 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
-
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
-
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams_1GbE => c_nof_streams_1GbE,
+ g_nof_streams_10GbE => 3, -- c_nof_streams_10GbE,
+ g_nof_streams_ddr => 1, -- c_nof_streams_ddr,
+ g_bg_block_size => c_bg_block_size
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+ reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_tx_10GbE_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_10GbE_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_10GbE_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_10GbE_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
-- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+
+ reg_dp_offload_rx_10GbE_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_10GbE_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- tr_10GbE
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+
+ -- DDR3 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR3 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
gen_udp_stream_10GbE : if c_revision_select.use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_10GbE,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_def_10GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen mm
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
- reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
- reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- dp_offload_rx
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- -- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_streams => c_nof_streams_10GbE,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_def_10GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen mm
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- dp_offload_tx
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_10GbE_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_10GbE_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_10GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- dp_offload_rx
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_10GbE_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_10GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
@@ -757,62 +758,62 @@ begin
-----------------------------------------------------------------------------
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
gen_tr_10GbE : if c_revision_select.use_10GbE = true generate
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_streams_10GbE,
- g_use_mdio => true,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => i_xaui_tx_arr,
- xaui_rx_arr => i_xaui_rx_arr,
-
- -- MDIO External clock and serial data.
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_streams_10GbE,
+ g_use_mdio => true,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ cal_rec_clk => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr,
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => i_xaui_tx_arr,
+ xaui_rx_arr => i_xaui_rx_arr,
+
+ -- MDIO External clock and serial data.
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-- Wire together different types
gen_wires: for i in 0 to c_nof_streams_10GbE-1 generate
@@ -821,158 +822,157 @@ begin
end generate;
gen_tr_front : if c_revision_select.use_front = 1 generate
- u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_streams_10GbE
- )
- port map (
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ u_front_io : entity unb1_board_lib.unb1_board_front_io
+ generic map (
+ g_nof_xaui => c_nof_streams_10GbE
+ )
+ port map (
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
end generate;
end generate;
-gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
- u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_I_ctlr_clk,
- ctlr_rst_out => MB_I_ctlr_rst,
-
- ctlr_clk_in => MB_I_ctlr_clk,
- ctlr_rst_in => MB_I_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_I_IN,
- phy3_io => MB_I_IO,
- phy3_ou => MB_I_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ gen_mms_io_ddr_diag_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
+ u_mms_io_ddr_diag_MB_I : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_I_ctlr_clk,
+ ctlr_rst_out => MB_I_ctlr_rst,
+
+ ctlr_clk_in => MB_I_ctlr_clk,
+ ctlr_rst_in => MB_I_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_I_IN,
+ phy3_io => MB_I_IO,
+ phy3_ou => MB_I_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
-gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
- u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
- generic map(
- -- System
- g_technology => g_technology,
- g_dp_data_w => c_data_w_64,
- g_dp_seq_dat_w => c_seq_dat_w,
- g_dp_wr_fifo_depth => c_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_revision_select.use_tech_ddr,
- -- DIAG data buffer
- g_db_use_db => c_use_db,
- g_db_buf_nof_data => c_buf_nof_data
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- DDR reference clock
- ctlr_ref_clk => CLK,
- ctlr_ref_rst => ddr_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => MB_II_ctlr_clk,
- ctlr_rst_out => MB_II_ctlr_rst,
-
- ctlr_clk_in => MB_II_ctlr_clk,
- ctlr_rst_in => MB_II_ctlr_rst,
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR3 pass on signals from master to slave controller
- term_ctrl_out => OPEN,
- term_ctrl_in => OPEN,
-
- -- DDR3 PHY external interface
- phy3_in => MB_II_IN,
- phy3_io => MB_II_IO,
- phy3_ou => MB_II_OU,
-
- -- DIAG Tx seq
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- -- DIAG rx seq with optional data buffer
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
+ u_mms_io_ddr_diag_MB_II : entity io_ddr_lib.mms_io_ddr_diag
+ generic map(
+ -- System
+ g_technology => g_technology,
+ g_dp_data_w => c_data_w_64,
+ g_dp_seq_dat_w => c_seq_dat_w,
+ g_dp_wr_fifo_depth => c_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_rd_fifo_depth,
+ -- IO_DDR
+ g_io_tech_ddr => c_revision_select.use_tech_ddr,
+ -- DIAG data buffer
+ g_db_use_db => c_use_db,
+ g_db_buf_nof_data => c_buf_nof_data
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- DDR reference clock
+ ctlr_ref_clk => CLK,
+ ctlr_ref_rst => ddr_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => MB_II_ctlr_clk,
+ ctlr_rst_out => MB_II_ctlr_rst,
+
+ ctlr_clk_in => MB_II_ctlr_clk,
+ ctlr_rst_in => MB_II_ctlr_rst,
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR3 pass on signals from master to slave controller
+ term_ctrl_out => OPEN,
+ term_ctrl_in => OPEN,
+
+ -- DDR3 PHY external interface
+ phy3_in => MB_II_IN,
+ phy3_io => MB_II_IO,
+ phy3_ou => MB_II_OU,
+
+ -- DIAG Tx seq
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ -- DIAG rx seq with optional data buffer
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index a1c4f5a3856ce1a8df548e1190e7af7fcedeb604..344c7de3e534bc9818cf8ee08e8647529509c89c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -20,61 +20,61 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb1_test_pkg is
type t_unb1_test_config is record
- use_front : natural;
- use_back : natural;
- use_streaming_1GbE : boolean;
- use_nof_streams_1GbE : natural;
- use_10GbE : boolean;
- use_nof_streams_10GbE : natural;
- use_ddr_MB_I : natural;
- use_ddr_MB_II : natural;
- use_nof_streams_ddr : natural;
- use_tech_ddr : t_c_tech_ddr;
- end record;
+ use_front : natural;
+ use_back : natural;
+ use_streaming_1GbE : boolean;
+ use_nof_streams_1GbE : natural;
+ use_10GbE : boolean;
+ use_nof_streams_10GbE : natural;
+ use_ddr_MB_I : natural;
+ use_ddr_MB_II : natural;
+ use_nof_streams_ddr : natural;
+ use_tech_ddr : t_c_tech_ddr;
+end record;
- -- dp_offload_tx
- constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
-
- -- Function to select the revision configuration.
- function func_unb1_test_sel_revision_rec(g_design_name : string) return t_unb1_test_config;
+-- dp_offload_tx
+constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
+constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+-- Function to select the revision configuration.
+function func_unb1_test_sel_revision_rec(g_design_name : string) return t_unb1_test_config;
end unb1_test_pkg;
package body unb1_test_pkg is
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index fd3eea1c8906c14b0f5954900da4ffd3b0059732..0cd5280da33d47254e045e5512b0deb5bdc09b2a 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -45,21 +45,21 @@
library ip_stratixiv_ddr3_mem_model_lib;
library IEEE, common_lib, unb1_board_lib, i2c_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
-use work.unb1_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
+ use work.unb1_test_pkg.all;
entity tb_unb1_test is
- generic (
- g_design_name : string := "unb1_test";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 7 -- Back node 3
- );
+ generic (
+ g_design_name : string := "unb1_test";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 7 -- Back node 3
+ );
end tb_unb1_test;
architecture tb of tb_unb1_test is
@@ -218,14 +218,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_I : if c_revision_select.use_ddr_MB_I = 1 generate
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_I_ou,
- mem3_io => phy_MB_I_io,
- mem3_ou => phy_MB_I_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_I_ou,
+ mem3_io => phy_MB_I_io,
+ mem3_ou => phy_MB_I_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -233,14 +233,14 @@ begin
------------------------------------------------------------------------------
gen_tech_ddr_memory_model_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_revision_select.use_tech_ddr
- )
- port map (
- mem3_in => phy_MB_II_ou,
- mem3_io => phy_MB_II_io,
- mem3_ou => phy_MB_II_in
- );
+ generic map (
+ g_tech_ddr => c_revision_select.use_tech_ddr
+ )
+ port map (
+ mem3_in => phy_MB_II_ou,
+ mem3_io => phy_MB_II_io,
+ mem3_ou => phy_MB_II_in
+ );
end generate;
------------------------------------------------------------------------------
@@ -248,36 +248,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
index 2a79752d439f79bbff34789cd312d69bab8def26..59a395c9b90e3de084eb79aaf685fffef8e23ff8 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
@@ -20,23 +20,23 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity mmm_unb1_tr_10GbE is
generic (
@@ -252,7 +252,7 @@ begin
mm_rst_n <= not(mm_rst);
u_qsys_unb1_tr_10GbE : qsys_unb1_tr_10GbE
- port map(
+ port map(
clk_in_clk => mm_clk,
eth1g_irq_export => eth1g_reg_interrupt,
eth1g_mm_clk_export => OPEN,
@@ -385,5 +385,4 @@ begin
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index 289839f6e9daa2b3af18e6de67b6f92ae6593bd0..8f63e9a99933baf0beb9d31c2a7f22e59dbf86c0 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb1_board_lib, diag_lib, dp_lib, eth_lib, tech_tse_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
-- Purpose:
@@ -86,7 +86,7 @@ entity unb1_tr_10GbE is
SI_FN_2_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_3_CNTRL : inout std_logic_vector(c_unb1_board_ci.tr.cntrl_w - 1 downto 0);
SI_FN_RSTN : out std_logic := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
- -- So we need to assign a '1' to it.
+ -- So we need to assign a '1' to it.
);
end unb1_tr_10GbE;
@@ -98,14 +98,15 @@ architecture str of unb1_tr_10GbE is
constant c_bg_block_size : natural := 176;
constant c_bg_gapsize : natural := 256 - 176;
constant c_bg_blocks_per_sync : natural := 100;
- constant c_bg_ctrl : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable: On by default in simulation; MM enable required on hardware.
+ sel_a_b(g_sim, '1', '0'),
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- System
signal cs_sim : std_logic;
signal xo_clk : std_logic;
@@ -194,25 +195,25 @@ begin
-- TX: 3 Block generators
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_10GbE_streams,
- g_buf_dat_w => 64,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/composite_signals",
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
-
- out_sosi_arr => mms_diag_block_gen_src_out_arr
- );
+ generic map (
+ g_nof_streams => c_nof_10GbE_streams,
+ g_buf_dat_w => 64,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/composite_signals",
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+
+ out_sosi_arr => mms_diag_block_gen_src_out_arr
+ );
-----------------------------------------------------------------------------
-- 10GbE TX/RX
@@ -224,294 +225,294 @@ begin
end generate;
u_front_io : entity unb1_board_lib.unb1_board_front_io
- generic map (
- g_nof_xaui => c_nof_10GbE_streams
- )
- port map (
- xaui_tx_arr => unb_xaui_tx_arr,
- xaui_rx_arr => unb_xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
+ generic map (
+ g_nof_xaui => c_nof_10GbE_streams
+ )
+ port map (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
u_areset_sa_rst : entity common_lib.common_areset
- generic map(
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
+ generic map(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
- generic map(
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_streams,
- g_use_mdio => true
- )
- port map (
- -- Transceiver PLL reference clock
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- -- Calibration & reconfig clock
- cal_rec_clk => mm_clk,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
- mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_snk_in_arr,
- src_in_arr => dp_offload_rx_snk_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- -- MDIO interface
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
+ generic map(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => true
+ )
+ port map (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams - 1 downto 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams - 1 downto 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
--- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
--- GENERIC MAP (
--- g_nof_streams => c_nof_10GbE_streams,
--- g_data_w => c_xgmii_data_w,
--- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
--- g_remove_crc => FALSE,
--- g_crc_nof_words => 0
--- )
--- PORT MAP (
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
---
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
--- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
---
--- snk_in_arr => dp_offload_rx_snk_in_arr,
--- snk_out_arr => dp_offload_rx_snk_out_arr,
---
--- src_out_arr => dp_offload_rx_src_out_arr,
--- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
---
--- hdr_fields_out_arr => hdr_fields_out_arr
--- );
---
--- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
--- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
--- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
---
--- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
--- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
--- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
--- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
--- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
--- END GENERATE;
+ -- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ -- GENERIC MAP (
+ -- g_nof_streams => c_nof_10GbE_streams,
+ -- g_data_w => c_xgmii_data_w,
+ -- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ -- g_remove_crc => FALSE,
+ -- g_crc_nof_words => 0
+ -- )
+ -- PORT MAP (
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ --
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ -- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ --
+ -- snk_in_arr => dp_offload_rx_snk_in_arr,
+ -- snk_out_arr => dp_offload_rx_snk_out_arr,
+ --
+ -- src_out_arr => dp_offload_rx_src_out_arr,
+ -- src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
+ --
+ -- hdr_fields_out_arr => hdr_fields_out_arr
+ -- );
+ --
+ -- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ -- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
+ -- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+ --
+ -- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ -- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ -- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ -- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ -- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ -- END GENERATE;
-----------------------------------------------------------------------------
-- RX: BSN monitors at several stages in the stream
-----------------------------------------------------------------------------
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 5,
- g_sync_timeout => 200000000,
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => dp_bsn_monitor_in_siso_arr,
- in_sosi_arr => dp_bsn_monitor_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => 5,
+ g_sync_timeout => 200000000,
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => dp_bsn_monitor_in_siso_arr,
+ in_sosi_arr => dp_bsn_monitor_in_sosi_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_sim_flash_model => false,
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_use_phy => c_use_phy,
- g_aux => c_unb1_board_aux,
- g_dp_clk_use_pll => true,
- g_xo_clk_use_pll => true
- )
- port map (
- -- Clock and reset signals
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk_out => mm_clk,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_locked => mm_locked,
- mm_locked_out => mm_locked,
-
- epcs_clk => epcs_clk,
- epcs_clk_out => epcs_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- cal_rec_clk => cal_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_tse_clk_out => eth1g_tse_clk,
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- -- . 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_flash_model => false,
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_dp_clk_use_pll => true,
+ g_xo_clk_use_pll => true
+ )
+ port map (
+ -- Clock and reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_tr_10GbE : entity work.mmm_unb1_tr_10GbE
- generic map(
- g_sim => g_sim
- )
- port map(
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- pout_wdi => pout_wdi,
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
- reg_mdio_0_mosi => reg_mdio_0_mosi,
- reg_mdio_0_miso => reg_mdio_0_miso,
- reg_mdio_1_mosi => reg_mdio_1_mosi,
- reg_mdio_1_miso => reg_mdio_1_miso,
- reg_mdio_2_mosi => reg_mdio_2_mosi,
- reg_mdio_2_miso => reg_mdio_2_miso,
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso,
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso
- );
+ generic map(
+ g_sim => g_sim
+ )
+ port map(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+ reg_mdio_0_mosi => reg_mdio_0_mosi,
+ reg_mdio_0_miso => reg_mdio_0_miso,
+ reg_mdio_1_mosi => reg_mdio_1_mosi,
+ reg_mdio_1_miso => reg_mdio_1_miso,
+ reg_mdio_2_mosi => reg_mdio_2_mosi,
+ reg_mdio_2_miso => reg_mdio_2_miso,
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+ reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso
+ );
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
index 3c298d5e150f24bc44068be7a26b712e08eaa951..7290ead5630e7d7cde61ebc3faf76743de59d2c1 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
@@ -25,11 +25,11 @@
-- Usage:
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_tr_10GbE is
end tb_unb1_tr_10GbE;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index a26175ea386e55baf9e1192f275b4efe3d48cabb..73451c84e976f8cb1f820db616e575dac5525cc0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -26,17 +26,17 @@
-- . node_<design_name>.vhd with the actual functionality of <design_name>
library IEEE, common_lib, mm_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb1_board is
generic (
@@ -364,31 +364,31 @@ begin
gen_pll: if g_dp_clk_use_pll = true generate
u_unb1_board_clk200_pll : entity work.unb1_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_sel => c_dp_clk_pll_sel,
- g_clk200_phase_shift => g_dp_clk_phase,
- g_clk_vec_w => g_dp_phs_clk_vec_w,
- g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
- g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
- g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
- g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
- g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
- g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
- g_clk1_divide_by => g_dp_phs_clk_divide_by,
- g_clk2_divide_by => g_dp_phs_clk_divide_by,
- g_clk3_divide_by => g_dp_phs_clk_divide_by,
- g_clk4_divide_by => g_dp_phs_clk_divide_by,
- g_clk5_divide_by => g_dp_phs_clk_divide_by,
- g_clk6_divide_by => g_dp_phs_clk_divide_by
- )
- port map (
- arst => dp_dis,
- clk200 => ext_clk,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst,
- st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
- );
+ generic map (
+ g_technology => g_technology,
+ g_sel => c_dp_clk_pll_sel,
+ g_clk200_phase_shift => g_dp_clk_phase,
+ g_clk_vec_w => g_dp_phs_clk_vec_w,
+ g_clk1_phase_shift => c_dp_clk1_phase, -- dp_phs_clk_vec(0)
+ g_clk2_phase_shift => c_dp_clk2_phase, -- dp_phs_clk_vec(1)
+ g_clk3_phase_shift => c_dp_clk3_phase, -- dp_phs_clk_vec(2)
+ g_clk4_phase_shift => c_dp_clk4_phase, -- dp_phs_clk_vec(3)
+ g_clk5_phase_shift => c_dp_clk5_phase, -- dp_phs_clk_vec(4)
+ g_clk6_phase_shift => c_dp_clk6_phase, -- dp_phs_clk_vec(5)
+ g_clk1_divide_by => g_dp_phs_clk_divide_by,
+ g_clk2_divide_by => g_dp_phs_clk_divide_by,
+ g_clk3_divide_by => g_dp_phs_clk_divide_by,
+ g_clk4_divide_by => g_dp_phs_clk_divide_by,
+ g_clk5_divide_by => g_dp_phs_clk_divide_by,
+ g_clk6_divide_by => g_dp_phs_clk_divide_by
+ )
+ port map (
+ arst => dp_dis,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst,
+ st_clk_vec => dp_phs_clk_vec -- PLL c6-c1
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false and g_dp_clk_use_xo_pll = false generate
@@ -401,6 +401,7 @@ begin
-- for UNB1 designs with SOPC g_xo_clk_use_pll=FALSE and the the SOPC generates and outputs the mm_clk
-- for UNB1 designs with QSYS g_xo_clk_use_pll=TRUE and this ctrl_unb1_board generates and outputs the mm_clk
gen_clk25_pll: if g_xo_clk_use_pll = true generate
+
gen_sim : if g_sim = true generate
sim_mm_clk <= not sim_mm_clk after c_mmf_mm_clk_period / 2;
end generate;
@@ -408,7 +409,7 @@ begin
mm_clk_out <= sim_mm_clk when g_sim = true else
clk125M when g_mm_clk_freq = c_unb1_board_mm_clk_freq_125M else
clk50M when g_mm_clk_freq = c_unb1_board_mm_clk_freq_50M else
- clk50M;
+ clk50M;
gen_dp_clk : if g_dp_clk_use_xo_pll = true and g_dp_clk_use_pll = false generate
dp_clk <= clk200M;
@@ -418,74 +419,74 @@ begin
end generate;
u_unb1_board_clk25_pll : entity work.unb1_board_clk25_pll
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk25 => i_xo_clk,
+ c0_clk20 => clk20M,
+ c1_clk40 => clk40M,
+ c2_clk50 => clk50M,
+ c3_clk125 => clk125M,
+ c4_clk200 => clk200M,
+ pll_locked => mm_locked_out
+ );
+ end generate;
+
+ u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
generic map (
- g_technology => g_technology
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk25 => i_xo_clk,
- c0_clk20 => clk20M,
- c1_clk40 => clk40M,
- c2_clk50 => clk50M,
- c3_clk125 => clk125M,
- c4_clk200 => clk200M,
- pll_locked => mm_locked_out
+ xo_clk => i_xo_clk,
+ xo_rst_n => i_xo_rst_n,
+ sys_clk => mm_clk,
+ sys_locked => mm_locked,
+ sys_rst => i_mm_rst,
+ cal_clk => '0',
+ cal_rst => OPEN,
+ st_clk => node_ctrl_dp_clk_in,
+ st_rst => node_ctrl_dp_rst_out,
+ wdi_in => pout_wdi,
+ wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ pulse_us => OPEN,
+ pulse_ms => mm_pulse_ms,
+ pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => i_xo_clk,
- xo_rst_n => i_xo_rst_n,
- sys_clk => mm_clk,
- sys_locked => mm_locked,
- sys_rst => i_mm_rst,
- cal_clk => '0',
- cal_rst => OPEN,
- st_clk => node_ctrl_dp_clk_in,
- st_rst => node_ctrl_dp_rst_out,
- wdi_in => pout_wdi,
- wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- pulse_us => OPEN,
- pulse_ms => mm_pulse_ms,
- pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-- System info
cs_sim <= is_true(g_sim);
u_mms_unb1_board_system_info : entity work.mms_unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version,
- g_technology => g_technology
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -520,12 +521,12 @@ begin
led_toggle_green <= sel_a_b(g_design_name(1 to 8) /= "unb1_min", led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -536,15 +537,15 @@ begin
WDI <= sel_a_b(g_use_phy.wdi, mm_wdi or temp_alarm or wdi_override, 'Z');
u_unb1_board_wdi_reg : entity work.unb1_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -554,15 +555,15 @@ begin
-- and reconfigure from that address.
gen_mms_remu : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_remu : entity remu_lib.mms_remu
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
end generate;
no_remu_in_sim : if c_use_flash = false generate
@@ -574,31 +575,31 @@ begin
-----------------------------------------------------------------------------
gen_mms_epcs : if c_use_flash = true generate -- enable on HW, disable to save simulation time when not used in tb
u_mms_epcs : entity epcs_lib.mms_epcs
- generic map (
- g_sim_flash_model => g_sim_flash_model,
- g_protect_addr_range => g_epcs_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sim_flash_model => g_sim_flash_model,
+ g_protect_addr_range => g_epcs_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
end generate;
no_epcs_in_sim : if c_use_flash = false generate
@@ -612,45 +613,45 @@ begin
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => mms_ppsh_pps_sys
- );
+ generic map (
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => mms_ppsh_pps_sys
+ );
------------------------------------------------------------------------------
-- PPS delay
------------------------------------------------------------------------------
gen_mms_common_pulse_delay : if g_pps_delay_max > 0 generate
u_mms_common_pulse_delay : entity common_lib.mms_common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pps_delay_max,
- g_register_out => true
- )
- port map (
- pulse_clk => dp_clk_in,
- pulse_rst => dp_rst_in,
- pulse_in => mms_ppsh_pps_sys,
- pulse_out => dp_pps,
-
- mm_clk => mm_clk,
- mm_rst => i_mm_rst,
- reg_mosi => reg_common_pulse_delay_mosi,
- reg_miso => reg_common_pulse_delay_miso
- );
+ generic map (
+ g_pulse_delay_max => g_pps_delay_max,
+ g_register_out => true
+ )
+ port map (
+ pulse_clk => dp_clk_in,
+ pulse_rst => dp_rst_in,
+ pulse_in => mms_ppsh_pps_sys,
+ pulse_out => dp_pps,
+
+ mm_clk => mm_clk,
+ mm_rst => i_mm_rst,
+ reg_mosi => reg_common_pulse_delay_mosi,
+ reg_miso => reg_common_pulse_delay_miso
+ );
end generate;
no_mms_common_pulse_delay : if g_pps_delay_max = 0 generate
@@ -664,28 +665,28 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => sens_sc,
- sda => sens_sd,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => sens_sc,
+ sda => sens_sd,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -713,44 +714,43 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_mac : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_sim => g_sim,
- g_sim_level => g_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => mm_clk, -- use mm_clk direct
- eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => mm_clk, -- use mm_clk direct
+ eth_clk => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index b6754497a9df7b060f29f3a9e7857ec10a2b674a..a4d9f84fa369998ad22bd80b02d0f9c6712512dc 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb1_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb1_board_sens is
generic (
@@ -63,46 +63,46 @@ architecture str of mms_unb1_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb1_board_sens_reg : entity work.unb1_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both BN3 and all nodes implies that sens_err is only valid for BN3.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb1_board_sens : entity work.unb1_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index 35016608694c658dc4ba2234c6ee3f4855414ee9..9c9d7387b1a9c652ac3dc854e9e9a086ac541cbe 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb1_board_system_info is
generic (
@@ -59,7 +59,7 @@ entity mms_unb1_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb1_board_system_info;
architecture str of mms_unb1_board_system_info is
@@ -69,68 +69,69 @@ architecture str of mms_unb1_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
- signal i_info : std_logic_vector(c_word_w - 1 downto 0);
+ signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb1_board_system_info: entity work.unb1_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb1_board_system_info_reg: entity work.unb1_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_use_phy => g_use_phy,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_use_phy => g_use_phy,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index f7ddc510062859aa916d7f5743157ee601e5a717..a01f04a0fbcdf13efd1fb1111c393d66e1afeb71 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -123,13 +123,13 @@
-- advantage is that it
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
entity node_unb1_fn_terminal_db is
generic(
@@ -238,7 +238,7 @@ architecture str of node_unb1_fn_terminal_db is
signal rx_usr_siso_arr : t_dp_siso_arr(g_usr_nof_streams - 1 downto 0);
signal rx_usr_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
- -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
@@ -249,67 +249,67 @@ begin
-----------------------------------------------------------------------------
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- -- System
- g_node_type => e_fn,
- g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
- -- User
- g_usr_use_complex => true,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_block_len,
- g_usr_nof_streams => c_usr_nof_streams_per_bus,
- -- Phy
- g_phy_nof_serial => g_mesh_nof_serial,
- g_phy_gx_mbps => g_mesh_gx_mbps,
- g_phy_rx_fifo_size => c_phy_rx_fifo_size,
- g_phy_ena_reorder => g_mesh_ena_reorder,
- -- Tx
- g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
- g_tx_input_use_fifo => false, -- no user Tx
- -- Rx
- g_use_rx => true, -- user Rx must be TRUE for DB in FN,
- g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
- g_rx_output_fifo_size => c_rx_output_fifo_size,
- g_rx_output_fifo_fill => c_rx_output_fifo_fill,
- g_rx_timeout_w => c_rx_timeout_w,
- -- Monitoring
- g_mon_select => g_mesh_mon_select,
- g_mon_nof_words => g_mesh_mon_nof_words,
- g_mon_use_sync => g_mesh_mon_use_sync
- )
- port map (
- chip_id => chip_id,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_sync => dp_pps,
- tr_clk => tr_mesh_clk,
- cal_clk => cal_clk,
-
- -- User interface (4 nodes)(4 input streams)
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
-
- -- Mesh interface level (4 nodes)(4 lanes)
- -- . Serial (tr_nonbonded)
- tx_serial_2arr => tx_serial_2arr, -- Tx
- rx_serial_2arr => rx_serial_2arr, -- Rx
-
- -- MM Control
- -- . tr_nonbonded
- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
- reg_diagnostics_mosi => reg_diagnostics_mosi,
- reg_diagnostics_miso => reg_diagnostics_miso,
-
- -- . diag_data_buffer
- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => c_unb1_board_nof_bn, -- 4 to 4 nodes in mesh
+ -- User
+ g_usr_use_complex => true,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_block_len,
+ g_usr_nof_streams => c_usr_nof_streams_per_bus,
+ -- Phy
+ g_phy_nof_serial => g_mesh_nof_serial,
+ g_phy_gx_mbps => g_mesh_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => g_mesh_ena_reorder,
+ -- Tx
+ g_use_tx => g_mesh_use_tx, -- optionally do support diag Tx
+ g_tx_input_use_fifo => false, -- no user Tx
+ -- Rx
+ g_use_rx => true, -- user Rx must be TRUE for DB in FN,
+ g_rx_output_use_fifo => true, -- Rx output provides FIFOs to ensure that dp_distribute does not get blocked due to substantial backpressure on another output
+ g_rx_output_fifo_size => c_rx_output_fifo_size,
+ g_rx_output_fifo_fill => c_rx_output_fifo_fill,
+ g_rx_timeout_w => c_rx_timeout_w,
+ -- Monitoring
+ g_mon_select => g_mesh_mon_select,
+ g_mon_nof_words => g_mesh_mon_nof_words,
+ g_mon_use_sync => g_mesh_mon_use_sync
+ )
+ port map (
+ chip_id => chip_id,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => tr_mesh_clk,
+ cal_clk => cal_clk,
+
+ -- User interface (4 nodes)(4 input streams)
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr, -- Rx (user Tx from FN to BN is unused)
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ -- . Serial (tr_nonbonded)
+ tx_serial_2arr => tx_serial_2arr, -- Tx
+ rx_serial_2arr => rx_serial_2arr, -- Rx
+
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ -- . diag_data_buffer
+ ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
---------------------------------------------------------------------------------------
-- Forward the received streams, rewire for single or multi UniBoard use
@@ -328,6 +328,7 @@ begin
-- From 2d to 1d array
---------------------------------------------------------------------------------------
gen_i : for I in 0 to c_unb1_board_nof_bn - 1 generate
+
gen_j : for J in 0 to c_usr_nof_streams_per_bus - 1 generate
rx_rew_siso_2arr(I)(J) <= rx_usr_siso_arr(I * c_usr_nof_streams_per_bus + J);
rx_usr_sosi_arr(I * c_usr_nof_streams_per_bus + J) <= rx_rew_sosi_2arr(I)(J);
@@ -345,51 +346,51 @@ begin
gen_align : if g_use_bsn_align = true generate
u_bsn_align : entity dp_lib.dp_bsn_align
- generic map (
- g_block_size => g_usr_block_len,
- g_nof_input => g_usr_nof_streams,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => c_burst_bsn_latency,
- g_bsn_request_pipeline => c_bsn_request_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => rx_usr_siso_arr,
- snk_in_arr => rx_usr_sosi_arr,
- -- ST source
- src_in_arr => dp_out_siso_arr,
- src_out_arr => db_in_sosi_arr,
- -- MM
- in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
- in_en_arr => (others => '1') -- default all user inputs are enabled
- );
+ generic map (
+ g_block_size => g_usr_block_len,
+ g_nof_input => g_usr_nof_streams,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => c_burst_bsn_latency,
+ g_bsn_request_pipeline => c_bsn_request_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => rx_usr_siso_arr,
+ snk_in_arr => rx_usr_sosi_arr,
+ -- ST source
+ src_in_arr => dp_out_siso_arr,
+ src_out_arr => db_in_sosi_arr,
+ -- MM
+ in_en_evt => '0', -- pulse '1' indicates that the in_en_arr user input enables have been updated
+ in_en_arr => (others => '1') -- default all user inputs are enabled
+ );
u_bsn_monitor_align : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
- g_cross_clock_domain => true,
- g_sync_timeout => g_mesh_sync_timeout,
- g_bsn_w => c_dp_stream_bsn_w,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_log_first_bsn => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => (others => c_dp_siso_rdy),
- in_sosi_arr => db_in_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- All streams are synchronous. Only monitor stream(0).
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_mesh_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_log_first_bsn => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => (others => c_dp_siso_rdy),
+ in_sosi_arr => db_in_sosi_arr(0 downto 0)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -402,27 +403,27 @@ begin
gen_data_buf : if g_use_data_buf = true generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => g_usr_nof_streams,
- g_data_w => g_usr_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => db_in_sosi_arr(0).sync,
- in_sosi_arr => db_in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_usr_nof_streams,
+ g_data_w => g_usr_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => db_in_sosi_arr(0).sync,
+ in_sosi_arr => db_in_sosi_arr
+ );
end generate;
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index b3e77264270a51387859a01866e22ff72c27713a..62a048e5316065e12a1bfea0c4ccd53441a64a06 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_io is
generic (
@@ -59,5 +59,4 @@ begin
rx_serial_2arr(2)(I) <= BN_BI_2_RX(I);
rx_serial_2arr(3)(I) <= BN_BI_3_RX(I);
end generate;
-
end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index 8f32540b83c6c94ebffbfd2b5b331a084ff6851e..8624fee3d23e1c089c51466124bc2036a52ac3ca 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -53,11 +53,11 @@
-- . See unb1_board_back_model_sl.vhd for the Apertif backplane model
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_reorder is
port (
@@ -96,69 +96,69 @@ begin
-- Map the usr busses for the other UniBoards to the phy busses 2:0
case TO_UINT(bck_id) is
when 0 =>
- -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 0 connects to UniBoards 3,2,1 via phy busses 0,2,1
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 1 =>
- -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
+ -- UniBoard 1 connects to UniBoards 3,2,0 via phy busses 0,1,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1); -- from unb 2
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(2);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0); -- from unb 3
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(3);
when 2 =>
- -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
- tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
+ -- UniBoard 2 connects to UniBoards 3,1,0 via phy busses 1,0,2
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(2); -- from unb 0
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(0); -- from unb 1
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(3); -- to unb 3
+ tx_usr_siso_2arr(3) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(1); -- from unb 3
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(3);
when 3 =>
- -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
- tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
- tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
- rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
- rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
-
- tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
- tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
- rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
- rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
-
- tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
- tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
- rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
- rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
+ -- UniBoard 3 connects to UniBoards 2,1,0 via phy busses 2,1,0
+ tx_phy_sosi_2arr(0) <= tx_usr_sosi_2arr(0); -- to unb 0
+ tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(0);
+ rx_usr_sosi_2arr(0) <= rx_phy_sosi_2arr(0); -- from unb 0
+ rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(0);
+
+ tx_phy_sosi_2arr(1) <= tx_usr_sosi_2arr(1); -- to unb 1
+ tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(1);
+ rx_usr_sosi_2arr(1) <= rx_phy_sosi_2arr(1); -- from unb 1
+ rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(1);
+
+ tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(2); -- to unb 2
+ tx_usr_siso_2arr(2) <= tx_phy_siso_2arr(2);
+ rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(2); -- from unb 2
+ rx_phy_siso_2arr(2) <= rx_usr_siso_2arr(2);
when others => null;
end case;
end process;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
index 6aaadd11ea1fcea8cb001f040fb40ce135024ca9..f0c0dccc40cd7d50a40adca8a5339b24a0b17e96 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -36,11 +36,11 @@
-- are ignored.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_back_select is
port (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index 1ee7f136478cfb001d46ccc8237c79f1ebe933a4..dd380e61f082adf6a6ed182fe27e47516c0267ad 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_back_uth_terminals_bidir is
generic (
@@ -83,51 +83,50 @@ architecture str of unb1_board_back_uth_terminals_bidir is
begin
gen_bus : for I in 0 to c_unb1_board_tr_back.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
- tx_dp_siso_arr => tx_dp_siso_2arr(I),
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I),
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
- rx_dp_siso_arr => rx_dp_siso_2arr(I),
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I),
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- -- monitoring interface
- rx_mon_pkt_sosi_arr => OPEN,
- rx_mon_dist_sosi_arr => open
- );
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => OPEN,
+ rx_mon_dist_sosi_arr => open
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
index 54d62c3a5def1be5cf5d2b3b32e667346ce45695..8e5daa68cf1c31134f832b7f6557bb8311a9b84c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -108,9 +108,9 @@ entity unb1_board_clk200_pll is
g_clk3_phase_shift : string := "313"; -- = 022.5 = st_clk_vec[3]
g_clk4_phase_shift : string := "469"; -- = 033.75 = st_clk_vec[4]
g_clk5_phase_shift : string := "625"; -- = 045 = st_clk_vec[5]
- -- "781"; -- = 056.25
+ -- "781"; -- = 056.25
g_clk6_phase_shift : string := "938"; -- = 067.5 = st_clk_vec[6]
- -- "1094"; -- = 078.75
+ -- "1094"; -- = 078.75
g_clk1_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk2_divide_by : natural := 32; -- = clk 200/32 MHz
g_clk3_divide_by : natural := 32; -- = clk 200/32 MHz
@@ -163,96 +163,96 @@ begin
gen_0 : if g_sel = 0 generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_1 : if g_sel = 1 generate
i_st_clk200p <= i_st_clk_vec(0);
u_st_pll_p6 : entity tech_pll_lib.tech_pll_clk200_p6
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk0_phase_shift,
- g_clk1_used => c_clk1_used,
- g_clk2_used => c_clk2_used,
- g_clk3_used => c_clk3_used,
- g_clk4_used => c_clk4_used,
- g_clk5_used => c_clk5_used,
- g_clk6_used => c_clk6_used,
- g_clk1_divide_by => g_clk1_divide_by,
- g_clk2_divide_by => g_clk2_divide_by,
- g_clk3_divide_by => g_clk3_divide_by,
- g_clk4_divide_by => g_clk4_divide_by,
- g_clk5_divide_by => g_clk5_divide_by,
- g_clk6_divide_by => g_clk6_divide_by,
- g_clk1_phase_shift => g_clk1_phase_shift,
- g_clk2_phase_shift => g_clk2_phase_shift,
- g_clk3_phase_shift => g_clk3_phase_shift,
- g_clk4_phase_shift => g_clk4_phase_shift,
- g_clk5_phase_shift => g_clk5_phase_shift,
- g_clk6_phase_shift => g_clk6_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200,
- c0 => i_st_clk200,
- c1 => i_st_clk_vec(0),
- c2 => i_st_clk_vec(1),
- c3 => i_st_clk_vec(2),
- c4 => i_st_clk_vec(3),
- c5 => i_st_clk_vec(4),
- c6 => i_st_clk_vec(5),
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk0_phase_shift,
+ g_clk1_used => c_clk1_used,
+ g_clk2_used => c_clk2_used,
+ g_clk3_used => c_clk3_used,
+ g_clk4_used => c_clk4_used,
+ g_clk5_used => c_clk5_used,
+ g_clk6_used => c_clk6_used,
+ g_clk1_divide_by => g_clk1_divide_by,
+ g_clk2_divide_by => g_clk2_divide_by,
+ g_clk3_divide_by => g_clk3_divide_by,
+ g_clk4_divide_by => g_clk4_divide_by,
+ g_clk5_divide_by => g_clk5_divide_by,
+ g_clk6_divide_by => g_clk6_divide_by,
+ g_clk1_phase_shift => g_clk1_phase_shift,
+ g_clk2_phase_shift => g_clk2_phase_shift,
+ g_clk3_phase_shift => g_clk3_phase_shift,
+ g_clk4_phase_shift => g_clk4_phase_shift,
+ g_clk5_phase_shift => g_clk5_phase_shift,
+ g_clk6_phase_shift => g_clk6_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200,
+ c0 => i_st_clk200,
+ c1 => i_st_clk_vec(0),
+ c2 => i_st_clk_vec(1),
+ c3 => i_st_clk_vec(2),
+ c4 => i_st_clk_vec(3),
+ c5 => i_st_clk_vec(4),
+ c6 => i_st_clk_vec(5),
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end stratix4;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
index f5684a4c5c866e8f11968beb953ac30f187a589c..fa1544c63e181e8a27984761c9b6b07d20f15b03 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -53,17 +53,17 @@ end unb1_board_clk25_pll;
architecture stratixiv of unb1_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk40,
- c2 => c2_clk50,
- c3 => c3_clk125,
- c4 => c4_clk200,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk40,
+ c2 => c2_clk50,
+ c3 => c3_clk125,
+ c4 => c4_clk200,
+ locked => pll_locked
+ );
end stratixiv;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
index 4498f945ae69c11320ddfe1a96de83c9ed05cb35..008bb0bd5bb7eceb5a8b1dd7564ea74fd0efaba2 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
index ce43144b74c4f5a0287591ac3fbecbad66a1bca6..0a2c544ee30d56294ecb40a137f6837ef9d19db3 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_front_io is
generic (
@@ -78,50 +78,49 @@ begin
-- MDIO buffers
gen_iobuf_0 : if g_nof_xaui > 0 generate
u_iobuf_0 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(0),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(0)
- );
+ port map (
+ dat_inout => SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(0),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(0)
+ );
SI_FN_0_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(0);
end generate;
gen_iobuf_1 : if g_nof_xaui > 1 generate
u_iobuf_1 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(1),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(1)
- );
+ port map (
+ dat_inout => SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(1),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(1)
+ );
SI_FN_1_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(1);
end generate;
gen_iobuf_2 : if g_nof_xaui > 2 generate
u_iobuf_2 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(2),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(2)
- );
+ port map (
+ dat_inout => SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(2),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(2)
+ );
SI_FN_2_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(2);
end generate;
gen_iobuf_3 : if g_nof_xaui > 3 generate
u_iobuf_3 : entity common_lib.common_inout
- port map (
- dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
- dat_in_from_line => mdio_mdat_in_arr(3),
- dat_out_to_line => '0',
- dat_out_en => mdio_mdat_oen_arr(3)
- );
+ port map (
+ dat_inout => SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdio_id),
+ dat_in_from_line => mdio_mdat_in_arr(3),
+ dat_out_to_line => '0',
+ dat_out_en => mdio_mdat_oen_arr(3)
+ );
SI_FN_3_CNTRL(c_unb1_board_ci.tr.cntrl_mdc_id) <= mdio_mdc_arr(3);
end generate;
-
end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index f16b3b3714b61fd33155b0e9e20b47225c1a6799..89dbd777706e50e2429fb8e66b63dab13cc234e6 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_io is
generic (
@@ -57,5 +57,4 @@ begin
rx_serial_2arr(2)(I) <= FN_BN_2_RX(I);
rx_serial_2arr(3)(I) <= FN_BN_3_RX(I);
end generate;
-
end;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 28c28e6f37d7c579f208370edd249925e777aef4..f8beb5a23c2dc4ad96ed80feef82aedbab32a252 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -133,11 +133,11 @@
-- unb1_board_mesh_model_sl.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_bidir is
generic (
@@ -166,30 +166,30 @@ end unb1_board_mesh_reorder_bidir;
architecture str of unb1_board_mesh_reorder_bidir is
begin
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => tx_clk,
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => tx_clk,
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_reorder
- )
- port map (
- chip_id => chip_id,
- clk => rx_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => rx_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index 71b2ca81148443b5ee2188af3661006c96fc78a6..4dd350e6095ea54cbe87ab61070277de608466eb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_rx is
generic (
@@ -91,8 +91,8 @@ begin
tx_usr_siso_2arr(1) <= tx_phy_siso_2arr(0);
tx_usr_siso_2arr(0) <= tx_phy_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
- -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
+ 5 => -- this is BN0
+ -- or BN1, connect phy bus 0,1,2,3 to usr bus 3,2,1,0
-- sosi
rx_usr_sosi_2arr(3) <= rx_phy_sosi_2arr(0);
rx_usr_sosi_2arr(2) <= rx_phy_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index 7fe1309d411ffe2e996a2656772676fc7634a219..ba44d1f768ff6f704a65ba959905e68df431c657 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -31,11 +31,11 @@
-- . Indexing for *_2arr = (node id 0,1,2,3)(tr lane 3,2,1,0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_reorder_tx is
generic (
@@ -59,19 +59,19 @@ begin
-- Register the chip_id from FPGA pins to ease timing closure.
-- . Alternatively these registers may better be removed and pin input chip_id[] set as false path for timing closure
u_chip_id : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_meta_delay_len,
- g_reset_value => 0,
- g_in_dat_w => chip_id'LENGTH,
- g_out_dat_w => chip_id'length
- )
- port map (
- rst => '0',
- clk => clk,
- in_dat => chip_id,
- out_dat => chip_id_reg
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_meta_delay_len,
+ g_reset_value => 0,
+ g_in_dat_w => chip_id'LENGTH,
+ g_out_dat_w => chip_id'length
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ in_dat => chip_id,
+ out_dat => chip_id_reg
+ );
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
chip_id_i <= func_unb1_board_chip_id(chip_id_reg, g_node_type);
@@ -109,8 +109,8 @@ begin
rx_phy_siso_2arr(1) <= rx_usr_siso_2arr(0);
rx_phy_siso_2arr(0) <= rx_usr_siso_2arr(1);
when 4 |
- 5 => -- this is BN0
- -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
+ 5 => -- this is BN0
+ -- or BN1, connect usr bus 0,1,2,3 to phy bus 3,2,1,0
-- sosi
tx_phy_sosi_2arr(3) <= tx_usr_sosi_2arr(0);
tx_phy_sosi_2arr(2) <= tx_usr_sosi_2arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index a4259a7adea7c7e99a672f4afb6a6cf2127f1b6b..6cc39cd1894181b18962d273e94226caf54f5e82 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -26,13 +26,13 @@
-- except for the SOSI entity I/O types and the monitor outputs.
library IEEE, common_lib, dp_lib, uth_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use work.unb1_board_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use work.unb1_board_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_mesh_uth_terminals_bidir is
generic (
@@ -90,54 +90,53 @@ architecture str of unb1_board_mesh_uth_terminals_bidir is
begin
gen_uth_terminal_bidir : for I in 0 to c_unb1_board_tr_mesh.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => g_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_mux_mode => c_tx_mux_mode,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => g_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_mux_mode => c_tx_mux_mode,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- usr side interface
- tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ -- usr side interface
+ tx_dp_sosi_arr => tx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ tx_dp_siso_arr => tx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
- rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
- rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ rx_dp_sosi_arr => rx_dp_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0),
+ rx_dp_siso_arr => rx_dp_siso_2arr(I)(g_usr_nof_streams - 1 downto 0),
- -- phy side interface
- tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ -- phy side interface
+ tx_uth_sosi_arr => tx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ tx_uth_siso_arr => tx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_sosi_arr => rx_uth_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_uth_siso_arr => rx_uth_siso_2arr(I)(g_phy_nof_serial - 1 downto 0),
- -- monitoring interface
- rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
- rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
- );
+ -- monitoring interface
+ rx_mon_pkt_sosi_arr => rx_mon_pkt_sosi_2arr(I)(g_phy_nof_serial - 1 downto 0),
+ rx_mon_dist_sosi_arr => rx_mon_dist_sosi_2arr(I)(g_usr_nof_streams - 1 downto 0)
+ );
end generate;
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
index d5644e7de883ffe3e3e1cd1b9fe0caa76f9fd6ee..f443ce99dedbf8066ab238f09c1b852212180043 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Provide the basic node control along with an SOPC Builder system:
@@ -66,59 +66,59 @@ begin
pulse_ms <= i_pulse_ms;
u_unb1_board_clk_rst : entity work.unb1_board_clk_rst
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
- );
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => i_sys_rst -- release reset some clock cycles after sys_locked went high
+ );
u_common_areset_cal : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => cal_clk,
- out_rst => cal_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => cal_clk,
+ out_rst => cal_rst
+ );
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
- clk => st_clk,
- out_rst => st_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_sys_rst, -- release reset some clock cycles after i_sys_rst went low
+ clk => st_clk,
+ out_rst => st_rst
+ );
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => pulse_s
+ );
u_unb1_board_wdi_extend : entity work.unb1_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_sys_rst,
- clk => sys_clk,
- pulse_ms => i_pulse_ms,
- wdi_in => wdi_in,
- wdi_out => wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_sys_rst,
+ clk => sys_clk,
+ pulse_ms => i_pulse_ms,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
index d524e5a62326d474ef631bf8ea9bd9333f760fe2..41915c70cba276e7eeb238cb9e19b923e2ab8e6c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb1_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb1_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
@@ -157,7 +157,6 @@ package unb1_board_peripherals_pkg is
end record;
constant c_unb1_board_peripherals_mm_reg_default : t_c_unb1_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1);
-
end unb1_board_peripherals_pkg;
package body unb1_board_peripherals_pkg is
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
index 180b535b22becf962ec54fbf906e62071c0757a8..748da3da5b2cc5656453f141ee6824682ade2560 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb1_board_pkg is
-- UniBoard
@@ -41,13 +41,13 @@ package unb1_board_pkg is
constant c_unb1_board_nof_uniboard_w : natural := 5; -- Only 2 required for 4 boards; full width is 5.
-- Clock frequencies
- constant c_unb1_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb1_board_eth_clk_freq : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL in SOPC
- constant c_unb1_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_50M : natural := 50 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_100M : natural := 100 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
- constant c_unb1_board_mm_clk_freq_125M : natural := 125 * 10**6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_ext_clk_freq_200M : natural := 200 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb1_board_eth_clk_freq : natural := 25 * 10 ** 6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL in SOPC
+ constant c_unb1_board_tse_clk_freq : natural := 125 * 10 ** 6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_cal_clk_freq : natural := 40 * 10 ** 6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_50M : natural := 50 * 10 ** 6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_100M : natural := 100 * 10 ** 6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
+ constant c_unb1_board_mm_clk_freq_125M : natural := 125 * 10 ** 6; -- SOPC memory mapped bus clock derived from ETH_clk by PLL in SOPC
-- PHY interface device numbers
constant c_unb1_board_phy_id_eth1g : natural := 1;
@@ -191,107 +191,109 @@ package unb1_board_pkg is
nof_ovr : natural; -- = 2; -- Fixed 2 overflow signals, one for ports AB and one for ports CD
port_w : natural; -- = 8; -- Fixed 8 bit ADC BI port width, the ADC sample width is also 8 bit
lvds_data_rate : natural; -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
- use_dpa : boolean; -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
- use_lvds_clk : boolean; -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
- use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
- lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
- nof_clocks : natural; -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
- -- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
- lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
- dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
- end record;
-
- constant c_unb1_board_ai : t_c_unb1_board_ai := (4, 2, 8, 800, true, true, false, 0, 2, 2, 4);
-
- type t_unb1_board_fw_version is record
- hi : natural; -- = 0..15
- lo : natural; -- = 0..15, firmware version is: hi.lo
- end record;
-
- constant c_unb1_board_fw_version : t_unb1_board_fw_version := (0, 0);
-
- -- SIGNAL RECORD DECLARATIONS -----------------------------------------------
-
- -- DDR3 (definitions similar as in ug_altmemphy.pdf)
- type t_unb1_board_ddr_in is record
- evt : std_logic;
- --nc : STD_LOGIC; -- not connect, needed to be able to initialize constant record which has to have more than one field in VHDL
- end record;
-
- type t_unb1_board_ddr_inout is record
- dq : std_logic_vector(c_unb1_board_ci.ddr.dq_w - 1 downto 0); -- data bus
- dqs : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0); -- data strobe bus
- dqs_n : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0);
- clk : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, positive edge clock
- clk_n : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, negative edge clock
- scl : std_logic; -- I2C
- sda : std_logic;
- end record;
-
- type t_unb1_board_ddr_out is record
- a : std_logic_vector(c_unb1_board_ci.ddr.a_w - 1 downto 0); -- row and column address
- ba : std_logic_vector(c_unb1_board_ci.ddr.ba_w - 1 downto 0); -- bank address
- dm : std_logic_vector(c_unb1_board_ci.ddr.dm_w - 1 downto 0); -- data mask bus
- cas_n : std_logic; -- column address strobe
- ras_n : std_logic; -- row address strobe
- we_n : std_logic; -- write enable signal
- reset_n : std_logic; -- reset signal
- odt : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- on-die termination control signal
- cke : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- clock enable
- cs_n : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- chip select
- end record;
-
- --CONSTANT c_unb1_board_ddr_in_rst : t_unb1_board_ddr_in := ('0', 'X');
- constant c_unb1_board_ddr_inout_rst : t_unb1_board_ddr_inout := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0');
- constant c_unb1_board_ddr_out_rst : t_unb1_board_ddr_out := ((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
-
- -- I2C, MDIO
- -- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
- -- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
- type t_unb1_board_i2c_inout is record
- scl : std_logic; -- serial clock
- sda : std_logic; -- serial data
- end record;
-
- -- System info
- type t_c_unb1_board_system_info is record
- version : natural; -- UniBoard board HW version (2 bit value)
- id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
- bck_id : natural; -- = id[7:3], ID part from back plane
- chip_id : natural; -- = id[2:0], ID part from UniBoard
- is_bn : natural; -- = id[2], 0 for Front Node, 1 for Back Node
- node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
- is_bn3 : natural; -- 1 for Back Node 3, else 0.
- end record;
-
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
-
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector;
-
- -- Connect: out_2arr = in_2arr of different types
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
-
- -- Transpose: out_2arr(J)(I) = in_2arr(I)(J) for different types
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr;
- function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr;
-
+ use_dpa : boolean; -- = TRUE; -- When TRUE use LVDS_RX with DPA, else used fixed IOE delays and/or lvds_clk_phase instead of DPA
+ use_lvds_clk : boolean; -- = TRUE; -- When TRUE use the one or both ADC BI lvds_clk, else use the single dp_clk to capture the lvds data
+ use_lvds_clk_rst : boolean; -- = FALSE; -- When TRUE then support reset pulse to ADU to align the lvds_clk to the dp_clk, else no support
+lvds_clk_phase : natural; -- = 0; -- Use PLL phase 0 for center aligned. Only for no DPA
+nof_clocks : natural; -- = 2; -- 1 --> Use ADC BI clock D or dp_clk and 32 bit port ABCD
+-- 2 --> Use ADC BI clock A, D and 16 bit ports AB, CD
+lvds_deser_factor : natural; -- = 2; -- The ADC sampled data comes in with a DDR lvds_clk, so lvds_data_rate / 2
+dp_deser_factor : natural; -- = 4; -- The Data Path clock dp_clk frequency is 200 MHz, so lvds_data_rate / 4
+end record;
+
+constant c_unb1_board_ai : t_c_unb1_board_ai := (4, 2, 8, 800, true, true, false, 0, 2, 2, 4);
+
+type t_unb1_board_fw_version is record
+ hi : natural; -- = 0..15
+ lo : natural; -- = 0..15, firmware version is: hi.lo
+end record;
+
+constant c_unb1_board_fw_version : t_unb1_board_fw_version := (0, 0);
+
+-- SIGNAL RECORD DECLARATIONS -----------------------------------------------
+
+-- DDR3 (definitions similar as in ug_altmemphy.pdf)
+type t_unb1_board_ddr_in is record
+ evt : std_logic;
+ --nc : STD_LOGIC; -- not connect, needed to be able to initialize constant record which has to have more than one field in VHDL
+end record;
+
+type t_unb1_board_ddr_inout is record
+ dq : std_logic_vector(c_unb1_board_ci.ddr.dq_w - 1 downto 0); -- data bus
+ dqs : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0); -- data strobe bus
+ dqs_n : std_logic_vector(c_unb1_board_ci.ddr.dqs_w - 1 downto 0);
+ clk : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, positive edge clock
+ clk_n : std_logic_vector(c_unb1_board_ci.ddr.clk_w - 1 downto 0); -- clock, negative edge clock
+ scl : std_logic; -- I2C
+ sda : std_logic;
+end record;
+
+type t_unb1_board_ddr_out is record
+ a : std_logic_vector(c_unb1_board_ci.ddr.a_w - 1 downto 0); -- row and column address
+ ba : std_logic_vector(c_unb1_board_ci.ddr.ba_w - 1 downto 0); -- bank address
+ dm : std_logic_vector(c_unb1_board_ci.ddr.dm_w - 1 downto 0); -- data mask bus
+ cas_n : std_logic; -- column address strobe
+ ras_n : std_logic; -- row address strobe
+ we_n : std_logic; -- write enable signal
+ reset_n : std_logic; -- reset signal
+ odt : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- on-die termination control signal
+ cke : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- clock enable
+ cs_n : std_logic_vector(c_unb1_board_ci.ddr.cs_w - 1 downto 0); -- chip select
+end record;
+
+--CONSTANT c_unb1_board_ddr_in_rst : t_unb1_board_ddr_in := ('0', 'X');
+constant c_unb1_board_ddr_inout_rst : t_unb1_board_ddr_inout := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0');
+constant c_unb1_board_ddr_out_rst : t_unb1_board_ddr_out := ((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
+
+-- I2C, MDIO
+-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
+-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
+type t_unb1_board_i2c_inout is record
+ scl : std_logic; -- serial clock
+ sda : std_logic; -- serial data
+end record;
+
+-- System info
+type t_c_unb1_board_system_info is record
+ version : natural; -- UniBoard board HW version (2 bit value)
+ id : natural; -- UniBoard FPGA node id (8 bit value)
+ -- Derived ID info:
+ bck_id : natural; -- = id[7:3], ID part from back plane
+ chip_id : natural; -- = id[2:0], ID part from UniBoard
+ is_bn : natural; -- = id[2], 0 for Front Node, 1 for Back Node
+ node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
+ is_bn3 : natural; -- 1 for Back Node 3, else 0.
+end record;
+
+function func_unb1_board_system_info(
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info;
+
+function func_unb1_board_chip_id(
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector;
+
+-- Connect: out_2arr = in_2arr of different types
+function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
+function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+function func_unb1_board_connect_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+
+-- Transpose: out_2arr(J)(I) = in_2arr(I)(J) for different types
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_back_siso_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_sosi_2arr) return t_unb1_board_mesh_sosi_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_mesh_siso_2arr) return t_unb1_board_mesh_siso_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_sosi_2arr) return t_unb1_board_back_sosi_2arr;
+function func_unb1_board_transpose_2arr(in_2arr : t_unb1_board_back_siso_2arr) return t_unb1_board_back_siso_2arr;
end unb1_board_pkg;
package body unb1_board_pkg is
- function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
+ function func_unb1_board_system_info(
+ VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
variable v_system_info : t_c_unb1_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
@@ -304,8 +306,9 @@ package body unb1_board_pkg is
return v_system_info;
end;
- function func_unb1_board_chip_id(chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
- node_type : in t_e_unb1_board_node) return std_logic_vector is
+ function func_unb1_board_chip_id(
+ chip_id : in std_logic_vector(c_unb1_board_aux.chip_id_w - 1 downto 0);
+ node_type : in t_e_unb1_board_node) return std_logic_vector is
variable v_chip_id : std_logic_vector(chip_id'range); -- [2:0]
begin
v_chip_id := chip_id; -- default for design that can run on either FN or BN
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
index ac56d4d4b26382c050acbec406dfede7432a5479..3e3e906f208c990c7f046fc55d362f1cbf8de75c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb1_board_sens is
generic (
@@ -47,9 +47,9 @@ end entity;
architecture str of unb1_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10 ** 6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -62,43 +62,43 @@ architecture str of unb1_board_sens is
signal smbus_out_end : std_logic;
begin
u_unb1_board_sens_ctrl : entity work.unb1_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_i2c_phy => c_sens_phy
+ )
+ port map (
+ gs_sim => g_sim,
+ clk => clk,
+ rst => rst,
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
+ );
end architecture;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index a9747754f1745d8a09223b4dc012ea48eb23212c..595dfb9b17760d25c901d8b334219df322f66fd4 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb1_board_sens_ctrl is
generic (
@@ -69,7 +69,7 @@ architecture rtl of unb1_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
index 43e27b565f8525aff904d8dad008a0f5714278f7..135cf1680fc1bf2d78f1364204104135aa538dce 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_sens_reg is
generic (
@@ -92,15 +92,16 @@ end unb1_board_sens_reg;
architecture rtl of unb1_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
- signal i_temp_high : std_logic_vector(6 downto 0);
+ signal i_temp_high : std_logic_vector(6 downto 0);
begin
temp_high <= i_temp_high;
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
index 06b60254c051f75626dc4214d5d74b4cf1c8869f..dd3e9f97da01942b102c81851537fca8e3328bdb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index 594354d35e7a30d3ea330b3020a46e422530eea1..9be4cccce7ad421a59f349b1383ce92611f4d2b0 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_system_info_reg is
generic (
@@ -69,7 +69,7 @@ entity unb1_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb1_board_system_info_reg;
architecture rtl of unb1_board_system_info_reg is
@@ -80,24 +80,25 @@ architecture rtl of unb1_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
-
- constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
- TO_UVEC(g_use_phy.tr_front,1) &
- TO_UVEC(g_use_phy.tr_mesh, 1) &
- TO_UVEC(g_use_phy.tr_back, 1) &
- TO_UVEC(g_use_phy.ddr3_I, 1) &
- TO_UVEC(g_use_phy.ddr3_II, 1) &
- TO_UVEC(g_use_phy.adc, 1) &
- TO_UVEC(g_use_phy.wdi, 1);
-
- constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
- constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
+
+ constant c_use_phy_w : natural := 8;
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
+ TO_UVEC(g_use_phy.tr_front,1) &
+ TO_UVEC(g_use_phy.tr_mesh, 1) &
+ TO_UVEC(g_use_phy.tr_back, 1) &
+ TO_UVEC(g_use_phy.ddr3_I, 1) &
+ TO_UVEC(g_use_phy.ddr3_II, 1) &
+ TO_UVEC(g_use_phy.adc, 1) &
+ TO_UVEC(g_use_phy.wdi, 1);
+
+ constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
begin
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index d0e464d77e299726b0f8d7fa82147d577b6578ba..76da47a898b1c110b5002dca13c0593a3e8d5ca9 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -34,14 +34,14 @@
-- g_use_tx and g_use_rx because they are both TRUE.
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_back is
generic (
@@ -136,80 +136,80 @@ architecture str of unb1_board_terminals_back is
signal rx_serial_arr : std_logic_vector(c_nof_gx - 1 downto 0);
begin
u_unb1_board_back_select: entity work.unb1_board_back_select
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_usr_sosi_2arr,
- tx_usr_siso_2arr => tx_usr_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_usr_sosi_2arr,
+ tx_usr_siso_2arr => tx_usr_siso_2arr,
- rx_usr_sosi_2arr => rx_usr_sosi_2arr,
- rx_usr_siso_2arr => rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => rx_usr_sosi_2arr,
+ rx_usr_siso_2arr => rx_usr_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_sel_sosi_2arr,
- tx_phy_siso_2arr => tx_sel_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_sel_sosi_2arr,
+ tx_phy_siso_2arr => tx_sel_siso_2arr,
- rx_phy_sosi_2arr => rx_sel_sosi_2arr,
- rx_phy_siso_2arr => rx_sel_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_sel_sosi_2arr,
+ rx_phy_siso_2arr => rx_sel_siso_2arr
+ );
u_unb1_board_back_reorder : entity work.unb1_board_back_reorder
- port map (
- bck_id => bck_id,
- clk => dp_clk,
+ port map (
+ bck_id => bck_id,
+ clk => dp_clk,
- -- User side
- tx_usr_sosi_2arr => tx_sel_sosi_2arr,
- tx_usr_siso_2arr => tx_sel_siso_2arr,
+ -- User side
+ tx_usr_sosi_2arr => tx_sel_sosi_2arr,
+ tx_usr_siso_2arr => tx_sel_siso_2arr,
- rx_usr_sosi_2arr => rx_sel_sosi_2arr,
- rx_usr_siso_2arr => rx_sel_siso_2arr,
+ rx_usr_sosi_2arr => rx_sel_sosi_2arr,
+ rx_usr_siso_2arr => rx_sel_siso_2arr,
- -- Phy side
- tx_phy_sosi_2arr => tx_term_sosi_2arr,
- tx_phy_siso_2arr => tx_term_siso_2arr,
+ -- Phy side
+ tx_phy_sosi_2arr => tx_term_sosi_2arr,
+ tx_phy_siso_2arr => tx_term_siso_2arr,
- rx_phy_sosi_2arr => rx_term_sosi_2arr,
- rx_phy_siso_2arr => rx_term_siso_2arr
- );
+ rx_phy_sosi_2arr => rx_term_sosi_2arr,
+ rx_phy_siso_2arr => rx_term_siso_2arr
+ );
u_unb1_board_back_uth_terminals_bidir : entity work.unb1_board_back_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- -- Rx
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_timeout_w => g_rx_timeout_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- User
- tx_dp_sosi_2arr => tx_term_sosi_2arr,
- tx_dp_siso_2arr => tx_term_siso_2arr,
-
- rx_dp_sosi_2arr => rx_term_sosi_2arr,
- rx_dp_siso_2arr => rx_term_siso_2arr,
-
- -- Phy
- tx_uth_sosi_2arr => tx_phy_sosi_2arr,
- tx_uth_siso_2arr => tx_phy_siso_2arr,
-
- rx_uth_sosi_2arr => rx_phy_sosi_2arr,
- rx_uth_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ -- Rx
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_timeout_w => g_rx_timeout_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- User
+ tx_dp_sosi_2arr => tx_term_sosi_2arr,
+ tx_dp_siso_2arr => tx_term_siso_2arr,
+
+ rx_dp_sosi_2arr => rx_term_sosi_2arr,
+ rx_dp_siso_2arr => rx_term_siso_2arr,
+
+ -- Phy
+ tx_uth_sosi_2arr => tx_phy_sosi_2arr,
+ tx_uth_siso_2arr => tx_phy_siso_2arr,
+
+ rx_uth_sosi_2arr => rx_phy_sosi_2arr,
+ rx_uth_siso_2arr => rx_phy_siso_2arr
+ );
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
@@ -217,55 +217,56 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for i in c_nof_bus_serial - 1 downto 0 generate
+
gen_lane : for j in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
- tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
+ -- SOSI
+ tx_phy_sosi_arr(i * g_phy_nof_serial + j) <= tx_phy_sosi_2arr(i)(j);
+ tx_phy_siso_2arr(i)(j) <= tx_phy_siso_arr(i * g_phy_nof_serial + j);
- rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
- rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
+ rx_phy_sosi_2arr(i)(j) <= rx_phy_sosi_arr(i * g_phy_nof_serial + j);
+ rx_phy_siso_arr(i * g_phy_nof_serial + j) <= rx_phy_siso_2arr(i)(j);
- -- Serial
- tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
- rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
+ -- Serial
+ tx_serial_2arr(i)(j) <= tx_serial_arr(i * g_phy_nof_serial + j);
+ rx_serial_arr(i * g_phy_nof_serial + j) <= rx_serial_2arr(i)(j);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_nof_gx => c_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => true,
- g_rx => true,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_gx => c_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => true,
+ g_rx => true,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index b65dc635d740a2feb41f36c9ea01d9f6f5a088b7..414a63b0d081080c8f459c586115778c04af58eb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -49,14 +49,14 @@
-- hardware use the default g_phy_ena_reorder = TRUE.
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb1_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.dp_packet_pkg.all;
-use uth_lib.uth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb1_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.dp_packet_pkg.all;
+ use uth_lib.uth_pkg.all;
entity unb1_board_terminals_mesh is
generic (
@@ -88,12 +88,12 @@ entity unb1_board_terminals_mesh is
g_rx_timeout_w : natural := 0; -- when 0 then no timeout else when > 0 then flush pending rx payload after 2**g_timeout_w clk cylces of inactive uth_rx snk_in.valid
-- Monitoring
g_mon_select : natural := 0; -- 0 = no SOSI data buffers monitor via MM
- -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
- -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
- -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
- -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
- -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
- -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
+ -- 1 = enable monitor the Rx UTH packets per serial lane after the tr_nonbonded
+ -- 2 = enable monitor the Rx UTH packets per serial lane after the mesh reorder
+ -- 3 = enable monitor the Rx DP packets per serial lane after the uth_rx
+ -- 4 = enable monitor the Rx DP packets per user stream after the dp_distribute
+ -- 5 = enable monitor the Tx UTH packets per serial lane to the tr_nonbonded
+ -- 6 = enable monitor the Tx UTH packets per serial lane to the mesh reorder
g_mon_nof_words : natural := 1024;
g_mon_use_sync : boolean := true;
-- UTH
@@ -145,19 +145,19 @@ architecture str of unb1_board_terminals_mesh is
-- g_mon_select
constant c_usr_nof_streams : natural := g_nof_bus * g_usr_nof_streams;
constant c_mon_nof_streams : natural := sel_n(g_mon_select, c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_phy_nof_gx,
- c_usr_nof_streams,
- c_phy_nof_gx,
- c_phy_nof_gx);
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_phy_nof_gx,
+ c_usr_nof_streams,
+ c_phy_nof_gx,
+ c_phy_nof_gx);
constant c_mon_data_w : natural := sel_n(g_mon_select, c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- c_packet_data_w,
- g_usr_data_w,
- c_packet_data_w,
- c_packet_data_w);
+ c_packet_data_w,
+ c_packet_data_w,
+ c_packet_data_w,
+ g_usr_data_w,
+ c_packet_data_w,
+ c_packet_data_w);
-- uth terminals
signal tx_term_siso_2arr : t_unb1_board_mesh_siso_2arr;
@@ -190,7 +190,9 @@ begin
------------------------------------------------------------------------------
mon_rx_mesh : if g_mon_select = 1 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= rx_phy_sosi_2arr(I)(J);
end generate;
@@ -198,7 +200,9 @@ begin
end generate;
mon_rx_term_uth : if g_mon_select = 2 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= rx_term_sosi_2arr(I)(J);
end generate;
@@ -206,7 +210,9 @@ begin
end generate;
mon_rx_term_pkt : if g_mon_select = 3 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= mon_rx_term_pkt_sosi_2arr(I)(J);
end generate;
@@ -214,7 +220,9 @@ begin
end generate;
mon_rx_term_dist : if g_mon_select = 4 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_usr_nof_streams - 1 generate
mon_sosi_arr(I * g_usr_nof_streams + J) <= mon_rx_term_dist_sosi_2arr(I)(J);
end generate;
@@ -222,7 +230,9 @@ begin
end generate;
mon_tx_mesh : if g_mon_select = 5 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
end generate;
@@ -230,7 +240,9 @@ begin
end generate;
mon_tx_term_uth : if g_mon_select = 6 generate
+
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
+
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
mon_sosi_arr(I * g_phy_nof_serial + J) <= tx_term_sosi_2arr(I)(J);
end generate;
@@ -243,25 +255,25 @@ begin
gen_monitor : if g_mon_select >= 1 generate
u_data_buf : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_mon_nof_streams,
- g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
- g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
- g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- -- ST interface
- in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
- in_sosi_arr => mon_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_mon_nof_streams,
+ g_data_w => c_mon_data_w, -- stream data width must be <= c_word_w = 32b, the MM word width
+ g_buf_nof_data => g_mon_nof_words, -- nof words per data buffer
+ g_buf_use_sync => g_mon_use_sync -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ -- ST interface
+ in_sync => dp_sync, -- input sync pulse in ST dp_clk domain that starts data buffer when g_use_in_sync = TRUE
+ in_sosi_arr => mon_sosi_arr
+ );
end generate;
------------------------------------------------------------------------------
@@ -269,85 +281,85 @@ begin
------------------------------------------------------------------------------
u_unb1_board_mesh_uth_terminals_bidir : entity work.unb1_board_mesh_uth_terminals_bidir
- generic map (
- -- User
- g_usr_nof_streams => g_usr_nof_streams,
- g_usr_use_complex => g_usr_use_complex,
- g_usr_data_w => g_usr_data_w,
- g_usr_frame_len => g_usr_frame_len,
- -- DP/UTH packet
- g_packet_data_w => c_packet_data_w,
- -- Phy
- g_phy_nof_serial => g_phy_nof_serial,
- -- Tx
- g_use_tx => g_use_tx,
- g_tx_input_use_fifo => g_tx_input_use_fifo,
- g_tx_input_fifo_size => g_tx_input_fifo_size,
- g_tx_input_fifo_fill => g_tx_input_fifo_fill,
- -- Rx
- g_use_rx => g_use_rx,
- g_rx_output_use_fifo => g_rx_output_use_fifo,
- g_rx_output_fifo_size => g_rx_output_fifo_size,
- g_rx_output_fifo_fill => g_rx_output_fifo_fill,
- g_rx_timeout_w => g_rx_timeout_w,
- -- UTH
- g_uth_len_max => g_uth_len_max,
- g_uth_typ_ofs => g_uth_typ_ofs
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ -- User
+ g_usr_nof_streams => g_usr_nof_streams,
+ g_usr_use_complex => g_usr_use_complex,
+ g_usr_data_w => g_usr_data_w,
+ g_usr_frame_len => g_usr_frame_len,
+ -- DP/UTH packet
+ g_packet_data_w => c_packet_data_w,
+ -- Phy
+ g_phy_nof_serial => g_phy_nof_serial,
+ -- Tx
+ g_use_tx => g_use_tx,
+ g_tx_input_use_fifo => g_tx_input_use_fifo,
+ g_tx_input_fifo_size => g_tx_input_fifo_size,
+ g_tx_input_fifo_fill => g_tx_input_fifo_fill,
+ -- Rx
+ g_use_rx => g_use_rx,
+ g_rx_output_use_fifo => g_rx_output_use_fifo,
+ g_rx_output_fifo_size => g_rx_output_fifo_size,
+ g_rx_output_fifo_fill => g_rx_output_fifo_fill,
+ g_rx_timeout_w => g_rx_timeout_w,
+ -- UTH
+ g_uth_len_max => g_uth_len_max,
+ g_uth_typ_ofs => g_uth_typ_ofs
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- User
- tx_dp_sosi_2arr => tx_usr_sosi_2arr,
- tx_dp_siso_2arr => tx_usr_siso_2arr,
+ -- User
+ tx_dp_sosi_2arr => tx_usr_sosi_2arr,
+ tx_dp_siso_2arr => tx_usr_siso_2arr,
- rx_dp_sosi_2arr => rx_usr_sosi_2arr,
- rx_dp_siso_2arr => rx_usr_siso_2arr,
+ rx_dp_sosi_2arr => rx_usr_sosi_2arr,
+ rx_dp_siso_2arr => rx_usr_siso_2arr,
- -- Phy
- tx_uth_sosi_2arr => tx_term_sosi_2arr,
- tx_uth_siso_2arr => tx_term_siso_2arr,
+ -- Phy
+ tx_uth_sosi_2arr => tx_term_sosi_2arr,
+ tx_uth_siso_2arr => tx_term_siso_2arr,
- rx_uth_sosi_2arr => rx_term_sosi_2arr,
- rx_uth_siso_2arr => rx_term_siso_2arr,
+ rx_uth_sosi_2arr => rx_term_sosi_2arr,
+ rx_uth_siso_2arr => rx_term_siso_2arr,
- -- Monitoring
- rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
- rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
- );
+ -- Monitoring
+ rx_mon_pkt_sosi_2arr => mon_rx_term_pkt_sosi_2arr,
+ rx_mon_dist_sosi_2arr => mon_rx_term_dist_sosi_2arr
+ );
------------------------------------------------------------------------------
-- Compensate for mesh reorder (g_phy_ena_reorder)
------------------------------------------------------------------------------
u_tx : entity work.unb1_board_mesh_reorder_tx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
- rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
- tx_phy_sosi_2arr => tx_phy_sosi_2arr,
- rx_phy_siso_2arr => rx_phy_siso_2arr
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ tx_usr_sosi_2arr => tx_term_sosi_2arr, -- g_use_tx
+ rx_usr_siso_2arr => rx_term_siso_2arr, -- g_use_rx
+ tx_phy_sosi_2arr => tx_phy_sosi_2arr,
+ rx_phy_siso_2arr => rx_phy_siso_2arr
+ );
u_rx : entity work.unb1_board_mesh_reorder_rx
- generic map (
- g_node_type => g_node_type,
- g_reorder => g_phy_ena_reorder
- )
- port map (
- chip_id => chip_id,
- clk => dp_clk,
- rx_phy_sosi_2arr => rx_phy_sosi_2arr,
- tx_phy_siso_2arr => tx_phy_siso_2arr,
- rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
- tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
- );
+ generic map (
+ g_node_type => g_node_type,
+ g_reorder => g_phy_ena_reorder
+ )
+ port map (
+ chip_id => chip_id,
+ clk => dp_clk,
+ rx_phy_sosi_2arr => rx_phy_sosi_2arr,
+ tx_phy_siso_2arr => tx_phy_siso_2arr,
+ rx_usr_sosi_2arr => rx_term_sosi_2arr, -- g_use_rx
+ tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
+ );
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
@@ -355,56 +367,57 @@ begin
-- Map 1-dim array on 2-dim array
gen_bus : for I in g_nof_bus - 1 downto 0 generate
+
gen_lane : for J in g_phy_nof_serial - 1 downto 0 generate
- -- SOSI
- tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
- tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
+ -- SOSI
+ tx_phy_sosi_arr(I * g_phy_nof_serial + J) <= tx_phy_sosi_2arr(I)(J);
+ tx_phy_siso_2arr(I)(J) <= tx_phy_siso_arr(I * g_phy_nof_serial + J);
- rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
- rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
+ rx_phy_sosi_2arr(I)(J) <= rx_phy_sosi_arr(I * g_phy_nof_serial + J);
+ rx_phy_siso_arr(I * g_phy_nof_serial + J) <= rx_phy_siso_2arr(I)(J);
- -- Serial
- tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
- rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
+ -- Serial
+ tx_serial_2arr(I)(J) <= tx_serial_arr(I * g_phy_nof_serial + J);
+ rx_serial_arr(I * g_phy_nof_serial + J) <= rx_serial_2arr(I)(J);
end generate;
end generate;
u_tr_nonbonded : entity tr_nonbonded_lib.mms_tr_nonbonded
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_data_w => c_phy_data_w,
- g_nof_gx => c_phy_nof_gx,
- g_mbps => g_phy_gx_mbps,
- g_tx => g_use_tx,
- g_rx => g_use_rx,
- g_rx_fifo_depth => g_phy_rx_fifo_size
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- tr_clk => tr_clk,
- cal_rec_clk => cal_clk,
-
- --Serial data I/O
- tx_dataout => tx_serial_arr,
- rx_datain => rx_serial_arr,
-
- --Streaming I/O
- snk_out_arr => tx_phy_siso_arr,
- snk_in_arr => tx_phy_sosi_arr,
-
- src_in_arr => rx_phy_siso_arr,
- src_out_arr => rx_phy_sosi_arr,
-
- tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
- tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
-
- diagnostics_mm_mosi => reg_diagnostics_mosi,
- diagnostics_mm_miso => reg_diagnostics_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_data_w => c_phy_data_w,
+ g_nof_gx => c_phy_nof_gx,
+ g_mbps => g_phy_gx_mbps,
+ g_tx => g_use_tx,
+ g_rx => g_use_rx,
+ g_rx_fifo_depth => g_phy_rx_fifo_size
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ tr_clk => tr_clk,
+ cal_rec_clk => cal_clk,
+
+ --Serial data I/O
+ tx_dataout => tx_serial_arr,
+ rx_datain => rx_serial_arr,
+
+ --Streaming I/O
+ snk_out_arr => tx_phy_siso_arr,
+ snk_in_arr => tx_phy_sosi_arr,
+
+ src_in_arr => rx_phy_siso_arr,
+ src_out_arr => rx_phy_sosi_arr,
+
+ tr_nonbonded_mm_mosi => reg_tr_nonbonded_mosi,
+ tr_nonbonded_mm_miso => reg_tr_nonbonded_miso,
+
+ diagnostics_mm_mosi => reg_diagnostics_mosi,
+ diagnostics_mm_miso => reg_diagnostics_miso
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
index 5bc2d1698e2f30dff83d3194158162ed750a55a2..2cf805ea257598b14f896835d1e54bc46bf40b16 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index 8645f86e8f80ca85685e98d3edef549b275d5a9c..d107844fb52d08b1ae39dfed4dd23aac60f1e38b 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb1_board_wdi_reg is
port (
@@ -40,19 +40,20 @@ entity unb1_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb1_board_wdi_reg;
architecture rtl of unb1_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- -- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- For safety, WDI override requires the following word to be written:
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
@@ -68,7 +69,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
if sla_in.wrdata(c_word_w - 1 downto 0) = c_cmd_reconfigure then
wdi_override <= '1';
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index ca4d940d7bb06aeace52fde1a3d53c77a8550a22..a9c0720d6a67d790cad11c9160e193c0fa73660b 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -32,17 +32,17 @@ entity tb_mms_unb1_board_sens is
end tb_mms_unb1_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb1_board_sens is
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
- constant c_clk_freq : natural := 100 * 10**6;
- constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
+ constant c_clk_freq : natural := 100 * 10 ** 6;
+ constant c_clk_period : time := (10 ** 9 / c_clk_freq) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
-- Model I2C sensor slaves as on the UniBoard
@@ -147,58 +147,58 @@ begin
-- I2C sensors master
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
index f489d4b5d4fbd2961b7a502c764f3e3eecb93b8e..608063dc99210c529e447166b5580d171cbdc56d 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
@@ -27,7 +27,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_tb_unb1_board_regression is
end tb_tb_tb_unb1_board_regression;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index c30e88c962f588450e0ebe8fe699809b789ffd3f..5edd44e3a2134aa03c49526032bda3542b7a687c 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_clk200_pll is
end tb_unb1_board_clk200_pll;
@@ -68,68 +68,68 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "0",
- g_clk200p_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "0",
+ g_clk200p_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 0, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=0 for clk200_pll.vhd
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_sel => 0, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=0 for clk200_pll.vhd
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb1_board_clk200_pll
- generic map (
- g_sel => 1, -- g_sel=0 for clk200_pll.vhd
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk200_phase_shift => "0",
- -- g_sel=1 for clk200_pll_p6.vhd
- g_clk0_phase_shift => "0",
- g_clk_vec_w => c_clk_vec_w,
- g_clk1_phase_shift => "0",
- g_clk2_phase_shift => "156",
- g_clk3_phase_shift => "313",
- g_clk4_phase_shift => "469",
- g_clk5_phase_shift => "625",
- g_clk6_phase_shift => "938",
- g_clk1_divide_by => c_clk_div,
- g_clk2_divide_by => c_clk_div,
- g_clk3_divide_by => c_clk_div,
- g_clk4_divide_by => c_clk_div,
- g_clk5_divide_by => c_clk_div,
- g_clk6_divide_by => c_clk_div
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200,
- -- . g_sel=1
- st_clk_vec => st_clk_vec
- );
+ generic map (
+ g_sel => 1, -- g_sel=0 for clk200_pll.vhd
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk200_phase_shift => "0",
+ -- g_sel=1 for clk200_pll_p6.vhd
+ g_clk0_phase_shift => "0",
+ g_clk_vec_w => c_clk_vec_w,
+ g_clk1_phase_shift => "0",
+ g_clk2_phase_shift => "156",
+ g_clk3_phase_shift => "313",
+ g_clk4_phase_shift => "469",
+ g_clk5_phase_shift => "625",
+ g_clk6_phase_shift => "938",
+ g_clk1_divide_by => c_clk_div,
+ g_clk2_divide_by => c_clk_div,
+ g_clk3_divide_by => c_clk_div,
+ g_clk4_divide_by => c_clk_div,
+ g_clk5_divide_by => c_clk_div,
+ g_clk6_divide_by => c_clk_div
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200,
+ -- . g_sel=1
+ st_clk_vec => st_clk_vec
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 1eaa6aa8070c062fe3b18135e3703eea919e7181..d95f9ef7d5da8b4a6931885d2787e62bf6dca56b 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -40,12 +40,12 @@
-- transceiver bus reorderings on UniBoard PCB.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity tb_unb1_board_mesh_reorder_bidir is
end tb_unb1_board_mesh_reorder_bidir;
@@ -181,7 +181,9 @@ begin
------------------------------------------------------------------------------
gen_node : for I in 0 to c_nof_node-1 generate
+
gen_bus : for J in 0 to c_nof_bus - 1 generate
+
gen_lanes : for K in c_bus_w - 1 downto 0 generate
-- SOSI
-- . Transmit order
@@ -220,27 +222,27 @@ begin
gen_fn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_fn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
- tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
- tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
- rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
- );
+ generic map (
+ g_node_type => e_fn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(I, c_chip_id_w), -- chip id 0, 1, 2, 3
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => fn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from FN user
+ tx_usr_siso_2arr => fn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to FN user
+ tx_phy_sosi_2arr => fn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => fn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => fn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => fn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => fn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to FN user
+ rx_usr_siso_2arr => fn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from FN user
+ );
end generate;
------------------------------------------------------------------------------
@@ -251,7 +253,9 @@ begin
-- Use tx_phy SOSI.valid stimuli for input to unb1_board_mesh_model_sl
gen_tx_serial : for I in 0 to c_nof_node-1 generate
+
gen_bus : for J in 0 to c_nof_bus - 1 generate
+
gen_lanes : for K in c_bus_w - 1 downto 0 generate
fn_tx_phy_sl_3arr(I)(J)(K) <= fn_tx_phy_sosi_3arr(I)(J)(K).valid;
bn_tx_phy_sl_3arr(I)(J)(K) <= bn_tx_phy_sosi_3arr(I)(J)(K).valid;
@@ -260,22 +264,24 @@ begin
end generate;
u_pcb_mesh_serial : entity work.unb1_board_mesh_model_sl
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
- bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
-
- -- BN to FN
- bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
- fn_rx_sl_3arr => fn_rx_phy_sl_3arr
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn_tx_sl_3arr => fn_tx_phy_sl_3arr,
+ bn_rx_sl_3arr => bn_rx_phy_sl_3arr,
+
+ -- BN to FN
+ bn_tx_sl_3arr => bn_tx_phy_sl_3arr,
+ fn_rx_sl_3arr => fn_rx_phy_sl_3arr
+ );
-- Use rx_phy SOSI.valid as reference output to verify output of unb1_board_mesh_model_sl
mon_rx_serial : for I in 0 to c_nof_node-1 generate
+
gen_bus : for J in 0 to c_nof_bus - 1 generate
+
gen_lanes : for K in c_bus_w - 1 downto 0 generate
-- Monitor SOSI valids in SLV
bn_rx_phy_valid((I * c_nof_bus + J) * c_bus_w + K) <= bn_rx_phy_sosi_3arr(I)(J)(K).valid;
@@ -298,62 +304,62 @@ begin
-- >>> unb1_board_mesh_model_sosi
u_pcb_mesh_sosi : entity work.unb1_board_mesh_model_sosi
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
- fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
- fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
- fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
-
- bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
- bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
- bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
- bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
-
- -- BN to FN
- bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
- bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
- bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
- bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
-
- fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
- fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
- fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
- fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_tx_sosi_2arr => fn_tx_phy_sosi_3arr(0),
+ fn1_tx_sosi_2arr => fn_tx_phy_sosi_3arr(1),
+ fn2_tx_sosi_2arr => fn_tx_phy_sosi_3arr(2),
+ fn3_tx_sosi_2arr => fn_tx_phy_sosi_3arr(3),
+
+ bn0_rx_sosi_2arr => bn_rx_phy_sosi_3arr(0),
+ bn1_rx_sosi_2arr => bn_rx_phy_sosi_3arr(1),
+ bn2_rx_sosi_2arr => bn_rx_phy_sosi_3arr(2),
+ bn3_rx_sosi_2arr => bn_rx_phy_sosi_3arr(3),
+
+ -- BN to FN
+ bn0_tx_sosi_2arr => bn_tx_phy_sosi_3arr(0),
+ bn1_tx_sosi_2arr => bn_tx_phy_sosi_3arr(1),
+ bn2_tx_sosi_2arr => bn_tx_phy_sosi_3arr(2),
+ bn3_tx_sosi_2arr => bn_tx_phy_sosi_3arr(3),
+
+ fn0_rx_sosi_2arr => fn_rx_phy_sosi_3arr(0),
+ fn1_rx_sosi_2arr => fn_rx_phy_sosi_3arr(1),
+ fn2_rx_sosi_2arr => fn_rx_phy_sosi_3arr(2),
+ fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
+ );
-- >>> unb1_board_mesh_model_siso
u_pcb_mesh_siso : entity work.unb1_board_mesh_model_siso
- generic map (
- g_reorder => c_reorder
- )
- port map (
- -- FN to BN
- fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
- fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
- fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
- fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
-
- bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
- bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
- bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
- bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
-
- -- BN to FN
- bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
- bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
- bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
- bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
-
- fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
- fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
- fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
- fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
- );
+ generic map (
+ g_reorder => c_reorder
+ )
+ port map (
+ -- FN to BN
+ fn0_rx_siso_2arr => fn_rx_phy_siso_3arr(0),
+ fn1_rx_siso_2arr => fn_rx_phy_siso_3arr(1),
+ fn2_rx_siso_2arr => fn_rx_phy_siso_3arr(2),
+ fn3_rx_siso_2arr => fn_rx_phy_siso_3arr(3),
+
+ bn0_tx_siso_2arr => bn_tx_phy_siso_3arr(0),
+ bn1_tx_siso_2arr => bn_tx_phy_siso_3arr(1),
+ bn2_tx_siso_2arr => bn_tx_phy_siso_3arr(2),
+ bn3_tx_siso_2arr => bn_tx_phy_siso_3arr(3),
+
+ -- BN to FN
+ bn0_rx_siso_2arr => bn_rx_phy_siso_3arr(0),
+ bn1_rx_siso_2arr => bn_rx_phy_siso_3arr(1),
+ bn2_rx_siso_2arr => bn_rx_phy_siso_3arr(2),
+ bn3_rx_siso_2arr => bn_rx_phy_siso_3arr(3),
+
+ fn0_tx_siso_2arr => fn_tx_phy_siso_3arr(0),
+ fn1_tx_siso_2arr => fn_tx_phy_siso_3arr(1),
+ fn2_tx_siso_2arr => fn_tx_phy_siso_3arr(2),
+ fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
+ );
------------------------------------------------------------------------------
-- UniBoard BN0,1,2,3
@@ -361,27 +367,26 @@ begin
gen_bn : for I in 0 to c_nof_node-1 generate
u_order : entity work.unb1_board_mesh_reorder_bidir
- generic map (
- g_node_type => e_bn,
- g_reorder => c_reorder
- )
- port map (
- chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
-
- -- Transmit clock domain
- tx_clk => clk,
- tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
- tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
- tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
- tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
-
- -- Receive clock domain
- rx_clk => clk,
- rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
- rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
- rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
- rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
- );
+ generic map (
+ g_node_type => e_bn,
+ g_reorder => c_reorder
+ )
+ port map (
+ chip_id => TO_UVEC(c_nof_node + I, c_chip_id_w), -- chip id 4, 5, 6, 7
+
+ -- Transmit clock domain
+ tx_clk => clk,
+ tx_usr_sosi_2arr => bn_tx_usr_sosi_3arr(I), -- user sosi to phy = sosi.valid driver from BN user
+ tx_usr_siso_2arr => bn_tx_usr_siso_3arr(I), -- user siso from phy = siso.ready result to BN user
+ tx_phy_sosi_2arr => bn_tx_phy_sosi_3arr(I), -- phy sosi to mesh
+ tx_phy_siso_2arr => bn_tx_phy_siso_3arr(I), -- phy siso from mesh
+
+ -- Receive clock domain
+ rx_clk => clk,
+ rx_phy_sosi_2arr => bn_rx_phy_sosi_3arr(I), -- phy sosi from mesh
+ rx_phy_siso_2arr => bn_rx_phy_siso_3arr(I), -- phy siso to mesh
+ rx_usr_sosi_2arr => bn_rx_usr_sosi_3arr(I), -- user sosi from phy = sosi.valid result to BN user
+ rx_usr_siso_2arr => bn_rx_usr_siso_3arr(I) -- user siso to phy = siso.ready driver from BN user
+ );
end generate;
-
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index de88c784052fc566fbc1eb57b3421a3d233e5bdb..bb724d59f86cbaca8713307592ec2bb3b28fedfd 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb1_board_node_ctrl is
end tb_unb1_board_node_ctrl;
@@ -76,22 +76,22 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb1_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => sys_rst,
- wdi_in => wdi_in,
- wdi_out => wdi_out,
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => sys_rst,
+ wdi_in => wdi_in,
+ wdi_out => wdi_out,
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
index f404f0a478c97d124b41261aa6adcb672de693b8..09df5093c494938f529845e095885b7da2d84679 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
package tb_unb1_board_pkg is
-- Aggregate types to contain all TR for all nodes on one side of the mesh or backplane interface
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 59579fcd400bcbb69b4f32f9db8e55211e2480ef..51be36531904ba4e29622d9859a71260cd03a2eb 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -35,11 +35,11 @@
-- . Phy bus 3 is not used and left not connected on the backplane.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sl is
port (
@@ -77,5 +77,4 @@ begin
-- | Same scheme applies to all back nodes
-- Receiving UniBoard
end generate;
-
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index 6262f52ab7711cb61a488128ea3ad22a12e0dfe7..d4ba18aab75cbc31dd27a123327ad0b71e9c774b 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -25,11 +25,11 @@
-- Model the backplane at sosi level. See unb1_board_back_model_sl for more details.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_back_model_sosi is
port (
@@ -67,5 +67,4 @@ begin
-- | Same scheme applies to all back nodes
-- Receiving UniBoard
end generate;
-
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index c186f45bb476e7f843cdff7ffbc25496406a61b1..2dd293a791fa3912249f9ab508d70be83746b3e9 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_siso is
generic (
@@ -108,7 +108,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_tx_siso_2arr(0) <= fn3_rx_siso_2arr(1); -- 0,0 <= 3,1
bn0_tx_siso_2arr(1) <= fn2_rx_siso_2arr(0); -- 0,1 <= 2,0
bn0_tx_siso_2arr(2) <= fn1_rx_siso_2arr(0); -- 0,2 <= 1,0
@@ -129,7 +129,7 @@ begin
bn3_tx_siso_2arr(2) <= fn2_rx_siso_2arr(3); -- 3,2 <= 2,3
bn3_tx_siso_2arr(3) <= fn1_rx_siso_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_tx_siso_2arr(0) <= bn0_rx_siso_2arr(3); -- 0,0 <= 0,3
fn0_tx_siso_2arr(1) <= bn3_rx_siso_2arr(1); -- 0,1 <= 3,1
fn0_tx_siso_2arr(2) <= bn2_rx_siso_2arr(2); -- 0,2 <= 2,2
@@ -150,5 +150,4 @@ begin
fn3_tx_siso_2arr(2) <= bn2_rx_siso_2arr(0); -- 3,2 <= 2,0
fn3_tx_siso_2arr(3) <= bn3_rx_siso_2arr(0); -- 3,3 <= 3,0
end generate;
-
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 11019e63c4c6db0e5fa6280786b6ca49c7c64b18..784e43e4571f80af00efcc6d298b7464570a909e 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -25,12 +25,12 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
-use work.tb_unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
+ use work.tb_unb1_board_pkg.all;
entity unb1_board_mesh_model_sl is
generic (
@@ -54,6 +54,7 @@ begin
-- BN(i)(j) <= FN(j)(i)
-- FN(i)(j) <= BN(j)(i)
gen_i : for i in 0 to 3 generate
+
gen_j : for j in 0 to 3 generate
bn_rx_sl_3arr(i)(j) <= fn_tx_sl_3arr(j)(i);
fn_rx_sl_3arr(i)(j) <= bn_tx_sl_3arr(j)(i);
@@ -63,7 +64,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn_rx_sl_3arr(0)(0) <= fn_tx_sl_3arr(3)(1); -- 0,0 <= 3,1
bn_rx_sl_3arr(0)(1) <= fn_tx_sl_3arr(2)(0); -- 0,1 <= 2,0
bn_rx_sl_3arr(0)(2) <= fn_tx_sl_3arr(1)(0); -- 0,2 <= 1,0
@@ -84,7 +85,7 @@ begin
bn_rx_sl_3arr(3)(2) <= fn_tx_sl_3arr(2)(3); -- 3,2 <= 2,3
bn_rx_sl_3arr(3)(3) <= fn_tx_sl_3arr(1)(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn_rx_sl_3arr(0)(0) <= bn_tx_sl_3arr(0)(3); -- 0,0 <= 0,3
fn_rx_sl_3arr(0)(1) <= bn_tx_sl_3arr(3)(1); -- 0,1 <= 3,1
fn_rx_sl_3arr(0)(2) <= bn_tx_sl_3arr(2)(2); -- 0,2 <= 2,2
@@ -105,5 +106,4 @@ begin
fn_rx_sl_3arr(3)(2) <= bn_tx_sl_3arr(2)(0); -- 3,2 <= 2,0
fn_rx_sl_3arr(3)(3) <= bn_tx_sl_3arr(3)(0); -- 3,3 <= 3,0
end generate;
-
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index 17a37b3c881936f1a33457affc22e200b3e28df2..4c960adde8efe08d1b2cedc078f48ce05aa73520 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -24,11 +24,11 @@
-- Description: See unb1_board_mesh_reorder_bidir.vhd
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb1_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb1_board_pkg.all;
entity unb1_board_mesh_model_sosi is
generic (
@@ -108,7 +108,7 @@ begin
-- Actual UniBoard PCB mesh connect for transpose
gen_reorder : if g_reorder = true generate
- -- BN, phy <= FN, phy
+ -- BN, phy <= FN, phy
bn0_rx_sosi_2arr(0) <= fn3_tx_sosi_2arr(1); -- 0,0 <= 3,1
bn0_rx_sosi_2arr(1) <= fn2_tx_sosi_2arr(0); -- 0,1 <= 2,0
bn0_rx_sosi_2arr(2) <= fn1_tx_sosi_2arr(0); -- 0,2 <= 1,0
@@ -129,7 +129,7 @@ begin
bn3_rx_sosi_2arr(2) <= fn2_tx_sosi_2arr(3); -- 3,2 <= 2,3
bn3_rx_sosi_2arr(3) <= fn1_tx_sosi_2arr(2); -- 3,3 <= 1,2
- -- FN, phy <= BN, phy
+ -- FN, phy <= BN, phy
fn0_rx_sosi_2arr(0) <= bn0_tx_sosi_2arr(3); -- 0,0 <= 0,3
fn0_rx_sosi_2arr(1) <= bn3_tx_sosi_2arr(1); -- 0,1 <= 3,1
fn0_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(2); -- 0,2 <= 2,2
@@ -150,5 +150,4 @@ begin
fn3_rx_sosi_2arr(2) <= bn2_tx_sosi_2arr(0); -- 3,2 <= 2,0
fn3_rx_sosi_2arr(3) <= bn3_tx_sosi_2arr(0); -- 3,3 <= 3,0
end generate;
-
end beh;
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index ebe9c5d3e787e0ac953101ca9ea487f6c94d337b..54eb78e0056131cfc09d1eaf6c51089a3ff89c40 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_led is
generic (
@@ -99,15 +99,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -118,40 +118,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity unb2_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity unb2_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
@@ -177,17 +177,17 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : common_lib.common_pulse_extend
generic map (
@@ -201,12 +201,12 @@ begin
);
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 71ff33a36be4bde8faadd07cc53b7d83f610e40f..257ecaa76346177874f8d60f981a9e1108b9c0b1 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -39,18 +39,18 @@
--
library IEEE, common_lib, unb2_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_led is
- generic (
- g_design_name : string := "unb2_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_led;
architecture tb of tb_unb2_led is
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 2bd1ab97d597736b53b76506cb5b59a2d9c06e35..0f143272d342929fa609c8c7762565c12160df35 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2_minimal_pkg.all;
entity mmm_unb2_minimal is
generic (
@@ -110,33 +110,43 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -291,7 +301,6 @@ begin
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
index 305c225eae2455dcf6574d3992aa4340e2dfd4fe..bae95c115b132477a57ba74d7ec1c9d61bd65929 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -20,136 +20,135 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
-
- component qsys_unb2_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_minimal;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_minimal;
end qsys_unb2_minimal_pkg;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index c0ae33a4c217ae760f46c77bea8ca1b18d5a84e8..9aa1b2df9befe48a7e45feb43a1aa416fe32b6f9 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
entity unb2_minimal is
generic (
@@ -156,219 +156,219 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ QSFP_LED => QSFP_LED
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
--- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_factory_image => g_factory_image,
--- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
--- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
--- )
--- PORT MAP (
--- rst => mm_rst,
--- clk => mm_clk,
--- green_led_arr => qsfp_green_led_arr,
--- red_led_arr => qsfp_red_led_arr
--- );
---
--- u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
--- GENERIC MAP (
--- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
--- )
--- PORT MAP (
--- green_led_arr => qsfp_green_led_arr,
--- red_led_arr => qsfp_red_led_arr,
--- QSFP_LED => QSFP_LED
--- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
+
+ -- u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_factory_image => g_factory_image,
+ -- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ -- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ -- )
+ -- PORT MAP (
+ -- rst => mm_rst,
+ -- clk => mm_clk,
+ -- green_led_arr => qsfp_green_led_arr,
+ -- red_led_arr => qsfp_red_led_arr
+ -- );
+ --
+ -- u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
+ -- GENERIC MAP (
+ -- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ -- )
+ -- PORT MAP (
+ -- green_led_arr => qsfp_green_led_arr,
+ -- red_led_arr => qsfp_red_led_arr,
+ -- QSFP_LED => QSFP_LED
+ -- );
end str;
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index 5f1ebd006c75218dd65ffee60766d2b82c741210..41cdac2354d369ffe6d8a07c3b00ec0cd0a57277 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2_minimal is
- generic (
- g_design_name : string := "unb2_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2_minimal;
architecture tb of tb_unb2_minimal is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 24a8174ff6cb64308949e445ebd127229d2e1b41..2bd18d0c0194eb93f7167c3e5e3e9c91e02e1c0e 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_pinning is
port (
@@ -131,8 +131,8 @@ entity unb2_pinning is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -141,184 +141,184 @@ entity unb2_pinning is
end unb2_pinning;
architecture str of unb2_pinning is
- component ddr4 is
- port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic -- readdatavalid
- );
- end component ddr4;
-
- component transceiver_phy is
- port (
- tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(47 downto 0); -- clk
- rx_clkout : out std_logic_vector(47 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(383 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
- );
- end component transceiver_phy;
-
- component transceiver_phy_24channel is
- port (
- tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
- tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
- rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
- rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
- tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
- rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
- rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_cdr_refclk0 : in std_logic := 'X'; -- clk
- tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
- rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
- tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
- tx_clkout : out std_logic_vector(23 downto 0); -- clk
- rx_clkout : out std_logic_vector(23 downto 0); -- clk
- tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
- rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
- rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
- tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
- tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
- tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
- unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
- unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
- rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
- rx_control : out std_logic_vector(191 downto 0); -- rx_control
- unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
- unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
- );
- end component transceiver_phy_24channel;
-
- component transceiver_reset_controller is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller;
-
- component transceiver_reset_controller_24 is
- port (
- clock : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
- tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
- rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
- rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
- rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
- rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
- );
- end component transceiver_reset_controller_24;
-
- component transceiver_pll is
- port (
- pll_powerdown : in std_logic := 'X'; -- pll_powerdown
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_locked : out std_logic; -- pll_locked
- pll_cal_busy : out std_logic; -- pll_cal_busy
- mcgb_rst : in std_logic := 'X'; -- mcgb_rst
- mcgb_serial_clk : out std_logic -- clk
- );
- end component transceiver_pll;
-
- component sys_clkctrl is
- port (
- inclk : in std_logic := 'X'; -- inclk
- outclk : out std_logic -- outclk
- );
- end component sys_clkctrl;
-
- component system_pll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component ddr4 is
+ port (
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_alert_n : in std_logic_vector(0 downto 0); -- mem_alert_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par ** new in 14.0 **
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic; -- local_cal_fail
+ emif_usr_reset_n : out std_logic; -- reset_n
+ emif_usr_clk : out std_logic; -- clk
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address ** chg from 23 bits in 14.0 **
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount ** chg from 8 bits in 14.0 **
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic -- readdatavalid
+ );
+ end component ddr4;
+
+ component transceiver_phy is
+ port (
+ tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(47 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(47 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(47 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(47 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(47 downto 0); -- clk
+ rx_clkout : out std_logic_vector(47 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(47 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(47 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(3071 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(431 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(3071 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(383 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(3071 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(575 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy;
+
+ component transceiver_phy_24channel is
+ port (
+ tx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_digitalreset
+ rx_analogreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_digitalreset : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_digitalreset
+ tx_cal_busy : out std_logic_vector(23 downto 0); -- tx_cal_busy
+ rx_cal_busy : out std_logic_vector(23 downto 0); -- rx_cal_busy
+ rx_is_lockedtodata : out std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ tx_serial_clk0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_cdr_refclk0 : in std_logic := 'X'; -- clk
+ tx_serial_data : out std_logic_vector(23 downto 0); -- tx_serial_data
+ rx_serial_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_serial_data
+ tx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ rx_coreclkin : in std_logic_vector(23 downto 0) := (others => 'X'); -- clk
+ tx_clkout : out std_logic_vector(23 downto 0); -- clk
+ rx_clkout : out std_logic_vector(23 downto 0); -- clk
+ tx_enh_data_valid : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_enh_data_valid
+ rx_enh_data_valid : out std_logic_vector(23 downto 0); -- rx_enh_data_valid
+ rx_enh_blk_lock : out std_logic_vector(23 downto 0); -- rx_enh_blk_lock
+ tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- tx_parallel_data
+ tx_control : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_control
+ tx_err_ins : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_err_ins
+ unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => 'X'); -- unused_tx_parallel_data
+ unused_tx_control : in std_logic_vector(215 downto 0) := (others => 'X'); -- unused_tx_control
+ rx_parallel_data : out std_logic_vector(1535 downto 0); -- rx_parallel_data
+ rx_control : out std_logic_vector(191 downto 0); -- rx_control
+ unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data
+ unused_rx_control : out std_logic_vector(287 downto 0) -- unused_rx_control
+ );
+ end component transceiver_phy_24channel;
+
+ component transceiver_reset_controller is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(47 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(47 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(47 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(47 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(47 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(47 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(47 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(47 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller;
+
+ component transceiver_reset_controller_24 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ tx_analogreset : out std_logic_vector(23 downto 0); -- tx_analogreset
+ tx_digitalreset : out std_logic_vector(23 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(23 downto 0); -- tx_ready
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ tx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_cal_busy
+ rx_analogreset : out std_logic_vector(23 downto 0); -- rx_analogreset
+ rx_digitalreset : out std_logic_vector(23 downto 0); -- rx_digitalreset
+ rx_ready : out std_logic_vector(23 downto 0); -- rx_ready
+ rx_is_lockedtodata : in std_logic_vector(23 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_cal_busy : in std_logic_vector(23 downto 0) := (others => 'X') -- rx_cal_busy
+ );
+ end component transceiver_reset_controller_24;
+
+ component transceiver_pll is
+ port (
+ pll_powerdown : in std_logic := 'X'; -- pll_powerdown
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_locked : out std_logic; -- pll_locked
+ pll_cal_busy : out std_logic; -- pll_cal_busy
+ mcgb_rst : in std_logic := 'X'; -- mcgb_rst
+ mcgb_serial_clk : out std_logic -- clk
+ );
+ end component transceiver_pll;
+
+ component sys_clkctrl is
+ port (
+ inclk : in std_logic := 'X'; -- inclk
+ outclk : out std_logic -- outclk
+ );
+ end component sys_clkctrl;
+
+ component system_pll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_pll;
- component system_fpll is
- port (
- pll_refclk0 : in std_logic := 'X'; -- clk
- pll_powerdown : in std_logic := 'X';
- pll_locked : out std_logic;
- pll_cal_busy : out std_logic;
- outclk0 : out std_logic; -- outclk0
- outclk1 : out std_logic; -- outclk1
- outclk2 : out std_logic -- outclk2
- );
+ component system_fpll is
+ port (
+ pll_refclk0 : in std_logic := 'X'; -- clk
+ pll_powerdown : in std_logic := 'X';
+ pll_locked : out std_logic;
+ pll_cal_busy : out std_logic;
+ outclk0 : out std_logic; -- outclk0
+ outclk1 : out std_logic; -- outclk1
+ outclk2 : out std_logic -- outclk2
+ );
end component system_fpll;
component unb2_pinning_qsys is
@@ -381,608 +381,608 @@ architecture str of unb2_pinning is
eth_tse_1_serial_connection_txp_0 : out std_logic; -- txp
pio_0_external_connection_export : in std_logic_vector(11 downto 0) := (others => 'X') -- export
- );
+ );
end component unb2_pinning_qsys;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
-
- -- general reset and clock signals
- signal reset_n : std_logic;
- signal reset_p : std_logic;
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
- signal CLK_buffered : std_logic := '0';
-
- -- signals for the ddr4 controllers
- signal local_i_cal_success : std_logic;
- signal local_i_cal_fail : std_logic;
- signal local_i_reset_n : std_logic;
- signal local_i_clk : std_logic;
- signal local_i_ready : std_logic;
- signal local_i_read : std_logic;
- signal local_i_write : std_logic;
- signal local_i_address : std_logic_vector(26 downto 0);
- signal local_i_readdata : std_logic_vector(575 downto 0);
- signal local_i_writedata : std_logic_vector(575 downto 0);
- signal local_i_burstcount : std_logic_vector(6 downto 0);
- signal local_i_be : std_logic_vector(71 downto 0);
- signal local_i_read_data_valid : std_logic;
- signal mb_i_a_internal : std_logic_vector(16 downto 0);
- signal local_ii_cal_success : std_logic;
- signal local_ii_cal_fail : std_logic;
- signal local_ii_reset_n : std_logic;
- signal local_ii_clk : std_logic;
- signal local_ii_ready : std_logic;
- signal local_ii_read : std_logic;
- signal local_ii_write : std_logic;
- signal local_ii_address : std_logic_vector(26 downto 0);
- signal local_ii_readdata : std_logic_vector(575 downto 0);
- signal local_ii_writedata : std_logic_vector(575 downto 0);
- signal local_ii_burstcount : std_logic_vector(6 downto 0);
- signal local_ii_be : std_logic_vector(71 downto 0);
- signal local_ii_read_data_valid: std_logic;
- signal mb_ii_a_internal : std_logic_vector(16 downto 0);
-
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(47 downto 0);
- signal rx_serial_data_front : std_logic_vector(47 downto 0);
- signal dataloopback_front : std_logic_vector(3071 downto 0);
- signal controlloopback_front : std_logic_vector(383 downto 0);
- signal tx_serdesclk_front : std_logic_vector(47 downto 0);
- signal validloopback_front : std_logic_vector(47 downto 0);
- signal tx_analogreset_front : std_logic_vector(47 downto 0);
- signal tx_digitalreset_front : std_logic_vector(47 downto 0);
- signal rx_analogreset_front : std_logic_vector(47 downto 0);
- signal rx_digitalreset_front : std_logic_vector(47 downto 0);
- signal tx_cal_busy_front : std_logic_vector(47 downto 0);
- signal rx_cal_busy_front : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
- signal pll_cal_busy_front : std_logic;
- signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
- signal pll_powerdown_front : std_logic_vector(0 downto 0);
- signal pll_locked_front : std_logic_vector(0 downto 0);
- signal tx_serial_clk_front : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_front : std_logic;
-
- signal tx_serial_data_back : std_logic_vector(47 downto 0);
- signal rx_serial_data_back : std_logic_vector(47 downto 0);
- signal dataloopback_back : std_logic_vector(3071 downto 0);
- signal controlloopback_back : std_logic_vector(383 downto 0);
- signal dataloopback_test : std_logic_vector(1535 downto 0);
- signal controlloopback_test : std_logic_vector(191 downto 0);
- signal tx_serdesclk_back : std_logic_vector(47 downto 0);
- signal validloopback_back : std_logic_vector(47 downto 0);
- signal tx_analogreset_back : std_logic_vector(47 downto 0);
- signal tx_digitalreset_back : std_logic_vector(47 downto 0);
- signal rx_analogreset_back : std_logic_vector(47 downto 0);
- signal rx_digitalreset_back : std_logic_vector(47 downto 0);
- signal tx_cal_busy_back : std_logic_vector(47 downto 0);
- signal rx_cal_busy_back : std_logic_vector(47 downto 0);
- signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
- signal pll_cal_busy_back_upper : std_logic;
- signal pll_cal_busy_back_lower : std_logic;
- signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
- signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
- signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
- signal pll_locked_back_upper : std_logic_vector(0 downto 0);
- signal pll_locked_back_lower : std_logic_vector(0 downto 0);
- signal tx_serial_clk_back : std_logic_vector(47 downto 0);
- signal mcgb_serial_clk_back_upper : std_logic;
- signal mcgb_serial_clk_back_lower : std_logic;
-
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+
+ -- general reset and clock signals
+ signal reset_n : std_logic;
+ signal reset_p : std_logic;
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
+ signal CLK_buffered : std_logic := '0';
+
+ -- signals for the ddr4 controllers
+ signal local_i_cal_success : std_logic;
+ signal local_i_cal_fail : std_logic;
+ signal local_i_reset_n : std_logic;
+ signal local_i_clk : std_logic;
+ signal local_i_ready : std_logic;
+ signal local_i_read : std_logic;
+ signal local_i_write : std_logic;
+ signal local_i_address : std_logic_vector(26 downto 0);
+ signal local_i_readdata : std_logic_vector(575 downto 0);
+ signal local_i_writedata : std_logic_vector(575 downto 0);
+ signal local_i_burstcount : std_logic_vector(6 downto 0);
+ signal local_i_be : std_logic_vector(71 downto 0);
+ signal local_i_read_data_valid : std_logic;
+ signal mb_i_a_internal : std_logic_vector(16 downto 0);
+ signal local_ii_cal_success : std_logic;
+ signal local_ii_cal_fail : std_logic;
+ signal local_ii_reset_n : std_logic;
+ signal local_ii_clk : std_logic;
+ signal local_ii_ready : std_logic;
+ signal local_ii_read : std_logic;
+ signal local_ii_write : std_logic;
+ signal local_ii_address : std_logic_vector(26 downto 0);
+ signal local_ii_readdata : std_logic_vector(575 downto 0);
+ signal local_ii_writedata : std_logic_vector(575 downto 0);
+ signal local_ii_burstcount : std_logic_vector(6 downto 0);
+ signal local_ii_be : std_logic_vector(71 downto 0);
+ signal local_ii_read_data_valid: std_logic;
+ signal mb_ii_a_internal : std_logic_vector(16 downto 0);
+
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(47 downto 0);
+ signal rx_serial_data_front : std_logic_vector(47 downto 0);
+ signal dataloopback_front : std_logic_vector(3071 downto 0);
+ signal controlloopback_front : std_logic_vector(383 downto 0);
+ signal tx_serdesclk_front : std_logic_vector(47 downto 0);
+ signal validloopback_front : std_logic_vector(47 downto 0);
+ signal tx_analogreset_front : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal rx_analogreset_front : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_front : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_front : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_front : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_front : std_logic;
+ signal rx_is_lockedtodata_front: std_logic_vector(47 downto 0);
+ signal pll_powerdown_front : std_logic_vector(0 downto 0);
+ signal pll_locked_front : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_front : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_front : std_logic;
+
+ signal tx_serial_data_back : std_logic_vector(47 downto 0);
+ signal rx_serial_data_back : std_logic_vector(47 downto 0);
+ signal dataloopback_back : std_logic_vector(3071 downto 0);
+ signal controlloopback_back : std_logic_vector(383 downto 0);
+ signal dataloopback_test : std_logic_vector(1535 downto 0);
+ signal controlloopback_test : std_logic_vector(191 downto 0);
+ signal tx_serdesclk_back : std_logic_vector(47 downto 0);
+ signal validloopback_back : std_logic_vector(47 downto 0);
+ signal tx_analogreset_back : std_logic_vector(47 downto 0);
+ signal tx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal rx_analogreset_back : std_logic_vector(47 downto 0);
+ signal rx_digitalreset_back : std_logic_vector(47 downto 0);
+ signal tx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal rx_cal_busy_back : std_logic_vector(47 downto 0);
+ signal txpll_cal_busy_back : std_logic_vector(47 downto 0);
+ signal pll_cal_busy_back_upper : std_logic;
+ signal pll_cal_busy_back_lower : std_logic;
+ signal rx_is_lockedtodata_back: std_logic_vector(47 downto 0);
+ signal pll_powerdown_back_upper : std_logic_vector(0 downto 0);
+ signal pll_powerdown_back_lower : std_logic_vector(0 downto 0);
+ signal pll_locked_back_upper : std_logic_vector(0 downto 0);
+ signal pll_locked_back_lower : std_logic_vector(0 downto 0);
+ signal tx_serial_clk_back : std_logic_vector(47 downto 0);
+ signal mcgb_serial_clk_back_upper : std_logic;
+ signal mcgb_serial_clk_back_lower : std_logic;
+
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
begin
- WDI <= 'Z';
-
- -- ****** DDR4 memory controllers ******
-
- mb_i_a <= mb_i_a_internal(13 downto 0);
- mb_i_we_a14 <= mb_i_a_internal(14);
- mb_i_cas_a15 <= mb_i_a_internal(15);
- mb_i_ras_a16 <= mb_i_a_internal(16);
-
- local_i_proc : process(local_i_clk, local_i_reset_n)
- begin
- if local_i_reset_n = '0' then
- local_i_read <= '0';
- local_i_write <= '0';
- local_i_address <= (others => '0');
- local_i_writedata <= (others => '0');
- local_i_burstcount <= (others => '0');
- local_i_be <= (others => '0');
- else
- if local_i_clk'event and local_i_clk = '1' then
- local_i_be <= (others => '1');
- if local_i_ready = '1' then
- local_i_read <= not local_i_read;
- local_i_write <= local_i_read_data_valid;
- local_i_address <= local_i_address + 1;
- if local_i_read_data_valid = '1' then
- local_i_writedata <= not local_i_readdata;
- else
- local_i_writedata <= (others => '1');
- end if;
+ WDI <= 'Z';
+
+ -- ****** DDR4 memory controllers ******
+
+ mb_i_a <= mb_i_a_internal(13 downto 0);
+ mb_i_we_a14 <= mb_i_a_internal(14);
+ mb_i_cas_a15 <= mb_i_a_internal(15);
+ mb_i_ras_a16 <= mb_i_a_internal(16);
+
+ local_i_proc : process(local_i_clk, local_i_reset_n)
+ begin
+ if local_i_reset_n = '0' then
+ local_i_read <= '0';
+ local_i_write <= '0';
+ local_i_address <= (others => '0');
+ local_i_writedata <= (others => '0');
+ local_i_burstcount <= (others => '0');
+ local_i_be <= (others => '0');
+ else
+ if local_i_clk'event and local_i_clk = '1' then
+ local_i_be <= (others => '1');
+ if local_i_ready = '1' then
+ local_i_read <= not local_i_read;
+ local_i_write <= local_i_read_data_valid;
+ local_i_address <= local_i_address + 1;
+ if local_i_read_data_valid = '1' then
+ local_i_writedata <= not local_i_readdata;
+ else
+ local_i_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_i : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_I_REF_CLK,
- oct_rzqin => MB_I_RZQ,
- mem_ck => mb_i_ck,
- mem_ck_n => mb_i_ck_n,
- mem_a => mb_i_a_internal,
- mem_act_n => mb_i_act_n,
- mem_ba => mb_i_ba,
- mem_bg => mb_i_bg,
- mem_cke => mb_i_cke,
- mem_cs_n => mb_i_cs,
- mem_odt => mb_i_odt,
- mem_reset_n => mb_i_reset_n,
- mem_alert_n => mb_i_alert_n,
- mem_par => mb_i_parity,
- mem_dqs => mb_i_dqs,
- mem_dqs_n => mb_i_dqs_n,
- mem_dq(63 downto 0) => mb_i_dq,
- mem_dq(71 downto 64) => mb_i_cb,
- mem_dbi_n => mb_i_dm,
- local_cal_success => local_i_cal_success,
- local_cal_fail => local_i_cal_fail,
- emif_usr_reset_n => local_i_reset_n,
- emif_usr_clk => local_i_clk,
- amm_ready_0 => local_i_ready,
- amm_read_0 => local_i_read,
- amm_write_0 => local_i_write,
- amm_address_0 => local_i_address,
- amm_readdata_0 => local_i_readdata,
- amm_writedata_0 => local_i_writedata,
- amm_burstcount_0 => local_i_burstcount,
- amm_byteenable_0 => local_i_be,
- amm_readdatavalid_0 => local_i_read_data_valid
- );
-
- mb_ii_a <= mb_ii_a_internal(13 downto 0);
- mb_ii_we_a14 <= mb_ii_a_internal(14);
- mb_ii_cas_a15 <= mb_ii_a_internal(15);
- mb_ii_ras_a16 <= mb_ii_a_internal(16);
-
- local_ii_proc : process(local_ii_clk, local_ii_reset_n)
- begin
- if local_ii_reset_n = '0' then
- local_ii_read <= '0';
- local_ii_write <= '0';
- local_ii_address <= (others => '0');
- local_ii_writedata <= (others => '0');
- local_ii_burstcount <= (others => '0');
- local_ii_be <= (others => '0');
- else
- if local_ii_clk'event and local_ii_clk = '1' then
- local_ii_be <= (others => '1');
- if local_ii_ready = '1' then
- local_ii_read <= not local_ii_read;
- local_ii_write <= local_ii_read_data_valid;
- local_ii_address <= local_ii_address + 1;
- if local_ii_read_data_valid = '1' then
- local_ii_writedata <= not local_ii_readdata;
- else
- local_ii_writedata <= (others => '1');
- end if;
+ end if;
+ end process;
+
+ u_ddr4_i : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_I_REF_CLK,
+ oct_rzqin => MB_I_RZQ,
+ mem_ck => mb_i_ck,
+ mem_ck_n => mb_i_ck_n,
+ mem_a => mb_i_a_internal,
+ mem_act_n => mb_i_act_n,
+ mem_ba => mb_i_ba,
+ mem_bg => mb_i_bg,
+ mem_cke => mb_i_cke,
+ mem_cs_n => mb_i_cs,
+ mem_odt => mb_i_odt,
+ mem_reset_n => mb_i_reset_n,
+ mem_alert_n => mb_i_alert_n,
+ mem_par => mb_i_parity,
+ mem_dqs => mb_i_dqs,
+ mem_dqs_n => mb_i_dqs_n,
+ mem_dq(63 downto 0) => mb_i_dq,
+ mem_dq(71 downto 64) => mb_i_cb,
+ mem_dbi_n => mb_i_dm,
+ local_cal_success => local_i_cal_success,
+ local_cal_fail => local_i_cal_fail,
+ emif_usr_reset_n => local_i_reset_n,
+ emif_usr_clk => local_i_clk,
+ amm_ready_0 => local_i_ready,
+ amm_read_0 => local_i_read,
+ amm_write_0 => local_i_write,
+ amm_address_0 => local_i_address,
+ amm_readdata_0 => local_i_readdata,
+ amm_writedata_0 => local_i_writedata,
+ amm_burstcount_0 => local_i_burstcount,
+ amm_byteenable_0 => local_i_be,
+ amm_readdatavalid_0 => local_i_read_data_valid
+ );
+
+ mb_ii_a <= mb_ii_a_internal(13 downto 0);
+ mb_ii_we_a14 <= mb_ii_a_internal(14);
+ mb_ii_cas_a15 <= mb_ii_a_internal(15);
+ mb_ii_ras_a16 <= mb_ii_a_internal(16);
+
+ local_ii_proc : process(local_ii_clk, local_ii_reset_n)
+ begin
+ if local_ii_reset_n = '0' then
+ local_ii_read <= '0';
+ local_ii_write <= '0';
+ local_ii_address <= (others => '0');
+ local_ii_writedata <= (others => '0');
+ local_ii_burstcount <= (others => '0');
+ local_ii_be <= (others => '0');
+ else
+ if local_ii_clk'event and local_ii_clk = '1' then
+ local_ii_be <= (others => '1');
+ if local_ii_ready = '1' then
+ local_ii_read <= not local_ii_read;
+ local_ii_write <= local_ii_read_data_valid;
+ local_ii_address <= local_ii_address + 1;
+ if local_ii_read_data_valid = '1' then
+ local_ii_writedata <= not local_ii_readdata;
+ else
+ local_ii_writedata <= (others => '1');
end if;
- end if;
+ end if;
end if;
- end process;
-
- u_ddr4_ii : ddr4
- port map (
- global_reset_n => reset_n,
- pll_ref_clk => MB_II_REF_CLK,
- oct_rzqin => MB_II_RZQ,
- mem_ck => mb_ii_ck,
- mem_ck_n => mb_ii_ck_n,
- mem_a => mb_ii_a_internal,
- mem_act_n => mb_ii_act_n,
- mem_ba => mb_ii_ba,
- mem_bg => mb_ii_bg,
- mem_cke => mb_ii_cke,
- mem_cs_n => mb_ii_cs,
- mem_odt => mb_ii_odt,
- mem_reset_n => mb_ii_reset_n,
- mem_alert_n => mb_ii_alert_n,
- mem_par => mb_ii_parity,
- mem_dqs => mb_ii_dqs,
- mem_dqs_n => mb_ii_dqs_n,
- mem_dq(63 downto 0) => mb_ii_dq,
- mem_dq(71 downto 64) => mb_ii_cb,
- mem_dbi_n => mb_ii_dm,
- local_cal_success => local_ii_cal_success,
- local_cal_fail => local_ii_cal_fail,
- emif_usr_reset_n => local_ii_reset_n,
- emif_usr_clk => local_ii_clk,
- amm_ready_0 => local_ii_ready,
- amm_read_0 => local_ii_read,
- amm_write_0 => local_ii_write,
- amm_address_0 => local_ii_address,
- amm_readdata_0 => local_ii_readdata,
- amm_writedata_0 => local_ii_writedata,
- amm_burstcount_0 => local_ii_burstcount,
- amm_byteenable_0 => local_ii_be,
- amm_readdatavalid_0 => local_ii_read_data_valid
- );
-
--- -- ****** Front side transceivers ******
---
- RING_0_TX <= tx_serial_data_front(47 downto 36);
- QSFP_0_TX <= tx_serial_data_front(35 downto 32);
- QSFP_1_TX <= tx_serial_data_front(31 downto 28);
- QSFP_2_TX <= tx_serial_data_front(27 downto 24);
- QSFP_3_TX <= tx_serial_data_front(23 downto 20);
- QSFP_4_TX <= tx_serial_data_front(19 downto 16);
- QSFP_5_TX <= tx_serial_data_front(15 downto 12);
- RING_1_TX <= tx_serial_data_front(11 downto 0);
-
- rx_serial_data_front <= RING_0_RX
+ end if;
+ end process;
+
+ u_ddr4_ii : ddr4
+ port map (
+ global_reset_n => reset_n,
+ pll_ref_clk => MB_II_REF_CLK,
+ oct_rzqin => MB_II_RZQ,
+ mem_ck => mb_ii_ck,
+ mem_ck_n => mb_ii_ck_n,
+ mem_a => mb_ii_a_internal,
+ mem_act_n => mb_ii_act_n,
+ mem_ba => mb_ii_ba,
+ mem_bg => mb_ii_bg,
+ mem_cke => mb_ii_cke,
+ mem_cs_n => mb_ii_cs,
+ mem_odt => mb_ii_odt,
+ mem_reset_n => mb_ii_reset_n,
+ mem_alert_n => mb_ii_alert_n,
+ mem_par => mb_ii_parity,
+ mem_dqs => mb_ii_dqs,
+ mem_dqs_n => mb_ii_dqs_n,
+ mem_dq(63 downto 0) => mb_ii_dq,
+ mem_dq(71 downto 64) => mb_ii_cb,
+ mem_dbi_n => mb_ii_dm,
+ local_cal_success => local_ii_cal_success,
+ local_cal_fail => local_ii_cal_fail,
+ emif_usr_reset_n => local_ii_reset_n,
+ emif_usr_clk => local_ii_clk,
+ amm_ready_0 => local_ii_ready,
+ amm_read_0 => local_ii_read,
+ amm_write_0 => local_ii_write,
+ amm_address_0 => local_ii_address,
+ amm_readdata_0 => local_ii_readdata,
+ amm_writedata_0 => local_ii_writedata,
+ amm_burstcount_0 => local_ii_burstcount,
+ amm_byteenable_0 => local_ii_be,
+ amm_readdatavalid_0 => local_ii_read_data_valid
+ );
+
+ -- -- ****** Front side transceivers ******
+ --
+ RING_0_TX <= tx_serial_data_front(47 downto 36);
+ QSFP_0_TX <= tx_serial_data_front(35 downto 32);
+ QSFP_1_TX <= tx_serial_data_front(31 downto 28);
+ QSFP_2_TX <= tx_serial_data_front(27 downto 24);
+ QSFP_3_TX <= tx_serial_data_front(23 downto 20);
+ QSFP_4_TX <= tx_serial_data_front(19 downto 16);
+ QSFP_5_TX <= tx_serial_data_front(15 downto 12);
+ RING_1_TX <= tx_serial_data_front(11 downto 0);
+
+ rx_serial_data_front <= RING_0_RX
& QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
- & RING_1_RX;
-
- transceiver_phy_front : transceiver_phy
- port map (
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- tx_cal_busy => tx_cal_busy_front,
- rx_cal_busy => rx_cal_busy_front,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- tx_serial_clk0 => tx_serial_clk_front,
- rx_cdr_refclk0 => sa_clk,
- tx_serial_data => tx_serial_data_front,
- rx_serial_data => rx_serial_data_front,
- tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_front,
- tx_clkout => tx_serdesclk_front,
- rx_clkout => open,
- tx_enh_data_valid => validloopback_front,
- rx_enh_data_valid => validloopback_front,
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_front,
- tx_control => controlloopback_front,
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_front,
- rx_control => controlloopback_front,
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_front : transceiver_reset_controller
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_front,
- tx_analogreset => tx_analogreset_front,
- tx_digitalreset => tx_digitalreset_front,
- tx_ready => open,
- pll_locked => pll_locked_front,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_front,
- rx_analogreset => rx_analogreset_front,
- rx_digitalreset => rx_digitalreset_front,
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_front,
- rx_cal_busy => rx_cal_busy_front
- );
-
- transceiver_pll_front : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_front(0),
- pll_refclk0 => sa_clk,
- pll_locked => pll_locked_front(0),
- pll_cal_busy => pll_cal_busy_front,
- mcgb_rst => pll_powerdown_front(0),
- mcgb_serial_clk => mcgb_serial_clk_front
- );
-
- tx_serial_clk_front <= (others => mcgb_serial_clk_front);
- txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
-
- -- ****** Back side transceivers ******
- -- upper 24 transceivers use sb_clk
- -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
-
- BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
--- BCK_TX(47) <= '0';
-
- rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
--- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
--- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
-
- transceiver_phy_back_upper : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- tx_cal_busy => tx_cal_busy_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24),
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
- rx_cdr_refclk0 => sb_clk,
- tx_serial_data => tx_serial_data_back(47 downto 24),
- rx_serial_data => rx_serial_data_back(47 downto 24),
- tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(47 downto 24),
- tx_clkout => tx_serdesclk_back(47 downto 24),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_data_valid => validloopback_back(47 downto 24),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(3071 downto 1536),
- tx_control => controlloopback_back(383 downto 192),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(3071 downto 1536),
- rx_control => controlloopback_back(383 downto 192),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_upper : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_upper,
- tx_analogreset => tx_analogreset_back(47 downto 24),
- tx_digitalreset => tx_digitalreset_back(47 downto 24),
- tx_ready => open,
- pll_locked => pll_locked_back_upper,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(47 downto 24),
- rx_analogreset => rx_analogreset_back(47 downto 24),
- rx_digitalreset => rx_digitalreset_back(47 downto 24),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
- rx_cal_busy => rx_cal_busy_back(47 downto 24)
- );
-
- transceiver_pll_back_upper : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_upper(0),
- pll_refclk0 => sb_clk,
- pll_locked => pll_locked_back_upper(0),
- pll_cal_busy => pll_cal_busy_back_upper,
- mcgb_rst => pll_powerdown_back_upper(0),
- mcgb_serial_clk => mcgb_serial_clk_back_upper
- );
-
- tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
- txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
-
- -- lower 24 transceivers use sb_clk
-
- transceiver_phy_back_lower : transceiver_phy_24channel
- port map (
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- tx_cal_busy => tx_cal_busy_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0),
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
- rx_cdr_refclk0 => bck_ref_clk,
- tx_serial_data => tx_serial_data_back(23 downto 0),
- rx_serial_data => rx_serial_data_back(23 downto 0),
- tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
- rx_coreclkin => tx_serdesclk_back(23 downto 0),
- tx_clkout => tx_serdesclk_back(23 downto 0),
- rx_clkout => open,
- tx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_data_valid => validloopback_back(23 downto 0),
- rx_enh_blk_lock => open,
- tx_parallel_data => dataloopback_back(1535 downto 0),
- tx_control => controlloopback_back(191 downto 0),
- tx_err_ins => (others => '0'), -- use to insert sync errors
- unused_tx_parallel_data => (others => '0'),
- unused_tx_control => (others => '0'),
- rx_parallel_data => dataloopback_back(1535 downto 0),
- rx_control => controlloopback_back(191 downto 0),
- unused_rx_parallel_data => open,
- unused_rx_control => open
- );
-
- transceiver_reset_back_lower : transceiver_reset_controller_24
- port map (
- clock => clk,
- reset => reset_p,
- pll_powerdown => pll_powerdown_back_lower,
- tx_analogreset => tx_analogreset_back(23 downto 0),
- tx_digitalreset => tx_digitalreset_back(23 downto 0),
- tx_ready => open,
- pll_locked => pll_locked_back_lower,
- pll_select => "0",
- tx_cal_busy => txpll_cal_busy_back(23 downto 0),
- rx_analogreset => rx_analogreset_back(23 downto 0),
- rx_digitalreset => rx_digitalreset_back(23 downto 0),
- rx_ready => open,
- rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
- rx_cal_busy => rx_cal_busy_back(23 downto 0)
- );
-
- transceiver_pll_back_lower : transceiver_pll
- port map (
- pll_powerdown => pll_powerdown_back_lower(0),
- pll_refclk0 => bck_ref_clk,
- pll_locked => pll_locked_back_lower(0),
- pll_cal_busy => pll_cal_busy_back_lower,
- mcgb_rst => pll_powerdown_back_lower(0),
- mcgb_serial_clk => mcgb_serial_clk_back_lower
- );
-
- tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
- txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
-
- -- ****** node control for resets and wdi
-
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
-
- reset_p <= not reset_n;
-
- u0 : component sys_clkctrl
- port map (
- inclk => CLK, -- altclkctrl_input.inclk
- outclk => CLK_buffered -- altclkctrl_output.outclk
+ & RING_1_RX;
+
+ transceiver_phy_front : transceiver_phy
+ port map (
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ tx_cal_busy => tx_cal_busy_front,
+ rx_cal_busy => rx_cal_busy_front,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ tx_serial_clk0 => tx_serial_clk_front,
+ rx_cdr_refclk0 => sa_clk,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_front,
+ tx_clkout => tx_serdesclk_front,
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_front,
+ rx_enh_data_valid => validloopback_front,
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_front,
+ tx_control => controlloopback_front,
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_front,
+ rx_control => controlloopback_front,
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_front : transceiver_reset_controller
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_front,
+ tx_analogreset => tx_analogreset_front,
+ tx_digitalreset => tx_digitalreset_front,
+ tx_ready => open,
+ pll_locked => pll_locked_front,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_front,
+ rx_analogreset => rx_analogreset_front,
+ rx_digitalreset => rx_digitalreset_front,
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_front,
+ rx_cal_busy => rx_cal_busy_front
+ );
+
+ transceiver_pll_front : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_front(0),
+ pll_refclk0 => sa_clk,
+ pll_locked => pll_locked_front(0),
+ pll_cal_busy => pll_cal_busy_front,
+ mcgb_rst => pll_powerdown_front(0),
+ mcgb_serial_clk => mcgb_serial_clk_front
+ );
+
+ tx_serial_clk_front <= (others => mcgb_serial_clk_front);
+ txpll_cal_busy_front <= tx_cal_busy_front when pll_cal_busy_front = '0' else (others => '1');
+
+ -- ****** Back side transceivers ******
+ -- upper 24 transceivers use sb_clk
+ -- Nov 4 - temporarily disconnect BCK_TX/RX(47) to see what gets synthesised away
+
+ BCK_TX(47 downto 0) <= tx_serial_data_back(47 downto 0);
+ -- BCK_TX(47) <= '0';
+
+ rx_serial_data_back(47 downto 0) <= BCK_RX(47 downto 0);
+ -- dataloopback_test <= X"0000000000000000" & dataloopback_back(3007 downto 1536);
+ -- controlloopback_test <= X"00" & controlloopback_back(375 downto 192);
+
+ transceiver_phy_back_upper : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ tx_cal_busy => tx_cal_busy_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ tx_serial_clk0 => tx_serial_clk_back(47 downto 24),
+ rx_cdr_refclk0 => sb_clk,
+ tx_serial_data => tx_serial_data_back(47 downto 24),
+ rx_serial_data => rx_serial_data_back(47 downto 24),
+ tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(47 downto 24),
+ tx_clkout => tx_serdesclk_back(47 downto 24),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_data_valid => validloopback_back(47 downto 24),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(3071 downto 1536),
+ tx_control => controlloopback_back(383 downto 192),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(3071 downto 1536),
+ rx_control => controlloopback_back(383 downto 192),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_upper : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_upper,
+ tx_analogreset => tx_analogreset_back(47 downto 24),
+ tx_digitalreset => tx_digitalreset_back(47 downto 24),
+ tx_ready => open,
+ pll_locked => pll_locked_back_upper,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(47 downto 24),
+ rx_analogreset => rx_analogreset_back(47 downto 24),
+ rx_digitalreset => rx_digitalreset_back(47 downto 24),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(47 downto 24),
+ rx_cal_busy => rx_cal_busy_back(47 downto 24)
+ );
+
+ transceiver_pll_back_upper : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_upper(0),
+ pll_refclk0 => sb_clk,
+ pll_locked => pll_locked_back_upper(0),
+ pll_cal_busy => pll_cal_busy_back_upper,
+ mcgb_rst => pll_powerdown_back_upper(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_upper
+ );
+
+ tx_serial_clk_back(47 downto 24) <= (others => mcgb_serial_clk_back_upper);
+ txpll_cal_busy_back(47 downto 24) <= tx_cal_busy_back(47 downto 24) when pll_cal_busy_back_upper = '0' else (others => '1');
+
+ -- lower 24 transceivers use sb_clk
+
+ transceiver_phy_back_lower : transceiver_phy_24channel
+ port map (
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ tx_cal_busy => tx_cal_busy_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0),
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ tx_serial_clk0 => tx_serial_clk_back(23 downto 0),
+ rx_cdr_refclk0 => bck_ref_clk,
+ tx_serial_data => tx_serial_data_back(23 downto 0),
+ rx_serial_data => rx_serial_data_back(23 downto 0),
+ tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
+ rx_coreclkin => tx_serdesclk_back(23 downto 0),
+ tx_clkout => tx_serdesclk_back(23 downto 0),
+ rx_clkout => open,
+ tx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_data_valid => validloopback_back(23 downto 0),
+ rx_enh_blk_lock => open,
+ tx_parallel_data => dataloopback_back(1535 downto 0),
+ tx_control => controlloopback_back(191 downto 0),
+ tx_err_ins => (others => '0'), -- use to insert sync errors
+ unused_tx_parallel_data => (others => '0'),
+ unused_tx_control => (others => '0'),
+ rx_parallel_data => dataloopback_back(1535 downto 0),
+ rx_control => controlloopback_back(191 downto 0),
+ unused_rx_parallel_data => open,
+ unused_rx_control => open
+ );
+
+ transceiver_reset_back_lower : transceiver_reset_controller_24
+ port map (
+ clock => clk,
+ reset => reset_p,
+ pll_powerdown => pll_powerdown_back_lower,
+ tx_analogreset => tx_analogreset_back(23 downto 0),
+ tx_digitalreset => tx_digitalreset_back(23 downto 0),
+ tx_ready => open,
+ pll_locked => pll_locked_back_lower,
+ pll_select => "0",
+ tx_cal_busy => txpll_cal_busy_back(23 downto 0),
+ rx_analogreset => rx_analogreset_back(23 downto 0),
+ rx_digitalreset => rx_digitalreset_back(23 downto 0),
+ rx_ready => open,
+ rx_is_lockedtodata => rx_is_lockedtodata_back(23 downto 0),
+ rx_cal_busy => rx_cal_busy_back(23 downto 0)
+ );
+
+ transceiver_pll_back_lower : transceiver_pll
+ port map (
+ pll_powerdown => pll_powerdown_back_lower(0),
+ pll_refclk0 => bck_ref_clk,
+ pll_locked => pll_locked_back_lower(0),
+ pll_cal_busy => pll_cal_busy_back_lower,
+ mcgb_rst => pll_powerdown_back_lower(0),
+ mcgb_serial_clk => mcgb_serial_clk_back_lower
+ );
+
+ tx_serial_clk_back(23 downto 0) <= (others => mcgb_serial_clk_back_lower);
+ txpll_cal_busy_back(23 downto 0) <= tx_cal_busy_back(23 downto 0) when pll_cal_busy_back_lower = '0' else (others => '1');
+
+ -- ****** node control for resets and wdi
+
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
);
- u_system_pll : system_pll
- port map(
--- refclk => ETH_CLK,
- refclk => CLK_buffered,
--- refclk => INTB,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
-
--- u_system_pll : system_fpll
--- port map(
--- pll_refclk0 => INTB,
--- pll_powerdown => reset_p,
--- pll_locked => sys_locked,
--- pll_cal_busy => open,
--- outclk0 => mm_clk, -- 100MHz
--- outclk1 => sys_clk, -- 300MHz
--- outclk2 => clk_125 -- 125MHz for 1ge
--- );
-
- -- ****** i2c interfaces ******
-
- u_qsys : unb2_pinning_qsys
- port map (
- clk_clk => mm_clk,
- reset_reset_n => reset_n,
- avs_i2c_master_0_gs_sim_export => cs_sim,
- avs_i2c_master_0_sync_export => cs_sync,
- avs_i2c_master_0_i2c_scl_export => sens_sc,
- avs_i2c_master_0_i2c_sda_export => sens_sd,
- avs_i2c_master_1_gs_sim_export => cs_sim,
- avs_i2c_master_1_sync_export => cs_sync,
- avs_i2c_master_1_i2c_scl_export => pmbus_sc,
- avs_i2c_master_1_i2c_sda_export => pmbus_sd,
- avs_i2c_master_2_gs_sim_export => cs_sim,
- avs_i2c_master_2_sync_export => cs_sync,
- avs_i2c_master_2_i2c_scl_export => bck_scl(0),
- avs_i2c_master_2_i2c_sda_export => bck_sda(0),
- avs_i2c_master_3_gs_sim_export => cs_sim,
- avs_i2c_master_3_sync_export => cs_sync,
- avs_i2c_master_3_i2c_scl_export => bck_scl(1),
- avs_i2c_master_3_i2c_sda_export => bck_sda(1),
- avs_i2c_master_4_sync_export => cs_sync,
- avs_i2c_master_4_gs_sim_export => cs_sim,
- avs_i2c_master_4_i2c_scl_export => bck_scl(2),
- avs_i2c_master_4_i2c_sda_export => bck_sda(2),
- avs_i2c_master_5_sync_export => cs_sync,
- avs_i2c_master_5_gs_sim_export => cs_sim,
- avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
- avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
- avs_i2c_master_6_sync_export => cs_sync,
- avs_i2c_master_6_gs_sim_export => cs_sim,
- avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
- avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
- avs_i2c_master_7_sync_export => cs_sync,
- avs_i2c_master_7_gs_sim_export => cs_sim,
- avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
- avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
- avs_i2c_master_8_sync_export => cs_sync,
- avs_i2c_master_8_gs_sim_export => cs_sim,
- avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
- avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
- avs_i2c_master_9_sync_export => cs_sync,
- avs_i2c_master_9_gs_sim_export => cs_sim,
- avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
- avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
- avs_i2c_master_10_sync_export => cs_sync,
- avs_i2c_master_10_gs_sim_export => cs_sim,
- avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
- avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
- avs_i2c_master_11_sync_export => cs_sync,
- avs_i2c_master_11_gs_sim_export => cs_sim,
- avs_i2c_master_11_i2c_sda_export => mb_sda,
- avs_i2c_master_11_i2c_scl_export => mb_scl,
- eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
- eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
- --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
- eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
- eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
- eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
- pio_0_external_connection_export => ver_id_pmbusalert
- );
-
--- bidirectional and misc
--- use PPS as output enable
-
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
- QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
-
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in(5 downto 0) <= TESTIO(5 downto 0);
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
-
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= testio_in(2 downto 0);
- testio_out(2 downto 0) <= testio_in(5 downto 3);
- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
-
- ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
+ reset_p <= not reset_n;
+
+ u0 : component sys_clkctrl
+ port map (
+ inclk => CLK, -- altclkctrl_input.inclk
+ outclk => CLK_buffered -- altclkctrl_output.outclk
+ );
+
+ u_system_pll : system_pll
+ port map(
+ -- refclk => ETH_CLK,
+ refclk => CLK_buffered,
+ -- refclk => INTB,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
+
+ -- u_system_pll : system_fpll
+ -- port map(
+ -- pll_refclk0 => INTB,
+ -- pll_powerdown => reset_p,
+ -- pll_locked => sys_locked,
+ -- pll_cal_busy => open,
+ -- outclk0 => mm_clk, -- 100MHz
+ -- outclk1 => sys_clk, -- 300MHz
+ -- outclk2 => clk_125 -- 125MHz for 1ge
+ -- );
+
+ -- ****** i2c interfaces ******
+
+ u_qsys : unb2_pinning_qsys
+ port map (
+ clk_clk => mm_clk,
+ reset_reset_n => reset_n,
+ avs_i2c_master_0_gs_sim_export => cs_sim,
+ avs_i2c_master_0_sync_export => cs_sync,
+ avs_i2c_master_0_i2c_scl_export => sens_sc,
+ avs_i2c_master_0_i2c_sda_export => sens_sd,
+ avs_i2c_master_1_gs_sim_export => cs_sim,
+ avs_i2c_master_1_sync_export => cs_sync,
+ avs_i2c_master_1_i2c_scl_export => pmbus_sc,
+ avs_i2c_master_1_i2c_sda_export => pmbus_sd,
+ avs_i2c_master_2_gs_sim_export => cs_sim,
+ avs_i2c_master_2_sync_export => cs_sync,
+ avs_i2c_master_2_i2c_scl_export => bck_scl(0),
+ avs_i2c_master_2_i2c_sda_export => bck_sda(0),
+ avs_i2c_master_3_gs_sim_export => cs_sim,
+ avs_i2c_master_3_sync_export => cs_sync,
+ avs_i2c_master_3_i2c_scl_export => bck_scl(1),
+ avs_i2c_master_3_i2c_sda_export => bck_sda(1),
+ avs_i2c_master_4_sync_export => cs_sync,
+ avs_i2c_master_4_gs_sim_export => cs_sim,
+ avs_i2c_master_4_i2c_scl_export => bck_scl(2),
+ avs_i2c_master_4_i2c_sda_export => bck_sda(2),
+ avs_i2c_master_5_sync_export => cs_sync,
+ avs_i2c_master_5_gs_sim_export => cs_sim,
+ avs_i2c_master_5_i2c_sda_export => qsfp_sda(0),
+ avs_i2c_master_5_i2c_scl_export => qsfp_scl(0),
+ avs_i2c_master_6_sync_export => cs_sync,
+ avs_i2c_master_6_gs_sim_export => cs_sim,
+ avs_i2c_master_6_i2c_sda_export => qsfp_sda(1),
+ avs_i2c_master_6_i2c_scl_export => qsfp_scl(1),
+ avs_i2c_master_7_sync_export => cs_sync,
+ avs_i2c_master_7_gs_sim_export => cs_sim,
+ avs_i2c_master_7_i2c_sda_export => qsfp_sda(2),
+ avs_i2c_master_7_i2c_scl_export => qsfp_scl(2),
+ avs_i2c_master_8_sync_export => cs_sync,
+ avs_i2c_master_8_gs_sim_export => cs_sim,
+ avs_i2c_master_8_i2c_sda_export => qsfp_sda(3),
+ avs_i2c_master_8_i2c_scl_export => qsfp_scl(3),
+ avs_i2c_master_9_sync_export => cs_sync,
+ avs_i2c_master_9_gs_sim_export => cs_sim,
+ avs_i2c_master_9_i2c_sda_export => qsfp_sda(4),
+ avs_i2c_master_9_i2c_scl_export => qsfp_scl(4),
+ avs_i2c_master_10_sync_export => cs_sync,
+ avs_i2c_master_10_gs_sim_export => cs_sim,
+ avs_i2c_master_10_i2c_sda_export => qsfp_sda(5),
+ avs_i2c_master_10_i2c_scl_export => qsfp_scl(5),
+ avs_i2c_master_11_sync_export => cs_sync,
+ avs_i2c_master_11_gs_sim_export => cs_sim,
+ avs_i2c_master_11_i2c_sda_export => mb_sda,
+ avs_i2c_master_11_i2c_scl_export => mb_scl,
+ eth_tse_0_serial_connection_rxp_0 => ETH_SGIN(0),
+ eth_tse_0_serial_connection_txp_0 => ETH_SGOUT(0),
+ --eth_tse_0_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_0_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ --eth_tse_1_pcs_ref_clk_clock_connection_clk => clk_125,
+ eth_tse_1_pcs_ref_clk_clock_connection_clk => ETH_CLK,
+ eth_tse_1_serial_connection_rxp_0 => ETH_SGIN(1),
+ eth_tse_1_serial_connection_txp_0 => ETH_SGOUT(1),
+ pio_0_external_connection_export => ver_id_pmbusalert
+ );
+
+ -- bidirectional and misc
+ -- use PPS as output enable
+
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO(5 downto 0) <= testio_out(5 downto 0) when PPS = '1' else "ZZZZZZ";
+ QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in(5 downto 0) <= TESTIO(5 downto 0);
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
+
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= testio_in(2 downto 0);
+ testio_out(2 downto 0) <= testio_in(5 downto 3);
+ qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
+
+ ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
end str;
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index 8f346a6f27cd7e3c42e7cd900c8702cbe0dceea8..f99c071326dc4ba1604cc934bfd26ee3827bb1a8 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, unb_common_lib;
-use unb_common_lib.unb_common_pkg.all;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use unb_common_lib.unb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity unb2_singlemac is
port (
@@ -47,54 +47,54 @@ entity unb2_singlemac is
BCK_REF_CLK : in std_logic; -- SerDes reference clock back
-- SO-DIMM DDR4 Memory Bank i2c (common)
--- MB_SCL : inout std_logic;
--- MB_SDA : inout std_logic;
+ -- MB_SCL : inout std_logic;
+ -- MB_SDA : inout std_logic;
-- SO-DIMM DDR4 Memory Bank I
--- MB_I_RZQ : in STD_LOGIC;
--- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_I_A : out std_logic_vector (13 downto 0);
--- MB_I_ACT_N : out std_logic_vector(0 downto 0);
--- MB_I_BA : out std_logic_vector (1 downto 0);
--- MB_I_BG : out std_logic_vector (1 downto 0);
--- MB_I_CAS_A15 : out std_logic;
--- MB_I_CB : inout std_logic_vector (7 downto 0);
--- MB_I_CK : out std_logic_vector (1 downto 0);
--- MB_I_CK_n : out std_logic_vector (1 downto 0);
--- MB_I_CKE : out std_logic_vector (1 downto 0);
--- MB_I_CS : out std_logic_vector (1 downto 0);
--- MB_I_DM : inout std_logic_vector (8 downto 0);
--- MB_I_DQ : inout std_logic_vector (63 downto 0);
--- MB_I_DQS : inout std_logic_vector (8 downto 0);
--- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_I_ODT : out std_logic_vector (1 downto 0);
--- MB_I_PARITY : out std_logic_vector(0 downto 0);
--- MB_I_RAS_A16 : out std_logic;
--- MB_I_WE_A14 : out std_logic;
--- MB_I_RESET_N : out std_logic_vector(0 downto 0);
--- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_I_RZQ : in STD_LOGIC;
+ -- MB_I_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_I_A : out std_logic_vector (13 downto 0);
+ -- MB_I_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_I_BA : out std_logic_vector (1 downto 0);
+ -- MB_I_BG : out std_logic_vector (1 downto 0);
+ -- MB_I_CAS_A15 : out std_logic;
+ -- MB_I_CB : inout std_logic_vector (7 downto 0);
+ -- MB_I_CK : out std_logic_vector (1 downto 0);
+ -- MB_I_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_I_CKE : out std_logic_vector (1 downto 0);
+ -- MB_I_CS : out std_logic_vector (1 downto 0);
+ -- MB_I_DM : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_I_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_I_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_I_ODT : out std_logic_vector (1 downto 0);
+ -- MB_I_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_I_RAS_A16 : out std_logic;
+ -- MB_I_WE_A14 : out std_logic;
+ -- MB_I_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_I_ALERT_N : in std_logic_vector(0 downto 0);
-- SO-DIMM DDR4 Memory Bank II
--- MB_II_RZQ : in STD_LOGIC;
--- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
--- MB_II_A : out std_logic_vector (13 downto 0);
--- MB_II_ACT_N : out std_logic_vector(0 downto 0);
--- MB_II_BA : out std_logic_vector (1 downto 0);
--- MB_II_BG : out std_logic_vector (1 downto 0);
--- MB_II_CAS_A15 : out std_logic;
--- MB_II_CB : inout std_logic_vector (7 downto 0);
--- MB_II_CK : out std_logic_vector (1 downto 0);
--- MB_II_CK_n : out std_logic_vector (1 downto 0);
--- MB_II_CKE : out std_logic_vector (1 downto 0);
--- MB_II_CS : out std_logic_vector (1 downto 0);
--- MB_II_DM : inout std_logic_vector (8 downto 0);
--- MB_II_DQ : inout std_logic_vector (63 downto 0);
--- MB_II_DQS : inout std_logic_vector (8 downto 0);
--- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
--- MB_II_ODT : out std_logic_vector (1 downto 0);
--- MB_II_PARITY : out std_logic_vector(0 downto 0);
--- MB_II_RAS_A16 : out std_logic;
--- MB_II_WE_A14 : out std_logic;
--- MB_II_RESET_N : out std_logic_vector(0 downto 0);
--- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
+ -- MB_II_RZQ : in STD_LOGIC;
+ -- MB_II_REF_CLK : in STD_LOGIC; -- External reference clock
+ -- MB_II_A : out std_logic_vector (13 downto 0);
+ -- MB_II_ACT_N : out std_logic_vector(0 downto 0);
+ -- MB_II_BA : out std_logic_vector (1 downto 0);
+ -- MB_II_BG : out std_logic_vector (1 downto 0);
+ -- MB_II_CAS_A15 : out std_logic;
+ -- MB_II_CB : inout std_logic_vector (7 downto 0);
+ -- MB_II_CK : out std_logic_vector (1 downto 0);
+ -- MB_II_CK_n : out std_logic_vector (1 downto 0);
+ -- MB_II_CKE : out std_logic_vector (1 downto 0);
+ -- MB_II_CS : out std_logic_vector (1 downto 0);
+ -- MB_II_DM : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQ : inout std_logic_vector (63 downto 0);
+ -- MB_II_DQS : inout std_logic_vector (8 downto 0);
+ -- MB_II_DQS_n : inout std_logic_vector (8 downto 0);
+ -- MB_II_ODT : out std_logic_vector (1 downto 0);
+ -- MB_II_PARITY : out std_logic_vector(0 downto 0);
+ -- MB_II_RAS_A16 : out std_logic;
+ -- MB_II_WE_A14 : out std_logic;
+ -- MB_II_RESET_N : out std_logic_vector(0 downto 0);
+ -- MB_II_ALERT_N : in std_logic_vector(0 downto 0);
-- back transceivers
BCK_SDA : inout std_logic_vector(2 downto 0);
@@ -113,8 +113,8 @@ entity unb2_singlemac is
-- I2C Interface to Sensors
SENS_SC : inout std_logic;
SENS_SD : inout std_logic;
- -- Others
--- CFG_DATA : inout std_logic_vector (3 downto 0);
+ -- Others
+ -- CFG_DATA : inout std_logic_vector (3 downto 0);
VERSION : in std_logic_vector(1 downto 0);
ID : in std_logic_vector(7 downto 0);
TESTIO : inout std_logic_vector(5 downto 0);
@@ -123,15 +123,15 @@ entity unb2_singlemac is
end unb2_singlemac;
architecture str of unb2_singlemac is
- component system_iopll is
- port (
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X';
- locked : out std_logic;
- outclk_0 : out std_logic; -- outclk0
- outclk_1 : out std_logic; -- outclk1
- outclk_2 : out std_logic -- outclk2
- );
+ component system_iopll is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X';
+ locked : out std_logic;
+ outclk_0 : out std_logic; -- outclk0
+ outclk_1 : out std_logic; -- outclk1
+ outclk_2 : out std_logic -- outclk2
+ );
end component system_iopll;
component tech_transceiver_arria10_1 is
@@ -196,85 +196,85 @@ architecture str of unb2_singlemac is
);
end component ip_arria10_mac_10g;
- -- constants
- constant cs_sim : std_logic := '0';
- constant cs_sync : std_logic := '1';
- --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
- constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
+ -- constants
+ constant cs_sim : std_logic := '0';
+ constant cs_sync : std_logic := '1';
+ --CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+ constant c_block_len : natural := 1118; -- = 8944 user bytes. Including packetizing: 9012 bytes.
- -- general reset and clock signals
- signal reset_n : std_logic := '0';
- signal reset_p : std_logic := '0';
- signal pout_wdi : std_logic := '0';
- signal sys_clk : std_logic := '0';
- signal sys_locked : std_logic := '0';
- signal mm_clk : std_logic := '0';
- signal clk_125 : std_logic := '0';
+ -- general reset and clock signals
+ signal reset_n : std_logic := '0';
+ signal reset_p : std_logic := '0';
+ signal pout_wdi : std_logic := '0';
+ signal sys_clk : std_logic := '0';
+ signal sys_locked : std_logic := '0';
+ signal mm_clk : std_logic := '0';
+ signal clk_125 : std_logic := '0';
- -- signals for the transceivers
- signal tx_serial_data_front : std_logic_vector(0 downto 0);
- signal rx_serial_data_front : std_logic_vector(0 downto 0);
- signal xgmii_tx : std_logic_vector(71 downto 0);
- signal xgmii_rx : std_logic_vector(71 downto 0);
- signal clk_156 : std_logic_vector(0 downto 0);
- signal clk_312 : std_logic_vector(0 downto 0);
+ -- signals for the transceivers
+ signal tx_serial_data_front : std_logic_vector(0 downto 0);
+ signal rx_serial_data_front : std_logic_vector(0 downto 0);
+ signal xgmii_tx : std_logic_vector(71 downto 0);
+ signal xgmii_rx : std_logic_vector(71 downto 0);
+ signal clk_156 : std_logic_vector(0 downto 0);
+ signal clk_312 : std_logic_vector(0 downto 0);
- -- signals for the MAC
- signal mac_10g_loopback_sop : std_logic;
- signal mac_10g_loopback_eop : std_logic;
- signal mac_10g_loopback_valid : std_logic;
- signal mac_10g_loopback_ready : std_logic;
- signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
- signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
- signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
+ -- signals for the MAC
+ signal mac_10g_loopback_sop : std_logic;
+ signal mac_10g_loopback_eop : std_logic;
+ signal mac_10g_loopback_valid : std_logic;
+ signal mac_10g_loopback_ready : std_logic;
+ signal mac_10g_loopback_data : std_logic_vector(63 downto 0);
+ signal mac_10g_loopback_empty : std_logic_vector(2 downto 0);
+ signal mac_10g_loopback_err : std_logic_vector(5 downto 0);
- signal reg_mac_rd : std_logic;
- signal reg_mac_wr : std_logic;
- signal reg_mac_waitrequest : std_logic;
- signal reg_mac_rddata : std_logic_vector(31 downto 0);
- signal reg_mac_wrdata : std_logic_vector(31 downto 0);
- signal reg_mac_address : std_logic_vector(12 downto 0);
+ signal reg_mac_rd : std_logic;
+ signal reg_mac_wr : std_logic;
+ signal reg_mac_waitrequest : std_logic;
+ signal reg_mac_rddata : std_logic_vector(31 downto 0);
+ signal reg_mac_wrdata : std_logic_vector(31 downto 0);
+ signal reg_mac_address : std_logic_vector(12 downto 0);
- -- signals for the bidirectional and misc ios
- signal inta_in : std_logic;
- signal intb_in : std_logic;
- signal testio_in : std_logic_vector(5 downto 0);
- signal qsfp_led_in : std_logic_vector(11 downto 0);
- signal bck_err_in : std_logic_vector(2 downto 0);
- signal inta_out : std_logic;
- signal intb_out : std_logic;
- signal testio_out : std_logic_vector(5 downto 0);
- signal qsfp_led_out : std_logic_vector(11 downto 0);
- signal bck_err_out : std_logic_vector(2 downto 0);
- signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
- signal toggle_count : std_logic_vector(31 downto 0);
- signal toggle_count1 : std_logic_vector(31 downto 0);
- signal led_state : std_logic;
+ -- signals for the bidirectional and misc ios
+ signal inta_in : std_logic;
+ signal intb_in : std_logic;
+ signal testio_in : std_logic_vector(5 downto 0);
+ signal qsfp_led_in : std_logic_vector(11 downto 0);
+ signal bck_err_in : std_logic_vector(2 downto 0);
+ signal inta_out : std_logic;
+ signal intb_out : std_logic;
+ signal testio_out : std_logic_vector(5 downto 0);
+ signal qsfp_led_out : std_logic_vector(11 downto 0);
+ signal bck_err_out : std_logic_vector(2 downto 0);
+ signal ver_id_pmbusalert : std_logic_vector(10 downto 0);
+ signal toggle_count : std_logic_vector(31 downto 0);
+ signal toggle_count1 : std_logic_vector(31 downto 0);
+ signal led_state : std_logic;
begin
- WDI <= 'Z';
+ WDI <= 'Z';
--- -- ****** Front side transceivers and MAC ******
---
- QSFP_0_TX <= tx_serial_data_front;
- rx_serial_data_front <= QSFP_0_RX;
+ -- -- ****** Front side transceivers and MAC ******
+ --
+ QSFP_0_TX <= tx_serial_data_front;
+ rx_serial_data_front <= QSFP_0_RX;
- u_transceiver: tech_transceiver_arria10_1
- generic map (
- g_nof_channels => 1
- )
- port map(
- clk => mm_clk,
- reset_p => reset_p,
- refclk => SA_CLK,
- clk_156_arr => clk_156,
- clk_312_arr => clk_312,
- tx_serial_data => tx_serial_data_front,
- rx_serial_data => rx_serial_data_front,
- tx_parallel_data => xgmii_tx(63 downto 0),
- rx_parallel_data => xgmii_rx(63 downto 0),
- tx_control => xgmii_tx(71 downto 64),
- rx_control => xgmii_rx(71 downto 64)
- );
+ u_transceiver: tech_transceiver_arria10_1
+ generic map (
+ g_nof_channels => 1
+ )
+ port map(
+ clk => mm_clk,
+ reset_p => reset_p,
+ refclk => SA_CLK,
+ clk_156_arr => clk_156,
+ clk_312_arr => clk_312,
+ tx_serial_data => tx_serial_data_front,
+ rx_serial_data => rx_serial_data_front,
+ tx_parallel_data => xgmii_tx(63 downto 0),
+ rx_parallel_data => xgmii_rx(63 downto 0),
+ tx_control => xgmii_tx(71 downto 64),
+ rx_control => xgmii_rx(71 downto 64)
+ );
u0 : ip_arria10_mac_10g
port map (
@@ -318,96 +318,96 @@ begin
avalon_st_rxstatus_error => open
);
- -- ****** node control for resets and wdi
+ -- ****** node control for resets and wdi
- u_node_ctrl : entity unb_common_lib.unb_node_ctrl
- generic map (
- g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- xo_clk => ETH_clk,
- xo_rst_n => reset_n,
- sys_clk => sys_clk,
- sys_locked => sys_locked,
- sys_rst => open,
- st_clk => clk,
- st_rst => open,
- wdi_in => pout_wdi,
- wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
- pulse_us => open,
- pulse_ms => open,
- pulse_s => open -- could be used to toggle a LED
- );
+ u_node_ctrl : entity unb_common_lib.unb_node_ctrl
+ generic map (
+ g_pulse_us => c_unb_tse_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ xo_clk => ETH_clk,
+ xo_rst_n => reset_n,
+ sys_clk => sys_clk,
+ sys_locked => sys_locked,
+ sys_rst => open,
+ st_clk => clk,
+ st_rst => open,
+ wdi_in => pout_wdi,
+ wdi_out => WDI, -- overrule default WDI = 'Z' and let SW toggle WDI via pout_wdi to enable the watchdog
+ pulse_us => open,
+ pulse_ms => open,
+ pulse_s => open -- could be used to toggle a LED
+ );
- reset_p <= not reset_n;
+ reset_p <= not reset_n;
- u_system_pll : system_iopll
- port map(
- refclk => ETH_CLK,
- rst => reset_p,
- locked => sys_locked,
- outclk_0 => mm_clk, -- 100MHz
- outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
- );
+ u_system_pll : system_iopll
+ port map(
+ refclk => ETH_CLK,
+ rst => reset_p,
+ locked => sys_locked,
+ outclk_0 => mm_clk, -- 100MHz
+ outclk_1 => sys_clk, -- 300MHz
+ outclk_2 => clk_125 -- 125MHz for 1ge
+ );
--- bidirectional and misc
--- use PPS as output enable
+ -- bidirectional and misc
+ -- use PPS as output enable
- INTA <= inta_out when PPS = '1' else 'Z';
- INTB <= intb_out when PPS = '1' else 'Z';
- TESTIO <= testio_out;
- QSFP_LED <= qsfp_led_out;
- BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
+ INTA <= inta_out when PPS = '1' else 'Z';
+ INTB <= intb_out when PPS = '1' else 'Z';
+ TESTIO <= testio_out;
+ QSFP_LED <= qsfp_led_out;
+ BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
- inta_in <= INTA;
- intb_in <= INTB;
- testio_in <= TESTIO;
- qsfp_led_in <= QSFP_LED;
- bck_err_in <= BCK_ERR;
+ inta_in <= INTA;
+ intb_in <= INTB;
+ testio_in <= TESTIO;
+ qsfp_led_in <= QSFP_LED;
+ bck_err_in <= BCK_ERR;
- inta_out <= intb_in;
- intb_out <= inta_in;
- testio_out(5 downto 3) <= (others => '0');
- testio_out(0) <= CLK;
- testio_out(1) <= mm_clk;
--- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
--- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
- qsfp_led_out(11 downto 6) <= (others => led_state);
- qsfp_led_out(5 downto 0) <= (others => not led_state);
- bck_err_out(2) <= bck_err_in(1);
- bck_err_out(1) <= bck_err_in(0);
- bck_err_out(0) <= bck_err_in(2);
+ inta_out <= intb_in;
+ intb_out <= inta_in;
+ testio_out(5 downto 3) <= (others => '0');
+ testio_out(0) <= CLK;
+ testio_out(1) <= mm_clk;
+ -- qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+ -- qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+ qsfp_led_out(11 downto 6) <= (others => led_state);
+ qsfp_led_out(5 downto 0) <= (others => not led_state);
+ bck_err_out(2) <= bck_err_in(1);
+ bck_err_out(1) <= bck_err_in(0);
+ bck_err_out(0) <= bck_err_in(2);
- ver_id_pmbusalert <= version & id & pmbus_alert;
+ ver_id_pmbusalert <= version & id & pmbus_alert;
- toggle_led_proc: process(mm_clk, reset_p)
- begin
- if reset_p = '1' then
- toggle_count <= (others => '0');
- led_state <= '0';
- else
- if mm_clk'event and mm_clk = '1' then
- if (toggle_count < 100000000) then
- toggle_count <= toggle_count + 1;
- else
- toggle_count <= (others => '0');
- led_state <= not led_state;
- end if;
+ toggle_led_proc: process(mm_clk, reset_p)
+ begin
+ if reset_p = '1' then
+ toggle_count <= (others => '0');
+ led_state <= '0';
+ else
+ if mm_clk'event and mm_clk = '1' then
+ if (toggle_count < 100000000) then
+ toggle_count <= toggle_count + 1;
+ else
+ toggle_count <= (others => '0');
+ led_state <= not led_state;
end if;
end if;
- end process;
+ end if;
+ end process;
- toggle_led_proc1: process(clk)
- begin
- if clk'event and clk = '1' then
- if (toggle_count1 < 100000000) then
- toggle_count1 <= toggle_count1 + 1;
- else
- toggle_count1 <= (others => '0');
- testio_out(2) <= not testio_out(2);
- pout_wdi <= not pout_wdi;
- end if;
+ toggle_led_proc1: process(clk)
+ begin
+ if clk'event and clk = '1' then
+ if (toggle_count1 < 100000000) then
+ toggle_count1 <= toggle_count1 + 1;
+ else
+ toggle_count1 <= (others => '0');
+ testio_out(2) <= not testio_out(2);
+ pout_wdi <= not pout_wdi;
end if;
- end process;
+ end if;
+ end process;
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
index aa7c4a89fa5d2a486444c2e35025e7870e698116..8df414c185aa64ffa0e0e609fd63dbac014635db 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_10GbE is
end tb_unb2_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2_test_10GbE;
architecture tb of tb_unb2_test_10GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 3fbb7d4604baf0a97b9f0e4dfa79204d605658c5..329ae0ed68afe1236fabe6a86f119a697ccf0963 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2_test_10GbE;
architecture str of unb2_test_10GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
index 3d56ebd96f5575db9fa150a6220db6377c5bf2db..2f4a8c358db123b8c1204c6656764f4a76822f9f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_1GbE is
end tb_unb2_test_1GbE;
@@ -29,7 +29,7 @@ end tb_unb2_test_1GbE;
architecture tb of tb_unb2_test_1GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index d80b47e0e24b0d05e1cb16aa34a0f3fccc1682e2..80bdf307c8703e3883f6fd5d150049d08242a130 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_test_1GbE is
generic (
@@ -71,42 +71,42 @@ end unb2_test_1GbE;
architecture str of unb2_test_1GbE is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
index d1b4f650eeaad022550d1960905a35558c32fc5d..719d918f4227db1d4b82416c8539e6e9d1f4ab21 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_all is
end tb_unb2_test_all;
@@ -29,8 +29,8 @@ end tb_unb2_test_all;
architecture tb of tb_unb2_test_all is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 2eaf164405e9fa77976a5c679e6d65f5e095b7a9..f79c418ebc620e73d1f1b37cf6d54454b71b29eb 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_all is
generic (
@@ -71,17 +71,17 @@ entity unb2_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -120,91 +120,91 @@ end unb2_test_all;
architecture str of unb2_test_all is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index 2c4a69008fa527571a7502f505ba163cef11cb5b..5b72bdddbfc3f6e58784c1a49b3175988d22ef7c 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I is
end tb_unb2_test_ddr_MB_I;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_I;
architecture tb of tb_unb2_test_ddr_MB_I is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index 2443e9f95a5c7f3d10ad2d974128c933c46a957b..d952390c8e027b7d0757e32de0bb445f8758117e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I is
generic (
@@ -80,50 +80,50 @@ end unb2_test_ddr_MB_I;
architecture str of unb2_test_ddr_MB_I is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
index 35969d021c7cbf1565629d5d2da994e3aecfbf0b..f3cefb9401119659a6f20fa08e4cf7fb952fce06 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_II is
end tb_unb2_test_ddr_MB_II;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_II;
architecture tb of tb_unb2_test_ddr_MB_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index 13039a84e05ee9e1cb8e71edbf56cf5f09a672e2..6b05fda99db19580ed71b954f675227fc2c50b2e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_II is
generic (
@@ -80,50 +80,50 @@ end unb2_test_ddr_MB_II;
architecture str of unb2_test_ddr_MB_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
index f7b56945a1495ebedbbaca7d0bb6cb04bbccaa11..024fe1a14d5a4673aff12d6cf6b8ba3139f3097a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2_test_ddr_MB_I_II is
end tb_unb2_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2_test_ddr_MB_I_II;
architecture tb of tb_unb2_test_ddr_MB_I_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
- generic map (
- g_design_name => "unb2_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 9680fc8e5d5f46fea841832f2bb4bcc4dfca3c60..73601693107c23d4995ae20015f8519206a2c68e 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2_test_ddr_MB_I_II;
architecture str of unb2_test_ddr_MB_I_II is
begin
u_revision : entity unb2_test_lib.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 0e6ff5436b8694a8ac2b36a829ca58f4d2925381..44df8a1127784625d5ecb6df7b3544d758292b27 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use unb2_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use unb2_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2_test_pkg.all;
entity mmm_unb2_test is
generic (
@@ -234,16 +234,16 @@ architecture str of mmm_unb2_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -263,7 +263,7 @@ architecture str of mmm_unb2_test is
-- Simulation
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -284,110 +284,171 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
- u_mm_file_reg_fpga_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
- port map(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -412,10 +473,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -635,32 +696,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -758,21 +819,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
@@ -823,5 +884,4 @@ begin
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 3db6393627fe5aafe9588fa02a19d351423c55a7..8e5c27fcc8965ced78f06fc158e1e59876a2ad0a 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2_test_pkg is
-----------------------------------------------------------------------------
@@ -28,354 +28,353 @@ package qsys_unb2_test_pkg is
-- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_read_export : out std_logic; -- export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- export
- ram_diag_bg_1gbe_write_export : out std_logic; -- export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- export
- reg_diag_bg_1gbe_read_export : out std_logic; -- export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- export
- reg_diag_bg_1gbe_write_export : out std_logic; -- export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_sens_clk_export : out std_logic; -- export
- reg_fpga_sens_read_export : out std_logic; -- export
- reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_sens_reset_export : out std_logic; -- export
- reg_fpga_sens_write_export : out std_logic; -- export
- reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2_test;
-
+ component qsys_unb2_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_sens_clk_export : out std_logic; -- export
+ reg_fpga_sens_read_export : out std_logic; -- export
+ reg_fpga_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_sens_reset_export : out std_logic; -- export
+ reg_fpga_sens_write_export : out std_logic; -- export
+ reg_fpga_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2_test;
end qsys_unb2_test_pkg;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index b025b45615e2eb7cf6660fc33fcf9c9cc9b64da5..1af974b973704e4f311d0b1a01ba1bb6fd0eabe2 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2_test_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2_test_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable (disabled by default)
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl,
- g_use_tx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_use_tx_seq => true
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,51 +292,51 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index a4e2c262f85c563935ad879102395a2f2b226797..7cfe29ac2f2dfb2ddaa68eeb284e49c892af8cab 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2_board_lib, unb2_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2_test_pkg.all;
entity unb2_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -351,13 +351,13 @@ architecture str of unb2_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -433,388 +433,389 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- --g_tse_clk_buf => TRUE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ --g_tse_clk_buf => TRUE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
- --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_sens_miso => reg_fpga_temp_sens_miso, -- FIXME:
+ --reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ --reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ --reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ --reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
+
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -825,80 +826,80 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
-
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -917,163 +918,163 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- --green_led_arr => qsfp_green_led_arr(2-1 DOWNTO 0),
- --red_led_arr => qsfp_red_led_arr(2-1 DOWNTO 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ --green_led_arr => qsfp_green_led_arr(2-1 DOWNTO 0),
+ --red_led_arr => qsfp_red_led_arr(2-1 DOWNTO 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1084,156 +1085,155 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index da3fbc3dc0c7e427c802c985f802c95fa7b931eb..6e9495477c2a7499bbf115e8531096e67516e0c6 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -20,37 +20,37 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 3fca57d0e88f3ca7b41acfec566ff13c9183f83c..f4c6b21171d543808194386b0e31dc40fa2cef6d 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2_test : entity work.unb2_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- QSFP_0_TX => si_lpbk_0,
- QSFP_0_RX => si_lpbk_0,
- QSFP_1_TX => si_lpbk_1,
- QSFP_1_RX => si_lpbk_1,
- QSFP_2_TX => si_lpbk_2,
- QSFP_2_RX => si_lpbk_2,
- QSFP_3_TX => si_lpbk_3,
- QSFP_3_RX => si_lpbk_3,
- QSFP_4_TX => si_lpbk_4,
- QSFP_4_RX => si_lpbk_4,
- QSFP_5_TX => si_lpbk_5,
- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ QSFP_0_TX => si_lpbk_0,
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_1_TX => si_lpbk_1,
+ QSFP_1_RX => si_lpbk_1,
+ QSFP_2_TX => si_lpbk_2,
+ QSFP_2_RX => si_lpbk_2,
+ QSFP_3_TX => si_lpbk_3,
+ QSFP_3_RX => si_lpbk_3,
+ QSFP_4_TX => si_lpbk_4,
+ QSFP_4_RX => si_lpbk_4,
+ QSFP_5_TX => si_lpbk_5,
+ QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index 8a4c6bd89ad9db59424e1cbddfbcb0bf8b468f41..2b4d43cd2a2b6d75152e97785d0c9ac4749a99a7 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -315,15 +315,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -332,15 +332,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -348,26 +348,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk
@@ -378,46 +378,47 @@ begin
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
gen_dp_clk_hardware: if g_sim = false generate
+
gen_pll: if g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
- generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
- )
- port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => dp_rst
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => dp_rst
+ );
end generate;
no_pll: if g_dp_clk_use_pll = false generate
dp_clk <= i_ext_clk200;
u_common_areset_st : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
end generate;
end generate;
@@ -431,51 +432,51 @@ begin
clk125 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M else
- clk50; -- default
+ clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -483,33 +484,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -544,12 +545,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -560,15 +561,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -577,73 +578,73 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -652,69 +653,69 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_ms; -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_clk_freq => g_mm_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_clk_freq => g_mm_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => true,
- g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => true,
+ g_clk_freq => 8 * 10**6 -- I2C bus run at ~300kHz @ mm_clk=50MHz
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -723,18 +724,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -759,43 +760,42 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index f8a10253cf5088c77b01be22f6249b4f2881e0cb..17f15224b64b1793748b56afb48736cd341f1a8c 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
generic (
@@ -64,47 +64,47 @@ architecture str of mms_unb2_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_pmbus => g_pmbus,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => c_sens_nof_result
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_pmbus => g_pmbus,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => c_sens_nof_result
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508a7900047234ce33af9b17cac31ab6b..42e0f6ec2563d269199002628a3abac432234026 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
architecture str of mms_unb2_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
- signal i_info : std_logic_vector(c_word_w - 1 downto 0);
+ signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1f752ba2a41427bec97e98a72ec56b9..a9515f45dbe56b66384cba46284391c5c01de32d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
generic (
@@ -62,51 +62,51 @@ architecture str of mms_unb2_fpga_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index 9210abec473ed84d946b293e806bb4b0984261fb..abec98f5a61e5141c4dadf6f6d8010218fede03f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
generic (
@@ -52,6 +52,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5c7c879188216a074787a6333284c9b..70c859387be2033842eb0babccdacc0e4e8da73e 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -60,46 +60,45 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
-
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e78f0da81b3f430987fdcaf05726dee..e355792acc0e7487d9975c6a988f9eef56208beb 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad5f22b82c1e67a22ed53b6e41810b3f..b7c5c65b98c09c59471a234c67d21af1f24c4e1a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -52,16 +52,16 @@ end unb2_board_clk25_pll;
architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9..053490af9736784c0adc97d70fd7e6aba8cf672b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 1e8e9a974ccf749390f10740b6ea31491bb2e456..78bdf3a1dd0908b5e0979cb6701ced5fdcd61f86 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
generic (
@@ -61,9 +61,10 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f11db1f8998aab9844b0589d93c76f4..9b1f24ec6333c6e35e4616e6ee43bb4192ea6ec1 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index aa42e0627dc1bfdf127e7b0e0fec5afdf9881fc2..be696c5096143427ab835b5c2263ebdf354d7821 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
@@ -164,7 +164,6 @@ package unb2_board_peripherals_pkg is
end record;
constant c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 3, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 5);
-
end unb2_board_peripherals_pkg;
package body unb2_board_peripherals_pkg is
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 20f69332252ac3a14fc387c19ee4aae9ffb0b673..82c3bf754eee3b43b5d6ceaf32562b1a0f097cfe 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
@@ -39,15 +39,15 @@ package unb2_board_pkg is
constant c_unb2_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
-- Clock frequencies
- constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10 ** 6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10 ** 6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2_board_tse_clk_freq : natural := 125 * 10 ** 6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2_board_cal_clk_freq : natural := 40 * 10 ** 6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10 ** 6; -- clock derived from ETH_clk by PLL
-- I2C
constant c_unb2_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
@@ -135,21 +135,22 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
-
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 45987424f355bbc7e5349362e411a7b0c149e1f6..ee2859bcc2b6347a2288579a4a2b8040bbf86a08 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
generic (
@@ -71,16 +71,16 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
--- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
+ -- SMBUS_READ_BYTE , LOC_POWER_CORE, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_CORE, LP_TEMP,
--SMBUS_READ_BYTE , LOC_POWER_ERAM, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
---
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
+ --
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
@@ -88,26 +88,26 @@ architecture rtl of unb2_board_pmbus_ctrl is
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_VOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_IOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
---
--- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
--- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_TR_T, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_TR_T, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_BAT, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_BAT, LP_TEMP,
+ --
+ -- --SMBUS_READ_BYTE , LOC_POWER_IO, LP_VOUT_MODE,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_VOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_IOUT,
+ -- SMBUS_READ_WORD , LOC_POWER_IO, LP_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a02523b0507df351a6a312d529c7a741251..f27863ead8317ba49c8ff2290fe0c0bac5b021a9 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index b83c06965924d692e1324f51a4141d7acd068f1a..cd59c987274f2cfdf76a0e69bc3a3e6e7dc4a2ae 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
generic (
@@ -47,6 +47,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 18a16b5aaba0e355cf70850c8564d86ccc50cdaa..8b353cdcd53c6d64fb86ac0d6fc05e62b590ed89 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
entity unb2_board_sens is
generic (
@@ -48,9 +48,9 @@ end entity;
architecture str of unb2_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10 ** 6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
@@ -64,68 +64,68 @@ architecture str of unb2_board_sens is
begin
gen_unb2_board_sens_ctrl : if g_pmbus = false generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_pmbus = true generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index da90d846f87364a7d68931a44fd5d93028a51c8d..346249206755cc4d296ec284513bf52ca1025257 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
generic (
@@ -69,7 +69,7 @@ architecture rtl of unb2_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
+ ); -- = (7 24 1) (7 77 1) (7 68 4) (7 68 5) (20, timeout[0:3]) (19)
constant c_seq_len : natural := c_SEQ'length - 1; -- upto SMBUS_C_END, the SMBUS_C_NOP is dummy to allow sufficient seq_cnt range
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0f4d588f779a2cbbc1b52487596c100..78752f3556eed76eb58aa4bfe8a3992d44aef178 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -92,15 +92,16 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
- signal i_temp_high : std_logic_vector(6 downto 0);
+ signal i_temp_high : std_logic_vector(6 downto 0);
begin
temp_high <= i_temp_high;
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa4075c5c30ba82ba3ebb60a095c07d8833..fef40200a3eddd77f151fd8ad27cac809fbb9788 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c5803c8e7a09da72b6fbb027358d1e5..28e4c0f9f7104a91f951e10417c0c8bafcc92f96 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
@@ -79,17 +79,18 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
- constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ constant c_use_phy_w : natural := 8;
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
- constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
- constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+ constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
begin
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff956c56a6a0ad91728c26da6f7fd03e3..9e6ef28e799a87ebaef7f05941d9a5eb355afff9 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f06f94cf92b05921391eaadd7b20ab7..1c7b8941a165d93c9871524232fbdf9274d37959 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,19 +40,20 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- -- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- For safety, WDI override requires the following word to be written:
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
@@ -68,7 +69,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
if sla_in.wrdata(c_word_w - 1 downto 0) = c_cmd_reconfigure then
wdi_override <= '1';
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e89a2425d552442030f2e3bf2964138..22f84d19e8261fcdf185975620be4d19ea1812d1 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
generic (
@@ -64,20 +64,20 @@ begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => start,
+ start_sense => start,
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3449629f924542e11912156b5b8a71b0cbca0838..37fd04e83fe10c44d80e15b3b2b772f82afad9d3 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,17 +32,17 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
- constant c_clk_freq : natural := 100 * 10**6;
- constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
+ constant c_clk_freq : natural := 100 * 10 ** 6;
+ constant c_clk_period : time := (10 ** 9 / c_clk_freq) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
-- Model I2C sensor slaves as on the UniBoard
@@ -147,58 +147,58 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec133b48c2ee0a1855949db6f37474baa8..35eb1a301661397805246ff75752e758327248e5 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1ebbb885fdc524cf39c36ecfaae6575c..6dbde563b3d6652fd030e9424f27f6667354d078 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d0d5715d52945bb2c636f11ca860615..cbb9a1d472973a6a83d0fb3fb7b670e8ea8e6a93 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58dc61776f1aa9f906a18959ecabfcde..ed4bda1034bf4548263e70eab334bd7db48d29f6 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e54767bb5b341bc1677d6083e49cee22ff..16940514912358cde96072769b934931d567bb39 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,17 +37,17 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
architecture tb of tb_unb2_board_qsfp_leds is
- constant c_clk_freq_hz : natural := 200 * 10**6;
- constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
+ constant c_clk_freq_hz : natural := 200 * 10 ** 6;
+ constant c_clk_period_ns : natural := 10 ** 9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
constant clk_period : time := c_clk_period_ns * 1 ns;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 24d2ecc45e73c420bdd45d639c7d0ce09edbc2ad..8924b23776ddec47f2721269b3fa53c8d7d4662f 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_10gbe is
generic (
@@ -74,17 +74,17 @@ architecture str of unb2_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index f2b16a715495109a68ad8c1939b70094532de969..c21c545a25c9b0560137e04b06ca9cc4014bd6e5 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIIskew;
+component ddr4_micron46_mbIIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+end component ddr4_micron46_mbIIskew;
- u0 : component ddr4_micron46_mbIIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+u0 : component ddr4_micron46_mbIIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index c028fced708026eff114f3297a08f0c515850074..fe371a18ec22a7de8abddfc7e8c8a80f84c7a424 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIskew;
+component ddr4_micron46_mbIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+end component ddr4_micron46_mbIskew;
- u0 : component ddr4_micron46_mbIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+u0 : component ddr4_micron46_mbIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index f1ce0394dc61a6390274e086ee406a1851c0acb0..345f6429518fa1e3a5988741b91dbf084e1b9a10 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_heater_pkg.all;
entity mmm_unb2a_heater is
generic (
@@ -114,36 +114,47 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -306,7 +317,6 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
index b60792517e855717caef9e115180635f2a54d2bf..ef6eb0a2f4633b5d113b98c38eb548511df5862c 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
@@ -20,143 +20,142 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
- -----------------------------------------------------------------------------
-
- component qsys_unb2a_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_heater;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2a_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_heater;
end qsys_unb2a_heater_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 5c298a90dc10e64e4061ee6f27663ba742bab6f9..15f9bfcf2cc14df9bb84aa2608595f02fdad01c7 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2a_heater is
generic (
@@ -161,240 +161,240 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736 -- 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index 16c91fe7540da69df83e96af141730e13484a3c9..cf108a644a08c7ca231bcc9e1defd4973edba3d5 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_heater is
- generic (
- g_design_name : string := "unb2a_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_heater;
architecture tb of tb_unb2a_heater is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index 4290c6d733f4a7085f678a1d48faca2ef9196844..7c04262c09b741b688531847a83dc4d4919f082e 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_led is
generic (
@@ -99,15 +99,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- mm_clk
@@ -118,40 +118,40 @@ begin
i_mm_clk <= clk50;
gen_mm_clk_sim: if g_sim = true generate
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- mm_locked <= '0', '1' after 70 ns;
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2a_board_clk125_pll : entity unb2a_board_lib.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2a_board_node_ctrl : entity unb2a_board_lib.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
------------------------------------------------------------------------------
-- Toggle red LED when unb2a_minimal is running, green LED for other designs.
@@ -160,15 +160,15 @@ begin
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
-- Red LED control
TESTIO(c_unb2_board_testio_led_red) <= led_flash_red;
@@ -177,36 +177,36 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
QSFP_LED(6) <= led_toggle;
diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
index 4e604241be67822b45600364a912743390aec8aa..9eeed8ebd9077551f95d7439183367fb1aac5b44 100644
--- a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
@@ -39,18 +39,18 @@
--
library IEEE, common_lib, unb2a_board_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2a_led is
- generic (
- g_design_name : string := "unb2a_led";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_led";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_led;
architecture tb of tb_unb2a_led is
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 2a634cb5632302f7c4fca1240baf02519ad780cc..a7e6a6ed000eb18057608d899abf2ed6cfc42a94 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2a_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2a_minimal_pkg.all;
entity mmm_unb2a_minimal is
generic (
@@ -110,33 +110,43 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -291,7 +301,6 @@ begin
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w - 1 downto 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 6897ea10bfdf03e5d40e7f2c1d7a4d618ada9160..33cadf49791d9df09745434aef81ca6b01809aec 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -20,136 +20,135 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
-
- component qsys_unb2a_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2a_minimal;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2a_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2a_minimal;
end qsys_unb2a_minimal_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index ea1f2090f826ec063406aeb77ede160913651c0f..4ceac5de57fcc18cf8b5732aa221281530531c46 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
entity unb2a_minimal is
generic (
@@ -156,217 +156,217 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 6f8ae35cfe579d513b79e2dcab5f944ebc4d484d..ca172e78c9b5a64fb4715afa456fd5216c708ce6 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2a_minimal is
- generic (
- g_design_name : string := "unb2a_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2a_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2a_minimal;
architecture tb of tb_unb2a_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
index 61f50f2ce0bc398f6c4533ed9ab3dee477749f57..ff638f6c222a9a20cfaedaa5273c277268191d21 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_10GbE is
end tb_unb2a_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2a_test_10GbE;
architecture tb of tb_unb2a_test_10GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index bbcc7c1c0f2542aabfe38115e8c1fcea9feaa6ff..49fcc6023cf5d6bd417744d6230d2de260bcb4e2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2a_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2a_test_10GbE;
architecture str of unb2a_test_10GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
index bbf7b8271ea4ddd6c7f042781bfc78f503bbd945..d5f2442823f3ff13eed2aa9c86e33e3a30698b18 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_1GbE is
end tb_unb2a_test_1GbE;
@@ -29,7 +29,7 @@ end tb_unb2a_test_1GbE;
architecture tb of tb_unb2a_test_1GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_1GbE"
- );
+ generic map (
+ g_design_name => "unb2a_test_1GbE"
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index d326502fefb6a118e511aa62ae030c5a6ff00fae..657aa4d913af634652f37bf430214353e86ad3aa 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2a_test_1GbE is
generic (
@@ -71,42 +71,42 @@ end unb2a_test_1GbE;
architecture str of unb2a_test_1GbE is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
index f0a08f448d7e3658153742a5b8473e590dd296bb..947345317fbef780b9da5ee7dac984e0ff40e4ac 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_all is
end tb_unb2a_test_all;
@@ -29,8 +29,8 @@ end tb_unb2a_test_all;
architecture tb of tb_unb2a_test_all is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_all",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_all",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 3f78a1a9417af8293d22b4d3d1ee4a644a46b2bb..c02b5bb9f6b0d8fbfc9110b8f81448df3413d652 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_all is
generic (
@@ -71,17 +71,17 @@ entity unb2a_test_all is
MB_II_REF_CLK : in std_logic; -- Reference clock for MB_II
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2_board_tr_back.bus_w * c_unb2_board_tr_back.nof_bus)-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
--- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
--- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -120,91 +120,91 @@ end unb2a_test_all;
architecture str of unb2a_test_all is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
index e09dc3465bee813c7f871f01784d257b03639bde..c7308b5171c9dfea8c7c4415740152ffa1dcb98e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I is
end tb_unb2a_test_ddr_MB_I;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_I;
architecture tb of tb_unb2a_test_ddr_MB_I is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index 7f6bcc8d641644078cdd129bbb6d2c638a0c94ed..a2563c0b6f1d2d9c3d41da79b68bf0a8fa7bc34d 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I is
generic (
@@ -80,50 +80,50 @@ end unb2a_test_ddr_MB_I;
architecture str of unb2a_test_ddr_MB_I is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
index 0c5b8a474e1248f370d3feab3d2c8b69c14c40a1..26fc2a72470fc4b4941940e8bc03c4c7275239d8 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_II is
end tb_unb2a_test_ddr_MB_II;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_II;
architecture tb of tb_unb2a_test_ddr_MB_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 45225efbb730d73c0748f64cf82136088e54adb1..62c7df0f8bc691d1b64b9022b95edeb5d93e9ae2 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_II is
generic (
@@ -80,50 +80,50 @@ end unb2a_test_ddr_MB_II;
architecture str of unb2a_test_ddr_MB_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
index 4e43f4e2f6a42a7dc5706a2cbaeedd040212ddf1..1850e8ff7ef24ddaa3e7839968272a6cf066fc4b 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2a_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2a_test_ddr_MB_I_II is
end tb_unb2a_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2a_test_ddr_MB_I_II;
architecture tb of tb_unb2a_test_ddr_MB_I_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
- generic map (
- g_design_name => "unb2a_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2a_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index a6f576bdf924b428376ed1e7f639da238f856878..6d3ddbd47b667cc34c7b0781b21f7e50e217daaf 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2a_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2a_test_ddr_MB_I_II;
architecture str of unb2a_test_ddr_MB_I_II is
begin
u_revision : entity unb2a_test_lib.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 262091355adb479dc226846baa15fb29cc297e0e..fcf867f1ae70c6985ef3bd7dd1cc072e7413d11a 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use unb2a_board_lib.unb2_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2a_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use unb2a_board_lib.unb2_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2a_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2a_test_pkg.all;
entity mmm_unb2a_test is
generic (
@@ -237,16 +237,16 @@ architecture str of mmm_unb2a_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -266,7 +266,7 @@ architecture str of mmm_unb2a_test is
-- Simulation
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -287,116 +287,179 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_10gbase_r_24 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
- port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_10gbase_r_24 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_10GBASE_R_24")
+ port map(mm_rst, mm_clk, reg_10gbase_r_24_mosi, reg_10gbase_r_24_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -421,10 +484,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -661,32 +724,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -784,21 +847,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
@@ -849,5 +912,4 @@ begin
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 1a5006c92d75968729f9fc849d656f8f42f90f68..9660b3f0531b1e3681f6880d2b9e890fd24471a2 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2a_test_pkg is
-----------------------------------------------------------------------------
@@ -28,369 +28,368 @@ package qsys_unb2a_test_pkg is
-- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2a_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
- reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
- reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
- reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
- reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
- reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
- reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
- reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2a_test;
-
+ component qsys_unb2a_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_10gbase_r_24_address_export : out std_logic_vector(14 downto 0); -- reg_10gbase_r_24_address.export
+ reg_10gbase_r_24_clk_export : out std_logic; -- reg_10gbase_r_24_clk.export
+ reg_10gbase_r_24_read_export : out std_logic; -- reg_10gbase_r_24_read.export
+ reg_10gbase_r_24_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_10gbase_r_24_readdata.export
+ reg_10gbase_r_24_reset_export : out std_logic; -- reg_10gbase_r_24_reset.export
+ reg_10gbase_r_24_waitrequest_export : in std_logic := '0'; -- reg_10gbase_r_24_waitrequest.export
+ reg_10gbase_r_24_write_export : out std_logic; -- reg_10gbase_r_24_write.export
+ reg_10gbase_r_24_writedata_export : out std_logic_vector(31 downto 0); -- reg_10gbase_r_24_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2a_test;
end qsys_unb2a_test_pkg;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 1784bbb118a15525eff62cb4869aba6a45da3f93..17e255270a8b40fef8bc42250de568029cb3e2a5 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2a_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2a_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2a_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable (disabled by default)
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 73f726f8a9557e0bf3dd2f5c30c5fe6ba386ea37..3892c9022f8ef05fad835d98a7a484887ab88282 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2a_board_lib, unb2a_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2a_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2a_test_pkg.all;
entity unb2a_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2a_test is
signal i_QSFP_TX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -354,13 +354,13 @@ architecture str of unb2a_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -437,389 +437,390 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2a_board_lib.ctrl_unb2_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
- g_aux => c_unb2_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
+ g_aux => c_unb2_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2a_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2_board_nof_eth,
- g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
+
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -830,89 +831,89 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -931,161 +932,161 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2a_board_lib.unb2_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2a_board_lib.unb2_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2a_board_lib.unb2_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1096,156 +1097,155 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index b3bb5004d9a3571a7699de756f01fa9f7c2188c3..1cedef8a6d3d0d8f23472094078afe627a926120 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -20,37 +20,37 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2a_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 819942904d1b93c6625ca6826dd11e4e79bc2b42..18b084dd0ef2b68ccff17ea6ac0a8b742fe65e39 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2a_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2a_board_lib.unb2_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2a_board_lib.unb2_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2a_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2a_test : entity work.unb2a_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 2f62140372553a4993ae19a4fad7e85e5493390d..faa637dd32dd4c1e00601879c275624f60edbae1 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2_board is
generic (
@@ -327,15 +327,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -344,15 +344,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -360,26 +360,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -393,29 +393,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2_board_clk200_pll : entity work.unb2_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -427,51 +427,51 @@ begin
clk125 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2_board_mm_clk_freq_50M else
- clk50; -- default
+ clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= not mm_sim_clk after 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2_board_clk125_pll : entity work.unb2_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2_board_node_ctrl : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -479,33 +479,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2_board_system_info : entity work.mms_unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -540,12 +540,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -556,15 +556,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2_board_wdi_reg : entity work.unb2_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -573,75 +573,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -650,74 +650,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2_board_pmbus : entity work.mms_unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2_fpga_sens : entity work.mms_unb2_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -726,18 +726,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -762,43 +762,42 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
- generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true
- )
- port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
- );
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index f3276e71962da4539f3196a98d0488c0e136745b..446b6865c4c3b439961529cad03bc7c1f1064823 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2_board_sens is
generic (
@@ -65,48 +65,48 @@ architecture str of mms_unb2_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2_board_sens : entity work.unb2_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8116249508a7900047234ce33af9b17cac31ab6b..42e0f6ec2563d269199002628a3abac432234026 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2_board_system_info;
architecture str of mms_unb2_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 10; -- 2^10 = 1024 addresses * 32 bits = 4 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
- signal i_info : std_logic_vector(c_word_w - 1 downto 0);
+ signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2_board_system_info_reg: entity work.unb2_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 9697e2b7f1f752ba2a41427bec97e98a72ec56b9..a9515f45dbe56b66384cba46284391c5c01de32d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2_fpga_sens.vhd
library IEEE, technology_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2_fpga_sens is
generic (
@@ -62,51 +62,51 @@ architecture str of mms_unb2_fpga_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_sens_nof_result => c_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- start => mm_start,
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_sens_nof_result => c_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ start => mm_start,
- -- Memory Mapped Slave in mm_clk domain
- sla_temp_in => reg_temp_mosi,
- sla_temp_out => reg_temp_miso,
- sla_voltage_in => reg_voltage_mosi,
- sla_voltage_out => reg_voltage_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_temp_in => reg_temp_mosi,
+ sla_temp_out => reg_temp_miso,
+ sla_voltage_in => reg_voltage_mosi,
+ sla_voltage_out => reg_voltage_miso,
- -- MM registers
- --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- --sens_data => sens_data,
+ -- MM registers
+ --sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ --sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
--- u_unb2_board_sens : ENTITY work.unb2_board_sens
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_clk_freq => g_clk_freq,
--- g_temp_high => g_temp_high,
--- g_sens_nof_result => c_sens_nof_result
--- )
--- PORT MAP (
--- clk => mm_clk,
--- rst => mm_rst,
--- start => mm_start,
--- -- i2c bus
--- scl => scl,
--- sda => sda,
--- -- read results
--- sens_evt => OPEN,
--- sens_err => sens_err,
--- sens_data => sens_data
--- );
+ -- u_unb2_board_sens : ENTITY work.unb2_board_sens
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_clk_freq => g_clk_freq,
+ -- g_temp_high => g_temp_high,
+ -- g_sens_nof_result => c_sens_nof_result
+ -- )
+ -- PORT MAP (
+ -- clk => mm_clk,
+ -- rst => mm_rst,
+ -- start => mm_start,
+ -- -- i2c bus
+ -- scl => scl,
+ -- sda => sda,
+ -- -- read results
+ -- sens_evt => OPEN,
+ -- sens_err => sens_err,
+ -- sens_data => sens_data
+ -- );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
index 9210abec473ed84d946b293e806bb4b0984261fb..abec98f5a61e5141c4dadf6f6d8010218fede03f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_back_io is
generic (
@@ -52,6 +52,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
index 48fad46da5c7c879188216a074787a6333284c9b..70c859387be2033842eb0babccdacc0e4e8da73e 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -60,46 +60,45 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
-
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
index 9ca4ebe75e78f0da81b3f430987fdcaf05726dee..e355792acc0e7487d9975c6a988f9eef56208beb 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
index 70d83befad5f22b82c1e67a22ed53b6e41810b3f..b7c5c65b98c09c59471a234c67d21af1f24c4e1a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -52,16 +52,16 @@ end unb2_board_clk25_pll;
architecture arria10 of unb2_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
index 4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9..053490af9736784c0adc97d70fd7e6aba8cf672b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
index 1e8e9a974ccf749390f10740b6ea31491bb2e456..78bdf3a1dd0908b5e0979cb6701ced5fdcd61f86 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_front_io is
generic (
@@ -61,9 +61,10 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 226d6091e3a666822673eee57b30d41e244cb5cc..1ff6b5d52ca6c7396d94d401c7fd337dffe3536a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_hmc_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2_board_hmc_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
index b37cfbaf8f11db1f8998aab9844b0589d93c76f4..9b1f24ec6333c6e35e4616e6ee43bb4192ea6ec1 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2_board_wdi_extend : entity work.unb2_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index a936b7c0e6942cd9da490062dece4fb4710ee815..f93e6259a9d5794842448ee9cf3fb82cd86b862e 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
@@ -164,7 +164,6 @@ package unb2_board_peripherals_pkg is
end record;
constant c_unb2_board_peripherals_mm_reg_default : t_c_unb2_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 10, 1, 1, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
-
end unb2_board_peripherals_pkg;
package body unb2_board_peripherals_pkg is
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
index 081135d117cace5d448362750f4499d99563a5d8..b71baf2497ae5ae1656ba94a24365734bfd99601 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-- UniBoard
@@ -39,16 +39,16 @@ package unb2_board_pkg is
constant c_unb2_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
-- Clock frequencies
- constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_ext_clk_freq_200M : natural := 200 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2_board_eth_clk_freq_25M : natural := 25 * 10 ** 6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2_board_eth_clk_freq_125M : natural := 125 * 10 ** 6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2_board_tse_clk_freq : natural := 125 * 10 ** 6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2_board_cal_clk_freq : natural := 40 * 10 ** 6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_10M : natural := 10 * 10 ** 6; -- clock when g_sim=TRUE
+ constant c_unb2_board_mm_clk_freq_25M : natural := 25 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_50M : natural := 50 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_100M : natural := 100 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2_board_mm_clk_freq_125M : natural := 125 * 10 ** 6; -- clock derived from ETH_clk by PLL
-- I2C
constant c_unb2_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2_board_sens_reg.vhd
@@ -140,21 +140,22 @@ package unb2_board_pkg is
type t_c_unb2_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
-
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info;
end unb2_board_pkg;
package body unb2_board_pkg is
- function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
+ function func_unb2_board_system_info(
+ VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index efe7114174765639425ad726eff2c665d6c350ed..770eac1e6dfff9bcecb9f027924e5eb272e045d4 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_pmbus_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2_board_pmbus_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
index db1d2a02523b0507df351a6a312d529c7a741251..f27863ead8317ba49c8ff2290fe0c0bac5b021a9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index b83c06965924d692e1324f51a4141d7acd068f1a..cd59c987274f2cfdf76a0e69bc3a3e6e7dc4a2ae 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_ring_io is
generic (
@@ -47,6 +47,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
index 877028aa9cafa4b330899aaf95b5b6d92c69e7f7..0179848860f8d3889e11ed06e92dc0eaa158b83a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_sens is
generic (
@@ -50,20 +50,20 @@ end entity;
architecture str of unb2_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10 ** 6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,93 +78,93 @@ architecture str of unb2_board_sens is
begin
gen_unb2_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2_board_pmbus_ctrl : entity work.unb2_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2_board_hmc_ctrl : entity work.unb2_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 9da0c246c199f3d96b40c90dda720db9f370a1f9..33716a06a3c644920b11cdccea5ac05bcee9ff46 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2_board_sens_ctrl is
generic (
@@ -105,7 +105,7 @@ architecture rtl of unb2_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
index 9790dc3ea0f4d588f779a2cbbc1b52487596c100..78752f3556eed76eb58aa4bfe8a3992d44aef178 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_sens_reg is
generic (
@@ -92,15 +92,16 @@ end unb2_board_sens_reg;
architecture rtl of unb2_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
- signal i_temp_high : std_logic_vector(6 downto 0);
+ signal i_temp_high : std_logic_vector(6 downto 0);
begin
temp_high <= i_temp_high;
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
index c3958aa4075c5c30ba82ba3ebb60a095c07d8833..fef40200a3eddd77f151fd8ad27cac809fbb9788 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 2b7a13332c5803c8e7a09da72b6fbb027358d1e5..28e4c0f9f7104a91f951e10417c0c8bafcc92f96 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
entity unb2_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2_board_system_info_reg;
architecture rtl of unb2_board_system_info_reg is
@@ -79,17 +79,18 @@ architecture rtl of unb2_board_system_info_reg is
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
- constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+ constant c_use_phy_w : natural := 8;
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
- constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
- constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+ constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
begin
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
index e09adb5ff956c56a6a0ad91728c26da6f7fd03e3..9e6ef28e799a87ebaef7f05941d9a5eb355afff9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index fa05af1d4f06f94cf92b05921391eaadd7b20ab7..1c7b8941a165d93c9871524232fbdf9274d37959 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2_board_wdi_reg is
port (
@@ -40,19 +40,20 @@ entity unb2_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2_board_wdi_reg;
architecture rtl of unb2_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- -- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- For safety, WDI override requires the following word to be written:
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
@@ -68,7 +69,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
if sla_in.wrdata(c_word_w - 1 downto 0) = c_cmd_reconfigure then
wdi_override <= '1';
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 049c7da72e89a2425d552442030f2e3bf2964138..22f84d19e8261fcdf185975620be4d19ea1812d1 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -23,11 +23,11 @@
--
library IEEE, common_lib, technology_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_fpga_sens_reg is
generic (
@@ -64,20 +64,20 @@ begin
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => start,
+ start_sense => start,
- reg_temp_mosi => sla_temp_in,
- reg_temp_miso => sla_temp_out,
+ reg_temp_mosi => sla_temp_in,
+ reg_temp_miso => sla_temp_out,
- reg_voltage_store_mosi => sla_voltage_in,
- reg_voltage_store_miso => sla_voltage_out
- );
+ reg_voltage_store_mosi => sla_voltage_in,
+ reg_voltage_store_miso => sla_voltage_out
+ );
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a91ab0e90c9610711bd7a345d391b1dd8092e692..b164b504eb4b8642ae9bdbbbbb29adf43085bb68 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -32,18 +32,18 @@ entity tb_mms_unb2_board_sens is
end tb_mms_unb2_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2_board_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
- constant c_clk_freq : natural := 100 * 10**6;
- constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
+ constant c_clk_freq : natural := 100 * 10 ** 6;
+ constant c_clk_period : time := (10 ** 9 / c_clk_freq) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
-- Model I2C sensor slaves as on the UniBoard
@@ -148,61 +148,61 @@ begin
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index bd1504ec133b48c2ee0a1855949db6f37474baa8..35eb1a301661397805246ff75752e758327248e5 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index ae4e087f1ebbb885fdc524cf39c36ecfaae6575c..6dbde563b3d6652fd030e9424f27f6667354d078 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b8ea88958d0d5715d52945bb2c636f11ca860615..cbb9a1d472973a6a83d0fb3fb7b670e8ea8e6a93 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 1d6125db58dc61776f1aa9f906a18959ecabfcde..ed4bda1034bf4548263e70eab334bd7db48d29f6 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 2a4f41e54767bb5b341bc1677d6083e49cee22ff..16940514912358cde96072769b934931d567bb39 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -37,17 +37,17 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
architecture tb of tb_unb2_board_qsfp_leds is
- constant c_clk_freq_hz : natural := 200 * 10**6;
- constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
+ constant c_clk_freq_hz : natural := 200 * 10 ** 6;
+ constant c_clk_period_ns : natural := 10 ** 9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
constant clk_period : time := c_clk_period_ns * 1 ns;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2_factory_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2_user_qsfp_leds : entity work.unb2_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 1abc9ae0a3a1e55644b88e23af49158714ea4835..f62222669d11ee68e3a1bc257dd2fe234eede6da 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2_board_10gbe is
generic (
@@ -76,17 +76,17 @@ architecture str of unb2_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 4b7405306f3ac123a1f109107a81d09bce051d17..1f7787737d6d463a358a28031c109860e4dda7b8 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -27,16 +27,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, eth_lib, eth1g_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_arp_ping is
generic (
@@ -187,130 +187,130 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_sim_level => g_sim_level,
- g_technology => g_technology,
- g_base_ip => c_base_ip,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
- g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
- g_protect_addr_range => g_protect_addr_range,
- g_app_led_red => true,
- g_app_led_green => true
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- app_led_red => app_led_red,
- app_led_green => app_led_green,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_technology => g_technology,
+ g_base_ip => c_base_ip,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_udp_offload => g_sim, -- use g_udp_offload to enable ETH instance in simulation
+ g_udp_offload_nof_streams => 3, -- use g_udp_offload, but no UDP offload streams
+ g_protect_addr_range => g_protect_addr_range,
+ g_app_led_red => true,
+ g_app_led_green => true
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ app_led_red => app_led_red,
+ app_led_green => app_led_green,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-- normaly done by unb_os
p_wdi : process(mm_clk)
@@ -338,46 +338,46 @@ begin
--u_eth1g_master : ENTITY eth1g_lib.eth1g_master(beh)
u_eth1g_master : entity eth1g_lib.eth1g_master(rtl)
- generic map (
- g_sim => g_sim
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- tse_mosi => eth1g_tse_mosi,
- tse_miso => eth1g_tse_miso,
- reg_interrupt => eth1g_reg_interrupt,
- reg_mosi => eth1g_reg_mosi,
- reg_miso => eth1g_reg_miso,
- ram_mosi => eth1g_ram_mosi,
- ram_miso => eth1g_ram_miso,
-
- src_mac => src_mac,
- src_ip => src_ip
- );
+ generic map (
+ g_sim => g_sim
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ tse_mosi => eth1g_tse_mosi,
+ tse_miso => eth1g_tse_miso,
+ reg_interrupt => eth1g_reg_interrupt,
+ reg_mosi => eth1g_reg_mosi,
+ reg_miso => eth1g_reg_miso,
+ ram_mosi => eth1g_ram_mosi,
+ ram_miso => eth1g_ram_miso,
+
+ src_mac => src_mac,
+ src_ip => src_ip
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index e5066695940d5c016c797f682f075981cb035c43..b9bbf5e533bd4a8abe43b5a634f7bdc14de5bb80 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -40,19 +40,19 @@
-- > run -all
library IEEE, common_lib, dp_lib, technology_lib, eth_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity tb_eth1g is
-- Test bench control parameters
@@ -90,7 +90,7 @@ architecture tb of tb_eth1g is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -103,171 +103,182 @@ architecture tb of tb_eth1g is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
-
- -- . IP header
- constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
- constant c_dut_ip_addr : natural := 16#01020304#;
- constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
-
- -- support only ping protocol or UDP protocol over IP
- -- symbols counter ARP ping=1 UDP=17
- constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
-
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
-
- -- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
- tha => c_dut_src_mac,
- tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
-
- -- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
-
- -- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
- constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
- constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
- constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
- constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
- constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
-
- -- ETH control
- constant c_dut_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
- constant c_dut_control_tx_en : natural := 2**c_eth_mm_reg_control_bi.tx_en;
-
- -- Clocks and reset
- signal eth_clk : std_logic := '0'; -- tse reference clock
- signal sys_clk : std_logic := '0'; -- system clock
- signal st_clk : std_logic; -- stream clock
- signal st_rst : std_logic := '1'; -- reset synchronous with st_clk
- signal mm_clk : std_logic; -- memory-mapped bus clock
- signal mm_rst : std_logic := '1'; -- reset synchronous with mm_clk
-
- -- ETH TSE interface
- signal dut_tse_init : std_logic := '1';
- signal dut_eth_init : std_logic := '1';
- signal eth_tse_miso : t_mem_miso;
- signal eth_tse_mosi : t_mem_mosi;
- signal eth_psc_access : std_logic;
- signal eth_txp : std_logic;
- signal eth_rxp : std_logic;
- signal eth_led : t_tech_tse_led;
-
- -- ETH MM registers interface
- signal eth_reg_miso : t_mem_miso;
- signal eth_reg_mosi : t_mem_mosi;
- signal eth_reg_interrupt : std_logic;
-
- signal eth_mm_reg_control : t_eth_mm_reg_control;
- signal eth_mm_reg_status : t_eth_mm_reg_status;
-
- signal eth_ram_miso : t_mem_miso;
- signal eth_ram_mosi : t_mem_mosi;
-
- -- ETH UDP data path interface
- signal udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
- signal udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
- signal udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
- signal udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-
- -- LCU TSE interface
- signal lcu_init : std_logic := '1';
- signal lcu_tse_miso : t_mem_miso;
- signal lcu_tse_mosi : t_mem_mosi;
- signal lcu_psc_access : std_logic;
- signal lcu_tx_en : std_logic := '1';
- signal lcu_tx_siso : t_dp_siso;
- signal lcu_tx_sosi : t_dp_sosi;
- signal lcu_tx_mac_in : t_tech_tse_tx_mac;
- signal lcu_tx_mac_out : t_tech_tse_tx_mac;
- signal lcu_rx_sosi : t_dp_sosi;
- signal lcu_rx_siso : t_dp_siso;
- signal lcu_rx_mac_out : t_tech_tse_rx_mac;
- signal lcu_txp : std_logic;
- signal lcu_rxp : std_logic;
- signal lcu_led : t_tech_tse_led;
-
- -- Verification
- signal tx_end : std_logic := '0';
- signal rx_end : std_logic := '0';
- signal rx_timeout : natural := 0;
- signal tx_pkt_cnt : natural := 0;
- signal rx_pkt_cnt : natural := 0;
- signal rx_pkt_discarded_cnt: natural := 0;
- signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0);
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
+ constant c_exp_eth_header : t_network_eth_header := ( -- \/
+ dst_mac => c_tx_eth_header.src_mac,
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type); -- =
+
+ -- . IP header
+ constant c_lcu_ip_addr : natural := 16#05060708#; -- = 05:06:07:08
+ constant c_dut_ip_addr : natural := 16#01020304#;
+ constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
+
+ -- support only ping protocol or UDP protocol over IP
+ -- symbols counter ARP ping=1 UDP=17
+ constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
+
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ dst_ip_addr => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
+
+ constant c_exp_ip_header : t_network_ip_header := ( -- =
+ version => c_tx_ip_header.version,
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+
+ -- . ARP packet
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => TO_UVEC(c_lcu_ip_addr, c_network_ip_addr_w),
+ tha => c_dut_src_mac,
+ tpa => TO_UVEC(c_dut_ip_addr, c_network_ip_addr_w));
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa); -- / \
+
+ -- . ICMP header
+ constant c_tx_icmp_header : t_network_icmp_header := ( -- ping request
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+ constant c_exp_icmp_header : t_network_icmp_header := ( -- ping reply
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence);
+
+ -- . UDP header
+ constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
+ constant c_dut_udp_port_st0 : natural := 57; -- ETH demux UDP port 0
+ constant c_dut_udp_port_st1 : natural := 58; -- ETH demux UDP port 1
+ constant c_dut_udp_port_st2 : natural := 59; -- ETH demux UDP port 2
+ constant c_dut_udp_port_en : natural := 16#10000#; -- ETH demux UDP port enable bit 16
+ constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
+ constant c_dut_udp_port_st : natural := c_dut_udp_port_st0; -- UDP port used for dst_port
+ constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+
+ constant c_exp_udp_header : t_network_udp_header := ( -- \/
+ src_port => c_tx_udp_header.dst_port,
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum); -- init value
+
+ signal tx_total_header : t_network_total_header; -- transmitted packet header
+ signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
+ signal exp_total_header : t_network_total_header; -- expected received packet header
+
+ -- ETH control
+ constant c_dut_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
+ constant c_dut_control_tx_en : natural := 2 ** c_eth_mm_reg_control_bi.tx_en;
+
+ -- Clocks and reset
+ signal eth_clk : std_logic := '0'; -- tse reference clock
+ signal sys_clk : std_logic := '0'; -- system clock
+ signal st_clk : std_logic; -- stream clock
+ signal st_rst : std_logic := '1'; -- reset synchronous with st_clk
+ signal mm_clk : std_logic; -- memory-mapped bus clock
+ signal mm_rst : std_logic := '1'; -- reset synchronous with mm_clk
+
+ -- ETH TSE interface
+ signal dut_tse_init : std_logic := '1';
+ signal dut_eth_init : std_logic := '1';
+ signal eth_tse_miso : t_mem_miso;
+ signal eth_tse_mosi : t_mem_mosi;
+ signal eth_psc_access : std_logic;
+ signal eth_txp : std_logic;
+ signal eth_rxp : std_logic;
+ signal eth_led : t_tech_tse_led;
+
+ -- ETH MM registers interface
+ signal eth_reg_miso : t_mem_miso;
+ signal eth_reg_mosi : t_mem_mosi;
+ signal eth_reg_interrupt : std_logic;
+
+ signal eth_mm_reg_control : t_eth_mm_reg_control;
+ signal eth_mm_reg_status : t_eth_mm_reg_status;
+
+ signal eth_ram_miso : t_mem_miso;
+ signal eth_ram_mosi : t_mem_mosi;
+
+ -- ETH UDP data path interface
+ signal udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
+ signal udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
+ signal udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
+ signal udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
+
+ -- LCU TSE interface
+ signal lcu_init : std_logic := '1';
+ signal lcu_tse_miso : t_mem_miso;
+ signal lcu_tse_mosi : t_mem_mosi;
+ signal lcu_psc_access : std_logic;
+ signal lcu_tx_en : std_logic := '1';
+ signal lcu_tx_siso : t_dp_siso;
+ signal lcu_tx_sosi : t_dp_sosi;
+ signal lcu_tx_mac_in : t_tech_tse_tx_mac;
+ signal lcu_tx_mac_out : t_tech_tse_tx_mac;
+ signal lcu_rx_sosi : t_dp_sosi;
+ signal lcu_rx_siso : t_dp_siso;
+ signal lcu_rx_mac_out : t_tech_tse_rx_mac;
+ signal lcu_txp : std_logic;
+ signal lcu_rxp : std_logic;
+ signal lcu_led : t_tech_tse_led;
+
+ -- Verification
+ signal tx_end : std_logic := '0';
+ signal rx_end : std_logic := '0';
+ signal rx_timeout : natural := 0;
+ signal tx_pkt_cnt : natural := 0;
+ signal rx_pkt_cnt : natural := 0;
+ signal rx_pkt_discarded_cnt: natural := 0;
+ signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0);
begin
-- run 50 us
@@ -321,9 +332,9 @@ begin
while dut_eth_init = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the TSE MAC
proc_tech_tse_setup(g_technology_dut,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_dut_src_mac, eth_psc_access,
- mm_clk, eth_tse_miso, eth_tse_mosi);
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_dut_src_mac, eth_psc_access,
+ mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
wait;
end process;
@@ -396,7 +407,7 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_ram_rd_latency, mm_clk);
proc_mem_mm_bus_wr(c_eth_ram_tx_offset + I, TO_SINT(eth_ram_miso.rddata(c_word_w - 1 downto 0)), mm_clk, eth_ram_miso, eth_ram_mosi);
end loop;
- --ELSE
+ --ELSE
-- . only reply header
end if;
v_eth_control_word := func_eth_mm_reg_control(eth_mm_reg_control);
@@ -422,9 +433,9 @@ begin
while mm_rst = '1' loop wait until rising_edge(mm_clk); end loop;
-- Setup the LCU TSE MAC
proc_tech_tse_setup(g_technology_lcu,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_lcu_src_mac, lcu_psc_access,
- mm_clk, lcu_tse_miso, lcu_tse_mosi);
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_lcu_src_mac, lcu_psc_access,
+ mm_clk, lcu_tse_miso, lcu_tse_mosi);
-- Wait for DUT init done
while dut_tse_init /= '0' loop wait until rising_edge(mm_clk); end loop;
lcu_init <= '0';
@@ -478,17 +489,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
@@ -523,77 +534,77 @@ begin
end generate;
dut : entity eth_lib.eth
- generic map (
- g_technology => g_technology_dut,
- g_cross_clock_domain => c_cross_clock_domain,
- g_frm_discard_en => g_frm_discard_en
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- st_rst => st_rst,
- st_clk => st_clk,
- -- UDP transmit interfaceg_frm_discard_en
- -- . ST sink
- udp_tx_snk_in_arr => udp_tx_sosi_arr,
- udp_tx_snk_out_arr => udp_tx_siso_arr,
- -- UDP receive interface
- -- . ST source
- udp_rx_src_in_arr => udp_rx_siso_arr,
- udp_rx_src_out_arr => udp_rx_sosi_arr,
- -- Control Memory Mapped Slaves
- tse_sla_in => eth_tse_mosi,
- tse_sla_out => eth_tse_miso,
- reg_sla_in => eth_reg_mosi,
- reg_sla_out => eth_reg_miso,
- reg_sla_interrupt => eth_reg_interrupt,
- ram_sla_in => eth_ram_mosi,
- ram_sla_out => eth_ram_miso,
- -- Monitoring
- rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
- -- PHY interface
- eth_txp => eth_txp,
- eth_rxp => eth_rxp,
- -- LED interface
- tse_led => eth_led
- );
+ generic map (
+ g_technology => g_technology_dut,
+ g_cross_clock_domain => c_cross_clock_domain,
+ g_frm_discard_en => g_frm_discard_en
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+ -- UDP transmit interfaceg_frm_discard_en
+ -- . ST sink
+ udp_tx_snk_in_arr => udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => udp_tx_siso_arr,
+ -- UDP receive interface
+ -- . ST source
+ udp_rx_src_in_arr => udp_rx_siso_arr,
+ udp_rx_src_out_arr => udp_rx_sosi_arr,
+ -- Control Memory Mapped Slaves
+ tse_sla_in => eth_tse_mosi,
+ tse_sla_out => eth_tse_miso,
+ reg_sla_in => eth_reg_mosi,
+ reg_sla_out => eth_reg_miso,
+ reg_sla_interrupt => eth_reg_interrupt,
+ ram_sla_in => eth_ram_mosi,
+ ram_sla_out => eth_ram_miso,
+ -- Monitoring
+ rx_flushed_frm_cnt => rx_pkt_flushed_cnt,
+ -- PHY interface
+ eth_txp => eth_txp,
+ eth_rxp => eth_rxp,
+ -- LED interface
+ tse_led => eth_led
+ );
lcu : entity tech_tse_lib.tech_tse
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => eth_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => eth_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
-- Verification
tx_pkt_cnt <= tx_pkt_cnt + 1 when lcu_tx_sosi.sop = '1' and rising_edge(st_clk);
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index ce140222f1027601e53316b1a3479af8727686f2..5be58566e8f42822a53ae208405ca7afda9f3ce9 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -28,10 +28,10 @@
-- > run -all
library IEEE, technology_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
entity tb_tb_eth1g is
generic (
@@ -46,24 +46,24 @@ architecture tb of tb_tb_eth1g is
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
--- g_technology_dut : NATURAL := c_tech_select_default;
--- g_technology_lcu : NATURAL := c_tech_select_default;
--- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
--- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
--- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
--- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
--- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
--- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
--- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
--- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
--- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
+ -- g_technology_dut : NATURAL := c_tech_select_default;
+ -- g_technology_lcu : NATURAL := c_tech_select_default;
+ -- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ -- g_flush_test_en : BOOLEAN := FALSE; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ -- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ -- g_data_type : NATURAL := c_tb_tech_tse_data_type_udp
--- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
--- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
--- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
+ -- u_use_symbols : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_symbols) PORT MAP (tb_end_vec(0));
+ -- u_use_counter : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, FALSE, FALSE, FALSE, c_tb_tech_tse_data_type_counter) PORT MAP (tb_end_vec(1));
+ -- u_use_arp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_arp ) PORT MAP (tb_end_vec(2));
u_use_ping : entity work.tb_eth1g generic map (g_technology_dut, c_technology_lcu, true, false, false, c_tb_tech_tse_data_type_ping ) port map (tb_end_vec(3));
--- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
--- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
+ -- u_use_udp : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, FALSE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(4));
+ -- u_use_udp_flush : ENTITY work.tb_eth1g GENERIC MAP (g_technology_dut, c_technology_lcu, TRUE, TRUE, FALSE, c_tb_tech_tse_data_type_udp ) PORT MAP (tb_end_vec(5));
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 7acf42ed8e04c75dc18ba3b005bbfcc6e48bbc9a..4c40ff284694761fe8124d32734105df85837079 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -43,31 +43,31 @@
--
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.tb_common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_unb2b_arp_ping is
- generic (
- g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
- g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
- -- g_data_type = c_tb_tech_tse_data_type_arp = 2
- -- g_data_type = c_tb_tech_tse_data_type_ping = 3
- -- g_data_type = c_tb_tech_tse_data_type_udp = 4
- g_data_type : natural := c_tb_tech_tse_data_type_ping;
- g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
- );
+ generic (
+ g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+ g_flush_test_en : boolean := false; -- when TRUE send many large frames to enforce flush in eth_buffer
+ -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
+ -- g_data_type = c_tb_tech_tse_data_type_counter = 1
+ -- g_data_type = c_tb_tech_tse_data_type_arp = 2
+ -- g_data_type = c_tb_tech_tse_data_type_ping = 3
+ -- g_data_type = c_tb_tech_tse_data_type_udp = 4
+ g_data_type : natural := c_tb_tech_tse_data_type_ping;
+ g_tb_end : boolean := true -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+ );
port (
tb_end : out std_logic
);
@@ -187,7 +187,7 @@ architecture tb of tb_unb2b_arp_ping is
-- Payload user data
constant c_tb_nof_data : natural := 0; -- nof UDP user data, nof ping padding data
constant c_tb_ip_nof_data : natural := c_network_udp_header_len + c_tb_nof_data; -- nof IP data,
- -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
+ -- also suits ICMP, because c_network_icmp_header_len = c_network_udp_header_len
constant c_tb_reply_payload : boolean := true; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
-- Packet headers
@@ -195,101 +195,112 @@ architecture tb of tb_unb2b_arp_ping is
-- symbols counter ARP=0x806 IP=0x800 IP=0x800
constant c_dut_ethertype : natural := sel_n(g_data_type, 16#07F0#, 16#07F1#, c_network_eth_type_arp, c_network_eth_type_ip, c_network_eth_type_ip);
- constant c_tx_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
- constant c_discard_eth_header : t_network_eth_header := (dst_mac => c_dut_src_mac,
- src_mac => c_lcu_src_mac,
- eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
- constant c_exp_eth_header : t_network_eth_header := (dst_mac => c_tx_eth_header.src_mac, -- \/
- src_mac => c_tx_eth_header.dst_mac, -- /\
- eth_type => c_tx_eth_header.eth_type); -- =
-
- -- . IP header
- constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
-
- -- support only ping protocol or UDP protocol over IP
- -- symbols counter ARP ping=1 UDP=17
- constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
-
- constant c_tx_ip_header : t_network_ip_header := (version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
- header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
- services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
- total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
- identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
- flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
- fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
- time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
- protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
- header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
- src_ip_addr => c_lcu_src_ip,
- dst_ip_addr => c_dut_src_ip);
-
- constant c_exp_ip_header : t_network_ip_header := (version => c_tx_ip_header.version, -- =
- header_length => c_tx_ip_header.header_length, -- =
- services => c_tx_ip_header.services, -- =
- total_length => c_tx_ip_header.total_length, -- =
- identification => c_tx_ip_header.identification, -- =
- flags => c_tx_ip_header.flags, -- =
- fragment_offset => c_tx_ip_header.fragment_offset, -- =
- time_to_live => c_tx_ip_header.time_to_live, -- =
- protocol => c_tx_ip_header.protocol, -- =
- header_checksum => c_tx_ip_header.header_checksum, -- init value
- src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
- dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
-
- -- . ARP packet
- constant c_tx_arp_packet : t_network_arp_packet := (htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
- ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
- hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
- plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
- oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
- sha => c_lcu_src_mac,
- spa => c_lcu_src_ip,
- tha => c_dut_src_mac,
- tpa => c_dut_src_ip);
-
- constant c_exp_arp_packet : t_network_arp_packet := (htype => c_tx_arp_packet.htype,
- ptype => c_tx_arp_packet.ptype,
- hlen => c_tx_arp_packet.hlen,
- plen => c_tx_arp_packet.plen,
- oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
- sha => c_tx_arp_packet.tha, -- \/
- spa => c_tx_arp_packet.tpa, -- /\ \/
- tha => c_tx_arp_packet.sha, -- / \ /\
- tpa => c_tx_arp_packet.spa); -- / \
-
- -- . ICMP header
- constant c_tx_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w), -- ping request
- code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
- checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
- id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
- sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
- constant c_exp_icmp_header : t_network_icmp_header := (msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w), -- ping reply
- code => c_tx_icmp_header.code,
- checksum => c_tx_icmp_header.checksum, -- init value
- id => c_tx_icmp_header.id,
- sequence => c_tx_icmp_header.sequence);
-
- -- . UDP header
- constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
- constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
-
- constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
-
- constant c_tx_udp_header : t_network_udp_header := (src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
- dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
- total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
- checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
-
- constant c_exp_udp_header : t_network_udp_header := (src_port => c_tx_udp_header.dst_port, -- \/
- dst_port => c_tx_udp_header.src_port, -- /\
- total_length => c_tx_udp_header.total_length, -- =
- checksum => c_tx_udp_header.checksum); -- init value
-
- signal tx_total_header : t_network_total_header; -- transmitted packet header
- signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
- signal exp_total_header : t_network_total_header; -- expected received packet header
+ constant c_tx_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(c_dut_ethertype, c_network_eth_type_w));
+ constant c_discard_eth_header : t_network_eth_header := (
+ dst_mac => c_dut_src_mac,
+ src_mac => c_lcu_src_mac,
+ eth_type => TO_UVEC(16#07F0#, c_network_eth_type_w));
+ constant c_exp_eth_header : t_network_eth_header := ( -- \/
+ dst_mac => c_tx_eth_header.src_mac,
+ src_mac => c_tx_eth_header.dst_mac, -- /\
+ eth_type => c_tx_eth_header.eth_type); -- =
+
+ -- . IP header
+ constant c_tb_ip_total_length : natural := c_network_ip_total_length + c_tb_ip_nof_data;
+
+ -- support only ping protocol or UDP protocol over IP
+ -- symbols counter ARP ping=1 UDP=17
+ constant c_tb_ip_protocol : natural := sel_n(g_data_type, 13, 14, 15, c_network_ip_protocol_icmp, c_network_ip_protocol_udp);
+
+ constant c_tx_ip_header : t_network_ip_header := (
+ version => TO_UVEC(c_network_ip_version, c_network_ip_version_w),
+ header_length => TO_UVEC(c_network_ip_header_length, c_network_ip_header_length_w),
+ services => TO_UVEC(c_network_ip_services, c_network_ip_services_w),
+ total_length => TO_UVEC(c_tb_ip_total_length, c_network_ip_total_length_w),
+ identification => TO_UVEC(c_network_ip_identification, c_network_ip_identification_w),
+ flags => TO_UVEC(c_network_ip_flags, c_network_ip_flags_w),
+ fragment_offset => TO_UVEC(c_network_ip_fragment_offset, c_network_ip_fragment_offset_w),
+ time_to_live => TO_UVEC(c_network_ip_time_to_live, c_network_ip_time_to_live_w),
+ protocol => TO_UVEC(c_tb_ip_protocol, c_network_ip_protocol_w),
+ header_checksum => TO_UVEC(c_network_ip_header_checksum, c_network_ip_header_checksum_w), -- init value (or try 0xEBBD = 60349)
+ src_ip_addr => c_lcu_src_ip,
+ dst_ip_addr => c_dut_src_ip);
+
+ constant c_exp_ip_header : t_network_ip_header := ( -- =
+ version => c_tx_ip_header.version,
+ header_length => c_tx_ip_header.header_length, -- =
+ services => c_tx_ip_header.services, -- =
+ total_length => c_tx_ip_header.total_length, -- =
+ identification => c_tx_ip_header.identification, -- =
+ flags => c_tx_ip_header.flags, -- =
+ fragment_offset => c_tx_ip_header.fragment_offset, -- =
+ time_to_live => c_tx_ip_header.time_to_live, -- =
+ protocol => c_tx_ip_header.protocol, -- =
+ header_checksum => c_tx_ip_header.header_checksum, -- init value
+ src_ip_addr => c_tx_ip_header.dst_ip_addr, -- \/
+ dst_ip_addr => c_tx_ip_header.src_ip_addr); -- /\
+
+ -- . ARP packet
+ constant c_tx_arp_packet : t_network_arp_packet := (
+ htype => TO_UVEC(c_network_arp_htype, c_network_arp_htype_w),
+ ptype => TO_UVEC(c_network_arp_ptype, c_network_arp_ptype_w),
+ hlen => TO_UVEC(c_network_arp_hlen, c_network_arp_hlen_w),
+ plen => TO_UVEC(c_network_arp_plen, c_network_arp_plen_w),
+ oper => TO_UVEC(c_network_arp_oper_request, c_network_arp_oper_w),
+ sha => c_lcu_src_mac,
+ spa => c_lcu_src_ip,
+ tha => c_dut_src_mac,
+ tpa => c_dut_src_ip);
+
+ constant c_exp_arp_packet : t_network_arp_packet := (
+ htype => c_tx_arp_packet.htype,
+ ptype => c_tx_arp_packet.ptype,
+ hlen => c_tx_arp_packet.hlen,
+ plen => c_tx_arp_packet.plen,
+ oper => TO_UVEC(c_network_arp_oper_reply, c_network_arp_oper_w), -- reply
+ sha => c_tx_arp_packet.tha, -- \/
+ spa => c_tx_arp_packet.tpa, -- /\ \/
+ tha => c_tx_arp_packet.sha, -- / \ /\
+ tpa => c_tx_arp_packet.spa); -- / \
+
+ -- . ICMP header
+ constant c_tx_icmp_header : t_network_icmp_header := ( -- ping request
+ msg_type => TO_UVEC(c_network_icmp_msg_type_request, c_network_icmp_msg_type_w),
+ code => TO_UVEC(c_network_icmp_code, c_network_icmp_code_w),
+ checksum => TO_UVEC(c_network_icmp_checksum, c_network_icmp_checksum_w), -- init value
+ id => TO_UVEC(c_network_icmp_id, c_network_icmp_id_w),
+ sequence => TO_UVEC(c_network_icmp_sequence, c_network_icmp_sequence_w));
+ constant c_exp_icmp_header : t_network_icmp_header := ( -- ping reply
+ msg_type => TO_UVEC(c_network_icmp_msg_type_reply, c_network_icmp_msg_type_w),
+ code => c_tx_icmp_header.code,
+ checksum => c_tx_icmp_header.checksum, -- init value
+ id => c_tx_icmp_header.id,
+ sequence => c_tx_icmp_header.sequence);
+
+ -- . UDP header
+ constant c_dut_udp_port_ctrl : natural := 11; -- ETH demux UDP for control
+ constant c_lcu_udp_port : natural := 10; -- UDP port used for src_port
+
+ constant c_tb_udp_total_length : natural := c_network_udp_total_length + c_tb_nof_data;
+
+ constant c_tx_udp_header : t_network_udp_header := (
+ src_port => TO_UVEC(c_lcu_udp_port, c_network_udp_port_w),
+ dst_port => TO_UVEC(c_dut_udp_port_ctrl, c_network_udp_port_w), -- or use c_dut_udp_port_st#
+ total_length => TO_UVEC(c_tb_udp_total_length, c_network_udp_total_length_w),
+ checksum => TO_UVEC(c_network_udp_checksum, c_network_udp_checksum_w)); -- init value
+
+ constant c_exp_udp_header : t_network_udp_header := ( -- \/
+ src_port => c_tx_udp_header.dst_port,
+ dst_port => c_tx_udp_header.src_port, -- /\
+ total_length => c_tx_udp_header.total_length, -- =
+ checksum => c_tx_udp_header.checksum); -- init value
+
+ signal tx_total_header : t_network_total_header; -- transmitted packet header
+ signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
+ signal exp_total_header : t_network_total_header; -- expected received packet header
begin
------------------------------------------------------------------------------
-- DUT
@@ -311,37 +322,37 @@ begin
PMBUS_SD <= 'H'; -- pull up
u_dut : entity work.unb2b_arp_ping
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- GENERAL
- CLK => sys_clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- sens_sc => sens_scl,
- sens_sd => sens_sda,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => eth_clk,
- ETH_SGIN => eth_rxp_arr,
- ETH_SGOUT => eth_txp_arr,
-
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- GENERAL
+ CLK => sys_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ sens_sc => sens_scl,
+ sens_sd => sens_sda,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp_arr,
+ ETH_SGOUT => eth_txp_arr,
+
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- Ethernet cable between LCU and DUT
@@ -371,51 +382,51 @@ begin
-- Setup the LCU TSE MAC
proc_tech_tse_setup(c_tech_select_default,
- c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
- c_lcu_src_mac, lcu_psc_access,
- mm_clk, lcu_tse_miso, lcu_tse_mosi);
+ c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
+ c_lcu_src_mac, lcu_psc_access,
+ mm_clk, lcu_tse_miso, lcu_tse_mosi);
lcu_init <= '0';
wait;
end process;
u_lcu : entity tech_tse_lib.tech_tse
- generic map (
- g_sim => c_sim,
- g_sim_level => c_sim_level
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- eth_clk => tse_clk,
- tx_snk_clk => st_clk,
- rx_src_clk => st_clk,
-
- -- Memory Mapped Slave
- mm_sla_in => lcu_tse_mosi,
- mm_sla_out => lcu_tse_miso,
-
- -- MAC transmit interface
- -- . ST sink
- tx_snk_in => lcu_tx_sosi,
- tx_snk_out => lcu_tx_siso,
- -- . MAC specific
- tx_mac_in => lcu_tx_mac_in,
- tx_mac_out => lcu_tx_mac_out,
-
- -- MAC receive interface
- -- . ST Source
- rx_src_in => lcu_rx_siso,
- rx_src_out => lcu_rx_sosi,
- -- . MAC specific
- rx_mac_out => lcu_rx_mac_out,
-
- -- PHY interface
- eth_txp => lcu_txp,
- eth_rxp => lcu_rxp,
-
- tse_led => lcu_led
- );
+ generic map (
+ g_sim => c_sim,
+ g_sim_level => c_sim_level
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ eth_clk => tse_clk,
+ tx_snk_clk => st_clk,
+ rx_src_clk => st_clk,
+
+ -- Memory Mapped Slave
+ mm_sla_in => lcu_tse_mosi,
+ mm_sla_out => lcu_tse_miso,
+
+ -- MAC transmit interface
+ -- . ST sink
+ tx_snk_in => lcu_tx_sosi,
+ tx_snk_out => lcu_tx_siso,
+ -- . MAC specific
+ tx_mac_in => lcu_tx_mac_in,
+ tx_mac_out => lcu_tx_mac_out,
+
+ -- MAC receive interface
+ -- . ST Source
+ rx_src_in => lcu_rx_siso,
+ rx_src_out => lcu_rx_sosi,
+ -- . MAC specific
+ rx_mac_out => lcu_rx_mac_out,
+
+ -- PHY interface
+ eth_txp => lcu_txp,
+ eth_rxp => lcu_rxp,
+
+ tse_led => lcu_led
+ );
------------------------------------------------------------------------------
-- LCU transmit and receive packets
@@ -484,17 +495,17 @@ begin
proc_tech_tse_tx_packet(tx_total_header, 2, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
end if;
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
--- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1472, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1500, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 101, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 102, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 1000, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 103, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 104, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
+ -- proc_tech_tse_tx_packet(tx_total_header, 105, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, lcu_tx_en, lcu_tx_siso, lcu_tx_sosi);
tx_end <= '1';
wait;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index ccfa91c51360b894621e7c726d976f3ca44be5c8..eeb586427eba36527a296ae46fba6f1f6390a89f 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_heater_pkg.all;
entity mmm_unb2b_heater is
generic (
@@ -114,36 +114,47 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -222,7 +233,7 @@ begin
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
rom_system_info_address_export => rom_unb_system_info_mosi.address(9 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ --c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -239,7 +250,7 @@ begin
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
pio_pps_address_export => reg_ppsh_mosi.address(0 downto 0),
---c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ --c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w - 1 downto 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
@@ -308,7 +319,6 @@ begin
reg_heater_readdata_export => reg_heater_miso.rddata(c_word_w - 1 downto 0),
reg_heater_write_export => reg_heater_mosi.wr,
reg_heater_writedata_export => reg_heater_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
index b36fb7ceda0540405cad0b725787029d599db6c2..d99394e45ae96f96786dc92ba09d9e997b3b44c3 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
@@ -20,142 +20,141 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_heater_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v17 QSYS builder
- -----------------------------------------------------------------------------
- component qsys_unb2b_heater is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_heater;
-
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v17 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2b_heater is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_heater;
end qsys_unb2b_heater_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index be12b6758a30a849d1b19047b11e49d489991e88..09e5a4d38a2c209f90da0a7bcbfe10e6780b1a5d 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2b_heater is
generic (
@@ -56,12 +56,12 @@ entity unb2b_heater is
TESTIO : inout std_logic_vector(c_unb2b_board_aux.testio_w - 1 downto 0);
-- I2C Interface to Sensors
--- SENS_SC : INOUT STD_LOGIC;
--- SENS_SD : INOUT STD_LOGIC;
---
--- PMBUS_SC : INOUT STD_LOGIC;
--- PMBUS_SD : INOUT STD_LOGIC;
--- PMBUS_ALERT : IN STD_LOGIC := '0';
+ -- SENS_SC : INOUT STD_LOGIC;
+ -- SENS_SD : INOUT STD_LOGIC;
+ --
+ -- PMBUS_SC : INOUT STD_LOGIC;
+ -- PMBUS_SD : INOUT STD_LOGIC;
+ -- PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : in std_logic;
@@ -161,244 +161,244 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_dp_clk_use_pll => true,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_tse_clk_buf => false, -- TRUE,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
--- SENS_SC => 'Z', --SENS_SC,
--- SENS_SD => 'Z', --SENS_SD,
--- -- PM bus
--- PMBUS_SC => 'Z', --PMBUS_SC,
--- PMBUS_SD => 'Z', --PMBUS_SD,
--- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_dp_clk_use_pll => true,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_tse_clk_buf => false, -- TRUE,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ -- SENS_SC => 'Z', --SENS_SC,
+ -- SENS_SD => 'Z', --SENS_SD,
+ -- -- PM bus
+ -- PMBUS_SC => 'Z', --PMBUS_SC,
+ -- PMBUS_SD => 'Z', --PMBUS_SD,
+ -- PMBUS_ALERT => 'Z', --PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_heater
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
- g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
+ g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index aec05451addeae374aa66e1819b2f275f8230316..fd134966d5ffadb218bf24ea0dc345b33d68306e 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -43,18 +43,18 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb2b_heater is
- generic (
- g_design_name : string := "unb2b_heater";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_heater";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_heater;
architecture tb of tb_unb2b_heater is
@@ -181,36 +181,36 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..1c2fecffe63864ebecf0883cb4ac85b45871adf0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..c9239eba0d665eaf7a73aa4fd323b4f1018399fc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..9ff4466cf1e3c09a5aca87bda3ff57a943bb16d0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..556545d436abf557e2581ad8cca643a01e7028c9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..bbdcb4db8093469451ae5cfdd64646e45e101a7c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..fa71f3dded5d3faf74199be419de685c295802fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..59df25d1b28f8518ee8185cee5c580a6347eb34c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..a7de702cec273692f2ab3ebcefef042b77f6fbeb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..c5f8f7bcb06d2ab28322ab1d8cbe579854adcd27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..2d82124533b1c4ef8538276273ef4abad3fdb2e5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..a8380499642f0d779741f36aac5a45b538fda2b5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..97ced477679b27e0c35f1cc7c44970ebd74a2921 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..0bdc87768e7d9f18c8b87ebe7a276ad87fa96248 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,13 +135,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -174,11 +175,12 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ARP Packet
@@ -215,12 +217,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -246,12 +248,13 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -280,7 +283,7 @@ package common_network_layers_pkg is
constant c_network_icmp_sequence_len : natural := 2;
constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
@@ -300,8 +303,9 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
------------------------------------------------------------------------------
-- UDP Packet
@@ -326,9 +330,9 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-- default field values
constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
@@ -347,9 +351,9 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
package body common_network_layers_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..e2dadbc0250f9bba58022f6aca5b01a2c8a34e08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,51 +454,51 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
-
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
function pow2(n : natural) return natural is
begin
- return 2**n;
+ return 2 ** n;
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
- return natural(integer(ceil(2**real(n))));
+ return natural(integer(ceil(2 ** real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -514,12 +516,12 @@ package body common_pkg is
function is_pow2(n : natural) return boolean is
begin
- return n = 2**true_log2(n);
+ return n = 2 ** true_log2(n);
end;
function true_log_pow2(n : natural) return natural is
begin
- return 2**true_log2(n);
+ return 2 ** true_log2(n);
end;
function ratio(n, d : natural) return natural is
@@ -664,7 +666,7 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2 ** c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -678,7 +680,7 @@ package body common_pkg is
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
- for I in 0 to c_w / (2**(J + 1)) - 1 loop
+ for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "OR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "XOR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
@@ -773,7 +775,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1740,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1750,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2145,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2175,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2181,7 +2185,7 @@ package body common_pkg is
begin
loop_stage : for j in 0 to c_nof_stages - 1 loop
v_prev_stage_pipeline_arr := v_stage_pipeline_arr;
- loop_cell : for i in 0 to c_nof_output_per_cell**j - 1 loop
+ loop_cell : for i in 0 to c_nof_output_per_cell ** j - 1 loop
v_stage_pipeline_arr((i + 1) * c_nof_output_per_cell - 1 downto i * c_nof_output_per_cell) := v_prev_stage_pipeline_arr(i) + (k_cell_pipeline_factor_arr(j) * k_cell_pipeline_arr);
end loop;
end loop;
@@ -2276,8 +2280,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2320,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..08f30597b3d79d527846c94ee83c2007737cb677 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -391,16 +396,16 @@ package dp_stream_pkg is
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
-
end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +420,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +453,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1239,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1272,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1424,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..4add394e3f929dc8f063c90f70d48f0c0f3ec372 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,149 +71,149 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
-
- ------------------------------------------------------------------------------
- -- Definitions for eth demux udp
- ------------------------------------------------------------------------------
-
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
- constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
-
- ------------------------------------------------------------------------------
- -- MM register map
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
- constant c_eth_reg_config_nof_words : natural := 4;
- constant c_eth_reg_control_nof_words : natural := 1;
- constant c_eth_reg_frame_nof_words : natural := 1;
- constant c_eth_reg_status_nof_words : natural := 1;
-
- constant c_eth_reg_demux_wi : natural := 0;
- constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
- constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
- constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
- constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
- constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
-
- -- . write/read back registers
- type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
- type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
- end record;
-
- type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
- end record;
-
- type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- . read only registers
- type t_eth_mm_reg_frame is record
- is_dhcp : std_logic;
- is_udp_ctrl_port : std_logic;
- is_udp : std_logic;
- is_icmp : std_logic;
- ip_address_match : std_logic;
- ip_checksum_is_ok : std_logic;
- is_ip : std_logic;
- is_arp : std_logic;
- mac_address_match : std_logic;
- eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
- end record;
-
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
- end record;
-
- constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
- constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
-
- type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
-
- ------------------------------------------------------------------------------
- -- Definitions for eth_mm_registers
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
-
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth demux udp
+ ------------------------------------------------------------------------------
+
+ constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ constant c_eth_nof_channels : natural := 2 ** c_eth_channel_w;
+
+ ------------------------------------------------------------------------------
+ -- MM register map
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
+ constant c_eth_reg_config_nof_words : natural := 4;
+ constant c_eth_reg_control_nof_words : natural := 1;
+ constant c_eth_reg_frame_nof_words : natural := 1;
+ constant c_eth_reg_status_nof_words : natural := 1;
+
+ constant c_eth_reg_demux_wi : natural := 0;
+ constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
+ constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
+ constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
+ constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
+ constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
+
+ -- . write/read back registers
+ type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ type t_eth_mm_reg_demux is record
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
+ udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ end record;
+
+ type t_eth_mm_reg_config is record
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ end record;
+
+ type t_eth_mm_reg_control is record
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_request : std_logic; -- 1 bit
+ tx_en : std_logic; -- 1 bit
+ rx_en : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_control_bi is record -- bit indices
+ tx_nof_words : natural; -- [26:18]
+ tx_empty : natural; -- [17:16]
+ tx_request : natural; -- [2]
+ tx_en : natural; -- [1]
+ rx_en : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- . read only registers
+ type t_eth_mm_reg_frame is record
+ is_dhcp : std_logic;
+ is_udp_ctrl_port : std_logic;
+ is_udp : std_logic;
+ is_icmp : std_logic;
+ ip_address_match : std_logic;
+ ip_checksum_is_ok : std_logic;
+ is_ip : std_logic;
+ is_arp : std_logic;
+ mac_address_match : std_logic;
+ eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
+ end record;
+
+ type t_eth_mm_reg_frame_bi is record -- bit indices
+ is_dhcp : natural; -- [15]
+ is_udp_ctrl_port : natural; -- [14]
+ is_udp : natural; -- [13]
+ is_icmp : natural; -- [12]
+ ip_address_match : natural; -- [11]
+ ip_checksum_is_ok : natural; -- [10]
+ is_ip : natural; -- [9]
+ is_arp : natural; -- [8]
+ mac_address_match : natural; -- [7]
+ eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ end record;
+
+ constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
+ constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
+
+ type t_eth_mm_reg_status is record
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_avail : std_logic; -- 1 bit
+ tx_done : std_logic; -- 1 bit
+ rx_avail : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_status_bi is record -- bit indices
+ rx_nof_words : natural; -- [26:18]
+ rx_empty : natural; -- [17:16]
+ tx_avail : natural; -- [2]
+ tx_done : natural; -- [1]
+ rx_avail : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- Register mapping functions
+ function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth_mm_registers
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
package body eth_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..2b6431ed8fe167e96d75dc9d5b40613bbeaa2f34 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
@@ -31,7 +31,7 @@ package tech_tse_pkg is
constant c_tech_tse_data_w : natural := c_word_w; -- = 32
constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
+ constant c_tech_tse_symbol_max : natural := 2 ** c_tech_tse_symbol_w - 1; -- = 255
constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
@@ -80,7 +80,6 @@ package tech_tse_pkg is
crs : std_logic;
col : std_logic;
end record;
-
end tech_tse_pkg;
package body tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..97ced477679b27e0c35f1cc7c44970ebd74a2921 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..0bdc87768e7d9f18c8b87ebe7a276ad87fa96248 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,13 +135,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -174,11 +175,12 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ARP Packet
@@ -215,12 +217,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -246,12 +248,13 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -280,7 +283,7 @@ package common_network_layers_pkg is
constant c_network_icmp_sequence_len : natural := 2;
constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
@@ -300,8 +303,9 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
------------------------------------------------------------------------------
-- UDP Packet
@@ -326,9 +330,9 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-- default field values
constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
@@ -347,9 +351,9 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
package body common_network_layers_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..e2dadbc0250f9bba58022f6aca5b01a2c8a34e08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,51 +454,51 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
-
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
function pow2(n : natural) return natural is
begin
- return 2**n;
+ return 2 ** n;
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
- return natural(integer(ceil(2**real(n))));
+ return natural(integer(ceil(2 ** real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -514,12 +516,12 @@ package body common_pkg is
function is_pow2(n : natural) return boolean is
begin
- return n = 2**true_log2(n);
+ return n = 2 ** true_log2(n);
end;
function true_log_pow2(n : natural) return natural is
begin
- return 2**true_log2(n);
+ return 2 ** true_log2(n);
end;
function ratio(n, d : natural) return natural is
@@ -664,7 +666,7 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2 ** c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -678,7 +680,7 @@ package body common_pkg is
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
- for I in 0 to c_w / (2**(J + 1)) - 1 loop
+ for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "OR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "XOR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
@@ -773,7 +775,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1740,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1750,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2145,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2175,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2181,7 +2185,7 @@ package body common_pkg is
begin
loop_stage : for j in 0 to c_nof_stages - 1 loop
v_prev_stage_pipeline_arr := v_stage_pipeline_arr;
- loop_cell : for i in 0 to c_nof_output_per_cell**j - 1 loop
+ loop_cell : for i in 0 to c_nof_output_per_cell ** j - 1 loop
v_stage_pipeline_arr((i + 1) * c_nof_output_per_cell - 1 downto i * c_nof_output_per_cell) := v_prev_stage_pipeline_arr(i) + (k_cell_pipeline_factor_arr(j) * k_cell_pipeline_arr);
end loop;
end loop;
@@ -2276,8 +2280,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2320,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..08f30597b3d79d527846c94ee83c2007737cb677 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -391,16 +396,16 @@ package dp_stream_pkg is
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
-
end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +420,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +453,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1239,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1272,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1424,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..4add394e3f929dc8f063c90f70d48f0c0f3ec372 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,149 +71,149 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
-
- ------------------------------------------------------------------------------
- -- Definitions for eth demux udp
- ------------------------------------------------------------------------------
-
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
- constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
-
- ------------------------------------------------------------------------------
- -- MM register map
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
- constant c_eth_reg_config_nof_words : natural := 4;
- constant c_eth_reg_control_nof_words : natural := 1;
- constant c_eth_reg_frame_nof_words : natural := 1;
- constant c_eth_reg_status_nof_words : natural := 1;
-
- constant c_eth_reg_demux_wi : natural := 0;
- constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
- constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
- constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
- constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
- constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
-
- -- . write/read back registers
- type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
- type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
- end record;
-
- type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
- end record;
-
- type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- . read only registers
- type t_eth_mm_reg_frame is record
- is_dhcp : std_logic;
- is_udp_ctrl_port : std_logic;
- is_udp : std_logic;
- is_icmp : std_logic;
- ip_address_match : std_logic;
- ip_checksum_is_ok : std_logic;
- is_ip : std_logic;
- is_arp : std_logic;
- mac_address_match : std_logic;
- eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
- end record;
-
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
- end record;
-
- constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
- constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
-
- type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
-
- ------------------------------------------------------------------------------
- -- Definitions for eth_mm_registers
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
-
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth demux udp
+ ------------------------------------------------------------------------------
+
+ constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ constant c_eth_nof_channels : natural := 2 ** c_eth_channel_w;
+
+ ------------------------------------------------------------------------------
+ -- MM register map
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
+ constant c_eth_reg_config_nof_words : natural := 4;
+ constant c_eth_reg_control_nof_words : natural := 1;
+ constant c_eth_reg_frame_nof_words : natural := 1;
+ constant c_eth_reg_status_nof_words : natural := 1;
+
+ constant c_eth_reg_demux_wi : natural := 0;
+ constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
+ constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
+ constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
+ constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
+ constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
+
+ -- . write/read back registers
+ type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ type t_eth_mm_reg_demux is record
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
+ udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ end record;
+
+ type t_eth_mm_reg_config is record
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ end record;
+
+ type t_eth_mm_reg_control is record
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_request : std_logic; -- 1 bit
+ tx_en : std_logic; -- 1 bit
+ rx_en : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_control_bi is record -- bit indices
+ tx_nof_words : natural; -- [26:18]
+ tx_empty : natural; -- [17:16]
+ tx_request : natural; -- [2]
+ tx_en : natural; -- [1]
+ rx_en : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- . read only registers
+ type t_eth_mm_reg_frame is record
+ is_dhcp : std_logic;
+ is_udp_ctrl_port : std_logic;
+ is_udp : std_logic;
+ is_icmp : std_logic;
+ ip_address_match : std_logic;
+ ip_checksum_is_ok : std_logic;
+ is_ip : std_logic;
+ is_arp : std_logic;
+ mac_address_match : std_logic;
+ eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
+ end record;
+
+ type t_eth_mm_reg_frame_bi is record -- bit indices
+ is_dhcp : natural; -- [15]
+ is_udp_ctrl_port : natural; -- [14]
+ is_udp : natural; -- [13]
+ is_icmp : natural; -- [12]
+ ip_address_match : natural; -- [11]
+ ip_checksum_is_ok : natural; -- [10]
+ is_ip : natural; -- [9]
+ is_arp : natural; -- [8]
+ mac_address_match : natural; -- [7]
+ eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ end record;
+
+ constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
+ constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
+
+ type t_eth_mm_reg_status is record
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_avail : std_logic; -- 1 bit
+ tx_done : std_logic; -- 1 bit
+ rx_avail : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_status_bi is record -- bit indices
+ rx_nof_words : natural; -- [26:18]
+ rx_empty : natural; -- [17:16]
+ tx_avail : natural; -- [2]
+ tx_done : natural; -- [1]
+ rx_avail : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- Register mapping functions
+ function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth_mm_registers
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
package body eth_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..2b6431ed8fe167e96d75dc9d5b40613bbeaa2f34 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
@@ -31,7 +31,7 @@ package tech_tse_pkg is
constant c_tech_tse_data_w : natural := c_word_w; -- = 32
constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
+ constant c_tech_tse_symbol_max : natural := 2 ** c_tech_tse_symbol_w - 1; -- = 255
constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
@@ -80,7 +80,6 @@ package tech_tse_pkg is
crs : std_logic;
col : std_logic;
end record;
-
end tech_tse_pkg;
package body tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..1db149d4b3900a9632e3cca9845ca4e53adaf0ea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..f5b386839514684123794a757628cb3f3e7f6fdc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..530ffe22745aa5e71d9502cb15c001f1f2bcc594 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..e1d0e8ddbe0d7c28e35f6a332fcc00bb48a47bc5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index f745d32d0b9a636140d0cb000f2acf129a6741ad..3921081b642736800e1c9a37bb29bc27527015f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -15,55 +15,55 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
- end process;
+ end if;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
---synthesis translate_on
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -71,96 +71,96 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_FF <= internal_fifo_FF;
- --vhdl renameroo for output signals
- r_dat <= internal_r_dat;
- --vhdl renameroo for output signals
- wfifo_empty <= internal_wfifo_empty;
- --vhdl renameroo for output signals
- wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_FF <= internal_fifo_FF;
+ --vhdl renameroo for output signals
+ r_dat <= internal_r_dat;
+ --vhdl renameroo for output signals
+ wfifo_empty <= internal_wfifo_empty;
+ --vhdl renameroo for output signals
+ wfifo_used <= internal_wfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
port map(
fifo_FF => internal_fifo_FF,
r_dat => internal_r_dat,
@@ -171,103 +171,103 @@ begin
fifo_wr => fifo_wr
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- wfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => fifo_wdata,
--- empty => internal_wfifo_empty,
--- full => internal_fifo_FF,
--- q => internal_r_dat,
--- rdreq => rd_wfifo,
--- usedw => internal_wfifo_used,
--- wrreq => fifo_wr
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- wfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => fifo_wdata,
+ -- empty => internal_wfifo_empty,
+ -- full => internal_fifo_FF,
+ -- q => internal_r_dat,
+ -- rdreq => rd_wfifo,
+ -- usedw => internal_wfifo_used,
+ -- wrreq => fifo_wr
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
+ end if;
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
end if;
- end process;
-
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
---synthesis translate_on
+ end if;
+ end process;
+
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -275,97 +275,97 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_EF <= internal_fifo_EF;
- --vhdl renameroo for output signals
- fifo_rdata <= internal_fifo_rdata;
- --vhdl renameroo for output signals
- rfifo_full <= internal_rfifo_full;
- --vhdl renameroo for output signals
- rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_EF <= internal_fifo_EF;
+ --vhdl renameroo for output signals
+ fifo_rdata <= internal_fifo_rdata;
+ --vhdl renameroo for output signals
+ rfifo_full <= internal_rfifo_full;
+ --vhdl renameroo for output signals
+ rfifo_used <= internal_rfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
port map(
fifo_EF => internal_fifo_EF,
fifo_rdata => internal_fifo_rdata,
@@ -376,344 +376,347 @@ begin
rst_n => rst_n
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- rfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => t_dat,
--- empty => internal_fifo_EF,
--- full => internal_rfifo_full,
--- q => internal_fifo_rdata,
--- rdreq => fifo_rd,
--- usedw => internal_rfifo_used,
--- wrreq => wr_rfifo
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- rfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => t_dat,
+ -- empty => internal_fifo_EF,
+ -- full => internal_rfifo_full,
+ -- q => internal_fifo_rdata,
+ -- rdreq => fifo_rd,
+ -- usedw => internal_rfifo_used,
+ -- wrreq => wr_rfifo
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
-
-architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
-begin
- --avalon_jtag_slave, which is an e_avalon_slave
- rd_wfifo <= r_ena and not wfifo_empty;
- wr_rfifo <= t_ena and not rfifo_full;
- fifo_clear <= not rst_n;
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
- port map(
- fifo_FF => fifo_FF,
- r_dat => r_dat,
- wfifo_empty => wfifo_empty,
- wfifo_used => wfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr,
- rd_wfifo => rd_wfifo
- );
-
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
- port map(
- fifo_EF => fifo_EF,
- fifo_rdata => fifo_rdata,
- rfifo_full => rfifo_full,
- rfifo_used => rfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_rd => fifo_rd,
- rst_n => rst_n,
- t_dat => t_dat,
- wr_rfifo => wr_rfifo
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
- ipen_AE <= ien_AE and fifo_AE;
- ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
- av_irq <= ipen_AE or ipen_AF;
- activity <= t_pause or t_ena;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- pause_irq <= std_logic'('0');
- elsif clk'event and clk = '1' then
- -- only if fifo is not empty...
- if std_logic'((t_pause and not fifo_EF)) = '1' then
- pause_irq <= std_logic'('1');
- elsif std_logic'(read_0) = '1' then
- pause_irq <= std_logic'('0');
- end if;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- r_val <= std_logic'('0');
- t_dav <= std_logic'('1');
- elsif clk'event and clk = '1' then
- r_val <= r_ena and not wfifo_empty;
- t_dav <= not rfifo_full;
- end if;
- end process;
+architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- fifo_AE <= std_logic'('0');
- fifo_AF <= std_logic'('0');
- fifo_wr <= std_logic'('0');
- rvalid <= std_logic'('0');
- read_0 <= std_logic'('0');
- ien_AE <= std_logic'('0');
- ien_AF <= std_logic'('0');
- ac <= std_logic'('0');
- woverflow <= std_logic'('0');
- internal_av_waitrequest <= std_logic'('1');
- elsif clk'event and clk = '1' then
- fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_wr <= std_logic'('0');
- read_0 <= std_logic'('0');
- internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
- if std_logic'(activity) = '1' then
- ac <= std_logic'('1');
- end if;
- -- write
- if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is control; addr 0 is data
- if std_logic'(av_address) = '1' then
- ien_AF <= av_writedata(0);
- ien_AE <= av_writedata(1);
- if std_logic'((av_writedata(10) and not activity)) = '1' then
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
+ begin
+ --avalon_jtag_slave, which is an e_avalon_slave
+ rd_wfifo <= r_ena and not wfifo_empty;
+ wr_rfifo <= t_ena and not rfifo_full;
+ fifo_clear <= not rst_n;
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
+ port map(
+ fifo_FF => fifo_FF,
+ r_dat => r_dat,
+ wfifo_empty => wfifo_empty,
+ wfifo_used => wfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr,
+ rd_wfifo => rd_wfifo
+ );
+
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
+ port map(
+ fifo_EF => fifo_EF,
+ fifo_rdata => fifo_rdata,
+ rfifo_full => rfifo_full,
+ rfifo_used => rfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n,
+ t_dat => t_dat,
+ wr_rfifo => wr_rfifo
+ );
+
+ ipen_AE <= ien_AE and fifo_AE;
+ ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
+ av_irq <= ipen_AE or ipen_AF;
+ activity <= t_pause or t_ena;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ pause_irq <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ -- only if fifo is not empty...
+ if std_logic'((t_pause and not fifo_EF)) = '1' then
+ pause_irq <= std_logic'('1');
+ elsif std_logic'(read_0) = '1' then
+ pause_irq <= std_logic'('0');
+ end if;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ r_val <= std_logic'('0');
+ t_dav <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ r_val <= r_ena and not wfifo_empty;
+ t_dav <= not rfifo_full;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ fifo_AE <= std_logic'('0');
+ fifo_AF <= std_logic'('0');
+ fifo_wr <= std_logic'('0');
+ rvalid <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ ien_AE <= std_logic'('0');
+ ien_AF <= std_logic'('0');
ac <= std_logic'('0');
+ woverflow <= std_logic'('0');
+ internal_av_waitrequest <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_wr <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
+ if std_logic'(activity) = '1' then
+ ac <= std_logic'('1');
+ end if;
+ -- write
+ if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is control; addr 0 is data
+ if std_logic'(av_address) = '1' then
+ ien_AF <= av_writedata(0);
+ ien_AE <= av_writedata(1);
+ if std_logic'((av_writedata(10) and not activity)) = '1' then
+ ac <= std_logic'('0');
+ end if;
+ else
+ fifo_wr <= not fifo_FF;
+ woverflow <= fifo_FF;
+ end if;
+ end if;
+ -- read
+ if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is interrupt; addr 0 is data
+ if std_logic'(not av_address) = '1' then
+ rvalid <= not fifo_EF;
+ end if;
+ read_0 <= not av_address;
+ end if;
end if;
- else
- fifo_wr <= not fifo_FF;
- woverflow <= fifo_FF;
- end if;
- end if;
- -- read
- if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is interrupt; addr 0 is data
- if std_logic'(not av_address) = '1' then
- rvalid <= not fifo_EF;
- end if;
- read_0 <= not av_address;
- end if;
- end if;
- end process;
-
- fifo_wdata <= av_writedata(7 downto 0);
- fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
- av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- readyfordata <= std_logic'('0');
- elsif clk'event and clk = '1' then
- readyfordata <= not fifo_FF;
- end if;
- end process;
-
- --vhdl renameroo for output signals
- av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
- end process;
-
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
- end process;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
--- generic map(
--- INSTANCE_ID => 0,
--- LOG2_RXFIFO_DEPTH => 6,
--- LOG2_TXFIFO_DEPTH => 6,
--- SLD_AUTO_INSTANCE_INDEX => "YES"
--- )
--- port map(
--- clk => clk,
--- r_dat => r_dat,
--- r_ena => r_ena,
--- r_val => r_val,
--- rst_n => rst_n,
--- t_dat => t_dat,
--- t_dav => t_dav,
--- t_ena => t_ena,
--- t_pause => t_pause
--- );
---
--- process (clk, rst_n)
--- begin
--- if rst_n = '0' then
--- dataavailable <= std_logic'('0');
--- elsif clk'event and clk = '1' then
--- dataavailable <= NOT fifo_EF;
--- end if;
---
--- end process;
---
---synthesis read_comments_as_HDL off
-end europa;
+ end process;
+
+ fifo_wdata <= av_writedata(7 downto 0);
+ fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
+ av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ readyfordata <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ readyfordata <= not fifo_FF;
+ end if;
+ end process;
+
+ --vhdl renameroo for output signals
+ av_waitrequest <= internal_av_waitrequest;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
+ end process;
+
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
+ end process;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
+ -- generic map(
+ -- INSTANCE_ID => 0,
+ -- LOG2_RXFIFO_DEPTH => 6,
+ -- LOG2_TXFIFO_DEPTH => 6,
+ -- SLD_AUTO_INSTANCE_INDEX => "YES"
+ -- )
+ -- port map(
+ -- clk => clk,
+ -- r_dat => r_dat,
+ -- r_ena => r_ena,
+ -- r_val => r_val,
+ -- rst_n => rst_n,
+ -- t_dat => t_dat,
+ -- t_dav => t_dav,
+ -- t_ena => t_ena,
+ -- t_pause => t_pause
+ -- );
+ --
+ -- process (clk, rst_n)
+ -- begin
+ -- if rst_n = '0' then
+ -- dataavailable <= std_logic'('0');
+ -- elsif clk'event and clk = '1' then
+ -- dataavailable <= NOT fifo_EF;
+ -- end if;
+ --
+ -- end process;
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..68a1b9756e73d17acaeb627e04c372716fd9e831 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 64222401d7c70495e31aafcbeecd90272b38bdb4..fdabd7b57dbeb6788e005a2457084e5190c45c22 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -15,99 +15,99 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
+ -- outputs:
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(31 downto 0)
+ );
+ end component altsyncram;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
+ begin
+ wren <= chipselect and write;
+ clocken0 <= clken and not reset_req;
+ the_altsyncram : altsyncram
+ generic map(
+ byte_size => 8,
+ init_file => INIT_FILE,
+ lpm_type => "altsyncram",
+ maximum_depth => 32768,
+ numwords_a => 32768,
+ operation_mode => "SINGLE_PORT",
+ outdata_reg_a => "UNREGISTERED",
+ ram_block_type => "AUTO",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ read_during_write_mode_port_a => "DONT_CARE",
+ width_a => 32,
+ width_byteena_a => 4,
+ widthad_a => 15
+ )
+ port map(
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
- end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
-begin
- wren <= chipselect and write;
- clocken0 <= clken and not reset_req;
- the_altsyncram : altsyncram
- generic map(
- byte_size => 8,
- init_file => INIT_FILE,
- lpm_type => "altsyncram",
- maximum_depth => 32768,
- numwords_a => 32768,
- operation_mode => "SINGLE_PORT",
- outdata_reg_a => "UNREGISTERED",
- ram_block_type => "AUTO",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- read_during_write_mode_port_a => "DONT_CARE",
- width_a => 32,
- width_byteena_a => 4,
- widthad_a => 15
- )
- port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
- );
- --s1, which is an e_avalon_slave
- --s2, which is an e_avalon_slave
- --vhdl renameroo for output signals
- readdata <= internal_readdata;
-end europa;
+ --s1, which is an e_avalon_slave
+ --s2, which is an e_avalon_slave
+ --vhdl renameroo for output signals
+ readdata <= internal_readdata;
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..500649d8da089ce1009f41be3852c17d19673c7c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..faef008bb80319ce0002573aeb8369f8eb5463d9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..031eaa0af9c383db5a3c0817ba95b7a06f3ebdbc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 0cc60e970e8bf720a6ebe320a18a2ffee267bccc..cc76a06817a980bdbb7f34baa9b4d542c92a3479 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -15,40 +15,41 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) and data_out;
+
process (clk, reset_n)
begin
if reset_n = '0' then
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..0b7dcff4021c0c79e50813f59fca9ff6ee280ed3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..b7feaef4257e3b0b83d070fda492f5065fe72014 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..c3c65aee84b4eaa16e64150da02a14a7aee6164f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..7cae834a564f49a180c0f391cc0f2836e73ead03 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..7a32df88c67781ad32090e018368f72797c9f94f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..cfde8e91765c2b090ec5fe88e8b06f0ecc2bf584 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..73c8f9c0cf46cbf6eb19994466f1a6724d26f8ec 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..c9c446304330b022496042600066e4aefb5f0679 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..e54b9651be45a9e4bc3fc42698883bc10c100db5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..c9fdcffd9c2ab6fb6e8c5393b45c3cfb270e378e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..c80cce2d60ffea663f6db2a5f032abfbcf59eac7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..f956b5a4e798c8bbe347cf55b3207aa9aaeadac6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..ed9ccedfa950200b6d72ecfeab8388b3ba5740f6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index a954c70405f58c881dbee5a2d7c5a50b9fdbe730..12915de2ba26e9c734878d2361eab8e6da7c9e8e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -15,53 +15,54 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
-
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
-end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
+
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(15 downto 0)
+ );
+ end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
clk_en <= std_logic'('1');
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -79,6 +80,7 @@ begin
counter_is_zero <= to_std_logic(((std_logic_vector'("000000000000000") & (internal_counter)) = std_logic_vector'("00000000000000000000000000000000")));
counter_load_value <= std_logic_vector'("11000011010011111");
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -92,6 +94,7 @@ begin
do_start_counter <= std_logic'('1');
do_stop_counter <= std_logic'('0');
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -120,6 +123,7 @@ begin
end process;
timeout_event <= (counter_is_zero) and not (delayed_unxcounter_is_zeroxx0);
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -138,6 +142,7 @@ begin
irq <= timeout_occurred and control_interrupt_enable;
--s1, which is an e_avalon_slave
read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTOR(control_register))))) or ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -152,6 +157,7 @@ begin
period_l_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010"))));
period_h_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000011"))));
control_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001"))));
+
process (clk, reset_n)
begin
if reset_n = '0' then
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..e6864d98a9aad5782a0d0118e9ca0caf75d10111 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 5e0e90fde0e616c1acf47f212484ceb92e1baddf..0d89cb41bb25232bfcc208c8fb6d12df28f6d452 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node0 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node0 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -82,49 +82,49 @@ end unb2b_jesd_node0;
architecture str of unb2b_jesd_node0 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED,
+ QSFP_LED => QSFP_LED,
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..1c2fecffe63864ebecf0883cb4ac85b45871adf0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..c9239eba0d665eaf7a73aa4fd323b4f1018399fc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..9ff4466cf1e3c09a5aca87bda3ff57a943bb16d0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..556545d436abf557e2581ad8cca643a01e7028c9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..bbdcb4db8093469451ae5cfdd64646e45e101a7c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..fa71f3dded5d3faf74199be419de685c295802fb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..59df25d1b28f8518ee8185cee5c580a6347eb34c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..a7de702cec273692f2ab3ebcefef042b77f6fbeb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..c5f8f7bcb06d2ab28322ab1d8cbe579854adcd27 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..2d82124533b1c4ef8538276273ef4abad3fdb2e5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..a8380499642f0d779741f36aac5a45b538fda2b5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..97ced477679b27e0c35f1cc7c44970ebd74a2921 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..0bdc87768e7d9f18c8b87ebe7a276ad87fa96248 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,13 +135,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -174,11 +175,12 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ARP Packet
@@ -215,12 +217,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -246,12 +248,13 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -280,7 +283,7 @@ package common_network_layers_pkg is
constant c_network_icmp_sequence_len : natural := 2;
constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
@@ -300,8 +303,9 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
------------------------------------------------------------------------------
-- UDP Packet
@@ -326,9 +330,9 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-- default field values
constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
@@ -347,9 +351,9 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
package body common_network_layers_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..e2dadbc0250f9bba58022f6aca5b01a2c8a34e08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,51 +454,51 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
-
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
function pow2(n : natural) return natural is
begin
- return 2**n;
+ return 2 ** n;
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
- return natural(integer(ceil(2**real(n))));
+ return natural(integer(ceil(2 ** real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -514,12 +516,12 @@ package body common_pkg is
function is_pow2(n : natural) return boolean is
begin
- return n = 2**true_log2(n);
+ return n = 2 ** true_log2(n);
end;
function true_log_pow2(n : natural) return natural is
begin
- return 2**true_log2(n);
+ return 2 ** true_log2(n);
end;
function ratio(n, d : natural) return natural is
@@ -664,7 +666,7 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2 ** c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -678,7 +680,7 @@ package body common_pkg is
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
- for I in 0 to c_w / (2**(J + 1)) - 1 loop
+ for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "OR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "XOR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
@@ -773,7 +775,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1740,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1750,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2145,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2175,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2181,7 +2185,7 @@ package body common_pkg is
begin
loop_stage : for j in 0 to c_nof_stages - 1 loop
v_prev_stage_pipeline_arr := v_stage_pipeline_arr;
- loop_cell : for i in 0 to c_nof_output_per_cell**j - 1 loop
+ loop_cell : for i in 0 to c_nof_output_per_cell ** j - 1 loop
v_stage_pipeline_arr((i + 1) * c_nof_output_per_cell - 1 downto i * c_nof_output_per_cell) := v_prev_stage_pipeline_arr(i) + (k_cell_pipeline_factor_arr(j) * k_cell_pipeline_arr);
end loop;
end loop;
@@ -2276,8 +2280,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2320,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..08f30597b3d79d527846c94ee83c2007737cb677 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -391,16 +396,16 @@ package dp_stream_pkg is
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
-
end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +420,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +453,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1239,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1272,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1424,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..4add394e3f929dc8f063c90f70d48f0c0f3ec372 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,149 +71,149 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
-
- ------------------------------------------------------------------------------
- -- Definitions for eth demux udp
- ------------------------------------------------------------------------------
-
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
- constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
-
- ------------------------------------------------------------------------------
- -- MM register map
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
- constant c_eth_reg_config_nof_words : natural := 4;
- constant c_eth_reg_control_nof_words : natural := 1;
- constant c_eth_reg_frame_nof_words : natural := 1;
- constant c_eth_reg_status_nof_words : natural := 1;
-
- constant c_eth_reg_demux_wi : natural := 0;
- constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
- constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
- constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
- constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
- constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
-
- -- . write/read back registers
- type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
- type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
- end record;
-
- type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
- end record;
-
- type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- . read only registers
- type t_eth_mm_reg_frame is record
- is_dhcp : std_logic;
- is_udp_ctrl_port : std_logic;
- is_udp : std_logic;
- is_icmp : std_logic;
- ip_address_match : std_logic;
- ip_checksum_is_ok : std_logic;
- is_ip : std_logic;
- is_arp : std_logic;
- mac_address_match : std_logic;
- eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
- end record;
-
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
- end record;
-
- constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
- constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
-
- type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
-
- ------------------------------------------------------------------------------
- -- Definitions for eth_mm_registers
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
-
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth demux udp
+ ------------------------------------------------------------------------------
+
+ constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ constant c_eth_nof_channels : natural := 2 ** c_eth_channel_w;
+
+ ------------------------------------------------------------------------------
+ -- MM register map
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
+ constant c_eth_reg_config_nof_words : natural := 4;
+ constant c_eth_reg_control_nof_words : natural := 1;
+ constant c_eth_reg_frame_nof_words : natural := 1;
+ constant c_eth_reg_status_nof_words : natural := 1;
+
+ constant c_eth_reg_demux_wi : natural := 0;
+ constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
+ constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
+ constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
+ constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
+ constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
+
+ -- . write/read back registers
+ type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ type t_eth_mm_reg_demux is record
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
+ udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ end record;
+
+ type t_eth_mm_reg_config is record
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ end record;
+
+ type t_eth_mm_reg_control is record
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_request : std_logic; -- 1 bit
+ tx_en : std_logic; -- 1 bit
+ rx_en : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_control_bi is record -- bit indices
+ tx_nof_words : natural; -- [26:18]
+ tx_empty : natural; -- [17:16]
+ tx_request : natural; -- [2]
+ tx_en : natural; -- [1]
+ rx_en : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- . read only registers
+ type t_eth_mm_reg_frame is record
+ is_dhcp : std_logic;
+ is_udp_ctrl_port : std_logic;
+ is_udp : std_logic;
+ is_icmp : std_logic;
+ ip_address_match : std_logic;
+ ip_checksum_is_ok : std_logic;
+ is_ip : std_logic;
+ is_arp : std_logic;
+ mac_address_match : std_logic;
+ eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
+ end record;
+
+ type t_eth_mm_reg_frame_bi is record -- bit indices
+ is_dhcp : natural; -- [15]
+ is_udp_ctrl_port : natural; -- [14]
+ is_udp : natural; -- [13]
+ is_icmp : natural; -- [12]
+ ip_address_match : natural; -- [11]
+ ip_checksum_is_ok : natural; -- [10]
+ is_ip : natural; -- [9]
+ is_arp : natural; -- [8]
+ mac_address_match : natural; -- [7]
+ eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ end record;
+
+ constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
+ constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
+
+ type t_eth_mm_reg_status is record
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_avail : std_logic; -- 1 bit
+ tx_done : std_logic; -- 1 bit
+ rx_avail : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_status_bi is record -- bit indices
+ rx_nof_words : natural; -- [26:18]
+ rx_empty : natural; -- [17:16]
+ tx_avail : natural; -- [2]
+ tx_done : natural; -- [1]
+ rx_avail : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- Register mapping functions
+ function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth_mm_registers
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
package body eth_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..2b6431ed8fe167e96d75dc9d5b40613bbeaa2f34 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
@@ -31,7 +31,7 @@ package tech_tse_pkg is
constant c_tech_tse_data_w : natural := c_word_w; -- = 32
constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
+ constant c_tech_tse_symbol_max : natural := 2 ** c_tech_tse_symbol_w - 1; -- = 255
constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
@@ -80,7 +80,6 @@ package tech_tse_pkg is
crs : std_logic;
col : std_logic;
end record;
-
end tech_tse_pkg;
package body tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index d648f26fb1cb1a3e9c804714afad5c500ffa4798..97ced477679b27e0c35f1cc7c44970ebd74a2921 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -26,10 +26,10 @@
-- . The avs2_eth_coe_hw.tcl determines the read latency per port
library IEEE, common_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use work.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use work.eth_pkg.all;
entity avs2_eth_coe is
port (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index e879f1b9edecdcf0c9866d6359c01c0b6a645338..0bdc87768e7d9f18c8b87ebe7a276ad87fa96248 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -23,9 +23,9 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -85,9 +85,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -134,13 +135,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -174,11 +175,12 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ARP Packet
@@ -215,12 +217,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -246,12 +248,13 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -280,7 +283,7 @@ package common_network_layers_pkg is
constant c_network_icmp_sequence_len : natural := 2;
constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
@@ -300,8 +303,9 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
------------------------------------------------------------------------------
-- UDP Packet
@@ -326,9 +330,9 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-- default field values
constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
@@ -347,9 +351,9 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
-
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
end common_network_layers_pkg;
package body common_network_layers_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf..e2dadbc0250f9bba58022f6aca5b01a2c8a34e08 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -30,9 +30,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -332,7 +332,7 @@ package common_pkg is
function TO_SVEC_32(dec : integer) return std_logic_vector; -- = TO_SVEC() with w=32 for t_slv_32_arr slv elements
--- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
+ -- The RESIZE for SIGNED in IEEE.NUMERIC_STD extends the sign bit or it keeps the sign bit and LS part. This
-- behaviour of preserving the sign bit is less suitable for DSP and not necessary in general. A more
-- appropriate approach is to ignore the MSbit sign and just keep the LS part. For too large values this
-- means that the result gets wrapped, but that is fine for default behaviour, because that is also what
@@ -353,7 +353,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -429,20 +429,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -452,51 +454,51 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
-
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
function pow2(n : natural) return natural is
begin
- return 2**n;
+ return 2 ** n;
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
- return natural(integer(ceil(2**real(n))));
+ return natural(integer(ceil(2 ** real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -514,12 +516,12 @@ package body common_pkg is
function is_pow2(n : natural) return boolean is
begin
- return n = 2**true_log2(n);
+ return n = 2 ** true_log2(n);
end;
function true_log_pow2(n : natural) return natural is
begin
- return 2**true_log2(n);
+ return 2 ** true_log2(n);
end;
function ratio(n, d : natural) return natural is
@@ -664,7 +666,7 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2 ** c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -678,7 +680,7 @@ package body common_pkg is
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
- for I in 0 to c_w / (2**(J + 1)) - 1 loop
+ for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "OR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "XOR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
@@ -773,7 +775,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1738,8 +1740,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -1748,8 +1750,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2143,16 +2145,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2172,8 +2175,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2181,7 +2185,7 @@ package body common_pkg is
begin
loop_stage : for j in 0 to c_nof_stages - 1 loop
v_prev_stage_pipeline_arr := v_stage_pipeline_arr;
- loop_cell : for i in 0 to c_nof_output_per_cell**j - 1 loop
+ loop_cell : for i in 0 to c_nof_output_per_cell ** j - 1 loop
v_stage_pipeline_arr((i + 1) * c_nof_output_per_cell - 1 downto i * c_nof_output_per_cell) := v_prev_stage_pipeline_arr(i) + (k_cell_pipeline_factor_arr(j) * k_cell_pipeline_arr);
end loop;
end loop;
@@ -2276,8 +2280,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -2316,9 +2320,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 7b6d1a2da0ec2558d87aa708358be0b79c70944d..08f30597b3d79d527846c94ee83c2007737cb677 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Resize functions to fit an integer or an SLV in the corresponding t_dp_sosi field width
-- . Use these functions to assign sosi data TO a record field
@@ -353,11 +358,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -391,16 +396,16 @@ package dp_stream_pkg is
-- Deconcatenate data and complex re,im fields from SOSI into SOSI array
function func_dp_stream_deconcat(snk_in : t_dp_sosi; nof_streams, data_w : natural) return t_dp_sosi_arr; -- Deconcat SOSI data
function func_dp_stream_deconcat(src_out_arr : t_dp_siso_arr) return t_dp_siso; -- Wire SISO_ARR(0) to single SISO
-
end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -415,20 +420,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -446,10 +453,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -1231,16 +1239,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1264,7 +1272,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1416,11 +1424,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index 103667575791b885ea6d707accd5dc6c04bcb535..4add394e3f929dc8f063c90f70d48f0c0f3ec372 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, tech_tse_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
package eth_pkg is
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
@@ -44,12 +44,12 @@ package eth_pkg is
-- Actual frame space in RAM <= c_eth_max_frame_sz, default >= 1520, <= 9020 for jumbo
--CONSTANT c_eth_frame_sz : NATURAL := 1024*3/2; -- Use 1536 = 3/2 M9K, to benefit from Rx and Tx in single buffer of 2*1.5=3 M9K, but does
- -- yield simulation warning: Address pointed at port A is out of bound!
+ -- yield simulation warning: Address pointed at port A is out of bound!
--CONSTANT c_eth_frame_sz : NATURAL := 1024*8; -- Use 8192 = 8 M9K for jumbo frame support with payload size <= 8172
--CONSTANT c_eth_frame_sz : NATURAL := 1024*9; -- Use 9216 = 9 M9K for jumbo frame support with payload size <= 9000
constant c_eth_frame_sz : natural := 1024 * 2; -- Use 2048 = 2 M9K to avoid simulation warning: Address pointed at port A is out of bound!
- -- when the module is used in an Nios II SOPC system
- -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
+ -- when the module is used in an Nios II SOPC system
+ -- The FIFOs seem to require nof words to be a power of 2, but that is taken care of locally if necessary
constant c_eth_frame_nof_words : natural := c_eth_frame_sz / c_word_sz;
constant c_eth_frame_nof_words_w : natural := ceil_log2(c_eth_frame_nof_words); -- >= 9 bit, <= 12 bit
@@ -71,149 +71,149 @@ package eth_pkg is
is_dhcp : std_logic;
end record;
- constant c_eth_hdr_status_rst : t_eth_hdr_status := ('0', '0', '0', '0',
- (others => '0'), '0', '0',
- (others => '0'), '0');
-
- ------------------------------------------------------------------------------
- -- Definitions for eth demux udp
- ------------------------------------------------------------------------------
-
- constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
- constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
- constant c_eth_nof_channels : natural := 2**c_eth_channel_w;
-
- ------------------------------------------------------------------------------
- -- MM register map
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
- constant c_eth_reg_config_nof_words : natural := 4;
- constant c_eth_reg_control_nof_words : natural := 1;
- constant c_eth_reg_frame_nof_words : natural := 1;
- constant c_eth_reg_status_nof_words : natural := 1;
-
- constant c_eth_reg_demux_wi : natural := 0;
- constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
- constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
- constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
- constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
- constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
-
- -- . write/read back registers
- type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
- type t_eth_mm_reg_demux is record
- udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
- udp_ports : t_eth_demux_ports_arr; -- [15:0]
- end record;
-
- type t_eth_mm_reg_config is record
- udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
- ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
- mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
- end record;
-
- type t_eth_mm_reg_control is record
- tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_request : std_logic; -- 1 bit
- tx_en : std_logic; -- 1 bit
- rx_en : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_control_bi is record -- bit indices
- tx_nof_words : natural; -- [26:18]
- tx_empty : natural; -- [17:16]
- tx_request : natural; -- [2]
- tx_en : natural; -- [1]
- rx_en : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- . read only registers
- type t_eth_mm_reg_frame is record
- is_dhcp : std_logic;
- is_udp_ctrl_port : std_logic;
- is_udp : std_logic;
- is_icmp : std_logic;
- ip_address_match : std_logic;
- ip_checksum_is_ok : std_logic;
- is_ip : std_logic;
- is_arp : std_logic;
- mac_address_match : std_logic;
- eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
- end record;
-
- type t_eth_mm_reg_frame_bi is record -- bit indices
- is_dhcp : natural; -- [15]
- is_udp_ctrl_port : natural; -- [14]
- is_udp : natural; -- [13]
- is_icmp : natural; -- [12]
- ip_address_match : natural; -- [11]
- ip_checksum_is_ok : natural; -- [10]
- is_ip : natural; -- [9]
- is_arp : natural; -- [8]
- mac_address_match : natural; -- [7]
- eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
- end record;
-
- constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
- constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
-
- type t_eth_mm_reg_status is record
- rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
- rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
- tx_avail : std_logic; -- 1 bit
- tx_done : std_logic; -- 1 bit
- rx_avail : std_logic; -- 1 bit
- end record;
-
- type t_eth_mm_reg_status_bi is record -- bit indices
- rx_nof_words : natural; -- [26:18]
- rx_empty : natural; -- [17:16]
- tx_avail : natural; -- [2]
- tx_done : natural; -- [1]
- rx_avail : natural; -- [0]
- end record;
-
- constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
- constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
-
- -- Register mapping functions
- function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
- function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
- function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
- function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
- function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
- function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
- function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
- function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
- function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
- function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
-
- ------------------------------------------------------------------------------
- -- Definitions for eth_mm_registers
- ------------------------------------------------------------------------------
-
- constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
- c_eth_reg_config_nof_words +
- c_eth_reg_control_nof_words +
- c_eth_reg_frame_nof_words +
- c_eth_reg_status_nof_words;
- constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
-
- ------------------------------------------------------------------------------
- -- Definitions for ETH Rx packet buffer and Tx packet buffer
- ------------------------------------------------------------------------------
-
- -- Use MM bus data width = c_word_w = 32
- constant c_eth_ram_rx_offset : natural := 0;
- constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
- constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
- constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
-
+ constant c_eth_hdr_status_rst : t_eth_hdr_status := (
+ '0', '0', '0', '0',
+ (others => '0'), '0', '0',
+ (others => '0'), '0');
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth demux udp
+ ------------------------------------------------------------------------------
+
+ constant c_eth_nof_udp_ports : natural := 4; -- support 2, 4, 8, ... UDP off-load ports
+ constant c_eth_channel_w : natural := ceil_log2(c_eth_nof_udp_ports + 1); -- + 1 for all other packets that go to the default port
+ constant c_eth_nof_channels : natural := 2 ** c_eth_channel_w;
+
+ ------------------------------------------------------------------------------
+ -- MM register map
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_demux_nof_words : natural := c_eth_nof_udp_ports;
+ constant c_eth_reg_config_nof_words : natural := 4;
+ constant c_eth_reg_control_nof_words : natural := 1;
+ constant c_eth_reg_frame_nof_words : natural := 1;
+ constant c_eth_reg_status_nof_words : natural := 1;
+
+ constant c_eth_reg_demux_wi : natural := 0;
+ constant c_eth_reg_config_wi : natural := c_eth_reg_demux_wi + c_eth_reg_demux_nof_words;
+ constant c_eth_reg_control_wi : natural := c_eth_reg_config_wi + c_eth_reg_config_nof_words;
+ constant c_eth_reg_frame_wi : natural := c_eth_reg_control_wi + c_eth_reg_control_nof_words;
+ constant c_eth_reg_status_wi : natural := c_eth_reg_frame_wi + c_eth_reg_frame_nof_words;
+ constant c_eth_reg_continue_wi : natural := c_eth_reg_status_wi + c_eth_reg_status_nof_words;
+
+ -- . write/read back registers
+ type t_eth_demux_ports_arr is array(1 to c_eth_nof_udp_ports) of std_logic_vector(c_network_udp_port_w - 1 downto 0);
+ type t_eth_mm_reg_demux is record
+ udp_ports_en : std_logic_vector(1 to c_eth_nof_udp_ports); -- [16]
+ udp_ports : t_eth_demux_ports_arr; -- [15:0]
+ end record;
+
+ type t_eth_mm_reg_config is record
+ udp_port : std_logic_vector(c_network_udp_port_w - 1 downto 0); -- [15:0]
+ ip_address : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- [31:0]
+ mac_address : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0); -- [15:0], [31:0]
+ end record;
+
+ type t_eth_mm_reg_control is record
+ tx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ tx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_request : std_logic; -- 1 bit
+ tx_en : std_logic; -- 1 bit
+ rx_en : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_control_bi is record -- bit indices
+ tx_nof_words : natural; -- [26:18]
+ tx_empty : natural; -- [17:16]
+ tx_request : natural; -- [2]
+ tx_en : natural; -- [1]
+ rx_en : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_control_bi : t_eth_mm_reg_control_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_control_rst : t_eth_mm_reg_control := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- . read only registers
+ type t_eth_mm_reg_frame is record
+ is_dhcp : std_logic;
+ is_udp_ctrl_port : std_logic;
+ is_udp : std_logic;
+ is_icmp : std_logic;
+ ip_address_match : std_logic;
+ ip_checksum_is_ok : std_logic;
+ is_ip : std_logic;
+ is_arp : std_logic;
+ mac_address_match : std_logic;
+ eth_mac_error : std_logic_vector(c_eth_error_w - 1 downto 0);
+ end record;
+
+ type t_eth_mm_reg_frame_bi is record -- bit indices
+ is_dhcp : natural; -- [15]
+ is_udp_ctrl_port : natural; -- [14]
+ is_udp : natural; -- [13]
+ is_icmp : natural; -- [12]
+ ip_address_match : natural; -- [11]
+ ip_checksum_is_ok : natural; -- [10]
+ is_ip : natural; -- [9]
+ is_arp : natural; -- [8]
+ mac_address_match : natural; -- [7]
+ eth_mac_error : natural; -- [6] not used, [5:0] = TSE MAC error
+ end record;
+
+ constant c_eth_mm_reg_frame_bi : t_eth_mm_reg_frame_bi := (15, 14, 13, 12, 11, 10, 9, 8, 7, 0);
+ constant c_eth_mm_reg_frame_rst : t_eth_mm_reg_frame := ('0', '0', '0', '0', '0', '0', '0', '0', '0', (others => '0'));
+
+ type t_eth_mm_reg_status is record
+ rx_nof_words : std_logic_vector(c_eth_max_frame_nof_words_w - 1 downto 0); -- 12 bit
+ rx_empty : std_logic_vector(c_eth_empty_w - 1 downto 0); -- 2 bit
+ tx_avail : std_logic; -- 1 bit
+ tx_done : std_logic; -- 1 bit
+ rx_avail : std_logic; -- 1 bit
+ end record;
+
+ type t_eth_mm_reg_status_bi is record -- bit indices
+ rx_nof_words : natural; -- [26:18]
+ rx_empty : natural; -- [17:16]
+ tx_avail : natural; -- [2]
+ tx_done : natural; -- [1]
+ rx_avail : natural; -- [0]
+ end record;
+
+ constant c_eth_mm_reg_status_bi : t_eth_mm_reg_status_bi := (18, 16, 2, 1, 0);
+ constant c_eth_mm_reg_status_rst : t_eth_mm_reg_status := ((others => '0'), (others => '0'), '0', '0', '0');
+
+ -- Register mapping functions
+ function func_eth_mm_reg_demux( mm_reg : std_logic_vector) return t_eth_mm_reg_demux;
+ function func_eth_mm_reg_demux( mm_reg : t_eth_mm_reg_demux) return std_logic_vector;
+ function func_eth_mm_reg_config( mm_reg : std_logic_vector) return t_eth_mm_reg_config;
+ function func_eth_mm_reg_config( mm_reg : t_eth_mm_reg_config) return std_logic_vector;
+ function func_eth_mm_reg_control(mm_reg : std_logic_vector) return t_eth_mm_reg_control;
+ function func_eth_mm_reg_control(mm_reg : t_eth_mm_reg_control) return std_logic_vector;
+ function func_eth_mm_reg_frame( mm_reg : std_logic_vector) return t_eth_mm_reg_frame;
+ function func_eth_mm_reg_frame( mm_reg : t_eth_mm_reg_frame) return std_logic_vector;
+ function func_eth_mm_reg_status( mm_reg : std_logic_vector) return t_eth_mm_reg_status;
+ function func_eth_mm_reg_status( mm_reg : t_eth_mm_reg_status) return std_logic_vector;
+
+ ------------------------------------------------------------------------------
+ -- Definitions for eth_mm_registers
+ ------------------------------------------------------------------------------
+
+ constant c_eth_reg_nof_words : natural := c_eth_reg_demux_nof_words +
+ c_eth_reg_config_nof_words +
+ c_eth_reg_control_nof_words +
+ c_eth_reg_frame_nof_words +
+ c_eth_reg_status_nof_words;
+ constant c_eth_reg_addr_w : natural := ceil_log2(c_eth_reg_nof_words + 1); -- + 1 for c_eth_continue_wi
+
+ ------------------------------------------------------------------------------
+ -- Definitions for ETH Rx packet buffer and Tx packet buffer
+ ------------------------------------------------------------------------------
+
+ -- Use MM bus data width = c_word_w = 32
+ constant c_eth_ram_rx_offset : natural := 0;
+ constant c_eth_ram_tx_offset : natural := c_eth_frame_nof_words;
+ constant c_eth_ram_nof_words : natural := c_eth_frame_nof_words * 2;
+ constant c_eth_ram_addr_w : natural := ceil_log2(c_eth_ram_nof_words);
end eth_pkg;
package body eth_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 177eb750c7386763043b7282d1bfb4b3a3fc6636..2b6431ed8fe167e96d75dc9d5b40613bbeaa2f34 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package tech_tse_pkg is
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
@@ -31,7 +31,7 @@ package tech_tse_pkg is
constant c_tech_tse_data_w : natural := c_word_w; -- = 32
constant c_tech_tse_symbol_w : natural := c_byte_w; -- = 8
- constant c_tech_tse_symbol_max : natural := 2**c_tech_tse_symbol_w - 1; -- = 255
+ constant c_tech_tse_symbol_max : natural := 2 ** c_tech_tse_symbol_w - 1; -- = 255
constant c_tech_tse_symbols_per_beat : natural := c_tech_tse_data_w / c_tech_tse_symbol_w; -- = 4
constant c_tech_tse_pcs_reg_addr_w : natural := 5; -- = max 32 PCS registers
@@ -80,7 +80,6 @@ package tech_tse_pkg is
crs : std_logic;
col : std_logic;
end record;
-
end tech_tse_pkg;
package body tech_tse_pkg is
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..1db149d4b3900a9632e3cca9845ca4e53adaf0ea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..f5b386839514684123794a757628cb3f3e7f6fdc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..530ffe22745aa5e71d9502cb15c001f1f2bcc594 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..e1d0e8ddbe0d7c28e35f6a332fcc00bb48a47bc5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index f745d32d0b9a636140d0cb000f2acf129a6741ad..3921081b642736800e1c9a37bb29bc27527015f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -15,55 +15,55 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library std;
-use std.textio.all;
+ use std.textio.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
begin
---synthesis translate_off
- process (clk)
+ --synthesis translate_off
+ process (clk)
variable write_line : line;
- begin
- if clk'event and clk = '1' then
- if std_logic'(fifo_wr) = '1' then
- write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
- write(write_line, string'(""));
- write(output, write_line.all);
- deallocate (write_line);
- end if;
+ begin
+ if clk'event and clk = '1' then
+ if std_logic'(fifo_wr) = '1' then
+ write(write_line, character'val(CONV_INTEGER(fifo_wdata)));
+ write(write_line, string'(""));
+ write(output, write_line.all);
+ deallocate (write_line);
end if;
- end process;
+ end if;
+ end process;
- wfifo_used <= A_REP(std_logic'('0'), 6);
- r_dat <= A_REP(std_logic'('0'), 8);
- fifo_FF <= std_logic'('0');
- wfifo_empty <= std_logic'('1');
---synthesis translate_on
+ wfifo_used <= A_REP(std_logic'('0'), 6);
+ r_dat <= A_REP(std_logic'('0'), 8);
+ fifo_FF <= std_logic'('0');
+ wfifo_empty <= std_logic'('1');
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -71,96 +71,96 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_FF : std_logic;
- signal internal_r_dat : std_logic_vector(7 downto 0);
- signal internal_wfifo_empty : std_logic;
- signal internal_wfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_FF <= internal_fifo_FF;
- --vhdl renameroo for output signals
- r_dat <= internal_r_dat;
- --vhdl renameroo for output signals
- wfifo_empty <= internal_wfifo_empty;
- --vhdl renameroo for output signals
- wfifo_used <= internal_wfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_FF : std_logic;
+ signal internal_r_dat : std_logic_vector(7 downto 0);
+ signal internal_wfifo_empty : std_logic;
+ signal internal_wfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_FF <= internal_fifo_FF;
+ --vhdl renameroo for output signals
+ r_dat <= internal_r_dat;
+ --vhdl renameroo for output signals
+ wfifo_empty <= internal_wfifo_empty;
+ --vhdl renameroo for output signals
+ wfifo_used <= internal_wfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w
port map(
fifo_FF => internal_fifo_FF,
r_dat => internal_r_dat,
@@ -171,103 +171,103 @@ begin
fifo_wr => fifo_wr
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- wfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => fifo_wdata,
--- empty => internal_wfifo_empty,
--- full => internal_fifo_FF,
--- q => internal_r_dat,
--- rdreq => rd_wfifo,
--- usedw => internal_wfifo_used,
--- wrreq => fifo_wr
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- wfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => fifo_wdata,
+ -- empty => internal_wfifo_empty,
+ -- full => internal_fifo_FF,
+ -- q => internal_r_dat,
+ -- rdreq => rd_wfifo,
+ -- usedw => internal_wfifo_used,
+ -- wrreq => fifo_wr
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- signal bytes_left : std_logic_vector(31 downto 0);
- signal fifo_rd_d : std_logic;
- signal internal_rfifo_full1 : std_logic;
- signal new_rom : std_logic;
- signal num_bytes : std_logic_vector(31 downto 0);
- signal rfifo_entries : std_logic_vector(6 downto 0);
+ signal bytes_left : std_logic_vector(31 downto 0);
+ signal fifo_rd_d : std_logic;
+ signal internal_rfifo_full1 : std_logic;
+ signal new_rom : std_logic;
+ signal num_bytes : std_logic_vector(31 downto 0);
+ signal rfifo_entries : std_logic_vector(6 downto 0);
begin
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
---synthesis translate_off
- -- Generate rfifo_entries for simulation
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- bytes_left <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rd_d <= std_logic'('0');
- elsif clk'event and clk = '1' then
- fifo_rd_d <= fifo_rd;
- -- decrement on read
- if std_logic'(fifo_rd_d) = '1' then
- bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
- end if;
- -- catch new contents
- if std_logic'(new_rom) = '1' then
- bytes_left <= num_bytes;
- end if;
+ --synthesis translate_off
+ -- Generate rfifo_entries for simulation
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ bytes_left <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rd_d <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ fifo_rd_d <= fifo_rd;
+ -- decrement on read
+ if std_logic'(fifo_rd_d) = '1' then
+ bytes_left <= A_EXT (((std_logic_vector'("0") & (bytes_left)) - (std_logic_vector'("00000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 32);
+ end if;
+ -- catch new contents
+ if std_logic'(new_rom) = '1' then
+ bytes_left <= num_bytes;
end if;
- end process;
-
- fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
- internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
- rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
- rfifo_used <= rfifo_entries(5 downto 0);
- new_rom <= std_logic'('0');
- num_bytes <= std_logic_vector'("00000000000000000000000000000000");
- fifo_rdata <= std_logic_vector'("00000000");
---synthesis translate_on
+ end if;
+ end process;
+
+ fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
+ internal_rfifo_full1 <= to_std_logic((bytes_left > std_logic_vector'("00000000000000000000000001000000")));
+ rfifo_entries <= A_EXT (A_WE_StdLogicVector((std_logic'((internal_rfifo_full1)) = '1'), std_logic_vector'("00000000000000000000000001000000"), bytes_left), 7);
+ rfifo_used <= rfifo_entries(5 downto 0);
+ new_rom <= std_logic'('0');
+ num_bytes <= std_logic_vector'("00000000000000000000000000000000");
+ fifo_rdata <= std_logic_vector'("00000000");
+ --synthesis translate_on
end europa;
-- turn off superfluous VHDL processor warnings
@@ -275,97 +275,97 @@ end europa;
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
---synthesis translate_off
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- component scfifo is
---GENERIC (
--- lpm_hint : STRING;
--- lpm_numwords : NATURAL;
--- lpm_showahead : STRING;
--- lpm_type : STRING;
--- lpm_width : NATURAL;
--- lpm_widthu : NATURAL;
--- overflow_checking : STRING;
--- underflow_checking : STRING;
--- use_eab : STRING
--- );
--- PORT (
--- signal full : OUT STD_LOGIC;
--- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
--- signal empty : OUT STD_LOGIC;
--- signal rdreq : IN STD_LOGIC;
--- signal aclr : IN STD_LOGIC;
--- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal clock : IN STD_LOGIC;
--- signal wrreq : IN STD_LOGIC
--- );
--- end component scfifo;
---synthesis read_comments_as_HDL off
- signal internal_fifo_EF : std_logic;
- signal internal_fifo_rdata : std_logic_vector(7 downto 0);
- signal internal_rfifo_full : std_logic;
- signal internal_rfifo_used : std_logic_vector(5 downto 0);
-begin
- --vhdl renameroo for output signals
- fifo_EF <= internal_fifo_EF;
- --vhdl renameroo for output signals
- fifo_rdata <= internal_fifo_rdata;
- --vhdl renameroo for output signals
- rfifo_full <= internal_rfifo_full;
- --vhdl renameroo for output signals
- rfifo_used <= internal_rfifo_used;
---synthesis translate_off
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
+ --synthesis translate_off
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- component scfifo is
+ --GENERIC (
+ -- lpm_hint : STRING;
+ -- lpm_numwords : NATURAL;
+ -- lpm_showahead : STRING;
+ -- lpm_type : STRING;
+ -- lpm_width : NATURAL;
+ -- lpm_widthu : NATURAL;
+ -- overflow_checking : STRING;
+ -- underflow_checking : STRING;
+ -- use_eab : STRING
+ -- );
+ -- PORT (
+ -- signal full : OUT STD_LOGIC;
+ -- signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal usedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+ -- signal empty : OUT STD_LOGIC;
+ -- signal rdreq : IN STD_LOGIC;
+ -- signal aclr : IN STD_LOGIC;
+ -- signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal clock : IN STD_LOGIC;
+ -- signal wrreq : IN STD_LOGIC
+ -- );
+ -- end component scfifo;
+ --synthesis read_comments_as_HDL off
+ signal internal_fifo_EF : std_logic;
+ signal internal_fifo_rdata : std_logic_vector(7 downto 0);
+ signal internal_rfifo_full : std_logic;
+ signal internal_rfifo_used : std_logic_vector(5 downto 0);
+ begin
+ --vhdl renameroo for output signals
+ fifo_EF <= internal_fifo_EF;
+ --vhdl renameroo for output signals
+ fifo_rdata <= internal_fifo_rdata;
+ --vhdl renameroo for output signals
+ rfifo_full <= internal_rfifo_full;
+ --vhdl renameroo for output signals
+ rfifo_used <= internal_rfifo_used;
+ --synthesis translate_off
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r
port map(
fifo_EF => internal_fifo_EF,
fifo_rdata => internal_fifo_rdata,
@@ -376,344 +376,347 @@ begin
rst_n => rst_n
);
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- rfifo : scfifo
--- generic map(
--- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
--- lpm_numwords => 64,
--- lpm_showahead => "OFF",
--- lpm_type => "scfifo",
--- lpm_width => 8,
--- lpm_widthu => 6,
--- overflow_checking => "OFF",
--- underflow_checking => "OFF",
--- use_eab => "ON"
--- )
--- port map(
--- aclr => fifo_clear,
--- clock => clk,
--- data => t_dat,
--- empty => internal_fifo_EF,
--- full => internal_rfifo_full,
--- q => internal_fifo_rdata,
--- rdreq => fifo_rd,
--- usedw => internal_rfifo_used,
--- wrreq => wr_rfifo
--- );
---
---synthesis read_comments_as_HDL off
-end europa;
-
--- turn off superfluous VHDL processor warnings
--- altera message_level Level1
--- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- rfifo : scfifo
+ -- generic map(
+ -- lpm_hint => "RAM_BLOCK_TYPE=AUTO",
+ -- lpm_numwords => 64,
+ -- lpm_showahead => "OFF",
+ -- lpm_type => "scfifo",
+ -- lpm_width => 8,
+ -- lpm_widthu => 6,
+ -- overflow_checking => "OFF",
+ -- underflow_checking => "OFF",
+ -- use_eab => "ON"
+ -- )
+ -- port map(
+ -- aclr => fifo_clear,
+ -- clock => clk,
+ -- data => t_dat,
+ -- empty => internal_fifo_EF,
+ -- full => internal_rfifo_full,
+ -- q => internal_fifo_rdata,
+ -- rdreq => fifo_rd,
+ -- usedw => internal_rfifo_used,
+ -- wrreq => wr_rfifo
+ -- );
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
+
+ -- turn off superfluous VHDL processor warnings
+ -- altera message_level Level1
+ -- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.all;
+ use altera_mf.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
library lpm;
-use lpm.all;
+ use lpm.all;
entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
- port (
- -- inputs:
- signal av_address : in std_logic;
- signal av_chipselect : in std_logic;
- signal av_read_n : in std_logic;
- signal av_write_n : in std_logic;
- signal av_writedata : in std_logic_vector(31 downto 0);
- signal clk : in std_logic;
- signal rst_n : in std_logic;
-
- -- outputs:
- signal av_irq : out std_logic;
- signal av_readdata : out std_logic_vector(31 downto 0);
- signal av_waitrequest : out std_logic;
- signal dataavailable : out std_logic;
- signal readyfordata : out std_logic
- );
-attribute ALTERA_ATTRIBUTE : string;
-attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
-end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
-
-architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_wdata : in std_logic_vector(7 downto 0);
- signal fifo_wr : in std_logic;
- signal rd_wfifo : in std_logic;
-
- -- outputs:
- signal fifo_FF : out std_logic;
- signal r_dat : out std_logic_vector(7 downto 0);
- signal wfifo_empty : out std_logic;
- signal wfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
-component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
- port (
- -- inputs:
- signal clk : in std_logic;
- signal fifo_clear : in std_logic;
- signal fifo_rd : in std_logic;
- signal rst_n : in std_logic;
- signal t_dat : in std_logic_vector(7 downto 0);
- signal wr_rfifo : in std_logic;
-
- -- outputs:
- signal fifo_EF : out std_logic;
- signal fifo_rdata : out std_logic_vector(7 downto 0);
- signal rfifo_full : out std_logic;
- signal rfifo_used : out std_logic_vector(5 downto 0)
- );
-end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
---synthesis read_comments_as_HDL on
--- component alt_jtag_atlantic is
---GENERIC (
--- INSTANCE_ID : NATURAL;
--- LOG2_RXFIFO_DEPTH : NATURAL;
--- LOG2_TXFIFO_DEPTH : NATURAL;
--- SLD_AUTO_INSTANCE_INDEX : STRING
--- );
--- PORT (
--- signal t_pause : OUT STD_LOGIC;
--- signal r_ena : OUT STD_LOGIC;
--- signal t_ena : OUT STD_LOGIC;
--- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal t_dav : IN STD_LOGIC;
--- signal rst_n : IN STD_LOGIC;
--- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- signal r_val : IN STD_LOGIC;
--- signal clk : IN STD_LOGIC
--- );
--- end component alt_jtag_atlantic;
---synthesis read_comments_as_HDL off
- signal ac : std_logic;
- signal activity : std_logic;
- signal fifo_AE : std_logic;
- signal fifo_AF : std_logic;
- signal fifo_EF : std_logic;
- signal fifo_FF : std_logic;
- signal fifo_clear : std_logic;
- signal fifo_rd : std_logic;
- signal fifo_rdata : std_logic_vector(7 downto 0);
- signal fifo_wdata : std_logic_vector(7 downto 0);
- signal fifo_wr : std_logic;
- signal ien_AE : std_logic;
- signal ien_AF : std_logic;
- signal internal_av_waitrequest : std_logic;
- signal ipen_AE : std_logic;
- signal ipen_AF : std_logic;
- signal pause_irq : std_logic;
- signal r_dat : std_logic_vector(7 downto 0);
- signal r_ena : std_logic;
- signal r_val : std_logic;
- signal rd_wfifo : std_logic;
- signal read_0 : std_logic;
- signal rfifo_full : std_logic;
- signal rfifo_used : std_logic_vector(5 downto 0);
- signal rvalid : std_logic;
- signal sim_r_ena : std_logic;
- signal sim_t_dat : std_logic;
- signal sim_t_ena : std_logic;
- signal sim_t_pause : std_logic;
- signal t_dat : std_logic_vector(7 downto 0);
- signal t_dav : std_logic;
- signal t_ena : std_logic;
- signal t_pause : std_logic;
- signal wfifo_empty : std_logic;
- signal wfifo_used : std_logic_vector(5 downto 0);
- signal woverflow : std_logic;
- signal wr_rfifo : std_logic;
-begin
- --avalon_jtag_slave, which is an e_avalon_slave
- rd_wfifo <= r_ena and not wfifo_empty;
- wr_rfifo <= t_ena and not rfifo_full;
- fifo_clear <= not rst_n;
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
- port map(
- fifo_FF => fifo_FF,
- r_dat => r_dat,
- wfifo_empty => wfifo_empty,
- wfifo_used => wfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_wdata => fifo_wdata,
- fifo_wr => fifo_wr,
- rd_wfifo => rd_wfifo
- );
-
- --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
- the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
- port map(
- fifo_EF => fifo_EF,
- fifo_rdata => fifo_rdata,
- rfifo_full => rfifo_full,
- rfifo_used => rfifo_used,
- clk => clk,
- fifo_clear => fifo_clear,
- fifo_rd => fifo_rd,
- rst_n => rst_n,
- t_dat => t_dat,
- wr_rfifo => wr_rfifo
+ port (
+ -- inputs:
+ signal av_address : in std_logic;
+ signal av_chipselect : in std_logic;
+ signal av_read_n : in std_logic;
+ signal av_write_n : in std_logic;
+ signal av_writedata : in std_logic_vector(31 downto 0);
+ signal clk : in std_logic;
+ signal rst_n : in std_logic;
+
+ -- outputs:
+ signal av_irq : out std_logic;
+ signal av_readdata : out std_logic_vector(31 downto 0);
+ signal av_waitrequest : out std_logic;
+ signal dataavailable : out std_logic;
+ signal readyfordata : out std_logic
);
+ attribute ALTERA_ATTRIBUTE : string;
+ attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
+ end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
- ipen_AE <= ien_AE and fifo_AE;
- ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
- av_irq <= ipen_AE or ipen_AF;
- activity <= t_pause or t_ena;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- pause_irq <= std_logic'('0');
- elsif clk'event and clk = '1' then
- -- only if fifo is not empty...
- if std_logic'((t_pause and not fifo_EF)) = '1' then
- pause_irq <= std_logic'('1');
- elsif std_logic'(read_0) = '1' then
- pause_irq <= std_logic'('0');
- end if;
- end if;
- end process;
-
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- r_val <= std_logic'('0');
- t_dav <= std_logic'('1');
- elsif clk'event and clk = '1' then
- r_val <= r_ena and not wfifo_empty;
- t_dav <= not rfifo_full;
- end if;
- end process;
+architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_wdata : in std_logic_vector(7 downto 0);
+ signal fifo_wr : in std_logic;
+ signal rd_wfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_FF : out std_logic;
+ signal r_dat : out std_logic_vector(7 downto 0);
+ signal wfifo_empty : out std_logic;
+ signal wfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- fifo_AE <= std_logic'('0');
- fifo_AF <= std_logic'('0');
- fifo_wr <= std_logic'('0');
- rvalid <= std_logic'('0');
- read_0 <= std_logic'('0');
- ien_AE <= std_logic'('0');
- ien_AF <= std_logic'('0');
- ac <= std_logic'('0');
- woverflow <= std_logic'('0');
- internal_av_waitrequest <= std_logic'('1');
- elsif clk'event and clk = '1' then
- fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
- fifo_wr <= std_logic'('0');
- read_0 <= std_logic'('0');
- internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
- if std_logic'(activity) = '1' then
- ac <= std_logic'('1');
- end if;
- -- write
- if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is control; addr 0 is data
- if std_logic'(av_address) = '1' then
- ien_AF <= av_writedata(0);
- ien_AE <= av_writedata(1);
- if std_logic'((av_writedata(10) and not activity)) = '1' then
+ component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
+ port (
+ -- inputs:
+ signal clk : in std_logic;
+ signal fifo_clear : in std_logic;
+ signal fifo_rd : in std_logic;
+ signal rst_n : in std_logic;
+ signal t_dat : in std_logic_vector(7 downto 0);
+ signal wr_rfifo : in std_logic;
+
+ -- outputs:
+ signal fifo_EF : out std_logic;
+ signal fifo_rdata : out std_logic_vector(7 downto 0);
+ signal rfifo_full : out std_logic;
+ signal rfifo_used : out std_logic_vector(5 downto 0)
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
+
+ --synthesis read_comments_as_HDL on
+ -- component alt_jtag_atlantic is
+ --GENERIC (
+ -- INSTANCE_ID : NATURAL;
+ -- LOG2_RXFIFO_DEPTH : NATURAL;
+ -- LOG2_TXFIFO_DEPTH : NATURAL;
+ -- SLD_AUTO_INSTANCE_INDEX : STRING
+ -- );
+ -- PORT (
+ -- signal t_pause : OUT STD_LOGIC;
+ -- signal r_ena : OUT STD_LOGIC;
+ -- signal t_ena : OUT STD_LOGIC;
+ -- signal t_dat : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal t_dav : IN STD_LOGIC;
+ -- signal rst_n : IN STD_LOGIC;
+ -- signal r_dat : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ -- signal r_val : IN STD_LOGIC;
+ -- signal clk : IN STD_LOGIC
+ -- );
+ -- end component alt_jtag_atlantic;
+ --synthesis read_comments_as_HDL off
+ signal ac : std_logic;
+ signal activity : std_logic;
+ signal fifo_AE : std_logic;
+ signal fifo_AF : std_logic;
+ signal fifo_EF : std_logic;
+ signal fifo_FF : std_logic;
+ signal fifo_clear : std_logic;
+ signal fifo_rd : std_logic;
+ signal fifo_rdata : std_logic_vector(7 downto 0);
+ signal fifo_wdata : std_logic_vector(7 downto 0);
+ signal fifo_wr : std_logic;
+ signal ien_AE : std_logic;
+ signal ien_AF : std_logic;
+ signal internal_av_waitrequest : std_logic;
+ signal ipen_AE : std_logic;
+ signal ipen_AF : std_logic;
+ signal pause_irq : std_logic;
+ signal r_dat : std_logic_vector(7 downto 0);
+ signal r_ena : std_logic;
+ signal r_val : std_logic;
+ signal rd_wfifo : std_logic;
+ signal read_0 : std_logic;
+ signal rfifo_full : std_logic;
+ signal rfifo_used : std_logic_vector(5 downto 0);
+ signal rvalid : std_logic;
+ signal sim_r_ena : std_logic;
+ signal sim_t_dat : std_logic;
+ signal sim_t_ena : std_logic;
+ signal sim_t_pause : std_logic;
+ signal t_dat : std_logic_vector(7 downto 0);
+ signal t_dav : std_logic;
+ signal t_ena : std_logic;
+ signal t_pause : std_logic;
+ signal wfifo_empty : std_logic;
+ signal wfifo_used : std_logic_vector(5 downto 0);
+ signal woverflow : std_logic;
+ signal wr_rfifo : std_logic;
+ begin
+ --avalon_jtag_slave, which is an e_avalon_slave
+ rd_wfifo <= r_ena and not wfifo_empty;
+ wr_rfifo <= t_ena and not rfifo_full;
+ fifo_clear <= not rst_n;
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w
+ port map(
+ fifo_FF => fifo_FF,
+ r_dat => r_dat,
+ wfifo_empty => wfifo_empty,
+ wfifo_used => wfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_wdata => fifo_wdata,
+ fifo_wr => fifo_wr,
+ rd_wfifo => rd_wfifo
+ );
+
+ --the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
+ the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
+ port map(
+ fifo_EF => fifo_EF,
+ fifo_rdata => fifo_rdata,
+ rfifo_full => rfifo_full,
+ rfifo_used => rfifo_used,
+ clk => clk,
+ fifo_clear => fifo_clear,
+ fifo_rd => fifo_rd,
+ rst_n => rst_n,
+ t_dat => t_dat,
+ wr_rfifo => wr_rfifo
+ );
+
+ ipen_AE <= ien_AE and fifo_AE;
+ ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
+ av_irq <= ipen_AE or ipen_AF;
+ activity <= t_pause or t_ena;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ pause_irq <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ -- only if fifo is not empty...
+ if std_logic'((t_pause and not fifo_EF)) = '1' then
+ pause_irq <= std_logic'('1');
+ elsif std_logic'(read_0) = '1' then
+ pause_irq <= std_logic'('0');
+ end if;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ r_val <= std_logic'('0');
+ t_dav <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ r_val <= r_ena and not wfifo_empty;
+ t_dav <= not rfifo_full;
+ end if;
+ end process;
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ fifo_AE <= std_logic'('0');
+ fifo_AF <= std_logic'('0');
+ fifo_wr <= std_logic'('0');
+ rvalid <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ ien_AE <= std_logic'('0');
+ ien_AF <= std_logic'('0');
ac <= std_logic'('0');
+ woverflow <= std_logic'('0');
+ internal_av_waitrequest <= std_logic'('1');
+ elsif clk'event and clk = '1' then
+ fifo_AE <= to_std_logic(((std_logic_vector'("0000000000000000000000000") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_AF <= to_std_logic(((std_logic_vector'("000000000000000000000000") & (((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(rfifo_full) & rfifo_used))))))) <= std_logic_vector'("00000000000000000000000000001000")));
+ fifo_wr <= std_logic'('0');
+ read_0 <= std_logic'('0');
+ internal_av_waitrequest <= not (((av_chipselect and ((not av_write_n or not av_read_n))) and internal_av_waitrequest));
+ if std_logic'(activity) = '1' then
+ ac <= std_logic'('1');
+ end if;
+ -- write
+ if std_logic'(((av_chipselect and not av_write_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is control; addr 0 is data
+ if std_logic'(av_address) = '1' then
+ ien_AF <= av_writedata(0);
+ ien_AE <= av_writedata(1);
+ if std_logic'((av_writedata(10) and not activity)) = '1' then
+ ac <= std_logic'('0');
+ end if;
+ else
+ fifo_wr <= not fifo_FF;
+ woverflow <= fifo_FF;
+ end if;
+ end if;
+ -- read
+ if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
+ -- addr 1 is interrupt; addr 0 is data
+ if std_logic'(not av_address) = '1' then
+ rvalid <= not fifo_EF;
+ end if;
+ read_0 <= not av_address;
+ end if;
end if;
- else
- fifo_wr <= not fifo_FF;
- woverflow <= fifo_FF;
- end if;
- end if;
- -- read
- if std_logic'(((av_chipselect and not av_read_n) and internal_av_waitrequest)) = '1' then
- -- addr 1 is interrupt; addr 0 is data
- if std_logic'(not av_address) = '1' then
- rvalid <= not fifo_EF;
- end if;
- read_0 <= not av_address;
- end if;
- end if;
- end process;
-
- fifo_wdata <= av_writedata(7 downto 0);
- fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
- av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
- process (clk, rst_n)
- begin
- if rst_n = '0' then
- readyfordata <= std_logic'('0');
- elsif clk'event and clk = '1' then
- readyfordata <= not fifo_FF;
- end if;
- end process;
-
- --vhdl renameroo for output signals
- av_waitrequest <= internal_av_waitrequest;
---synthesis translate_off
- -- Tie off Atlantic Interface signals not used for simulation
- process (clk)
- begin
- if clk'event and clk = '1' then
- sim_t_pause <= std_logic'('0');
- sim_t_ena <= std_logic'('0');
- sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
- sim_r_ena <= std_logic'('0');
- end if;
- end process;
-
- r_ena <= sim_r_ena;
- t_ena <= sim_t_ena;
- t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
- t_pause <= sim_t_pause;
- process (fifo_EF)
- begin
- dataavailable <= not fifo_EF;
- end process;
-
---synthesis translate_on
---synthesis read_comments_as_HDL on
--- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
--- generic map(
--- INSTANCE_ID => 0,
--- LOG2_RXFIFO_DEPTH => 6,
--- LOG2_TXFIFO_DEPTH => 6,
--- SLD_AUTO_INSTANCE_INDEX => "YES"
--- )
--- port map(
--- clk => clk,
--- r_dat => r_dat,
--- r_ena => r_ena,
--- r_val => r_val,
--- rst_n => rst_n,
--- t_dat => t_dat,
--- t_dav => t_dav,
--- t_ena => t_ena,
--- t_pause => t_pause
--- );
---
--- process (clk, rst_n)
--- begin
--- if rst_n = '0' then
--- dataavailable <= std_logic'('0');
--- elsif clk'event and clk = '1' then
--- dataavailable <= NOT fifo_EF;
--- end if;
---
--- end process;
---
---synthesis read_comments_as_HDL off
-end europa;
+ end process;
+
+ fifo_wdata <= av_writedata(7 downto 0);
+ fifo_rd <= A_WE_StdLogic((std_logic'(((((av_chipselect and not av_read_n) and internal_av_waitrequest) and not av_address))) = '1'), not fifo_EF, std_logic'('0'));
+ av_readdata <= A_EXT (A_WE_StdLogicVector((std_logic'(read_0) = '1'), (std_logic_vector'("0") & ((A_REP(std_logic'('0'), 9) & A_ToStdLogicVector(rfifo_full) & rfifo_used & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & fifo_rdata))), (A_REP(std_logic'('0'), 9) & ((std_logic_vector'("01000000") - (std_logic_vector'("0") & (std_logic_vector'(A_ToStdLogicVector(fifo_FF) & wfifo_used))))) & A_ToStdLogicVector(rvalid) & A_ToStdLogicVector(woverflow) & A_ToStdLogicVector(not fifo_FF) & A_ToStdLogicVector(not fifo_EF) & A_ToStdLogicVector(std_logic'('0')) & A_ToStdLogicVector(ac) & A_ToStdLogicVector(ipen_AE) & A_ToStdLogicVector(ipen_AF) & A_REP(std_logic'('0'), 6) & A_ToStdLogicVector(ien_AE) & A_ToStdLogicVector(ien_AF))), 32);
+
+ process (clk, rst_n)
+ begin
+ if rst_n = '0' then
+ readyfordata <= std_logic'('0');
+ elsif clk'event and clk = '1' then
+ readyfordata <= not fifo_FF;
+ end if;
+ end process;
+
+ --vhdl renameroo for output signals
+ av_waitrequest <= internal_av_waitrequest;
+ --synthesis translate_off
+ -- Tie off Atlantic Interface signals not used for simulation
+ process (clk)
+ begin
+ if clk'event and clk = '1' then
+ sim_t_pause <= std_logic'('0');
+ sim_t_ena <= std_logic'('0');
+ sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
+ sim_r_ena <= std_logic'('0');
+ end if;
+ end process;
+
+ r_ena <= sim_r_ena;
+ t_ena <= sim_t_ena;
+ t_dat <= std_logic_vector'("0000000") & (A_TOSTDLOGICVECTOR(sim_t_dat));
+ t_pause <= sim_t_pause;
+
+ process (fifo_EF)
+ begin
+ dataavailable <= not fifo_EF;
+ end process;
+
+ --synthesis translate_on
+ --synthesis read_comments_as_HDL on
+ -- qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_alt_jtag_atlantic : alt_jtag_atlantic
+ -- generic map(
+ -- INSTANCE_ID => 0,
+ -- LOG2_RXFIFO_DEPTH => 6,
+ -- LOG2_TXFIFO_DEPTH => 6,
+ -- SLD_AUTO_INSTANCE_INDEX => "YES"
+ -- )
+ -- port map(
+ -- clk => clk,
+ -- r_dat => r_dat,
+ -- r_ena => r_ena,
+ -- r_val => r_val,
+ -- rst_n => rst_n,
+ -- t_dat => t_dat,
+ -- t_dav => t_dav,
+ -- t_ena => t_ena,
+ -- t_pause => t_pause
+ -- );
+ --
+ -- process (clk, rst_n)
+ -- begin
+ -- if rst_n = '0' then
+ -- dataavailable <= std_logic'('0');
+ -- elsif clk'event and clk = '1' then
+ -- dataavailable <= NOT fifo_EF;
+ -- end if;
+ --
+ -- end process;
+ --
+ --synthesis read_comments_as_HDL off
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..68a1b9756e73d17acaeb627e04c372716fd9e831 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index 64222401d7c70495e31aafcbeecd90272b38bdb4..fdabd7b57dbeb6788e005a2457084e5190c45c22 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -15,99 +15,99 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
- generic (
- INIT_FILE : string := "onchip_memory2_0.hex"
- );
- port (
- -- inputs:
- signal address : in std_logic_vector(14 downto 0);
- signal byteenable : in std_logic_vector(3 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal clken : in std_logic;
- signal freeze : in std_logic;
- signal reset : in std_logic;
- signal reset_req : in std_logic;
- signal write : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ generic (
+ INIT_FILE : string := "onchip_memory2_0.hex"
+ );
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(14 downto 0);
+ signal byteenable : in std_logic_vector(3 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal clken : in std_logic;
+ signal freeze : in std_logic;
+ signal reset : in std_logic;
+ signal reset_req : in std_logic;
+ signal write : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
+ -- outputs:
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
-generic (
+ generic (
byte_size : natural;
- init_file : string;
- lpm_type : string;
- maximum_depth : natural;
- numwords_a : natural;
- operation_mode : string;
- outdata_reg_a : string;
- ram_block_type : string;
- read_during_write_mode_mixed_ports : string;
- read_during_write_mode_port_a : string;
- width_a : natural;
- width_byteena_a : natural;
- widthad_a : natural
- );
+ init_file : string;
+ lpm_type : string;
+ maximum_depth : natural;
+ numwords_a : natural;
+ operation_mode : string;
+ outdata_reg_a : string;
+ ram_block_type : string;
+ read_during_write_mode_mixed_ports : string;
+ read_during_write_mode_port_a : string;
+ width_a : natural;
+ width_byteena_a : natural;
+ widthad_a : natural
+ );
port (
- signal q_a : out std_logic_vector(31 downto 0);
- signal wren_a : in std_logic;
- signal byteena_a : in std_logic_vector(3 downto 0);
- signal clock0 : in std_logic;
- signal address_a : in std_logic_vector(14 downto 0);
- signal clocken0 : in std_logic;
- signal data_a : in std_logic_vector(31 downto 0)
+ signal q_a : out std_logic_vector(31 downto 0);
+ signal wren_a : in std_logic;
+ signal byteena_a : in std_logic_vector(3 downto 0);
+ signal clock0 : in std_logic;
+ signal address_a : in std_logic_vector(14 downto 0);
+ signal clocken0 : in std_logic;
+ signal data_a : in std_logic_vector(31 downto 0)
+ );
+ end component altsyncram;
+ signal clocken0 : std_logic;
+ signal internal_readdata : std_logic_vector(31 downto 0);
+ signal wren : std_logic;
+ begin
+ wren <= chipselect and write;
+ clocken0 <= clken and not reset_req;
+ the_altsyncram : altsyncram
+ generic map(
+ byte_size => 8,
+ init_file => INIT_FILE,
+ lpm_type => "altsyncram",
+ maximum_depth => 32768,
+ numwords_a => 32768,
+ operation_mode => "SINGLE_PORT",
+ outdata_reg_a => "UNREGISTERED",
+ ram_block_type => "AUTO",
+ read_during_write_mode_mixed_ports => "DONT_CARE",
+ read_during_write_mode_port_a => "DONT_CARE",
+ width_a => 32,
+ width_byteena_a => 4,
+ widthad_a => 15
+ )
+ port map(
+ address_a => address,
+ byteena_a => byteenable,
+ clock0 => clk,
+ clocken0 => clocken0,
+ data_a => writedata,
+ q_a => internal_readdata,
+ wren_a => wren
);
- end component altsyncram;
- signal clocken0 : std_logic;
- signal internal_readdata : std_logic_vector(31 downto 0);
- signal wren : std_logic;
-begin
- wren <= chipselect and write;
- clocken0 <= clken and not reset_req;
- the_altsyncram : altsyncram
- generic map(
- byte_size => 8,
- init_file => INIT_FILE,
- lpm_type => "altsyncram",
- maximum_depth => 32768,
- numwords_a => 32768,
- operation_mode => "SINGLE_PORT",
- outdata_reg_a => "UNREGISTERED",
- ram_block_type => "AUTO",
- read_during_write_mode_mixed_ports => "DONT_CARE",
- read_during_write_mode_port_a => "DONT_CARE",
- width_a => 32,
- width_byteena_a => 4,
- widthad_a => 15
- )
- port map(
- address_a => address,
- byteena_a => byteenable,
- clock0 => clk,
- clocken0 => clocken0,
- data_a => writedata,
- q_a => internal_readdata,
- wren_a => wren
- );
- --s1, which is an e_avalon_slave
- --s2, which is an e_avalon_slave
- --vhdl renameroo for output signals
- readdata <= internal_readdata;
-end europa;
+ --s1, which is an e_avalon_slave
+ --s2, which is an e_avalon_slave
+ --vhdl renameroo for output signals
+ readdata <= internal_readdata;
+ end europa;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..500649d8da089ce1009f41be3852c17d19673c7c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..faef008bb80319ce0002573aeb8369f8eb5463d9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..031eaa0af9c383db5a3c0817ba95b7a06f3ebdbc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 0cc60e970e8bf720a6ebe320a18a2ffee267bccc..cc76a06817a980bdbb7f34baa9b4d542c92a3479 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -15,40 +15,41 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- port (
- -- inputs:
- signal address : in std_logic_vector(1 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(31 downto 0);
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(1 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(31 downto 0);
- -- outputs:
- signal out_port : out std_logic;
- signal readdata : out std_logic_vector(31 downto 0)
- );
-end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
+ -- outputs:
+ signal out_port : out std_logic;
+ signal readdata : out std_logic_vector(31 downto 0)
+ );
+ end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
- signal clk_en : std_logic;
- signal data_out : std_logic;
- signal read_mux_out : std_logic;
+ signal clk_en : std_logic;
+ signal data_out : std_logic;
+ signal read_mux_out : std_logic;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) and data_out;
+
process (clk, reset_n)
begin
if reset_n = '0' then
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..0b7dcff4021c0c79e50813f59fca9ff6ee280ed3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..b7feaef4257e3b0b83d070fda492f5065fe72014 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..c3c65aee84b4eaa16e64150da02a14a7aee6164f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..7cae834a564f49a180c0f391cc0f2836e73ead03 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..7a32df88c67781ad32090e018368f72797c9f94f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..cfde8e91765c2b090ec5fe88e8b06f0ecc2bf584 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..73c8f9c0cf46cbf6eb19994466f1a6724d26f8ec 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..c9c446304330b022496042600066e4aefb5f0679 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..e54b9651be45a9e4bc3fc42698883bc10c100db5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..c9fdcffd9c2ab6fb6e8c5393b45c3cfb270e378e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..c80cce2d60ffea663f6db2a5f032abfbcf59eac7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..f956b5a4e798c8bbe347cf55b3207aa9aaeadac6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..ed9ccedfa950200b6d72ecfeab8388b3ba5740f6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index a954c70405f58c881dbee5a2d7c5a50b9fdbe730..12915de2ba26e9c734878d2361eab8e6da7c9e8e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -15,53 +15,54 @@
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
library altera;
-use altera.altera_europa_support_lib.all;
+ use altera.altera_europa_support_lib.all;
library altera_mf;
-use altera_mf.altera_mf_components.all;
+ use altera_mf.altera_mf_components.all;
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- port (
- -- inputs:
- signal address : in std_logic_vector(2 downto 0);
- signal chipselect : in std_logic;
- signal clk : in std_logic;
- signal reset_n : in std_logic;
- signal write_n : in std_logic;
- signal writedata : in std_logic_vector(15 downto 0);
-
- -- outputs:
- signal irq : out std_logic;
- signal readdata : out std_logic_vector(15 downto 0)
- );
-end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
+ port (
+ -- inputs:
+ signal address : in std_logic_vector(2 downto 0);
+ signal chipselect : in std_logic;
+ signal clk : in std_logic;
+ signal reset_n : in std_logic;
+ signal write_n : in std_logic;
+ signal writedata : in std_logic_vector(15 downto 0);
+
+ -- outputs:
+ signal irq : out std_logic;
+ signal readdata : out std_logic_vector(15 downto 0)
+ );
+ end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
- signal clk_en : std_logic;
- signal control_interrupt_enable : std_logic;
- signal control_register : std_logic;
- signal control_wr_strobe : std_logic;
- signal counter_is_running : std_logic;
- signal counter_is_zero : std_logic;
- signal counter_load_value : std_logic_vector(16 downto 0);
- signal delayed_unxcounter_is_zeroxx0 : std_logic;
- signal do_start_counter : std_logic;
- signal do_stop_counter : std_logic;
- signal force_reload : std_logic;
- signal internal_counter : std_logic_vector(16 downto 0);
- signal period_h_wr_strobe : std_logic;
- signal period_l_wr_strobe : std_logic;
- signal read_mux_out : std_logic_vector(15 downto 0);
- signal status_wr_strobe : std_logic;
- signal timeout_event : std_logic;
- signal timeout_occurred : std_logic;
+ signal clk_en : std_logic;
+ signal control_interrupt_enable : std_logic;
+ signal control_register : std_logic;
+ signal control_wr_strobe : std_logic;
+ signal counter_is_running : std_logic;
+ signal counter_is_zero : std_logic;
+ signal counter_load_value : std_logic_vector(16 downto 0);
+ signal delayed_unxcounter_is_zeroxx0 : std_logic;
+ signal do_start_counter : std_logic;
+ signal do_stop_counter : std_logic;
+ signal force_reload : std_logic;
+ signal internal_counter : std_logic_vector(16 downto 0);
+ signal period_h_wr_strobe : std_logic;
+ signal period_l_wr_strobe : std_logic;
+ signal read_mux_out : std_logic_vector(15 downto 0);
+ signal status_wr_strobe : std_logic;
+ signal timeout_event : std_logic;
+ signal timeout_occurred : std_logic;
begin
clk_en <= std_logic'('1');
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -79,6 +80,7 @@ begin
counter_is_zero <= to_std_logic(((std_logic_vector'("000000000000000") & (internal_counter)) = std_logic_vector'("00000000000000000000000000000000")));
counter_load_value <= std_logic_vector'("11000011010011111");
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -92,6 +94,7 @@ begin
do_start_counter <= std_logic'('1');
do_stop_counter <= std_logic'('0');
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -120,6 +123,7 @@ begin
end process;
timeout_event <= (counter_is_zero) and not (delayed_unxcounter_is_zeroxx0);
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -138,6 +142,7 @@ begin
irq <= timeout_occurred and control_interrupt_enable;
--s1, which is an e_avalon_slave
read_mux_out <= ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001")))), 16) and (std_logic_vector'("000000000000000") & (A_TOSTDLOGICVECTOR(control_register))))) or ((A_REP(to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 16) and (std_logic_vector'("00000000000000") & (std_logic_vector'(A_ToStdLogicVector(counter_is_running) & A_ToStdLogicVector(timeout_occurred))))));
+
process (clk, reset_n)
begin
if reset_n = '0' then
@@ -152,6 +157,7 @@ begin
period_l_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010"))));
period_h_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000011"))));
control_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000001"))));
+
process (clk, reset_n)
begin
if reset_n = '0' then
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..e6864d98a9aad5782a0d0118e9ca0caf75d10111 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 514ae4a7481860c8aec306184d0d937322216be4..9f9849ac84bbe092e8cd096bb7de5092ede381c7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, unb2b_jesd_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd_node3 is
generic (
@@ -45,7 +45,7 @@ entity unb2b_jesd_node3 is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -82,49 +82,49 @@ end unb2b_jesd_node3;
architecture str of unb2b_jesd_node3 is
begin
u_revision : entity unb2b_jesd_lib.unb2b_jesd
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- -- 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED,
+ QSFP_LED => QSFP_LED,
- -- JESD signals
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_sysref => jesd204_rx_sysref,
- jesd204_device_clk => jesd204_device_clk
- );
+ -- JESD signals
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_sysref => jesd204_rx_sysref,
+ jesd204_device_clk => jesd204_device_clk
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 91849daf0fb485fa8e569cd2d38af59bb2829758..c54e99c950ba83400eeffe420f71f430cb852991 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_jesd_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_jesd_pkg.all;
entity mmm_unb2b_jesd is
generic (
@@ -134,33 +134,43 @@ begin
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -333,56 +343,56 @@ begin
reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
- -- connections to the JESD IP:
-
- --altjesd_reset_seq_irq_irq =>
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
- --altjesd_reset_seq_pll_reset_reset =>
- altjesd_reset_seq_reset_in0_reset => mm_rst,
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
- --altjesd_rx_csr_cf_export =>
- --altjesd_rx_csr_cs_export =>
- --altjesd_rx_csr_f_export =>
- --altjesd_rx_csr_hd_export =>
- --altjesd_rx_csr_k_export =>
- --altjesd_rx_csr_l_export =>
- altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
- --altjesd_rx_csr_m_export =>
- --altjesd_rx_csr_n_export =>
- --altjesd_rx_csr_np_export =>
- --altjesd_rx_csr_rx_testmode_export =>
- --altjesd_rx_csr_s_export =>
- altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
- altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
- altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
- altjesd_rx_jesd204_rx_frame_error_export => '0',
- altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
- altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
- altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
- altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
- altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
- altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
- altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
- --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
- --altjesd_rx_rxphy_clk_export =>
- --altjesd_rx_sof_export =>
- --altjesd_rx_somf_export =>
- altjesd_rx_sysref_export => jesd204_rx_sysref,
- --altjesd_ss_rx_corepll_locked_export =>
- --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
- device_clk_clk => jesd204_device_clk,
- device_clk_reset_reset_n => '1',
- frame_clk_clk => frame_clk,
- pll_out_frame_clk_clk => frame_clk,
- frame_clk_reset_reset_n => '1',
- link_clk_clk => link_clk,
- pll_out_link_clk_clk => link_clk,
- link_clk_reset_reset_n => '1'
- );
+ -- connections to the JESD IP:
+
+ --altjesd_reset_seq_irq_irq =>
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual => i_reset_n,
+ --altjesd_reset_seq_pll_reset_reset =>
+ altjesd_reset_seq_reset_in0_reset => mm_rst,
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual => '1',
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual => rx_xcvr_ready_in,
+ --altjesd_rx_csr_cf_export =>
+ --altjesd_rx_csr_cs_export =>
+ --altjesd_rx_csr_f_export =>
+ --altjesd_rx_csr_hd_export =>
+ --altjesd_rx_csr_k_export =>
+ --altjesd_rx_csr_l_export =>
+ altjesd_rx_csr_lane_powerdown_export => rx_csr_lane_powerdown,
+ --altjesd_rx_csr_m_export =>
+ --altjesd_rx_csr_n_export =>
+ --altjesd_rx_csr_np_export =>
+ --altjesd_rx_csr_rx_testmode_export =>
+ --altjesd_rx_csr_s_export =>
+ altjesd_rx_dev_sync_n_export => jesd204_sync_n_out,
+ altjesd_rx_jesd204_rx_dlb_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_data_valid_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_disperr_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_errdetect_export => (others => '0'),
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export => (others => '0'),
+ altjesd_rx_jesd204_rx_frame_error_export => '0',
+ altjesd_rx_jesd204_rx_int_irq => jesd204_rx_link_error,
+ altjesd_rx_jesd204_rx_link_data => jesd204_rx_link_data,
+ altjesd_rx_jesd204_rx_link_valid => jesd204_rx_link_valid,
+ altjesd_rx_jesd204_rx_link_ready => jesd204_rx_link_ready,
+ altjesd_rx_rx_serial_data_rx_serial_data(0) => jesd204_rx_serial_data,
+ altjesd_rx_rxlink_rst_n_reset_n => rx_link_rst_n,
+ altjesd_ss_rx_link_reset_out_reset_reset_n => rx_link_rst_n,
+ --altjesd_ss_rx_frame_reset_out_reset_reset_n =>
+ --altjesd_rx_rxphy_clk_export =>
+ --altjesd_rx_sof_export =>
+ --altjesd_rx_somf_export =>
+ altjesd_rx_sysref_export => jesd204_rx_sysref,
+ --altjesd_ss_rx_corepll_locked_export =>
+ --altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown =>
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready => xcvr_rst_ctrl_rx_ready,
+ device_clk_clk => jesd204_device_clk,
+ device_clk_reset_reset_n => '1',
+ frame_clk_clk => frame_clk,
+ pll_out_frame_clk_clk => frame_clk,
+ frame_clk_reset_reset_n => '1',
+ link_clk_clk => link_clk,
+ pll_out_link_clk_clk => link_clk,
+ link_clk_reset_reset_n => '1'
+ );
end generate;
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
index fd4dfd48d297596d0790d66898ca7b23f920e06f..9ccb6e04ab5722204ee4e34d38842e11282c9a36 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
@@ -20,198 +20,197 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_jesd_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
-
-component qsys_unb2b_jesd is
- port (
- altjesd_reset_seq_irq_irq : out std_logic; -- irq
- altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
- altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
- altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
- altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_hd_export : out std_logic; -- export
- altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
- altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
- altjesd_rx_dev_sync_n_export : out std_logic; -- export
- altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
- altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
- altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
- altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
- altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
- altjesd_rx_sysref_export : in std_logic := 'X'; -- export
- altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
- altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
- altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
- altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- device_clk_clk : in std_logic := 'X'; -- clk
- device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- frame_clk_clk : in std_logic := 'X'; -- clk
- frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- link_clk_clk : in std_logic := 'X'; -- clk
- link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- pll_out_frame_clk_clk : out std_logic; -- clk
- pll_out_link_clk_clk : out std_logic; -- clk
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_jesd;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2b_jesd is
+ port (
+ altjesd_reset_seq_irq_irq : out std_logic; -- irq
+ altjesd_reset_seq_pll_locked_in_reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ altjesd_reset_seq_pll_reset_reset : out std_logic; -- reset
+ altjesd_reset_seq_reset_in0_reset : in std_logic := 'X'; -- reset
+ altjesd_reset_seq_rx_xcvr_ready_in_reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ altjesd_reset_seq_tx_xcvr_ready_in_reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ altjesd_rx_csr_cf_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_cs_export : out std_logic_vector(1 downto 0); -- export
+ altjesd_rx_csr_f_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_hd_export : out std_logic; -- export
+ altjesd_rx_csr_k_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_l_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_lane_powerdown_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_csr_m_export : out std_logic_vector(7 downto 0); -- export
+ altjesd_rx_csr_n_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_np_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_csr_rx_testmode_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_csr_s_export : out std_logic_vector(4 downto 0); -- export
+ altjesd_rx_dev_sync_n_export : out std_logic; -- export
+ altjesd_rx_jesd204_rx_dlb_data_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_data_valid_export : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_disperr_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_errdetect_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_dlb_kchar_data_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ altjesd_rx_jesd204_rx_frame_error_export : in std_logic := 'X'; -- export
+ altjesd_rx_jesd204_rx_int_irq : out std_logic; -- irq
+ altjesd_rx_jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ altjesd_rx_jesd204_rx_link_valid : out std_logic; -- valid
+ altjesd_rx_jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ altjesd_rx_rx_serial_data_rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ altjesd_rx_rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ altjesd_rx_rxphy_clk_export : out std_logic_vector(0 downto 0); -- export
+ altjesd_rx_sof_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_somf_export : out std_logic_vector(3 downto 0); -- export
+ altjesd_rx_sysref_export : in std_logic := 'X'; -- export
+ altjesd_ss_rx_corepll_locked_export : out std_logic; -- export
+ altjesd_ss_rx_xcvr_reset_control_pll_powerdown_pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ altjesd_ss_rx_xcvr_reset_control_rx_ready_rx_ready : out std_logic_vector(0 downto 0); -- rx_ready
+ altjesd_ss_rx_frame_reset_out_reset_reset_n : out std_logic; -- reset_n
+ altjesd_ss_rx_link_reset_out_reset_reset_n : out std_logic; -- reset_n
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ device_clk_clk : in std_logic := 'X'; -- clk
+ device_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ frame_clk_clk : in std_logic := 'X'; -- clk
+ frame_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ link_clk_clk : in std_logic := 'X'; -- clk
+ link_clk_reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ pll_out_frame_clk_clk : out std_logic; -- clk
+ pll_out_link_clk_clk : out std_logic; -- clk
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buf_jesd_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_read_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_write_export : out std_logic; -- export
+ ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buf_jesd_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_read_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_write_export : out std_logic; -- export
+ reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_jesd;
end qsys_unb2b_jesd_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index 91de0e9f2772a37c0081c401f556e230fda90183..7f33484855bfb69cb08666849f8aa3730d154322 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -21,14 +21,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity unb2b_jesd is
generic (
@@ -46,7 +46,7 @@ entity unb2b_jesd is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- System Clock
+ -- CLK : IN STD_LOGIC; -- System Clock
PPS : in std_logic; -- System Sync
WDI : out std_logic; -- Watchdog Clear
INTA : inout std_logic; -- FPGA interconnect line
@@ -183,212 +183,212 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_use_pll => false
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => st_pps,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => st_pps,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_jesd
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- --
- ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
- ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
- reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
- reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
-
- jesd204_rx_serial_data => jesd204_rx_serial_data,
- jesd204_sync_n_out => jesd204_sync_n_out,
- jesd204_rx_link_error => jesd204_rx_link_error,
- jesd204_rx_link_data => jesd204_rx_link_data,
- jesd204_rx_link_valid => jesd204_rx_link_valid,
- jesd204_rx_link_ready => jesd204_rx_link_ready,
- jesd204_rx_sysref => jesd204_rx_sysref_n,
- jesd204_device_clk => st_clk
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ --
+ ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+ reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+
+ jesd204_rx_serial_data => jesd204_rx_serial_data,
+ jesd204_sync_n_out => jesd204_sync_n_out,
+ jesd204_rx_link_error => jesd204_rx_link_error,
+ jesd204_rx_link_data => jesd204_rx_link_data,
+ jesd204_rx_link_valid => jesd204_rx_link_valid,
+ jesd204_rx_link_ready => jesd204_rx_link_ready,
+ jesd204_rx_sysref => jesd204_rx_sysref_n,
+ jesd204_device_clk => st_clk
+ );
CLK <= jesd204_device_clk;
--PPS <= jesd204_rx_sysref;
@@ -403,26 +403,26 @@ begin
end generate;
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_data_w => 32,
- g_buf_nof_data => 16384, -- 8192,
- g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- g_use_rx_seq => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => mm_rst,
- dp_clk => st_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
- ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
- reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
- reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
- in_sosi_arr => diag_data_buf_snk_in_arr,
- in_sync => st_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_data_w => 32,
+ g_buf_nof_data => 16384, -- 8192,
+ g_buf_use_sync => true, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ g_use_rx_seq => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => mm_rst,
+ dp_clk => st_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+ in_sosi_arr => diag_data_buf_snk_in_arr,
+ in_sync => st_pps
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index ec0e76432a205b9af472413490552af89cc5ef35..dfc6a8483c32923f156fae644ad06327360688fe 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2b_pkg.all;
-use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2b_pkg.all;
+ use i2c_lib.i2c_commander_unb2b_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index a915740dc56c968cea7358d18a0c7d354f1f3e2a..c674e9c74eaeb2f4c732631ccc724e1a3e78eee8 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_minimal_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_minimal_125m is
generic (
@@ -74,46 +74,46 @@ end unb2b_minimal_125m;
architecture str of unb2b_minimal_125m is
begin
u_revision : entity unb2b_minimal_lib.unb2b_minimal
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_technology => g_technology,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 94c4b4e44734dbcd37a02a86632e8a6eeedde24e..2b4b8c500a1b08a171cf97f2b2ff6cec57eba6c0 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2b_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2b_minimal_pkg.all;
entity mmm_unb2b_minimal is
generic (
@@ -114,36 +114,47 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -306,7 +317,6 @@ begin
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
ram_scrap_read_export => ram_scrap_mosi.rd,
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index 1470cca51163e20c03fea684792e0fc3269da00f..e7643965bfc25a106ec90f6a7d8052b71d63083a 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -20,143 +20,142 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_minimal_pkg is
- -----------------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus v14 QSYS builder
- -----------------------------------------------------------------------------
-
- component qsys_unb2b_minimal is
- port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_reset_export : out std_logic -- export
- );
- end component qsys_unb2b_minimal;
+ -----------------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus v14 QSYS builder
+ -----------------------------------------------------------------------------
+ component qsys_unb2b_minimal is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export: out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_reset_export : out std_logic -- export
+ );
+ end component qsys_unb2b_minimal;
end qsys_unb2b_minimal_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index af68ce0e0a9d34558339dd888f16ea75c5e61838..f9e1e1481f6bec223e4290302d43b7a8085998b4 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
entity unb2b_minimal is
generic (
@@ -163,226 +163,226 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 08f2d036be105e43527af6fdc08992fc0229a514..6b169ce467cdbd39cc8d26e99d6e6db0bbfa0915 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -43,20 +43,20 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2b_minimal is
- generic (
- g_design_name : string := "unb2b_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2b_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
@@ -185,51 +185,51 @@ begin
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
u_pmbus_tcvr0 : entity i2c_lib.dev_pmbus
- generic map (
- g_address => c_pmbus_tcvr0_address
- )
- port map (
- scl => PMBUS_SC,
- sda => PMBUS_SD,
- vout_mode => 13,
- vin => 92,
- vout => 18,
- iout => 12,
- vcap => 0,
- temp => 36
- );
+ generic map (
+ g_address => c_pmbus_tcvr0_address
+ )
+ port map (
+ scl => PMBUS_SC,
+ sda => PMBUS_SD,
+ vout_mode => 13,
+ vin => 92,
+ vout => 18,
+ iout => 12,
+ vcap => 0,
+ temp => 36
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
index cf02b0fabcf9a9f8f98d2a9352b47b30dfa5dd3d..0028319fece01290365874c15e722df12d98929f 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_10GbE is
end tb_unb2b_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2b_test_10GbE;
architecture tb of tb_unb2b_test_10GbE is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2b_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index b8d21e890e0a16f9cabfc918278fcac6875bfa86..bc018685b5a398a0ca9b79f12b7ddc79cb48189a 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_test_10GbE is
generic (
@@ -66,20 +66,20 @@ entity unb2b_test_10GbE is
BCK_REF_CLK : in std_logic; -- Clock 10GbE back lower 24 lines
-- back transceivers
--- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
--- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
--- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_TX : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_back.bus_w * c_unb2b_board_tr_back.nof_bus)-1 downto 0);
+ -- BCK_RX : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS=>'0');
+ -- BCK_TX : OUT STD_LOGIC_VECTOR(4-1 downto 0);
BCK_SDA : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_SCL : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
BCK_ERR : inout std_logic_vector(c_unb2b_board_tr_back.i2c_w - 1 downto 0);
-- ring transceivers
- -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
- -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
+ -- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 downto 0);
-- pmbus
PMBUS_SC : inout std_logic;
PMBUS_SD : inout std_logic;
@@ -109,78 +109,78 @@ end unb2b_test_10GbE;
architecture str of unb2b_test_10GbE is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- -- BCK_RX => BCK_RX,
- -- BCK_TX => BCK_TX,
-
- BCK_SDA => BCK_SDA,
- BCK_SCL => BCK_SCL,
- BCK_ERR => BCK_ERR,
-
- -- ring transceivers
- -- RING_0_RX => RING_0_RX,
- -- RING_0_TX => RING_0_TX,
- -- RING_1_RX => RING_1_RX,
- -- RING_1_TX => RING_1_TX,
- -- pmbus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_SDA => QSFP_SDA,
- QSFP_SCL => QSFP_SCL,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ -- BCK_RX => BCK_RX,
+ -- BCK_TX => BCK_TX,
+
+ BCK_SDA => BCK_SDA,
+ BCK_SCL => BCK_SCL,
+ BCK_ERR => BCK_ERR,
+
+ -- ring transceivers
+ -- RING_0_RX => RING_0_RX,
+ -- RING_0_TX => RING_0_TX,
+ -- RING_1_RX => RING_1_RX,
+ -- RING_1_TX => RING_1_TX,
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_SDA => QSFP_SDA,
+ QSFP_SCL => QSFP_SCL,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
index a5b99242985e239c70f5ac80f75cfea8c4e61616..e89be398264da2cd87166c34b0a63580b94134f7 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2b_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2b_test_ddr_MB_I_II is
end tb_unb2b_test_ddr_MB_I_II;
@@ -29,8 +29,8 @@ end tb_unb2b_test_ddr_MB_I_II;
architecture tb of tb_unb2b_test_ddr_MB_I_II is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
- generic map (
- g_design_name => "unb2b_test_ddr_MB_I_II",
- g_sim_model_ddr => false
- );
+ generic map (
+ g_design_name => "unb2b_test_ddr_MB_I_II",
+ g_sim_model_ddr => false
+ );
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index 150e0d63045d3adf645914ff4000210671f53740..d0255f5d2ed8c05d3abaceef177238bdbd78af70 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2b_test_ddr_MB_I_II is
generic (
@@ -86,56 +86,56 @@ end unb2b_test_ddr_MB_I_II;
architecture str of unb2b_test_ddr_MB_I_II is
begin
u_revision : entity unb2b_test_lib.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
-
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index ab0300e724b7bb8f55b4b891a838ca736862dc05..9abfc168f24dfaefb061060ff29735fbad7cece2 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2b_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use unb2b_board_lib.unb2b_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2b_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2b_test_pkg.all;
entity mmm_unb2b_test is
generic (
@@ -235,16 +235,16 @@ architecture str of mmm_unb2b_test is
constant c_ram_diag_databuffer_ddr_addr_w : natural := ceil_log2(2 * pow2(ceil_log2(g_bg_block_size)));
-- dp_offload
--- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
--- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
---
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
---
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
--- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
+ -- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1; -- Dev note: add to c_unb2b_board_peripherals_mm_reg_default
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_tx_1GbE_hdr_dat_adr_w));
+ --
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words : NATURAL := field_nof_words(c_hdr_field_arr, c_word_w);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_rx_1GbE_hdr_dat_nof_words);
+ -- CONSTANT c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w : NATURAL := ceil_log2(g_nof_streams_1GbE * pow2(c_reg_dp_offload_rx_1GbE_hdr_dat_adr_w));
-- tr_10GbE
constant c_reg_tr_10GbE_adr_w : natural := func_tech_mac_10g_csr_addr_w(g_technology);
@@ -264,7 +264,7 @@ architecture str of mmm_unb2b_test is
-- Simulation
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -285,113 +285,175 @@ begin
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+
+ u_mm_file_reg_unb_pmbus : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
+
+ u_mm_file_ram_diag_bg_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_diag_tx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_unb_pmbus : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- port map(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ -- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
+ --
+ -- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
+ --
+ -- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
+ -- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_bsn_monitor_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
- u_mm_file_reg_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
- u_mm_file_reg_diag_tx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_1GbE_mosi, reg_diag_tx_seq_1GbE_miso);
+ u_mm_file_reg_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+ u_mm_file_ram_diag_data_buffer_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
--- u_mm_file_reg_dp_offload_tx_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_mosi, reg_dp_offload_tx_1GbE_miso);
---
--- u_mm_file_reg_dp_offload_tx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_1GbE_hdr_dat_mosi, reg_dp_offload_tx_1GbE_hdr_dat_miso);
---
--- u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
--- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
-
- u_mm_file_reg_bsn_monitor_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_1GbE_mosi, reg_diag_data_buf_1GbE_miso);
- u_mm_file_ram_diag_data_buffer_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
- u_mm_file_reg_diag_rx_seq_1GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_diag_rx_seq_1GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_1GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_1GbE_mosi, reg_diag_rx_seq_1GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
- u_mm_file_reg_eth1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
- port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
- u_mm_file_reg_tr_10GbE_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
- u_mm_file_reg_eth10g_back1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
- port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
+ u_mm_file_reg_eth0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+
+ u_mm_file_reg_eth1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
+ port map(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+
+ u_mm_file_reg_tr_10GbE_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK1")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back1_mosi, reg_tr_10GbE_back1_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+
+ u_mm_file_reg_eth10g_back1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK1")
+ port map(mm_rst, mm_clk, reg_eth10g_back1_mosi, reg_eth10g_back1_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -416,10 +478,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
- else
- eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
- end if;
+ eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
+ else
+ eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -647,32 +709,32 @@ begin
reg_eth10g_back1_read_export => reg_eth10g_back1_mosi.rd,
reg_eth10g_back1_readdata_export => reg_eth10g_back1_miso.rddata(c_word_w - 1 downto 0),
--- -- the_reg_dp_offload_tx_1GbE
--- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
--- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
--- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_tx_1GbE_hdr_dat
--- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
---
--- -- the_reg_dp_offload_rx_1GbE_hdr_dat
--- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
--- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
--- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
--- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
--- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- -- the_reg_dp_offload_tx_1GbE
+ -- reg_dp_offload_tx_1GbE_address_export => reg_dp_offload_tx_1GbE_mosi.address(c_reg_dp_offload_tx_1GbE_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_read_export => reg_dp_offload_tx_1GbE_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_readdata_export => reg_dp_offload_tx_1GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_write_export => reg_dp_offload_tx_1GbE_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_writedata_export => reg_dp_offload_tx_1GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_tx_1GbE_hdr_dat
+ -- reg_dp_offload_tx_1GbE_hdr_dat_address_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_tx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_read_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_readdata_export => reg_dp_offload_tx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_tx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_write_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_writedata_export => reg_dp_offload_tx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ --
+ -- -- the_reg_dp_offload_rx_1GbE_hdr_dat
+ -- reg_dp_offload_rx_1GbE_hdr_dat_address_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.address(c_reg_dp_offload_rx_1GbE_hdr_dat_multi_adr_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_clk_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_read_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.rd,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_readdata_export => reg_dp_offload_rx_1GbE_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ -- reg_dp_offload_rx_1GbE_hdr_dat_reset_export => OPEN,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
@@ -770,21 +832,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
@@ -835,5 +897,4 @@ begin
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index 02021567e290a50a5b46eff215147816e76578ef..8c8bfc4e7061b079742f9a92a1ca3c882e50e44e 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2b_test_pkg is
-----------------------------------------------------------------------------
@@ -28,361 +28,360 @@ package qsys_unb2b_test_pkg is
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
- component qsys_unb2b_test is
- port (
- avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
- avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
- avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
- avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
- avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
- avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
- avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
- avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
- avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
- avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
- avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
- avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
- avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
- avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
- avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
- avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
- avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
- avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
- avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
- avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
- clk_clk : in std_logic := '0'; -- clk.clk
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
- pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
- pio_pps_read_export : out std_logic; -- pio_pps_read.export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
- pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
- pio_pps_write_export : out std_logic; -- pio_pps_write.export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
- pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
- pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
- pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
- pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
- pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
- ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
- ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
- ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
- ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
- ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
- ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
- ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
- ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
- ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
- ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
- ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
- ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
- ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
- ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
- ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
- reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
- reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
- reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
- reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
- reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
- reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
- reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
- reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
- reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
- reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
- reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
- reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
- reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
- reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
- reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
- reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
- reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
- reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
- reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
- reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
- reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
- reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
- reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
- reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
- reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
- reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
- reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
- reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
- reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
- reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
- reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
- reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
- reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
- reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
- reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
- reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
- reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
- reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
- reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
- reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
- reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
- reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
- reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
- reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
- reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
- reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
- reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
- reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
- reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
- reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
- reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
- reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
- reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
- reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
- reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
- reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
- reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
- reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
- reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
- reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
- reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
- reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
- reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
- reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
- reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
- reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
- reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
- reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
- reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
- reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
- reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
- reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
- reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
- reg_remu_read_export : out std_logic; -- reg_remu_read.export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
- reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
- reg_remu_write_export : out std_logic; -- reg_remu_write.export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
- reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
- reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
- reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
- reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
- reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
- reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
- reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
- reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
- reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
- reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
- reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
- reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
- reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
- reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
- reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
- reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
- reset_reset_n : in std_logic := '0'; -- reset.reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
- rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
- rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
- rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
- rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
- );
- end component qsys_unb2b_test;
-
+ component qsys_unb2b_test is
+ port (
+ avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
+ avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
+ avs_eth_0_ram_read_export : out std_logic; -- avs_eth_0_ram_read.export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_ram_readdata.export
+ avs_eth_0_ram_write_export : out std_logic; -- avs_eth_0_ram_write.export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_ram_writedata.export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_0_reg_address.export
+ avs_eth_0_reg_read_export : out std_logic; -- avs_eth_0_reg_read.export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_reg_readdata.export
+ avs_eth_0_reg_write_export : out std_logic; -- avs_eth_0_reg_write.export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_reg_writedata.export
+ avs_eth_0_reset_export : out std_logic; -- avs_eth_0_reset.export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_tse_address.export
+ avs_eth_0_tse_read_export : out std_logic; -- avs_eth_0_tse_read.export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_0_tse_readdata.export
+ avs_eth_0_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_0_tse_waitrequest.export
+ avs_eth_0_tse_write_export : out std_logic; -- avs_eth_0_tse_write.export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_0_tse_writedata.export
+ avs_eth_1_clk_export : out std_logic; -- avs_eth_1_clk.export
+ avs_eth_1_irq_export : in std_logic := '0'; -- avs_eth_1_irq.export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_ram_address.export
+ avs_eth_1_ram_read_export : out std_logic; -- avs_eth_1_ram_read.export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_ram_readdata.export
+ avs_eth_1_ram_write_export : out std_logic; -- avs_eth_1_ram_write.export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_ram_writedata.export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- avs_eth_1_reg_address.export
+ avs_eth_1_reg_read_export : out std_logic; -- avs_eth_1_reg_read.export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_reg_readdata.export
+ avs_eth_1_reg_write_export : out std_logic; -- avs_eth_1_reg_write.export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_reg_writedata.export
+ avs_eth_1_reset_export : out std_logic; -- avs_eth_1_reset.export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- avs_eth_1_tse_address.export
+ avs_eth_1_tse_read_export : out std_logic; -- avs_eth_1_tse_read.export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- avs_eth_1_tse_readdata.export
+ avs_eth_1_tse_waitrequest_export : in std_logic := '0'; -- avs_eth_1_tse_waitrequest.export
+ avs_eth_1_tse_write_export : out std_logic; -- avs_eth_1_tse_write.export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- avs_eth_1_tse_writedata.export
+ clk_clk : in std_logic := '0'; -- clk.clk
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- pio_pps_address.export
+ pio_pps_clk_export : out std_logic; -- pio_pps_clk.export
+ pio_pps_read_export : out std_logic; -- pio_pps_read.export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_pps_readdata.export
+ pio_pps_reset_export : out std_logic; -- pio_pps_reset.export
+ pio_pps_write_export : out std_logic; -- pio_pps_write.export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- pio_pps_writedata.export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- pio_system_info_address.export
+ pio_system_info_clk_export : out std_logic; -- pio_system_info_clk.export
+ pio_system_info_read_export : out std_logic; -- pio_system_info_read.export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- pio_system_info_readdata.export
+ pio_system_info_reset_export : out std_logic; -- pio_system_info_reset.export
+ pio_system_info_write_export : out std_logic; -- pio_system_info_write.export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- pio_system_info_writedata.export
+ pio_wdi_external_connection_export : out std_logic; -- pio_wdi_external_connection.export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_bg_10gbe_address.export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- ram_diag_bg_10gbe_clk.export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- ram_diag_bg_10gbe_read.export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_10gbe_readdata.export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- ram_diag_bg_10gbe_reset.export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- ram_diag_bg_10gbe_write.export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_10gbe_writedata.export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_bg_1gbe_address.export
+ ram_diag_bg_1gbe_clk_export : out std_logic; -- ram_diag_bg_1gbe_clk.export
+ ram_diag_bg_1gbe_read_export : out std_logic; -- ram_diag_bg_1gbe_read.export
+ ram_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_bg_1gbe_readdata.export
+ ram_diag_bg_1gbe_reset_export : out std_logic; -- ram_diag_bg_1gbe_reset.export
+ ram_diag_bg_1gbe_write_export : out std_logic; -- ram_diag_bg_1gbe_write.export
+ ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_bg_1gbe_writedata.export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- ram_diag_data_buffer_10gbe_address.export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- ram_diag_data_buffer_10gbe_clk.export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- ram_diag_data_buffer_10gbe_read.export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_10gbe_readdata.export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- ram_diag_data_buffer_10gbe_reset.export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- ram_diag_data_buffer_10gbe_write.export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_10gbe_writedata.export
+ ram_diag_data_buffer_1gbe_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_1gbe_address.export
+ ram_diag_data_buffer_1gbe_clk_export : out std_logic; -- ram_diag_data_buffer_1gbe_clk.export
+ ram_diag_data_buffer_1gbe_read_export : out std_logic; -- ram_diag_data_buffer_1gbe_read.export
+ ram_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_1gbe_readdata.export
+ ram_diag_data_buffer_1gbe_reset_export : out std_logic; -- ram_diag_data_buffer_1gbe_reset.export
+ ram_diag_data_buffer_1gbe_write_export : out std_logic; -- ram_diag_data_buffer_1gbe_write.export
+ ram_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_1gbe_writedata.export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_i_address.export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_clk.export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_read.export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_i_readdata.export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_reset.export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_i_write.export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_i_writedata.export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_address.export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_clk.export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_read.export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- ram_diag_data_buffer_ddr_mb_ii_readdata.export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_reset.export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- ram_diag_data_buffer_ddr_mb_ii_write.export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- ram_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- reg_bsn_monitor_10gbe_address.export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- reg_bsn_monitor_10gbe_clk.export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- reg_bsn_monitor_10gbe_read.export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_10gbe_readdata.export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- reg_bsn_monitor_10gbe_reset.export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- reg_bsn_monitor_10gbe_write.export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_10gbe_writedata.export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_bsn_monitor_1gbe_address.export
+ reg_bsn_monitor_1gbe_clk_export : out std_logic; -- reg_bsn_monitor_1gbe_clk.export
+ reg_bsn_monitor_1gbe_read_export : out std_logic; -- reg_bsn_monitor_1gbe_read.export
+ reg_bsn_monitor_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_bsn_monitor_1gbe_readdata.export
+ reg_bsn_monitor_1gbe_reset_export : out std_logic; -- reg_bsn_monitor_1gbe_reset.export
+ reg_bsn_monitor_1gbe_write_export : out std_logic; -- reg_bsn_monitor_1gbe_write.export
+ reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_bsn_monitor_1gbe_writedata.export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_10gbe_address.export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- reg_diag_bg_10gbe_clk.export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- reg_diag_bg_10gbe_read.export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_10gbe_readdata.export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- reg_diag_bg_10gbe_reset.export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- reg_diag_bg_10gbe_write.export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_10gbe_writedata.export
+ reg_diag_bg_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_bg_1gbe_address.export
+ reg_diag_bg_1gbe_clk_export : out std_logic; -- reg_diag_bg_1gbe_clk.export
+ reg_diag_bg_1gbe_read_export : out std_logic; -- reg_diag_bg_1gbe_read.export
+ reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_bg_1gbe_readdata.export
+ reg_diag_bg_1gbe_reset_export : out std_logic; -- reg_diag_bg_1gbe_reset.export
+ reg_diag_bg_1gbe_write_export : out std_logic; -- reg_diag_bg_1gbe_write.export
+ reg_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_bg_1gbe_writedata.export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- reg_diag_data_buffer_10gbe_address.export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- reg_diag_data_buffer_10gbe_clk.export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- reg_diag_data_buffer_10gbe_read.export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_10gbe_readdata.export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- reg_diag_data_buffer_10gbe_reset.export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- reg_diag_data_buffer_10gbe_write.export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_10gbe_writedata.export
+ reg_diag_data_buffer_1gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_1gbe_address.export
+ reg_diag_data_buffer_1gbe_clk_export : out std_logic; -- reg_diag_data_buffer_1gbe_clk.export
+ reg_diag_data_buffer_1gbe_read_export : out std_logic; -- reg_diag_data_buffer_1gbe_read.export
+ reg_diag_data_buffer_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_1gbe_readdata.export
+ reg_diag_data_buffer_1gbe_reset_export : out std_logic; -- reg_diag_data_buffer_1gbe_reset.export
+ reg_diag_data_buffer_1gbe_write_export : out std_logic; -- reg_diag_data_buffer_1gbe_write.export
+ reg_diag_data_buffer_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_1gbe_writedata.export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_i_address.export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_clk.export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_read.export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_i_readdata.export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_reset.export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_i_write.export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_i_writedata.export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_address.export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_clk.export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_read.export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_data_buffer_ddr_mb_ii_readdata.export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_reset.export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- reg_diag_data_buffer_ddr_mb_ii_write.export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_data_buffer_ddr_mb_ii_writedata.export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- reg_diag_rx_seq_10gbe_address.export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- reg_diag_rx_seq_10gbe_clk.export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- reg_diag_rx_seq_10gbe_read.export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_10gbe_readdata.export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- reg_diag_rx_seq_10gbe_reset.export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- reg_diag_rx_seq_10gbe_write.export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_10gbe_writedata.export
+ reg_diag_rx_seq_1gbe_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_1gbe_address.export
+ reg_diag_rx_seq_1gbe_clk_export : out std_logic; -- reg_diag_rx_seq_1gbe_clk.export
+ reg_diag_rx_seq_1gbe_read_export : out std_logic; -- reg_diag_rx_seq_1gbe_read.export
+ reg_diag_rx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_1gbe_readdata.export
+ reg_diag_rx_seq_1gbe_reset_export : out std_logic; -- reg_diag_rx_seq_1gbe_reset.export
+ reg_diag_rx_seq_1gbe_write_export : out std_logic; -- reg_diag_rx_seq_1gbe_write.export
+ reg_diag_rx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_1gbe_writedata.export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_i_address.export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_clk.export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_read.export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_i_readdata.export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_reset.export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_i_write.export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_i_writedata.export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_address.export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_clk.export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_read.export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_rx_seq_ddr_mb_ii_readdata.export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_reset.export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_rx_seq_ddr_mb_ii_write.export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_rx_seq_ddr_mb_ii_writedata.export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- reg_diag_tx_seq_10gbe_address.export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- reg_diag_tx_seq_10gbe_clk.export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- reg_diag_tx_seq_10gbe_read.export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_10gbe_readdata.export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- reg_diag_tx_seq_10gbe_reset.export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- reg_diag_tx_seq_10gbe_write.export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_10gbe_writedata.export
+ reg_diag_tx_seq_1gbe_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_1gbe_address.export
+ reg_diag_tx_seq_1gbe_clk_export : out std_logic; -- reg_diag_tx_seq_1gbe_clk.export
+ reg_diag_tx_seq_1gbe_read_export : out std_logic; -- reg_diag_tx_seq_1gbe_read.export
+ reg_diag_tx_seq_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_1gbe_readdata.export
+ reg_diag_tx_seq_1gbe_reset_export : out std_logic; -- reg_diag_tx_seq_1gbe_reset.export
+ reg_diag_tx_seq_1gbe_write_export : out std_logic; -- reg_diag_tx_seq_1gbe_write.export
+ reg_diag_tx_seq_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_1gbe_writedata.export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_i_address.export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_clk.export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_read.export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_i_readdata.export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_reset.export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_i_write.export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_i_writedata.export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_address.export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_clk.export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_read.export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_diag_tx_seq_ddr_mb_ii_readdata.export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_reset.export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- reg_diag_tx_seq_ddr_mb_ii_write.export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_diag_tx_seq_ddr_mb_ii_writedata.export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_ctrl_address.export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- reg_dpmm_ctrl_clk.export
+ reg_dpmm_ctrl_read_export : out std_logic; -- reg_dpmm_ctrl_read.export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_ctrl_readdata.export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- reg_dpmm_ctrl_reset.export
+ reg_dpmm_ctrl_write_export : out std_logic; -- reg_dpmm_ctrl_write.export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_ctrl_writedata.export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- reg_dpmm_data_address.export
+ reg_dpmm_data_clk_export : out std_logic; -- reg_dpmm_data_clk.export
+ reg_dpmm_data_read_export : out std_logic; -- reg_dpmm_data_read.export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_dpmm_data_readdata.export
+ reg_dpmm_data_reset_export : out std_logic; -- reg_dpmm_data_reset.export
+ reg_dpmm_data_write_export : out std_logic; -- reg_dpmm_data_write.export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_dpmm_data_writedata.export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- reg_epcs_address.export
+ reg_epcs_clk_export : out std_logic; -- reg_epcs_clk.export
+ reg_epcs_read_export : out std_logic; -- reg_epcs_read.export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_epcs_readdata.export
+ reg_epcs_reset_export : out std_logic; -- reg_epcs_reset.export
+ reg_epcs_write_export : out std_logic; -- reg_epcs_write.export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- reg_epcs_writedata.export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back0_address.export
+ reg_eth10g_back0_clk_export : out std_logic; -- reg_eth10g_back0_clk.export
+ reg_eth10g_back0_read_export : out std_logic; -- reg_eth10g_back0_read.export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back0_readdata.export
+ reg_eth10g_back0_reset_export : out std_logic; -- reg_eth10g_back0_reset.export
+ reg_eth10g_back0_write_export : out std_logic; -- reg_eth10g_back0_write.export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back0_writedata.export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- reg_eth10g_back1_address.export
+ reg_eth10g_back1_clk_export : out std_logic; -- reg_eth10g_back1_clk.export
+ reg_eth10g_back1_read_export : out std_logic; -- reg_eth10g_back1_read.export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_back1_readdata.export
+ reg_eth10g_back1_reset_export : out std_logic; -- reg_eth10g_back1_reset.export
+ reg_eth10g_back1_write_export : out std_logic; -- reg_eth10g_back1_write.export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_back1_writedata.export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- reg_eth10g_qsfp_ring_address.export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- reg_eth10g_qsfp_ring_clk.export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- reg_eth10g_qsfp_ring_read.export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_eth10g_qsfp_ring_readdata.export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- reg_eth10g_qsfp_ring_reset.export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- reg_eth10g_qsfp_ring_write.export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_eth10g_qsfp_ring_writedata.export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- reg_fpga_temp_sens_address.export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- reg_fpga_temp_sens_clk.export
+ reg_fpga_temp_sens_read_export : out std_logic; -- reg_fpga_temp_sens_read.export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_temp_sens_readdata.export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- reg_fpga_temp_sens_reset.export
+ reg_fpga_temp_sens_write_export : out std_logic; -- reg_fpga_temp_sens_write.export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_temp_sens_writedata.export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- reg_fpga_voltage_sens_address.export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- reg_fpga_voltage_sens_clk.export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- reg_fpga_voltage_sens_read.export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_fpga_voltage_sens_readdata.export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- reg_fpga_voltage_sens_reset.export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- reg_fpga_voltage_sens_write.export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_fpga_voltage_sens_writedata.export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_i_address.export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- reg_io_ddr_mb_i_clk.export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- reg_io_ddr_mb_i_read.export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_i_readdata.export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- reg_io_ddr_mb_i_reset.export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- reg_io_ddr_mb_i_write.export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_i_writedata.export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- reg_io_ddr_mb_ii_address.export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- reg_io_ddr_mb_ii_clk.export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- reg_io_ddr_mb_ii_read.export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_io_ddr_mb_ii_readdata.export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- reg_io_ddr_mb_ii_reset.export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- reg_io_ddr_mb_ii_write.export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- reg_io_ddr_mb_ii_writedata.export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_ctrl_address.export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- reg_mmdp_ctrl_clk.export
+ reg_mmdp_ctrl_read_export : out std_logic; -- reg_mmdp_ctrl_read.export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_ctrl_readdata.export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- reg_mmdp_ctrl_reset.export
+ reg_mmdp_ctrl_write_export : out std_logic; -- reg_mmdp_ctrl_write.export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_ctrl_writedata.export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- reg_mmdp_data_address.export
+ reg_mmdp_data_clk_export : out std_logic; -- reg_mmdp_data_clk.export
+ reg_mmdp_data_read_export : out std_logic; -- reg_mmdp_data_read.export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_mmdp_data_readdata.export
+ reg_mmdp_data_reset_export : out std_logic; -- reg_mmdp_data_reset.export
+ reg_mmdp_data_write_export : out std_logic; -- reg_mmdp_data_write.export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- reg_mmdp_data_writedata.export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- reg_remu_address.export
+ reg_remu_clk_export : out std_logic; -- reg_remu_clk.export
+ reg_remu_read_export : out std_logic; -- reg_remu_read.export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_remu_readdata.export
+ reg_remu_reset_export : out std_logic; -- reg_remu_reset.export
+ reg_remu_write_export : out std_logic; -- reg_remu_write.export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- reg_remu_writedata.export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back0_address.export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- reg_tr_10gbe_back0_clk.export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- reg_tr_10gbe_back0_read.export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back0_readdata.export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- reg_tr_10gbe_back0_reset.export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back0_waitrequest.export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- reg_tr_10gbe_back0_write.export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back0_writedata.export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- reg_tr_10gbe_back1_address.export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- reg_tr_10gbe_back1_clk.export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- reg_tr_10gbe_back1_read.export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_back1_readdata.export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- reg_tr_10gbe_back1_reset.export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_back1_waitrequest.export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- reg_tr_10gbe_back1_write.export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_back1_writedata.export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- reg_tr_10gbe_qsfp_ring_address.export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_clk.export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_read.export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_tr_10gbe_qsfp_ring_readdata.export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_reset.export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := '0'; -- reg_tr_10gbe_qsfp_ring_waitrequest.export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- reg_tr_10gbe_qsfp_ring_write.export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- reg_tr_10gbe_qsfp_ring_writedata.export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- reg_unb_pmbus_address.export
+ reg_unb_pmbus_clk_export : out std_logic; -- reg_unb_pmbus_clk.export
+ reg_unb_pmbus_read_export : out std_logic; -- reg_unb_pmbus_read.export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_pmbus_readdata.export
+ reg_unb_pmbus_reset_export : out std_logic; -- reg_unb_pmbus_reset.export
+ reg_unb_pmbus_write_export : out std_logic; -- reg_unb_pmbus_write.export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_pmbus_writedata.export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- reg_unb_sens_address.export
+ reg_unb_sens_clk_export : out std_logic; -- reg_unb_sens_clk.export
+ reg_unb_sens_read_export : out std_logic; -- reg_unb_sens_read.export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_unb_sens_readdata.export
+ reg_unb_sens_reset_export : out std_logic; -- reg_unb_sens_reset.export
+ reg_unb_sens_write_export : out std_logic; -- reg_unb_sens_write.export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- reg_unb_sens_writedata.export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- reg_wdi_address.export
+ reg_wdi_clk_export : out std_logic; -- reg_wdi_clk.export
+ reg_wdi_read_export : out std_logic; -- reg_wdi_read.export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- reg_wdi_readdata.export
+ reg_wdi_reset_export : out std_logic; -- reg_wdi_reset.export
+ reg_wdi_write_export : out std_logic; -- reg_wdi_write.export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- reg_wdi_writedata.export
+ reset_reset_n : in std_logic := '0'; -- reset.reset_n
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- rom_system_info_address.export
+ rom_system_info_clk_export : out std_logic; -- rom_system_info_clk.export
+ rom_system_info_read_export : out std_logic; -- rom_system_info_read.export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- rom_system_info_readdata.export
+ rom_system_info_reset_export : out std_logic; -- rom_system_info_reset.export
+ rom_system_info_write_export : out std_logic; -- rom_system_info_write.export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- rom_system_info_writedata.export
+ );
+ end component qsys_unb2b_test;
end qsys_unb2b_test_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index db643432f2f69347a5544c11a16615c59ae5ed39..153cbc0329b6e0dc1fe9abac0a5ce022ebfdb157 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2b_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2b_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2b_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable (disabled by default)
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index 5886a9aef1f2cdadbdeb47b185fea035593d6c63..276d51837dad969a12417e63c9e863923b5e914b 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -21,20 +21,20 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2b_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2b_test_pkg.all;
entity unb2b_test is
generic (
@@ -315,10 +315,10 @@ architecture str of unb2b_test is
signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
- -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
- -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_TX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
+ -- SIGNAL i_BCK_RX : t_unb2b_board_back_bus_2arr(c_nof_back_bus-1 DOWNTO 0);
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 + c_nof_streams_back1 - 1 downto 0);
@@ -351,13 +351,13 @@ architecture str of unb2b_test is
signal reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
signal reg_diag_tx_seq_10GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
---
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
--- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_miso : t_mem_miso;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_tx_1GbE_hdr_dat_miso : t_mem_miso;
+ --
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_mosi : t_mem_mosi;
+ -- SIGNAL reg_dp_offload_rx_1GbE_hdr_dat_miso : t_mem_miso;
signal reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
signal reg_bsn_monitor_1GbE_miso : t_mem_miso;
@@ -434,386 +434,387 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2b_board_lib.ctrl_unb2b_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_udp_offload => c_use_1GbE,
- g_udp_offload_nof_streams => c_nof_streams_1GbE,
- g_dp_clk_use_pll => true,
- g_factory_image => g_factory_image
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth1g_eth0_mm_rst,
- eth1g_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_tse_miso => eth1g_eth0_tse_miso,
- eth1g_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_reg_miso => eth1g_eth0_reg_miso,
- eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_udp_offload => c_use_1GbE,
+ g_udp_offload_nof_streams => c_nof_streams_1GbE,
+ g_dp_clk_use_pll => true,
+ g_factory_image => g_factory_image
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2b_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_1GbE => c_unb2b_board_nof_eth,
- g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
- g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
- g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
- g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
- eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
- eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
- eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
- eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
- eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
- eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
- eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
-
- -- eth1g ch1
- eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
- eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
- eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
- eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
- eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
- eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
- eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
- eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- block gen
- ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
- reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
- reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
-
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- dp_offload_tx
--- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
---
--- -- dp_offload_rx
--- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-
- -- bsn
- reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
-
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
- reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
- reg_eth10g_back1_miso => reg_eth10g_back1_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
- );
-
- gen_udp_stream_1GbE : if c_use_1GbE = true generate
- u_udp_stream_1GbE : entity work.udp_stream
generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_1GbE,
- g_data_w => c_data_w_32,
- g_bg_block_size => c_def_1GbE_block_size,
- g_bg_gapsize => c_bg_gapsize_1GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_1GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
- g_remove_crc => true
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_1GbE => c_unb2b_board_nof_eth,
+ g_nof_streams_qsfp => c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => 24, -- c_unb2b_board_tr_ring.nof_bus * c_unb2b_board_tr_ring.bus_w,
+ g_nof_streams_back0 => 24, -- c_unb2b_board_tr_back.bus_w,
+ g_nof_streams_back1 => 24 -- c_unb2b_board_tr_back.bus_w
)
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ID => ID,
-
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_eth0_mm_rst => eth1g_eth0_mm_rst,
+ eth1g_eth0_tse_mosi => eth1g_eth0_tse_mosi,
+ eth1g_eth0_tse_miso => eth1g_eth0_tse_miso,
+ eth1g_eth0_reg_mosi => eth1g_eth0_reg_mosi,
+ eth1g_eth0_reg_miso => eth1g_eth0_reg_miso,
+ eth1g_eth0_reg_interrupt => eth1g_eth0_reg_interrupt,
+ eth1g_eth0_ram_mosi => eth1g_eth0_ram_mosi,
+ eth1g_eth0_ram_miso => eth1g_eth0_ram_miso,
+
+ -- eth1g ch1
+ eth1g_eth1_mm_rst => eth1g_eth1_mm_rst,
+ eth1g_eth1_tse_mosi => eth1g_eth1_tse_mosi,
+ eth1g_eth1_tse_miso => eth1g_eth1_tse_miso,
+ eth1g_eth1_reg_mosi => eth1g_eth1_reg_mosi,
+ eth1g_eth1_reg_miso => eth1g_eth1_reg_miso,
+ eth1g_eth1_reg_interrupt => eth1g_eth1_reg_interrupt,
+ eth1g_eth1_ram_mosi => eth1g_eth1_ram_mosi,
+ eth1g_eth1_ram_miso => eth1g_eth1_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- block gen
+ ram_diag_bg_1GbE_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_1GbE_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_bg_1GbE_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_1GbE_miso => reg_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_1GbE_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_1GbE_miso => reg_diag_tx_seq_1GbE_miso,
+
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-- dp_offload_tx
--- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
--- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
--- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
- dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-
- -- dp_offload_rx
--- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
--- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
- dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+ -- reg_dp_offload_tx_1GbE_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_1GbE_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_1GbE_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ --
+ -- -- dp_offload_rx
+ -- reg_dp_offload_rx_1GbE_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_1GbE_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
-- bsn
- reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_1GbE_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_1GbE_miso => reg_bsn_monitor_1GbE_miso,
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-- databuffer
- reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ ram_diag_data_buf_1GbE_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_1GbE_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_data_buf_1GbE_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_1GbE_miso => reg_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_1GbE_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_1GbE_miso => reg_diag_rx_seq_1GbE_miso,
+
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ reg_tr_10GbE_back1_mosi => reg_tr_10GbE_back1_mosi,
+ reg_tr_10GbE_back1_miso => reg_tr_10GbE_back1_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ reg_eth10g_back1_mosi => reg_eth10g_back1_mosi,
+ reg_eth10g_back1_miso => reg_eth10g_back1_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
+
+ gen_udp_stream_1GbE : if c_use_1GbE = true generate
+ u_udp_stream_1GbE : entity work.udp_stream
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_1GbE,
+ g_data_w => c_data_w_32,
+ g_bg_block_size => c_def_1GbE_block_size,
+ g_bg_gapsize => c_bg_gapsize_1GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_1GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
+ g_remove_crc => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ID => ID,
+
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
+
+ -- dp_offload_tx
+ -- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
+ -- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
+ -- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
+ dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
+
+ -- dp_offload_rx
+ -- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
+ -- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
+
+ -- bsn
+ reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
+
+ -- databuffer
+ reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
+ );
end generate;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
+
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -824,87 +825,87 @@ begin
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
-
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -923,161 +924,161 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- --QSFP_SDA => QSFP_SDA,
- --QSFP_SCL => QSFP_SCL,
- --QSFP_RST => QSFP_RST,
-
- QSFP_LED => QSFP_LED
- );
-
--- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
--- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
--- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
--- END GENERATE;
---
--- i_RING_RX(0) <= RING_0_RX;
--- i_RING_RX(1) <= RING_1_RX;
--- RING_0_TX <= i_RING_TX(0);
--- RING_1_TX <= i_RING_TX(1);
---
--- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
--- GENERIC MAP (
--- g_nof_ring_bus => 2--c_nof_ring_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_ring_arr,
--- serial_rx_arr => serial_10G_rx_ring_arr,
--- RING_RX => i_RING_RX,
--- RING_TX => i_RING_TX
--- );
-
--- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
--- GENERIC MAP (
--- g_sim => g_sim,
--- g_sim_level => 1,
--- g_technology => g_technology,
--- g_nof_macs => c_nof_streams_back0,
--- g_tx_fifo_fill => c_def_10GbE_block_size,
--- g_tx_fifo_size => c_def_10GbE_block_size*2
--- )
--- PORT MAP (
--- tr_ref_clk => SB_CLK,
--- mm_rst => mm_rst,
--- mm_clk => mm_clk,
--- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
--- reg_mac_miso => reg_tr_10GbE_back0_miso,
--- reg_eth10g_mosi => reg_eth10g_back0_mosi,
--- reg_eth10g_miso => reg_eth10g_back0_miso,
--- dp_rst => dp_rst,
--- dp_clk => dp_clk,
---
--- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
--- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
----- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
----- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
---
--- serial_tx_arr => i_serial_10G_tx_back0_arr,
--- serial_rx_arr => i_serial_10G_rx_back0_arr
--- );
---
--- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
--- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
--- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
--- END GENERATE;
--- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
--- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
--- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
--- --END GENERATE;
---
--- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => c_nof_back_bus
--- )
--- PORT MAP (
--- serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_10G_rx_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
--- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
--- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
--- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
---
--- BCK_SDA => BCK_SDA,
--- BCK_SCL => BCK_SCL,
--- BCK_ERR => BCK_ERR
--- );
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ --QSFP_SDA => QSFP_SDA,
+ --QSFP_SCL => QSFP_SCL,
+ --QSFP_RST => QSFP_RST,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ -- gen_ring_wires: FOR i IN 0 TO c_nof_streams_ring-1 GENERATE
+ -- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i+c_nof_streams_qsfp);
+ -- i_serial_10G_rx_qsfp_ring_arr(i+c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
+ -- END GENERATE;
+ --
+ -- i_RING_RX(0) <= RING_0_RX;
+ -- i_RING_RX(1) <= RING_1_RX;
+ -- RING_0_TX <= i_RING_TX(0);
+ -- RING_1_TX <= i_RING_TX(1);
+ --
+ -- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ -- GENERIC MAP (
+ -- g_nof_ring_bus => 2--c_nof_ring_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_ring_arr,
+ -- serial_rx_arr => serial_10G_rx_ring_arr,
+ -- RING_RX => i_RING_RX,
+ -- RING_TX => i_RING_TX
+ -- );
+
+ -- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
+ -- GENERIC MAP (
+ -- g_sim => g_sim,
+ -- g_sim_level => 1,
+ -- g_technology => g_technology,
+ -- g_nof_macs => c_nof_streams_back0,
+ -- g_tx_fifo_fill => c_def_10GbE_block_size,
+ -- g_tx_fifo_size => c_def_10GbE_block_size*2
+ -- )
+ -- PORT MAP (
+ -- tr_ref_clk => SB_CLK,
+ -- mm_rst => mm_rst,
+ -- mm_clk => mm_clk,
+ -- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ -- reg_mac_miso => reg_tr_10GbE_back0_miso,
+ -- reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ -- reg_eth10g_miso => reg_eth10g_back0_miso,
+ -- dp_rst => dp_rst,
+ -- dp_clk => dp_clk,
+ --
+ -- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ -- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ ---- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0-1 DOWNTO 0),
+ ---- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0-1 DOWNTO 0),
+ --
+ -- serial_tx_arr => i_serial_10G_tx_back0_arr,
+ -- serial_rx_arr => i_serial_10G_rx_back0_arr
+ -- );
+ --
+ -- gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
+ -- serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
+ -- i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
+ -- END GENERATE;
+ -- --gen_back1_wires: FOR i IN 0 TO c_nof_streams_back1-1 GENERATE
+ -- -- serial_10G_tx_back_arr(i+c_nof_streams_back0) <= i_serial_10G_tx_back1_arr(i);
+ -- -- i_serial_10G_rx_back1_arr(i) <= serial_10G_rx_back_arr(i+c_nof_streams_back0);
+ -- --END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2b_board_lib.unb2b_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => c_nof_back_bus
+ -- )
+ -- PORT MAP (
+ -- serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_10G_rx_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_back0-1 downto 0),
+ -- BCK_TX(0) => BCK_TX(c_nof_streams_back0-1 downto 0),
+ -- --BCK_RX(1) => BCK_RX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ -- --BCK_TX(1) => BCK_TX(c_nof_streams_back0+c_nof_streams_back1-1 downto c_nof_streams_back0),
+ --
+ -- BCK_SDA => BCK_SDA,
+ -- BCK_SCL => BCK_SCL,
+ -- BCK_ERR => BCK_ERR
+ -- );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
-
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
-
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2b_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1088,156 +1089,155 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_I,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_I,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
-
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
-
- -- IO_DDR
- g_io_tech_ddr => g_ddr_MB_II,
-
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
+
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+
+ -- IO_DDR
+ g_io_tech_ddr => g_ddr_MB_II,
+
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index 1fbcce3b6de1d7bae0adb60756efb0bb0f6b8cc3..d152d2ef5110fc954140be54d4a3804a3e4d5f7d 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -20,37 +20,37 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
package unb2b_test_pkg is
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index fbf404947d04d7a4da2c9edc811afae477859de1..881f9e5bcd549f80bd2b94d1d86f60ff408370a2 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -43,14 +43,14 @@
--
library IEEE, common_lib, unb2b_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2b_board_lib.unb2b_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2b_board_lib.unb2b_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2b_test is
generic (
@@ -182,142 +182,142 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2b_test : entity work.unb2b_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr,
- g_ddr_MB_I => c_ddr_MB_I,
- g_ddr_MB_II => c_ddr_MB_II
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- SENS_SC => sens_scl,
- SENS_SD => sens_sda,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- PMBUS_ALERT => '0',
-
- -- Serial I/O
- -- QSFP_0_TX => si_lpbk_0,
- -- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_ddr_MB_I => c_ddr_MB_I,
+ g_ddr_MB_II => c_ddr_MB_II
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ PMBUS_ALERT => '0',
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => sens_scl,
- sda => sens_sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index a23d26634c2fbf51d0e5ce4ec96d2069c24970cc..f7d8d5fbbf338786d33fcebda9905ea0fc651ebd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2b_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2b_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2b_board is
generic (
@@ -260,7 +260,7 @@ architecture str of ctrl_unb2b_board is
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
- constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
+ constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2 ** 9, 'X');
-- Clock and reset
signal i_ext_clk200 : std_logic;
@@ -335,15 +335,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -352,15 +352,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -368,26 +368,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -401,29 +401,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2b_board_clk200_pll : entity work.unb2b_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -434,51 +434,51 @@ begin
clk125 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2b_board_mm_clk_freq_50M else
- clk50; -- default
+ clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2b_board_clk125_pll : entity work.unb2b_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2b_board_node_ctrl : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -486,33 +486,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2b_board_system_info : entity work.mms_unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -547,12 +547,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -563,15 +563,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2b_board_wdi_reg : entity work.unb2b_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -580,75 +580,75 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
@@ -657,74 +657,74 @@ begin
mm_board_sens_start <= mm_pulse_s when g_sim = false else mm_pulse_s; -- mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
u_mms_unb2b_board_pmbus : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
u_mms_unb2b_fpga_sens : entity work.mms_unb2b_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -733,18 +733,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -769,60 +769,60 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(0),
+ eth_rxp => ETH_SGIN(0),
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(0),
- eth_rxp => ETH_SGIN(0),
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index 80d5432cf6ed616ad16f6149380e518f04c943fb..e205ce4a2a976ac78abab1a66ab10aad9c1798e9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -23,10 +23,10 @@
-- Description: See unb2b_board_sens.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_unb2b_board_sens is
generic (
@@ -65,48 +65,48 @@ architecture str of mms_unb2b_board_sens is
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
begin
u_unb2b_board_sens_reg : entity work.unb2b_board_sens_reg
- generic map (
- g_sens_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_sens_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers
- sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
- sens_data => sens_data,
+ -- MM registers
+ sens_err => sens_err, -- using same protocol list for both node2 and all nodes implies that sens_err is only valid for node2.
+ sens_data => sens_data,
- -- Max temp threshold
- temp_high => temp_high
- );
+ -- Max temp threshold
+ temp_high => temp_high
+ );
u_unb2b_board_sens : entity work.unb2b_board_sens
- generic map (
- g_sim => g_sim,
- g_i2c_peripheral => g_i2c_peripheral,
- g_clk_freq => g_clk_freq,
- g_temp_high => g_temp_high,
- g_sens_nof_result => g_sens_nof_result,
- g_comma_w => g_comma_w
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
- start => mm_start,
- -- i2c bus
- scl => scl,
- sda => sda,
- -- read results
- sens_evt => OPEN,
- sens_err => sens_err,
- sens_data => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_i2c_peripheral => g_i2c_peripheral,
+ g_clk_freq => g_clk_freq,
+ g_temp_high => g_temp_high,
+ g_sens_nof_result => g_sens_nof_result,
+ g_comma_w => g_comma_w
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+ start => mm_start,
+ -- i2c bus
+ scl => scl,
+ sda => sda,
+ -- read results
+ sens_evt => OPEN,
+ sens_err => sens_err,
+ sens_data => sens_data
+ );
-- Temperature: 7 bits (1 bit per degree) plus sign. A faulty readout (never pulled down = all ones)
-- would produce -1 degrees so does not trigger a temperature alarm.
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 690b1507ac402793d47bcb056b7b37114c1613f9..5faec735a07cfe84f9028421d604988e1acd75f0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2b_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2b_board_system_info;
architecture str of mms_unb2b_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2b_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/";
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
- signal i_info : std_logic_vector(c_word_w - 1 downto 0);
+ signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2b_board_system_info: entity work.unb2b_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2b_board_system_info_reg: entity work.unb2b_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 8debc61a00f8796d34118b4aa36ceb74fbc6cd97..a85af1b037f67d713cd8ebe912894f1dbcb5168e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2b_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2b_fpga_sens is
generic (
@@ -55,22 +55,22 @@ end mms_unb2b_fpga_sens;
architecture str of mms_unb2b_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index 4054420d21a4f987e7375b8fb9b59906f14d0a14..1c00a27dc04283d17057b33867f836797260fc23 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_back_io is
generic (
@@ -52,6 +52,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2b_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index f2886ef970e244fdfc973e7c87111c79e50f3c7c..0019aeacef456d53679dd2fccbbeeb0b41d9f9c0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -60,46 +60,45 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
-
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index ac2db2f0ca43b5d3458a016c25a86eae4d501a1c..013753bc46c1fde588713ddf9e9f7370e73c61bf 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index 24625f7333a8fd823fd6eed0cf2e5198724b47e4..f1feb6518f26ea08cb2981bd1c9ae57a1fd951da 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -52,16 +52,16 @@ end unb2b_board_clk25_pll;
architecture arria10 of unb2b_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index a5877c96a459a50258e9d6de8005778240fbda51..3ab240a0a33a71ad4445b5ba677cca4394046c47 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index 8eaa8e52bc3779e074e5dadfa7cb482dfaf3e66f..2884e1a48f12e57dcba88b7471ed4b6d33790ad7 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_front_io is
generic (
@@ -61,9 +61,10 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2b_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index 06b87a197e1dbb9cfea0f70f306cb3308e86a314..b3431dbeba3cd91bb40a9d51ee51a3dac350742c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_hmc_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2b_board_hmc_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index affbc014cb1d346b7737e6de055d4398127139e8..5c5bdd5405fe5676667d237eaa890fa00ae8376f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2b_board_wdi_extend : entity work.unb2b_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 50a6d2d7a593b54b932f9ed9bdfcec53db98972a..fe9123e3d8f8977cdb8cd07d82e857773b350876 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2b_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2b_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
@@ -164,7 +164,6 @@ package unb2b_board_peripherals_pkg is
end record;
constant c_unb2b_board_peripherals_mm_reg_default : t_c_unb2b_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 13, 1, 2, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
-
end unb2b_board_peripherals_pkg;
package body unb2b_board_peripherals_pkg is
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index ecc6fbb01be98b27604e6e0aa49c84cb2d09a4fc..59d425b521a2866a0d9d9d7ccc37e47d090f802b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2b_board_pkg is
-- UniBoard
@@ -39,17 +39,17 @@ package unb2b_board_pkg is
constant c_unb2b_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
-- Clock frequencies
- constant c_unb2b_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2b_board_ext_clk_freq_256M : natural := 256 * 10**6; -- external clock, SMA clock
- constant c_unb2b_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2b_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2b_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2b_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2b_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2b_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_ext_clk_freq_200M : natural := 200 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2b_board_ext_clk_freq_256M : natural := 256 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2b_board_eth_clk_freq_25M : natural := 25 * 10 ** 6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2b_board_eth_clk_freq_125M : natural := 125 * 10 ** 6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2b_board_tse_clk_freq : natural := 125 * 10 ** 6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2b_board_cal_clk_freq : natural := 40 * 10 ** 6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_10M : natural := 10 * 10 ** 6; -- clock when g_sim=TRUE
+ constant c_unb2b_board_mm_clk_freq_25M : natural := 25 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_50M : natural := 50 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_100M : natural := 100 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2b_board_mm_clk_freq_125M : natural := 125 * 10 ** 6; -- clock derived from ETH_clk by PLL
-- I2C
constant c_unb2b_board_reg_sens_adr_w : natural := 3; -- must match ceil_log2(c_mm_nof_dat) in unb2b_board_sens_reg.vhd
@@ -145,21 +145,22 @@ package unb2b_board_pkg is
type t_c_unb2b_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
-
+ function func_unb2b_board_system_info(
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info;
end unb2b_board_pkg;
package body unb2b_board_pkg is
- function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
+ function func_unb2b_board_system_info(
+ VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
variable v_system_info : t_c_unb2b_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index c900196512ceae7f91f3fea9cbf0e2aba2b702cd..6fc54360dd48037a211f7256cc43cf3cf1bf8de0 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_pmbus_ctrl is
generic (
@@ -89,7 +89,7 @@ architecture rtl of unb2b_board_pmbus_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index 08ffbbe35b61070253acda92abc2d44202345617..0caece24bd4fdd58022412949139a36f01ffcd5b 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 4d89b79a08e3f6a00a0076e2f4b7523ec2f07012..e3c43d15b64ef9bc990262ab0f5c77691a814b0e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_ring_io is
generic (
@@ -47,6 +47,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2b_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index bdcc956341f6e19ac53b011b4d505c2928505a45..2da9e40914c15cc304c977fe718ea0bcee1a7bee 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_sens is
generic (
@@ -50,20 +50,20 @@ end entity;
architecture str of unb2b_board_sens is
-- I2C clock rate settings
- constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
+ constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10 ** 6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
- -- 0 = no comma time
+ -- 0 = no comma time
--- octave:4> t=1/50e6
--- t = 2.0000e-08
--- octave:5> delay=2^13 * t
--- delay = 1.6384e-04
--- octave:6> delay/t
--- ans = 8192
--- octave:7> log2(ans)
--- ans = 13
--- octave:8> log2(delay/t)
--- ans = 13
+ -- octave:4> t=1/50e6
+ -- t = 2.0000e-08
+ -- octave:5> delay=2^13 * t
+ -- delay = 1.6384e-04
+ -- octave:6> delay/t
+ -- ans = 8192
+ -- octave:7> log2(ans)
+ -- ans = 13
+ -- octave:8> log2(delay/t)
+ -- ans = 13
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,93 +78,93 @@ architecture str of unb2b_board_sens is
begin
gen_unb2b_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2b_board_sens_ctrl : entity work.unb2b_board_sens_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_pmbus_ctrl : if g_i2c_peripheral = c_i2c_peripheral_pmbus generate
u_unb2b_board_pmbus_ctrl : entity work.unb2b_board_pmbus_ctrl
- generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
- )
- port map (
- clk => clk,
- rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
- );
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
end generate;
gen_unb2b_board_hmc_ctrl : if g_i2c_peripheral = c_i2c_peripheral_hmc generate
u_unb2b_board_hmc_ctrl : entity work.unb2b_board_hmc_ctrl
+ generic map (
+ g_sim => g_sim,
+ g_nof_result => g_sens_nof_result,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ start => start,
+ in_dat => smbus_out_dat,
+ in_val => smbus_out_val,
+ in_err => smbus_out_err,
+ in_ack => smbus_out_ack,
+ in_end => smbus_out_end,
+ out_dat => smbus_in_dat,
+ out_val => smbus_in_val,
+ result_val => sens_evt,
+ result_err => sens_err,
+ result_dat => sens_data
+ );
+ end generate;
+
+ u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
- g_sim => g_sim,
- g_nof_result => g_sens_nof_result,
- g_temp_high => g_temp_high
+ g_i2c_phy => c_sens_phy,
+ g_clock_stretch_sense_scl => true
)
port map (
+ gs_sim => g_sim,
clk => clk,
rst => rst,
- start => start,
- in_dat => smbus_out_dat,
- in_val => smbus_out_val,
- in_err => smbus_out_err,
- in_ack => smbus_out_ack,
- in_end => smbus_out_end,
- out_dat => smbus_in_dat,
- out_val => smbus_in_val,
- result_val => sens_evt,
- result_err => sens_err,
- result_dat => sens_data
+ in_dat => smbus_in_dat,
+ in_req => smbus_in_val,
+ out_dat => smbus_out_dat,
+ out_val => smbus_out_val,
+ out_err => smbus_out_err,
+ out_ack => smbus_out_ack,
+ st_end => smbus_out_end,
+ scl => scl,
+ sda => sda
);
- end generate;
-
- u_i2c_smbus : entity i2c_lib.i2c_smbus
- generic map (
- g_i2c_phy => c_sens_phy,
- g_clock_stretch_sense_scl => true
- )
- port map (
- gs_sim => g_sim,
- clk => clk,
- rst => rst,
- in_dat => smbus_in_dat,
- in_req => smbus_in_val,
- out_dat => smbus_out_dat,
- out_val => smbus_out_val,
- out_err => smbus_out_err,
- out_ack => smbus_out_ack,
- st_end => smbus_out_end,
- scl => scl,
- sda => sda
- );
end architecture;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index 60b4028d32b6c4203b3485c3e4794d9ec058570d..f11b8ad431be6a2789274c0bf41cffa4d994fe79 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use i2c_lib.i2c_smbus_pkg.all;
-use i2c_lib.i2c_dev_max1617_pkg.all;
-use i2c_lib.i2c_dev_ltc4260_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use i2c_lib.i2c_smbus_pkg.all;
+ use i2c_lib.i2c_dev_max1617_pkg.all;
+ use i2c_lib.i2c_dev_ltc4260_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use common_lib.common_pkg.all;
entity unb2b_board_sens_ctrl is
generic (
@@ -105,7 +105,7 @@ architecture rtl of unb2b_board_sens_ctrl is
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
- );
+ );
constant c_seq_len : natural := c_SEQ'length - 1;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index b7b2e852c0b8c482d15b8331209b0a909f6a6721..23a8c21ffdd227669dc1dc9b171656a9ba36456a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -60,10 +60,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_sens_reg is
generic (
@@ -92,15 +92,16 @@ end unb2b_board_sens_reg;
architecture rtl of unb2b_board_sens_reg is
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
- -- +1 to fit sens_err in the last address
+ -- +1 to fit sens_err in the last address
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_mm_nof_dat),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_mm_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_mm_nof_dat),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_mm_nof_dat,
+ init_sl => '0');
- signal i_temp_high : std_logic_vector(6 downto 0);
+ signal i_temp_high : std_logic_vector(6 downto 0);
begin
temp_high <= i_temp_high;
@@ -130,14 +131,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
if vA = g_sens_nof_result + 1 then
- -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
- -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
- if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
- i_temp_high <= sla_in.wrdata(6 downto 0);
- end if;
+ -- Only change temp_high if user writes a max. 7-bit value. This prevents accidentally
+ -- setting a negative temp as temp_high, e.g. 128 which becomes -128.
+ if unsigned(sla_in.wrdata(c_word_w - 1 downto 7)) = 0 then
+ i_temp_high <= sla_in.wrdata(6 downto 0);
+ end if;
end if;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index adf5baaffbd23aa5f2b97e2505c658967f120276..712298637811f7ba5bddffb9ad4dc0e4d2da0592 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2b_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2b_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index c3f5a857aa5ddf0586bf89976b5b8d5928120fdf..04c2f6f193b78c91c5510ffc0d5bdbd94e29ea10 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
entity unb2b_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2b_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2b_board_system_info_reg;
architecture rtl of unb2b_board_system_info_reg is
@@ -86,18 +86,19 @@ architecture rtl of unb2b_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
-
- constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
-
- constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
- constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
- constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
+
+ constant c_use_phy_w : natural := 8;
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+
+ constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
+ constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
begin
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index 74ccf1459b4566fda04c42e9f0c7bcdac29ad01d..3958d7e2ec67fb374146258e997b1f625d78dc98 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index f052cbb7b21c950df7ca60ccab1ad3afb4019eac..f2d4001fe56334b38a83979660bdd8fadcf72882 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2b_board_wdi_reg is
port (
@@ -40,19 +40,20 @@ entity unb2b_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2b_board_wdi_reg;
architecture rtl of unb2b_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- -- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- For safety, WDI override requires the following word to be written:
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
@@ -68,7 +69,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
if sla_in.wrdata(c_word_w - 1 downto 0) = c_cmd_reconfigure then
wdi_override <= '1';
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index ef80a940f59a7650e4e52b4a9ea66389cf3ca932..91791eccd7572585b67f52599d46f7ed58ec111e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -32,18 +32,18 @@ entity tb_mms_unb2b_board_sens is
end tb_mms_unb2b_board_sens;
library IEEE, common_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.unb2b_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.unb2b_board_pkg.all;
architecture tb of tb_mms_unb2b_board_sens is
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
- constant c_clk_freq : natural := 100 * 10**6;
- constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
+ constant c_clk_freq : natural := 100 * 10 ** 6;
+ constant c_clk_period : time := (10 ** 9 / c_clk_freq) * 1 ns;
constant c_rst_period : time := 4 * c_clk_period;
-- Model I2C sensor slaves as on the UniBoard
@@ -148,61 +148,61 @@ begin
-- I2C sensors master
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
- generic map (
- g_sim => c_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => c_clk_freq,
- g_temp_high => c_temp_high,
- g_comma_w => 13
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- mm_start => start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- i2c bus
- scl => scl,
- sda => sda
- );
+ generic map (
+ g_sim => c_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => c_clk_freq,
+ g_temp_high => c_temp_high,
+ g_comma_w => 13
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ mm_start => start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- i2c bus
+ scl => scl,
+ sda => sda
+ );
-- I2C slaves that are available for each FPGA
u_fpga_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_fpga_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_fpga_temp
- );
+ generic map (
+ g_address => c_fpga_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_fpga_temp
+ );
-- I2C slaves that are available only via FPGA node 3
u_eth_temp : entity i2c_lib.dev_max1618
- generic map (
- g_address => c_eth_temp_address
- )
- port map (
- scl => scl,
- sda => sda,
- temp => c_eth_temp
- );
+ generic map (
+ g_address => c_eth_temp_address
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ temp => c_eth_temp
+ );
u_power : entity i2c_lib.dev_ltc4260
- generic map (
- g_address => c_hot_swap_address,
- g_R_sense => c_hot_swap_R_sense
- )
- port map (
- scl => scl,
- sda => sda,
- ana_current_sense => c_uniboard_current,
- ana_volt_source => c_uniboard_supply,
- ana_volt_adin => c_uniboard_adin
- );
+ generic map (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ port map (
+ scl => scl,
+ sda => sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index df9a474f610174d3792ccb898670b46681356db3..9030c140a80edad4d920e5cd963b4cef376a2892 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk125_pll is
end tb_unb2b_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index e0559528e8cc578ca11794aa41f5b15b09b1eb37..d330a1fe3221449f7d8f72ac2ab9d48060fffaac 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk200_pll is
end tb_unb2b_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2b_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index 02d31bf344c1f93ca78584062c1c502ce14416ea..ed44f1a5f79754af810396b5e1981b963604e7ba 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_clk25_pll is
end tb_unb2b_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2b_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index 9f41504493b612ccd9a7bcfad71468dfb29e42f4..d7f9dbb21f12b0e09257cd99abad4d3a7333a44d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2b_board_node_ctrl is
end tb_unb2b_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2b_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index b7d1a8ba03c55658283f0d6f4d43cf20062e0114..8ce375d3b66dd852706446b59227d0420035348e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -37,17 +37,17 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2b_board_qsfp_leds is
end tb_unb2b_board_qsfp_leds;
architecture tb of tb_unb2b_board_qsfp_leds is
- constant c_clk_freq_hz : natural := 200 * 10**6;
- constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
+ constant c_clk_freq_hz : natural := 200 * 10 ** 6;
+ constant c_clk_period_ns : natural := 10 ** 9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
constant clk_period : time := c_clk_period_ns * 1 ns;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2b_factory_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2b_user_qsfp_leds : entity work.unb2b_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index 615aa3863ad6316b754355c47b5b07308c4ef2cf..249c026b7a8da2d5c1630ecbb92fd680b134281e 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2b_board_10gbe is
generic (
@@ -77,17 +77,17 @@ architecture str of unb2b_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2b_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index 40e4278b6c8442b5a18c6278b4780c03ef227fbe..a1afbf0bfd68968bdff91ee2c7efaeb3bbdc44b9 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_led is
generic (
@@ -114,57 +114,57 @@ begin
-- by using the fpll, the CLKUSR is used for calibration. So in case fpll does not work, check CLKUSR
u_unb2c_board_clk200_pll : entity unb2c_board_lib.unb2c_board_clk200_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk200 => CLK,
- st_clk200 => clk200
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk200 => CLK,
+ st_clk200 => clk200
+ );
xo_ethclk <= ETH_CLK(0); -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_ethclk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_ethclk,
+ out_rst => xo_rst
+ );
u_unb2c_board_clk125_pll : entity unb2c_board_lib.unb2c_board_clk125_pll
- generic map (
- g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
- g_technology => g_technology
- )
- port map (
- arst => xo_rst,
- clk125 => xo_ethclk,
- c1_clk50 => clk50,
- pll_locked => mm_locked
- );
+ generic map (
+ g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
+ g_technology => g_technology
+ )
+ port map (
+ arst => xo_rst,
+ clk125 => xo_ethclk,
+ c1_clk50 => clk50,
+ pll_locked => mm_locked
+ );
u_unb2c_board_node_ctrl : entity unb2c_board_lib.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => clk50,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => mm_pulse_s,
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
+ generic map (
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => clk50,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => mm_pulse_s,
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
------------------------------------------------------------------------------
-- Toggle red LED when unb2c_minimal is running, green LED for other designs.
@@ -173,15 +173,15 @@ begin
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
u_extend : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => mm_pulse_s,
- ep_out => led_flash
- );
+ generic map (
+ g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => mm_pulse_s,
+ ep_out => led_flash
+ );
-- Red LED control
TESTIO(c_unb2c_board_testio_led_red) <= led_flash_red;
@@ -190,36 +190,36 @@ begin
TESTIO(c_unb2c_board_testio_led_green) <= led_flash_green;
u_common_pulser_10Hz : entity common_lib.common_pulser
- generic map (
- g_pulse_period => 100,
- g_pulse_phase => 100 - 1
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- clken => '1',
- pulse_en => mm_pulse_ms,
- pulse_out => pulse_10Hz
- );
+ generic map (
+ g_pulse_period => 100,
+ g_pulse_phase => 100 - 1
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ clken => '1',
+ pulse_en => mm_pulse_ms,
+ pulse_out => pulse_10Hz
+ );
u_extend_10Hz : entity common_lib.common_pulse_extend
- generic map (
- g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
- )
- port map (
- rst => mm_rst,
- clk => clk50,
- p_in => pulse_10Hz,
- ep_out => pulse_10Hz_extended
- );
+ generic map (
+ g_extend_w => 21 -- (2^21) / 50e6 = 0.041943 th of 1 sec
+ )
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ p_in => pulse_10Hz,
+ ep_out => pulse_10Hz_extended
+ );
u_toggle : entity common_lib.common_toggle
- port map (
- rst => mm_rst,
- clk => clk50,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => mm_rst,
+ clk => clk50,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
QSFP_LED(2) <= pulse_10Hz_extended;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index c93a01d6edde99eae874b1c13b9b5e3a6202a0e3..20af6c0dae184bcf6def5e5b512391000b72bca0 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use work.qsys_unb2c_minimal_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use work.qsys_unb2c_minimal_pkg.all;
entity mmm_unb2c_minimal is
generic (
@@ -107,30 +107,39 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -277,7 +286,6 @@ begin
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w - 1 downto 0),
ram_scrap_read_export => ram_scrap_mosi.rd,
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
- );
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index 0d31242e088c49a836b4f27adaa586763bfc9338..75e4338ba02d22d49a0579c0c5a87dcdf97caad9 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -20,129 +20,128 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_minimal_pkg is
- ----------------------------------------------------------------------
- -- this component declaration is copy-pasted from Quartus QSYS builder
- ----------------------------------------------------------------------
-
- component qsys_unb2c_minimal is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_minimal;
+ ----------------------------------------------------------------------
+ -- this component declaration is copy-pasted from Quartus QSYS builder
+ ----------------------------------------------------------------------
+ component qsys_unb2c_minimal is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_minimal;
end qsys_unb2c_minimal_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 87ec5850530b265c069f02e647273a4534d0804e..d004b289a49aed3a2ccdbc62290c68bace98775d 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
entity unb2c_minimal is
generic (
@@ -146,209 +146,209 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . 1GbE Control Interface
--- ETH_clk => ETH_CLK(0),
--- ETH_SGIN => ETH_SGIN(0),
--- ETH_SGOUT => ETH_SGOUT(0)
-
- ETH_clk => ETH_CLK(1),
- ETH_SGIN => ETH_SGIN(1),
- ETH_SGOUT => ETH_SGOUT(1)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . 1GbE Control Interface
+ -- ETH_clk => ETH_CLK(0),
+ -- ETH_SGIN => ETH_SGIN(0),
+ -- ETH_SGOUT => ETH_SGOUT(0)
+
+ ETH_clk => ETH_CLK(1),
+ ETH_SGIN => ETH_SGIN(1),
+ ETH_SGOUT => ETH_SGOUT(1)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_minimal
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
index 5fc724c707fc437f308a4c839036bf3d318bfbc6..d885913a24509e075a87dca7f599378919dc4d95 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
@@ -42,20 +42,20 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use i2c_lib.i2c_dev_unb2_pkg.all;
-use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use i2c_lib.i2c_dev_unb2_pkg.all;
+ use i2c_lib.i2c_commander_unb2_pmbus_pkg.all;
entity tb_unb2c_minimal is
- generic (
- g_design_name : string := "unb2c_minimal";
- g_sim_unb_nr : natural := 0; -- UniBoard 0
- g_sim_node_nr : natural := 3 -- Node 3
- );
+ generic (
+ g_design_name : string := "unb2c_minimal";
+ g_sim_unb_nr : natural := 0; -- UniBoard 0
+ g_sim_node_nr : natural := 3 -- Node 3
+ );
end tb_unb2c_minimal;
architecture tb of tb_unb2c_minimal is
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
index cb584d11aa0e0042a81cb707dfd96b766ad3e4aa..9360603d06d53fe9aedfc67b65ad18e2609e47fd 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_10GbE is
end tb_unb2c_test_10GbE;
@@ -29,7 +29,7 @@ end tb_unb2c_test_10GbE;
architecture tb of tb_unb2c_test_10GbE is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_10GbE"
- );
+ generic map (
+ g_design_name => "unb2c_test_10GbE"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index b7c61245b6954414a2676567fe16525d2d3faf27..904184ba9ee3f39bbb84d215c4aa967a23b3a67f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_10GbE is
generic (
@@ -92,63 +92,63 @@ end unb2c_test_10GbE;
architecture str of unb2c_test_10GbE is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
- SB_CLK => SB_CLK,
- BCK_REF_CLK => BCK_REF_CLK,
-
- -- back transceivers
- --BCK_RX => BCK_RX,
- --BCK_TX => BCK_TX,
-
- -- ring transceivers
- RING_0_RX => RING_0_RX,
- RING_0_TX => RING_0_TX,
- RING_1_RX => RING_1_RX,
- RING_1_TX => RING_1_TX,
-
- -- front transceivers
- QSFP_0_RX => QSFP_0_RX,
- QSFP_0_TX => QSFP_0_TX,
- QSFP_1_RX => QSFP_1_RX,
- QSFP_1_TX => QSFP_1_TX,
- QSFP_2_RX => QSFP_2_RX,
- QSFP_2_TX => QSFP_2_TX,
- QSFP_3_RX => QSFP_3_RX,
- QSFP_3_TX => QSFP_3_TX,
- QSFP_4_RX => QSFP_4_RX,
- QSFP_4_TX => QSFP_4_TX,
- QSFP_5_RX => QSFP_5_RX,
- QSFP_5_TX => QSFP_5_TX,
-
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ SB_CLK => SB_CLK,
+ BCK_REF_CLK => BCK_REF_CLK,
+
+ -- back transceivers
+ --BCK_RX => BCK_RX,
+ --BCK_TX => BCK_TX,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- front transceivers
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ QSFP_2_RX => QSFP_2_RX,
+ QSFP_2_TX => QSFP_2_TX,
+ QSFP_3_RX => QSFP_3_RX,
+ QSFP_3_TX => QSFP_3_TX,
+ QSFP_4_RX => QSFP_4_RX,
+ QSFP_4_TX => QSFP_4_TX,
+ QSFP_5_RX => QSFP_5_RX,
+ QSFP_5_TX => QSFP_5_TX,
+
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 55beabab75a339e670927d19901f167e8763a5b5..0c8dcdaa05dd43248f428d81c89854089810d131 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -43,7 +43,7 @@
-- > tc_unb2_test_eth.py --gn2 0 --stream 0 --dest loopback -r 10000 --sizes 1000 --interval 100 --scheme tx_rx --sim
-- stop simulation.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_I is
end tb_unb2c_test_1GbE_I;
@@ -66,27 +66,27 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_I : entity work.unb2c_test_1GbE_I
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
- QSFP_LED => open
- );
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 14e29aca56f9ea10d188ec35f58018de0f5a4bc8..8ccd3f755e7f8d59001306fc45e1b57caa60fe0b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_I is
generic (
@@ -67,34 +67,34 @@ end unb2c_test_1GbE_I;
architecture str of unb2c_test_1GbE_I is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 0d481eb3274a34a366c02f8695af0bfb8629374b..85b2717521e389756ea6ad64d43570a55c1f5068 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -45,7 +45,7 @@
-- for faster sim.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_1GbE_II is
end tb_unb2c_test_1GbE_II;
@@ -68,27 +68,27 @@ begin
eth_sgin <= eth_sgout; -- loopback eth0 and eth1
u_unb2c_test_1GbE_II : entity work.unb2c_test_1GbE_II
- generic map (
- g_sim => true
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => wdi,
- INTA => OPEN,
- INTB => OPEN,
+ generic map (
+ g_sim => true
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => wdi,
+ INTA => OPEN,
+ INTB => OPEN,
- -- Others
- VERSION => "00",
- ID => "00000000",
- TESTIO => OPEN,
+ -- Others
+ VERSION => "00",
+ ID => "00000000",
+ TESTIO => OPEN,
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_sgin,
- ETH_SGOUT => eth_sgout,
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_sgin,
+ ETH_SGOUT => eth_sgout,
- QSFP_LED => open
- );
+ QSFP_LED => open
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 850e616ac8d293cfa7d82aa9392fc18e0437cbd5..e07f77e72f6b45de352e6bc718d2147c0a136dfd 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -25,11 +25,11 @@
-- Description:
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_1GbE_II is
generic (
@@ -67,34 +67,34 @@ end unb2c_test_1GbE_II;
architecture str of unb2c_test_1GbE_II is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
index d25bb0a613465f7b9704239e7a84e9784d285b76..aea05dd7b028ac6413d96d57bb3812a2b5e63bc7 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr is
end tb_unb2c_test_ddr;
@@ -29,7 +29,7 @@ end tb_unb2c_test_ddr;
architecture tb of tb_unb2c_test_ddr is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index b5b75bb185e1c4debb78015ca0aa15bec37c771b..91be6ded842d5cb9c47862412ec8a4e3ccd6d929 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr is
generic (
@@ -78,48 +78,48 @@ end unb2c_test_ddr;
architecture str of unb2c_test_ddr is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
index b3a43fdf88406ee1b8f379bd616d730a44616e1f..d2989beca7962850106e3e366e7cfb6d392b1c52 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_ddr_16G is
end tb_unb2c_test_ddr_16G;
@@ -29,7 +29,7 @@ end tb_unb2c_test_ddr_16G;
architecture tb of tb_unb2c_test_ddr_16G is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_ddr_16G"
- );
+ generic map (
+ g_design_name => "unb2c_test_ddr_16G"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index a19523ddcae8447148730f2de4abdb640ebb17a9..d7fea759e22afe7103f7eb38f5fb38f652257fdc 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity unb2c_test_ddr_16G is
generic (
@@ -78,48 +78,48 @@ end unb2c_test_ddr_16G;
architecture str of unb2c_test_ddr_16G is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- DDR reference clocks
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
+ -- DDR reference clocks
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
index 33951098a328a1f2fcb1ff7fef3bc337be04d581..dbaca1d2604ee290e7535e4c30115da9cca56802 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_heater is
end tb_unb2c_test_heater;
@@ -29,7 +29,7 @@ end tb_unb2c_test_heater;
architecture tb of tb_unb2c_test_heater is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_heater"
- );
+ generic map (
+ g_design_name => "unb2c_test_heater"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index e85b07f9c188d7050e385628bf96c27e3700d884..047ad42c6f6f0339dcbf9a260216407aed8af571 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_heater is
generic (
@@ -63,34 +63,34 @@ end unb2c_test_heater;
architecture str of unb2c_test_heater is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
index 9c8cc77e4e6b2fc803cbedbe09b9e23c893d204e..7edfbe592e77616483e96646fa60cf6b42f38ed8 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, unb2c_test_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_unb2c_test_jesd204b is
end tb_unb2c_test_jesd204b;
@@ -29,7 +29,7 @@ end tb_unb2c_test_jesd204b;
architecture tb of tb_unb2c_test_jesd204b is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
- generic map (
- g_design_name => "unb2c_test_jesd204b"
- );
+ generic map (
+ g_design_name => "unb2c_test_jesd204b"
+ );
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index 3c61c0768039e3da09c4666f29d1e74d2652bf95..709947100cb6a6e45d4afe48d35e2e31beb20534 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_jesd204b is
generic (
@@ -69,40 +69,40 @@ end unb2c_test_jesd204b;
architecture str of unb2c_test_jesd204b is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- -- jesd204b
- BCK_REF_CLK => BCK_REF_CLK,
- BCK_RX => BCK_RX,
- JESD204B_SYSREF => JESD204B_SYSREF,
- JESD204B_SYNC => JESD204B_SYNC,
+ -- jesd204b
+ BCK_REF_CLK => BCK_REF_CLK,
+ BCK_RX => BCK_RX,
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC => JESD204B_SYNC,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index 85260e0c01ed2df1c82ce1c1422f4a482294a140..3eabc49a20ef49b1e2a5022dde327604266335e8 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_test_minimal is
generic (
@@ -63,34 +63,34 @@ end unb2c_test_minimal;
architecture str of unb2c_test_minimal is
begin
u_revision : entity unb2c_test_lib.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- port map (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
+ generic map (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ port map (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 468e48a1a4c0f2ce6ab7076a9494994d7bf54ba8..e70189016d2cff3c346938d3a0b63439fbd481da 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -20,25 +20,25 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib, tech_mac_10g_lib, io_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_network_total_header_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use eth_lib.eth_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use work.qsys_unb2c_test_pkg.all;
-use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-use work.unb2c_test_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_network_total_header_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use work.qsys_unb2c_test_pkg.all;
+ use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
+ use work.unb2c_test_pkg.all;
entity mmm_unb2c_test is
generic (
@@ -259,7 +259,7 @@ architecture str of mmm_unb2c_test is
-- Simulation
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -280,115 +280,187 @@ begin
eth_0_mm_rst <= mm_rst;
eth_1_mm_rst <= mm_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
-
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
-
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
-
- u_mm_file_reg_fpga_temp_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
-
- u_mm_file_reg_fpga_voltage_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
-
- u_mm_file_reg_ppsh : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-
- u_mm_file_reg_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
- u_mm_file_ram_diag_bg_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
- port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
- u_mm_file_reg_diag_tx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
-
- u_mm_file_reg_bsn_monitor_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
-
- u_mm_file_reg_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
- u_mm_file_ram_diag_data_buffer_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
- port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
- u_mm_file_reg_diag_rx_seq_10GbE : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
-
- u_mm_file_reg_io_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
-
- u_mm_file_reg_io_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
- u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
- u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
- u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
- port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+
+ u_mm_file_reg_fpga_temp_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+
+ u_mm_file_reg_fpga_voltage_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ port map(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+
+ u_mm_file_reg_ppsh : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ port map(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+
+ u_mm_file_reg_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_bg_10GbE_mosi, reg_diag_bg_10GbE_miso);
+
+ u_mm_file_ram_diag_bg_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_bg_10GbE_mosi, ram_diag_bg_10GbE_miso);
+
+ u_mm_file_reg_diag_tx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_10GbE_mosi, reg_diag_tx_seq_10GbE_miso);
+
+ u_mm_file_reg_bsn_monitor_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
+
+ u_mm_file_reg_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_10GbE_mosi, reg_diag_data_buf_10GbE_miso);
+
+ u_mm_file_ram_diag_data_buffer_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_10GBE")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_10GbE_mosi, ram_diag_data_buf_10GbE_miso);
+
+ u_mm_file_reg_diag_rx_seq_10GbE : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
+
+ u_mm_file_reg_io_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
+
+ u_mm_file_reg_io_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
+
+ u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
+
+ u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
+ port map(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
-- . 1GbE_I with TSE setup by NiosII
- u_mm_file_reg_eth_0_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
- port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
- u_mm_file_reg_eth_0_reg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
- port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
- u_mm_file_reg_eth_0_ram : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
- port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
+ u_mm_file_reg_eth_0_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_TSE")
+ port map(mm_rst, mm_clk, eth_0_tse_mosi, eth_0_tse_miso);
+
+ u_mm_file_reg_eth_0_reg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_REG")
+ port map(mm_rst, mm_clk, i_eth_0_reg_mosi, eth_0_reg_miso);
+
+ u_mm_file_reg_eth_0_ram : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_RAM")
+ port map(mm_rst, mm_clk, eth_0_ram_mosi, eth_0_ram_miso);
-- . 1GbE_II with TSE setup in VHDL
- u_mm_file_reg_eth_1_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
- port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
-
- u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
- port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
- u_mm_file_reg_tr_10GbE_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
- port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
-
- u_mm_file_reg_eth10g_qsfp_ring : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
- port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
- u_mm_file_reg_eth10g_back0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
- port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
-
- u_mm_file_reg_heater : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
- port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
- u_mm_file_ram_scrap : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
-
- u_mm_file_reg_reg_diag_bg_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
- u_mm_file_reg_hdr_dat_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
- u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
- u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
- u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
-
- u_mm_file_reg_reg_diag_bg_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
- port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
- u_mm_file_reg_hdr_dat_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
- port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
- u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
- u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
- u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
- u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
- port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
+ u_mm_file_reg_eth_1_tse : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_TSE")
+ port map(mm_rst, mm_clk, eth_1_tse_mosi, eth_1_tse_miso);
+
+ u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
+
+ u_mm_file_reg_tr_10GbE_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_BACK0")
+ port map(mm_rst, mm_clk, reg_tr_10GbE_back0_mosi, reg_tr_10GbE_back0_miso);
+
+ u_mm_file_reg_eth10g_qsfp_ring : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_QSFP_RING")
+ port map(mm_rst, mm_clk, reg_eth10g_qsfp_ring_mosi, reg_eth10g_qsfp_ring_miso);
+
+ u_mm_file_reg_eth10g_back0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ETH10G_BACK0")
+ port map(mm_rst, mm_clk, reg_eth10g_back0_mosi, reg_eth10g_back0_miso);
+
+ u_mm_file_reg_heater : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HEATER")
+ port map(mm_rst, mm_clk, reg_heater_mosi, reg_heater_miso );
+
+ u_mm_file_ram_scrap : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ port map(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
+ u_mm_file_reg_reg_diag_bg_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_0")
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_0_copi, reg_diag_bg_eth_0_cipo );
+
+ u_mm_file_reg_hdr_dat_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_0")
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_0_copi, reg_hdr_dat_eth_0_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_0")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_0_copi, reg_bsn_monitor_v2_tx_eth_0_cipo );
+
+ u_mm_file_reg_strobe_total_count_tx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_0")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_0_copi, reg_strobe_total_count_tx_eth_0_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_0")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_0_copi, reg_bsn_monitor_v2_rx_eth_0_cipo );
+
+ u_mm_file_reg_strobe_total_count_rx_eth_0 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_0")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_0_copi, reg_strobe_total_count_rx_eth_0_cipo );
+
+ u_mm_file_reg_reg_diag_bg_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_ETH_1")
+ port map(mm_rst, mm_clk, reg_diag_bg_eth_1_copi, reg_diag_bg_eth_1_cipo );
+
+ u_mm_file_reg_hdr_dat_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT_ETH_1")
+ port map(mm_rst, mm_clk, reg_hdr_dat_eth_1_copi, reg_hdr_dat_eth_1_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_tx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX_ETH_1")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_eth_1_copi, reg_bsn_monitor_v2_tx_eth_1_cipo );
+
+ u_mm_file_reg_strobe_total_count_tx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_TX_ETH_1")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_tx_eth_1_copi, reg_strobe_total_count_tx_eth_1_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ETH_1")
+ port map(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_eth_1_copi, reg_bsn_monitor_v2_rx_eth_1_cipo );
+
+ u_mm_file_reg_strobe_total_count_rx_eth_1 : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STROBE_TOTAL_COUNT_RX_ETH_1")
+ port map(mm_rst, mm_clk, reg_strobe_total_count_rx_eth_1_copi, reg_strobe_total_count_rx_eth_1_cipo );
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -413,10 +485,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth_0_reg_mosi, i_eth_0_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth_0_reg_mosi <= sim_eth_0_reg_mosi;
- else
- eth_0_reg_mosi <= i_eth_0_reg_mosi;
- end if;
+ eth_0_reg_mosi <= sim_eth_0_reg_mosi;
+ else
+ eth_0_reg_mosi <= i_eth_0_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -892,5 +964,4 @@ begin
ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w - 1 downto 0)
);
end generate;
-
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
index 082cb255033db9026064bf00a896cde6129207ff..5204c44ac564514aa493157940c5d1514665cf5d 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
@@ -27,15 +27,15 @@
-- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
library IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
-use diag_lib.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use unb2c_board_lib.unb2c_board_peripherals_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity node_adc_input_and_timing_nowg is
generic (
@@ -86,33 +86,34 @@ entity node_adc_input_and_timing_nowg is
end node_adc_input_and_timing_nowg;
architecture str of node_adc_input_and_timing_nowg is
- constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
-
- -- Frame parameters TBC
- constant c_bs_bsn_w : natural := 64; -- 51;
- constant c_bs_block_size : natural := 1024;
- constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
- constant c_data_w : natural := 16;
-
- -- JESD signals
- signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
- signal rx_rst : std_logic;
- signal rx_sysref : std_logic;
-
- -- Sosis and sosi arrays
- signal rx_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal bs_sosi : t_dp_sosi;
- signal mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
- signal mm_rst_internal : std_logic;
- signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
- signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal jesd204b_reset : std_logic;
+ constant c_mm_jesd_ctrl_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
+
+ -- Frame parameters TBC
+ constant c_bs_bsn_w : natural := 64; -- 51;
+ constant c_bs_block_size : natural := 1024;
+ constant c_bs_nof_block_per_sync : natural := 390625; -- generate a sync every 2s for testing
+ constant c_data_w : natural := 16;
+
+ -- JESD signals
+ signal rx_clk : std_logic; -- formerly jesd204b_frame_clk
+ signal rx_rst : std_logic;
+ signal rx_sysref : std_logic;
+
+ -- Sosis and sosi arrays
+ signal rx_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal bs_sosi : t_dp_sosi;
+ signal mux_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+
+ signal mm_rst_internal : std_logic;
+ signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
+ signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal jesd204b_reset : std_logic;
begin
-- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
@@ -133,62 +134,62 @@ begin
-----------------------------------------------------------------------------
u_jesd204b: entity tech_jesd204b_lib.tech_jesd204b
- generic map(
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_nof_sync_n => g_nof_sync_n,
- g_jesd_freq => g_jesd_freq
- )
- port map(
- jesd204b_refclk => jesd204b_refclk,
- jesd204b_sysref => jesd204b_sysref,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
- );
+ generic map(
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_nof_sync_n => g_nof_sync_n,
+ g_jesd_freq => g_jesd_freq
+ )
+ port map(
+ jesd204b_refclk => jesd204b_refclk,
+ jesd204b_sysref => jesd204b_sysref,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
+
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => jesd204b_serial_data(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
u_bsn_source : entity dp_lib.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_block_size => c_bs_block_size,
+ g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_bsn_w => c_bs_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ dp_pps => rx_sysref,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_bsn_source_mosi,
+ reg_miso => reg_bsn_source_miso,
+
+ -- Streaming clock domain
+ bs_sosi => bs_sosi
+ );
mux_sosi_arr <= rx_sosi_arr when rising_edge(rx_clk);
@@ -197,6 +198,7 @@ begin
-----------------------------------------------------------------------------
gen_concat : for I in 0 to g_nof_streams - 1 generate
+
p_sosi : process(mux_sosi_arr(I), bs_sosi)
begin
st_sosi_arr(I) <= bs_sosi;
@@ -215,73 +217,73 @@ begin
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => false
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
+ generic map (
+ g_nof_streams => 1, -- They're all the same
+ g_sync_timeout => g_bsn_sync_timeout,
+ g_bsn_w => c_bs_bsn_w,
+ g_log_first_bsn => false
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_input_mosi,
+ reg_miso => reg_bsn_monitor_input_miso,
+
+ -- Streaming clock domain
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+ in_sosi_arr => st_sosi_arr(0 downto 0)
+ );
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
+ -----------------------------------------------------------------------------
+ -- Diagnostic Data Buffer
-----------------------------------------------------------------------------
u_diag_data_buffer_bsn : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => g_buf_nof_data,
+ g_buf_use_sync => true -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+ in_sosi_arr => st_sosi_arr,
+ in_sync => st_sosi_arr(0).sync
+ );
-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : entity common_lib.common_reg_r_w
- generic map (
- g_reg => c_mm_jesd_ctrl_reg,
- g_init_reg => (others => '0')
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
- rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
- -- data side
- out_reg => mm_jesd_ctrl_reg,
- in_reg => mm_jesd_ctrl_reg
- );
+ generic map (
+ g_reg => c_mm_jesd_ctrl_reg,
+ g_init_reg => (others => '0')
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => jesd_ctrl_mosi.wr,
+ wr_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_en => jesd_ctrl_mosi.rd,
+ rd_adr => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w - 1 downto 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
+ -- data side
+ out_reg => mm_jesd_ctrl_reg,
+ in_reg => mm_jesd_ctrl_reg
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index ee430f809c65a58a0eec86b38732fef2f3d243ea..de55ca0b1f2e0d6780313f129192c5321a5a3a95 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -20,448 +20,447 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package qsys_unb2c_test_pkg is
- component qsys_unb2c_test is
- port (
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_1_reset_export : out std_logic; -- export
- avs_eth_1_clk_export : out std_logic; -- export
- avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_tse_write_export : out std_logic; -- export
- avs_eth_1_tse_read_export : out std_logic; -- export
- avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_1_reg_write_export : out std_logic; -- export
- avs_eth_1_reg_read_export : out std_logic; -- export
- avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_1_ram_write_export : out std_logic; -- export
- avs_eth_1_ram_read_export : out std_logic; -- export
- avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_1_irq_export : in std_logic := 'X'; -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_10gbe_reset_export : out std_logic; -- export
- ram_diag_bg_10gbe_clk_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_10gbe_read_export : out std_logic; -- export
- ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
- ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
- reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_10gbe_reset_export : out std_logic; -- export
- reg_diag_bg_10gbe_clk_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_10gbe_read_export : out std_logic; -- export
- reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_0_reset_export : out std_logic; -- export
- reg_diag_bg_eth_0_clk_export : out std_logic; -- export
- reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_bg_eth_0_write_export : out std_logic; -- export
- reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_0_read_export : out std_logic; -- export
- reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_eth_1_reset_export : out std_logic; -- export
- reg_diag_bg_eth_1_clk_export : out std_logic; -- export
- reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_eth_1_write_export : out std_logic; -- export
- reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_eth_1_read_export : out std_logic; -- export
- reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
- reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
- reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
- reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
- reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
- reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back0_reset_export : out std_logic; -- export
- reg_eth10g_back0_clk_export : out std_logic; -- export
- reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back0_write_export : out std_logic; -- export
- reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back0_read_export : out std_logic; -- export
- reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_back1_reset_export : out std_logic; -- export
- reg_eth10g_back1_clk_export : out std_logic; -- export
- reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
- reg_eth10g_back1_write_export : out std_logic; -- export
- reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_back1_read_export : out std_logic; -- export
- reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
- reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
- reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_hdr_dat_eth_1_write_export : out std_logic; -- export
- reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_1_read_export : out std_logic; -- export
- reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
- reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
- reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_eth_0_write_export : out std_logic; -- export
- reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_eth_0_read_export : out std_logic; -- export
- reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
- reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_heater_reset_export : out std_logic; -- export
- reg_heater_clk_export : out std_logic; -- export
- reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
- reg_heater_write_export : out std_logic; -- export
- reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_heater_read_export : out std_logic; -- export
- reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_i_reset_export : out std_logic; -- export
- reg_io_ddr_mb_i_clk_export : out std_logic; -- export
- reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_i_write_export : out std_logic; -- export
- reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_i_read_export : out std_logic; -- export
- reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
- reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
- reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
- reg_io_ddr_mb_ii_write_export : out std_logic; -- export
- reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_io_ddr_mb_ii_read_export : out std_logic; -- export
- reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_reset_export : out std_logic; -- export
- reg_tr_10gbe_back0_clk_export : out std_logic; -- export
- reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back0_write_export : out std_logic; -- export
- reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back0_read_export : out std_logic; -- export
- reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_back1_reset_export : out std_logic; -- export
- reg_tr_10gbe_back1_clk_export : out std_logic; -- export
- reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
- reg_tr_10gbe_back1_write_export : out std_logic; -- export
- reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_back1_read_export : out std_logic; -- export
- reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
- reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
- reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component qsys_unb2c_test;
-
+ component qsys_unb2c_test is
+ port (
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_1_reset_export : out std_logic; -- export
+ avs_eth_1_clk_export : out std_logic; -- export
+ avs_eth_1_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_tse_write_export : out std_logic; -- export
+ avs_eth_1_tse_read_export : out std_logic; -- export
+ avs_eth_1_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_1_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_1_reg_write_export : out std_logic; -- export
+ avs_eth_1_reg_read_export : out std_logic; -- export
+ avs_eth_1_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_1_ram_write_export : out std_logic; -- export
+ avs_eth_1_ram_read_export : out std_logic; -- export
+ avs_eth_1_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_1_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_1_irq_export : in std_logic := 'X'; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_diag_bg_10gbe_reset_export : out std_logic; -- export
+ ram_diag_bg_10gbe_clk_export : out std_logic; -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_bg_10gbe_write_export : out std_logic; -- export
+ ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_10gbe_read_export : out std_logic; -- export
+ ram_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_address_export : out std_logic_vector(16 downto 0); -- export
+ ram_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ ram_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(10 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ ram_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(10 downto 0); -- export
+ reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
+ reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_reset_export : out std_logic; -- export
+ reg_bsn_source_clk_export : out std_logic; -- export
+ reg_bsn_source_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bsn_source_write_export : out std_logic; -- export
+ reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_read_export : out std_logic; -- export
+ reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_10gbe_reset_export : out std_logic; -- export
+ reg_diag_bg_10gbe_clk_export : out std_logic; -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_10gbe_write_export : out std_logic; -- export
+ reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_10gbe_read_export : out std_logic; -- export
+ reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_0_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_0_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_eth_0_write_export : out std_logic; -- export
+ reg_diag_bg_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_0_read_export : out std_logic; -- export
+ reg_diag_bg_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_eth_1_reset_export : out std_logic; -- export
+ reg_diag_bg_eth_1_clk_export : out std_logic; -- export
+ reg_diag_bg_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_eth_1_write_export : out std_logic; -- export
+ reg_diag_bg_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_eth_1_read_export : out std_logic; -- export
+ reg_diag_bg_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_10gbe_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_diag_data_buffer_10gbe_write_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_10gbe_read_export : out std_logic; -- export
+ reg_diag_data_buffer_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(11 downto 0); -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_data_buffer_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_rx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_rx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_rx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_rx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_rx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_10gbe_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_diag_tx_seq_10gbe_write_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_10gbe_read_export : out std_logic; -- export
+ reg_diag_tx_seq_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_i_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_tx_seq_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_tx_seq_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_diag_tx_seq_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back0_reset_export : out std_logic; -- export
+ reg_eth10g_back0_clk_export : out std_logic; -- export
+ reg_eth10g_back0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back0_write_export : out std_logic; -- export
+ reg_eth10g_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back0_read_export : out std_logic; -- export
+ reg_eth10g_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_back1_reset_export : out std_logic; -- export
+ reg_eth10g_back1_clk_export : out std_logic; -- export
+ reg_eth10g_back1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_eth10g_back1_write_export : out std_logic; -- export
+ reg_eth10g_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_back1_read_export : out std_logic; -- export
+ reg_eth10g_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_eth10g_qsfp_ring_reset_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_clk_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_eth10g_qsfp_ring_write_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_eth10g_qsfp_ring_read_export : out std_logic; -- export
+ reg_eth10g_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_1_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_1_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_1_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_hdr_dat_eth_1_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_1_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_1_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_1_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_eth_0_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_eth_0_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_eth_0_reset_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_clk_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_eth_0_write_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_eth_0_read_export : out std_logic; -- export
+ reg_hdr_dat_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_rx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_rx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_rx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_strobe_total_count_tx_eth_0_reset_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_clk_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_write_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_strobe_total_count_tx_eth_0_read_export : out std_logic; -- export
+ reg_strobe_total_count_tx_eth_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_heater_reset_export : out std_logic; -- export
+ reg_heater_clk_export : out std_logic; -- export
+ reg_heater_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_heater_write_export : out std_logic; -- export
+ reg_heater_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_heater_read_export : out std_logic; -- export
+ reg_heater_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_i_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_i_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_i_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_i_write_export : out std_logic; -- export
+ reg_io_ddr_mb_i_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_i_read_export : out std_logic; -- export
+ reg_io_ddr_mb_i_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_io_ddr_mb_ii_reset_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_clk_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_address_export : out std_logic_vector(15 downto 0); -- export
+ reg_io_ddr_mb_ii_write_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_mb_ii_read_export : out std_logic; -- export
+ reg_io_ddr_mb_ii_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back0_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back0_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back0_write_export : out std_logic; -- export
+ reg_tr_10gbe_back0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back0_read_export : out std_logic; -- export
+ reg_tr_10gbe_back0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back0_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_back1_reset_export : out std_logic; -- export
+ reg_tr_10gbe_back1_clk_export : out std_logic; -- export
+ reg_tr_10gbe_back1_address_export : out std_logic_vector(17 downto 0); -- export
+ reg_tr_10gbe_back1_write_export : out std_logic; -- export
+ reg_tr_10gbe_back1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_back1_read_export : out std_logic; -- export
+ reg_tr_10gbe_back1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_back1_waitrequest_export : in std_logic := 'X'; -- export
+ reg_tr_10gbe_qsfp_ring_reset_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_clk_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_address_export : out std_logic_vector(18 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_write_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_qsfp_ring_read_export : out std_logic; -- export
+ reg_tr_10gbe_qsfp_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_qsfp_ring_waitrequest_export : in std_logic := 'X'; -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
+ );
+ end component qsys_unb2c_test;
end qsys_unb2c_test_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index bb282b576aae33d6e609ccf03ed4bdd039a75566..555d7e198d97141a1b3ca0ff2f06cd7708a505c8 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -21,19 +21,19 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, unb2c_board_lib, dp_lib, eth_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use work.unb2c_test_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use technology_lib.technology_pkg.all;
entity udp_stream is
generic (
@@ -102,14 +102,15 @@ end udp_stream;
architecture str of udp_stream is
-- Block generator
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
- '0', -- enable_sync
- TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable (disabled by default)
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( g_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( g_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -150,127 +151,127 @@ begin
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
u_mms_diag_block_gen: entity diag_lib.mms_diag_block_gen
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => g_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_index_arr => array_init(0, g_nof_streams),
- g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
--- g_use_tx_seq => TRUE
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_miso
- );
-
- gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
- u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => 47,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_size => 50
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => g_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_index_arr => array_init(0, g_nof_streams),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(g_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ -- g_use_tx_seq => TRUE
)
port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink (from BG)
- snk_out => block_gen_src_in_arr(i),
- snk_in => block_gen_src_out_arr(i),
- -- ST source (to tx_offload)
- src_in => fifo_block_gen_src_in_arr(i),
- src_out => fifo_block_gen_src_out_arr(i)
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ reg_tx_seq_mosi => reg_diag_tx_seq_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_miso
);
+
+ gen_dp_fifo_sc : for i in 0 to g_nof_streams - 1 generate -- FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
+ u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => 47,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_size => 50
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink (from BG)
+ snk_out => block_gen_src_in_arr(i),
+ snk_in => block_gen_src_out_arr(i),
+ -- ST source (to tx_offload)
+ src_in => fifo_block_gen_src_in_arr(i),
+ src_out => fifo_block_gen_src_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_use_complex => false,
--- g_max_nof_words_per_block => c_max_nof_words_per_block,
- g_nof_words_per_block => g_def_block_size,
--- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
- g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM
- --reg_mosi => reg_dp_offload_tx_mosi,
- --reg_miso => reg_dp_offload_tx_miso,
- --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- -- from blockgen-fifo
- snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
- snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
-
- -- output to MAC
- src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
- src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
-
- hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_use_complex => false,
+ -- g_max_nof_words_per_block => c_max_nof_words_per_block,
+ g_nof_words_per_block => g_def_block_size,
+ -- g_max_nof_blocks_per_packet => g_max_nof_blocks_per_packet,
+ g_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM
+ --reg_mosi => reg_dp_offload_tx_mosi,
+ --reg_miso => reg_dp_offload_tx_miso,
+ --reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ -- from blockgen-fifo
+ snk_in_arr => fifo_block_gen_src_out_arr(g_nof_streams - 1 downto 0),
+ snk_out_arr => fifo_block_gen_src_in_arr(g_nof_streams - 1 downto 0),
+
+ -- output to MAC
+ src_out_arr => dp_offload_tx_src_out_arr(g_nof_streams - 1 downto 0),
+ src_in_arr => dp_offload_tx_src_in_arr(g_nof_streams - 1 downto 0),
+
+ hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
+ );
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => g_remove_crc,
- g_crc_nof_words => c_nof_crc_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => g_remove_crc,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- -- from MAC
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- to databuffer
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
+ --reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ --reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
- hdr_fields_out_arr => hdr_fields_out_arr
- );
+ -- from MAC
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ -- to databuffer
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
@@ -291,52 +292,52 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
- g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
- in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_bg_blocks_per_sync * (g_bg_block_size + g_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(g_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(g_bg_blocks_per_sync * g_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ in_siso_arr => diag_data_buf_snk_out_arr(g_nof_streams - 1 downto 0),
+ in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => 32, -- g_data_w, --FIXME
- g_buf_nof_data => 1024,
- g_buf_use_sync => false, -- sync by reading last address of data buffer
- g_use_rx_seq => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sync,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_data_w => 32, -- g_data_w, --FIXME
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => false, -- sync by reading last address of data buffer
+ g_use_rx_seq => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ reg_rx_seq_mosi => reg_diag_rx_seq_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sync,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index bed4ac8d3e09c468888fe4d8288a4d33e182a43e..1d1ec51c4c0a68b6fdccd82ec0e819483da8a14a 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -21,22 +21,22 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, unb2c_board_lib, unb2c_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib, tech_ddr_lib, io_ddr_lib, tech_jesd204b_lib, util_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_interface_layers_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use diag_lib.diag_pkg.all;
-use eth_lib.eth_pkg.all;
-use eth_lib.eth_tester_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
-use work.unb2c_test_pkg.all;
-use util_lib.util_heater_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_interface_layers_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use eth_lib.eth_tester_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
+ use work.unb2c_test_pkg.all;
+ use util_lib.util_heater_pkg.all;
entity unb2c_test is
generic (
@@ -337,7 +337,7 @@ architecture str of unb2c_test is
signal serial_10G_tx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0) := (others => '0');
signal serial_10G_rx_back_arr : std_logic_vector(c_nof_streams_back0 - 1 downto 0);
--- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
+ -- SIGNAL serial_rx_jesd204b_back_arr : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
signal reg_10gbase_r_24_mosi : t_mem_mosi;
signal reg_10gbase_r_24_miso : t_mem_miso;
@@ -471,327 +471,327 @@ begin
-- General control function
-----------------------------------------------------------------------------
u_ctrl : entity unb2c_board_lib.ctrl_unb2c_board
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
- g_udp_offload => c_use_eth_0_UDP,
- g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- port map (
- -- Clock an reset signals
- cs_sim => cs_sim,
-
- ext_clk200 => ext_clk200,
- ext_rst200 => ext_rst200,
-
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- mb_I_ref_rst => mb_I_ref_rst,
- mb_II_ref_rst => mb_II_ref_rst,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth1g_mm_rst => eth_0_mm_rst,
- eth1g_tse_mosi => eth_0_tse_mosi,
- eth1g_tse_miso => eth_0_tse_miso,
- eth1g_reg_mosi => eth_0_reg_mosi,
- eth1g_reg_miso => eth_0_reg_miso,
- eth1g_reg_interrupt => eth_0_reg_interrupt,
- eth1g_ram_mosi => eth_0_ram_mosi,
- eth1g_ram_miso => eth_0_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
- udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
- udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
-
- -- scrap ram
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- . DDR reference clock domains reset creation
- MB_I_REF_CLK => MB_I_REF_CLK,
- MB_II_REF_CLK => MB_II_REF_CLK,
- -- . 1GbE Control Interface
- ETH_CLK => ETH_CLK(0),
- ETH_SGIN => ETH_SGIN(0),
- ETH_SGOUT => ETH_SGOUT(0)
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
+ g_udp_offload => c_use_eth_0_UDP,
+ g_udp_offload_nof_streams => c_nof_udp_streams_eth_0,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ port map (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+
+ ext_clk200 => ext_clk200,
+ ext_rst200 => ext_rst200,
+
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ mb_I_ref_rst => mb_I_ref_rst,
+ mb_II_ref_rst => mb_II_ref_rst,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth1g_mm_rst => eth_0_mm_rst,
+ eth1g_tse_mosi => eth_0_tse_mosi,
+ eth1g_tse_miso => eth_0_tse_miso,
+ eth1g_reg_mosi => eth_0_reg_mosi,
+ eth1g_reg_miso => eth_0_reg_miso,
+ eth1g_reg_interrupt => eth_0_reg_interrupt,
+ eth1g_ram_mosi => eth_0_ram_mosi,
+ eth1g_ram_miso => eth_0_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => eth_0_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth_0_udp_tx_siso_arr,
+ udp_rx_sosi_arr => eth_0_udp_rx_sosi_arr,
+ udp_rx_siso_arr => eth_0_udp_rx_siso_arr,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- . DDR reference clock domains reset creation
+ MB_I_REF_CLK => MB_I_REF_CLK,
+ MB_II_REF_CLK => MB_II_REF_CLK,
+ -- . 1GbE Control Interface
+ ETH_CLK => ETH_CLK(0),
+ ETH_SGIN => ETH_SGIN(0),
+ ETH_SGOUT => ETH_SGOUT(0)
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : entity work.mmm_unb2c_test
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_technology => g_technology,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr,
- g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
- g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
- g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
- )
- port map(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g ch0
- eth_0_mm_rst => eth_0_mm_rst,
- eth_0_tse_mosi => eth_0_tse_mosi,
- eth_0_tse_miso => eth_0_tse_miso,
- eth_0_reg_mosi => eth_0_reg_mosi,
- eth_0_reg_miso => eth_0_reg_miso,
- eth_0_reg_interrupt => eth_0_reg_interrupt,
- eth_0_ram_mosi => eth_0_ram_mosi,
- eth_0_ram_miso => eth_0_ram_miso,
-
- reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
- reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
-
- reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
-
- -- eth1g ch1
- eth_1_mm_rst => eth_1_mm_rst,
- eth_1_tse_mosi => eth_1_tse_mosi,
- eth_1_tse_miso => eth_1_tse_miso,
- eth_1_reg_mosi => OPEN,
- eth_1_reg_miso => c_mem_cipo_rst,
- eth_1_reg_interrupt => '0',
- eth_1_ram_mosi => OPEN,
- eth_1_ram_miso => c_mem_cipo_rst,
-
- reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
- reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
-
- reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- heater:
- reg_heater_mosi => reg_heater_mosi,
- reg_heater_miso => reg_heater_miso,
-
- -- block gen
- ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
- reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
- reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- bsn
- reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
-
- -- databuffer
- ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
-
- -- 10GbE
-
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
-
- reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
-
- reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
- reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
-
- -- eth10g status
- reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
-
- reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_back0_miso => reg_eth10g_back0_miso,
-
- -- DDR4 : MB I
- reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
- reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
- reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
- reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
- reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
- ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- -- DDR4 : MB II
- reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
- reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
- reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
- reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
- reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
- ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- -- Jesd reset control
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
-
- -- Scrap RAM
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_technology => g_technology,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_nof_streams_qsfp => c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w,
+ g_nof_streams_ring => c_unb2c_board_tr_ring.nof_bus * c_unb2c_board_tr_ring.bus_w,
+ g_nof_streams_back0 => c_unb2c_board_tr_back.bus_w
+ )
+ port map(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g ch0
+ eth_0_mm_rst => eth_0_mm_rst,
+ eth_0_tse_mosi => eth_0_tse_mosi,
+ eth_0_tse_miso => eth_0_tse_miso,
+ eth_0_reg_mosi => eth_0_reg_mosi,
+ eth_0_reg_miso => eth_0_reg_miso,
+ eth_0_reg_interrupt => eth_0_reg_interrupt,
+ eth_0_ram_mosi => eth_0_ram_mosi,
+ eth_0_ram_miso => eth_0_ram_miso,
+
+ reg_diag_bg_eth_0_copi => reg_diag_bg_eth_0_copi,
+ reg_diag_bg_eth_0_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_eth_0_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_eth_0_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_eth_0_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_eth_0_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_eth_0_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_eth_0_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_0_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_eth_0_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_eth_0_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_eth_0_cipo => reg_strobe_total_count_rx_eth_0_cipo,
+
+ -- eth1g ch1
+ eth_1_mm_rst => eth_1_mm_rst,
+ eth_1_tse_mosi => eth_1_tse_mosi,
+ eth_1_tse_miso => eth_1_tse_miso,
+ eth_1_reg_mosi => OPEN,
+ eth_1_reg_miso => c_mem_cipo_rst,
+ eth_1_reg_interrupt => '0',
+ eth_1_ram_mosi => OPEN,
+ eth_1_ram_miso => c_mem_cipo_rst,
+
+ reg_diag_bg_eth_1_copi => reg_diag_bg_eth_1_copi,
+ reg_diag_bg_eth_1_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_eth_1_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_eth_1_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_eth_1_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_eth_1_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_eth_1_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_eth_1_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+
+ reg_bsn_monitor_v2_rx_eth_1_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_eth_1_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_eth_1_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_eth_1_cipo => reg_strobe_total_count_rx_eth_1_cipo,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- heater:
+ reg_heater_mosi => reg_heater_mosi,
+ reg_heater_miso => reg_heater_miso,
+
+ -- block gen
+ ram_diag_bg_10GbE_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_10GbE_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_bg_10GbE_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_10GbE_miso => reg_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_10GbE_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_10GbE_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- bsn
+ reg_bsn_monitor_10GbE_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_10GbE_miso => reg_bsn_monitor_10GbE_miso,
+
+ -- databuffer
+ ram_diag_data_buf_10GbE_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_10GbE_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_data_buf_10GbE_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_10GbE_miso => reg_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_10GbE_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_10GbE_miso => reg_diag_rx_seq_10GbE_miso,
+
+ -- 10GbE
+
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+
+ reg_tr_10GbE_qsfp_ring_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_tr_10GbE_qsfp_ring_miso => reg_tr_10GbE_qsfp_ring_miso,
+
+ reg_tr_10GbE_back0_mosi => reg_tr_10GbE_back0_mosi,
+ reg_tr_10GbE_back0_miso => reg_tr_10GbE_back0_miso,
+
+ -- eth10g status
+ reg_eth10g_qsfp_ring_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_qsfp_ring_miso => reg_eth10g_qsfp_ring_miso,
+
+ reg_eth10g_back0_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_back0_miso => reg_eth10g_back0_miso,
+
+ -- DDR4 : MB I
+ reg_io_ddr_MB_I_mosi => reg_io_ddr_MB_I_mosi,
+ reg_io_ddr_MB_I_miso => reg_io_ddr_MB_I_miso,
+ reg_diag_tx_seq_ddr_MB_I_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_diag_tx_seq_ddr_MB_I_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+ reg_diag_rx_seq_ddr_MB_I_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_diag_rx_seq_ddr_MB_I_miso => reg_diag_rx_seq_ddr_MB_I_miso,
+ reg_diag_data_buf_ddr_MB_I_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_diag_data_buf_ddr_MB_I_miso => reg_diag_data_buf_ddr_MB_I_miso,
+ ram_diag_data_buf_ddr_MB_I_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_diag_data_buf_ddr_MB_I_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ -- DDR4 : MB II
+ reg_io_ddr_MB_II_mosi => reg_io_ddr_MB_II_mosi,
+ reg_io_ddr_MB_II_miso => reg_io_ddr_MB_II_miso,
+ reg_diag_tx_seq_ddr_MB_II_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_diag_tx_seq_ddr_MB_II_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+ reg_diag_rx_seq_ddr_MB_II_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_diag_rx_seq_ddr_MB_II_miso => reg_diag_rx_seq_ddr_MB_II_miso,
+ reg_diag_data_buf_ddr_MB_II_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_diag_data_buf_ddr_MB_II_miso => reg_diag_data_buf_ddr_MB_II_miso,
+ ram_diag_data_buf_ddr_MB_II_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ -- Jesd reset control
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd ip status/control
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
gen_eth_0_udp : if c_use_eth_0_UDP = true generate
-- Derive MAC/IP/UDP from gn_index
@@ -801,48 +801,48 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_I : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_0,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_I,
- ip_src_addr => gn_ip_src_addr_I,
- udp_src_port => gn_udp_src_port_I,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_0,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_I,
+ ip_src_addr => gn_ip_src_addr_I,
+ udp_src_port => gn_udp_src_port_I,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_0_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_0_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_0_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_0_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_0_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_0_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_0_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_0_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_0_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_0_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_0_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_0_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_0_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_0_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_0_cipo
+ );
-- Uses eth.vhd with ETH/TSE interface with UDP streams in ctrl_unb2c_board
-- to stream UDP data via eth_0 = 1GbE-I.
@@ -858,218 +858,218 @@ begin
-- Generate UDP Tx and monitor UDP Rx
u_eth_tester_II : entity eth_lib.eth_tester
- generic map (
- g_nof_streams => c_nof_udp_streams_eth_1,
- g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
- g_remove_crc => true -- use TRUE when using TSE link interface
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
- st_pps => dp_pps,
-
- -- UDP transmit interface
- eth_src_mac => gn_eth_src_mac_II,
- ip_src_addr => gn_ip_src_addr_II,
- udp_src_port => gn_udp_src_port_II,
-
- tx_fifo_rd_emp_arr => OPEN,
-
- tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
- tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
-
- -- UDP receive interface
- rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves (one per stream)
- -- . Tx
- reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
- reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
- reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
- reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
- reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
- reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
- reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
- reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
- -- . Rx
- reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
- reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
- reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
- reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
- );
+ generic map (
+ g_nof_streams => c_nof_udp_streams_eth_1,
+ g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
+ g_remove_crc => true -- use TRUE when using TSE link interface
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+ st_pps => dp_pps,
+
+ -- UDP transmit interface
+ eth_src_mac => gn_eth_src_mac_II,
+ ip_src_addr => gn_ip_src_addr_II,
+ udp_src_port => gn_udp_src_port_II,
+
+ tx_fifo_rd_emp_arr => OPEN,
+
+ tx_udp_sosi_arr => eth_1_udp_tx_sosi_arr,
+ tx_udp_siso_arr => eth_1_udp_tx_siso_arr,
+
+ -- UDP receive interface
+ rx_udp_sosi_arr => eth_1_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves (one per stream)
+ -- . Tx
+ reg_bg_ctrl_copi => reg_diag_bg_eth_1_copi,
+ reg_bg_ctrl_cipo => reg_diag_bg_eth_1_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_eth_1_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_eth_1_cipo,
+ reg_bsn_monitor_v2_tx_copi => reg_bsn_monitor_v2_tx_eth_1_copi,
+ reg_bsn_monitor_v2_tx_cipo => reg_bsn_monitor_v2_tx_eth_1_cipo,
+ reg_strobe_total_count_tx_copi => reg_strobe_total_count_tx_eth_1_copi,
+ reg_strobe_total_count_tx_cipo => reg_strobe_total_count_tx_eth_1_cipo,
+ -- . Rx
+ reg_bsn_monitor_v2_rx_copi => reg_bsn_monitor_v2_rx_eth_1_copi,
+ reg_bsn_monitor_v2_rx_cipo => reg_bsn_monitor_v2_rx_eth_1_cipo,
+ reg_strobe_total_count_rx_copi => reg_strobe_total_count_rx_eth_1_copi,
+ reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_eth_1_cipo
+ );
-- Use eth_stream with ETH/TSE interface for UDP port g_rx_udp_port to
-- stream UDP data via eth_1 = 1GbE-II
u_eth_stream : entity eth_lib.eth_stream
- generic map (
- g_technology => g_technology,
- g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
- g_jumbo_en => true,
- g_sim => g_sim,
- g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst, -- eth_1_mm_rst
- mm_clk => mm_clk,
- eth_clk => ETH_CLK(1),
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- TSE setup
- src_mac => gn_eth_src_mac_II,
- setup_done => OPEN,
-
- -- UDP transmit interface
- udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
- udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
-
- -- UDP receive interface
- udp_rx_src_in => c_dp_siso_rdy,
- udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
-
- -- Memory Mapped Slaves
- tse_ctlr_copi => eth_1_tse_mosi,
- tse_ctlr_cipo => eth_1_tse_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT(1),
- eth_rxp => ETH_SGIN(1),
-
- -- LED interface
- tse_led => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_rx_udp_port => TO_UINT(c_eth_rx_udp_port), -- = 0x1771 = 6001
+ g_jumbo_en => true,
+ g_sim => g_sim,
+ g_sim_level => 1 -- 0 = use IP model (equivalent to g_sim = FALSE); 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst, -- eth_1_mm_rst
+ mm_clk => mm_clk,
+ eth_clk => ETH_CLK(1),
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- TSE setup
+ src_mac => gn_eth_src_mac_II,
+ setup_done => OPEN,
+
+ -- UDP transmit interface
+ udp_tx_snk_in => eth_1_udp_tx_sosi_arr(0),
+ udp_tx_snk_out => eth_1_udp_tx_siso_arr(0),
+
+ -- UDP receive interface
+ udp_rx_src_in => c_dp_siso_rdy,
+ udp_rx_src_out => eth_1_udp_rx_sosi_arr(0),
+
+ -- Memory Mapped Slaves
+ tse_ctlr_copi => eth_1_tse_mosi,
+ tse_ctlr_cipo => eth_1_tse_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT(1),
+ eth_rxp => ETH_SGIN(1),
+
+ -- LED interface
+ tse_led => open
+ );
end generate;
gen_udp_stream_10GbE : if c_use_10GbE = true and c_use_loopback = false generate
u_udp_stream_10GbE : entity work.udp_stream
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
- g_data_w => c_data_w_64,
- g_bg_block_size => c_bg_block_size,
- g_bg_gapsize => c_bg_gapsize_10GbE,
- g_bg_blocks_per_sync => c_bg_blocks_per_sync,
- g_def_block_size => c_def_10GbE_block_size,
- g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
- g_remove_crc => false
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ID => ID,
- -- blockgen MM
- reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
- reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
- ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
- ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
- reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
- reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
- -- loopback:
- --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
- --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
- --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
-
- -- connect to dp_offload:
- dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
- dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
- dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
- dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
-
- reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
- ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
- reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
- reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0,
+ g_data_w => c_data_w_64,
+ g_bg_block_size => c_bg_block_size,
+ g_bg_gapsize => c_bg_gapsize_10GbE,
+ g_bg_blocks_per_sync => c_bg_blocks_per_sync,
+ g_def_block_size => c_def_10GbE_block_size,
+ g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,
+ g_remove_crc => false
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ID => ID,
+ -- blockgen MM
+ reg_diag_bg_mosi => reg_diag_bg_10GbE_mosi,
+ reg_diag_bg_miso => reg_diag_bg_10GbE_miso,
+ ram_diag_bg_mosi => ram_diag_bg_10GbE_mosi,
+ ram_diag_bg_miso => ram_diag_bg_10GbE_miso,
+ reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
+ reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
+
+ -- loopback:
+ --dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ --dp_offload_rx_snk_in_arr => dp_offload_tx_10GbE_src_out_arr,
+ --dp_offload_rx_snk_out_arr => dp_offload_tx_10GbE_src_in_arr,
+
+ -- connect to dp_offload:
+ dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
+ dp_offload_tx_src_in_arr => dp_offload_tx_10GbE_src_in_arr,
+ dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
+ dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
+
+ reg_diag_data_buf_mosi => reg_diag_data_buf_10GbE_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_10GbE_miso,
+ ram_diag_data_buf_mosi => ram_diag_data_buf_10GbE_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_10GbE_miso,
+ reg_diag_rx_seq_mosi => reg_diag_rx_seq_10GbE_mosi,
+ reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
+ );
end generate;
gen_jesd204b : if c_use_jesd204b = true generate
u_jesd204b: entity work.node_adc_input_and_timing_nowg
- generic map(
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_jesd204b,
- g_jesd_freq => "200MHz",
- g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
- g_sim => g_sim
- )
- port map(
- -- clocks and resets
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- -- mm control buses
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
-
- -- Jesd external IOs
- jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
- jesd204b_refclk => BCK_REF_CLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n => JESD204B_SYNC
- );
+ generic map(
+ g_technology => g_technology,
+ g_nof_streams => c_nof_streams_jesd204b,
+ g_jesd_freq => "200MHz",
+ g_nof_sync_n => c_unb2c_board_nof_sync_jesd204b,
+ g_sim => g_sim
+ )
+ port map(
+ -- clocks and resets
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ -- mm control buses
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+ reg_bsn_source_mosi => reg_bsn_source_mosi,
+ reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
+ jesd_ctrl_mosi => jesd_ctrl_mosi,
+ jesd_ctrl_miso => jesd_ctrl_miso,
+
+ -- Jesd external IOs
+ jesd204b_serial_data => BCK_RX(c_nof_streams_jesd204b - 1 downto 0),
+ jesd204b_refclk => BCK_REF_CLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n => JESD204B_SYNC
+ );
end generate;
gen_front_10GbE : if c_use_10GbE = true generate
u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- QSFP and Ring lines
- generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
- )
- port map (
- tr_ref_clk => SA_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
- reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
- reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
- reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
- --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
- --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SA_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_qsfp_ring_mosi,
+ reg_mac_miso => reg_tr_10GbE_qsfp_ring_miso,
+ reg_eth10g_mosi => reg_eth10g_qsfp_ring_mosi,
+ reg_eth10g_miso => reg_eth10g_qsfp_ring_miso,
+ --reg_10gbase_r_24_mosi => reg_10gbase_r_24_mosi,
+ --reg_10gbase_r_24_miso => reg_10gbase_r_24_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp + c_nof_streams_ring - 1 downto 0),
- serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
- serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
- );
+ serial_tx_arr => i_serial_10G_tx_qsfp_ring_arr,
+ serial_rx_arr => i_serial_10G_rx_qsfp_ring_arr
+ );
gen_qsfp_wires: for i in 0 to c_nof_streams_qsfp - 1 generate
- serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
+ serial_10G_tx_qsfp_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i);
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
@@ -1088,24 +1088,24 @@ begin
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_qsfp_arr,
- serial_rx_arr => serial_10G_rx_qsfp_arr,
+ generic map (
+ g_nof_qsfp_bus => c_nof_qsfp_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_qsfp_arr,
+ serial_rx_arr => serial_10G_rx_qsfp_arr,
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0),
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
- QSFP_LED => QSFP_LED
- );
+ QSFP_LED => QSFP_LED
+ );
gen_ring_wires: for i in 0 to c_nof_streams_ring - 1 generate
- serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
+ serial_10G_tx_ring_arr(i) <= i_serial_10G_tx_qsfp_ring_arr(i + c_nof_streams_qsfp);
i_serial_10G_rx_qsfp_ring_arr(i + c_nof_streams_qsfp) <= serial_10G_rx_ring_arr(i);
end generate;
@@ -1115,140 +1115,141 @@ begin
RING_1_TX <= i_RING_TX(1);
u_ring_io : entity unb2c_board_lib.unb2c_board_ring_io
- generic map (
- g_nof_ring_bus => 2 -- c_nof_ring_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_ring_arr,
- serial_rx_arr => serial_10G_rx_ring_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
- );
-
- gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
- u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
generic map (
- g_sim => g_sim,
- g_sim_level => 1,
- g_technology => g_technology,
- g_use_loopback => c_use_loopback,
- g_nof_macs => c_nof_streams_back0,
- g_tx_fifo_fill => c_def_10GbE_block_size,
- g_tx_fifo_size => c_def_10GbE_block_size * 2
+ g_nof_ring_bus => 2 -- c_nof_ring_bus
)
port map (
- tr_ref_clk => SB_CLK,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mac_mosi => reg_tr_10GbE_back0_mosi,
- reg_mac_miso => reg_tr_10GbE_back0_miso,
- reg_eth10g_mosi => reg_eth10g_back0_mosi,
- reg_eth10g_miso => reg_eth10g_back0_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
- serial_tx_arr => i_serial_10G_tx_back0_arr,
- serial_rx_arr => i_serial_10G_rx_back0_arr
+ serial_tx_arr => serial_10G_tx_ring_arr,
+ serial_rx_arr => serial_10G_rx_ring_arr,
+ RING_RX => i_RING_RX,
+ RING_TX => i_RING_TX
);
+
+ gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
+ u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
+ generic map (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_technology => g_technology,
+ g_use_loopback => c_use_loopback,
+ g_nof_macs => c_nof_streams_back0,
+ g_tx_fifo_fill => c_def_10GbE_block_size,
+ g_tx_fifo_size => c_def_10GbE_block_size * 2
+ )
+ port map (
+ tr_ref_clk => SB_CLK,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mac_mosi => reg_tr_10GbE_back0_mosi,
+ reg_mac_miso => reg_tr_10GbE_back0_miso,
+ reg_eth10g_mosi => reg_eth10g_back0_mosi,
+ reg_eth10g_miso => reg_eth10g_back0_miso,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ src_in_arr => dp_offload_rx_10GbE_snk_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_out_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ snk_in_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0 + c_nof_streams_qsfp + c_nof_streams_ring - 1 downto c_nof_streams_qsfp + c_nof_streams_ring),
+ serial_tx_arr => i_serial_10G_tx_back0_arr,
+ serial_rx_arr => i_serial_10G_rx_back0_arr
+ );
end generate;
gen_back_wiring : if c_use_10GbE_back0 = true generate
+
gen_back0_wires: for i in 0 to c_nof_streams_back0 - 1 generate
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
i_serial_10G_rx_back0_arr(i) <= serial_10G_rx_back_arr(i);
end generate;
u_back_io : entity unb2c_board_lib.unb2c_board_back_io
- generic map (
- g_nof_back_bus => c_nof_back_bus
- )
- port map (
- serial_tx_arr => serial_10G_tx_back_arr,
- serial_rx_arr => serial_10G_rx_back_arr,
-
- -- Serial I/O
- -- back transceivers
- BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
- BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
- );
+ generic map (
+ g_nof_back_bus => c_nof_back_bus
+ )
+ port map (
+ serial_tx_arr => serial_10G_tx_back_arr,
+ serial_rx_arr => serial_10G_rx_back_arr,
+
+ -- Serial I/O
+ -- back transceivers
+ BCK_RX(0) => BCK_RX(c_nof_streams_back0 - 1 downto 0),
+ BCK_TX(0) => BCK_TX(c_nof_streams_back0 - 1 downto 0)
+ );
end generate;
--- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
--- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
--- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
--- END GENERATE;
---
--- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
--- GENERIC MAP (
--- g_nof_back_bus => 1
--- )
--- PORT MAP (
--- --serial_tx_arr => serial_10G_tx_back_arr,
--- serial_rx_arr => serial_rx_jesd204b_back_arr,
---
--- -- Serial I/O
--- -- back transceivers
--- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
--- BCK_TX(0) => open
--- );
--- END GENERATE;
+ -- gen_jesd204b_wiring : IF c_use_jesd204b = TRUE GENERATE
+ -- gen_jesd204b_wires: FOR i IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+ -- serial_rx_jesd204b_arr(i) <= serial_rx_jesd204b_back_arr(i);
+ -- END GENERATE;
+ --
+ -- u_back_io : ENTITY unb2c_board_lib.unb2c_board_back_io
+ -- GENERIC MAP (
+ -- g_nof_back_bus => 1
+ -- )
+ -- PORT MAP (
+ -- --serial_tx_arr => serial_10G_tx_back_arr,
+ -- serial_rx_arr => serial_rx_jesd204b_back_arr,
+ --
+ -- -- Serial I/O
+ -- -- back transceivers
+ -- BCK_RX(0) => BCK_RX(c_nof_streams_jesd204b-1 downto 0),
+ -- BCK_TX(0) => open
+ -- );
+ -- END GENERATE;
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_nof_qsfp_bus,
- g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_nof_qsfp_bus,
+ g_pulse_us => 1000 / (10**9 / c_unb2c_board_ext_clk_freq_200M) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_ring-1 DOWNTO 0),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_ring-1 DOWNTO 0),
- --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
+ --rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_back0+c_nof_streams_qsfp+c_nof_streams_ring-1 DOWNTO c_nof_streams_qsfp+c_nof_streams_ring),
- tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
- tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
- rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_siso_arr => dp_offload_tx_10GbE_src_in_arr(c_nof_streams_qsfp - 1 downto 0),
+ tx_sosi_arr => dp_offload_tx_10GbE_src_out_arr(c_nof_streams_qsfp - 1 downto 0),
+ rx_sosi_arr => dp_offload_rx_10GbE_snk_in_arr(c_nof_streams_qsfp - 1 downto 0),
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
- );
+ green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus - 1 downto 0),
+ red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus - 1 downto 0)
+ );
end generate;
gen_no_udp_stream_10GbE : if c_use_10GbE = false generate
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
- generic map (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- port map (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
+ generic map (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ port map (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
- generic map (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
+ generic map (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
end generate;
-----------------------------------------------------------------------------
@@ -1259,183 +1260,182 @@ begin
gen_stream_MB_I : if c_use_MB_I = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_I,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_I,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_I_REF_CLK,
- ctlr_ref_rst => mb_I_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_I_clk200,
- ctlr_rst_out => ddr_I_rst200,
-
- ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_I_IN,
- phy4_io => MB_I_IO,
- phy4_ou => MB_I_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_I_REF_CLK,
+ ctlr_ref_rst => mb_I_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_I_clk200,
+ ctlr_rst_out => ddr_I_rst200,
+
+ ctlr_clk_in => ddr_I_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_I_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_I_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_I_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_I_IN,
+ phy4_io => MB_I_IO,
+ phy4_ou => MB_I_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_I_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_I_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_I_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_I_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_I_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_I_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_I_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_I_miso
+ );
end generate;
gen_stream_MB_II : if c_use_MB_II = true generate
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
- generic map (
- -- System
- g_sim_model_ddr => g_sim_model_ddr,
- g_technology => g_technology,
+ generic map (
+ -- System
+ g_sim_model_ddr => g_sim_model_ddr,
+ g_technology => g_technology,
- g_dp_data_w => c_ddr_dp_data_w,
- g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
- g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
- g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
+ g_dp_data_w => c_ddr_dp_data_w,
+ g_dp_seq_dat_w => c_ddr_dp_seq_dat_w,
+ g_dp_wr_fifo_depth => c_ddr_dp_wr_fifo_depth,
+ g_dp_rd_fifo_depth => c_ddr_dp_rd_fifo_depth,
- -- IO_DDR
- g_io_tech_ddr => c_ddr_MB_II,
+ -- IO_DDR
+ g_io_tech_ddr => c_ddr_MB_II,
- -- DIAG data buffer
- g_db_use_db => false,
- g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
- )
- port map (
- ---------------------------------------------------------------------------
- -- System
- ---------------------------------------------------------------------------
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
-
- ---------------------------------------------------------------------------
- -- IO_DDR
- ---------------------------------------------------------------------------
- -- DDR reference clock
- ctlr_ref_clk => MB_II_REF_CLK,
- ctlr_ref_rst => mb_II_ref_rst,
-
- -- DDR controller clock domain
- ctlr_clk_out => ddr_II_clk200,
- ctlr_rst_out => ddr_II_rst200,
-
- ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
- ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
-
- -- MM interface
- reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
- reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
-
- -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
- wr_fifo_usedw => OPEN,
- rd_fifo_usedw => OPEN,
-
- -- DDR4 PHY external interface
- phy4_in => MB_II_IN,
- phy4_io => MB_II_IO,
- phy4_ou => MB_II_OU,
-
- ---------------------------------------------------------------------------
- -- DIAG Tx seq
- ---------------------------------------------------------------------------
- -- MM interface
- reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
- reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
-
- ---------------------------------------------------------------------------
- -- DIAG rx seq with optional data buffer
- ---------------------------------------------------------------------------
- -- MM interface
- reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
- reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
-
- ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
- ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
-
- reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
- reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
- );
+ -- DIAG data buffer
+ g_db_use_db => false,
+ g_db_buf_nof_data => c_ddr_db_buf_nof_data -- nof words per data buffer
+ )
+ port map (
+ ---------------------------------------------------------------------------
+ -- System
+ ---------------------------------------------------------------------------
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk, -- use alternative external clock or externally connect to ctlr_clk_out
+
+ ---------------------------------------------------------------------------
+ -- IO_DDR
+ ---------------------------------------------------------------------------
+ -- DDR reference clock
+ ctlr_ref_clk => MB_II_REF_CLK,
+ ctlr_ref_rst => mb_II_ref_rst,
+
+ -- DDR controller clock domain
+ ctlr_clk_out => ddr_II_clk200,
+ ctlr_rst_out => ddr_II_rst200,
+
+ ctlr_clk_in => ddr_II_clk200, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
+ ctlr_rst_in => ddr_II_rst200, -- connect ctlr_rst_out to ctlr_rst_in at top level
+
+ -- MM interface
+ reg_io_ddr_mosi => reg_io_ddr_MB_II_mosi, -- register for DDR controller status info
+ reg_io_ddr_miso => reg_io_ddr_MB_II_miso,
+
+ -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
+ wr_fifo_usedw => OPEN,
+ rd_fifo_usedw => OPEN,
+
+ -- DDR4 PHY external interface
+ phy4_in => MB_II_IN,
+ phy4_io => MB_II_IO,
+ phy4_ou => MB_II_OU,
+
+ ---------------------------------------------------------------------------
+ -- DIAG Tx seq
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_tx_seq_mosi => reg_diag_tx_seq_ddr_MB_II_mosi,
+ reg_tx_seq_miso => reg_diag_tx_seq_ddr_MB_II_miso,
+
+ ---------------------------------------------------------------------------
+ -- DIAG rx seq with optional data buffer
+ ---------------------------------------------------------------------------
+ -- MM interface
+ reg_data_buf_mosi => reg_diag_data_buf_ddr_MB_II_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_ddr_MB_II_miso,
+
+ ram_data_buf_mosi => ram_diag_data_buf_ddr_MB_II_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_ddr_MB_II_miso,
+
+ reg_rx_seq_mosi => reg_diag_rx_seq_ddr_MB_II_mosi,
+ reg_rx_seq_miso => reg_diag_rx_seq_ddr_MB_II_miso
+ );
end generate;
gen_heater : if c_use_heater = true generate
u_heater : entity util_lib.util_heater
- generic map (
- g_technology => g_technology,
- --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
- --g_nof_mac4 => 630 --
+ generic map (
+ g_technology => g_technology,
+ --g_nof_mac4 => 315 -- on Arria10 using 630 of 1518 DSP blocks
+ --g_nof_mac4 => 630 --
- --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
- g_nof_mac4 => 750,
+ --g_nof_mac4 => 736, -- max 736, 23 registers * 32 *2 = 1472 of 1518 DSP blocks (97%)
+ g_nof_mac4 => 750,
- g_pipeline => 72, -- max 72
- g_nof_ram => 4, -- max 4
+ g_pipeline => 72, -- max 72
+ g_nof_ram => 4, -- max 4
- g_nof_logic => 24 -- max 24
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ g_nof_logic => 24 -- max 24
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_heater_mosi,
- sla_out => reg_heater_miso
- );
+ sla_in => reg_heater_mosi,
+ sla_out => reg_heater_miso
+ );
end generate;
-
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index ecd624929ce531db8a1ed03d113ce557689377f7..58f349741a717d9219d5e02d88ff0ece60c0abcc 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -22,38 +22,38 @@
-- Purpose: Define selections for revisions of the unb2c_test design
library IEEE, common_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
package unb2c_test_pkg is
-- dp_offload_tx (carried over from unb2a_test_pkg
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( -- ( field_name_pad("align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ), -- FIXME fill this in for non point-to-point use
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 47, field_default(0) ));
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
@@ -62,34 +62,33 @@ package unb2c_test_pkg is
-----------------------------------------------------------------------------
type t_unb2c_test_config is record
- use_loopback : boolean; -- for pinning designs
- use_1GbE_I_UDP : boolean; -- Use the UDP offload on eth0. Eth0 is always enabled for control
- use_1GbE_II : boolean; -- Intantiate eth1 for pinning designs
- use_10GbE_qsfp : boolean;
- use_10GbE_ring : boolean;
- use_10GbE_back0 : boolean;
- use_jesd204b : boolean;
- use_MB_I : boolean;
- use_MB_II : boolean;
- use_heater : boolean;
- type_MB_I : t_c_tech_ddr;
- type_MB_II : t_c_tech_ddr;
- end record;
+ use_loopback : boolean; -- for pinning designs
+ use_1GbE_I_UDP : boolean; -- Use the UDP offload on eth0. Eth0 is always enabled for control
+ use_1GbE_II : boolean; -- Intantiate eth1 for pinning designs
+ use_10GbE_qsfp : boolean;
+ use_10GbE_ring : boolean;
+ use_10GbE_back0 : boolean;
+ use_jesd204b : boolean;
+ use_MB_I : boolean;
+ use_MB_II : boolean;
+ use_heater : boolean;
+type_MB_I : t_c_tech_ddr;
+type_MB_II : t_c_tech_ddr;
+end record;
- -- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
- constant c_test_minimal : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE : t_unb2c_test_config := (false,false,false, true, true,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
- constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
-
- -- Function to select the revision configuration.
- function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
+-- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
+constant c_test_minimal : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_10GbE : t_unb2c_test_config := (false,false,false, true, true,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
+constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+-- Function to select the revision configuration.
+function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
end unb2c_test_pkg;
package body unb2c_test_pkg is
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index a34e6633db99ec9a06cab4d836db5f2030d95324..6b5ac9bd41549ece7d3cedf5faf99e7d9d6f1614 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -42,14 +42,14 @@
--
library IEEE, common_lib, unb2c_board_lib, i2c_lib, technology_lib, tech_pll_lib, tech_ddr_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb2c_board_lib.unb2c_board_pkg.all;
-use common_lib.tb_common_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_pll_lib.tech_pll_component_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb2c_board_lib.unb2c_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_pll_lib.tech_pll_component_pkg.all;
+ use tech_ddr_lib.tech_ddr_pkg.all;
entity tb_unb2c_test is
generic (
@@ -161,97 +161,97 @@ begin
-- DUT
------------------------------------------------------------------------------
u_unb2c_test : entity work.unb2c_test
- generic map (
- g_design_name => g_design_name,
- g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
- g_sim_model_ddr => g_sim_model_ddr
- )
- port map (
- -- GENERAL
- CLK => clk,
- PPS => pps,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- 1GbE Control Interface
- ETH_CLK => eth_clk,
- ETH_SGIN => eth_rxp,
- ETH_SGOUT => eth_txp,
-
- -- Transceiver clocks
- SA_CLK => sa_clk,
- SB_CLK => sb_clk,
- BCK_REF_CLK => bck_ref_clk,
-
- -- DDR reference clocks
- MB_I_REF_CLK => mb_I_ref_clk,
- MB_II_REF_CLK => mb_II_ref_clk,
-
- -- Serial I/O
--- QSFP_0_TX => si_lpbk_0,
--- QSFP_0_RX => si_lpbk_0,
--- QSFP_1_TX => si_lpbk_1,
--- QSFP_1_RX => si_lpbk_1,
--- QSFP_2_TX => si_lpbk_2,
--- QSFP_2_RX => si_lpbk_2,
--- QSFP_3_TX => si_lpbk_3,
--- QSFP_3_RX => si_lpbk_3,
--- QSFP_4_TX => si_lpbk_4,
--- QSFP_4_RX => si_lpbk_4,
--- QSFP_5_TX => si_lpbk_5,
--- QSFP_5_RX => si_lpbk_5,
---
--- RING_0_TX => si_lpbk_6,
--- RING_0_RX => si_lpbk_6,
--- RING_1_TX => si_lpbk_7,
--- RING_1_RX => si_lpbk_7,
---
--- BCK_TX => si_lpbk_8,
--- BCK_RX => si_lpbk_8,
-
- -- SO-DIMM Memory Bank I
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU,
-
- -- SO-DIMM Memory Bank II
- MB_II_IN => MB_II_IN,
- MB_II_IO => MB_II_IO,
- MB_II_OU => MB_II_OU,
-
- -- Leds
- QSFP_LED => qsfp_led
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_sim_model_ddr => g_sim_model_ddr
+ )
+ port map (
+ -- GENERAL
+ CLK => clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => sa_clk,
+ SB_CLK => sb_clk,
+ BCK_REF_CLK => bck_ref_clk,
+
+ -- DDR reference clocks
+ MB_I_REF_CLK => mb_I_ref_clk,
+ MB_II_REF_CLK => mb_II_ref_clk,
+
+ -- Serial I/O
+ -- QSFP_0_TX => si_lpbk_0,
+ -- QSFP_0_RX => si_lpbk_0,
+ -- QSFP_1_TX => si_lpbk_1,
+ -- QSFP_1_RX => si_lpbk_1,
+ -- QSFP_2_TX => si_lpbk_2,
+ -- QSFP_2_RX => si_lpbk_2,
+ -- QSFP_3_TX => si_lpbk_3,
+ -- QSFP_3_RX => si_lpbk_3,
+ -- QSFP_4_TX => si_lpbk_4,
+ -- QSFP_4_RX => si_lpbk_4,
+ -- QSFP_5_TX => si_lpbk_5,
+ -- QSFP_5_RX => si_lpbk_5,
+ --
+ -- RING_0_TX => si_lpbk_6,
+ -- RING_0_RX => si_lpbk_6,
+ -- RING_1_TX => si_lpbk_7,
+ -- RING_1_RX => si_lpbk_7,
+ --
+ -- BCK_TX => si_lpbk_8,
+ -- BCK_RX => si_lpbk_8,
+
+ -- SO-DIMM Memory Bank I
+ MB_I_IN => MB_I_IN,
+ MB_I_IO => MB_I_IO,
+ MB_I_OU => MB_I_OU,
+
+ -- SO-DIMM Memory Bank II
+ MB_II_IN => MB_II_IN,
+ MB_II_IO => MB_II_IO,
+ MB_II_OU => MB_II_OU,
+
+ -- Leds
+ QSFP_LED => qsfp_led
+ );
------------------------------------------------------------------------------
-- UniBoard DDR4
------------------------------------------------------------------------------
u_tech_ddr_memory_model_MB_I : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_I
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_I_OU,
- mem4_io => MB_I_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_I
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_I_OU,
+ mem4_io => MB_I_IO
+ );
u_tech_ddr_memory_model_MB_II : entity tech_ddr_lib.tech_ddr_memory_model
- generic map (
- g_tech_ddr => c_ddr_MB_II
- )
- port map (
- -- DDR4 PHY interface
- mem4_in => MB_II_OU,
- mem4_io => MB_II_IO
- );
+ generic map (
+ g_tech_ddr => c_ddr_MB_II
+ )
+ port map (
+ -- DDR4 PHY interface
+ mem4_in => MB_II_OU,
+ mem4_io => MB_II_IO
+ );
end tb;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
index 2b7934b9c80f06c9048de3c8e495883c7c7e611d..28486c516573e840661254b102bbb9addfb17405 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -41,91 +41,91 @@
-- --------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
entity bscan2 is
- -- enter the number of BSCAN2 blocks to create. This is the only place that
- -- needs to be modified to control the number of local scan ports created.
- generic ( bscan_ports : positive := 2 );
- port( TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
+ -- enter the number of BSCAN2 blocks to create. This is the only place that
+ -- needs to be modified to control the number of local scan ports created.
+ generic ( bscan_ports : positive := 2 );
+ port( TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
end;
architecture behave of bscan2 is
- component top_linker is
- -- do not use the generic map to prevent the synthesis tool from
- -- appending the number of ports to the components name.
- port(TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- enable logic for TDO pins.
- TDO_enable : out std_logic;
- TDO : out std_logic;
- MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
- MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
- MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(4 downto 1)
- );
-end component top_linker;
--- synthesis FILE="top_linker.ngo"
+ component top_linker is
+ -- do not use the generic map to prevent the synthesis tool from
+ -- appending the number of ports to the components name.
+ port(TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- enable logic for TDO pins.
+ TDO_enable : out std_logic;
+ TDO : out std_logic;
+ MSPCLK : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDI : in std_logic_vector(4 * bscan_ports downto 1);
+ MSPTDO : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTMS : out std_logic_vector(4 * bscan_ports downto 1);
+ MSPTRST : out std_logic_vector(4 * bscan_ports downto 1);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(4 downto 1)
+ );
+ end component top_linker;
+ -- synthesis FILE="top_linker.ngo"
--- logic to enable TDO pins
-signal ENABLE_TDO : std_logic;
--- signal from tap controler that enables all TDOs.
-signal tdoENABLE : std_logic;
--- logic to generate tdo_sp and tdo_hdr
-signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
-signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
--- output of Port Mux
-signal TDO_int : std_logic;
+ -- logic to enable TDO pins
+ signal ENABLE_TDO : std_logic;
+ -- signal from tap controler that enables all TDOs.
+ signal tdoENABLE : std_logic;
+ -- logic to generate tdo_sp and tdo_hdr
+ signal LSPTMS : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTCK : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- output of Port Mux
+ signal TDO_int : std_logic;
begin
- -- Wire up all of the tri-state controlled lines automatically
- tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
- MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
- MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
- -- enable MSPTDOs for 1149.1
- MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
- end generate tri_state_lines;
+ -- Wire up all of the tri-state controlled lines automatically
+ tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
+ MSPTCK(lvar1) <= LSPTCK(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTMS(lvar1) <= LSPTMS(lvar1) when ENABLE_MSP = '1' else 'Z';
+ MSPTRST(lvar1) <= LSPTRST(lvar1) when ENABLE_MSP = '1' else 'Z';
+ -- enable MSPTDOs for 1149.1
+ MSPTDO(lvar1) <= LSPTDO(lvar1) when ENABLE_TDO = '1' else 'Z';
+ end generate tri_state_lines;
- -- MSP Port enable controls
- -- enable logic for all TDO pins
- ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
+ -- MSP Port enable controls
+ -- enable logic for all TDO pins
+ ENABLE_TDO <= ENABLE_MSP and tdoENABLE;
- TDO <= TDO_int when tdoENABLE = '1' else 'Z';
+ TDO <= TDO_int when tdoENABLE = '1' else 'Z';
- TopLinkerModule : component top_linker
- port map(
- TDO => TDO_int,
- TMS => TMS,
- TCK => TCK,
- TRST => TRST,
- TDI => TDI,
- TDO_enable => tdoENABLE,
- MSPTDI => MSPTDI,
- MSPTDO => LSPTDO,
- MSPTMS => LSPTMS,
- MSPCLK => LSPTCK,
- MSPTRST => LSPTRST,
- IDN => IDN
- );
+ TopLinkerModule : component top_linker
+ port map(
+ TDO => TDO_int,
+ TMS => TMS,
+ TCK => TCK,
+ TRST => TRST,
+ TDI => TDI,
+ TDO_enable => tdoENABLE,
+ MSPTDI => MSPTDI,
+ MSPTDO => LSPTDO,
+ MSPTMS => LSPTMS,
+ MSPCLK => LSPTCK,
+ MSPTRST => LSPTRST,
+ IDN => IDN
+ );
end behave;
--------------------------------- E O F --------------------------------------
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index a26751236aab0e7203dc36a06fd6758f5faf50dc..b3169201d320d741e3be11aad0a7b70b3eff4fd8 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -21,128 +21,128 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_unsigned.all;
architecture str of jtag_top is
- component bscan2 is
+ component bscan2 is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
- generic (
- bscan_ports : positive := 2
+ generic (
+ bscan_ports : positive := 2
- );
- port (
- TDI, TCK, TMS : in std_logic;
- TRST : in std_logic;
- -- Turn on slow slew in fitter for output signals
- TDO : out std_logic;
- -- OE control for MSP ports (Active high)
- ENABLE_MSP : in std_logic;
- MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
- -- one set of addresses to check for device
- IDN : in std_logic_vector(3 downto 0)
- );
- end component bscan2;
+ );
+ port (
+ TDI, TCK, TMS : in std_logic;
+ TRST : in std_logic;
+ -- Turn on slow slew in fitter for output signals
+ TDO : out std_logic;
+ -- OE control for MSP ports (Active high)
+ ENABLE_MSP : in std_logic;
+ MSPTCK : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDI : in std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTDO : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTMS : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ MSPTRST : out std_logic_vector(4 * bscan_ports - 1 downto 0);
+ -- one set of addresses to check for device
+ IDN : in std_logic_vector(3 downto 0)
+ );
+ end component bscan2;
--- internal enable signal for tri-stating the scanbridge
- constant jtag_chains : natural := 5;
- signal ENABLE_SB : std_logic;
- signal TDO_BSCAN : std_logic;
- signal TDA : std_logic;
- signal TDB : std_logic;
- signal TDC : std_logic;
- signal TDD : std_logic;
- signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
- begin
- bscan : component bscan2
- port map (
- TDI => TDI,
- TCK => TCK,
- TMS => TMS,
- TRST => TRST,
- TDO => TDO_BSCAN,
- ENABLE_MSP => ENABLE_SB,
- MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
- MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
- MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
- MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
- MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
- IDN => "0000"
- );
+ -- internal enable signal for tri-stating the scanbridge
+ constant jtag_chains : natural := 5;
+ signal ENABLE_SB : std_logic;
+ signal TDO_BSCAN : std_logic;
+ signal TDA : std_logic;
+ signal TDB : std_logic;
+ signal TDC : std_logic;
+ signal TDD : std_logic;
+ signal MSPTDO_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+ signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
+begin
+ bscan : component bscan2
+ port map (
+ TDI => TDI,
+ TCK => TCK,
+ TMS => TMS,
+ TRST => TRST,
+ TDO => TDO_BSCAN,
+ ENABLE_MSP => ENABLE_SB,
+ MSPTCK(jtag_chains - 1 downto 0) => MSPTCK_BSCAN,
+ MSPTDI(jtag_chains - 1 downto 0) => MSPTDI,
+ MSPTDO(jtag_chains - 1 downto 0) => MSPTDO_BSCAN,
+ MSPTMS(jtag_chains - 1 downto 0) => MSPTMS_BSCAN,
+ MSPTRST(jtag_chains - 1 downto 0) => MSPTRST_BSCAN,
+ IDN => "0000"
+ );
- p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
- begin
- ENABLE_SB <= '0';
- MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
- MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
+ begin
+ ENABLE_SB <= '0';
+ MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTCK(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTMS(jtag_chains - 1 downto 0) <= "ZZZZZ";
+ MSPTRST(jtag_chains - 1 downto 0) <= "ZZZZZ";
- if CTRL(1) = '1' then
- ENABLE_SB <= '1';
- MSPTDO <= MSPTDO_BSCAN;
- TDO <= TDO_BSCAN;
- MSPTCK <= MSPTCK_BSCAN;
- MSPTMS <= MSPTMS_BSCAN;
- MSPTRST <= MSPTRST_BSCAN;
- else
- if LPSEL(0) = '0' then
- MSPTDO(0) <= TDI;
- TDA <= MSPTDI(0);
- MSPTCK(0) <= TCK;
- MSPTMS(0) <= TMS;
- MSPTRST(0) <= TRST;
- else
- TDA <= TDI;
- end if;
+ if CTRL(1) = '1' then
+ ENABLE_SB <= '1';
+ MSPTDO <= MSPTDO_BSCAN;
+ TDO <= TDO_BSCAN;
+ MSPTCK <= MSPTCK_BSCAN;
+ MSPTMS <= MSPTMS_BSCAN;
+ MSPTRST <= MSPTRST_BSCAN;
+ else
+ if LPSEL(0) = '0' then
+ MSPTDO(0) <= TDI;
+ TDA <= MSPTDI(0);
+ MSPTCK(0) <= TCK;
+ MSPTMS(0) <= TMS;
+ MSPTRST(0) <= TRST;
+ else
+ TDA <= TDI;
+ end if;
- if LPSEL(1) = '0' then
- MSPTDO(1) <= TDA;
- TDB <= MSPTDI(1);
- MSPTCK(1) <= TCK;
- MSPTMS(1) <= TMS;
- MSPTRST(1) <= TRST;
- else
- TDB <= TDA;
- end if;
+ if LPSEL(1) = '0' then
+ MSPTDO(1) <= TDA;
+ TDB <= MSPTDI(1);
+ MSPTCK(1) <= TCK;
+ MSPTMS(1) <= TMS;
+ MSPTRST(1) <= TRST;
+ else
+ TDB <= TDA;
+ end if;
- if LPSEL(2) = '0' then
- MSPTDO(2) <= TDB;
- TDC <= MSPTDI(2);
- MSPTCK(2) <= TCK;
- MSPTMS(2) <= TMS;
- MSPTRST(2) <= TRST;
- else
- TDC <= TDB;
- end if;
+ if LPSEL(2) = '0' then
+ MSPTDO(2) <= TDB;
+ TDC <= MSPTDI(2);
+ MSPTCK(2) <= TCK;
+ MSPTMS(2) <= TMS;
+ MSPTRST(2) <= TRST;
+ else
+ TDC <= TDB;
+ end if;
- if LPSEL(3) = '0' then
- MSPTDO(3) <= TDC;
- TDD <= MSPTDI(3);
- MSPTCK(3) <= TCK;
- MSPTMS(3) <= TMS;
- MSPTRST(3) <= TRST;
- else
- TDD <= TDC;
- end if;
+ if LPSEL(3) = '0' then
+ MSPTDO(3) <= TDC;
+ TDD <= MSPTDI(3);
+ MSPTCK(3) <= TCK;
+ MSPTMS(3) <= TMS;
+ MSPTRST(3) <= TRST;
+ else
+ TDD <= TDC;
+ end if;
- if LPSEL(4) = '0' then
- MSPTDO(4) <= TDD;
- TDO <= MSPTDI(4);
- MSPTCK(4) <= TCK;
- MSPTMS(4) <= TMS;
- MSPTRST(4) <= TRST;
- else
- TDO <= TDD;
- end if;
- end if;
+ if LPSEL(4) = '0' then
+ MSPTDO(4) <= TDD;
+ TDO <= MSPTDI(4);
+ MSPTCK(4) <= TCK;
+ MSPTMS(4) <= TMS;
+ MSPTRST(4) <= TRST;
+ else
+ TDO <= TDD;
+ end if;
+ end if;
end process;
end str;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
index 1968d26ac97786594b1c59bf5eeaf1ae92a6a5ce..7aa11d383def3df79223297b423a56462807da87 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top.vhd
@@ -6,23 +6,23 @@
---------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity jtag_top is
- port (
- CTRL : in std_logic_vector(1 downto 0);
- ENABLE_MSP : in std_logic;
- IDN : in std_logic_vector(3 downto 0);
- LPSEL : in std_logic_vector(4 downto 0);
- MSPTCK : out std_logic_vector(4 downto 0);
- MSPTDI : in std_logic_vector(4 downto 0);
- MSPTDO : out std_logic_vector(4 downto 0);
- MSPTMS : out std_logic_vector(4 downto 0);
- MSPTRST : out std_logic_vector(4 downto 0);
- TCK : in std_logic;
- TDI : in std_logic;
- TDO : out std_logic;
- TMS : in std_logic;
- TRST : in std_logic
- );
+ port (
+ CTRL : in std_logic_vector(1 downto 0);
+ ENABLE_MSP : in std_logic;
+ IDN : in std_logic_vector(3 downto 0);
+ LPSEL : in std_logic_vector(4 downto 0);
+ MSPTCK : out std_logic_vector(4 downto 0);
+ MSPTDI : in std_logic_vector(4 downto 0);
+ MSPTDO : out std_logic_vector(4 downto 0);
+ MSPTMS : out std_logic_vector(4 downto 0);
+ MSPTRST : out std_logic_vector(4 downto 0);
+ TCK : in std_logic;
+ TDI : in std_logic;
+ TDO : out std_logic;
+ TMS : in std_logic;
+ TRST : in std_logic
+ );
end jtag_top;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 74bc5570a961ed53b0fcd6feed3601bfff152d3f..dba0118c5208eb0e189a5b169ec78e8bcc276c0f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -25,16 +25,16 @@
-- . ctrl_unb2c_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
library IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.unb2c_board_pkg.all;
-use i2c_lib.i2c_pkg.all;
-use technology_lib.technology_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use i2c_lib.i2c_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
entity ctrl_unb2c_board is
generic (
@@ -244,7 +244,7 @@ architecture str of ctrl_unb2c_board is
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
- constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
+ constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2 ** 9, 'X');
-- Clock and reset
signal i_ext_clk200 : std_logic;
@@ -318,15 +318,15 @@ begin
i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
u_common_areset_ext : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
-----------------------------------------------------------------------------
-- xo_ethclk = ETH_CLK
@@ -335,15 +335,15 @@ begin
i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
@@ -351,26 +351,26 @@ begin
-----------------------------------------------------------------------------
u_common_areset_mb_I : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
u_common_areset_mb_II : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
-----------------------------------------------------------------------------
-- dp_clk + dp_rst generation
@@ -384,29 +384,29 @@ begin
gen_pll: if g_sim = false and g_dp_clk_use_pll = true generate
u_unb2c_board_clk200_pll : entity work.unb2c_board_clk200_pll
+ generic map (
+ g_technology => g_technology,
+ g_use_fpll => true,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ port map (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ end generate;
+
+ u_common_areset_dp_rst : entity common_lib.common_areset
generic map (
- g_technology => g_technology,
- g_use_fpll => true,
- g_clk200_phase_shift => g_dp_clk_phase
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
)
port map (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
);
- end generate;
-
- u_common_areset_dp_rst : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-----------------------------------------------------------------------------
-- mm_clk
@@ -418,51 +418,51 @@ begin
clk125 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_125M else
clk100 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_100M else
clk50 when g_mm_clk_freq = c_unb2c_board_mm_clk_freq_50M else
- clk50; -- default
+ clk50; -- default
gen_mm_clk_sim: if g_sim = true generate
- epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
- clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
- clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
- clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
- sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
- mm_locked <= '0', '1' after 70 ns;
+ epcs_clk <= not epcs_clk after 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= not clk50 after 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= not clk100 after 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= not clk125 after 4 ns; -- 125 MHz, 8ns/2
+ sim_mm_clk <= not sim_mm_clk after g_sim_mm_clk_period / 2;
+ mm_locked <= '0', '1' after 70 ns;
end generate;
gen_mm_clk_hardware: if g_sim = false generate
u_unb2c_board_clk125_pll : entity work.unb2c_board_clk125_pll
+ generic map (
+ g_use_fpll => true,
+ g_technology => g_technology
+ )
+ port map (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ end generate;
+
+ u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
generic map (
- g_use_fpll => true,
- g_technology => g_technology
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
)
port map (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
- end generate;
-
- u_unb2c_board_node_ctrl : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- port map (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-----------------------------------------------------------------------------
-- System info
@@ -470,33 +470,33 @@ begin
cs_sim <= is_true(g_sim);
u_mms_unb2c_board_system_info : entity work.mms_unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- port map (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ port map (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
-----------------------------------------------------------------------------
-- Red LED control
@@ -531,12 +531,12 @@ begin
led_toggle_green <= sel_a_b(g_factory_image = false, led_toggle, '0');
u_toggle : entity common_lib.common_toggle
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
+ port map (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
------------------------------------------------------------------------------
-- WDI override
@@ -547,15 +547,15 @@ begin
WDI <= mm_wdi or temp_alarm or wdi_override;
u_unb2c_board_wdi_reg : entity work.unb2c_board_wdi_reg
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
- wdi_override => wdi_override
- );
+ wdi_override => wdi_override
+ );
------------------------------------------------------------------------------
-- Remote upgrade
@@ -564,98 +564,98 @@ begin
-- So there is full control over the memory mapped registers to set start address of the flash
-- and reconfigure from that address.
u_mms_remu: entity remu_lib.mms_remu
- generic map (
- g_technology => g_technology
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
-------------------------------------------------------------------------------
---- EPCS
-------------------------------------------------------------------------------
u_mms_epcs: entity epcs_lib.mms_epcs
- generic map (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- port map (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
+ generic map (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ port map (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
- epcs_clk => epcs_clk,
+ epcs_clk => epcs_clk,
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
u_mms_ppsh : entity ppsh_lib.mms_ppsh
- generic map (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
+ generic map (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
u_mms_unb2c_fpga_sens : entity work.mms_unb2c_fpga_sens
- generic map (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- port map (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- mm_start => '1',
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
+ generic map (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ mm_start => '1',
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
------------------------------------------------------------------------------
-- Ethernet 1GbE
@@ -664,18 +664,18 @@ begin
gen_tse_clk_buf: if g_tse_clk_buf = true generate
-- Separate clkbuf for the 1GbE tse_clk:
u_tse_clk_buf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
end generate;
gen_tse_no_clk_buf: if g_tse_clk_buf = false generate
- i_tse_clk <= i_xo_ethclk;
+ i_tse_clk <= i_xo_ethclk;
end generate;
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
@@ -700,60 +700,60 @@ begin
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
u_eth : entity eth_lib.eth
+ generic map (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => true,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ end generate;
+
+ u_ram_scrap : entity common_lib.common_ram_r_w
generic map (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => true,
- g_sim => g_sim,
- g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
+ g_ram => c_ram_scrap
)
port map (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
+ rd_val => ram_scrap_miso.rdval
);
- end generate;
-
- u_ram_scrap : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_scrap
- )
- port map (
- rst => i_mm_rst,
- clk => i_mm_clk,
- wr_en => ram_scrap_mosi.wr,
- wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w - 1 downto 0),
- rd_en => ram_scrap_mosi.rd,
- rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w - 1 downto 0),
- rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
- rd_val => ram_scrap_miso.rdval
- );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index 699c38a4d2262156a5cc1fa378aeb487034d732f..1de667b8511e5edfb500a576ac49db58b3648a21 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_board_system_info is
generic (
@@ -58,7 +58,7 @@ entity mms_unb2c_board_system_info is
-- Info output still supported for older designs
info : out std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mms_unb2c_board_system_info;
architecture str of mms_unb2c_board_system_info is
@@ -68,68 +68,69 @@ architecture str of mms_unb2c_board_system_info is
constant c_modelsim_path_prefix : string := "$UNB/Firmware/designs/" & g_design_name & "/build/synth/quartus/"; -- TODO: change path
constant c_path_prefix : string := sel_a_b(g_sim, c_modelsim_path_prefix, c_quartus_path_prefix);
--- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
--- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
+ -- No longer supporting MIF files in sim as non-$UNB (e.g. $AARTFAAC) designs will cause path error.
+ -- CONSTANT c_mif_name : STRING := sel_a_b((g_design_name="UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif");
constant c_mif_name : string := sel_a_b(g_sim, "UNUSED", sel_a_b((g_design_name = "UNUSED"), g_design_name, c_path_prefix & g_design_name & ".mif"));
constant c_rom_addr_w : natural := 13; -- 2^13 = 8192 addresses * 32 bits = 32 kiB
- constant c_mm_rom : t_c_mem := (latency => 1,
- adr_w => c_rom_addr_w,
- dat_w => c_word_w,
- nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
- init_sl => '0');
+ constant c_mm_rom : t_c_mem := (
+ latency => 1,
+ adr_w => c_rom_addr_w,
+ dat_w => c_word_w,
+ nof_dat => 2**c_rom_addr_w, -- = 2**adr_w
+ init_sl => '0');
- signal i_info : std_logic_vector(c_word_w - 1 downto 0);
+ signal i_info : std_logic_vector(c_word_w - 1 downto 0);
begin
- info <= i_info;
+ info <= i_info;
u_unb2c_board_system_info: entity work.unb2c_board_system_info
- generic map (
- g_sim => g_sim,
- g_fw_version => g_fw_version,
- g_rom_version => g_rom_version,
- g_technology => g_technology
- )
- port map (
- clk => mm_clk,
- hw_version => hw_version,
- id => id,
- info => i_info,
- chip_id => chip_id,
- bck_id => bck_id
- );
+ generic map (
+ g_sim => g_sim,
+ g_fw_version => g_fw_version,
+ g_rom_version => g_rom_version,
+ g_technology => g_technology
+ )
+ port map (
+ clk => mm_clk,
+ hw_version => hw_version,
+ id => id,
+ info => i_info,
+ chip_id => chip_id,
+ bck_id => bck_id
+ );
u_unb2c_board_system_info_reg: entity work.unb2c_board_system_info_reg
- generic map (
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- info => i_info
- );
+ generic map (
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ info => i_info
+ );
u_common_rom : entity common_lib.common_rom
- generic map (
- g_technology => g_technology,
- g_ram => c_mm_rom,
- g_init_file => c_mif_name
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- rd_en => rom_mosi.rd,
- rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
- rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
- rd_val => rom_miso.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_rom,
+ g_init_file => c_mif_name
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ rd_en => rom_mosi.rd,
+ rd_adr => rom_mosi.address(c_mm_rom.adr_w - 1 downto 0),
+ rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
+ rd_val => rom_miso.rdval
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index 6b19f5aad1f07bc80ddbdc66a4e10bde2219af4e..806297da80b7172b297f885e6a38a8aa667055d8 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -23,11 +23,11 @@
-- Description: See unb2c_fpga_sens.vhd
library IEEE, technology_lib, common_lib, fpga_sense_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_pkg.all;
entity mms_unb2c_fpga_sens is
generic (
@@ -55,22 +55,22 @@ end mms_unb2c_fpga_sens;
architecture str of mms_unb2c_fpga_sens is
begin
u_fpga_sense: entity fpga_sense_lib.fpga_sense
- generic map (
- g_technology => g_technology,
- g_sim => g_sim,
- g_temp_high => g_temp_high
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map (
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_temp_high => g_temp_high
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- start_sense => mm_start,
- temp_alarm => temp_alarm,
+ start_sense => mm_start,
+ temp_alarm => temp_alarm,
- reg_temp_mosi => reg_temp_mosi,
- reg_temp_miso => reg_temp_miso,
+ reg_temp_mosi => reg_temp_mosi,
+ reg_temp_miso => reg_temp_miso,
- reg_voltage_store_mosi => reg_voltage_mosi,
- reg_voltage_store_miso => reg_voltage_miso
- );
+ reg_voltage_store_mosi => reg_voltage_mosi,
+ reg_voltage_store_miso => reg_voltage_miso
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index f50eaf95d22a55f101164441bc0734c4cf31d123..e86291c24407aa31642a4b9dece4232d1c280344 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_back_io is
generic (
@@ -48,6 +48,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2c_board_tr_back.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index 1c0b8a5d378373cd491677a316c707a5d54e7020..24cbbc2bb3b142f1d85030c4e80ca3847d4ac8e2 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 125 MHz
-- Description:
@@ -60,46 +60,45 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk125,
- outclk => clk125buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk125,
+ outclk => clk125buf
+ );
end generate;
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
gen_fractional_pll : if g_use_fpll = true generate
u_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk125
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk125buf,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end generate;
-
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index ac16a08d1527d9590123f78b04e3bf8fe1ec08b4..93b82bca585013d702fb4207bb43c4324d2d3a24 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_clkbuf_lib, tech_pll_lib, tech_fractional_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 200 MHz
-- Description:
@@ -136,82 +136,82 @@ begin
gen_clkbuf : if g_use_clkbuf = true generate
u_clkbuf : entity tech_clkbuf_lib.tech_clkbuf
- generic map (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- port map (
- inclk => clk200,
- outclk => clk200buf
- );
+ generic map (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ port map (
+ inclk => clk200,
+ outclk => clk200buf
+ );
end generate;
gen_st_pll : if g_use_fpll = false generate
u_st_pll : entity tech_pll_lib.tech_pll_clk200
- generic map (
- g_technology => g_technology,
- g_operation_mode => g_operation_mode,
- g_clk0_phase_shift => g_clk200_phase_shift,
- g_clk1_phase_shift => g_clk200p_phase_shift
- )
- port map (
- areset => arst,
- inclk0 => clk200buf,
- c0 => i_st_clk200,
- c1 => i_st_clk200p,
- c2 => i_st_clk400,
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology,
+ g_operation_mode => g_operation_mode,
+ g_clk0_phase_shift => g_clk200_phase_shift,
+ g_clk1_phase_shift => g_clk200p_phase_shift
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf,
+ c0 => i_st_clk200,
+ c1 => i_st_clk200p,
+ c2 => i_st_clk400,
+ locked => st_locked
+ );
end generate;
gen_st_fractional_pll : if g_use_fpll = true generate
u_st_fractional_pll : entity tech_fractional_pll_lib.tech_fractional_pll_clk200
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk200buf, -- 200 MHz
- c0 => i_st_clk200, -- 200 MHz
- c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
- c2 => i_st_clk400, -- 400 MHz
- locked => st_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk200buf, -- 200 MHz
+ c0 => i_st_clk200, -- 200 MHz
+ c1 => i_st_clk200p, -- 200 MHz shifted 90 degrees
+ c2 => i_st_clk400, -- 400 MHz
+ locked => st_locked
+ );
end generate;
-- Release clock domain resets after some clock cycles when the PLL has locked
st_locked_n <= not st_locked;
u_rst200 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200,
- out_rst => i_st_rst200
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200,
+ out_rst => i_st_rst200
+ );
u_rst200p : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk200p,
- out_rst => st_rst200p
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk200p,
+ out_rst => st_rst200p
+ );
u_rst400 : entity common_lib.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => st_locked_n,
- clk => i_st_clk400,
- out_rst => st_rst400
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => st_locked_n,
+ clk => i_st_clk400,
+ out_rst => st_rst400
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index 71a8f3000c65aa0a7d3ed3c3ef3cee696d09c8b6..cc4344f34bdb10f32aeccd16eae2abd7774216c9 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_pll_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Purpose: PLL for UniBoard node CLK input @ 25 MHz
-- Description:
@@ -52,16 +52,16 @@ end unb2c_board_clk25_pll;
architecture arria10 of unb2c_board_clk25_pll is
begin
u_pll : entity tech_pll_lib.tech_pll_clk25
- generic map (
- g_technology => g_technology
- )
- port map (
- areset => arst,
- inclk0 => clk25,
- c0 => c0_clk20,
- c1 => c1_clk50,
- c2 => c2_clk100,
- c3 => c3_clk125,
- locked => pll_locked
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ areset => arst,
+ inclk0 => clk25,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
index 25dd597531db0184a247147f3cf4ae108149fc54..ecf4aab995d83121cb83cd070fcf3f3ed1e957b1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- 1) initial power up xo_rst_n that can be used to reset a SOPC system (via
@@ -55,27 +55,27 @@ begin
xo_rst_n <= not xo_rst;
u_common_areset_xo : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => xo_clk,
- out_rst => xo_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => xo_clk,
+ out_rst => xo_rst
+ );
-- System clock from SOPC system PLL and system reset
sys_locked_n <= not sys_locked;
u_common_areset_sys : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => sys_clk,
- out_rst => sys_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => sys_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => sys_clk,
+ out_rst => sys_rst
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index ca19220a75b529d1a263629c316a583a70dbb275..554c3c7e465271e10cefb7c1dd0f8c4a1478c6cc 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_front_io is
generic (
@@ -59,9 +59,10 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2c_board_tr_qsfp.bus_w - 1 generate
- si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
- serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
+ si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
+ serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
end generate;
end generate;
end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
index cd18bbc40cec125f81658a0fd47e06cef83951e1..7889453be5d8fd3dd6d688d111af6ffffca7af66 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide the basic node clock control (resets, pulses, WDI)
-- Description:
@@ -67,43 +67,43 @@ begin
mm_locked_n <= not mm_locked;
u_common_areset_mm : entity common_lib.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
- clk => mm_clk,
- out_rst => i_mm_rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => mm_locked_n, -- release reset after some clock cycles when the PLL has locked
+ clk => mm_clk,
+ out_rst => i_mm_rst
+ );
-- Create 1 pulse per us, per ms and per s
mm_pulse_ms <= i_mm_pulse_ms;
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us,
- g_pulse_ms => g_pulse_ms,
- g_pulse_s => g_pulse_s
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_us => mm_pulse_us,
- pulse_ms => i_mm_pulse_ms,
- pulse_s => mm_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us,
+ g_pulse_ms => g_pulse_ms,
+ g_pulse_s => g_pulse_s
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_us => mm_pulse_us,
+ pulse_ms => i_mm_pulse_ms,
+ pulse_s => mm_pulse_s
+ );
-- Toggle the WDI every 1 ms
u_unb2c_board_wdi_extend : entity work.unb2c_board_wdi_extend
- generic map (
- g_extend_w => g_wdi_extend_w
- )
- port map (
- rst => i_mm_rst,
- clk => mm_clk,
- pulse_ms => i_mm_pulse_ms,
- wdi_in => mm_wdi_in,
- wdi_out => mm_wdi_out
- );
+ generic map (
+ g_extend_w => g_wdi_extend_w
+ )
+ port map (
+ rst => i_mm_rst,
+ clk => mm_clk,
+ pulse_ms => i_mm_pulse_ms,
+ wdi_in => mm_wdi_in,
+ wdi_out => mm_wdi_out
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index 09f3d31eb03c9dea2187fe903fad302efc866c1b..0d7fde0d4451f10d1406725402c4aed1da54be69 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -39,7 +39,7 @@
-- these widths need to be defined locally in that design.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
package unb2c_board_peripherals_pkg is
-- *_adr_w : Actual MM address widths
@@ -74,10 +74,10 @@ package unb2c_board_peripherals_pkg is
-- pi_dp_ram_from_mm
reg_dp_ram_from_mm_adr_w : natural; -- = 1 -- fixed, see dp_ram_from_mm.vhd
- -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
+ -- ram_dp_ram_from_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_from_mm_reg.vhd
-- pi_dp_ram_to_mm
--- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
+ -- ram_dp_ram_to_mm_adr_w : NATURAL; -- = VAR -- Variable, from c_mm_reg in dp_ram_to_mm_reg.vhd
-- pi_epcs (uses DP-MM read and write FIFOs for data access)
reg_epcs_adr_w : natural; -- = 3 -- fixed, from c_mm_reg in epcs_reg
@@ -164,7 +164,6 @@ package unb2c_board_peripherals_pkg is
end record;
constant c_unb2c_board_peripherals_mm_reg_default : t_c_unb2c_board_peripherals_mm_reg := (true, 10, 4, 10, 5, 13, 1, 2, 6, 1, 1, 1, 1, 1, 3, 3, 3, 16, 4, 6, 2, 2, 1, 4, 3, 6, 13, 12, 2, 32, 8, 2, 8, 10, 16, 1024, 14, 5, 3, 11, 2, 3, 5, 16, 11, 3, 1, 3, 4, 6);
-
end unb2c_board_peripherals_pkg;
package body unb2c_board_peripherals_pkg is
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index 58d12477543d49583818dbc0ecda26a5527523f9..da2983db6475f415b03ddc9f2631475b5dfd4eb6 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package unb2c_board_pkg is
-- UniBoard
@@ -39,17 +39,17 @@ package unb2c_board_pkg is
constant c_unb2c_board_nof_uniboard_w : natural := 6; -- Only 2 required for 4 boards; full width is 6.
-- Clock frequencies
- constant c_unb2c_board_ext_clk_freq_200M : natural := 200 * 10**6; -- external clock, SMA clock
- constant c_unb2c_board_ext_clk_freq_256M : natural := 256 * 10**6; -- external clock, SMA clock
- constant c_unb2c_board_eth_clk_freq_25M : natural := 25 * 10**6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
- constant c_unb2c_board_eth_clk_freq_125M : natural := 125 * 10**6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
- constant c_unb2c_board_tse_clk_freq : natural := 125 * 10**6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
- constant c_unb2c_board_cal_clk_freq : natural := 40 * 10**6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_10M : natural := 10 * 10**6; -- clock when g_sim=TRUE
- constant c_unb2c_board_mm_clk_freq_25M : natural := 25 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_50M : natural := 50 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_100M : natural := 100 * 10**6; -- clock derived from ETH_clk by PLL
- constant c_unb2c_board_mm_clk_freq_125M : natural := 125 * 10**6; -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_ext_clk_freq_200M : natural := 200 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2c_board_ext_clk_freq_256M : natural := 256 * 10 ** 6; -- external clock, SMA clock
+ constant c_unb2c_board_eth_clk_freq_25M : natural := 25 * 10 ** 6; -- fixed 25 MHz ETH XO clock used as reference clock for the PLL
+ constant c_unb2c_board_eth_clk_freq_125M : natural := 125 * 10 ** 6; -- fixed 125 MHz ETH XO clock used as direct clock for TSE
+ constant c_unb2c_board_tse_clk_freq : natural := 125 * 10 ** 6; -- fixed 125 MHz TSE reference clock derived from ETH_clk by PLL
+ constant c_unb2c_board_cal_clk_freq : natural := 40 * 10 ** 6; -- fixed 40 MHz IO calibration clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_10M : natural := 10 * 10 ** 6; -- clock when g_sim=TRUE
+ constant c_unb2c_board_mm_clk_freq_25M : natural := 25 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_50M : natural := 50 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_100M : natural := 100 * 10 ** 6; -- clock derived from ETH_clk by PLL
+ constant c_unb2c_board_mm_clk_freq_125M : natural := 125 * 10 ** 6; -- clock derived from ETH_clk by PLL
-- ETH
constant c_unb2c_board_nof_eth : natural := 2; -- number of ETH channels per node
@@ -124,21 +124,22 @@ package unb2c_board_pkg is
type t_c_unb2c_board_system_info is record
version : natural; -- UniBoard board HW version (2 bit value)
id : natural; -- UniBoard FPGA node id (8 bit value)
- -- Derived ID info:
+ -- Derived ID info:
bck_id : natural; -- = id[7:2], ID part from back plane
chip_id : natural; -- = id[1:0], ID part from UniBoard
node_id : natural; -- = id[1:0], node ID: 0, 1, 2 or 3
is_node2 : natural; -- 1 for Node 2, else 0.
end record;
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
-
+ function func_unb2c_board_system_info(
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info;
end unb2c_board_pkg;
package body unb2c_board_pkg is
- function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
- ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
+ function func_unb2c_board_system_info(
+ VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
+ ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
variable v_system_info : t_c_unb2c_board_system_info;
begin
v_system_info.version := to_integer(unsigned(VERSION));
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
index 47ba71e8f14fc9c3f4fd57fb24ecdaa1de4724f1..ec3bcd365ea2c879af818003b2af7287015a4679 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Purpose: Provide visual activity information via the UniBoard2 front panel QSFP LEDs.
-- Description:
@@ -107,43 +107,43 @@ begin
-- Also output the pulses, because they could be useful for other purposes in the clk clock domain as well
u_common_pulser_us_ms_s : entity common_lib.common_pulser_us_ms_s
- generic map (
- g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
- g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_us => pulse_us,
- pulse_ms => i_pulse_ms,
- pulse_s => i_pulse_s
- );
+ generic map (
+ g_pulse_us => g_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => sel_a_b(g_sim, 10, 1000), -- nof pulse_us pulses to get ms period
+ g_pulse_s => sel_a_b(g_sim, 10, 1000) -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_us => pulse_us,
+ pulse_ms => i_pulse_ms,
+ pulse_s => i_pulse_s
+ );
u_common_toggle_s : entity common_lib.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => i_pulse_s,
- out_dat => toggle_s
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => i_pulse_s,
+ out_dat => toggle_s
+ );
gen_factory_image : if g_factory_image = true generate
green_led_arr <= (others => '0');
gen_red_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
u_red_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- -- led control
- ctrl_input => toggle_s,
- -- led output
- led => red_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- led control
+ ctrl_input => toggle_s,
+ -- led output
+ led => red_led_arr(I)
+ );
end generate;
end generate;
@@ -160,20 +160,20 @@ begin
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
u_green_led_controller : entity common_lib.common_led_controller
- generic map (
- g_nof_ms => c_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => i_pulse_ms,
- -- led control
- ctrl_on => qsfp_on_arr(I),
- ctrl_evt => qsfp_evt_arr(I),
- ctrl_input => toggle_s,
- -- led output
- led => green_led_arr(I)
- );
+ generic map (
+ g_nof_ms => c_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => i_pulse_ms,
+ -- led control
+ ctrl_on => qsfp_on_arr(I),
+ ctrl_evt => qsfp_evt_arr(I),
+ ctrl_input => toggle_s,
+ -- led output
+ led => green_led_arr(I)
+ );
end generate;
end generate;
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index 1ae3b3d7e6a67a5e4276d3a8a296b0ec36ec2984..c517b40288d2670d4eab663f05145e6ed85b39f3 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_ring_io is
generic (
@@ -47,6 +47,7 @@ begin
end generate;
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
+
gen_wire_signals : for j in 0 to c_unb2c_board_tr_ring.bus_w - 1 generate
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index ca28bdf4878eba02b20b0cc25d2ed634eb722b75..cfaefeb41f5e8db95150838e582d0fe3bec1244b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.unb2c_board_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.unb2c_board_pkg.all;
+ use technology_lib.technology_pkg.all;
-- Keep the UniBoard system info knowledge in this HDL entity and in the
-- corresponding software functions in unb_common.c,h. This avoids having to
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 355bf6c3afeb7a535f5da8a5ad23e2886cc4da62..143517fec02d4f1cafc7a02a2289a1e475d96352 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -44,11 +44,11 @@
-- =============================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.unb2c_board_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.unb2c_board_pkg.all;
entity unb2c_board_system_info_reg is
generic (
@@ -68,7 +68,7 @@ entity unb2c_board_system_info_reg is
sla_out : out t_mem_miso;
info : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end unb2c_board_system_info_reg;
architecture rtl of unb2c_board_system_info_reg is
@@ -86,18 +86,19 @@ architecture rtl of unb2c_board_system_info_reg is
constant c_revision_id_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
constant c_design_note_offset : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
constant c_nof_regs : natural := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
-
- constant c_use_phy_w : natural := 8;
- constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
-
- constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
- constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
- constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
+
+ constant c_use_phy_w : natural := 8;
+ constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := (others => '0'); -- Unused but keep for compatibillity
+
+ constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
+ constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
+ constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
begin
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
index 4c53cdcc41f7c1f197a447530a4d6890ae6d0d48..cfef795756164f85b3cefdbc9d2f92983429d391 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Extend the input WDI that is controlled in SW (as it should be) to avoid
@@ -68,26 +68,26 @@ begin
nxt_wdi_out <= not i_wdi_out when wdi_cnt_en = '1' else i_wdi_out;
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => wdi_in,
- out_evt => wdi_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => wdi_in,
+ out_evt => wdi_evt
+ );
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => wdi_evt,
- cnt_en => wdi_cnt_en,
- count => wdi_cnt
- );
+ generic map (
+ g_width => g_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => wdi_evt,
+ cnt_en => wdi_cnt_en,
+ count => wdi_cnt
+ );
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index 6c9a33e3833702e9aeffa2a846dd915129136e1f..2f0459d286a6b053a163eaca46d3ffd9fa45341f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -24,9 +24,9 @@
-- Write 0xB007FAC7 to address 0x0.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity unb2c_board_wdi_reg is
port (
@@ -40,19 +40,20 @@ entity unb2c_board_wdi_reg is
-- MM registers in st_clk domain
wdi_override : out std_logic
- );
+ );
end unb2c_board_wdi_reg;
architecture rtl of unb2c_board_wdi_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- -- For safety, WDI override requires the following word to be written:
- constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
+ -- For safety, WDI override requires the following word to be written:
+ constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -60,7 +61,7 @@ begin
-- Read access
sla_out <= c_mem_miso_rst;
-- Write access, register values
- wdi_override <= '0';
+ wdi_override <= '0';
elsif rising_edge(mm_clk) then
-- Read access defaults: unused
sla_out <= c_mem_miso_rst;
@@ -68,7 +69,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
if sla_in.wrdata(c_word_w - 1 downto 0) = c_cmd_reconfigure then
wdi_override <= '1';
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
index 320d5febe60192f37cbbf7a5b57e4e152c719d76..d9442c1441de863edd4a468885469c839c575630 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk125_pll is
end tb_unb2c_board_clk125_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk125_pll
- port map (
- arst => ext_rst,
- clk125 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk125 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
index 4a035d2eb5a0a25872bae21f0151d62c0582edde..f0837780b54d7b17b55c50b6148f60f8d1368892 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk200_pll is
end tb_unb2c_board_clk200_pll;
@@ -66,44 +66,44 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_0,
- st_rst200 => st_rst200_0,
- st_clk200p => st_clk200p0,
- st_rst200p => st_rst200p0,
- st_clk400 => st_clk400,
- st_rst400 => st_rst400
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_0,
+ st_rst200 => st_rst200_0,
+ st_clk200p => st_clk200p0,
+ st_rst200p => st_rst200p0,
+ st_clk400 => st_clk400,
+ st_rst400 => st_rst400
+ );
dut_45 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "625",
- g_clk200p_phase_shift => "625"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => st_clk200_45,
- st_rst200 => st_rst200_45,
- st_clk200p => st_clk200p45,
- st_rst200p => st_rst200p45,
- st_clk400 => OPEN,
- st_rst400 => open
- );
+ generic map (
+ g_clk200_phase_shift => "625",
+ g_clk200p_phase_shift => "625"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => st_clk200_45,
+ st_rst200 => st_rst200_45,
+ st_clk200p => st_clk200p45,
+ st_rst200p => st_rst200p45,
+ st_clk400 => OPEN,
+ st_rst400 => open
+ );
dut_p6 : entity work.unb2c_board_clk200_pll
- generic map (
- g_clk200_phase_shift => "0"
- )
- port map (
- arst => ext_rst,
- clk200 => ext_clk,
- st_clk200 => dp_clk200,
- st_rst200 => dp_rst200
- );
+ generic map (
+ g_clk200_phase_shift => "0"
+ )
+ port map (
+ arst => ext_rst,
+ clk200 => ext_clk,
+ st_clk200 => dp_clk200,
+ st_rst200 => dp_rst200
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
index 9923168e21be66ac5518393923c47ae5457e6d05..f2563fc31c9620b6963bc72445c50e371ad11176 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
@@ -27,8 +27,8 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_clk25_pll is
end tb_unb2c_board_clk25_pll;
@@ -51,15 +51,15 @@ begin
ext_rst <= '1', '0' after c_ext_clk_period * 7;
dut_0 : entity work.unb2c_board_clk25_pll
- port map (
- arst => ext_rst,
- clk25 => ext_clk,
+ port map (
+ arst => ext_rst,
+ clk25 => ext_clk,
- c0_clk20 => c0_clk20,
- c1_clk50 => c1_clk50,
- c2_clk100 => c2_clk100,
- c3_clk125 => c3_clk125,
+ c0_clk20 => c0_clk20,
+ c1_clk50 => c1_clk50,
+ c2_clk100 => c2_clk100,
+ c3_clk125 => c3_clk125,
- pll_locked => pll_locked
- );
+ pll_locked => pll_locked
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
index a7a90847160de275f83afcbb6bb16352204cba95..152a4d3e6e799f4580d47d343f3578352cd03a30 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity tb_unb2c_board_node_ctrl is
end tb_unb2c_board_node_ctrl;
@@ -71,23 +71,23 @@ begin
wdi_in <= wdi and sw; -- sw wdi only when sw is active, during sw inactive the wdi_out will be extended
dut : entity work.unb2c_board_node_ctrl
- generic map (
- g_pulse_us => c_pulse_us,
- g_pulse_ms => c_pulse_ms,
- g_pulse_s => c_pulse_s,
- g_wdi_extend_w => c_wdi_extend_w
- )
- port map (
- -- MM clock domain reset
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
- -- WDI extend
- mm_wdi_in => wdi_in,
- mm_wdi_out => wdi_out,
- -- Pulses
- mm_pulse_us => pulse_us,
- mm_pulse_ms => pulse_ms,
- mm_pulse_s => pulse_s
- );
+ generic map (
+ g_pulse_us => c_pulse_us,
+ g_pulse_ms => c_pulse_ms,
+ g_pulse_s => c_pulse_s,
+ g_wdi_extend_w => c_wdi_extend_w
+ )
+ port map (
+ -- MM clock domain reset
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ -- WDI extend
+ mm_wdi_in => wdi_in,
+ mm_wdi_out => wdi_out,
+ -- Pulses
+ mm_pulse_us => pulse_us,
+ mm_pulse_ms => pulse_ms,
+ mm_pulse_s => pulse_s
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
index 9ee6059b7f62c1dc5c3ae93cc12772da27049228..1510caa6ed215fe19c635772b4e67ecf9543f531 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
@@ -37,17 +37,17 @@
-- > run -a
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_unb2c_board_qsfp_leds is
end tb_unb2c_board_qsfp_leds;
architecture tb of tb_unb2c_board_qsfp_leds is
- constant c_clk_freq_hz : natural := 200 * 10**6;
- constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
+ constant c_clk_freq_hz : natural := 200 * 10 ** 6;
+ constant c_clk_period_ns : natural := 10 ** 9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
constant clk_period : time := c_clk_period_ns * 1 ns;
@@ -139,48 +139,48 @@ begin
end process;
u_unb2c_factory_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => true, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => factory_green_led_arr,
- red_led_arr => factory_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => true, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => factory_green_led_arr,
+ red_led_arr => factory_red_led_arr
+ );
u_unb2c_user_qsfp_leds : entity work.unb2c_board_qsfp_leds
- generic map (
- g_sim => true, -- when true speed up led toggling in simulation
- g_factory_image => false, -- distinguish factory image and user images
- g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
- g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
- )
- port map (
- rst => rst,
- clk => clk,
- -- internal pulser outputs
- pulse_us => pulse_us,
- pulse_ms => pulse_ms,
- pulse_s => pulse_s,
- -- lane status
- tx_siso_arr => tx_siso_arr,
- tx_sosi_arr => tx_sosi_arr,
- rx_sosi_arr => rx_sosi_arr,
- -- leds
- green_led_arr => user_green_led_arr,
- red_led_arr => user_red_led_arr
- );
+ generic map (
+ g_sim => true, -- when true speed up led toggling in simulation
+ g_factory_image => false, -- distinguish factory image and user images
+ g_nof_qsfp => c_nof_qsfp, -- number of QSFP cages each with one dual led that can light red or green (or amber = red + green)
+ g_pulse_us => c_nof_clk_per_us -- nof clk cycles to get us period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- internal pulser outputs
+ pulse_us => pulse_us,
+ pulse_ms => pulse_ms,
+ pulse_s => pulse_s,
+ -- lane status
+ tx_siso_arr => tx_siso_arr,
+ tx_sosi_arr => tx_sosi_arr,
+ rx_sosi_arr => rx_sosi_arr,
+ -- leds
+ green_led_arr => user_green_led_arr,
+ red_led_arr => user_red_led_arr
+ );
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 92199c7404a1380dffa28b1478c66a69c87469fc..0fd65d94c62207638e1ccd37f5fafcda2910374c 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_pkg.all;
entity unb2c_board_10gbe is
generic (
@@ -78,17 +78,17 @@ architecture str of unb2c_board_10gbe is
signal tr_ref_rst_156 : std_logic;
begin
u_unb2c_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
- generic map (
- g_technology => g_technology
- )
- port map (
- refclk_644 => tr_ref_clk,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => open
- );
+ generic map (
+ g_technology => g_technology
+ )
+ port map (
+ refclk_644 => tr_ref_clk,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => open
+ );
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index e95d9eaf75c95c18f69917a472c173b12a9cfdf2..ba3f3097235169ef5e6b729ce286dcc25b6ffaf0 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -35,10 +35,10 @@
-- registers.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.axi4_lite_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.axi4_lite_pkg.all;
entity axi4_lite_mm_bridge is
generic (
@@ -106,12 +106,12 @@ begin
if mm_out_cipo.waitrequest = '0' and axi4_in_copi.wvalid = '1' then
d_bvalid <= '1';
- -- BVALID is acknowledged by BREADY, so deassert BVALID.
+ -- BVALID is acknowledged by BREADY, so deassert BVALID.
elsif axi4_in_copi.bready = '1' then
d_bvalid <= '0';
end if;
if i_rst = '1' then
- d_bvalid <= '0';
+ d_bvalid <= '0';
end if;
end process;
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 5ac1714290e644596277486858106640dece0453..faea6f119b3cc194fe081da668db7b141c5d8ce7 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
package axi4_lite_pkg is
------------------------------------------------------------------------------
@@ -98,7 +98,6 @@ package axi4_lite_pkg is
-- Functions to convert MM to axi4-lite.
function func_axi4_lite_from_mm_copi(mm_copi : t_mem_copi) return t_axi4_lite_copi;
function func_axi4_lite_from_mm_cipo(mm_cipo : t_mem_cipo; bvalid : std_logic) return t_axi4_lite_cipo;
-
end axi4_lite_pkg;
package body axi4_lite_pkg is
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 35b1086347c509af47361b9e044acf0ed57cf023..934a72044e751b11e0ee3210a8986794d5da6fb4 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -48,10 +48,10 @@
-- . AXI4 does not have a DP Xon or sync equivalent.
library IEEE, common_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.axi4_stream_pkg.all;
entity axi4_stream_dp_bridge is
generic (
@@ -113,20 +113,20 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_dp_to_axi : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_dp_rl,
- g_out_latency => g_axi4_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_in_sosi,
- snk_out => dp_in_siso,
-
- src_out => axi4_from_dp_sosi,
- src_in => axi4_from_dp_siso
- );
+ generic map (
+ g_in_latency => g_dp_rl,
+ g_out_latency => g_axi4_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_in_sosi,
+ snk_out => dp_in_siso,
+
+ src_out => axi4_from_dp_sosi,
+ src_in => axi4_from_dp_siso
+ );
----------------------------
-- Translate AXI4 to DP
@@ -177,18 +177,18 @@ begin
-- Adapt Ready Latency
u_dp_latency_adapter_axi_to_dp : entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_axi4_rl,
- g_out_latency => g_dp_rl
- )
- port map (
- clk => in_clk,
- rst => i_rst,
-
- snk_in => dp_from_axi4_sosi,
- snk_out => dp_from_axi4_siso,
-
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_in_latency => g_axi4_rl,
+ g_out_latency => g_dp_rl
+ )
+ port map (
+ clk => in_clk,
+ rst => i_rst,
+
+ snk_in => dp_from_axi4_sosi,
+ snk_out => dp_from_axi4_siso,
+
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index 43a42a80fdbb0942ad69bf4f8f2ad64c91f79c5b..977c317b0266cc275c39cb9e3a79c8c85fc88e6a 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -47,10 +47,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
package axi4_stream_pkg is
constant c_axi4_stream_data_w : natural := 512; -- Data width, upto 512bit for Xilinx IP
@@ -101,30 +101,34 @@ package axi4_stream_pkg is
type t_axi4_sosi_mat is array (integer range <>, integer range <>) of t_axi4_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_axi4_data_shift_first(head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi;
@@ -186,16 +190,16 @@ package axi4_stream_pkg is
-- Function to derive DP empty from AXI4 tkeep by counting the 0s in TKEEP.
function func_axi4_stream_tkeep_to_dp_empty(tkeep : std_logic_vector) return std_logic_vector;
-
end axi4_stream_pkg;
package body axi4_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.tready;
-- Register siso.ready in c_ready_latency registers
@@ -210,20 +214,22 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- Default RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi : in t_axi4_sosi;
- signal siso : in t_axi4_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_axi4_sosi;
+ signal siso : in t_axi4_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_axi4_siso_alert;
-- SOSI/SISO array version
- procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).tready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -241,10 +247,11 @@ package body axi4_stream_pkg is
end proc_axi4_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_axi4_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_axi4_sosi_arr;
- signal siso_arr : in t_axi4_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_axi4_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_axi4_sosi_arr;
+ signal siso_arr : in t_axi4_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_axi4_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_axi4_siso_alert;
@@ -720,7 +727,7 @@ package body axi4_stream_pkg is
function func_axi4_stream_from_dp_siso(dp_siso : t_dp_siso) return t_axi4_siso is
variable v_axi4_siso : t_axi4_siso := c_axi4_siso_rst;
- -- Note that dp_siso.xon is not used.
+ -- Note that dp_siso.xon is not used.
begin
v_axi4_siso.tready := dp_siso.ready;
return v_axi4_siso;
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
index d4cc4a03ccb806bb9eec3cd9fd20759ea80e4d95..077f43f735171b93356254bda457cf6ed61650e0 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
@@ -43,16 +43,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_textio.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.axi4_lite_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.std_logic_textio.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.axi4_lite_pkg.all;
entity tb_axi4_lite_mm_bridge is
end tb_axi4_lite_mm_bridge;
@@ -62,75 +62,75 @@ architecture tb of tb_axi4_lite_mm_bridge is
constant c_reset_len : natural := 4;
constant c_mm_usr_ram : t_c_mem := (latency => 1,
- adr_w => 5,
- dat_w => 8,
- nof_dat => 32,
- init_sl => '0');
- constant c_offset : natural := 57; -- Some value to offset the counter data written to ram.
+ adr_w => 5,
+ dat_w => 8,
+ nof_dat => 32,
+ init_sl => '0');
+ constant c_offset : natural := 57; -- Some value to offset the counter data written to ram.
- signal mm_rst : std_logic;
- signal mm_clk : std_logic := '0';
- signal tb_end : std_logic := '0';
+ signal mm_rst : std_logic;
+ signal mm_clk : std_logic := '0';
+ signal tb_end : std_logic := '0';
- signal mm_in_copi : t_mem_copi := c_mem_copi_rst;
- signal mm_in_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal mm_out_copi : t_mem_copi := c_mem_copi_rst;
- signal mm_out_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal ram_copi : t_mem_copi := c_mem_copi_rst;
- signal ram_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal mm_in_copi : t_mem_copi := c_mem_copi_rst;
+ signal mm_in_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal mm_out_copi : t_mem_copi := c_mem_copi_rst;
+ signal mm_out_cipo : t_mem_cipo := c_mem_cipo_rst;
+ signal ram_copi : t_mem_copi := c_mem_copi_rst;
+ signal ram_cipo : t_mem_cipo := c_mem_cipo_rst;
- signal axi_copi : t_axi4_lite_copi;
- signal axi_cipo : t_axi4_lite_cipo;
+ signal axi_copi : t_axi4_lite_copi;
+ signal axi_cipo : t_axi4_lite_cipo;
begin
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * c_reset_len;
-- DUT
u_axi4_lite_mm_bridge : entity work.axi4_lite_mm_bridge
- port map (
- in_clk => mm_clk,
- in_rst => mm_rst,
+ port map (
+ in_clk => mm_clk,
+ in_rst => mm_rst,
- axi4_in_copi => axi_copi,
- axi4_in_cipo => axi_cipo,
- mm_out_copi => mm_out_copi,
- mm_out_cipo => mm_out_cipo,
- mm_in_copi => mm_in_copi,
- mm_in_cipo => mm_in_cipo,
- axi4_out_copi => axi_copi,
- axi4_out_cipo => axi_cipo
- );
+ axi4_in_copi => axi_copi,
+ axi4_in_cipo => axi_cipo,
+ mm_out_copi => mm_out_copi,
+ mm_out_cipo => mm_out_cipo,
+ mm_in_copi => mm_in_copi,
+ mm_in_cipo => mm_in_cipo,
+ axi4_out_copi => axi_copi,
+ axi4_out_cipo => axi_cipo
+ );
-- Provide waitrequest stimuli to model a peripheral with MM flow control.
u_waitrequest_model : entity mm_lib.mm_waitrequest_model
- generic map (
- g_waitrequest => true,
- g_seed => c_offset
- )
- port map (
- mm_clk => mm_clk,
- bus_mosi => mm_out_copi,
- bus_miso => mm_out_cipo,
- slave_mosi => ram_copi,
- slave_miso => ram_cipo
- );
+ generic map (
+ g_waitrequest => true,
+ g_seed => c_offset
+ )
+ port map (
+ mm_clk => mm_clk,
+ bus_mosi => mm_out_copi,
+ bus_miso => mm_out_cipo,
+ slave_mosi => ram_copi,
+ slave_miso => ram_cipo
+ );
-- Use common ram as a MM peripherpal.
u_ram : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_mm_usr_ram
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- clken => '1',
- wr_en => ram_copi.wr,
- wr_dat => ram_copi.wrdata(c_mm_usr_ram.dat_w - 1 downto 0),
- wr_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
- rd_en => ram_copi.rd,
- rd_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
- rd_dat => ram_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0),
- rd_val => ram_cipo.rdval
- );
+ generic map (
+ g_ram => c_mm_usr_ram
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ clken => '1',
+ wr_en => ram_copi.wr,
+ wr_dat => ram_copi.wrdata(c_mm_usr_ram.dat_w - 1 downto 0),
+ wr_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
+ rd_en => ram_copi.rd,
+ rd_adr => ram_copi.address(c_mm_usr_ram.adr_w - 1 downto 0),
+ rd_dat => ram_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0),
+ rd_val => ram_cipo.rdval
+ );
-- Testbench writes/reads a number of words to/from memory through the axi4_lite_mm_bridge.
-- This tests the interface MM <-> AXI4-Lite <-> MM.
@@ -149,8 +149,8 @@ begin
proc_mem_mm_bus_rd(I, mm_clk, mm_in_cipo, mm_in_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
assert TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0)) = (c_offset + I) report
- "Wrong value read from RAM at address " & int_to_str(I) & " expected " & int_to_str(c_offset + I)
- & " but received " & int_to_str(TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0))) severity ERROR;
+ "Wrong value read from RAM at address " & int_to_str(I) & " expected " & int_to_str(c_offset + I)
+ & " but received " & int_to_str(TO_UINT(mm_in_cipo.rddata(c_mm_usr_ram.dat_w - 1 downto 0))) severity ERROR;
end loop;
tb_end <= '1';
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index ca7be826cff4b337bf5af9b2cbf58ae17568e978..0e784728f3745928b1e2ae95c793d28e8dd8e36b 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -26,12 +26,12 @@
-- DP stream. The resulting DP stream is verified.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.axi4_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.axi4_stream_pkg.all;
entity tb_axi4_stream_dp_bridge is
generic (
@@ -164,26 +164,26 @@ begin
dut_sosi.eop <= in_eop;
dut : entity work.axi4_stream_dp_bridge
- generic map (
- g_use_empty => true,
- g_axi4_rl => g_axi4_rl,
- g_dp_rl => g_dp_rl
- )
- port map (
- in_rst => rst,
- in_clk => clk,
- -- ST sink
- dp_in_siso => dut_siso,
- dp_in_sosi => dut_sosi,
- -- ST source
- dp_out_siso => dut_out_siso,
- dp_out_sosi => dut_out_sosi,
- -- AXI4 Loopback
- axi4_in_sosi => dut_axi4_sosi,
- axi4_in_siso => dut_axi4_siso,
- axi4_out_sosi => dut_axi4_sosi,
- axi4_out_siso => dut_axi4_siso
- );
+ generic map (
+ g_use_empty => true,
+ g_axi4_rl => g_axi4_rl,
+ g_dp_rl => g_dp_rl
+ )
+ port map (
+ in_rst => rst,
+ in_clk => clk,
+ -- ST sink
+ dp_in_siso => dut_siso,
+ dp_in_sosi => dut_sosi,
+ -- ST source
+ dp_out_siso => dut_out_siso,
+ dp_out_sosi => dut_out_sosi,
+ -- AXI4 Loopback
+ axi4_in_sosi => dut_axi4_sosi,
+ axi4_in_siso => dut_axi4_siso,
+ axi4_out_sosi => dut_axi4_sosi,
+ axi4_out_siso => dut_axi4_siso
+ );
-- map record to sl, slv
dut_out_siso.ready <= out_ready; -- SISO
diff --git a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
index 28f6ea68f5fde2c46683b3d4ba106953bf33f54e..ee636ba2b069cc96d9bf33730a679f2399d93aa1 100644
--- a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
@@ -25,7 +25,7 @@
-- ready-latency configurations.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_axi4_stream_dp_bridge is
end tb_tb_axi4_stream_dp_bridge;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm.vhd b/libraries/base/common/src/vhdl/avs_common_mm.vhd
index 3739dffc6fb10c697d1d436f1579c27e7bb02644..8a6932b17ce5def97baf06c23dd4c921e288fedd 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm.vhd
@@ -30,7 +30,7 @@
-- typically 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
index 1f9b9ac8d31a13d1c3507010069245c86a3f0cb6..da8aa33e94269fc49e2e3fa0a5d913413dd8a8ad 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
@@ -27,7 +27,7 @@
-- . The avs_common_mm_irq_hw.tcl determines the read latency, which is 1.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_irq is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
index 474b078567a7d8ecbae615e7da9c6b113fcd5064..d5765820e26caeb6adfbd952ad7e9867f2e4d1dc 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
@@ -29,7 +29,7 @@
-- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency0 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
index a3cdecdfc319d2832ee3ab0f55d1f30e0a154953..f11e33c9a042743d99d5daf3150d36d283b5dfee 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency2 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
index c07a16f315a1e24926a52571010dcebd847b7358..b9e68f8d6c379d190dfea70d61a1fda241fa20c6 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
@@ -28,7 +28,7 @@
-- avs_common_mm_hw.tcl.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity avs_common_mm_readlatency4 is
generic (
diff --git a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
index bdf118db203240608da8269776a38fd9b01df640..c683498e5e53d93f3a84aa7938669d00eb25db84 100644
--- a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
@@ -31,8 +31,8 @@
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
entity avs_common_ram_crw_crw is
generic ( -- t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
@@ -71,27 +71,27 @@ architecture wrap of avs_common_ram_crw_crw is
begin
u_common_ram_crw_crw : entity work.common_ram_crw_crw
generic map(
- g_ram => c_avs_memrec,
- g_init_file => g_init_file
+ g_ram => c_avs_memrec,
+ g_init_file => g_init_file
)
port map(
- rst_a => csi_system_reset,
- rst_b => coe_rst_export,
- clk_a => csi_system_clk,
- clk_b => coe_clk_export,
- clken_a => '1',
- clken_b => '1',
- wr_en_a => avs_ram_write,
- wr_en_b => coe_wr_en_export,
- wr_dat_a => avs_ram_writedata,
- wr_dat_b => coe_wr_dat_export,
- adr_a => avs_ram_address,
- adr_b => coe_adr_export,
- rd_en_a => avs_ram_read,
- rd_en_b => coe_rd_en_export,
- rd_dat_a => avs_ram_readdata,
- rd_dat_b => coe_rd_dat_export,
- rd_val_a => OPEN,
- rd_val_b => coe_rd_val_export
+ rst_a => csi_system_reset,
+ rst_b => coe_rst_export,
+ clk_a => csi_system_clk,
+ clk_b => coe_clk_export,
+ clken_a => '1',
+ clken_b => '1',
+ wr_en_a => avs_ram_write,
+ wr_en_b => coe_wr_en_export,
+ wr_dat_a => avs_ram_writedata,
+ wr_dat_b => coe_wr_dat_export,
+ adr_a => avs_ram_address,
+ adr_b => coe_adr_export,
+ rd_en_a => avs_ram_read,
+ rd_en_b => coe_rd_en_export,
+ rd_dat_a => avs_ram_readdata,
+ rd_dat_b => coe_rd_dat_export,
+ rd_val_a => OPEN,
+ rd_val_b => coe_rd_val_export
);
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
index dda794990475e9aefaf176f3c733ca25536ea4f0..c9ea1cc9e42156c88b2f96184352a7013861e658 100644
--- a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
@@ -31,9 +31,9 @@
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity avs_common_reg_r_w is
generic (
diff --git a/libraries/base/common/src/vhdl/common_acapture.vhd b/libraries/base/common/src/vhdl/common_acapture.vhd
index cd7ccca147cefb9c3a43031cac01e9f006b9feb4..5f8cc188c62bbae6dd6047dff00d4fd311d3b453 100644
--- a/libraries/base/common/src/vhdl/common_acapture.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture.vhd
@@ -38,8 +38,8 @@
-- = 1 could be used.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture is
generic (
@@ -64,28 +64,28 @@ begin
-- pipeline input (all in input clock domain)
u_async_in : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => in_rst,
- clk => in_clk,
- din => in_dat,
- dout => i_in_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => i_in_cap
+ );
-- capture input into output clock domain with first FF, and
-- additional pipeline output with extra FF when g_out_delay_len > 1 to combat potential meta-stability
u_async_out : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => in_rst,
- clk => out_clk,
- din => i_in_cap,
- dout => out_cap
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => out_clk,
+ din => i_in_cap,
+ dout => out_cap
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_acapture_slv.vhd b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
index 04aa1970550e15f5ae0aececbf10ef805c9ac595..b986512afc0e3f95dbb1ed1c70f1e90aabd77e55 100644
--- a/libraries/base/common/src/vhdl/common_acapture_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
@@ -27,8 +27,8 @@
-- fit in 1 LAB if in_dat'LENGTH <= 10.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_acapture_slv is
generic (
@@ -51,19 +51,18 @@ architecture str of common_acapture_slv is
begin
gen_slv: for I in in_dat'range generate
u_acap : entity work.common_acapture
- generic map (
- g_rst_level => g_rst_level,
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat(I),
- in_cap => in_cap(I),
- out_clk => out_clk,
- out_cap => out_cap(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ in_cap => in_cap(I),
+ out_clk => out_clk,
+ out_cap => out_cap(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index f891ae560a8572449a100e2decf05c2ba05d161f..ee0479631ad880634f3870031427316b0ccd564b 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -26,9 +26,9 @@
-- active.
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_accumulate is
generic (
@@ -46,9 +46,9 @@ entity common_accumulate is
end common_accumulate;
architecture rtl of common_accumulate is
- constant c_acc_w : natural := out_dat'length;
+ constant c_acc_w : natural := out_dat'length;
- signal result : std_logic_vector(c_acc_w - 1 downto 0);
+ signal result : std_logic_vector(c_acc_w - 1 downto 0);
begin
process(rst, clk)
begin
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 62efa07c4d9682dbd8c1b8c7721ab17225a65af4..1402702d416a349839219fa37be4cae83bc7f172 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_add_sub is
generic (
@@ -60,7 +60,9 @@ begin
in_b_p <= in_b;
sel_add_p <= in_add;
end generate;
+
gen_input_reg : if g_pipeline_input > 0 generate -- register input
+
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -82,16 +84,16 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result_p(result'range),
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result_p(result'range),
+ out_dat => result
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_add_symbol.vhd b/libraries/base/common/src/vhdl/common_add_symbol.vhd
index 5472ab24a520321e4d79867d46b065d7c24ab83b..8e9ebf1583567481b19705f01fe6f34179ab3162 100644
--- a/libraries/base/common/src/vhdl/common_add_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_add_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol add of the two input data stream
-- Description:
@@ -79,49 +79,49 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_symbols * g_symbol_w,
- g_out_dat_w => g_nof_symbols * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sum_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_symbols * g_symbol_w,
+ g_out_dat_w => g_nof_symbols * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sum_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_adder_staged.vhd b/libraries/base/common/src/vhdl/common_adder_staged.vhd
index fe3c110aa9c35162249b14efd8e3566f6c0e5ab4..67fea2fa9aca7ace9ec5fea5cb65b5219cf86be9 100644
--- a/libraries/base/common/src/vhdl/common_adder_staged.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_staged.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Status:
-- . Compiles OK, but still needs to be functionally verified with a test bench.
@@ -84,41 +84,41 @@ architecture str of common_adder_staged is
begin
assert not(g_pipeline_output < c_nof_adder and g_adder_w < g_dat_w)
report "common_adder_staged: internal adder width < output adder width is only possible for pipeline >= nof adder"
- severity FAILURE;
+ severity FAILURE;
------------------------------------------------------------------------------
-- Input
------------------------------------------------------------------------------
u_pipe_a : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_input,
- g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat_a,
- out_dat => reg_dat_a
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_input,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat_a,
+ out_dat => reg_dat_a
+ );
u_pipe_b : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_input,
- g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat_b,
- out_dat => reg_dat_b
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_input,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat_b,
+ out_dat => reg_dat_b
+ );
------------------------------------------------------------------------------
-- Multiple adder sections (g_adder_w < g_dat_w)
@@ -166,28 +166,6 @@ begin
m_b(0, SECTION) <= vec_dat_b((SECTION + 1) * g_adder_w - 1 downto SECTION * g_adder_w);
u_stage_add_input : entity common_lib.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => "UNSIGNED", -- must treat the sections as unsigned
- g_pipeline_input => 0,
- g_pipeline_output => 1,
- g_in_dat_w => g_adder_w,
- g_out_dat_w => g_adder_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => m_a(0, SECTION),
- in_b => m_b(0, SECTION),
- result => m_sum(0, SECTION)
- );
-
- gen_stage : for STAGE in 1 to c_nof_adder - 1 generate
- m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0); -- sum from preceding stage
- m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w); -- carry from less significant section in preceding stage
-
- -- Adder stages to add and propagate the carry for each section
- u_add_carry : entity common_lib.common_add_sub
generic map (
g_direction => "ADD",
g_representation => "UNSIGNED", -- must treat the sections as unsigned
@@ -199,10 +177,32 @@ begin
port map (
clk => clk,
clken => clken,
- in_a => m_a(STAGE, SECTION),
- in_b => m_b(STAGE, SECTION), -- + carry 0 or 1 from the less significant adder section
- result => m_sum(STAGE, SECTION)
+ in_a => m_a(0, SECTION),
+ in_b => m_b(0, SECTION),
+ result => m_sum(0, SECTION)
);
+
+ gen_stage : for STAGE in 1 to c_nof_adder - 1 generate
+ m_a(STAGE, SECTION) <= m_sum(STAGE-1, SECTION )(g_adder_w - 1 downto 0); -- sum from preceding stage
+ m_b(STAGE, SECTION) <= RESIZE_UVEC(m_sum(STAGE-1, SECTION - 1)(g_adder_w), g_adder_w); -- carry from less significant section in preceding stage
+
+ -- Adder stages to add and propagate the carry for each section
+ u_add_carry : entity common_lib.common_add_sub
+ generic map (
+ g_direction => "ADD",
+ g_representation => "UNSIGNED", -- must treat the sections as unsigned
+ g_pipeline_input => 0,
+ g_pipeline_output => 1,
+ g_in_dat_w => g_adder_w,
+ g_out_dat_w => g_adder_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => m_a(STAGE, SECTION),
+ in_b => m_b(STAGE, SECTION), -- + carry 0 or 1 from the less significant adder section
+ result => m_sum(STAGE, SECTION)
+ );
end generate;
-- map the adder sections from the last stage to the output to slv
@@ -211,39 +211,39 @@ begin
-- Rest output pipeline
u_out_val : entity common_lib.common_pipeline
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline_output - c_nof_adder,
+ g_reset_value => 0,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => vec_add(g_dat_w - 1 downto 0), -- resize length of multiple g_adder_w back to g_dat_w width
+ out_dat => out_dat
+ );
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Parallel output control pipeline
+ ------------------------------------------------------------------------------
+
+ u_out_val : entity common_lib.common_pipeline
generic map (
g_representation => "UNSIGNED",
- g_pipeline => g_pipeline_output - c_nof_adder,
+ g_pipeline => c_pipeline,
g_reset_value => 0,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
)
port map (
clk => clk,
clken => clken,
- in_dat => vec_add(g_dat_w - 1 downto 0), -- resize length of multiple g_adder_w back to g_dat_w width
- out_dat => out_dat
+ in_dat => in_val_slv,
+ out_dat => out_val_slv
);
- end generate;
-
- ------------------------------------------------------------------------------
- -- Parallel output control pipeline
- ------------------------------------------------------------------------------
-
- u_out_val : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_val_slv,
- out_dat => out_val_slv
- );
in_val_slv(0) <= in_val;
out_val <= out_val_slv(0);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree.vhd b/libraries/base/common/src/vhdl/common_adder_tree.vhd
index 7d95c7b027a51d4b8950a204350a2dfc3463bd16..a22b17f11dcf86e5f374d8ee1ec9cab4966bac94 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Parallel adder tree.
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index ece19109a02fba5b375d21bd4325a91e3215ac31..e06b346d2a66b4e1bfd07d1e2c5c3c05b67fe0cf 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture recursive of common_adder_tree is
-- common_add_sub pipelining
@@ -36,7 +36,7 @@ architecture recursive of common_adder_tree is
variable v_ret : boolean := false;
begin
if h1 > 1 then
- if h1 = 2**ceil_log2(h1) and h2 = h1 + 1 then
+ if h1 = 2 ** ceil_log2(h1) and h2 = h1 + 1 then
v_ret := true;
end if;
end if;
@@ -77,37 +77,37 @@ architecture recursive of common_adder_tree is
begin
leaf_pipe : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => result
+ );
end generate;
leaf_add : if g_nof_inputs = 2 generate
u_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_dat( g_dat_w - 1 downto 0 ),
- in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
- result => result
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => c_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_dat( g_dat_w - 1 downto 0 ),
+ in_b => in_dat(2 * g_dat_w - 1 downto g_dat_w),
+ result => result
+ );
end generate;
gen_tree : if g_nof_inputs > 2 generate
@@ -147,36 +147,36 @@ begin
gen_reg_h1 : if c_stage_h1 = true generate
u_reg_h1 : entity work.common_pipeline
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_sum_h1_w,
+ g_out_dat_w => c_sum_h2_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => sum_h1,
+ out_dat => sum_h1_reg
+ );
+ end generate;
+
+ trunk_add : entity work.common_add_sub
generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_sum_h1_w,
- g_out_dat_w => c_sum_h2_w
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_sum_h_w,
+ g_out_dat_w => c_sum_w
)
port map (
clk => clk,
clken => clken,
- in_dat => sum_h1,
- out_dat => sum_h1_reg
+ in_a => sum_h1_reg,
+ in_b => sum_h2,
+ result => result
);
- end generate;
-
- trunk_add : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_sum_h_w,
- g_out_dat_w => c_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => sum_h1_reg,
- in_b => sum_h2,
- result => result
- );
end generate;
sum <= RESIZE_SVEC(result, g_sum_w) when g_representation = "SIGNED" else RESIZE_UVEC(result, g_sum_w);
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 579de011dc92e04ab491bea1fa48c23370b155f9..7dfdc6fb752a03c8f3a6e4726441711e19099980 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
architecture str of common_adder_tree is
-- common_add_sub pipelining
@@ -89,47 +89,48 @@ begin
-- Adder tree
gen_stage : for j in 0 to c_nof_stages - 1 generate
- gen_add : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
+
+ gen_add : for i in 0 to (c_N + (2 ** j) - 1) / (2 ** (j + 1)) - 1 generate
u_addj : entity work.common_add_sub
- generic map (
- g_direction => "ADD",
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
- in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
- result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
- );
+ generic map (
+ g_direction => "ADD",
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => adds(j - 1)((2 * i + 1) * (c_w + j) - 1 downto (2 * i + 0) * (c_w + j)),
+ in_b => adds(j - 1)((2 * i + 2) * (c_w + j) - 1 downto (2 * i + 1) * (c_w + j)),
+ result => adds(j)((i + 1) * (c_w + j + 1) - 1 downto i * (c_w + j + 1))
+ );
end generate;
- gen_pipe : if ((c_N + (2**j) - 1) / (2**j)) mod 2 /= 0 generate
+ gen_pipe : if ((c_N + (2 ** j) - 1) / (2 ** j)) mod 2 /= 0 generate
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => c_w + j,
- g_out_dat_w => c_w + j + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => adds(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * (c_w + j) - 1 downto
- (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * (c_w + j)),
- out_dat => adds(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * (c_w + j + 1) - 1 downto
- ((c_N + (2**j) - 1) / (2**(j + 1)) ) * (c_w + j + 1))
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_w + j,
+ g_out_dat_w => c_w + j + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => adds(j - 1)((2 * ((c_N + (2 ** j) - 1) / (2 ** (j + 1))) + 1) * (c_w + j) - 1 downto
+ (2 * ((c_N + (2 ** j) - 1) / (2 ** (j + 1))) + 0) * (c_w + j)),
+ out_dat => adds(j)(((c_N + (2 ** j) - 1) / (2 ** (j + 1)) + 1) * (c_w + j + 1) - 1 downto
+ ((c_N + (2 ** j) - 1) / (2 ** (j + 1)) ) * (c_w + j + 1))
+ );
end generate;
end generate;
-- Map final sum to larger output vector using sign extension or to smaller width output vector preserving the LS part
sum <= RESIZE_SVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w) when g_representation = "SIGNED" else
- RESIZE_UVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w);
+ RESIZE_UVEC(adds(c_nof_stages - 1)(c_sum_w - 1 downto 0), g_sum_w);
end generate; -- gen_tree
no_tree : if g_nof_inputs = 1 generate
@@ -138,18 +139,17 @@ begin
-- g_dat_w+1 also for g_nof_inputs = 1, because we assume an adder stage
-- that adds 0 to the single in_dat.
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => sum
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => sum
+ );
end generate; -- no_tree
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 13c3a2454c660456b76f0b0f3bfc1d6da2f559bb..e0e4232ad4dc7887f95f458cc161477e700f8a6e 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -32,14 +32,14 @@
-- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_areset is
generic (
g_in_rst_level : std_logic := '1'; -- = in_rst level
g_rst_level : std_logic := '1'; -- = out_rst level (keep original generic
- -- name for backward compatibility)
+ -- name for backward compatibility)
g_delay_len : natural := c_meta_delay_len
);
port (
@@ -58,14 +58,14 @@ begin
i_rst <= in_rst when g_in_rst_level = '1' else not in_rst;
u_async : entity work.common_async
- generic map (
- g_rst_level => c_out_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => i_rst,
- clk => clk,
- din => c_out_rst_level_n,
- dout => out_rst
- );
+ generic map (
+ g_rst_level => c_out_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => i_rst,
+ clk => clk,
+ din => c_out_rst_level_n,
+ dout => out_rst
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index e4a037445b3ae691e19928183db6d9b16ceb4ab2..26eb0e144d4d03a63726b44b016016c50c6092dd 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -24,8 +24,8 @@
-- The delay line combats the potential meta-stability of clocked in data.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_async is
generic (
diff --git a/libraries/base/common/src/vhdl/common_async_slv.vhd b/libraries/base/common/src/vhdl/common_async_slv.vhd
index 1ff3d1454aa4e77e1fa5d8d5ecb3baf01b0638a1..8dc09110f0650b3eaa0eb324eb7a0f59d569b97a 100644
--- a/libraries/base/common/src/vhdl/common_async_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_async_slv.vhd
@@ -25,8 +25,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_async_slv is
generic (
@@ -45,16 +45,15 @@ architecture str of common_async_slv is
begin
gen_slv: for I in dout'range generate
u_common_async : entity work.common_async
- generic map (
- g_rst_level => g_rst_level,
- g_delay_len => g_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => din(I),
- dout => dout(I)
- );
+ generic map (
+ g_rst_level => g_rst_level,
+ g_delay_len => g_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => din(I),
+ dout => dout(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_bit_delay.vhd b/libraries/base/common/src/vhdl/common_bit_delay.vhd
index 2f3dc51f730b5771ed3e96042eddf0bd2008d950..a23cecb6782f49a361d6aa99cee1be4560bf99cb 100644
--- a/libraries/base/common/src/vhdl/common_bit_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_bit_delay.vhd
@@ -34,7 +34,7 @@
-- to remove in_clr or to not use shift_reg(0) combinatorially.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_bit_delay is
generic (
@@ -60,6 +60,7 @@ begin
out_bit <= shift_reg(g_depth);
gen_reg : if g_depth > 0 generate
+
p_clk : process(clk, rst)
begin
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_blockreg.vhd b/libraries/base/common/src/vhdl/common_blockreg.vhd
index dafbf3163e97e2d30a30e1a304fe6e60c2980d23..edc0b1bfdf8a88106e0f01581851fb485d74ca9a 100755
--- a/libraries/base/common/src/vhdl/common_blockreg.vhd
+++ b/libraries/base/common/src/vhdl/common_blockreg.vhd
@@ -37,10 +37,10 @@
-- valid-dependent like the rest).
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_blockreg is
generic (
@@ -79,73 +79,73 @@ begin
out_val <= i_out_val;
u_fifo : entity work.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false,
- g_dat_w => g_dat_w,
- g_nof_words => g_block_size+1
- )
- port map (
- clk => clk,
- rst => rst,
-
- wr_dat => in_dat,
- wr_req => in_val,
-
- usedw => usedw,
- rd_req => rd_req,
-
- rd_dat => out_dat,
- rd_val => i_out_val
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false,
+ g_dat_w => g_dat_w,
+ g_nof_words => g_block_size+1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ wr_dat => in_dat,
+ wr_req => in_val,
+
+ usedw => usedw,
+ rd_req => rd_req,
+
+ rd_dat => out_dat,
+ rd_val => i_out_val
);
- -----------------------------------------------------------------------------
- -- Toggle rd_req to create output blocks of g_block_size
- -----------------------------------------------------------------------------
- p_block_out: process(in_val, prev_rd_req, out_cnt, usedw)
- begin
- rd_req <= prev_rd_req;
- if unsigned(out_cnt) = g_block_size-1 then
- -- End of current output block
- if unsigned(usedw) < g_block_size then
- -- de-asserting rd_req will not cause FIFO to overflow
- rd_req <= '0';
- end if;
- end if;
- if unsigned(usedw) = g_block_size then
- -- Start of new output block
- rd_req <= '1';
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- Valid output word counter
- -----------------------------------------------------------------------------
- p_out_cnt : process(i_out_val, out_cnt)
- begin
- nxt_out_cnt <= out_cnt;
- if i_out_val = '1' then
- nxt_out_cnt <= INCR_UVEC(out_cnt, 1);
- if unsigned(out_cnt) = g_block_size-1 then
- nxt_out_cnt <= (others => '0');
- end if;
- end if;
- end process;
-
- -----------------------------------------------------------------------------
- -- Registers
- -----------------------------------------------------------------------------
- p_clk : process(rst, clk)
- begin
- if rst = '1' then
- out_cnt <= (others => '0');
- prev_rd_req <= '0';
- elsif rising_edge(clk) then
- out_cnt <= nxt_out_cnt;
- prev_rd_req <= rd_req;
- end if;
- end process;
-
- end generate;
+-----------------------------------------------------------------------------
+-- Toggle rd_req to create output blocks of g_block_size
+-----------------------------------------------------------------------------
+p_block_out: process(in_val, prev_rd_req, out_cnt, usedw)
+begin
+ rd_req <= prev_rd_req;
+ if unsigned(out_cnt) = g_block_size-1 then
+ -- End of current output block
+ if unsigned(usedw) < g_block_size then
+ -- de-asserting rd_req will not cause FIFO to overflow
+ rd_req <= '0';
+ end if;
+ end if;
+ if unsigned(usedw) = g_block_size then
+ -- Start of new output block
+ rd_req <= '1';
+ end if;
+end process;
+
+-----------------------------------------------------------------------------
+-- Valid output word counter
+-----------------------------------------------------------------------------
+p_out_cnt : process(i_out_val, out_cnt)
+begin
+ nxt_out_cnt <= out_cnt;
+ if i_out_val = '1' then
+ nxt_out_cnt <= INCR_UVEC(out_cnt, 1);
+ if unsigned(out_cnt) = g_block_size-1 then
+ nxt_out_cnt <= (others => '0');
+ end if;
+ end if;
+end process;
+
+-----------------------------------------------------------------------------
+-- Registers
+-----------------------------------------------------------------------------
+p_clk : process(rst, clk)
+begin
+ if rst = '1' then
+ out_cnt <= (others => '0');
+ prev_rd_req <= '0';
+ elsif rising_edge(clk) then
+ out_cnt <= nxt_out_cnt;
+ prev_rd_req <= rd_req;
+ end if;
+end process;
+
+end generate;
end str;
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 3f83c3d3a8f2e3619b68628d4eb50e844afd8fb4..51359bc566ed98e04c5f6b2c02cad2bd53c3e400 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Function:
-- When enabled clip input, else pass input on unchanged. Report clippled
@@ -100,6 +100,7 @@ begin
end generate;
gen_reg : if g_pipeline > 0 generate
+
p_clk : process (rst, clk)
begin
if rst = '1' then
@@ -118,18 +119,18 @@ begin
pipe_in <= clip_ovr & clip_dat;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => c_output_pipe,
- g_in_dat_w => c_dat_w + 1,
- g_out_dat_w => c_dat_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => pipe_in,
- out_dat => pipe_out
- );
+ generic map (
+ g_pipeline => c_output_pipe,
+ g_in_dat_w => c_dat_w + 1,
+ g_out_dat_w => c_dat_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_in,
+ out_dat => pipe_out
+ );
out_ovr <= pipe_out(pipe_out'high);
out_dat <= pipe_out(pipe_out'high - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
index 246e57815e02004d836e322758e8a0a0fa722060..fb70ba3e8874ddfae3b4bd06d0b24397f1db5a5a 100644
--- a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Detect 400 MHz in_clk active in the 200 MHz dp_clk domain
-- Description:
@@ -51,7 +51,7 @@ architecture str of common_clock_active_detector is
constant c_dp_detect_max : natural := g_dp_detect_period + g_dp_detect_margin;
constant c_dp_detect_min : natural := g_dp_detect_period - g_dp_detect_margin;
constant c_dp_clk_cnt_w : natural := c_dp_detect_period_w + 1; -- +1 to be wide enough to fit somewhat more than maximum nof clock cycles per interval
- constant c_dp_clk_cnt_max : natural := 2**c_dp_clk_cnt_w - 1;
+ constant c_dp_clk_cnt_max : natural := 2 ** c_dp_clk_cnt_w - 1;
signal dbg_g_in_period_w : natural := g_in_period_w;
signal dbg_g_dp_detect_period : natural := g_dp_detect_period;
@@ -74,55 +74,55 @@ architecture str of common_clock_active_detector is
signal nxt_dp_in_clk_detected : std_logic;
begin
u_common_counter_in_clk : entity work.common_counter
- generic map (
- g_width => g_in_period_w
- )
- port map (
- rst => '0',
- clk => in_clk,
- count => in_clk_cnt
- );
+ generic map (
+ g_width => g_in_period_w
+ )
+ port map (
+ rst => '0',
+ clk => in_clk,
+ count => in_clk_cnt
+ );
in_toggle <= in_clk_cnt(in_clk_cnt'high);
u_common_async_dp_toggle : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- din => in_toggle,
- dout => dp_toggle
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => in_toggle,
+ dout => dp_toggle
+ );
u_common_evt : entity work.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => dp_toggle,
- out_evt => dp_toggle_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => dp_toggle,
+ out_evt => dp_toggle_revt
+ );
dp_clk_cnt_en <= '1' when unsigned(dp_clk_cnt) < c_dp_clk_cnt_max else '0';
dp_clk_cnt_clr <= dp_toggle_revt or not dp_clk_cnt_en;
u_common_counter_dp_clk : entity work.common_counter
- generic map (
- g_width => c_dp_clk_cnt_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => dp_clk_cnt_clr,
- cnt_en => dp_clk_cnt_en,
- count => dp_clk_cnt
- );
+ generic map (
+ g_width => c_dp_clk_cnt_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => dp_clk_cnt_clr,
+ cnt_en => dp_clk_cnt_en,
+ count => dp_clk_cnt
+ );
nxt_dp_clk_interval <= INCR_UVEC(dp_clk_cnt, 1) when dp_clk_cnt_clr = '1' else dp_clk_interval;
@@ -142,12 +142,12 @@ begin
dp_in_clk_detected <= i_dp_in_clk_detected;
u_common_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM
- r_in => i_dp_in_clk_detected,
- r_stable => dp_in_clk_stable,
- r_stable_ack => dp_in_clk_stable_ack
- );
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM
+ r_in => i_dp_in_clk_detected,
+ r_stable => dp_in_clk_stable,
+ r_stable_ack => dp_in_clk_stable_ack
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index b44ac564c54ada7d1b705da5abfb70621982ca9f..75a84912a017e2857fd155662b9637c0c974b485 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -93,8 +93,8 @@
-- pipeline stage.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_clock_phase_detector is
generic (
@@ -129,17 +129,17 @@ architecture str of common_clock_phase_detector is
begin
-- Capture the in_clk in the clk domain
u_async : entity work.common_async
- generic map (
- g_rising_edge => g_rising_edge,
- g_rst_level => g_phase_rst_level,
- g_delay_len => c_delay_len
- )
- port map (
- rst => rst,
- clk => clk,
- din => in_clk,
- dout => in_phs_cap
- );
+ generic map (
+ g_rising_edge => g_rising_edge,
+ g_rst_level => g_phase_rst_level,
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ din => in_clk,
+ dout => in_phs_cap
+ );
-- Process the registers in the rising edge clk domain
gen_r_wire : if g_rising_edge = true generate
diff --git a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
index 51192d7b4cfa2b8384e059dc685887e0e1ea59d6..1fa4bff9b0a56309bcb63e24b23e410d658f4c61 100644
--- a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_add_sub is
generic (
@@ -46,36 +46,36 @@ end common_complex_add_sub;
architecture str of common_complex_add_sub is
begin
add_re : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ar,
- in_b => in_br,
- result => out_re
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ar,
+ in_b => in_br,
+ result => out_re
+ );
add_im : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => g_representation,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => in_ai,
- in_b => in_bi,
- result => out_im
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => g_representation,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => in_ai,
+ in_b => in_bi,
+ result => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_complex_round.vhd b/libraries/base/common/src/vhdl/common_complex_round.vhd
index b365d78a728e29d04f4c6392d1368faa057cd1d2..71336ba9c152217b04c3b292bfb485710d49092b 100644
--- a/libraries/base/common/src/vhdl/common_complex_round.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_round.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_complex_round is
generic (
@@ -45,36 +45,36 @@ end;
architecture str of common_complex_round is
begin
re: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_re,
- out_dat => out_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_re,
+ out_dat => out_re
+ );
im: entity work.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_round,
- g_round_clip => g_round_clip,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_im,
- out_dat => out_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_round,
+ g_round_clip => g_round_clip,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_im,
+ out_dat => out_im
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_components_pkg.vhd b/libraries/base/common/src/vhdl/common_components_pkg.vhd
index ba5e04a595382f2f4586cf619f49c9088b596572..760521dec02ced99b5fc3afd222ef20b4456f0f5 100644
--- a/libraries/base/common/src/vhdl/common_components_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_components_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Purpose: Component declarations to check positional mapping
-- Description:
@@ -30,22 +30,22 @@ use work.common_mem_pkg.all;
package common_components_pkg is
component common_pipeline is
- generic (
- g_representation : string := "SIGNED"; -- or "UNSIGNED"
- g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
- g_reset_value : integer := 0;
- g_in_dat_w : natural := 8;
- g_out_dat_w : natural := 9
- );
- port (
- rst : in std_logic := '0';
- clk : in std_logic;
- clken : in std_logic := '1';
- in_clr : in std_logic := '0';
- in_en : in std_logic := '1';
- in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
- out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
- );
+ generic (
+ g_representation : string := "SIGNED"; -- or "UNSIGNED"
+ g_pipeline : natural := 1; -- 0 for wires, > 0 for registers,
+ g_reset_value : integer := 0;
+ g_in_dat_w : natural := 8;
+ g_out_dat_w : natural := 9
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_clr : in std_logic := '0';
+ in_en : in std_logic := '1';
+ in_dat : in std_logic_vector(g_in_dat_w - 1 downto 0);
+ out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
+ );
end component;
component common_pipeline_sl is
@@ -64,7 +64,6 @@ package common_components_pkg is
out_dat : out std_logic
);
end component;
-
end common_components_pkg;
package body common_components_pkg is
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index e5a449527e4e92286d1a16288bdd937d53aacd50..0f17e2262f9910f2dd272f99158bc5ec503f78d5 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -33,8 +33,8 @@
-- via ceil_log2(g_max+1)>g_width and use this to init the cnt_max input.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_counter is
generic (
@@ -53,9 +53,9 @@ entity common_counter is
cnt_ld : in std_logic := '0'; -- cnt_ld loads the output count with the input load value, independent of cnt_en
cnt_en : in std_logic := '1';
cnt_max : in std_logic_vector(g_width - 1 downto 0) := sel_a_b( g_step_size > 0 and g_max = 0, array_init('1', g_width),
- sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) )); -- see remarks
- load : in std_logic_vector(g_width - 1 downto 0) := TO_SVEC(g_init, g_width);
- count : out std_logic_vector(g_width - 1 downto 0)
+ sel_a_b( ceil_log2(g_max + 1) > g_width, array_init('1', g_width), TO_UVEC(g_max, g_width) )); -- see remarks
+ load : in std_logic_vector(g_width - 1 downto 0) := TO_SVEC(g_init, g_width);
+ count : out std_logic_vector(g_width - 1 downto 0)
);
end common_counter;
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
index a89e287f0db450947d3f56c963cfedf0de9b350d..cbae24e8100195809af4f4aa893cd23001c2cabc 100644
--- a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -50,8 +50,8 @@
-- out_sop and other strobes.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_create_strobes_from_valid is
generic (
diff --git a/libraries/base/common/src/vhdl/common_ddio_in.vhd b/libraries/base/common/src/vhdl/common_ddio_in.vhd
index 4a1e3e3d6ce1ceaa3c5293c857a6152c54fd22e1..a179198b617bc606e81728d55877a5d69383ff68 100644
--- a/libraries/base/common/src/vhdl/common_ddio_in.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Capture double data rate FPGA input
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_in is
generic(
@@ -43,16 +43,16 @@ end common_ddio_in;
architecture str of common_ddio_in is
begin
u_ddio_in : entity tech_iobuf_lib.tech_iobuf_ddio_in
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- in_dat => in_dat,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- rst => rst,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ in_dat => in_dat,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ rst => rst,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddio_out.vhd b/libraries/base/common/src/vhdl/common_ddio_out.vhd
index 1806830f51293749c4f2ae4e6e1ddfd79f16ce4a..68db6376c8e304ee821ed04aa2a44fbccf1e80d6 100644
--- a/libraries/base/common/src/vhdl/common_ddio_out.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_out.vhd
@@ -22,8 +22,8 @@
-- Purpose: Double data rate FPGA output or register single data rate FPGA output
library IEEE, technology_lib, tech_iobuf_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ddio_out is
generic(
@@ -43,16 +43,16 @@ end common_ddio_out;
architecture str of common_ddio_out is
begin
u_ddio_out : entity tech_iobuf_lib.tech_iobuf_ddio_out
- generic map (
- g_technology => g_technology,
- g_width => g_width
- )
- port map (
- rst => rst,
- in_clk => in_clk,
- in_clk_en => in_clk_en,
- in_dat_hi => in_dat_hi,
- in_dat_lo => in_dat_lo,
- out_dat => out_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_width => g_width
+ )
+ port map (
+ rst => rst,
+ in_clk => in_clk,
+ in_clk_en => in_clk_en,
+ in_dat_hi => in_dat_hi,
+ in_dat_lo => in_dat_lo,
+ out_dat => out_dat
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg.vhd b/libraries/base/common/src/vhdl/common_ddreg.vhd
index 74638cc7e16c677257c6e2b8b9d7b9690be4212e..6289cd167521cb5f9074aa6a303b0d2d881d61e9 100644
--- a/libraries/base/common/src/vhdl/common_ddreg.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg.vhd
@@ -70,8 +70,8 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_r is
generic (
@@ -93,29 +93,29 @@ architecture str of common_ddreg_r is
signal in_dat_d : std_logic;
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_hi = false else in_dat_r when rising_edge(out_clk);
-- Output at rising edge
u_out_hi : entity work.common_async
- generic map (
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_r
- );
+ generic map (
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_r
+ );
end str;
--------------------------------------------------------------------------------
@@ -123,8 +123,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_f is
generic (
@@ -146,30 +146,30 @@ architecture str of common_ddreg_f is
signal in_dat_d : std_logic;
begin
u_in : entity work.common_async
- generic map (
- g_delay_len => g_in_delay_len
- )
- port map (
- rst => rst,
- clk => in_clk,
- din => in_dat,
- dout => in_dat_r
- );
+ generic map (
+ g_delay_len => g_in_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => in_clk,
+ din => in_dat,
+ dout => in_dat_r
+ );
in_dat_d <= in_dat_r when g_tsetup_delay_lo = false else in_dat_r when falling_edge(out_clk);
-- Capture input at falling edge
u_fall : entity work.common_async
- generic map (
- g_rising_edge => false,
- g_delay_len => g_out_delay_len
- )
- port map (
- rst => rst,
- clk => out_clk,
- din => in_dat_d,
- dout => out_dat_f
- );
+ generic map (
+ g_rising_edge => false,
+ g_delay_len => g_out_delay_len
+ )
+ port map (
+ rst => rst,
+ clk => out_clk,
+ din => in_dat_d,
+ dout => out_dat_f
+ );
end str;
--------------------------------------------------------------------------------
@@ -177,8 +177,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_fr is
port (
@@ -201,8 +201,8 @@ end str;
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg is
generic (
@@ -226,39 +226,39 @@ architecture str of common_ddreg is
begin
-- out_dat_hi
u_ddreg_hi : entity work.common_ddreg_r
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len,
- g_tsetup_delay_hi => g_tsetup_delay_hi
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_r => out_dat_hi
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len,
+ g_tsetup_delay_hi => g_tsetup_delay_hi
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_r => out_dat_hi
+ );
-- out_dat_lo
u_ddreg_fall : entity work.common_ddreg_f
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len - 1,
- g_tsetup_delay_lo => g_tsetup_delay_lo
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_f => out_dat_f -- clocked at falling edge of out_clk
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len - 1,
+ g_tsetup_delay_lo => g_tsetup_delay_lo
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_f => out_dat_f -- clocked at falling edge of out_clk
+ );
u_ddreg_lo : entity work.common_ddreg_fr
- port map (
- rst => rst,
- clk => out_clk,
- in_dat_f => out_dat_f,
- out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
- );
+ port map (
+ rst => rst,
+ clk => out_clk,
+ in_dat_f => out_dat_f,
+ out_dat_r => out_dat_lo -- clocked at rising edge of out_clk
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
index 3b8b40e132784aac1480b8d0e0fd7aa23629f713..90f9bc09dcf4d2b96f6250ff74a3891aaee4e341 100644
--- a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
@@ -24,8 +24,8 @@
-- Remark:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_ddreg_slv is
generic (
@@ -46,18 +46,17 @@ architecture str of common_ddreg_slv is
begin
gen_slv: for I in in_dat'range generate
u_ddreg : entity work.common_ddreg
- generic map (
- g_in_delay_len => g_in_delay_len,
- g_out_delay_len => g_out_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat(I),
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi(I),
- out_dat_lo => out_dat_lo(I)
- );
+ generic map (
+ g_in_delay_len => g_in_delay_len,
+ g_out_delay_len => g_out_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat(I),
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi(I),
+ out_dat_lo => out_dat_lo(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index fa2d76a017ad2a9af1f4caed0cf0cf83ca0ab8d4..6684b6430399ea1e996367cd4948433dec8f7390 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose:
--
@@ -32,8 +32,8 @@ use work.common_pkg.all;
entity common_debounce is
generic (
g_type : string := "BOTH"; -- "BOTH" = debounce g_latency clk cycles for both bgoing high when d_in='1' and for going low when d_in='0'
- -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
- -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
+ -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
+ -- "LOW" = debounce g_latency clk cycles for going low when d_in='0', go high immediately when d_in='1'
g_delay_len : natural := c_meta_delay_len; -- = 3, combat meta stability
g_latency : natural := 8; -- >= 1, combat debounces over nof clk cycles
g_init_level : std_logic := '1'
@@ -99,15 +99,15 @@ begin
end generate;
u_counter : entity work.common_counter
- generic map (
- g_width => c_latency_w
- )
- port map (
- rst => '0',
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_latency_w
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_deinterleave.vhd b/libraries/base/common/src/vhdl/common_deinterleave.vhd
index 50f29010351f5d58aa9581d8291645d8cba186ef..5d82c282dd2dc60dcd636280b84e7f13ac72c46f 100644
--- a/libraries/base/common/src/vhdl/common_deinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_deinterleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Deinterleave input into g_nof_out output streams based on g_block_size.
-- Description:
@@ -38,7 +38,7 @@ entity common_deinterleave is
g_dat_w : natural;
g_block_size : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -69,18 +69,18 @@ architecture rtl of common_deinterleave is
signal nxt_demux_val_cnt : std_logic_vector(c_demux_val_cnt_w - 1 downto 0);
begin
u_demux : entity work.common_demultiplexer
- generic map (
- g_nof_out => g_nof_out,
- g_dat_w => g_dat_w
- )
- port map (
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => demux_out_sel,
- out_dat => demux_out_dat,
- out_val => demux_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => demux_out_sel,
+ out_dat => demux_out_dat,
+ out_val => demux_out_val
+ );
-----------------------------------------------------------------------------
-- Demultiplexer output selection
@@ -129,23 +129,24 @@ begin
-- Align the output streams by adding pipeline stages
-----------------------------------------------------------------------------
gen_align_out: if g_align_out = true generate
+
gen_inter: for i in 0 to g_nof_out - 1 generate
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
- g_nof_dat => 1,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- in_val => demux_out_val(i),
-
- out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
- out_val => out_val(i)
- );
+ generic map (
+ g_pipeline => g_nof_out * g_block_size - (i + 1) * g_block_size,
+ g_nof_dat => 1,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => demux_out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ in_val => demux_out_val(i),
+
+ out_dat => out_dat(i * g_dat_w + g_dat_w - 1 downto i * g_dat_w),
+ out_val => out_val(i)
+ );
end generate;
end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_delay.vhd b/libraries/base/common/src/vhdl/common_delay.vhd
index 0e72b7574362dbdef1c24d911acd3d84a04258ce..6e703c84921a61c0c46397f6eedd17fa75d42e7b 100644
--- a/libraries/base/common/src/vhdl/common_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_delay.vhd
@@ -25,7 +25,7 @@
-- indicates an active clock cycle.
library ieee;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_delay is
generic (
@@ -52,6 +52,7 @@ begin
out_dat <= shift_reg(g_depth);
gen_reg : if g_depth > 0 generate
+
p_clk : process(clk)
begin
if rising_edge(clk) then
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 52f37b9cd5be508a913914ed8705e79346678cc1..2a0a5d4adbe304922de8a0771f53e5a2184ab911 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Assign input to one of g_nof_out output streams based on out_sel input
-- Description: The output streams are concatenated into one SLV.
@@ -35,7 +35,7 @@ entity common_demultiplexer is
g_pipeline_out : natural := 0;
g_nof_out : natural;
g_dat_w : natural
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0'; -- for g_pipeline_* = 0 no rst and clk are needed, because then the demultiplexer works combinatorialy
@@ -73,6 +73,7 @@ begin
end generate;
gen_sel : if g_nof_out > 1 generate
+
p_sel : process(out_sel_reg, in_dat_reg, in_val_reg)
begin
sel_val <= (others => '0');
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index 8c09e6292f07279763381f58bd8325d475a8520f..afcb82c4635de51f6514964d4c31c17dba766ead 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -34,9 +34,9 @@
-- s_assert
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use WORK.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use WORK.common_pkg.all;
entity common_duty_cycle is
generic (
@@ -85,21 +85,21 @@ begin
case r.state is
when s_idle => v.state := s_idle;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_deassert;
- elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt or dc_act_cnt = TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_deassert;
+ elsif TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt or dc_act_cnt = dc_per_cnt then
+ v.state := s_assert;
+ end if;
when s_assert => v.dc_pulse := g_act_lvl;
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
- v.state := s_deassert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_act_cnt and dc_act_cnt < dc_per_cnt then
+ v.state := s_deassert;
+ end if;
when s_deassert => v.dc_pulse := not(g_act_lvl);
- if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
- v.state := s_assert;
- end if;
+ if TO_UVEC(r.cycle_cnt, c_cycle_cnt_w) = dc_per_cnt and dc_act_cnt /= TO_UVEC(0, c_cycle_cnt_w) then
+ v.state := s_assert;
+ end if;
end case;
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index c4ad6d2bfd1d34bebf41b8a3b41fc5ccfa381303..819360cd0a93d0b191315f58ac612c7d6c0f598d 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_evt is
generic (
@@ -69,6 +69,7 @@ begin
-- Output registered event pulse
gen_out_reg : if g_out_reg = true generate
+
p_clk : process(rst, clk)
begin
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_fanout.vhd b/libraries/base/common/src/vhdl/common_fanout.vhd
index 77143e1487c43d7c0147c90824b0c54df06afb42..e9a2785629a72016685224f5bd3b489beea70382 100644
--- a/libraries/base/common/src/vhdl/common_fanout.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout.vhd
@@ -28,8 +28,8 @@
-- registers maintain their value.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_fanout is
generic (
@@ -53,42 +53,41 @@ architecture str of common_fanout is
begin
gen_fanout : for i in g_nof_output - 1 downto 0 generate
u_pipe_en : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_en,
- in_en => '1',
- out_dat => out_en_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_en,
+ in_en => '1',
+ out_dat => out_en_vec(i)
+ );
u_pipe_valid : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(i)
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_val,
- in_en => in_en,
- out_dat => out_val_vec(i)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i)
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ in_en => in_en,
+ out_dat => out_val_vec(i)
+ );
u_pipe_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(i),
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- in_en => in_en,
- out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(i),
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ in_en => in_en,
+ out_dat => out_dat_vec((i + 1) * g_dat_w - 1 downto i * g_dat_w)
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index d0dcc9ba25c5e0b9d486220db465275b95f96fe4..0ce860e34f94c97116bcbbd272155e06c384e9a3 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Parallel fanout tree.
-- Description:
@@ -99,7 +99,7 @@ entity common_fanout_tree is
end common_fanout_tree;
architecture str of common_fanout_tree is
- constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
+ constant c_nof_output : natural := g_nof_output_per_cell ** g_nof_stages;
-- Define t_natural_arr range
constant c_cell_pipeline_factor_arr : t_natural_arr(g_nof_stages - 1 downto 0) := g_cell_pipeline_factor_arr; -- value: stage factor to multiply with g_cell_pipeline_arr
@@ -120,24 +120,25 @@ begin
-- Fanout tree
gen_stage : for j in 0 to g_nof_stages - 1 generate
- gen_cell : for i in 0 to g_nof_output_per_cell**j - 1 generate
+
+ gen_cell : for i in 0 to g_nof_output_per_cell ** j - 1 generate
-- output k =
u_fanout : entity work.common_fanout
- generic map (
- g_nof_output => g_nof_output_per_cell,
- g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => stage_en_vec_arr( j - 1)( i),
- in_val => stage_val_vec_arr(j - 1)( i),
- in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
- out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
- out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
- );
+ generic map (
+ g_nof_output => g_nof_output_per_cell,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(j) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => stage_en_vec_arr( j - 1)( i),
+ in_val => stage_val_vec_arr(j - 1)( i),
+ in_dat => stage_dat_vec_arr(j - 1)((i + 1) * g_dat_w - 1 downto i * g_dat_w),
+ out_en_vec => stage_en_vec_arr( j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_val_vec => stage_val_vec_arr(j)((i + 1) * g_nof_output_per_cell - 1 downto i * g_nof_output_per_cell),
+ out_dat_vec => stage_dat_vec_arr(j)((i + 1) * g_nof_output_per_cell * g_dat_w - 1 downto i * g_nof_output_per_cell * g_dat_w)
+ );
end generate;
end generate;
@@ -148,21 +149,20 @@ begin
no_tree : if g_nof_output = 1 generate
u_reg : entity work.common_fanout
- generic map (
- g_nof_output => 1,
- g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
- g_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_en => in_en,
- in_val => in_val,
- in_dat => in_dat,
- out_en_vec => out_en_vec,
- out_val_vec => out_val_vec,
- out_dat_vec => out_dat_vec
- );
+ generic map (
+ g_nof_output => 1,
+ g_pipeline_arr => c_cell_pipeline_factor_arr(0) * c_cell_pipeline_arr,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_en => in_en,
+ in_val => in_val,
+ in_dat => in_dat,
+ out_en_vec => out_en_vec,
+ out_val_vec => out_val_vec,
+ out_dat_vec => out_dat_vec
+ );
end generate; -- no_tree
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index 135a3cbfe48a950f6735339072ada38190e4a779..de195a12b69f8ee7ad45770b39fe2cac3e7ba2ca 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
-- Purpose:
-- . Dynamically map record-like field structures onto SLVs.
@@ -82,7 +82,6 @@ package common_field_pkg is
function field_arr_set_mode(field_arr : t_common_field_arr; mode : string) return t_common_field_arr;
function sel_a_b(sel : boolean; a, b : t_common_field_arr ) return t_common_field_arr;
-
end common_field_pkg;
package body common_field_pkg is
@@ -113,7 +112,7 @@ package body common_field_pkg is
end field_map_defaults;
function field_mode(field_arr : t_common_field_arr; name: string) return string is
- -- Returns the mode string of the passed (via name) field
+ -- Returns the mode string of the passed (via name) field
begin
if field_exists(field_arr, name) then
for i in 0 to field_arr'high loop
@@ -127,7 +126,7 @@ package body common_field_pkg is
end field_mode;
function field_size(field_arr : t_common_field_arr; name: string) return natural is
- -- Returns the size of the passed (via name) field
+ -- Returns the size of the passed (via name) field
begin
for i in 0 to field_arr'high loop
if field_arr(i).name = field_name_pad(name) then
@@ -137,7 +136,7 @@ package body common_field_pkg is
end field_size;
function field_hi(field_arr : t_common_field_arr; name: string) return integer is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -155,7 +154,7 @@ package body common_field_pkg is
end field_hi;
function field_hi(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
+ -- Returns the high (=left) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -167,7 +166,7 @@ package body common_field_pkg is
end field_hi;
function field_lo(field_arr : t_common_field_arr; name: string) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated IN or OUT SLV
variable v_acc_hi : natural := 0;
begin
if field_exists(field_arr, name) then
@@ -185,7 +184,7 @@ package body common_field_pkg is
end field_lo;
function field_lo(field_arr : t_common_field_arr; index : natural) return natural is
- -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
+ -- Returns the low (=right) bit range index of the field within the field_arr interpreted as concatenated SLV
variable v_acc_hi : natural := 0;
begin
for i in 0 to index loop
@@ -197,7 +196,7 @@ package body common_field_pkg is
end field_lo;
function field_slv_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of all fields in field_arr
+ -- Return the total length of all fields in field_arr
variable v_len : natural := 0;
begin
for i in 0 to field_arr'high loop
@@ -207,7 +206,7 @@ package body common_field_pkg is
end field_slv_len;
function field_slv_in_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the input fields in field_arr (= all "RO")
+ -- Return the total length of the input fields in field_arr (= all "RO")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -219,7 +218,7 @@ package body common_field_pkg is
end field_slv_in_len;
function field_slv_out_len(field_arr : t_common_field_arr) return natural is
- -- Return the total length of the output fields in field_arr (= all "RW")
+ -- Return the total length of the output fields in field_arr (= all "RW")
variable v_len : natural := 0;
begin
for f in 0 to field_arr'high loop
@@ -231,7 +230,7 @@ package body common_field_pkg is
end field_slv_out_len;
function field_nof_words(field_arr : t_common_field_arr; word_w : natural) return natural is
- -- Return the number of words (of width word_w) required to hold field_arr
+ -- Return the number of words (of width word_w) required to hold field_arr
variable v_word_cnt : natural := 0;
variable v_nof_reg_words : natural;
begin
@@ -246,12 +245,12 @@ package body common_field_pkg is
end field_nof_words;
function field_map_in(field_arr : t_common_field_arr; slv: std_logic_vector; word_w : natural; mode : string) return std_logic_vector is
- -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
+ -- Re-map a field SLV into a larger SLV, support mapping both the slv_in or the slv_out that dependents on mode; each field starting at a word boundary (word_w)
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
for f in 0 to field_arr'high loop
- -- Only extract the fields that are inputs
+ -- Only extract the fields that are inputs
if field_arr(f).mode = mode then -- if mode="RO" then slv = slv_in, else if mode="RW" then slv = slv_out
-- Extract the field
v_word_arr( v_word_cnt * word_w + field_arr(f).size-1 downto v_word_cnt * word_w) := slv( field_hi(field_arr, field_arr(f).name) downto field_lo(field_arr, field_arr(f).name) );
@@ -263,7 +262,7 @@ package body common_field_pkg is
end field_map_in;
function field_map_out(field_arr : t_common_field_arr; word_arr: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Reverse of field_map_in
+ -- Reverse of field_map_in
variable v_slv_out : std_logic_vector(field_slv_out_len(field_arr) - 1 downto 0) := (others => '0');
variable v_word_cnt : natural := 0;
begin
@@ -280,7 +279,7 @@ package body common_field_pkg is
end field_map_out;
function field_map(field_arr : t_common_field_arr; word_arr_in: std_logic_vector; word_arr_out: std_logic_vector; word_w : natural) return std_logic_vector is
- -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
+ -- Create one SLV consisting of both read-only and output-readback fields, e.g. as input to an MM reg
variable v_word_arr : std_logic_vector(field_nof_words(field_arr, word_w) * word_w - 1 downto 0);
variable v_word_cnt : natural := 0;
begin
@@ -298,7 +297,7 @@ package body common_field_pkg is
end field_map;
function field_select_subset(subset_field_arr : t_common_field_arr; larger_field_arr : t_common_field_arr; larger_slv : std_logic_vector) return std_logic_vector is
- -- Return SLV mapped to "subset_field_arr" extracted from a larger SLV mapped to "larger_field_arr".
+ -- Return SLV mapped to "subset_field_arr" extracted from a larger SLV mapped to "larger_field_arr".
variable v_hi_sub : natural;
variable v_lo_sub : natural;
variable v_hi_full : natural;
@@ -317,7 +316,7 @@ package body common_field_pkg is
end field_select_subset;
function field_ovr_arr(field_arr : t_common_field_arr; ovr_init: std_logic_vector) return t_common_field_arr is
- -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
+ -- Copy field_arr but change widths to 1 to create a 1-bit override field for each field in field_arr.
variable v_ovr_field_arr : t_common_field_arr(field_arr'range);
begin
v_ovr_field_arr := field_arr;
@@ -335,7 +334,7 @@ package body common_field_pkg is
return true;
end if;
end loop;
- return false;
+ return false;
end field_exists;
function field_arr_set_mode(field_arr : t_common_field_arr; mode : string) return t_common_field_arr is
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
index 08ad5365defe15e0e22c3acc25a08d01082688be..afef629eda537186e62b670be7609eed30ae72aa 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Dual clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc is
generic (
@@ -52,7 +52,7 @@ entity common_fifo_dc is
end common_fifo_dc;
architecture str of common_fifo_dc is
- constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
+ constant c_nof_words : natural := 2 ** ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
signal wr_rst : std_logic;
signal wr_init : std_logic;
@@ -73,27 +73,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
wr_init_out <= wr_init;
@@ -115,24 +115,24 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc
- generic map (
- g_technology => g_technology,
- g_dat_w => g_dat_w,
- g_nof_words => c_nof_words
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_dat_w => g_dat_w,
+ g_nof_words => c_nof_words
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
index f94b9e105487bac831a533128a1ecf0bfb35e6b0..aa7ccee11978641da60c56c7d996fb9d68abf276 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Control the FIFO fill level and report the dual clock lock status
-- Description:
@@ -103,7 +103,7 @@ end common_fifo_dc_lock_control;
architecture rtl of common_fifo_dc_lock_control is
constant c_fifo_latency : natural := 10; -- large enough to ensure that the FIFO filling has started, but small enough such that the FIFO is not filled yet
- constant c_fill_level_max : natural := 2**rd_usedw'length - 1;
+ constant c_fill_level_max : natural := 2 ** rd_usedw'length - 1;
constant c_cnt_arr : t_natural_arr := (g_hold_wr_clk_rst, g_hold_dc_fifo_rst, c_fifo_latency); -- array to hold all timeouts
constant c_cnt_max : natural := largest(c_cnt_arr); -- largest of all timeouts
@@ -225,24 +225,24 @@ begin
end process;
u_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_dc_locked_monitor : entity work.common_stable_monitor
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- MM
- r_in => i_dc_locked,
- r_stable => dc_stable,
- r_stable_ack => dc_stable_ack
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- MM
+ r_in => i_dc_locked,
+ r_stable => dc_stable,
+ r_stable_ack => dc_stable_ack
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
index 32aaf05a36d63454b735525c1fa03e4e4248b8b4..ea976d9e9f02b5e514f2a135cf293d6224f53e3a 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
@@ -41,9 +41,9 @@
-- been written to the FIFO the rdusedw will wrap and the output goes wrong.
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_dc_mixed_widths is
generic (
@@ -71,7 +71,7 @@ entity common_fifo_dc_mixed_widths is
end common_fifo_dc_mixed_widths;
architecture str of common_fifo_dc_mixed_widths is
- constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
+ constant c_nof_words : natural := 2 ** ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
signal wr_rst : std_logic;
signal wr_init : std_logic;
@@ -92,27 +92,27 @@ begin
-- . synchronize release of rst to wr_clk domain
-- Using common_areset is equivalent to using common_async with same signal applied to rst and din.
u_wr_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 3
- )
- port map (
- in_rst => rst,
- clk => wr_clk,
- out_rst => wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 3
+ )
+ port map (
+ in_rst => rst,
+ clk => wr_clk,
+ out_rst => wr_rst
+ );
-- Delay wr_init to ensure that FIFO ful has gone low after reset release
u_wr_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => wr_rst,
- clk => wr_clk,
- out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => wr_rst,
+ clk => wr_clk,
+ out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
+ );
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req and not wr_init; -- check on NOT ful is not necessary according to fifo_generator_ug175.pdf
@@ -131,25 +131,25 @@ begin
end process;
u_fifo : entity tech_fifo_lib.tech_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => c_nof_words,
- g_wrdat_w => g_wr_dat_w,
- g_rddat_w => g_rd_dat_w
- )
- port map (
- aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
- data => wr_dat,
- rdclk => rd_clk,
- rdreq => rd_en,
- wrclk => wr_clk,
- wrreq => wr_en,
- q => rd_dat,
- rdempty => emp,
- rdusedw => rdusedw,
- wrfull => ful,
- wrusedw => wrusedw
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => c_nof_words,
+ g_wrdat_w => g_wr_dat_w,
+ g_rddat_w => g_rd_dat_w
+ )
+ port map (
+ aclr => wr_rst, -- MegaWizard fifo_dc_mixed_widths seems to use aclr synchronous with wr_clk
+ data => wr_dat,
+ rdclk => rd_clk,
+ rdreq => rd_en,
+ wrclk => wr_clk,
+ wrreq => wr_en,
+ q => rd_dat,
+ rdempty => emp,
+ rdusedw => rdusedw,
+ wrfull => ful,
+ wrusedw => wrusedw
+ );
proc_common_fifo_asserts("common_fifo_dc_mixed_widths", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_rd.vhd b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
index 25ec1cdeeb7cab0401ae200f71b7ac99550c8592..6844b253e0cb477263ecb78ee80c6cead5a5b404 100644
--- a/libraries/base/common/src/vhdl/common_fifo_rd.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
-- Description: -
@@ -53,20 +53,20 @@ end common_fifo_rd;
architecture wrap of common_fifo_rd is
begin
u_rl0 : entity work.common_rl_decrease
- generic map (
- g_adapt => true,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => fifo_req,
- snk_in_dat => fifo_dat,
- snk_in_val => fifo_val,
- -- ST source: RL = 0
- src_in_ready => rd_req,
- src_out_dat => rd_dat,
- src_out_val => rd_val
- );
+ generic map (
+ g_adapt => true,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => fifo_req,
+ snk_in_dat => fifo_dat,
+ snk_in_val => fifo_val,
+ -- ST source: RL = 0
+ src_in_ready => rd_req,
+ src_out_dat => rd_dat,
+ src_out_val => rd_val
+ );
end wrap;
diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
index 302f5c2225f88fc1a3bcc4abdbcfc0fd4951156d..7f4882243fa3683d61f355708f647d225e9e2747 100644
--- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
@@ -22,9 +22,9 @@
-- Purpose: Single clock FIFO
library IEEE, technology_lib, tech_fifo_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_fifo_sc is
generic (
@@ -32,8 +32,8 @@ entity common_fifo_sc is
g_note_is_ful : boolean := true; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
g_fail_rd_emp : boolean := false; -- when TRUE report FAILURE when read from an empty FIFO
g_use_lut : boolean := false; -- when TRUE then force using LUTs via Altera eab="OFF",
- -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
- -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
+ -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
+ -- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
g_reset : boolean := false; -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
g_init : boolean := false; -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
g_dat_w : natural := 36; -- 36 * 256 = 1 M9K
@@ -51,7 +51,7 @@ entity common_fifo_sc is
rd_req : in std_logic;
rd_emp : out std_logic;
rd_val : out std_logic;
- usedw : out std_logic_vector(ceil_log2(g_nof_words) - 1 downto 0)
+ usedw : out std_logic_vector(ceil_log2(g_nof_words) - 1 downto 0)
);
end common_fifo_sc;
@@ -81,15 +81,15 @@ begin
-- Make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf). This is necessary in case
-- the FIFO reset is also used functionally to flush it, so not only after power up.
u_fifo_rst : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => rst,
- clk => clk,
- out_rst => fifo_rst
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => rst,
+ clk => clk,
+ out_rst => fifo_rst
+ );
end generate;
no_fifo_rst : if g_reset = false generate
@@ -99,15 +99,15 @@ begin
gen_init : if g_init = true generate
-- Wait at least 3 cycles after reset release before allowing fifo_wr_en (see fifo_generator_ug175.pdf)
u_fifo_init : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => 4
- )
- port map (
- in_rst => fifo_rst,
- clk => clk,
- out_rst => fifo_init
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ port map (
+ in_rst => fifo_rst,
+ clk => clk,
+ out_rst => fifo_init
+ );
p_init_reg : process(fifo_rst, clk)
begin
@@ -130,28 +130,28 @@ begin
wr_ful <= fifo_full;
rd_emp <= fifo_empty;
- usedw <= fifo_usedw;
+ usedw <= fifo_usedw;
- fifo_rd_en <= rd_req; -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
+fifo_rd_en <= rd_req; -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
- nxt_rd_val <= fifo_rd_en and not fifo_empty; -- check on NOT empty is necessary for rd_val
+nxt_rd_val <= fifo_rd_en and not fifo_empty; -- check on NOT empty is necessary for rd_val
- nxt_wr_aful <= '0' when TO_UINT(fifo_usedw) < g_nof_words - c_fifo_af_margin else '1';
+nxt_wr_aful <= '0' when TO_UINT(fifo_usedw) < g_nof_words - c_fifo_af_margin else '1';
- p_clk : process(fifo_rst, clk)
- begin
- if fifo_rst = '1' then
- wr_aful <= '0';
- rd_val <= '0';
- elsif rising_edge(clk) then
- wr_aful <= nxt_wr_aful;
- rd_val <= nxt_rd_val;
- end if;
- end process;
-
- -- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
- -- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
- u_fifo : entity tech_fifo_lib.tech_fifo_sc
+p_clk : process(fifo_rst, clk)
+begin
+ if fifo_rst = '1' then
+ wr_aful <= '0';
+ rd_val <= '0';
+ elsif rising_edge(clk) then
+ wr_aful <= nxt_wr_aful;
+ rd_val <= nxt_rd_val;
+ end if;
+end process;
+
+-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
+-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
+u_fifo : entity tech_fifo_lib.tech_fifo_sc
generic map (
g_technology => g_technology,
g_use_eab => c_use_eab,
@@ -167,8 +167,8 @@ begin
empty => fifo_empty,
full => fifo_full,
q => rd_dat,
- usedw => fifo_usedw
+ usedw => fifo_usedw
);
- proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
+proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
end str;
diff --git a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
index 9eeeeaf25c53d7446fd40f8a5406a5a442f58b2f..fb438d1e5dcc56128825be64020a8c9808048173 100644
--- a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
+++ b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
@@ -21,7 +21,7 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_flank_to_pulse is
port (
@@ -35,7 +35,7 @@ end common_flank_to_pulse;
architecture str of common_flank_to_pulse is
signal flank_in_dly : std_logic;
begin
- p_in_dly : process(rst, clk)
+ p_in_dly : process(rst, clk)
begin
if rst = '1' then
flank_in_dly <= '0';
diff --git a/libraries/base/common/src/vhdl/common_frame_busy.vhd b/libraries/base/common/src/vhdl/common_frame_busy.vhd
index 6357f11447baea056b928859533a88bc5aee4781..cb6191e6765902e5692d321b47db00d00ab17a85 100644
--- a/libraries/base/common/src/vhdl/common_frame_busy.vhd
+++ b/libraries/base/common/src/vhdl/common_frame_busy.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Determine when there is an active frame
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index 0dbfdf1c99393accdae15efcd5f7650ee4307150..d87d5005613e83c5afef8ea17fa9d37408f59924 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
--
@@ -83,14 +83,14 @@ begin
nxt_init_reg <= '1' when cnt_en = '0' and prev_cnt_en = '1' else '0';
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_latency_w + 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => '0',
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_latency_w + 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => '0',
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_inout.vhd b/libraries/base/common/src/vhdl/common_inout.vhd
index ba4efdbf26440dd4fc149816a28fd4c1247db5e9..22b05ac47d9f0b6c932f99945fb800c3cdb6a11e 100644
--- a/libraries/base/common/src/vhdl/common_inout.vhd
+++ b/libraries/base/common/src/vhdl/common_inout.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Tristate buffer
diff --git a/libraries/base/common/src/vhdl/common_int2float.vhd b/libraries/base/common/src/vhdl/common_int2float.vhd
index 2bcf2c8ee4500fd42d78192f0f1140ec4697de3a..0721d56a90b5e40653e3fd7b3a39aefbe2756b3f 100644
--- a/libraries/base/common/src/vhdl/common_int2float.vhd
+++ b/libraries/base/common/src/vhdl/common_int2float.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose:
-- Convert signed integer to semi-floating point number.
@@ -66,6 +66,7 @@ architecture rtl of common_int2float is
begin
-- registers
gen_reg_input : if g_pipeline = 2 generate
+
p_reg_input : process(clk)
begin
if rising_edge(clk) then
@@ -82,7 +83,7 @@ begin
assert g_pipeline = 1 or g_pipeline = 2
report "common_int2float: pipeline value not supported"
- severity FAILURE;
+ severity FAILURE;
p_clk : process(clk)
begin
@@ -98,10 +99,11 @@ begin
end generate;
gen_float : if out_dat'length <= in_dat'length generate
+
p_float: process (reg_dat)
begin
if unsigned(reg_dat(in_dat'high downto out_dat'high - 1)) = 0 or
- signed(reg_dat(in_dat'high downto out_dat'high - 1)) = -1 then
+ signed(reg_dat(in_dat'high downto out_dat'high - 1)) = -1 then
nxt_out_dat <= '0' & reg_dat(out_dat'high - 1 downto 0);
else
nxt_out_dat <= '1' & reg_dat(in_dat'high downto in_dat'high - out_dat'high + 1);
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 42890418c20ba63f325edd89b045fcd291aed20f..c900b52a320d4434bbb40513cf9a0c4907f29cae 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use IEEE.numeric_std.all;
package common_interface_layers_pkg is
------------------------------------------------------------------------------
@@ -61,7 +61,7 @@ package common_interface_layers_pkg is
type t_xgmii_dc_arr is array(integer range <>) of std_logic_vector(c_xgmii_w - 1 downto 0);
type t_xgmii_d_arr is array(integer range <>) of std_logic_vector(c_xgmii_data_w - 1 downto 0);
type t_xgmii_c_arr is array(integer range <>) of std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
- end common_interface_layers_pkg;
+end common_interface_layers_pkg;
package body common_interface_layers_pkg is
-- Refer to the 10GBASE-R PHY IP Core section of the Altera Transceiver PHY IP Core User Guide
diff --git a/libraries/base/common/src/vhdl/common_interleave.vhd b/libraries/base/common/src/vhdl/common_interleave.vhd
index 11645c0f290e5b3c585ee51f7c6fb72b080e4210..3b0eed9c79680e75ea0b598bdd2c61b5ae3d3b60 100644
--- a/libraries/base/common/src/vhdl/common_interleave.vhd
+++ b/libraries/base/common/src/vhdl/common_interleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Interleave g_nof_in inputs into one output stream based on g_block_size.
-- Description:
@@ -40,7 +40,7 @@ entity common_interleave is
g_nof_in : natural; -- >= 2
g_dat_w : natural;
g_block_size : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -112,46 +112,46 @@ begin
-----------------------------------------------------------------------------
gen_blockregs: for i in 0 to g_nof_in - 1 generate
u_blockreg : entity work.common_blockreg
- generic map (
- g_block_size => g_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => bkr_in_dat_arr(i),
- in_val => in_val,
-
- out_dat => bkr_out_dat_arr(i),
- out_val => bkr_out_val_arr(i)
+ generic map (
+ g_block_size => g_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => bkr_in_dat_arr(i),
+ in_val => in_val,
+
+ out_dat => bkr_out_dat_arr(i),
+ out_val => bkr_out_val_arr(i)
);
u_dat_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => bkr_out_dat_arr(i),
- out_dat => piped_bkr_out_dat_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => bkr_out_dat_arr(i),
+ out_dat => piped_bkr_out_dat_arr(i)
+ );
u_val_block_offset_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => i * g_block_size,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => slv(bkr_out_val_arr(i)),
- sl(out_dat) => piped_bkr_out_val_arr(i)
- );
+ generic map (
+ g_pipeline => i * g_block_size,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => slv(bkr_out_val_arr(i)),
+ sl(out_dat) => piped_bkr_out_val_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -165,21 +165,21 @@ begin
-- The multiplexer
-----------------------------------------------------------------------------
u_mux : entity work.common_multiplexer
- generic map (
- g_nof_in => g_nof_in,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => mux_in_sel,
- in_dat => mux_in_concat_dat_arr,
- in_val => mux_in_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => mux_in_sel,
+ in_dat => mux_in_concat_dat_arr,
+ in_val => mux_in_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
-----------------------------------------------------------------------------
-- Multiplexer input selection
diff --git a/libraries/base/common/src/vhdl/common_interval_monitor.vhd b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
index 0056a8bce9da6f6ed79166ed515bd0f4f0373d4e..4a916c1dc3274737500f1c70c7a94a97b4fb0e91 100644
--- a/libraries/base/common/src/vhdl/common_interval_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor the nof valid clock cycles between two in_evt pulses
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_iobuf_in.vhd b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
index 688910ed0dab3a8199c82df12ea5d574be9c0eff..7cde91658e9015cb4c7aeebcdd34d2412474f6ff 100644
--- a/libraries/base/common/src/vhdl/common_iobuf_in.vhd
+++ b/libraries/base/common/src/vhdl/common_iobuf_in.vhd
@@ -22,8 +22,8 @@
-- Purpose: Delay differential FPGA input
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity common_iobuf_in is
generic(
diff --git a/libraries/base/common/src/vhdl/common_led_controller.vhd b/libraries/base/common/src/vhdl/common_led_controller.vhd
index b0d2adbb0ec2383dad7d4deeb1e30d69849942ba..0b077e87479b80f1882ac4d2139ca448332c9219 100644
--- a/libraries/base/common/src/vhdl/common_led_controller.vhd
+++ b/libraries/base/common/src/vhdl/common_led_controller.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide visual activity information via a LED.
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index 3f11c037e9a5958791241439b19654ea710b8fff..c49062fc8eb52b5a60ceca85d1168d3d200e7b12 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -30,9 +30,9 @@
-- . Based on Xilinx application note xapp052.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_lfsr_sequences_pkg is
constant c_common_lfsr_max_nof_feedbacks : natural := 6;
@@ -51,89 +51,91 @@ package common_lfsr_sequences_pkg is
-- (0,0,0,0, 2, 1) yields repeat <0, 1, 2>
-- XNOR feedbacks from outputs for n = 3 .. 72 from Xilinx xapp052.pdf (that lists feedbacks for in total 168 sequences)
- constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1), -- 1 : <0, 1>
- (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
- (0,0,0,0, 3, 2), -- 3
- (0,0,0,0, 4, 3), -- 4
- (0,0,0,0, 5, 3), -- 5
- (0,0,0,0, 6, 5), -- 6
- (0,0,0,0, 7, 6), -- 7
- (0,0, 8, 6, 5, 4), -- 8
- (0,0,0,0, 9, 5), -- 9
- (0,0,0,0, 10, 7), -- 10
- (0,0,0,0, 11, 9), -- 11
- (0,0, 12, 6, 4, 1), -- 12
- (0,0, 13, 4, 3, 1), -- 13
- (0,0, 14, 5, 3, 1), -- 14
- (0,0,0,0, 15,14 ), -- 15
- (0,0, 16,15,13, 4), -- 16
- (0,0,0,0, 17,14 ), -- 17
- (0,0,0,0, 18,11 ), -- 18
- (0,0, 19, 6, 2, 1), -- 19
- (0,0,0,0, 20,17 ), -- 20
- (0,0,0,0, 21,19 ), -- 21
- (0,0,0,0, 22,21 ), -- 22
- (0,0,0,0, 23,18 ), -- 23
- (0,0, 24,23,22,17), -- 24
- (0,0,0,0, 25,22 ), -- 25
- (0,0, 26, 6, 2, 1), -- 26
- (0,0, 27, 5, 2, 1), -- 27
- (0,0,0,0, 28,25 ), -- 28
- (0,0,0,0, 29,27 ), -- 29
- (0,0, 30, 6, 4, 1), -- 30
- (0,0,0,0, 31,28 ), -- 31
- (0,0, 32,22, 2, 1), -- 32
- (0,0,0,0, 33,20 ), -- 33
- (0,0, 34,27, 2, 1), -- 34
- (0,0,0,0, 35,33 ), -- 35
- (0,0,0,0, 36,25 ), -- 36
- ( 37, 5, 4, 3, 2, 1), -- 37
- (0,0, 38, 6, 5, 1), -- 38
- (0,0,0,0, 39,35 ), -- 39
- (0,0, 40,38,21,19), -- 40
- (0,0,0,0, 41,38 ), -- 41
- (0,0, 42,41,20,19), -- 42
- (0,0, 43,42,38,37), -- 43
- (0,0, 44,43,18,17), -- 44
- (0,0, 45,44,42,41), -- 45
- (0,0, 46,45,26,25), -- 46
- (0,0,0,0, 47,42 ), -- 47
- (0,0, 48,47,21,20), -- 48
- (0,0,0,0, 49,40 ), -- 49
- (0,0, 50,49,24,23), -- 50
- (0,0, 51,50,36,35), -- 51
- (0,0,0,0, 52,49 ), -- 52
- (0,0, 53,52,38,37), -- 53
- (0,0, 54,53,18,17), -- 54
- (0,0,0,0, 55,31 ), -- 55
- (0,0, 56,55,35,34), -- 56
- (0,0,0,0, 57,50 ), -- 57
- (0,0,0,0, 58,39 ), -- 58
- (0,0, 59,58,38,37), -- 59
- (0,0,0,0, 60,59 ), -- 60
- (0,0, 61,60,46,45), -- 61
- (0,0, 62,61, 6, 5), -- 62
- (0,0,0,0, 63,62 ), -- 63
- (0,0, 64,63,61,60), -- 64
- (0,0,0,0, 65,47 ), -- 65
- (0,0, 66,65,57,56), -- 66
- (0,0, 67,66,58,57), -- 67
- (0,0,0,0, 68,59 ), -- 68
- (0,0, 69,67,42,40), -- 69
- (0,0, 70,69,55,54), -- 70
- (0,0,0,0, 71,65 ), -- 71
- (0,0, 72,66,25,19)); -- 72
+ constant c_common_lfsr_sequences : t_SEQUENCES := ( -- 1 : <0, 1>
+ (0,0,0,0,0, 1),
+ (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
+ (0,0,0,0, 3, 2), -- 3
+ (0,0,0,0, 4, 3), -- 4
+ (0,0,0,0, 5, 3), -- 5
+ (0,0,0,0, 6, 5), -- 6
+ (0,0,0,0, 7, 6), -- 7
+ (0,0, 8, 6, 5, 4), -- 8
+ (0,0,0,0, 9, 5), -- 9
+ (0,0,0,0, 10, 7), -- 10
+ (0,0,0,0, 11, 9), -- 11
+ (0,0, 12, 6, 4, 1), -- 12
+ (0,0, 13, 4, 3, 1), -- 13
+ (0,0, 14, 5, 3, 1), -- 14
+ (0,0,0,0, 15,14 ), -- 15
+ (0,0, 16,15,13, 4), -- 16
+ (0,0,0,0, 17,14 ), -- 17
+ (0,0,0,0, 18,11 ), -- 18
+ (0,0, 19, 6, 2, 1), -- 19
+ (0,0,0,0, 20,17 ), -- 20
+ (0,0,0,0, 21,19 ), -- 21
+ (0,0,0,0, 22,21 ), -- 22
+ (0,0,0,0, 23,18 ), -- 23
+ (0,0, 24,23,22,17), -- 24
+ (0,0,0,0, 25,22 ), -- 25
+ (0,0, 26, 6, 2, 1), -- 26
+ (0,0, 27, 5, 2, 1), -- 27
+ (0,0,0,0, 28,25 ), -- 28
+ (0,0,0,0, 29,27 ), -- 29
+ (0,0, 30, 6, 4, 1), -- 30
+ (0,0,0,0, 31,28 ), -- 31
+ (0,0, 32,22, 2, 1), -- 32
+ (0,0,0,0, 33,20 ), -- 33
+ (0,0, 34,27, 2, 1), -- 34
+ (0,0,0,0, 35,33 ), -- 35
+ (0,0,0,0, 36,25 ), -- 36
+ ( 37, 5, 4, 3, 2, 1), -- 37
+ (0,0, 38, 6, 5, 1), -- 38
+ (0,0,0,0, 39,35 ), -- 39
+ (0,0, 40,38,21,19), -- 40
+ (0,0,0,0, 41,38 ), -- 41
+ (0,0, 42,41,20,19), -- 42
+ (0,0, 43,42,38,37), -- 43
+ (0,0, 44,43,18,17), -- 44
+ (0,0, 45,44,42,41), -- 45
+ (0,0, 46,45,26,25), -- 46
+ (0,0,0,0, 47,42 ), -- 47
+ (0,0, 48,47,21,20), -- 48
+ (0,0,0,0, 49,40 ), -- 49
+ (0,0, 50,49,24,23), -- 50
+ (0,0, 51,50,36,35), -- 51
+ (0,0,0,0, 52,49 ), -- 52
+ (0,0, 53,52,38,37), -- 53
+ (0,0, 54,53,18,17), -- 54
+ (0,0,0,0, 55,31 ), -- 55
+ (0,0, 56,55,35,34), -- 56
+ (0,0,0,0, 57,50 ), -- 57
+ (0,0,0,0, 58,39 ), -- 58
+ (0,0, 59,58,38,37), -- 59
+ (0,0,0,0, 60,59 ), -- 60
+ (0,0, 61,60,46,45), -- 61
+ (0,0, 62,61, 6, 5), -- 62
+ (0,0,0,0, 63,62 ), -- 63
+ (0,0, 64,63,61,60), -- 64
+ (0,0,0,0, 65,47 ), -- 65
+ (0,0, 66,65,57,56), -- 66
+ (0,0, 67,66,58,57), -- 67
+ (0,0,0,0, 68,59 ), -- 68
+ (0,0, 69,67,42,40), -- 69
+ (0,0, 70,69,55,54), -- 70
+ (0,0,0,0, 71,65 ), -- 71
+ (0,0, 72,66,25,19)); -- 72
-- Procedure for calculating the next PSRG and COUNTER sequence value
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector);
+ procedure common_lfsr_nxt_seq(
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector);
-- Use lfsr part of common_lfsr_nxt_seq to make a random bit generator function
-- . width of lfsr selects the LFSR sequence
@@ -143,15 +145,16 @@ package common_lfsr_sequences_pkg is
end common_lfsr_sequences_pkg;
package body common_lfsr_sequences_pkg is
- procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
- constant g_incr : in integer;
- in_en : in std_logic;
- in_req : in std_logic;
- in_dat : in std_logic_vector;
- prsg : in std_logic_vector;
- cntr : in std_logic_vector;
- signal nxt_prsg : out std_logic_vector;
- signal nxt_cntr : out std_logic_vector) is
+ procedure common_lfsr_nxt_seq(
+ constant c_lfsr_nr : in natural;
+ constant g_incr : in integer;
+ in_en : in std_logic;
+ in_req : in std_logic;
+ in_dat : in std_logic_vector;
+ prsg : in std_logic_vector;
+ cntr : in std_logic_vector;
+ signal nxt_prsg : out std_logic_vector;
+ signal nxt_cntr : out std_logic_vector) is
variable v_feedback : std_logic;
begin
nxt_prsg <= prsg;
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 2dfec614b7bf5b0c4097f7f3de7a92e5be8ff8a0..c410ab9b28fa5a5923f1a916be1c0aaf857b8e9a 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -32,10 +32,10 @@
-- is reduced to within the [0:2pi> range inside SIN() or COS().
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
package common_math_pkg is
-- Function to create the cos/sin lookup table with amplitude, frequency and phase
@@ -97,15 +97,15 @@ package body common_math_pkg is
function common_math_create_look_up_table_cos(N : positive; W : positive) return t_nat_integer_arr is
begin
- return common_math_create_look_up_table_cos(N, real(2**(W - 1) - 1), 1.0, 0.0);
+ return common_math_create_look_up_table_cos(N, real(2 ** (W - 1) - 1), 1.0, 0.0);
end;
function common_math_create_look_up_table_cos(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
begin
if INVERT = false then
- return common_math_create_look_up_table_cos(N, real(2**(W - 1) - 1), 1.0, 0.0);
+ return common_math_create_look_up_table_cos(N, real(2 ** (W - 1) - 1), 1.0, 0.0);
else
- return common_math_create_look_up_table_cos(N, real(2**(W - 1) - 1), 1.0, MATH_PI);
+ return common_math_create_look_up_table_cos(N, real(2 ** (W - 1) - 1), 1.0, MATH_PI);
end if;
end;
@@ -124,15 +124,15 @@ package body common_math_pkg is
function common_math_create_look_up_table_sin(N : positive; W : positive) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(N - 1 downto 0);
begin
- return common_math_create_look_up_table_sin(N, real(2**(W - 1) - 1), 1.0, 0.0);
+ return common_math_create_look_up_table_sin(N, real(2 ** (W - 1) - 1), 1.0, 0.0);
end;
function common_math_create_look_up_table_sin(N : positive; W : positive; INVERT : boolean) return t_nat_integer_arr is
begin
if INVERT = false then
- return common_math_create_look_up_table_sin(N, real(2**(W - 1) - 1), 1.0, 0.0);
+ return common_math_create_look_up_table_sin(N, real(2 ** (W - 1) - 1), 1.0, 0.0);
else
- return common_math_create_look_up_table_sin(N, real(2**(W - 1) - 1), 1.0, MATH_PI);
+ return common_math_create_look_up_table_sin(N, real(2 ** (W - 1) - 1), 1.0, MATH_PI);
end if;
end;
diff --git a/libraries/base/common/src/vhdl/common_mem_demux.vhd b/libraries/base/common/src/vhdl/common_mem_demux.vhd
index 26692341887b313712ead728d2c962313facef82..9e5725231c2ea2f5104f0807cee57ecb89aa8223 100644
--- a/libraries/base/common/src/vhdl/common_mem_demux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_demux.vhd
@@ -50,9 +50,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_demux is
generic (
diff --git a/libraries/base/common/src/vhdl/common_mem_mux.vhd b/libraries/base/common/src/vhdl/common_mem_mux.vhd
index 17b494471e212fc87aba6ec98cc93e3f892d930f..5add185cbdf6c969fe53b59ee98ca2b8a0d8bb0c 100644
--- a/libraries/base/common/src/vhdl/common_mem_mux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_mux.vhd
@@ -57,9 +57,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_mem_mux is
generic (
@@ -135,5 +135,4 @@ begin
mosi_arr <= (others => mosi); -- broadcast write to all [g_nof_mosi-1:0] MM ports
miso <= miso_arr(0); -- broadcast read only from MM port [0]
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 9f035bdfd442ab3c23d9086666076bdfbb92b927..b382acf45b9ed11c738e7191377e8cc555ca8659 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -48,9 +48,9 @@
-- sufficient widths.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
package common_mem_pkg is
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
@@ -118,16 +118,19 @@ package common_mem_pkg is
-- check and wait for mm_copi.waitrequest = '0' before removing the MM
-- access.
------------------------------------------------------------------------------
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi);
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi);
+ procedure proc_mem_bus_rd(
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi);
------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface)
@@ -186,7 +189,7 @@ package common_mem_pkg is
end record;
constant c_mem_ram_rd_latency : natural := 2; -- note common_ram_crw_crw(stratix4) now also supports read latency 1
- constant c_mem_ram : t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2**10, 'X'); -- 1 M9K
+ constant c_mem_ram : t_c_mem := (c_mem_ram_rd_latency, 10, 9, 2 ** 10, 'X'); -- 1 M9K
constant c_mem_reg_rd_latency : natural := 1;
constant c_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 32, 1, 'X');
@@ -198,7 +201,6 @@ package common_mem_pkg is
------------------------------------------------------------------------------
function func_mem_swap_endianess(mm : t_mem_miso; sz : natural) return t_mem_miso;
function func_mem_swap_endianess(mm : t_mem_mosi; sz : natural) return t_mem_mosi;
-
end common_mem_pkg;
package body common_mem_pkg is
@@ -296,26 +298,29 @@ package body common_mem_pkg is
end RESIZE_MEM_XDATA;
-- Procedures to access MM bus
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= TO_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.wrdata <= RESIZE_MEM_DATA(wr_data);
mm_copi.wr <= '1';
end proc_mem_bus_wr;
- procedure proc_mem_bus_rd(constant wr_addr : in natural;
- signal mm_copi : out t_mem_copi) is
+ procedure proc_mem_bus_rd(
+ constant wr_addr : in natural;
+ signal mm_copi : out t_mem_copi) is
begin
mm_copi.address <= TO_MEM_ADDRESS(wr_addr);
mm_copi.rd <= '1';
diff --git a/libraries/base/common/src/vhdl/common_multiplexer.vhd b/libraries/base/common/src/vhdl/common_multiplexer.vhd
index b93832dae068851bc8936653675248c181a0aceb..4c0660a53f828c69c3aaaef793490e93342b19b3 100644
--- a/libraries/base/common/src/vhdl/common_multiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_multiplexer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Assign one of g_nof_in input streams to the output based on in_sel input
-- Description: The input streams are concatenated into one SLV.
@@ -33,7 +33,7 @@ entity common_multiplexer is
g_pipeline_out : natural := 0;
g_nof_in : natural;
g_dat_w : natural
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -50,23 +50,23 @@ end;
architecture str of common_multiplexer is
begin
u_select_symbol : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_in,
- g_symbol_w => g_dat_w,
- g_sel_w => ceil_log2(g_nof_in)
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_in,
+ g_symbol_w => g_dat_w,
+ g_sel_w => ceil_log2(g_nof_in)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_data => in_dat,
- in_val => in_val,
+ in_data => in_dat,
+ in_val => in_val,
- in_sel => in_sel,
+ in_sel => in_sel,
- out_symbol => out_dat,
- out_val => out_val
- );
+ out_symbol => out_dat,
+ out_val => out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index 904b55d3dfea5b58117775a3e898fc8e8f8bc44d..d56f0276e0b94118e2ef7ea264c7fbd285ad6788 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -23,10 +23,10 @@
-- Purpose: Define the fields of network headers
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_field_pkg.all;
package common_network_layers_pkg is
-- All *_len constants are in nof octets = nof bytes = c_8 bits
@@ -90,9 +90,10 @@ package common_network_layers_pkg is
eth_type : std_logic_vector(c_network_eth_type_w - 1 downto 0);
end record;
- constant c_network_eth_header_ones : t_network_eth_header := ("000000000000000000000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "0000000000000001");
+ constant c_network_eth_header_ones : t_network_eth_header := (
+ "000000000000000000000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "0000000000000001");
------------------------------------------------------------------------------
-- IPv4 Packet
@@ -139,13 +140,13 @@ package common_network_layers_pkg is
constant c_network_ip_addr_len : natural := 4;
constant c_network_ip_addr_w : natural := c_network_ip_addr_len * c_8;
- -- [0:7] [8:15] [16:31]
+ -- [0:7] [8:15] [16:31]
constant c_network_ip_header_len : natural := c_network_ip_version_header_len + c_network_ip_services_len + c_network_ip_total_length_len +
- c_network_ip_identification_len + c_network_ip_flags_fragment_len +
- c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
- c_network_ip_addr_len +
- c_network_ip_addr_len;
- -- = c_network_ip_header_length * c_word_sz = 20
+ c_network_ip_identification_len + c_network_ip_flags_fragment_len +
+ c_network_ip_time_to_live_len + c_network_ip_protocol_len + c_network_ip_header_checksum_len +
+ c_network_ip_addr_len +
+ c_network_ip_addr_len;
+ -- = c_network_ip_header_length * c_word_sz = 20
-- default field values
constant c_network_ip_version : natural := 4; -- 4 = IPv4,
constant c_network_ip_header_length : natural := 5; -- 5 = nof words in the header, no options field support
@@ -179,11 +180,12 @@ package common_network_layers_pkg is
dst_ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet
end record;
- constant c_network_ip_header_ones : t_network_ip_header := ("0001", "0001", "00000001", "0000000000000001",
- "0000000000000001", "001", "0000000000001",
- "00000001", "00000001", "0000000000000001",
- "00000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_ip_header_ones : t_network_ip_header := (
+ "0001", "0001", "00000001", "0000000000000001",
+ "0000000000000001", "001", "0000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "00000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ARP Packet
@@ -220,12 +222,12 @@ package common_network_layers_pkg is
constant c_network_arp_oper_len : natural := 2;
constant c_network_arp_oper_w : natural := c_network_arp_oper_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_arp_data_len : natural := c_network_arp_htype_len + c_network_arp_ptype_len +
- c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len +
- c_network_eth_mac_addr_len + c_network_ip_addr_len;
- -- [0:47] [0:31] = 8 + 2*(6+4) = 28
+ c_network_arp_hlen_len + c_network_arp_plen_len + c_network_arp_oper_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len +
+ c_network_eth_mac_addr_len + c_network_ip_addr_len;
+ -- [0:47] [0:31] = 8 + 2*(6+4) = 28
-- default field values
constant c_network_arp_htype : natural := 1; -- Hardware type, 1=ethernet
@@ -251,12 +253,13 @@ package common_network_layers_pkg is
tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0); -- 4 octet, Target Protocol Address
end record;
- constant c_network_arp_packet_ones : t_network_arp_packet := ("0000000000000001", "0000000000000001",
- "00000001", "00000001", "0000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001",
- "000000000000000000000000000000000000000000000001",
- "00000000000000000000000000000001");
+ constant c_network_arp_packet_ones : t_network_arp_packet := (
+ "0000000000000001", "0000000000000001",
+ "00000001", "00000001", "0000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001",
+ "000000000000000000000000000000000000000000000001",
+ "00000000000000000000000000000001");
------------------------------------------------------------------------------
-- ICMP (for ping)
@@ -285,7 +288,7 @@ package common_network_layers_pkg is
constant c_network_icmp_sequence_len : natural := 2;
constant c_network_icmp_sequence_w : natural := c_network_icmp_sequence_len * c_8;
constant c_network_icmp_header_len : natural := c_network_icmp_msg_type_len + c_network_icmp_code_len + c_network_icmp_checksum_len +
- c_network_icmp_id_len + c_network_icmp_sequence_len;
+ c_network_icmp_id_len + c_network_icmp_sequence_len;
-- default field values
constant c_network_icmp_msg_type_request : natural := 8; -- 8 = echo request
@@ -305,8 +308,9 @@ package common_network_layers_pkg is
sequence : std_logic_vector(c_network_icmp_sequence_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_icmp_header_ones : t_network_icmp_header := ("00000001", "00000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_icmp_header_ones : t_network_icmp_header := (
+ "00000001", "00000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
------------------------------------------------------------------------------
-- UDP Packet
@@ -331,9 +335,9 @@ package common_network_layers_pkg is
constant c_network_udp_checksum_len : natural := 2;
constant c_network_udp_checksum_w : natural := c_network_udp_checksum_len * c_8;
- -- [0:15] [16:31]
+ -- [0:15] [16:31]
constant c_network_udp_header_len : natural := c_network_udp_port_len + c_network_udp_port_len +
- c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
+ c_network_udp_total_length_len + c_network_udp_checksum_len; -- 8
-- default field values
constant c_network_udp_total_length : natural := 8; -- >= 8, nof bytes in entire datagram including header and data
@@ -352,11 +356,11 @@ package common_network_layers_pkg is
checksum : std_logic_vector(c_network_udp_checksum_w - 1 downto 0); -- 2 octet
end record;
- constant c_network_udp_header_ones : t_network_udp_header := ("0000000000000001", "0000000000000001",
- "0000000000000001", "0000000000000001");
+ constant c_network_udp_header_ones : t_network_udp_header := (
+ "0000000000000001", "0000000000000001",
+ "0000000000000001", "0000000000000001");
function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
-
end common_network_layers_pkg;
package body common_network_layers_pkg is
@@ -371,8 +375,8 @@ package body common_network_layers_pkg is
begin
-- vec = whole ip header excluding ip_header_checksum.
vec :=
- hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
- & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
+ hdr_fields_slv(field_hi(field_arr, "ip_version" ) downto field_lo(field_arr, "ip_protocol" ))
+ & hdr_fields_slv(field_hi(field_arr, "ip_src_addr" ) downto field_lo(field_arr, "ip_dst_addr" ));
-- sum up vec in halfwords
for i in 0 to c_nof_halfword - 1 loop
diff --git a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
index 32587a2affb491938595856dac431fd419cf9822..1df6f5279c5cfc7c4a36c546084efd4af01caa77 100644
--- a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
@@ -50,10 +50,10 @@
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_network_layers_pkg.all;
package common_network_total_header_pkg is
-- Define total network header that fits all relevant packets in common_network_layers_pkg, because they have the same total header length
@@ -75,11 +75,12 @@ package common_network_total_header_pkg is
udp : t_network_udp_header;
end record;
- constant c_network_total_header_ones : t_network_total_header := (c_network_eth_header_ones,
- c_network_arp_packet_ones,
- c_network_ip_header_ones,
- c_network_icmp_header_ones,
- c_network_udp_header_ones);
+ constant c_network_total_header_ones : t_network_total_header := (
+ c_network_eth_header_ones,
+ c_network_arp_packet_ones,
+ c_network_ip_header_ones,
+ c_network_icmp_header_ones,
+ c_network_udp_header_ones);
-----------------------------------------------------------------------------
-- Map total network header in words array
@@ -249,12 +250,14 @@ package common_network_total_header_pkg is
-- Construct the response total header array for a total header array
function func_network_total_header_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_32b_arr;
- function func_network_total_header_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_64b_arr;
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_32b_arr;
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_64b_arr;
function func_network_total_header_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
@@ -265,19 +268,20 @@ package common_network_total_header_pkg is
-- Construct the response total header array for a total header array without alignment bytes
function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_eth( eth_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_32b_arr;
- function func_network_total_header_no_align_response_arp( arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
- return t_network_total_header_64b_arr;
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_32b_arr;
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0))
+ return t_network_total_header_64b_arr;
function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_ip( ip_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
-
end common_network_total_header_pkg;
package body common_network_total_header_pkg is
@@ -717,8 +721,9 @@ package body common_network_total_header_pkg is
end;
-- Construct the response headers
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_eth(
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -733,8 +738,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_eth(
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -749,9 +755,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -773,9 +780,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_arp(
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -796,8 +804,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_ip(
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -811,8 +820,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_ip(
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -826,8 +836,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_icmp(
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -839,8 +850,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_icmp(
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -852,8 +864,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_response_udp(
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -865,8 +878,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_response_udp(
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -879,8 +893,9 @@ package body common_network_total_header_pkg is
end;
-- Construct the response headers for headers without word align padding
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_eth(
+ eth_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- Default
@@ -895,8 +910,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_eth(
+ eth_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- Default
@@ -910,9 +926,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -934,9 +951,10 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_arp(arp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
- ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_arp(
+ arp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0);
+ ip_addr : std_logic_vector(c_network_ip_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -957,8 +975,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_ip(
+ ip_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH
@@ -974,8 +993,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_ip(ip_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_ip(
+ ip_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH
@@ -990,8 +1010,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_icmp(
+ icmp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1003,8 +1024,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_icmp(icmp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_icmp(
+ icmp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
@@ -1016,8 +1038,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_32b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
+ function func_network_total_header_no_align_response_udp(
+ udp_arr : t_network_total_header_32b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
variable v_response : t_network_total_header_32b_arr;
begin
-- ETH, IP
@@ -1029,8 +1052,9 @@ package body common_network_total_header_pkg is
return v_response;
end;
- function func_network_total_header_no_align_response_udp(udp_arr : t_network_total_header_64b_arr;
- mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
+ function func_network_total_header_no_align_response_udp(
+ udp_arr : t_network_total_header_64b_arr;
+ mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr is
variable v_response : t_network_total_header_64b_arr;
begin
-- ETH, IP
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index d807bdcd3ff29a5a83b4e57ebeeb343a42b91753..3536ed187c661f150cfc0fa888c8763ba9f28385 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_operation is
generic (
@@ -88,7 +88,9 @@ begin
a <= nxt_a;
b <= nxt_b;
end generate;
+
gen_input_reg : if g_pipeline_input > 0 generate -- register input
+
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -103,16 +105,16 @@ begin
nxt_result <= func_operation(g_operation, g_representation, a, b);
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => nxt_result,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output, -- 0 for wires, >0 for register stages
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => nxt_result,
+ out_dat => result
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index 0ad7a72e6a505ae3d16858522dab7aae34254de7..a9dad46042a205b3791281c086b83a86a61f8582 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Parallel operation tree.
-- Description:
@@ -81,50 +81,51 @@ begin
-- Adder tree
gen_stage : for j in 0 to c_nof_stages - 1 generate
- gen_oper : for i in 0 to (c_N + (2**j) - 1) / (2**(j + 1)) - 1 generate
+
+ gen_oper : for i in 0 to (c_N + (2 ** j) - 1) / (2 ** (j + 1)) - 1 generate
u_operj : entity work.common_operation
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
- in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
- in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
- in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
- result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_a => stage_arr(j - 1)((2 * i + 1) * c_w - 1 downto (2 * i + 0) * c_w),
+ in_b => stage_arr(j - 1)((2 * i + 2) * c_w - 1 downto (2 * i + 1) * c_w),
+ in_en_a => sl(stage_en_arr(j - 1)(2 * i downto 2 * i )),
+ in_en_b => sl(stage_en_arr(j - 1)(2 * i + 1 downto 2 * i + 1)),
+ result => stage_arr(j)((i + 1) * c_w - 1 downto i * c_w)
+ );
-- In case two adjacent inputs are disbaled, the result of their operation should be disabled in the next stage as well.
-- Therfor a logic OR creates the stage_en vector for the next stage.
stage_en_arr(j)(i) <= stage_en_arr(j - 1)(2 * i) or stage_en_arr(j - 1)(2 * i + 1);
end generate;
- gen_pipe : if ((c_N + (2**j) - 1) / (2**j)) mod 2 /= 0 generate
+ gen_pipe : if ((c_N + (2 ** j) - 1) / (2 ** j)) mod 2 /= 0 generate
-- In case of an odd number of inputs the enable of the last input should ripple through
-- to the place where the data is connected to a common_operation block.
- stage_en_arr(j)(c_N / (2**(j + 1))) <= in_en_vec(g_nof_inputs - 1);
+ stage_en_arr(j)(c_N / (2 ** (j + 1))) <= in_en_vec(g_nof_inputs - 1);
u_pipej : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
- g_in_dat_w => c_w,
- g_out_dat_w => c_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => stage_arr(j - 1)((2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 1) * c_w - 1 downto
- (2 * ((c_N + (2**j) - 1) / (2**(j + 1))) + 0) * c_w),
- out_dat => stage_arr(j)(((c_N + (2**j) - 1) / (2**(j + 1)) + 1) * c_w - 1 downto
- ((c_N + (2**j) - 1) / (2**(j + 1)) ) * c_w)
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => sel_a_b((j + 1) mod g_pipeline_mod = 0, c_pipeline_out, 0),
+ g_in_dat_w => c_w,
+ g_out_dat_w => c_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => stage_arr(j - 1)((2 * ((c_N + (2 ** j) - 1) / (2 ** (j + 1))) + 1) * c_w - 1 downto
+ (2 * ((c_N + (2 ** j) - 1) / (2 ** (j + 1))) + 0) * c_w),
+ out_dat => stage_arr(j)(((c_N + (2 ** j) - 1) / (2 ** (j + 1)) + 1) * c_w - 1 downto
+ ((c_N + (2 ** j) - 1) / (2 ** (j + 1)) ) * c_w)
+ );
end generate;
end generate;
@@ -133,18 +134,17 @@ begin
no_tree : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_data_vec,
- out_dat => result
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_data_vec,
+ out_dat => result
+ );
end generate; -- no_tree
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
index 6deefedd86c140de86d38e5014d945099e4078c9..c009b37087ce6e06e9268d5d25e1c081f2d48324 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
@@ -17,12 +17,12 @@
-- limitations under the License.
--
-- -----------------------------------------------------------------------------
---
--- Author:
+--
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Multi page memory with seperate clock and address per port with single wr
--- and single rd
+-- and single rd
-- Description:
-- When *_next_page pulses then the next access will occur in the next page.
-- Remarks:
@@ -46,12 +46,12 @@
-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_cr_cw is
generic (
@@ -91,72 +91,75 @@ architecture rtl of common_paged_ram_cr_cw is
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
-- g_str = "use_mux" :
- constant c_page_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_page_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
- type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
- -- g_str = "use_adr" :
- constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
- constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
- constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+ -- g_str = "use_adr" :
+ constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
+ constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
+ constant c_mem_nof_words : natural := g_nof_pages * 2 ** c_page_addr_w; -- <= 2**c_mem_addr_w
- constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_mem_addr_w,
- dat_w => g_data_w,
- nof_dat => c_mem_nof_words,
- init_sl => '0');
+ constant c_mem_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
- -- g_str = "use_ofs" :
- constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
- constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
+ -- g_str = "use_ofs" :
+ constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
+ constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
- constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_buf_addr_w,
- dat_w => g_data_w,
- nof_dat => c_buf_nof_words,
- init_sl => '0');
+ constant c_buf_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
- -- >>> Page control
+ -- >>> Page control
- -- g_str = "use_mux" and g_str = "use_adr" :
- -- . use page_sel direct for wr_en, rd_en, and address
- signal page_sel_wr : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_wr : natural;
- signal page_sel_rd : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_rd : natural;
+ -- g_str = "use_mux" and g_str = "use_adr" :
+ -- . use page_sel direct for wr_en, rd_en, and address
+ signal page_sel_wr : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_wr : natural;
+ signal page_sel_rd : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_rd : natural;
- -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
- signal page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
+ signal page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_wr_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_rd_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- -- g_str = "use_ofs" :
- signal page_ofs_wr : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_wr : natural;
- signal page_ofs_rd : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_rd : natural;
+ -- g_str = "use_ofs" :
+ signal page_ofs_wr : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_wr : natural;
+ signal page_ofs_rd : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_rd : natural;
- -- >>> Access control
+ -- >>> Access control
- -- g_str = "use_mux" :
- signal page_wr_en : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_dat : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en : std_logic_vector(0 to g_nof_pages - 1);
- signal page_rd_dat : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val : std_logic_vector(0 to g_nof_pages - 1);
+ -- g_str = "use_mux" :
+ signal page_wr_en : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val : std_logic_vector(0 to g_nof_pages - 1);
- -- g_str = "use_adr" :
- signal mem_wr_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
- signal mem_rd_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ -- g_str = "use_adr" :
+ signal mem_wr_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ signal mem_rd_adr : std_logic_vector(c_mem_addr_w - 1 downto 0);
- -- g_str = "use_ofs" :
- signal buf_wr_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
- signal buf_rd_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ -- g_str = "use_ofs" :
+ signal buf_wr_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ signal buf_rd_adr : std_logic_vector(c_buf_addr_w - 1 downto 0);
begin
-- page select (for all) and page address offset (for use_ofs)
p_reg_wr : process (wr_rst, wr_clk)
@@ -221,32 +224,33 @@ begin
end process;
gen_mux : if g_str = "use_mux" generate
+
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED"
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- wr_clken => wr_clken,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- rd_clken => rd_clken,
- wr_adr => wr_adr,
- wr_en => page_wr_en(I),
- wr_dat => wr_dat,
- rd_adr => rd_adr,
- rd_en => page_rd_en(I),
- rd_dat => page_rd_dat(I),
- rd_val => page_rd_val(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => wr_adr,
+ wr_en => page_wr_en(I),
+ wr_dat => wr_dat,
+ rd_adr => rd_adr,
+ rd_en => page_rd_en(I),
+ rd_dat => page_rd_dat(I),
+ rd_val => page_rd_val(I)
+ );
end generate;
p_mux : process(page_sel_wr, wr_en, page_sel_wr_dly, page_sel_rd,
- rd_en, page_sel_rd_dly, page_rd_dat, page_rd_val)
+ rd_en, page_sel_rd_dly, page_rd_dat, page_rd_val)
begin
-- use page_sel direct for control
page_wr_en <= (others => '0');
@@ -262,26 +266,26 @@ begin
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_ram => c_mem_ram,
- g_init_file => "UNUSED"
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- wr_clken => wr_clken,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- rd_clken => rd_clken,
- wr_adr => mem_wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- rd_adr => mem_rd_adr,
- rd_en => rd_en,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => mem_wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ rd_adr => mem_rd_adr,
+ rd_en => rd_en,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
mem_wr_adr <= TO_UVEC(page_sel_wr, c_mem_nof_pages_w) & wr_adr;
mem_rd_adr <= TO_UVEC(page_sel_rd, c_mem_nof_pages_w) & rd_adr;
@@ -289,29 +293,28 @@ begin
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf_ram,
- g_init_file => "UNUSED"
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- wr_clken => wr_clken,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- rd_clken => rd_clken,
- wr_adr => buf_wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- rd_adr => buf_rd_adr,
- rd_en => rd_en,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ wr_clken => wr_clken,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ rd_clken => rd_clken,
+ wr_adr => buf_wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ rd_adr => buf_rd_adr,
+ rd_en => rd_en,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
buf_wr_adr <= INCR_UVEC(RESIZE_UVEC(wr_adr, c_buf_addr_w), page_ofs_wr);
buf_rd_adr <= INCR_UVEC(RESIZE_UVEC(rd_adr, c_buf_addr_w), page_ofs_rd);
end generate; -- gen_ofs
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index c4012fc05482c9c5b6318d8437e6419679fd8891..1c683f510747cb02ae6d1d2f4cd4f41272aa0a92 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -17,8 +17,8 @@
-- limitations under the License.
--
-- -----------------------------------------------------------------------------
---
--- Author:
+--
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -42,12 +42,12 @@
-- for more context.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_crw_crw is
generic (
@@ -91,78 +91,81 @@ architecture rtl of common_paged_ram_crw_crw is
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
-- g_str = "use_mux" :
- constant c_page_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_page_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
- type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
- -- g_str = "use_adr" :
- constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
- constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
- constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+ -- g_str = "use_adr" :
+ constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
+ constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
+ constant c_mem_nof_words : natural := g_nof_pages * 2 ** c_page_addr_w; -- <= 2**c_mem_addr_w
- constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_mem_addr_w,
- dat_w => g_data_w,
- nof_dat => c_mem_nof_words,
- init_sl => '0');
+ constant c_mem_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
- -- g_str = "use_ofs" :
- constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
- constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
+ -- g_str = "use_ofs" :
+ constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
+ constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
- constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_buf_addr_w,
- dat_w => g_data_w,
- nof_dat => c_buf_nof_words,
- init_sl => '0');
+ constant c_buf_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
- -- >>> Page control
+ -- >>> Page control
- -- g_str = "use_mux" and g_str = "use_adr" :
- -- . use page_sel direct for wr_en, rd_en, and address
- signal page_sel_a : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_a : natural;
- signal page_sel_b : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_b : natural;
+ -- g_str = "use_mux" and g_str = "use_adr" :
+ -- . use page_sel direct for wr_en, rd_en, and address
+ signal page_sel_a : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_a : natural;
+ signal page_sel_b : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_b : natural;
- -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
- signal page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
+ signal page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- -- g_str = "use_ofs" :
- signal page_ofs_a : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_a : natural;
- signal page_ofs_b : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_b : natural;
+ -- g_str = "use_ofs" :
+ signal page_ofs_a : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_a : natural;
+ signal page_ofs_b : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_b : natural;
- -- >>> Access control
+ -- >>> Access control
- -- g_str = "use_mux" :
- signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
+ -- g_str = "use_mux" :
+ signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
- signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
- -- g_str = "use_adr" :
- signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
- signal mem_adr_b : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ -- g_str = "use_adr" :
+ signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ signal mem_adr_b : std_logic_vector(c_mem_addr_w - 1 downto 0);
- -- g_str = "use_ofs" :
- signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
- signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ -- g_str = "use_ofs" :
+ signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
begin
-- page select (for all) and page address offset (for use_ofs)
p_reg_a : process (rst_a, clk_a)
@@ -227,38 +230,39 @@ begin
end process;
gen_mux : if g_str = "use_mux" generate
+
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => adr_a,
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => adr_b,
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => adr_a,
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => adr_b,
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
p_mux : process(page_sel_a, wr_en_a, rd_en_a, page_sel_a_dly, page_rd_dat_a, page_rd_val_a,
- page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
+ page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
begin
-- use page_sel direct for control
page_wr_en_a <= (others => '0');
@@ -280,32 +284,32 @@ begin
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_mem_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => mem_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => mem_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => mem_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => mem_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
@@ -313,35 +317,34 @@ begin
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst_a => rst_a,
- rst_b => rst_b,
- clk_a => clk_a,
- clk_b => clk_b,
- clken_a => clken_a,
- clken_b => clken_b,
- adr_a => buf_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => buf_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst_a => rst_a,
+ rst_b => rst_b,
+ clk_a => clk_a,
+ clk_b => clk_b,
+ clken_a => clken_a,
+ clken_b => clken_b,
+ adr_a => buf_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => buf_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
end generate; -- gen_ofs
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index b2f05fc2700a05592eb6960dfaf96a641b20ce4c..f5fd558a366ba276d75af9964a74c0dc774cf18e 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -26,11 +26,11 @@
-- . See common_paged_ram_rw_rw for details.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_r_w is
generic (
@@ -62,34 +62,34 @@ end common_paged_ram_r_w;
architecture str of common_paged_ram_r_w is
begin
u_rw_rw : entity work.common_paged_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_str => g_str,
- g_data_w => g_data_w,
- g_nof_pages => g_nof_pages,
- g_page_sz => g_page_sz,
- g_start_page_a => g_wr_start_page,
- g_start_page_b => g_rd_start_page,
- g_rd_latency => g_rd_latency,
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- next_page_a => wr_next_page,
- adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => rd_next_page,
- adr_b => rd_adr,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en,
- rd_dat_b => rd_dat,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_str => g_str,
+ g_data_w => g_data_w,
+ g_nof_pages => g_nof_pages,
+ g_page_sz => g_page_sz,
+ g_start_page_a => g_wr_start_page,
+ g_start_page_b => g_rd_start_page,
+ g_rd_latency => g_rd_latency,
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ next_page_a => wr_next_page,
+ adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => rd_next_page,
+ adr_b => rd_adr,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en,
+ rd_dat_b => rd_dat,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 4e4405a92ab196a72c53327c42d766a1e572ca85..dd48adbf15ee38e6cbdefaafadce3bdb2cc4fc6e 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -47,12 +47,12 @@
-- [1] Based on the architecture of common_paged_ram_crw_crw.vhd.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_rw_rw is
generic (
@@ -93,78 +93,81 @@ architecture rtl of common_paged_ram_rw_rw is
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
-- g_str = "use_mux" :
- constant c_page_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_page_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
+ constant c_page_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_page_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
- type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
- -- g_str = "use_adr" :
- constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
- constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
- constant c_mem_nof_words : natural := g_nof_pages * 2**c_page_addr_w; -- <= 2**c_mem_addr_w
+ -- g_str = "use_adr" :
+ constant c_mem_nof_pages_w : natural := true_log2(g_nof_pages);
+ constant c_mem_addr_w : natural := c_mem_nof_pages_w + c_page_addr_w;
+ constant c_mem_nof_words : natural := g_nof_pages * 2 ** c_page_addr_w; -- <= 2**c_mem_addr_w
- constant c_mem_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_mem_addr_w,
- dat_w => g_data_w,
- nof_dat => c_mem_nof_words,
- init_sl => '0');
+ constant c_mem_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_mem_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_mem_nof_words,
+ init_sl => '0');
- -- g_str = "use_ofs" :
- constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
- constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
+ -- g_str = "use_ofs" :
+ constant c_buf_addr_w : natural := ceil_log2(g_nof_pages * g_page_sz);
+ constant c_buf_nof_words : natural := g_nof_pages * g_page_sz;
- constant c_buf_ram : t_c_mem := (latency => g_rd_latency,
- adr_w => c_buf_addr_w,
- dat_w => g_data_w,
- nof_dat => c_buf_nof_words,
- init_sl => '0');
+ constant c_buf_ram : t_c_mem := (
+ latency => g_rd_latency,
+ adr_w => c_buf_addr_w,
+ dat_w => g_data_w,
+ nof_dat => c_buf_nof_words,
+ init_sl => '0');
- -- >>> Page control
+ -- >>> Page control
- -- g_str = "use_mux" and g_str = "use_adr" :
- -- . use page_sel direct for wr_en, rd_en, and address
- signal page_sel_a : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_a : natural;
- signal page_sel_b : natural range 0 to g_nof_pages - 1;
- signal nxt_page_sel_b : natural;
+ -- g_str = "use_mux" and g_str = "use_adr" :
+ -- . use page_sel direct for wr_en, rd_en, and address
+ signal page_sel_a : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_a : natural;
+ signal page_sel_b : natural range 0 to g_nof_pages - 1;
+ signal nxt_page_sel_b : natural;
- -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
- signal page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- signal nxt_page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ -- . use page_sel_dly to adjust for g_rd_latency of rd_dat and rd_val
+ signal page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_a_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
+ signal nxt_page_sel_b_dly : t_page_sel_arr(0 to g_rd_latency - 1);
- -- g_str = "use_ofs" :
- signal page_ofs_a : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_a : natural;
- signal page_ofs_b : natural range 0 to c_buf_nof_words - 1;
- signal nxt_page_ofs_b : natural;
+ -- g_str = "use_ofs" :
+ signal page_ofs_a : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_a : natural;
+ signal page_ofs_b : natural range 0 to c_buf_nof_words - 1;
+ signal nxt_page_ofs_b : natural;
- -- >>> Access control
+ -- >>> Access control
- -- g_str = "use_mux" :
- signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
+ -- g_str = "use_mux" :
+ signal page_wr_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_a : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
- signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
- signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
- signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_wr_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to g_nof_pages - 1);
+ signal page_rd_dat_b : t_data_arr(0 to g_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to g_nof_pages - 1);
- -- g_str = "use_adr" :
- signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
- signal mem_adr_b : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ -- g_str = "use_adr" :
+ signal mem_adr_a : std_logic_vector(c_mem_addr_w - 1 downto 0);
+ signal mem_adr_b : std_logic_vector(c_mem_addr_w - 1 downto 0);
- -- g_str = "use_ofs" :
- signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
- signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ -- g_str = "use_ofs" :
+ signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
+ signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
begin
-- page select (for all) and page address offset (for use_ofs)
p_reg_a : process (rst, clk)
@@ -229,35 +232,36 @@ begin
end process;
gen_mux : if g_str = "use_mux" generate
+
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => adr_a,
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => adr_b,
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => adr_a,
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => adr_b,
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
p_mux : process(page_sel_a, wr_en_a, rd_en_a, page_sel_a_dly, page_rd_dat_a, page_rd_val_a,
- page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
+ page_sel_b, wr_en_b, rd_en_b, page_sel_b_dly, page_rd_dat_b, page_rd_val_b)
begin
-- use page_sel direct for control
page_wr_en_a <= (others => '0');
@@ -279,29 +283,29 @@ begin
gen_adr : if g_str = "use_adr" generate
u_mem : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_mem_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => mem_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => mem_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mem_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => mem_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => mem_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
mem_adr_a <= TO_UVEC(page_sel_a, c_mem_nof_pages_w) & adr_a;
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
@@ -309,32 +313,31 @@ begin
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => buf_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => rd_en_a,
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- adr_b => buf_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- rd_en_b => rd_en_b,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => buf_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => rd_en_a,
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ adr_b => buf_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ rd_en_b => rd_en_b,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
buf_adr_a <= INCR_UVEC(RESIZE_UVEC(adr_a, c_buf_addr_w), page_ofs_a);
buf_adr_b <= INCR_UVEC(RESIZE_UVEC(adr_b, c_buf_addr_w), page_ofs_b);
end generate; -- gen_ofs
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index 4c253131235954b6e58b1a55d0afa6eb6a4f19ec..98034f12cebb47884962c983b3fe5f318204d325 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -26,9 +26,9 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_w_rr is
generic (
@@ -65,33 +65,33 @@ end common_paged_ram_w_rr;
architecture str of common_paged_ram_w_rr is
begin
u_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_technology => g_technology,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => g_data_w,
- g_page_sz => g_page_sz,
- g_ram_rd_latency => g_ram_rd_latency
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- -- next page control
- next_page => next_page,
- -- double write access to one page --> use only page a
- wr_adr_a => wr_adr,
- wr_en_a => wr_en,
- wr_dat_a => wr_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => rd_dat_a,
- rd_val_a => rd_val_a,
- rd_dat_b => rd_dat_b,
- rd_val_b => rd_val_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => g_data_w,
+ g_page_sz => g_page_sz,
+ g_ram_rd_latency => g_ram_rd_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page --> use only page a
+ wr_adr_a => wr_adr,
+ wr_en_a => wr_en,
+ wr_dat_a => wr_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => rd_dat_a,
+ rd_val_a => rd_val_a,
+ rd_dat_b => rd_dat_b,
+ rd_val_b => rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 8a0e60be2e9fc87e21176f90504d5e47ff4fd7d8..0e134ba17625da36c7c37013545f28245a8f68da 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -26,11 +26,11 @@
-- Each page uses one or more RAM blocks.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.common_components_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.common_components_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_paged_ram_ww_rr is
generic (
@@ -76,52 +76,53 @@ architecture rtl of common_paged_ram_ww_rr is
constant c_addr_w : natural := ceil_log2(g_page_sz);
- constant c_page_ram : t_c_mem := (latency => g_ram_rd_latency,
- adr_w => c_addr_w,
- dat_w => g_data_w,
- nof_dat => g_page_sz,
- init_sl => '0');
-
- type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
- type t_addr_arr is array (integer range <>) of std_logic_vector(c_addr_w - 1 downto 0);
-
- -- Page select control
- signal page_sel : std_logic;
- signal nxt_page_sel : std_logic;
- signal page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
- signal nxt_page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
- signal page_sel_in : std_logic;
- signal page_sel_out : std_logic;
-
- -- Double write in one page and double read in the other page
- -- . input
- signal nxt_page_wr_dat_a : std_logic_vector(g_data_w - 1 downto 0);
- signal nxt_page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
- signal page_wr_dat_a : std_logic_vector(g_data_w - 1 downto 0);
- signal page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
- signal nxt_page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
- signal nxt_page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
- signal page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
- signal page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
- signal nxt_page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
- signal nxt_page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
- signal page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
- signal page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
- signal nxt_page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
- signal nxt_page_adr_b : t_addr_arr(0 to c_nof_pages - 1);
- signal page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
- signal page_adr_b : t_addr_arr(0 to c_nof_pages - 1);
-
- -- . output
- signal page_rd_dat_a : t_data_arr(0 to c_nof_pages - 1);
- signal page_rd_val_a : std_logic_vector(0 to c_nof_pages - 1);
- signal page_rd_dat_b : t_data_arr(0 to c_nof_pages - 1);
- signal page_rd_val_b : std_logic_vector(0 to c_nof_pages - 1);
-
- signal nxt_rd_dat_a : std_logic_vector(g_data_w - 1 downto 0);
- signal nxt_rd_val_a : std_logic;
- signal nxt_rd_dat_b : std_logic_vector(g_data_w - 1 downto 0);
- signal nxt_rd_val_b : std_logic;
+ constant c_page_ram : t_c_mem := (
+ latency => g_ram_rd_latency,
+ adr_w => c_addr_w,
+ dat_w => g_data_w,
+ nof_dat => g_page_sz,
+ init_sl => '0');
+
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+ type t_addr_arr is array (integer range <>) of std_logic_vector(c_addr_w - 1 downto 0);
+
+ -- Page select control
+ signal page_sel : std_logic;
+ signal nxt_page_sel : std_logic;
+ signal page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
+ signal nxt_page_sel_dly : std_logic_vector(0 to c_sel_latency - 1);
+ signal page_sel_in : std_logic;
+ signal page_sel_out : std_logic;
+
+ -- Double write in one page and double read in the other page
+ -- . input
+ signal nxt_page_wr_dat_a : std_logic_vector(g_data_w - 1 downto 0);
+ signal nxt_page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
+ signal page_wr_dat_a : std_logic_vector(g_data_w - 1 downto 0);
+ signal page_wr_dat_b : std_logic_vector(g_data_w - 1 downto 0);
+ signal nxt_page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_wr_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_wr_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_rd_en_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_rd_en_b : std_logic_vector(0 to c_nof_pages - 1);
+ signal nxt_page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
+ signal nxt_page_adr_b : t_addr_arr(0 to c_nof_pages - 1);
+ signal page_adr_a : t_addr_arr(0 to c_nof_pages - 1);
+ signal page_adr_b : t_addr_arr(0 to c_nof_pages - 1);
+
+ -- . output
+ signal page_rd_dat_a : t_data_arr(0 to c_nof_pages - 1);
+ signal page_rd_val_a : std_logic_vector(0 to c_nof_pages - 1);
+ signal page_rd_dat_b : t_data_arr(0 to c_nof_pages - 1);
+ signal page_rd_val_b : std_logic_vector(0 to c_nof_pages - 1);
+
+ signal nxt_rd_dat_a : std_logic_vector(g_data_w - 1 downto 0);
+ signal nxt_rd_val_a : std_logic;
+ signal nxt_rd_dat_b : std_logic_vector(g_data_w - 1 downto 0);
+ signal nxt_rd_val_b : std_logic;
begin
-- page select
p_reg : process (rst, clk)
@@ -177,28 +178,28 @@ begin
u_pipe_page_adr_b : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, c_addr_w, c_addr_w) port map (rst, clk, clken, '0', '1', nxt_page_adr_b(I), page_adr_b(I));
u_page : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => c_page_ram,
- g_init_file => "UNUSED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- adr_a => page_adr_a(I),
- wr_en_a => page_wr_en_a(I),
- wr_dat_a => page_wr_dat_a,
- rd_en_a => page_rd_en_a(I),
- rd_dat_a => page_rd_dat_a(I),
- rd_val_a => page_rd_val_a(I),
- adr_b => page_adr_b(I),
- wr_en_b => page_wr_en_b(I),
- wr_dat_b => page_wr_dat_b,
- rd_en_b => page_rd_en_b(I),
- rd_dat_b => page_rd_dat_b(I),
- rd_val_b => page_rd_val_b(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_page_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ adr_a => page_adr_a(I),
+ wr_en_a => page_wr_en_a(I),
+ wr_dat_a => page_wr_dat_a,
+ rd_en_a => page_rd_en_a(I),
+ rd_dat_a => page_rd_dat_a(I),
+ rd_val_a => page_rd_val_a(I),
+ adr_b => page_adr_b(I),
+ wr_en_b => page_wr_en_b(I),
+ wr_dat_b => page_wr_dat_b,
+ rd_en_b => page_rd_en_b(I),
+ rd_dat_b => page_rd_dat_b(I),
+ rd_val_b => page_rd_val_b(I)
+ );
end generate;
-- use page_sel_out to account for the RAM read latency
diff --git a/libraries/base/common/src/vhdl/common_paged_reg.vhd b/libraries/base/common/src/vhdl/common_paged_reg.vhd
index 1e02358fc6f748f42a4df1a020cf466479a27893..80a6d807de7f864d6456ba15df8065c7378df258 100644
--- a/libraries/base/common/src/vhdl/common_paged_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_reg.vhd
@@ -27,8 +27,8 @@
-- Remarks:
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_paged_reg is
generic (
@@ -56,17 +56,16 @@ begin
-- Shift the intermediate data pages when enabled
gen_pages : for I in g_nof_pages - 1 downto 0 generate
u_page : entity work.common_pipeline
- generic map (
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_en => wr_en(I),
- in_dat => reg_dat(I + 1),
- out_dat => reg_dat(I)
- );
+ generic map (
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_en => wr_en(I),
+ in_dat => reg_dat(I + 1),
+ out_dat => reg_dat(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_peak.vhd b/libraries/base/common/src/vhdl/common_peak.vhd
index 0e71cf50f5c2e11aad3e36c8b8879bcfe664f825..4b1b5000250e531d2a7b518112dc2cff87fa2f14 100644
--- a/libraries/base/common/src/vhdl/common_peak.vhd
+++ b/libraries/base/common/src/vhdl/common_peak.vhd
@@ -28,8 +28,8 @@
--
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_peak is
generic (
@@ -72,20 +72,20 @@ begin
end if;
if(rst = '1') then
- v.peak := (others => '0');
- v.out_val := '0';
- end if;
+ v.peak := (others => '0');
+ v.out_val := '0';
+ end if;
- rin <= v;
- end process;
+ rin <= v;
+end process;
- p_regs : process(clk)
- begin
- if rising_edge(clk) then
- r <= rin;
- end if;
- end process;
+p_regs : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
- out_val <= r.out_val;
- out_dat <= r.peak;
+out_val <= r.out_val;
+out_dat <= r.peak;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index 27d000cd2b1f9cf65557a442b6bd99b5524a5484..441adfd1d365793a0a3594d4d3f4e80e3ea2c35d 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline is
generic (
@@ -50,6 +50,7 @@ architecture rtl of common_pipeline is
signal out_dat_p : t_out_dat(0 to g_pipeline) := (others => c_reset_value);
begin
gen_pipe_n : if g_pipeline > 0 generate
+
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -67,7 +68,7 @@ begin
end generate;
out_dat_p(0) <= RESIZE_SVEC(in_dat, out_dat'length) when g_representation = "SIGNED" else
- RESIZE_UVEC(in_dat, out_dat'length) when g_representation = "UNSIGNED";
+ RESIZE_UVEC(in_dat, out_dat'length) when g_representation = "UNSIGNED";
out_dat <= out_dat_p(g_pipeline);
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index 5965cde936445198449e97e2e441b7ffb0b657e3..c081c4bb298e1c98dfab16b65f157236775266b6 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_integer is
generic (
@@ -49,20 +49,20 @@ begin
out_dat <= TO_SINT(out_dat_slv) when g_representation = "SIGNED" else TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
index 971946f8d493a5ab394837cabc938ac36ed547f9..dbd5261009be5d15c04925a2f88b4d4bc8cb2aed 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pipeline_natural is
generic (
@@ -48,20 +48,20 @@ begin
out_dat <= TO_UINT(out_dat_slv);
u_int : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value,
- g_in_dat_w => g_dat_w,
- g_out_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value,
+ g_in_dat_w => g_dat_w,
+ g_out_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
index 0d592b72419de476307bb184b4820be12f7ae97a..803c854134fa76f4c808dd38ed922b4e8755f3ef 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity common_pipeline_sl is
generic (
@@ -49,20 +49,20 @@ begin
out_dat <= out_dat_slv(0);
u_sl : entity work.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => g_pipeline,
- g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_clr => in_clr,
- in_en => in_en,
- in_dat => in_dat_slv,
- out_dat => out_dat_slv
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => g_pipeline,
+ g_reset_value => sel_a_b(g_out_invert, 1 - g_reset_value, g_reset_value),
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_clr => in_clr,
+ in_en => in_en,
+ in_dat => in_dat_slv,
+ out_dat => out_dat_slv
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
index 8d883bbf79825eb22ceaac144aab055bc737e26a..f60e7383269b691e2e75fe7f5d6243739655b6c6 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol pipeline of the input data stream
-- Description:
@@ -65,53 +65,52 @@ begin
-- pipeline per symbol
u_pipe_symbol : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat_arr(I),
- out_dat => out_dat_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat_arr(I),
+ out_dat => out_dat_arr(I)
+ );
u_pipe_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val_arr(I)
+ );
u_pipe_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop_arr(I)
+ );
u_pipe_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_arr(I)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline_arr(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 9fdebec8751b6b80700e888d8d71b31456b45b13..8175b5002746233dbf1784f62a8495cd050b58fc 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -27,9 +27,9 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
package common_pkg is
-- CONSTANT DECLARATIONS ----------------------------------------------------
@@ -468,7 +468,7 @@ package common_pkg is
function INCR_UVEC(vec : std_logic_vector; dec : unsigned) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : integer) return std_logic_vector;
function INCR_SVEC(vec : std_logic_vector; dec : signed) return std_logic_vector;
- -- Used in common_add_sub.vhd
+ -- Used in common_add_sub.vhd
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as signed, slv output width is res_w
function SUB_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec - r_vec, treat slv operands as signed, slv output width is res_w
function ADD_UVEC(l_vec : std_logic_vector; r_vec : std_logic_vector; res_w : natural) return std_logic_vector; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is res_w
@@ -569,20 +569,22 @@ package common_pkg is
------------------------------------------------------------------------------
-- common_fifo_*
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic);
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic);
-- common_fanout_tree
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr;
-- common_reorder_symbol
function func_common_reorder2_is_there(I, J : natural) return boolean;
@@ -592,51 +594,51 @@ package common_pkg is
function func_common_reorder2_inverse_select(N : natural; select_arr : t_natural_arr) return t_natural_arr;
-- Generate faster sample SCLK from digital DCLK for sim only
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic);
-
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic);
end common_pkg;
package body common_pkg is
function pow2(n : natural) return natural is
begin
- return 2**n;
+ return 2 ** n;
end;
function ceil_pow2(n : integer) return natural is
- -- Also allows negative exponents and rounds up before returning the value
+ -- Also allows negative exponents and rounds up before returning the value
begin
- return natural(integer(ceil(2**real(n))));
+ return natural(integer(ceil(2 ** real(n))));
end;
function true_log2(n : natural) return natural is
- -- Purpose: For calculating extra vector width of existing vector
- -- Description: Return mathematical ceil(log2(n))
- -- n log2()
- -- 0 -> -oo --> FAILURE
- -- 1 -> 0
- -- 2 -> 1
- -- 3 -> 2
- -- 4 -> 2
- -- 5 -> 3
- -- 6 -> 3
- -- 7 -> 3
- -- 8 -> 3
- -- 9 -> 4
- -- etc, up to n = NATURAL'HIGH = 2**31-1
+ -- Purpose: For calculating extra vector width of existing vector
+ -- Description: Return mathematical ceil(log2(n))
+ -- n log2()
+ -- 0 -> -oo --> FAILURE
+ -- 1 -> 0
+ -- 2 -> 1
+ -- 3 -> 2
+ -- 4 -> 2
+ -- 5 -> 3
+ -- 6 -> 3
+ -- 7 -> 3
+ -- 8 -> 3
+ -- 9 -> 4
+ -- etc, up to n = NATURAL'HIGH = 2**31-1
begin
return natural(integer(ceil(log2(real(n)))));
end;
function ceil_log2(n : natural) return natural is
- -- Purpose: For calculating vector width of new vector
- -- Description:
- -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
- -- the vector width width for 1 address, to avoid NULL array for single
- -- word register address.
- -- If n = 0, return 0 so we get a NULL array when using
- -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
+ -- Purpose: For calculating vector width of new vector
+ -- Description:
+ -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
+ -- the vector width width for 1 address, to avoid NULL array for single
+ -- word register address.
+ -- If n = 0, return 0 so we get a NULL array when using
+ -- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
begin
if n = 0 then
return 0; -- Get NULL array
@@ -654,12 +656,12 @@ package body common_pkg is
function is_pow2(n : natural) return boolean is
begin
- return n = 2**true_log2(n);
+ return n = 2 ** true_log2(n);
end;
function true_log_pow2(n : natural) return natural is
begin
- return 2**true_log2(n);
+ return 2 ** true_log2(n);
end;
function ratio(n, d : natural) return natural is
@@ -832,7 +834,7 @@ package body common_pkg is
begin
assert data'length = c_nof_octets * c_octet_w
report "common_pkg: unpack_data must be integer number of octest"
- severity FAILURE;
+ severity FAILURE;
for I in v_a'range loop
v_a(I) := v_data((I + 1) * c_octet_w - 1 downto I * c_octet_w);
end loop;
@@ -926,7 +928,7 @@ package body common_pkg is
-- Instead use binary tree to determine result with smallest combinatorial delay that depends on log2(slv'LENGTH)
constant c_slv_w : natural := slv'length;
constant c_nof_stages : natural := ceil_log2(c_slv_w);
- constant c_w : natural := 2**c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
+ constant c_w : natural := 2 ** c_nof_stages; -- extend the input slv to a vector with length power of 2 to ease using binary tree
type t_stage_arr is array (-1 to c_nof_stages - 1) of std_logic_vector(c_w - 1 downto 0);
variable v_stage_arr : t_stage_arr;
variable v_result : std_logic := '0';
@@ -940,7 +942,7 @@ package body common_pkg is
end if;
v_stage_arr(-1)(c_slv_w - 1 downto 0) := slv; -- any unused input c_w : c_slv_w bits have void default value
for J in 0 to c_nof_stages - 1 loop
- for I in 0 to c_w / (2**(J + 1)) - 1 loop
+ for I in 0 to c_w / (2 ** (J + 1)) - 1 loop
if operation = "AND" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) and v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "OR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) or v_stage_arr(J - 1)(2 * I + 1);
elsif operation = "XOR" then v_stage_arr(J)(I) := v_stage_arr(J - 1)(2 * I) xor v_stage_arr(J - 1)(2 * I + 1);
@@ -1058,7 +1060,7 @@ package body common_pkg is
function smallest(n, m, l : integer) return integer is
variable v : natural;
begin
- v := n;
+ v := n;
if v > m then v := m; end if;
if v > l then v := l; end if;
return v;
@@ -1988,7 +1990,7 @@ package body common_pkg is
end;
function TO_UINT(udec : real; w, resolution_w : integer) return natural is
- constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
+ constant c_resolution : real := 1.0 / 2.0 ** real(resolution_w);
constant c_ureal : real := ROUND(udec / c_resolution); -- rounds away from zero
begin
if udec >= 0.0 then
@@ -2000,9 +2002,9 @@ package body common_pkg is
end;
function TO_SINT(sdec : real; w, resolution_w : integer) return integer is
- constant c_max : real := 2.0**REAL(w - 1) - 1.0;
- constant c_min : real := -2.0**REAL(w - 1);
- constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
+ constant c_max : real := 2.0 ** real(w - 1) - 1.0;
+ constant c_min : real := -2.0 ** real(w - 1);
+ constant c_resolution : real := 1.0 / 2.0 ** real(resolution_w);
constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
constant c_sint : integer := integer(c_sreal);
begin
@@ -2022,8 +2024,8 @@ package body common_pkg is
function TO_UVEC(udec : real; w, resolution_w : integer) return std_logic_vector is
-- Determine range that fits w bits
constant c_uvec_max : std_logic_vector(w - 1 downto 0) := (others => '1');
- constant c_max : real := 2.0**REAL(w) - 1.0;
- constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
+ constant c_max : real := 2.0 ** real(w) - 1.0;
+ constant c_resolution : real := 1.0 / 2.0 ** real(resolution_w);
variable v_ureal : real := ROUND(udec / c_resolution); -- rounds away from zero
-- Convert to uvec
variable v_floor : real := 0.0;
@@ -2068,12 +2070,12 @@ package body common_pkg is
-- Determine range that fits w bits
constant c_svec_max : std_logic_vector(w - 1 downto 0) := '0' & (w - 2 downto 0 => '1');
constant c_svec_min : std_logic_vector(w - 1 downto 0) := '1' & (w - 2 downto 0 => '0');
- constant c_max : real := 2.0**REAL(w - 1) - 1.0;
- constant c_min : real := -2.0**REAL(w - 1);
- constant c_resolution : real := 1.0 / 2.0**REAL(resolution_w);
+ constant c_max : real := 2.0 ** real(w - 1) - 1.0;
+ constant c_min : real := -2.0 ** real(w - 1);
+ constant c_resolution : real := 1.0 / 2.0 ** real(resolution_w);
constant c_sreal : real := ROUND(sdec / c_resolution); -- rounds away from zero
- -- Convert to positive using TO_UVEC, so if sdec is negative, then
- -- negate sdec to have positive c_udec.
+ -- Convert to positive using TO_UVEC, so if sdec is negative, then
+ -- negate sdec to have positive c_udec.
constant c_pos : boolean := sdec >= 0.0;
constant c_udec : real := sel_a_b(c_pos, sdec, -sdec);
-- Determine SLV value for positive REAL, use w+1 to fit negate of most negative value
@@ -2102,7 +2104,7 @@ package body common_pkg is
-- Avoid using INTEGER, which is limited to 32 bit, by determining per bit whether it contributes to the REAL value
for I in 0 to c_len - 1 loop
if c_uvec(I) = '1' then
- v_real := v_real + 2.0**REAL(I);
+ v_real := v_real + 2.0 ** real(I);
end if;
end loop;
return v_real;
@@ -2129,7 +2131,7 @@ package body common_pkg is
begin
-- First convert as unsigned integer, then scale to real. See TO_SREAL()
-- for interpretation of resolution_w
- return TO_UREAL(uvec) / 2.0**REAL(resolution_w);
+ return TO_UREAL(uvec) / 2.0 ** real(resolution_w);
end;
function TO_SREAL(svec : std_logic_vector; resolution_w : integer) return real is
@@ -2141,7 +2143,7 @@ package body common_pkg is
-- . resolution_w = 0 : scale by 2**0 = 1, so no scaling and the value is treated as an integer
-- . resolution_w < 0 : scale up
-- . resolution_w > 0 : scale down
- return TO_SREAL(svec) / 2.0**REAL(resolution_w);
+ return TO_SREAL(svec) / 2.0 ** real(resolution_w);
end;
function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
@@ -2217,8 +2219,8 @@ package body common_pkg is
-- Negate vec, but avoid overflow by forcing -min to +max. Use w <= vec'LENGTH.
function NEGATE_SVEC(vec : std_logic_vector; w : integer) return std_logic_vector is
- constant c_max : integer := 2**(w - 1) - 1;
- constant c_min : integer := -2**(w - 1);
+ constant c_max : integer := 2 ** (w - 1) - 1;
+ constant c_min : integer := -2 ** (w - 1);
constant c_vec_w : natural := vec'length;
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec; -- independent of vec'RANGE
variable v_val : std_logic_vector(w - 1 downto 0);
@@ -2330,7 +2332,7 @@ package body common_pkg is
-- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0.
-- Must must use brackets (ABS()) to avoid compile error.
-- Alternative equivalent code would be: SQRT(re * re + im * im).
- return SQRT((abs(re))**2.0 + (abs(im))**2.0);
+ return SQRT((abs(re)) ** 2.0 + (abs(im)) ** 2.0);
end;
function COMPLEX_RADIUS(re, im : integer) return real is
@@ -2432,10 +2434,10 @@ package body common_pkg is
begin
if shift < 0 then
return std_logic_vector(ROTATE_LEFT(unsigned(vec), -shift)); -- /<-- vec <--\
- -- \---------->/
+ -- \---------->/
else
return std_logic_vector(ROTATE_RIGHT(unsigned(vec), shift)); -- /--> vec -->\
- -- \<----------/
+ -- \<----------/
end if;
end;
@@ -2459,8 +2461,8 @@ package body common_pkg is
function offset_binary(a : std_logic_vector) return std_logic_vector is
variable v_res : std_logic_vector(a'length - 1 downto 0) := a;
begin
- v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
- return v_res;
+ v_res(v_res'high) := not v_res(v_res'high); -- invert MSbit to get to from offset binary to two's complement, or vice versa
+ return v_res;
end;
function truncate(vec : std_logic_vector; n : natural) return std_logic_vector is
@@ -2469,8 +2471,8 @@ package body common_pkg is
variable v_vec : std_logic_vector(c_vec_w - 1 downto 0) := vec;
variable v_res : std_logic_vector(c_trunc_w - 1 downto 0);
begin
- v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
- return v_res;
+ v_res := v_vec(c_vec_w - 1 downto n); -- keep MS part
+ return v_res;
end;
function truncate_and_resize_uvec(vec : std_logic_vector; n, w : natural) return std_logic_vector is
@@ -2928,16 +2930,17 @@ package body common_pkg is
-- common_fifo_*
------------------------------------------------------------------------------
- procedure proc_common_fifo_asserts (constant c_fifo_name : in string;
- constant c_note_is_ful : in boolean;
- constant c_fail_rd_emp : in boolean;
- signal wr_rst : in std_logic;
- signal wr_clk : in std_logic;
- signal wr_full : in std_logic;
- signal wr_en : in std_logic;
- signal rd_clk : in std_logic;
- signal rd_empty : in std_logic;
- signal rd_en : in std_logic) is
+ procedure proc_common_fifo_asserts (
+ constant c_fifo_name : in string;
+ constant c_note_is_ful : in boolean;
+ constant c_fail_rd_emp : in boolean;
+ signal wr_rst : in std_logic;
+ signal wr_clk : in std_logic;
+ signal wr_full : in std_logic;
+ signal wr_en : in std_logic;
+ signal rd_clk : in std_logic;
+ signal rd_empty : in std_logic;
+ signal rd_en : in std_logic) is
begin
-- c_fail_rd_emp : when TRUE report FAILURE when read from an empty FIFO, important when FIFO rd_val is not used
-- c_note_is_ful : when TRUE report NOTE when FIFO goes full, to note that operation is on the limit
@@ -2969,8 +2972,9 @@ package body common_pkg is
-- common_fanout_tree
------------------------------------------------------------------------------
- function func_common_fanout_tree_pipelining(c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
- c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
+ function func_common_fanout_tree_pipelining(
+ c_nof_stages, c_nof_output_per_cell, c_nof_output : natural;
+ c_cell_pipeline_factor_arr, c_cell_pipeline_arr : t_natural_arr) return t_natural_arr is
constant k_cell_pipeline_factor_arr : t_natural_arr(c_nof_stages - 1 downto 0) := c_cell_pipeline_factor_arr;
constant k_cell_pipeline_arr : t_natural_arr(c_nof_output_per_cell - 1 downto 0) := c_cell_pipeline_arr;
variable v_stage_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := (others => 0);
@@ -2978,7 +2982,7 @@ package body common_pkg is
begin
loop_stage : for j in 0 to c_nof_stages - 1 loop
v_prev_stage_pipeline_arr := v_stage_pipeline_arr;
- loop_cell : for i in 0 to c_nof_output_per_cell**j - 1 loop
+ loop_cell : for i in 0 to c_nof_output_per_cell ** j - 1 loop
v_stage_pipeline_arr((i + 1) * c_nof_output_per_cell - 1 downto i * c_nof_output_per_cell) := v_prev_stage_pipeline_arr(i) + (k_cell_pipeline_factor_arr(j) * k_cell_pipeline_arr);
end loop;
end loop;
@@ -3073,8 +3077,8 @@ package body common_pkg is
else
-- N is even so only use stage 1 of the inverse_out reorder, the other stages remain at default pass on
for K in 0 to N / 2 - 1 loop
- v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
- v_inverse_arr(v_Ki) := c_select_arr(K);
+ v_Ki := c_nof_select + K; -- stage 1 of the inverse_out reorder
+ v_inverse_arr(v_Ki) := c_select_arr(K);
end loop;
-- N is even so leave stage 1 of the inverse_in reorder at default pass on, and do inverse the other stages
for I in 2 to N loop
@@ -3113,9 +3117,10 @@ package body common_pkg is
-- that they all apply to the same wide data word that was clocked by the
-- rising edge of the DCLK.
------------------------------------------------------------------------------
- procedure proc_common_dclk_generate_sclk(constant Pfactor : in positive;
- signal dclk : in std_logic;
- signal sclk : inout std_logic) is
+ procedure proc_common_dclk_generate_sclk(
+ constant Pfactor : in positive;
+ signal dclk : in std_logic;
+ signal sclk : inout std_logic) is
variable v_dperiod : time;
variable v_speriod : time;
begin
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay.vhd b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
index 66ffa0296b87fcc73b80afe230f814cc1e23d0f7..3d381110182a8ad82bbaeeca691dcaa4b1faf128 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
@@ -26,8 +26,8 @@
-- . Note: pulse_out must have occurured before the next pulse_in can be delayed.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_pulse_delay is
generic (
@@ -58,17 +58,17 @@ begin
-- Switch to start counter @ pulse_in, and stop counter @ pulse_out.
-------------------------------------------------------------------------------
u_common_switch : entity work.common_switch
- generic map (
- g_or_high => true,
- g_priority_lo => false
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => pulse_in,
- switch_low => nxt_pulse_out,
- out_level => common_counter_cnt_en
- );
+ generic map (
+ g_or_high => true,
+ g_priority_lo => false
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => pulse_in,
+ switch_low => nxt_pulse_out,
+ out_level => common_counter_cnt_en
+ );
-------------------------------------------------------------------------------
-- Count delay cycles relative to pulse_in
@@ -78,18 +78,18 @@ begin
-- output count value after cnt_en (also 0).
-------------------------------------------------------------------------------
u_common_counter : entity work.common_counter
- generic map (
- g_width => c_pulse_delay_max_width,
- g_init => 1
- )
- port map (
- clk => clk,
- rst => rst,
- cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
- cnt_en => common_counter_cnt_en,
- load => TO_UVEC(1, c_pulse_delay_max_width),
- count => common_counter_count
- );
+ generic map (
+ g_width => c_pulse_delay_max_width,
+ g_init => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ cnt_ld => pulse_in, -- Clear (load "1") the counter on every pulse_in
+ cnt_en => common_counter_cnt_en,
+ load => TO_UVEC(1, c_pulse_delay_max_width),
+ count => common_counter_count
+ );
-------------------------------------------------------------------------------
-- Assign nxt_pulse_out
@@ -98,12 +98,13 @@ begin
nxt_pulse_delay_reg <= pulse_delay when pulse_in = '1' else pulse_delay_reg;
nxt_pulse_out <= pulse_in when pulse_delay = TO_UVEC(0, c_pulse_delay_max_width) else -- 0 cycles delay (pulse_delay_reg not valid yet; using pulse_delay)
- '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
+ '1' when common_counter_count = pulse_delay_reg else '0'; -- >=1 cycles delay (so pulse_delay_reg will contain registered pulse_delay)
-------------------------------------------------------------------------------
-- Optional output register
-------------------------------------------------------------------------------
gen_register : if g_register_out = true generate
+
p_clk : process (rst, clk)
begin
if rst = '1' then
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index f4e02fa89d7abea93b3391c150b08aa2e35abee7..33bdfda9612848361220baa1692bd65e63705a90 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -27,15 +27,15 @@
-- Set pulse_delay between incoming and outgoing pulse, in units of dp_clk cycles (5ns)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity common_pulse_delay_reg is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and pulse_clk are the same, else use TRUE to cross the clock domain
g_pulse_delay_max : natural := 0 -- Maximum number of clk cycles that pulse can be delayed
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -51,13 +51,14 @@ end common_pulse_delay_reg;
architecture rtl of common_pulse_delay_reg is
constant c_nof_mm_regs : natural := 1;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_mm_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_mm_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_mm_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_mm_regs,
+ init_sl => '0');
- signal mm_pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
+ signal mm_pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -88,7 +89,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -124,16 +125,15 @@ begin
gen_common_reg_cross_domain : if g_cross_clock_domain = true generate
u_common_reg_cross_domain : entity work.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_pulse_delay,
- in_done => OPEN,
- out_rst => pulse_rst,
- out_clk => pulse_clk,
- out_dat => pulse_delay,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_pulse_delay,
+ in_done => OPEN,
+ out_rst => pulse_rst,
+ out_clk => pulse_clk,
+ out_dat => pulse_delay,
+ out_new => open
+ );
end generate; -- gen_common_reg_cross_domain
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 23b38e1ebf0c4f404cd18e126280c803865b4914..3f302f23fd923559046bc39f9dd2e8e9f9a8e459 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Extend the active high time of a pulse
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
index 5100346bb59a6726d1cc421478d65f3a9a367455..d9af0fd72234bf51f8dc0d0076cb6dfbac829d55 100644
--- a/libraries/base/common/src/vhdl/common_pulser.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Output a one cycle pulse every period
-- Description:
@@ -58,7 +58,7 @@ architecture rtl of common_pulser is
-- For example for c_pulse_period_w = w = 3:
-- 0 1 2 3 4 5 6 7
-- 0 1 2 3 -4 -3 -2 -1 --> if p < 2**(w-1) then return phs else return phs-2**w
- constant c_pulse_init : integer := sel_a_b(g_pulse_phase < 2**(c_pulse_period_w - 1), g_pulse_phase, g_pulse_phase-2**c_pulse_period_w);
+ constant c_pulse_init : integer := sel_a_b(g_pulse_phase < 2 ** (c_pulse_period_w - 1), g_pulse_phase, g_pulse_phase-2 ** c_pulse_period_w);
signal cnt : std_logic_vector(c_pulse_period_w - 1 downto 0) := (others => '0');
signal cnt_en : std_logic;
@@ -83,16 +83,16 @@ begin
cnt_clr <= pulse_clr or cnt_period;
u_cnt : entity common_lib.common_counter
- generic map (
- g_init => c_pulse_init,
- g_width => c_pulse_period_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_init => c_pulse_init,
+ g_width => c_pulse_period_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
index 0afbe95fb9133a89cdcb03bb99ac462450ea5fda..7fd83ee3ed16641bca1571b78af255453e0277e3 100644
--- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Provide timing pulses for interval 1 us, 1 ms and 1 s
@@ -73,44 +73,44 @@ begin
end process;
u_common_pulser_us : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_us,
- g_pulse_phase => g_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => sync,
- pulse_out => pulse_us_pp
- );
+ generic map (
+ g_pulse_period => g_pulse_us,
+ g_pulse_phase => g_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => sync,
+ pulse_out => pulse_us_pp
+ );
u_common_pulser_ms : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_ms,
- g_pulse_phase => g_pulse_ms - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us_pp,
- pulse_clr => sync,
- pulse_out => pulse_ms_p
- );
+ generic map (
+ g_pulse_period => g_pulse_ms,
+ g_pulse_phase => g_pulse_ms - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us_pp,
+ pulse_clr => sync,
+ pulse_out => pulse_ms_p
+ );
u_common_pulser_s : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_pulse_s,
- g_pulse_phase => g_pulse_s - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_ms_p,
- pulse_clr => sync,
- pulse_out => pulse_s_reg
- );
+ generic map (
+ g_pulse_period => g_pulse_s,
+ g_pulse_phase => g_pulse_s - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_ms_p,
+ pulse_clr => sync,
+ pulse_out => pulse_s_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index 6977e8583cdb92b1f6baa3023d63706955e227fe..6789fe6ef57a287c52378d8a2bac6614e488d2c8 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -36,10 +36,10 @@
-- [1] Based on the architecture of common_ram_crw_crw.vhd.
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw is
generic (
@@ -79,20 +79,20 @@ architecture str of common_ram_cr_cw is
begin
assert g_ram.latency >= 1
report "common_ram_cr_cw : only support read latency >= 1"
- severity FAILURE;
+ severity FAILURE;
-- memory access
u_cr_cw : entity tech_memory_lib.tech_memory_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map
- (
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map
+ (
wrclock => wr_clk,
wrclocken => wr_clken,
wren => wr_en,
@@ -102,21 +102,21 @@ begin
rdclocken => rd_clken,
rdaddress => rd_adr,
q => ram_rd_dat
- );
+ );
-- read output
u_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => rd_clk,
- clken => rd_clken,
- in_dat => ram_rd_dat,
- out_dat => rd_dat
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_dat,
+ out_dat => rd_dat
+ );
-- rd_val control
ram_rd_en(0) <= rd_en;
@@ -124,15 +124,15 @@ begin
rd_val <= ram_rd_val(0);
u_rd_val : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => rd_clk,
- clken => rd_clken,
- in_dat => ram_rd_en,
- out_dat => ram_rd_val
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_en,
+ out_dat => ram_rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index d314cdc9f5163c4e2a4bb0a28746479bedf119a1..407233e8d1fd8bb907f9cc0921adfe78dfd0a4d8 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -32,10 +32,10 @@
-- [1] Based on the structure of common_crw_crw_ratio.vhd.
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_cr_cw_ratio is
generic (
@@ -75,54 +75,53 @@ architecture str of common_ram_cr_cw_ratio is
-- Map sl to single bit slv for rd_val pipelining
signal ram_rd_en : std_logic_vector(0 downto 0);
signal ram_rd_val : std_logic_vector(0 downto 0);
-
begin
assert c_ram.latency >= 1
report "common_ram_cr_cw_ratio : only support read latency >= 1"
- severity FAILURE;
+ severity FAILURE;
assert g_ram_wr.latency = g_ram_rd.latency
report "common_ram_cr_cw_ratio : only support same read latency for both ports"
- severity FAILURE;
+ severity FAILURE;
-- memory access
u_ramk : entity tech_memory_lib.tech_memory_ram_crk_cw
- generic map (
- g_technology => g_technology,
- g_wr_adr_w => g_ram_wr.adr_w,
- g_rd_adr_w => g_ram_rd.adr_w,
- g_wr_dat_w => g_ram_wr.dat_w,
- g_rd_dat_w => g_ram_rd.dat_w,
- g_wr_nof_words => g_ram_wr.nof_dat,
- g_rd_nof_words => g_ram_rd.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- wrclock => wr_clk,
- rdclock => rd_clk,
- wrclocken => wr_clken,
- rdclocken => rd_clken,
- wren => wr_en,
- data => wr_dat,
- wraddress => wr_adr,
- rdaddress => rd_adr,
- q => ram_rd_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_adr_w => g_ram_wr.adr_w,
+ g_rd_adr_w => g_ram_rd.adr_w,
+ g_wr_dat_w => g_ram_wr.dat_w,
+ g_rd_dat_w => g_ram_rd.dat_w,
+ g_wr_nof_words => g_ram_wr.nof_dat,
+ g_rd_nof_words => g_ram_rd.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ wrclock => wr_clk,
+ rdclock => rd_clk,
+ wrclocken => wr_clken,
+ rdclocken => rd_clken,
+ wren => wr_en,
+ data => wr_dat,
+ wraddress => wr_adr,
+ rdaddress => rd_adr,
+ q => ram_rd_dat
+ );
-- read output
u_pipe : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram_rd.dat_w,
- g_out_dat_w => g_ram_rd.dat_w
- )
- port map (
- clk => rd_clk,
- clken => rd_clken,
- in_dat => ram_rd_dat,
- out_dat => rd_dat
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_rd.dat_w,
+ g_out_dat_w => g_ram_rd.dat_w
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_dat,
+ out_dat => rd_dat
+ );
-- rd_val control
ram_rd_en(0) <= rd_en;
@@ -130,15 +129,15 @@ begin
rd_val <= ram_rd_val(0);
u_rd_val : entity work.common_pipeline
- generic map (
- g_pipeline => c_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => rd_clk,
- clken => rd_clken,
- in_dat => ram_rd_en,
- out_dat => ram_rd_val
- );
+ generic map (
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => rd_clk,
+ clken => rd_clken,
+ in_dat => ram_rd_en,
+ out_dat => ram_rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index 9460631e1d382162793e67faeca1b60b9220582c..1edb8ba7b5d6d20d16c74fdddb06e07c8577090a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -27,9 +27,9 @@
-- for more context.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cr is
generic (
@@ -67,29 +67,29 @@ begin
-- Use port b for read only in ST clock domain
u_crw_cr : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => '0',
- wr_dat_a => mm_wr_dat,
- wr_dat_b => (others => '0'),
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => st_rd_en,
- rd_dat_a => mm_rd_dat,
- rd_dat_b => st_rd_dat,
- rd_val_a => mm_rd_val,
- rd_val_b => st_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => '0',
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => (others => '0'),
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => st_rd_en,
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => st_rd_dat,
+ rd_val_a => mm_rd_val,
+ rd_val_b => st_rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index b602cf707d949f511a55c5950f308644a978cce9..da46698c887d17794ac2a317c0efbba5c36f3c6e 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -27,10 +27,10 @@
-- for more context.
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_crw is
generic (
@@ -77,47 +77,47 @@ architecture str of common_ram_crw_crw is
begin
assert g_ram.latency >= 1
report "common_ram_crw_crw : only support read latency >= 1"
- severity FAILURE;
+ severity FAILURE;
-- memory access
gen_true_dual_port : if g_true_dual_port = true generate
u_ram : entity tech_memory_lib.tech_memory_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- clock_a => clk_a,
- clock_b => clk_b,
- enable_a => clken_a,
- enable_b => clken_b,
- wren_a => wr_en_a,
- wren_b => wr_en_b,
- data_a => wr_dat_a,
- data_b => wr_dat_b,
- address_a => adr_a,
- address_b => adr_b,
- q_a => ram_rd_dat_a,
- q_b => ram_rd_dat_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock_a => clk_a,
+ clock_b => clk_b,
+ enable_a => clken_a,
+ enable_b => clken_b,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
end generate;
gen_simple_dual_port : if g_true_dual_port = false generate
u_ram : entity tech_memory_lib.tech_memory_ram_cr_cw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map
- (
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map
+ (
wrclock => clk_a,
wrclocken => clken_a,
wren => wr_en_a,
@@ -127,35 +127,35 @@ begin
rdclocken => clken_b,
rdaddress => adr_b,
q => ram_rd_dat_b
- );
+ );
end generate;
-- read output
u_pipe_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_dat_a,
- out_dat => rd_dat_a
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
u_pipe_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_dat_b,
- out_dat => rd_dat_b
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
@@ -165,28 +165,28 @@ begin
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_en_a,
- out_dat => ram_rd_val_a
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
u_rd_val_b : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_en_b,
- out_dat => ram_rd_val_b
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index c85bd11f2ed1e35a5a55991bfe36c4449b1874aa..d99ace4855cbce9d0a8ecb6216bea36929315215 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -27,10 +27,10 @@
-- for more context.
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_crw_ratio is
generic (
@@ -79,66 +79,66 @@ architecture str of common_ram_crw_crw_ratio is
begin
assert c_ram.latency >= 1
report "common_ram_crw_crw_ratio : only support read latency >= 1"
- severity FAILURE;
+ severity FAILURE;
assert g_ram_a.latency = g_ram_b.latency
report "common_ram_crw_crw_ratio : only support same read latency for both ports"
- severity FAILURE;
+ severity FAILURE;
-- memory access
u_ramk : entity tech_memory_lib.tech_memory_ram_crwk_crw
- generic map (
- g_technology => g_technology,
- g_adr_a_w => g_ram_a.adr_w,
- g_adr_b_w => g_ram_b.adr_w,
- g_dat_a_w => g_ram_a.dat_w,
- g_dat_b_w => g_ram_b.dat_w,
- g_nof_words_a => g_ram_a.nof_dat,
- g_nof_words_b => g_ram_b.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- clock_a => clk_a,
- clock_b => clk_b,
- enable_a => clken_a,
- enable_b => clken_b,
- wren_a => wr_en_a,
- wren_b => wr_en_b,
- data_a => wr_dat_a,
- data_b => wr_dat_b,
- address_a => adr_a,
- address_b => adr_b,
- q_a => ram_rd_dat_a,
- q_b => ram_rd_dat_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_adr_a_w => g_ram_a.adr_w,
+ g_adr_b_w => g_ram_b.adr_w,
+ g_dat_a_w => g_ram_a.dat_w,
+ g_dat_b_w => g_ram_b.dat_w,
+ g_nof_words_a => g_ram_a.nof_dat,
+ g_nof_words_b => g_ram_b.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock_a => clk_a,
+ clock_b => clk_b,
+ enable_a => clken_a,
+ enable_b => clken_b,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
-- read output
u_pipe_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram_a.dat_w,
- g_out_dat_w => g_ram_a.dat_w
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_dat_a,
- out_dat => rd_dat_a
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_a.dat_w,
+ g_out_dat_w => g_ram_a.dat_w
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
u_pipe_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram_b.dat_w,
- g_out_dat_w => g_ram_b.dat_w
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_dat_b,
- out_dat => rd_dat_b
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram_b.dat_w,
+ g_out_dat_w => g_ram_b.dat_w
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
@@ -148,28 +148,28 @@ begin
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_a,
- clken => clken_a,
- in_dat => ram_rd_en_a,
- out_dat => ram_rd_val_a
- );
+ generic map (
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_a,
+ clken => clken_a,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
u_rd_val_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk_b,
- clken => clken_b,
- in_dat => ram_rd_en_b,
- out_dat => ram_rd_val_b
- );
+ generic map (
+ g_pipeline => c_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk_b,
+ clken => clken_b,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 5fe4fde7782fbdff680103be8f74b3894325b558..38f5b82a6f419b41298647c761ff52c864fa24a6 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -27,9 +27,9 @@
-- for more context.
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_crw_cw is
generic (
@@ -66,29 +66,29 @@ begin
-- Use port b for write only in ST clock domain
u_crw_cw : entity work.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst_a => mm_rst,
- rst_b => st_rst,
- clk_a => mm_clk,
- clk_b => st_clk,
- clken_a => mm_clken,
- clken_b => st_clken,
- wr_en_a => mm_wr_en,
- wr_en_b => st_wr_en,
- wr_dat_a => mm_wr_dat,
- wr_dat_b => st_wr_dat,
- adr_a => mm_adr,
- adr_b => st_adr,
- rd_en_a => mm_rd_en,
- rd_en_b => '0',
- rd_dat_a => mm_rd_dat,
- rd_dat_b => OPEN,
- rd_val_a => mm_rd_val,
- rd_val_b => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst_a => mm_rst,
+ rst_b => st_rst,
+ clk_a => mm_clk,
+ clk_b => st_clk,
+ clken_a => mm_clken,
+ clken_b => st_clken,
+ wr_en_a => mm_wr_en,
+ wr_en_b => st_wr_en,
+ wr_dat_a => mm_wr_dat,
+ wr_dat_b => st_wr_dat,
+ adr_a => mm_adr,
+ adr_b => st_adr,
+ rd_en_a => mm_rd_en,
+ rd_en_b => '0',
+ rd_dat_a => mm_rd_dat,
+ rd_dat_b => OPEN,
+ rd_val_a => mm_rd_val,
+ rd_val_b => open
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
index 099cbb831f41c08a2e55c313e2b7b28045b7eafd..6965672ba81400ca8d9bfd87322db5d4c9061572 100644
--- a/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_r_w is
generic (
@@ -51,27 +51,27 @@ begin
-- Use port b only for read
u_rw_rw : entity work.common_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file,
- g_true_dual_port => g_true_dual_port
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en_a => wr_en,
- wr_en_b => '0',
- wr_dat_a => wr_dat,
- --wr_dat_b => (OTHERS=>'0'),
- adr_a => wr_adr,
- adr_b => rd_adr,
- rd_en_a => '0',
- rd_en_b => rd_en,
- rd_dat_a => OPEN,
- rd_dat_b => rd_dat,
- rd_val_a => OPEN,
- rd_val_b => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file,
+ g_true_dual_port => g_true_dual_port
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en_a => wr_en,
+ wr_en_b => '0',
+ wr_dat_a => wr_dat,
+ --wr_dat_b => (OTHERS=>'0'),
+ adr_a => wr_adr,
+ adr_b => rd_adr,
+ rd_en_a => '0',
+ rd_en_b => rd_en,
+ rd_dat_a => OPEN,
+ rd_dat_b => rd_dat,
+ rd_val_a => OPEN,
+ rd_val_b => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 4a2740b82e22215a7acbc6da526b0df18f0b119a..0e46fe3148ce1c0a56fb1755bfde4c276224bfcf 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -34,10 +34,10 @@
-- [1] Based on the architecture of common_ram_crw_crw.vhd.
library IEEE, technology_lib, tech_memory_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_ram_rw_rw is
generic (
@@ -81,45 +81,45 @@ architecture str of common_ram_rw_rw is
begin
assert g_ram.latency >= 1
report "common_ram_rw_rw : only support read latency >= 1"
- severity FAILURE;
+ severity FAILURE;
-- memory access
gen_true_dual_port : if g_true_dual_port = true generate
u_ram : entity tech_memory_lib.tech_memory_ram_rw_rw
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map (
- clock => clk,
- enable => clken,
- wren_a => wr_en_a,
- wren_b => wr_en_b,
- data_a => wr_dat_a,
- data_b => wr_dat_b,
- address_a => adr_a,
- address_b => adr_b,
- q_a => ram_rd_dat_a,
- q_b => ram_rd_dat_b
- );
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map (
+ clock => clk,
+ enable => clken,
+ wren_a => wr_en_a,
+ wren_b => wr_en_b,
+ data_a => wr_dat_a,
+ data_b => wr_dat_b,
+ address_a => adr_a,
+ address_b => adr_b,
+ q_a => ram_rd_dat_a,
+ q_b => ram_rd_dat_b
+ );
end generate;
gen_simple_dual_port : if g_true_dual_port = false generate
u_ram : entity tech_memory_lib.tech_memory_ram_r_w
- generic map (
- g_technology => g_technology,
- g_adr_w => g_ram.adr_w,
- g_dat_w => g_ram.dat_w,
- g_nof_words => g_ram.nof_dat,
- g_rd_latency => c_rd_latency,
- g_init_file => g_init_file
- )
- port map
- (
+ generic map (
+ g_technology => g_technology,
+ g_adr_w => g_ram.adr_w,
+ g_dat_w => g_ram.dat_w,
+ g_nof_words => g_ram.nof_dat,
+ g_rd_latency => c_rd_latency,
+ g_init_file => g_init_file
+ )
+ port map
+ (
clock => clk,
enable => clken,
wren => wr_en_a,
@@ -127,35 +127,35 @@ begin
data => wr_dat_a,
rdaddress => adr_b,
q => ram_rd_dat_b
- );
+ );
end generate;
-- read output
u_pipe_a : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => ram_rd_dat_a,
- out_dat => rd_dat_a
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_dat_a,
+ out_dat => rd_dat_a
+ );
u_pipe_b : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => g_ram.dat_w,
- g_out_dat_w => g_ram.dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => ram_rd_dat_b,
- out_dat => rd_dat_b
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => g_ram.dat_w,
+ g_out_dat_w => g_ram.dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_dat_b,
+ out_dat => rd_dat_b
+ );
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
@@ -165,28 +165,28 @@ begin
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => ram_rd_en_a,
- out_dat => ram_rd_val_a
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_en_a,
+ out_dat => ram_rd_val_a
+ );
u_rd_val_b : entity work.common_pipeline
- generic map (
- g_pipeline => g_ram.latency,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => ram_rd_en_b,
- out_dat => ram_rd_val_b
- );
+ generic map (
+ g_pipeline => g_ram.latency,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => ram_rd_en_b,
+ out_dat => ram_rd_val_b
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index 84e56f935c2a68e0df66662259b81b45ba48ab43..0214d8999429e4d50b7679b89e980b161d29d92b 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Purpose: Get in_dat from in_clk to out_clk domain when in_new is asserted.
-- Remarks:
@@ -97,6 +97,7 @@ begin
reg_new(0) <= in_new;
gen_latency : if g_in_new_latency > 0 generate
+
p_reg_new : process(in_rst, in_clk)
begin
if in_rst = '1' then
@@ -166,15 +167,15 @@ begin
-- cross clock domain
------------------------------------------------------------------------------
u_cross_req : entity common_lib.common_spulse
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_pulse => cross_req,
- in_busy => cross_busy,
- out_rst => out_rst,
- out_clk => out_clk,
- out_pulse => out_en
- );
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_pulse => cross_req,
+ in_busy => cross_busy,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_pulse => out_en
+ );
------------------------------------------------------------------------------
-- out_clk domain
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w.vhd b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
index f58ac2c3b00cdd510b8e66cf4c204ea9fe6261fd..26c2fd798cd4b6cf0d9b976a0afd3ecb166caff9 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
-- Derived from LOFAR cfg_single_reg
@@ -113,17 +113,17 @@ begin
-- Pipeline to support read data latency > 1
u_pipe_rd : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline,
- g_in_dat_w => c_pipe_dat_w,
- g_out_dat_w => c_pipe_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => pipe_dat_in,
- out_dat => pipe_dat_out
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_pipe_dat_w,
+ g_out_dat_w => c_pipe_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => pipe_dat_in,
+ out_dat => pipe_dat_out
+ );
pipe_dat_in <= int_rd_val & int_rd_dat;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
index 63e5a8a45f785fbcf29bfdfeb5bd1d10de4eb889..959001d911b86abf5008192689c85eb6f90f2b1b 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
@@ -52,9 +52,9 @@
-- the data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity common_reg_r_w_dc is
generic (
@@ -108,27 +108,27 @@ begin
sla_out <= i_sla_out;
u_reg : entity work.common_reg_r_w
- generic map (
- g_reg => g_reg,
- g_init_reg => g_init_reg
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- control side
- wr_en => sla_in.wr,
- wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
- rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
- rd_val => i_sla_out.rdval,
- -- data side
- reg_wr_arr => vector_wr_arr,
- reg_rd_arr => vector_rd_arr,
- out_reg => out_vector,
- in_reg => in_vector
- );
+ generic map (
+ g_reg => g_reg,
+ g_init_reg => g_init_reg
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- control side
+ wr_en => sla_in.wr,
+ wr_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ wr_dat => sla_in.wrdata(g_reg.dat_w - 1 downto 0),
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(g_reg.adr_w - 1 downto 0),
+ rd_dat => i_sla_out.rddata(g_reg.dat_w - 1 downto 0),
+ rd_val => i_sla_out.rdval,
+ -- data side
+ reg_wr_arr => vector_wr_arr,
+ reg_rd_arr => vector_rd_arr,
+ out_reg => out_vector,
+ in_reg => in_vector
+ );
------------------------------------------------------------------------------
-- Transfer register value between mm_clk and st_clk domain.
@@ -156,57 +156,58 @@ begin
end generate; -- no_cross
gen_cross : if g_cross_clock_domain = true generate
+
gen_rdback : if g_readback = true generate
in_vector <= in_reg;
end generate;
gen_rd : if g_readback = false generate
u_in_vector : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => g_in_new_latency
+ generic map (
+ g_in_new_latency => g_in_new_latency
+ )
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => in_new,
+ in_dat => in_reg,
+ in_done => OPEN,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => in_vector,
+ out_new => open
+ );
+ end generate;
+
+ u_out_reg : entity work.common_reg_cross_domain
+ generic map(
+ g_out_dat_init => g_init_reg
)
port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => in_new,
- in_dat => in_reg,
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => out_vector,
in_done => OPEN,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => in_vector,
- out_new => open
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => out_reg,
+ out_new => out_new_i
);
- end generate;
-
- u_out_reg : entity work.common_reg_cross_domain
- generic map(
- g_out_dat_init => g_init_reg
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => out_vector,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => out_reg,
- out_new => out_new_i
- );
u_toggle : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- switch_high => wr_pulse,
- switch_low => out_new_i,
- out_level => toggle
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ switch_high => wr_pulse,
+ switch_low => out_new_i,
+ out_level => toggle
+ );
wr_pulse <= '0' when vector_or(reg_wr_arr_i) = '0' else '1';
out_new <= out_new_i and toggle;
@@ -214,27 +215,26 @@ begin
gen_access_evt : for I in 0 to g_reg.nof_dat - 1 generate
u_reg_wr_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_wr_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_wr_arr_i(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_wr_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_wr_arr_i(I)
+ );
u_reg_rd_arr : entity work.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => vector_rd_arr(I),
- in_busy => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => reg_rd_arr(I)
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => vector_rd_arr(I),
+ in_busy => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => reg_rd_arr(I)
+ );
end generate;
-
end generate; -- gen_cross
end str;
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index af7766e68e562ad2f6d8ce40eeb6e64249340bce..0d5bfba06c7e4afa4f820be0a23003dd9f09aea7 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose:
-- Deinterleave g_nof_in inputs based on g_deint_block_size and re-interleave
@@ -41,7 +41,7 @@ entity common_reinterleave is
g_inter_block_size : natural;
g_dat_w : natural;
g_align_out : boolean := false
- );
+ );
port (
clk : in std_logic;
rst : in std_logic;
@@ -72,14 +72,14 @@ architecture rtl of common_reinterleave is
constant c_wires_only : boolean := g_nof_in = 1 and g_nof_out = 1;
constant c_nof_deint : natural := sel_a_b( c_interleave_only, 0,
- sel_a_b( c_deinterleave_only, 1,
- sel_a_b( c_wires_only, 0,
- g_nof_in)));
+ sel_a_b( c_deinterleave_only, 1,
+ sel_a_b( c_wires_only, 0,
+ g_nof_in)));
constant c_nof_inter : natural := sel_a_b( c_interleave_only, 1,
- sel_a_b( c_deinterleave_only, 0,
- sel_a_b( c_wires_only, 0,
- g_nof_out)));
+ sel_a_b( c_deinterleave_only, 0,
+ sel_a_b( c_wires_only, 0,
+ g_nof_out)));
constant c_nof_deint_out : natural := g_nof_out;
constant c_nof_inter_in : natural := g_nof_in;
@@ -140,22 +140,22 @@ begin
deint_in_val <= in_val;
u_deinterleave : entity work.common_deinterleave
- generic map (
- g_nof_out => c_nof_deint_out,
- g_dat_w => g_dat_w,
- g_block_size => g_deint_block_size,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => deint_in_dat_arr(i),
- in_val => deint_in_val,
-
- out_dat => deint_out_concat_dat_arr(i),
- out_val => deint_out_concat_val_arr(i)
- );
+ generic map (
+ g_nof_out => c_nof_deint_out,
+ g_dat_w => g_dat_w,
+ g_block_size => g_deint_block_size,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => deint_in_dat_arr(i),
+ in_val => deint_in_val,
+
+ out_dat => deint_out_concat_dat_arr(i),
+ out_val => deint_out_concat_val_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
@@ -164,7 +164,9 @@ begin
-- Use the entity outputs if no interleavers are instantiated.
-----------------------------------------------------------------------------
gen_wire_deint_out: if c_deinterleave_only = false generate
+
gen_wires_deint : for i in 0 to c_nof_deint - 1 generate
+
gen_deint_out : for j in 0 to c_nof_deint_out - 1 generate
deint_out_dat_2arr(i)(j) <= deint_out_concat_dat_arr(i)(j * g_dat_w + g_dat_w - 1 downto j * g_dat_w);
deint_out_val_2arr(i)(j) <= deint_out_concat_val_arr(i)(j);
@@ -181,7 +183,9 @@ begin
-- Deinterleavers -> Interleavers interconnections
-----------------------------------------------------------------------------
gen_interconnect: if c_deinterleave_only = false and c_interleave_only = false generate
+
gen_wires_deint : for i in 0 to c_nof_deint - 1 generate
+
gen_deint_out : for j in 0 to c_nof_deint_out - 1 generate
inter_in_dat_2arr(j)(i) <= deint_out_dat_2arr(i)(j);
inter_in_val_2arr(j)(i) <= deint_out_val_2arr(i)(j);
@@ -195,7 +199,9 @@ begin
-- Use the entity inputs if no deinterleavers are instantiated.
-----------------------------------------------------------------------------
gen_wire_inter_arr: if c_interleave_only = false generate
+
gen_nof_inter : for i in 0 to c_nof_inter - 1 generate
+
gen_inter_in : for j in 0 to c_nof_inter_in - 1 generate
inter_in_concat_dat_arr(i)(j * g_dat_w + g_dat_w - 1 downto j * g_dat_w) <= inter_in_dat_2arr(i)(j);
inter_in_concat_val_arr(i)(j) <= inter_in_val_2arr(i)(j);
@@ -216,24 +222,23 @@ begin
-----------------------------------------------------------------------------
gen_inter: for i in 0 to c_nof_inter - 1 generate
u_interleave : entity work.common_interleave
- generic map (
- g_nof_in => c_nof_inter_in,
- g_dat_w => g_dat_w,
- g_block_size => g_inter_block_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => inter_in_concat_dat_arr(i),
- in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
-
- out_dat => inter_out_dat_arr(i),
- out_val => inter_out_val(i)
- );
+ generic map (
+ g_nof_in => c_nof_inter_in,
+ g_dat_w => g_dat_w,
+ g_block_size => g_inter_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => inter_in_concat_dat_arr(i),
+ in_val => inter_in_concat_val_arr(i)(0), -- All input streams are valid at the same time.
+
+ out_dat => inter_out_dat_arr(i),
+ out_val => inter_out_val(i)
+ );
out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w) <= inter_out_dat_arr(i);
out_val(i) <= inter_out_val(i);
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index a3bcf0c3c6197039c53a3c0b602214b64311ac37..9dc6ca4f28bf551a0f3cdfed37784bf6e96006ae 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Reorder symbols from input data stream
--
@@ -152,17 +152,17 @@ begin
-- optional input pipelining
u_pipe_input : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => reorder_2arr(-1)(J),
- out_dat => reorder_2arr(0)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => reorder_2arr(-1)(J),
+ out_dat => reorder_2arr(0)(J)
+ );
end generate;
-- in_select
@@ -172,16 +172,16 @@ begin
-- align in_select to the optional input pipelining
u_pipe_input : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(0),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(-1)(K),
- out_dat => select_2arr(0)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(0),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(-1)(K),
+ out_dat => select_2arr(0)(K)
+ );
end generate;
------------------------------------------------------------------------------
@@ -190,6 +190,7 @@ begin
-- stage I=1:c_N
gen_stage : for I in 1 to c_N generate
+
gen_row : for J in 0 to c_N generate
-- generate the 2-input reorder cells for each stage
gen_reorder2 : if func_common_reorder2_is_there(I, J) generate
@@ -198,32 +199,32 @@ begin
-- optional pipelining per reorder stage
u_pipe_stage : entity work.common_pipeline
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_in_dat_w => g_symbol_w,
- g_out_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_reorder_2arr(I)(J),
- out_dat => reorder_2arr(I)(J)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_in_dat_w => g_symbol_w,
+ g_out_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_reorder_2arr(I)(J),
+ out_dat => reorder_2arr(I)(J)
+ );
end generate;
-- align in_select to the optional pipelining per reorder stage
gen_select : for K in 0 to g_nof_select - 1 generate
u_pipe_stage : entity work.common_pipeline_natural
- generic map (
- g_pipeline => c_pipeline_arr(I),
- g_dat_w => g_select_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => select_2arr(I - 1)(K),
- out_dat => select_2arr(I)(K)
- );
+ generic map (
+ g_pipeline => c_pipeline_arr(I),
+ g_dat_w => g_select_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => select_2arr(I - 1)(K),
+ out_dat => select_2arr(I)(K)
+ );
end generate;
end generate;
@@ -240,46 +241,46 @@ begin
------------------------------------------------------------------------------
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => out_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => out_sync
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e60f590d7815b90b0e1557ba8c46ce476d4bf25a..d463c4ea9ac0aff14177aeed417e2d2a331a93cd 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Requantize the input data to the output data width by removing
-- LSbits and/or MSbits
@@ -55,14 +55,14 @@ entity common_requantize is
generic (
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -94,41 +94,41 @@ begin
-- Remove LSBits using ROUND or TRUNCATE
u_remove_lsb : entity common_lib.common_round
- generic map (
- g_representation => g_representation,
- g_round => g_lsb_round,
- g_round_clip => g_lsb_round_clip,
- g_round_even => g_lsb_round_even,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_lsb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_rem_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat(g_in_dat_w - 1 downto 0),
- out_dat => rem_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_round => g_lsb_round,
+ g_round_clip => g_lsb_round_clip,
+ g_round_even => g_lsb_round_even,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_lsb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_rem_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat(g_in_dat_w - 1 downto 0),
+ out_dat => rem_dat
+ );
-- Remove MSBits using CLIP or WRAP
u_remove_msb : entity common_lib.common_resize
- generic map (
- g_representation => g_representation,
- g_pipeline_input => 0,
- g_pipeline_output => g_pipeline_remove_msb,
- g_clip => g_msb_clip,
- g_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_rem_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => rem_dat,
- out_dat => res_dat,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline_input => 0,
+ g_pipeline_output => g_pipeline_remove_msb,
+ g_clip => g_msb_clip,
+ g_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_rem_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => rem_dat,
+ out_dat => res_dat,
+ out_ovr => out_ovr
+ );
-- Output gain
gain_dat(g_out_dat_w + c_gain_w - 1 downto c_gain_w) <= res_dat;
diff --git a/libraries/base/common/src/vhdl/common_request.vhd b/libraries/base/common/src/vhdl/common_request.vhd
index 47506edcb2d00aede4aa954346662fb2fe040c3f..bfd75dc50a7bbb22ea77a4c3c31430c6392cf5a6 100644
--- a/libraries/base/common/src/vhdl/common_request.vhd
+++ b/libraries/base/common/src/vhdl/common_request.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_request is
port (
@@ -79,14 +79,14 @@ begin
in_req_evt <= in_req_reg and not in_req_prev;
u_protocol_act : entity work.common_switch
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- switch_high => in_req_evt,
- switch_low => out_req,
- out_level => req_pending
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ switch_high => in_req_evt,
+ switch_low => out_req,
+ out_level => req_pending
+ );
out_req <= req_pending and sync_reg;
nxt_out_req_evt <= out_req and not out_req_prev;
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 04ae5e8e6d7e24e1b028e370d9eb5384af5e3686..8d924e00e36d30b42c09385618bfec368a1d019e 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_resize is
generic (
g_representation : string := "SIGNED"; -- SIGNED or UNSIGNED resizing
g_clip : boolean := false; -- when TRUE clip input if it is outside the output range, else wrap
g_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_pipeline_input : natural := 0; -- >= 0
g_pipeline_output : natural := 1; -- >= 0
g_in_dat_w : integer := 36;
@@ -65,18 +65,18 @@ architecture rtl of common_resize is
signal out_vec : std_logic_vector(g_out_dat_w downto 0);
begin
u_input_pipe : entity work.common_pipeline -- pipeline input
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
no_clip : if c_clip = false generate
-- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
@@ -98,6 +98,7 @@ begin
end generate;
gen_clip : if c_clip = true generate
+
gen_s_clip : if g_representation = "SIGNED" generate
clip <= '1' when signed(reg_dat) > c_smax or signed(reg_dat) < c_smin else '0';
sign <= reg_dat(reg_dat'high);
@@ -115,18 +116,18 @@ begin
res_vec <= res_ovr & res_dat;
u_output_pipe : entity work.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w + 1,
- g_out_dat_w => g_out_dat_w + 1
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_vec,
- out_dat => out_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w + 1,
+ g_out_dat_w => g_out_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_vec,
+ out_dat => out_vec
+ );
out_ovr <= out_vec(g_out_dat_w);
out_dat <= out_vec(g_out_dat_w - 1 downto 0);
diff --git a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
index 783c41fe81b80a148ad6234c1c93734d06a68e4a..003030655c0828501f24225a05dd700f83be72c8 100644
--- a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
+++ b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
@@ -19,9 +19,9 @@
--------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -72,8 +72,8 @@ end common_reverse_n_data;
architecture str of common_reverse_n_data is
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
- g_reverse_len - 1 +
- g_pipeline_mux_in + g_pipeline_mux_out;
+ g_reverse_len - 1 +
+ g_pipeline_mux_in + g_pipeline_mux_out;
constant c_sel_w : natural := ceil_log2(g_reverse_len);
@@ -119,23 +119,23 @@ begin
end process;
u_common_demultiplexer : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_data_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_reverse_len,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_data_vec,
+ out_val => demux_val_vec
+ );
-- All g_reverse_len parts in demux_data_vec carry the same data, the
-- demux_val_vec determines for which demux stream it is. Use demux_data
@@ -185,62 +185,62 @@ begin
--
gen_reverse : for I in 0 to g_reverse_len - 1 generate
u_reverse_data : entity work.common_pipeline
+ generic map (
+ g_pipeline => 2 * I,
+ g_in_dat_w => g_data_w,
+ g_out_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
+ out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ );
+
+ u_reverse_val : entity work.common_pipeline_sl
+ generic map (
+ g_pipeline => 2 * I
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => demux_val_vec(g_reverse_len - 1 - I),
+ out_dat => reverse_val_vec(I)
+ );
+ end generate;
+
+ reverse_val <= vector_or(reverse_val_vec);
+
+ -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
+ u_pipe_sel : entity work.common_pipeline
generic map (
- g_pipeline => 2 * I,
- g_in_dat_w => g_data_w,
- g_out_dat_w => g_data_w
+ g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
)
port map (
rst => rst,
clk => clk,
- in_dat => demux_data_vec((g_reverse_len - 1 - I + 1) * g_data_w - 1 downto (g_reverse_len - 1 - I) * g_data_w),
- out_dat => reverse_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w)
+ in_dat => in_sel,
+ out_dat => reverse_sel
);
- u_reverse_val : entity work.common_pipeline_sl
+ u_common_multiplexer : entity work.common_multiplexer
generic map (
- g_pipeline => 2 * I
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_reverse_len,
+ g_dat_w => g_data_w
)
port map (
- rst => rst,
- clk => clk,
- in_dat => demux_val_vec(g_reverse_len - 1 - I),
- out_dat => reverse_val_vec(I)
- );
- end generate;
-
- reverse_val <= vector_or(reverse_val_vec);
+ rst => rst,
+ clk => clk,
- -- pipeline in_sel to align reverse_sel to reverse_data_vec and reverse_val_vec
- u_pipe_sel : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline_demux_in + g_pipeline_demux_out + g_reverse_len - 1,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => reverse_sel
- );
+ in_sel => reverse_sel,
+ in_dat => reverse_data_vec,
+ in_val => reverse_val,
- u_common_multiplexer : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_reverse_len,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => reverse_sel,
- in_dat => reverse_data_vec,
- in_val => reverse_val,
-
- out_dat => out_data,
- out_val => out_val -- = in_val delayed by c_pipeline_total
- );
+ out_dat => out_data,
+ out_val => out_val -- = in_val delayed by c_pipeline_total
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rl_decrease.vhd b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
index 41fa78b5592b069f56ad68357d26dd59ed469649..2f6f164af237037be0813bf472584e1930ee72ab 100644
--- a/libraries/base/common/src/vhdl/common_rl_decrease.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
@@ -23,7 +23,7 @@
-- >>> Ported from UniBoard dp_latency_adapter for fixed RL 0 --> 1
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Adapt from ready latency 1 to 0 to make a look ahead FIFO
-- Description: -
diff --git a/libraries/base/common/src/vhdl/common_rl_increase.vhd b/libraries/base/common/src/vhdl/common_rl_increase.vhd
index 43f002b9f52d79aa5edfe7446f93a04c2d66ad3c..4dde10a6a6fb489d9629813d529a04b637ececd0 100644
--- a/libraries/base/common/src/vhdl/common_rl_increase.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_increase.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- >>> Ported from UniBoard dp_latency_increase for fixed RL 0 --> 1
--
@@ -71,6 +71,7 @@ begin
end generate;
gen_adapt : if g_adapt = true generate
+
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -91,5 +92,4 @@ begin
nxt_hold_dat <= snk_in_dat when hold_val = '1' else hold_dat;
src_out_dat <= snk_in_dat when g_hold_dat_en = false else nxt_hold_dat;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_rl_register.vhd b/libraries/base/common/src/vhdl/common_rl_register.vhd
index 1a4f287ddc18dc343c2966e1a6b7f638901cf2cb..319b1e77c3fddcb093aaf84b09dedeeb654bd6ca 100644
--- a/libraries/base/common/src/vhdl/common_rl_register.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_register.vhd
@@ -23,7 +23,7 @@
-- >>> Ported from UniBoard dp_pipeline_ready for fixed RL 1 --> 0 --> 1
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Register both the data and the ready by going from RL=1 to 0 to 1.
-- Description: -
@@ -63,39 +63,39 @@ architecture str of common_rl_register is
signal reg_val : std_logic;
begin
u_rl0 : entity common_lib.common_rl_decrease
- generic map (
- g_adapt => g_adapt,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- snk_out_ready => snk_out_ready,
- snk_in_dat => snk_in_dat,
- snk_in_val => snk_in_val,
- -- ST source: RL = 0
- src_in_ready => reg_ready,
- src_out_dat => reg_dat,
- src_out_val => reg_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ snk_out_ready => snk_out_ready,
+ snk_in_dat => snk_in_dat,
+ snk_in_val => snk_in_val,
+ -- ST source: RL = 0
+ src_in_ready => reg_ready,
+ src_out_dat => reg_dat,
+ src_out_val => reg_val
+ );
u_rl1 : entity common_lib.common_rl_increase
- generic map (
- g_adapt => g_adapt,
- g_hold_dat_en => g_hold_dat_en,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- Sink
- snk_out_ready => reg_ready, -- sink RL = 0
- snk_in_dat => reg_dat,
- snk_in_val => reg_val,
- -- Source
- src_in_ready => src_in_ready, -- source RL = 1
- src_out_dat => src_out_dat,
- src_out_val => src_out_val
- );
+ generic map (
+ g_adapt => g_adapt,
+ g_hold_dat_en => g_hold_dat_en,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Sink
+ snk_out_ready => reg_ready, -- sink RL = 0
+ snk_in_dat => reg_dat,
+ snk_in_val => reg_val,
+ -- Source
+ src_in_ready => src_in_ready, -- source RL = 1
+ src_out_dat => src_out_dat,
+ src_out_val => src_out_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_rom.vhd b/libraries/base/common/src/vhdl/common_rom.vhd
index 0637ea290b9316b419f9c35700dd1fab8ec7cac6..12b37088cf8d8ab9d7e56d46482b90cd718183c9 100644
--- a/libraries/base/common/src/vhdl/common_rom.vhd
+++ b/libraries/base/common/src/vhdl/common_rom.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_rom is
generic (
@@ -46,21 +46,21 @@ begin
-- Only use the read port
u_r_w : entity work.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => g_ram,
- g_init_file => g_init_file
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- wr_en => '0',
- --wr_adr => (OTHERS=>'0'),
- --wr_dat => (OTHERS=>'0'),
- rd_en => rd_en,
- rd_adr => rd_adr,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => g_ram,
+ g_init_file => g_init_file
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ wr_en => '0',
+ --wr_adr => (OTHERS=>'0'),
+ --wr_dat => (OTHERS=>'0'),
+ rd_en => rd_en,
+ rd_adr => rd_adr,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 6f7aae19d2d8a1ef6b16dcab4e354766cf3e076c..5f1367dbf3484b64d92b3ed0313724072b502702 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use work.common_pkg.all;
entity common_round is
--
@@ -62,18 +62,18 @@ architecture rtl of common_round is
signal res_dat : std_logic_vector(out_dat'range);
begin
u_input_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_input,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => in_dat,
- out_dat => reg_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_input,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => in_dat,
+ out_dat => reg_dat
+ );
-- Increase to out_dat width
no_s : if c_remove_w <= 0 and g_representation = "SIGNED" generate
@@ -100,16 +100,16 @@ begin
end generate;
u_output_pipe : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline_output,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => res_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline_output,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => res_dat,
+ out_dat => out_dat
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
index 9c5981c47a625208abe8bff59d3d2a1b8e7c6185..d8333020e69faba19d32887d68ae834a6e3e6ace 100644
--- a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
+++ b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Select M symbols from an input data stream with N symbols
-- Description:
@@ -108,32 +108,32 @@ begin
in_select_arr(I) <= in_select_reg((I + 1) * c_sel_w - 1 downto I * c_sel_w);
u_sel : entity work.common_select_symbol
- generic map (
- g_pipeline_in => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out,
- g_nof_symbols => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_reg,
- in_val => in_val_reg,
- in_sop => in_sop_reg,
- in_eop => in_eop_reg,
- in_sync => in_sync_reg,
-
- in_sel => in_select_arr(I),
- out_sel => OPEN,
-
- out_symbol => out_data_arr(I),
- out_val => out_val_arr(I), -- pipelined in_val
- out_sop => out_sop_arr(I), -- pipelined in_sop
- out_eop => out_eop_arr(I), -- pipelined in_eop
- out_sync => out_sync_arr(I) -- pipelined in_sync
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out,
+ g_nof_symbols => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_reg,
+ in_val => in_val_reg,
+ in_sop => in_sop_reg,
+ in_eop => in_eop_reg,
+ in_sync => in_sync_reg,
+
+ in_sel => in_select_arr(I),
+ out_sel => OPEN,
+
+ out_symbol => out_data_arr(I),
+ out_val => out_val_arr(I), -- pipelined in_val
+ out_sop => out_sop_arr(I), -- pipelined in_sop
+ out_eop => out_eop_arr(I), -- pipelined in_eop
+ out_sync => out_sync_arr(I) -- pipelined in_sync
+ );
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_data_arr(I);
end generate;
diff --git a/libraries/base/common/src/vhdl/common_select_symbol.vhd b/libraries/base/common/src/vhdl/common_select_symbol.vhd
index 117fb8c133e1a1f783e09ff7e4e48e2764fc0146..6075f6b99046d01b7e94bf464e62df2a2dc89d89 100644
--- a/libraries/base/common/src/vhdl/common_select_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_select_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_components_pkg.all;
-- Purpose: Select symbol from input data stream
-- Description:
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 382a87a482c9a6c1d4976ea96cbbb0fa2357cdf5..43703b33e1736a530e603bb0faef72bfb6e0776d 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -50,11 +50,11 @@
-- r0..r2 = register stages.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity common_shiftram is
generic (
@@ -85,8 +85,9 @@ architecture rtl of common_shiftram is
constant c_ram_data_w : natural := g_data_w;
constant c_ram_nof_dat : natural := g_nof_words;
constant c_ram_init_sl : std_logic := '0';
- constant c_ram : t_c_mem := (c_ram_rl, c_ram_addr_w, c_ram_data_w,
- c_ram_nof_dat, c_ram_init_sl);
+ constant c_ram : t_c_mem := (
+ c_ram_rl, c_ram_addr_w, c_ram_data_w,
+ c_ram_nof_dat, c_ram_init_sl);
signal ram_data_out : std_logic_vector(g_data_w - 1 downto 0);
signal ram_data_out_val : std_logic;
@@ -100,11 +101,12 @@ architecture rtl of common_shiftram is
ram_wr_shift_incr : boolean;
end record;
- constant c_reg_0_defaults : t_reg_0 := ( (others => '0'),
- (others => '0'),
- '0',
- (others => '0'),
- false);
+ constant c_reg_0_defaults : t_reg_0 := (
+ (others => '0'),
+ (others => '0'),
+ '0',
+ (others => '0'),
+ false);
signal r0, nxt_r0 : t_reg_0 := c_reg_0_defaults;
@@ -115,33 +117,34 @@ architecture rtl of common_shiftram is
ram_rd_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
end record;
- constant c_reg_1_defaults : t_reg_1 := ( (others => '0'),
- '0',
- (others => '0'));
+ constant c_reg_1_defaults : t_reg_1 := (
+ (others => '0'),
+ '0',
+ (others => '0'));
- signal r1, nxt_r1 : t_reg_1 := c_reg_1_defaults;
+ signal r1, nxt_r1 : t_reg_1 := c_reg_1_defaults;
- -- Register stage 2
- type t_reg_2 is record
- data_out_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
- end record;
+ -- Register stage 2
+ type t_reg_2 is record
+ data_out_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
+ end record;
- constant c_reg_2_defaults : t_reg_2 := (others => (others => '0'));
+ constant c_reg_2_defaults : t_reg_2 := (others => (others => '0'));
- signal r2, nxt_r2 : t_reg_2 := c_reg_2_defaults;
+ signal r2, nxt_r2 : t_reg_2 := c_reg_2_defaults;
- -- Register stage 3 (optional)
- type t_reg_3 is record
- data_out_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
- data_out : std_logic_vector(g_data_w - 1 downto 0);
- data_out_val : std_logic;
- end record;
+ -- Register stage 3 (optional)
+ type t_reg_3 is record
+ data_out_shift : std_logic_vector(c_ram_addr_w - 1 downto 0);
+ data_out : std_logic_vector(g_data_w - 1 downto 0);
+ data_out_val : std_logic;
+ end record;
- constant c_reg_3_defaults : t_reg_3 := ( (others => '0'),
- (others => '0'),
- '0');
+ constant c_reg_3_defaults : t_reg_3 := ( (others => '0'),
+ (others => '0'),
+ '0');
- signal r3, nxt_r3 : t_reg_3 := c_reg_3_defaults;
+ signal r3, nxt_r3 : t_reg_3 := c_reg_3_defaults;
begin
-----------------------------------------------------------------------------
-- Register stage 0
@@ -159,7 +162,7 @@ begin
if data_in_val = '1' then
-- Limit max shift to g_nof_words-2
- v_data_in_shift := data_in_shift;
+ v_data_in_shift := data_in_shift;
if v_data_in_shift = TO_UVEC(g_nof_words - 1, c_ram_addr_w) then
v_data_in_shift := TO_UVEC(g_nof_words - 2, c_ram_addr_w);
@@ -250,30 +253,30 @@ begin
nxt_r2 <= v;
end process;
--- data_out_shift <= r2.data_out_shift;
+ -- data_out_shift <= r2.data_out_shift;
-----------------------------------------------------------------------------
-- RAM
-----------------------------------------------------------------------------
u_common_ram_r_w: entity common_lib.common_ram_r_w
- generic map (
- g_technology => g_technology,
- g_ram => c_ram,
- g_init_file => "UNUSED",
- g_true_dual_port => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => r0.ram_wr_en,
- wr_adr => r0.ram_wr_addr,
- wr_dat => r0.ram_wr_data,
- rd_en => r1.ram_rd_en,
- rd_adr => r1.ram_rd_addr,
- rd_dat => ram_data_out,
- rd_val => ram_data_out_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_ram,
+ g_init_file => "UNUSED",
+ g_true_dual_port => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => r0.ram_wr_en,
+ wr_adr => r0.ram_wr_addr,
+ wr_dat => r0.ram_wr_data,
+ rd_en => r1.ram_rd_en,
+ rd_adr => r1.ram_rd_addr,
+ rd_dat => ram_data_out,
+ rd_val => ram_data_out_val
+ );
gen_outputs: if g_output_invalid_during_shift_incr = false generate
data_out_shift <= r2.data_out_shift;
@@ -313,5 +316,4 @@ begin
data_out <= r3.data_out;
data_out_val <= r3.data_out_val;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index e18a57174abfb7bb2165f3de14ee4fab9b2e8780..ae7cb3e85ecad1ad2302104f85e35932987407a0 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Shift register when in_val is active with optional flush at in_eop.
-- Description:
@@ -134,16 +134,16 @@ begin
-- Shift control
u_flush : entity work.common_switch
- generic map (
- g_rst_level => '0'
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_eop,
- switch_low => eop_arr(0),
- out_level => flush
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_eop,
+ switch_low => eop_arr(0),
+ out_level => flush
+ );
shift_en <= in_val or flush when g_flush_en = true else in_val or out_req;
@@ -186,67 +186,67 @@ begin
out_eop <= i_out_eop_vec(0);
u_out_data_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat * g_dat_w,
- g_out_dat_w => g_nof_dat * g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => data_vec,
- out_dat => i_out_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat * g_dat_w,
+ g_out_dat_w => g_nof_dat * g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => data_vec,
+ out_dat => i_out_data_vec
+ );
u_out_val_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => val_vec,
- out_dat => i_out_val_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => val_vec,
+ out_dat => i_out_val_vec
+ );
u_out_sop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sop_vec,
- out_dat => i_out_sop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sop_vec,
+ out_dat => i_out_sop_vec
+ );
u_out_eop_vec : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_dat,
- g_out_dat_w => g_nof_dat
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => eop_vec,
- out_dat => i_out_eop_vec
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_dat,
+ g_out_dat_w => g_nof_dat
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => eop_vec,
+ out_dat => i_out_eop_vec
+ );
u_out_cnt : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => c_cnt_w,
- g_out_dat_w => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_cnt,
- out_dat => out_cnt
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => c_cnt_w,
+ g_out_dat_w => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_cnt,
+ out_dat => out_cnt
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
index e5a3137af0c6d1c0e6042f3dca9df27e67ddeefd..150662c2c13bd3bdad84018df5c9ddb49e0190ce 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Per symbol shift register of the input data stream
-- Description:
@@ -69,29 +69,28 @@ begin
-- pipeline per symbol
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_shiftline_arr(I),
- g_dat_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_shiftline_arr(I),
+ g_dat_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => in_dat_arr(I),
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
+ in_dat => in_dat_arr(I),
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
- out_dat => out_dat_arr(I),
- out_val => out_val_arr(I),
- out_sop => out_sop_arr(I),
- out_eop => out_eop_arr(I)
- );
+ out_dat => out_dat_arr(I),
+ out_val => out_val_arr(I),
+ out_sop => out_sop_arr(I),
+ out_eop => out_eop_arr(I)
+ );
-- map arr to output vector
out_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w) <= out_dat_arr(I);
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index d24c3034ffcd6324b9ec560e263f210e7531e273..58f856881584e35ea6470f2bc0f772451a70b861 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -31,8 +31,8 @@
-- the out_clk rate.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_spulse is
generic (
@@ -61,14 +61,14 @@ architecture rtl of common_spulse is
signal nxt_out_pulse : std_logic;
begin
capture_in_pulse : entity work.common_switch
- port map (
- clk => in_clk,
- clken => in_clken,
- rst => in_rst,
- switch_high => in_pulse,
- switch_low => pulse_ack,
- out_level => in_level
- );
+ port map (
+ clk => in_clk,
+ clken => in_clken,
+ rst => in_rst,
+ switch_high => in_pulse,
+ switch_low => pulse_ack,
+ out_level => in_level
+ );
in_busy <= in_level or pulse_ack;
diff --git a/libraries/base/common/src/vhdl/common_stable_delayed.vhd b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
index e9d5ae319709f9be85beb7a352cb700302200cbf..332219f807faf822bf5ec0158e7a635abb0720e2 100644
--- a/libraries/base/common/src/vhdl/common_stable_delayed.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- Output active r_in if it is still active after some delay.
@@ -80,14 +80,14 @@ begin
end process;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => g_delayed_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => g_delayed_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_stable_monitor.vhd b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
index fe41dae0f857445322c145c13d8219879b3819a4..3a7f466a22382a13b7954883fcea402b964c72f7 100644
--- a/libraries/base/common/src/vhdl/common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor whether r_in did not go low since the previous ack
-- Description:
@@ -60,29 +60,29 @@ begin
nxt_r_stable <= r_in and not r_evt_occured;
u_r_evt : entity work.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => r_in,
- out_evt => r_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => r_in,
+ out_evt => r_evt
+ );
u_r_evt_occured : entity work.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => r_evt,
- switch_low => r_stable_ack,
- out_level => r_evt_occured
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => r_evt,
+ switch_low => r_stable_ack,
+ out_level => r_evt_occured
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index e309a4d10a00d1432c3c166ae1b0bc0174f251c9..1665d16e7ba831bdc7f7eb143a8c176a6f25a0b8 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -29,11 +29,11 @@
-- . None
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.TEXTIO.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.TEXTIO.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_pkg.all;
package common_str_pkg is
type t_str_4_arr is array (integer range <>) of string(1 to 4);
@@ -66,13 +66,13 @@ end common_str_pkg;
package body common_str_pkg is
function nof_digits(number: natural) return natural is
- -- Returns number of digits in a natural number. Only used in string processing, so defined here.
- -- log10(0) is not allowed so:
- -- . nof_digits(0) = 1
- -- We're adding 1 so:
- -- . nof_digits(1) = 1
- -- . nof_digits(9) = 1
- -- . nof_digits(10) = 2
+ -- Returns number of digits in a natural number. Only used in string processing, so defined here.
+ -- log10(0) is not allowed so:
+ -- . nof_digits(0) = 1
+ -- We're adding 1 so:
+ -- . nof_digits(1) = 1
+ -- . nof_digits(9) = 1
+ -- . nof_digits(10) = 2
begin
if number > 0 then
return floor_log10(number) + 1;
@@ -83,14 +83,14 @@ package body common_str_pkg is
end;
function nof_digits_int(number: integer) return natural is
- -- Returns number of digits in a natural number. Only used in string processing, so defined here.
- -- log10(0) is not allowed so:
- -- . nof_digits(0) = 1
- -- We're adding 1 so:
- -- . nof_digits(1) = 1
- -- . nof_digits(9) = 1
- -- . nof_digits(10) = 2
- -- . nof_digits(1) = 2
+ -- Returns number of digits in a natural number. Only used in string processing, so defined here.
+ -- log10(0) is not allowed so:
+ -- . nof_digits(0) = 1
+ -- We're adding 1 so:
+ -- . nof_digits(1) = 1
+ -- . nof_digits(9) = 1
+ -- . nof_digits(10) = 2
+ -- . nof_digits(1) = 2
begin
if number = 0 then
return 1;
@@ -116,13 +116,13 @@ package body common_str_pkg is
function time_to_str(in_time : time) return string is
constant c_max_len_time : natural := 20;
- variable v_line : LINE;
- variable v_str : string(1 to c_max_len_time) := (others => ' ');
+ variable v_line : LINE;
+ variable v_str : string(1 to c_max_len_time) := (others => ' ');
begin
write(v_line, in_time);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
function str_to_time(in_str : string) return time is
@@ -134,15 +134,15 @@ package body common_str_pkg is
variable v_line : LINE;
variable v_str : string(1 to slv'length) := (others => ' ');
begin
- write(v_line, slv);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ write(v_line, slv);
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
function sl_to_str(sl : std_logic) return string is
begin
- return slv_to_str(slv(sl));
+ return slv_to_str(slv(sl));
end;
function str_to_hex(str : string) return string is
@@ -182,14 +182,14 @@ package body common_str_pkg is
end;
function hex_to_slv(str: string) return std_logic_vector is
- constant c_length : natural := str'length;
- variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
- variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
+ constant c_length : natural := str'length;
+ variable v_str : string(1 to str'length) := str; -- Keep local copy of str to prevent range mismatch
+ variable v_result : std_logic_vector(c_length * 4 - 1 downto 0);
begin
- for i in c_length downto 1 loop
- v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
- end loop;
- return v_result;
+ for i in c_length downto 1 loop
+ v_result(3 + (c_length - i) * 4 downto (c_length - i) * 4) := hex_nibble_to_slv(v_str(i));
+ end loop;
+ return v_result;
end;
function hex_nibble_to_slv(c: character) return std_logic_vector is
@@ -223,9 +223,9 @@ package body common_str_pkg is
when 'z' => v_result := "ZZZZ";
when 'Z' => v_result := "ZZZZ";
- when others => v_result := "0000";
- end case;
- return v_result;
+ when others => v_result := "0000";
+ end case;
+ return v_result;
end hex_nibble_to_slv;
function int_to_str(int: integer) return string is
@@ -261,66 +261,66 @@ package body common_str_pkg is
end;
procedure print_str(str: string) is
- variable v_line: LINE;
- begin
- write(v_line, str);
- writeline(output, v_line);
- deallocate(v_line);
- end;
-
- procedure print_str(str: string; enable: boolean) is
- variable v_line: LINE;
- begin
- if enable then
- print_str(str);
- end if;
- end;
-
- function str_to_ascii_integer_arr(s: string) return t_integer_arr is
- variable r: t_integer_arr(0 to s'right - 1);
- begin
- for i in s'range loop
- r(i - 1) := character'pos(s(i));
- end loop;
- return r;
- end;
-
- function str_to_ascii_slv_8_arr(s: string) return t_slv_8_arr is
- variable r: t_slv_8_arr(0 to s'right - 1);
- begin
- for i in s'range loop
- r(i - 1) := TO_UVEC(str_to_ascii_integer_arr(s)(i - 1), 8);
- end loop;
- return r;
- end;
-
- -- Returns minimum array size required to fit the string
- function str_to_ascii_slv_32_arr(s: string) return t_slv_32_arr is
- constant c_slv_8: t_slv_8_arr(0 to s'right - 1) := str_to_ascii_slv_8_arr(s);
- constant c_bytes_per_word : natural := 4;
- -- Initialize all elements to (OTHERS=>'0') so any unused bytes become a NULL character
- variable r: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := (others => (others => '0'));
- begin
- for word in r'range loop -- 0, 1
- for byte in 0 to c_bytes_per_word - 1 loop -- 0,1,2,3
- if byte + c_bytes_per_word * word <= c_slv_8'right then
- r(word)(byte * c_byte_w + c_byte_w - 1 downto byte * c_byte_w) := c_slv_8(byte + c_bytes_per_word * word);
+ variable v_line: LINE;
+ begin
+ write(v_line, str);
+ writeline(output, v_line);
+ deallocate(v_line);
+ end;
+
+ procedure print_str(str: string; enable: boolean) is
+ variable v_line: LINE;
+ begin
+ if enable then
+ print_str(str);
end if;
- end loop;
- end loop;
-
- return r;
- end;
-
- -- Overloaded version to match array size to arr_size
- function str_to_ascii_slv_32_arr(s: string; arr_size: natural) return t_slv_32_arr is
- constant slv_32: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := str_to_ascii_slv_32_arr(s);
- variable r: t_slv_32_arr(0 to arr_size-1) := (others => (others => '0'));
- begin
- for word in slv_32'range loop
- r(word) := slv_32(word);
- end loop;
- return r;
- end;
+ end;
+
+ function str_to_ascii_integer_arr(s: string) return t_integer_arr is
+ variable r: t_integer_arr(0 to s'right - 1);
+ begin
+ for i in s'range loop
+ r(i - 1) := character'pos(s(i));
+ end loop;
+ return r;
+ end;
+
+ function str_to_ascii_slv_8_arr(s: string) return t_slv_8_arr is
+ variable r: t_slv_8_arr(0 to s'right - 1);
+ begin
+ for i in s'range loop
+ r(i - 1) := TO_UVEC(str_to_ascii_integer_arr(s)(i - 1), 8);
+ end loop;
+ return r;
+ end;
+
+ -- Returns minimum array size required to fit the string
+ function str_to_ascii_slv_32_arr(s: string) return t_slv_32_arr is
+ constant c_slv_8: t_slv_8_arr(0 to s'right - 1) := str_to_ascii_slv_8_arr(s);
+ constant c_bytes_per_word : natural := 4;
+ -- Initialize all elements to (OTHERS=>'0') so any unused bytes become a NULL character
+ variable r: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := (others => (others => '0'));
+ begin
+ for word in r'range loop -- 0, 1
+ for byte in 0 to c_bytes_per_word - 1 loop -- 0,1,2,3
+ if byte + c_bytes_per_word * word <= c_slv_8'right then
+ r(word)(byte * c_byte_w + c_byte_w - 1 downto byte * c_byte_w) := c_slv_8(byte + c_bytes_per_word * word);
+ end if;
+ end loop;
+ end loop;
+
+ return r;
+ end;
+
+ -- Overloaded version to match array size to arr_size
+ function str_to_ascii_slv_32_arr(s: string; arr_size: natural) return t_slv_32_arr is
+ constant slv_32: t_slv_32_arr(0 to ceil_div(s'right * c_byte_w, c_word_w) - 1) := str_to_ascii_slv_32_arr(s);
+ variable r: t_slv_32_arr(0 to arr_size-1) := (others => (others => '0'));
+ begin
+ for word in slv_32'range loop
+ r(word) := slv_32(word);
+ end loop;
+ return r;
+ end;
end common_str_pkg;
diff --git a/libraries/base/common/src/vhdl/common_switch.vhd b/libraries/base/common/src/vhdl/common_switch.vhd
index ae38d1382f21e2ae23aba02ed97605269fef8c1b..7d01ee152ac4a02230469a10d9eeaa992c1882f0 100644
--- a/libraries/base/common/src/vhdl/common_switch.vhd
+++ b/libraries/base/common/src/vhdl/common_switch.vhd
@@ -30,7 +30,7 @@
-- switch_low are active simultaneously.
library ieee;
-use ieee.std_logic_1164.all;
+ use ieee.std_logic_1164.all;
entity common_switch is
generic (
diff --git a/libraries/base/common/src/vhdl/common_toggle.vhd b/libraries/base/common/src/vhdl/common_toggle.vhd
index 79d9a4a67ddc74f473f6e32c5175c0d3a6f05218..b479a0dba5d54dc5fa1b34a7e673914b9999bb9d 100644
--- a/libraries/base/common/src/vhdl/common_toggle.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle is
generic (
@@ -65,18 +65,18 @@ begin
-- Detect in_dat event
u_in_evt : entity work.common_evt
- generic map (
- g_evt_type => g_evt_type,
- g_out_invert => false,
- g_out_reg => true
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => in_hld,
- out_evt => in_evt
- );
+ generic map (
+ g_evt_type => g_evt_type,
+ g_out_invert => false,
+ g_out_reg => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => in_hld,
+ out_evt => in_evt
+ );
-- Toggle output at in_dat event
nxt_out_dat <= not i_out_dat when in_evt = '1' else i_out_dat;
diff --git a/libraries/base/common/src/vhdl/common_toggle_align.vhd b/libraries/base/common/src/vhdl/common_toggle_align.vhd
index 6739bf67d4c9fb7a678f09ad4605353dd19c1daa..4612fb4ef483d597943ebb00d236754534571071 100644
--- a/libraries/base/common/src/vhdl/common_toggle_align.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle_align.vhd
@@ -33,7 +33,7 @@
-- even when in_toggle stops toggling or change phase for some reason.
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity common_toggle_align is
generic (
@@ -95,14 +95,14 @@ begin
end process;
u_common_pipeline_sl : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline,
- g_reset_value => g_reset_value
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => nxt_out_toggle,
- out_dat => out_toggle
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_reset_value => g_reset_value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => nxt_out_toggle,
+ out_dat => out_toggle
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_transpose.vhd b/libraries/base/common/src/vhdl/common_transpose.vhd
index 0408bdf4864644e09e5870dee67dca9bfa2b7820..a2bc25f9ca10bd393d9a77ab200dfc7c4c4a540e 100644
--- a/libraries/base/common/src/vhdl/common_transpose.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
-- Purpose: Transpose the g_nof_data symbols in g_nof_data in_data to
-- g_nof_data symbols in g_nof_data out_data,
@@ -90,204 +90,204 @@ architecture str of common_transpose is
signal hold_sel : std_logic_vector(c_sel_w - 1 downto 0);
begin
u_sreg_data : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_data,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_data_vec,
- out_cnt => sreg_sel,
-
- out_val => sreg_val,
- out_eop => sreg_eop
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_data_vec,
+ out_cnt => sreg_sel,
+
+ out_val => sreg_val,
+ out_eop => sreg_eop
+ );
u_sreg_addr : entity common_lib.common_shiftreg
- generic map (
- g_pipeline => g_pipeline_shiftreg,
- g_flush_en => true,
- g_nof_dat => g_nof_data,
- g_dat_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_addr,
- in_val => in_val,
- in_eop => in_eop,
-
- out_data_vec => sreg_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_shiftreg,
+ g_flush_en => true,
+ g_nof_dat => g_nof_data,
+ g_dat_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_addr,
+ in_val => in_val,
+ in_eop => in_eop,
+
+ out_data_vec => sreg_addr_vec
+ );
sreg_full <= '1' when sreg_val = '1' and TO_UINT(sreg_sel) = 0 else '0';
u_transpose_data : entity common_lib.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => sreg_data_vec,
- out_data => trans_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => sreg_data_vec,
+ out_data => trans_data_vec
+ );
gen_offsets : for I in g_nof_data - 1 downto 0 generate
offset_addr_vec((I + 1) * g_addr_w - 1 downto I * g_addr_w) <= TO_UVEC(I * TO_UINT(in_offset), g_addr_w);
end generate;
u_add_addr : entity common_lib.common_add_symbol
- generic map (
- g_pipeline => g_pipeline_transpose,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_a => offset_addr_vec,
- in_b => sreg_addr_vec,
-
- out_data => add_addr_vec
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_a => offset_addr_vec,
+ in_b => sreg_addr_vec,
+
+ out_data => add_addr_vec
+ );
u_trans_full : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline_transpose
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_full,
- out_dat => trans_full
- );
+ generic map (
+ g_pipeline => g_pipeline_transpose
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_full,
+ out_dat => trans_full
+ );
u_hold_data : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_full,
-
- out_data => hold_data_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_full,
+
+ out_data => hold_data_vec
+ );
u_hold_addr : entity common_lib.common_shiftreg_symbol
- generic map (
- g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
- g_pipeline => g_pipeline_hold,
- g_flush_en => false,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => add_addr_vec,
- in_val => trans_full,
-
- out_data => hold_addr_vec
- );
+ generic map (
+ g_shiftline_arr => c_holdline_arr(g_nof_data - 1 downto 0),
+ g_pipeline => g_pipeline_hold,
+ g_flush_en => false,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => add_addr_vec,
+ in_val => trans_full,
+
+ out_data => hold_addr_vec
+ );
u_hold_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_sel,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_sel,
- out_dat => hold_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_sel,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_sel,
+ out_dat => hold_sel
+ );
u_hold_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_val,
- out_dat => hold_val
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_val,
+ out_dat => hold_val
+ );
u_hold_eop : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_sel
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => sreg_eop,
- out_dat => hold_eop
- );
+ generic map (
+ g_pipeline => c_pipeline_sel
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => sreg_eop,
+ out_dat => hold_eop
+ );
u_output_data : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_data_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_data_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_data_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_data_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
u_output_addr : entity common_lib.common_select_symbol
- generic map (
- g_pipeline_in => 0,
- g_pipeline_out => g_pipeline_select,
- g_nof_symbols => g_nof_data,
- g_symbol_w => g_addr_w,
- g_sel_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => hold_addr_vec,
- in_val => hold_val,
- in_eop => hold_eop,
-
- in_sel => hold_sel,
-
- out_symbol => out_addr
- );
+ generic map (
+ g_pipeline_in => 0,
+ g_pipeline_out => g_pipeline_select,
+ g_nof_symbols => g_nof_data,
+ g_symbol_w => g_addr_w,
+ g_sel_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => hold_addr_vec,
+ in_val => hold_val,
+ in_eop => hold_eop,
+
+ in_sel => hold_sel,
+
+ out_symbol => out_addr
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index bd6fc252d0e666f29c1a638464bf5ea0fa850c8c..4575b873e700dac04e0ffb81c28d65a3108d0ece 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
-- Purpose: Transpose of in_data to out_data
-- Description:
@@ -83,7 +83,9 @@ begin
end generate;
gen_transpose : if g_nof_data > 1 generate
+
gen_data : for I in g_nof_data - 1 downto 0 generate
+
gen_symbols : for J in c_nof_symbols - 1 downto 0 generate
-- map input vector to 2arr
in_symbol_2arr(I)(J) <= in_data((J + 1) * c_symbol_w + I * g_data_w - 1 downto J * c_symbol_w + I * g_data_w);
@@ -99,49 +101,49 @@ begin
-- pipeline data output
u_out_data : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => trans_data,
- out_dat => out_data
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => trans_data,
+ out_dat => out_data
+ );
-- pipeline control output
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => out_sop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => out_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => out_eop
+ );
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 10ddd4a1eb095fa4ea55cbca134a0ee91d16e85f..ba7c0fd44507e731f48902d65437fbc2ceafe350 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -27,8 +27,8 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_variable_delay is
generic (
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 4327b27652223a0cb41674eee9732cb927ee961c..06254951f1df21549823611fba42bb77337fa34c 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -32,8 +32,8 @@
-- eases the use of this scope within a design.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_wideband_data_scope is
generic (
@@ -67,34 +67,35 @@ architecture beh of common_wideband_data_scope is
signal scope_dat : std_logic_vector(g_dat_w - 1 downto 0);
begin
sim_only : if g_sim = true generate
- use_sclk : if g_use_sclk = true generate
+ use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
- end generate;
+end generate;
- gen_sclk : if g_use_sclk = false generate
- proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
- end generate;
+gen_sclk : if g_use_sclk = false generate
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+end generate;
- -- View in_data at the sample rate using out_dat
- p_scope_dat : process(SCLKi)
- variable vI : natural;
- begin
- if rising_edge(SCLKi) then
- if g_wideband_big_endian = true then
- vI := g_wideband_factor - 1 - scope_cnt;
- else
- vI := scope_cnt;
- end if;
- scope_cnt <= 0;
- if in_val = '1' and scope_cnt < g_wideband_factor - 1 then
- scope_cnt <= scope_cnt + 1;
- end if;
- scope_dat <= in_data((vI + 1) * g_dat_w - 1 downto vI * g_dat_w);
- out_val <= in_val;
- end if;
- end process;
+-- View in_data at the sample rate using out_dat
+p_scope_dat : process(SCLKi)
+ variable vI : natural;
+begin
+ if rising_edge(SCLKi) then
+ if g_wideband_big_endian = true then
+ vI := g_wideband_factor - 1 - scope_cnt;
+ else
+ vI := scope_cnt;
+ end if;
+ scope_cnt <= 0;
+ if in_val = '1' and scope_cnt < g_wideband_factor - 1 then
+ scope_cnt <= scope_cnt + 1;
+ end if;
+ scope_dat <= in_data((vI + 1) * g_dat_w - 1 downto vI * g_dat_w);
+ out_val <= in_val;
+ end if;
+end process;
+
+out_dat <= scope_dat;
+out_int <= TO_SINT(scope_dat);
+end generate;
- out_dat <= scope_dat;
- out_int <= TO_SINT(scope_dat);
- end generate;
end beh;
diff --git a/libraries/base/common/src/vhdl/common_zip.vhd b/libraries/base/common/src/vhdl/common_zip.vhd
index 2bb1bd6abda1cba1f7929db7668139cb7b6f749d..098c8d5a075dcd28d9337e16d9a7092528856083 100644
--- a/libraries/base/common/src/vhdl/common_zip.vhd
+++ b/libraries/base/common/src/vhdl/common_zip.vhd
@@ -25,8 +25,8 @@
-- to avoid the loss of data.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity common_zip is
generic (
@@ -62,37 +62,37 @@ begin
v.out_val := '0'; -- Default the output valid signal is low.
if(in_val = '1') then -- Wait for incoming data
- v.index := 1;
- v.out_val := '1';
- v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0); -- Output the first stream already
- for I in 1 to g_nof_streams - 1 loop
- v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0); -- Store input data in register
- end loop;
- end if;
+ v.index := 1;
+ v.out_val := '1';
+ v.out_dat := in_dat_arr(0)(g_dat_w - 1 downto 0); -- Output the first stream already
+ for I in 1 to g_nof_streams - 1 loop
+ v.in_dat_arr(I) := in_dat_arr(I)(g_dat_w - 1 downto 0); -- Store input data in register
+ end loop;
+ end if;
- if(r.index < g_nof_streams) then
- v.out_val := '1';
- v.out_dat := r.in_dat_arr(r.index); -- Output the next input stream
- v.index := r.index + 1;
- end if;
+ if(r.index < g_nof_streams) then
+ v.out_val := '1';
+ v.out_dat := r.in_dat_arr(r.index); -- Output the next input stream
+ v.index := r.index + 1;
+end if;
- if(rst = '1') then
- v.in_dat_arr := (others => (others => '0'));
- v.index := g_nof_streams;
- v.out_dat := (others => '0');
- v.out_val := '0';
- end if;
+if(rst = '1') then
+v.in_dat_arr := (others => (others => '0'));
+v.index := g_nof_streams;
+v.out_dat := (others => '0');
+v.out_val := '0';
+end if;
- rin <= v;
- end process comb;
+rin <= v;
+end process comb;
- regs : process(clk)
- begin
- if rising_edge(clk) then
- r <= rin;
- end if;
- end process;
+regs : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
- out_dat <= r.out_dat;
- out_val <= r.out_val;
+out_dat <= r.out_dat;
+out_val <= r.out_val;
end rtl;
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index ea0228354d9411895fb7453fa07eb334c6e49ac8..9b9570750dc6cda2a95e723f3737fb899dd2f4ce 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -25,17 +25,17 @@
-- . MM wrapper for common_pulse_delay.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_common_pulse_delay is
generic (
g_pulse_delay_max : natural := 0; -- Maximum number of clk cycles that pulse can be delayed
g_register_out : boolean
- );
+ );
port (
pulse_clk : in std_logic;
pulse_rst : in std_logic;
@@ -56,34 +56,34 @@ begin
-- common_pulse_delay
------------------------------------------------------------------------------
u_common_pulse_delay : entity common_lib.common_pulse_delay
- generic map (
- g_pulse_delay_max => g_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => pulse_clk,
- rst => pulse_rst,
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => g_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => pulse_clk,
+ rst => pulse_rst,
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
------------------------------------------------------------------------------
-- New MM interface via avs_common_mm
------------------------------------------------------------------------------
u_common_pulse_delay_reg : entity work.common_pulse_delay_reg
- generic map (
- g_cross_clock_domain => true,
- g_pulse_delay_max => g_pulse_delay_max
- )
- port map (
- pulse_clk => pulse_clk,
- pulse_rst => pulse_rst,
- pulse_delay => pulse_delay,
+ generic map (
+ g_cross_clock_domain => true,
+ g_pulse_delay_max => g_pulse_delay_max
+ )
+ port map (
+ pulse_clk => pulse_clk,
+ pulse_rst => pulse_rst,
+ pulse_delay => pulse_delay,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- sla_in => reg_mosi,
- sla_out => reg_miso
- );
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ sla_in => reg_mosi,
+ sla_out => reg_miso
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 56fb4f3865a2cbee12747a9ffa69878e1bf7856b..29af1c6621a8b14cfbcabc7b03e64ec6675b06a1 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -23,9 +23,9 @@
-- Description: Wrapper, see common_reg_r_w_dc.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_reg is
generic (
@@ -61,27 +61,27 @@ architecture str of mms_common_reg is
constant c_init_reg : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => g_mm_reg.init_sl);
begin
u_common_reg_r_w_dc : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => g_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => g_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => in_reg,
- out_reg => out_reg
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => in_reg,
+ out_reg => out_reg
+ );
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index c1bf30f4e766887b13fc92adceb1eca0088d0ebe..907477fc1afae8c1bb355aed775b60eb0c8e6b21 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -23,9 +23,9 @@
-- Description: See common_stable_monitor.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_common_stable_monitor is
generic (
@@ -53,42 +53,43 @@ architecture str of mms_common_stable_monitor is
constant c_adr_w : natural := ceil_log2(c_nof_dat);
constant c_dat_w : natural := sel_a_b(c_nof_dat = 1, g_nof_input, c_word_w);
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_adr_w,
- dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_adr_w,
+ dat_w => c_dat_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_dat,
+ init_sl => '0');
- signal reg_rd_arr : std_logic_vector(c_mm_reg.nof_dat - 1 downto 0);
+ signal reg_rd_arr : std_logic_vector(c_mm_reg.nof_dat - 1 downto 0);
- signal st_stable_arr : std_logic_vector(g_nof_input - 1 downto 0);
- signal st_stable_ack : std_logic;
+ signal st_stable_arr : std_logic_vector(g_nof_input - 1 downto 0);
+ signal st_stable_ack : std_logic;
- signal in_reg : std_logic_vector(c_nof_dat * c_word_w - 1 downto 0);
+ signal in_reg : std_logic_vector(c_nof_dat * c_word_w - 1 downto 0);
begin
u_mm_reg : entity work.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_reg => in_reg,
- out_reg => open
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_reg => in_reg,
+ out_reg => open
+ );
in_reg(g_nof_input - 1 downto 0) <= st_stable_arr;
@@ -97,14 +98,13 @@ begin
gen_mon : for I in g_nof_input - 1 downto 0 generate
u_stable_monitor : entity work.common_stable_monitor
- port map (
- rst => st_rst,
- clk => st_clk,
- -- MM
- r_in => st_in_arr(I),
- r_stable => st_stable_arr(I),
- r_stable_ack => st_stable_ack
- );
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- MM
+ r_in => st_in_arr(I),
+ r_stable => st_stable_arr(I),
+ r_stable_ack => st_stable_ack
+ );
end generate;
-
end str;
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index 57d388d15f500b1d3cc92f08eec27ff3e0db3556..150ca4e7e9e66c0bb0e2a86fd5b227da1fa44e1e 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -26,10 +26,10 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
entity mms_common_variable_delay is
port (
@@ -61,30 +61,30 @@ begin
-- device under test
u_common_variable_delay : entity work.common_variable_delay
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
u_mms_common_reg : entity work.mms_common_reg
- generic map (
- g_mm_reg => c_enable_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_mm_reg => c_enable_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- reg_mosi => reg_enable_mosi,
- reg_miso => reg_enable_miso,
+ reg_mosi => reg_enable_mosi,
+ reg_miso => reg_enable_miso,
- in_reg => enable_reg,
- out_reg => enable_reg
- );
+ in_reg => enable_reg,
+ out_reg => enable_reg
+ );
end;
diff --git a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
index 615f744bf26f4ae82be111d02e59c66eca2c4aa5..c6addaeb0a133648c78f647f91c4f8849c6ab04e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_acapture is
end tb_common_acapture;
@@ -75,14 +75,14 @@ begin
end process;
u_acapture : entity work.common_acapture
- generic map (
- g_rst_level => '0'
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_dat => in_dat,
- out_clk => out_clk,
- out_cap => out_cap
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_dat => in_dat,
+ out_clk => out_clk,
+ out_cap => out_cap
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index b415d4357756ff863f60880ad9b48e35103bd05a..56b0257c7a2d27814ba76e8ef8ef181ce1be9770 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_add_sub is
generic (
@@ -50,8 +50,8 @@ architecture tb of tb_common_add_sub is
if g_direction = "BOTH" and g_sel_add = '1' then v_result := v_a + v_b; end if;
if g_direction = "BOTH" and g_sel_add = '0' then v_result := v_a - v_b; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
- if v_result > 2**(g_out_dat_w - 1) - 1 then v_result := v_result - 2**g_out_dat_w; end if;
- if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
+ if v_result > 2 ** (g_out_dat_w - 1) - 1 then v_result := v_result - 2 ** g_out_dat_w; end if;
+ if v_result < - 2 ** (g_out_dat_w - 1) then v_result := v_result + 2 ** g_out_dat_w; end if;
return TO_SVEC(v_result, g_out_dat_w);
end;
@@ -112,8 +112,8 @@ begin
end loop;
-- All combinations
- for I in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
- for J in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
+ for I in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
+ for J in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
in_a <= TO_SVEC(I, g_in_dat_w);
in_b <= TO_SVEC(J, g_in_dat_w);
wait until rising_edge(clk);
@@ -127,38 +127,38 @@ begin
out_result <= func_result(in_a, in_b);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_add_sub
- generic map (
- g_direction => g_direction,
- g_representation => "SIGNED",
- g_pipeline_input => g_pipeline_in,
- g_pipeline_output => g_pipeline_out,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => g_sel_add,
- in_a => in_a,
- in_b => in_b,
- result => result_rtl
- );
+ generic map (
+ g_direction => g_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => g_pipeline_in,
+ g_pipeline_output => g_pipeline_out,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => g_sel_add,
+ in_a => in_a,
+ in_b => in_b,
+ result => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1686b6f4e3b5512fe8e5fa259922b31b52fd688d..af16c41caa135cc3af57950e8417dead9c8d0757 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -31,10 +31,10 @@
-- . The p_verify makes the tb self checking and asserts when the results are not equal
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_adder_tree is
generic (
@@ -109,7 +109,7 @@ begin
proc_common_wait_some_cycles(clk, 5);
-- Apply equal symbol value inputs
- for I in 0 to 2**g_symbol_w - 1 loop
+ for I in 0 to 2 ** g_symbol_w - 1 loop
in_data_vec <= func_data_vec(I);
proc_common_wait_some_cycles(clk, 1);
end loop;
@@ -124,20 +124,20 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated symbols in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -149,36 +149,36 @@ begin
result_comb <= func_result(in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => g_sum_w,
- g_out_dat_w => g_sum_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => result_comb,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => g_sum_w,
+ g_out_dat_w => g_sum_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => result_comb,
+ out_dat => result_expected
+ );
-- Using work.common_adder_tree(recursive) will only invoke the recursive architecture once, because the next recursive level will default to using the last compiled architecture
-- Therefore only instatiatiate the DUT once in this tb and use compile order to influence which architecture is used.
dut : entity work.common_adder_tree -- uses last compile architecture
- generic map (
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_symbol_w,
- g_sum_w => g_sum_w
- )
- port map (
- clk => clk,
- in_dat => in_data_vec,
- sum => result_dut
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_symbol_w,
+ g_sum_w => g_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_data_vec,
+ sum => result_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_async.vhd b/libraries/base/common/tb/vhdl/tb_common_async.vhd
index e6bf4e8c47b7a208b4e4d6abfb3a60764fe56a5a..4f572784c2e78f56e4141b3e50d8af06b050c8f4 100644
--- a/libraries/base/common/tb/vhdl/tb_common_async.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_async.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_async is
end tb_common_async;
@@ -82,25 +82,25 @@ begin
end process;
u_async : entity work.common_async
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- rst => in_rst,
- clk => clk,
- din => in_dat,
- dout => out_async
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ rst => in_rst,
+ clk => clk,
+ din => in_dat,
+ dout => out_async
+ );
u_areset : entity work.common_areset
- generic map (
- g_rst_level => '1',
- g_delay_len => c_delay_len
- )
- port map (
- in_rst => in_rst,
- clk => clk,
- out_rst => out_areset
- );
+ generic map (
+ g_rst_level => '1',
+ g_delay_len => c_delay_len
+ )
+ port map (
+ in_rst => in_rst,
+ clk => clk,
+ out_rst => out_areset
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
index 27265014b5ad9e222bcebc9c4ddc8cb5d4f3ff86..04bdd96be7cde4ecf3bdbae10fbd4a1ebe969e85 100644
--- a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
@@ -27,10 +27,10 @@
-- Description:
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_clock_phase_detector is
generic (
@@ -87,30 +87,30 @@ begin
end process;
u_common_clock_phase_detector_r : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => true,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_r,
- phase_det => phase_r_det
- );
+ generic map (
+ g_rising_edge => true,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_r,
+ phase_det => phase_r_det
+ );
u_common_clock_phase_detector_f : entity work.common_clock_phase_detector
- generic map (
- g_rising_edge => false,
- g_meta_delay_len => c_delay_len,
- g_clk_factor => c_clk_factor_num
- )
- port map (
- in_clk => in_clk, -- used as data input for clk domain
- rst => rst,
- clk => clk,
- phase => phase_f,
- phase_det => phase_f_det
- );
+ generic map (
+ g_rising_edge => false,
+ g_meta_delay_len => c_delay_len,
+ g_clk_factor => c_clk_factor_num
+ )
+ port map (
+ in_clk => in_clk, -- used as data input for clk domain
+ rst => rst,
+ clk => clk,
+ phase => phase_f,
+ phase_det => phase_f_det
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index ff4e5fd21d1e654375919064c2f6f76452eb05a3..333d016e3aa1a079f9cc73bc5a5e09e09ffa4493 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_counter is
end tb_common_counter;
@@ -80,26 +80,26 @@ begin
end loop;
-- set the cnt_max
- cnt_max <= TO_UVEC(2**(c_cnt_w - 1), c_cnt_w);
+ cnt_max <= TO_UVEC(2 ** (c_cnt_w - 1), c_cnt_w);
wait;
end process;
-- device under test
u_dut : entity work.common_counter
- generic map (
- g_init => c_cnt_init,
- g_width => c_cnt_w,
- g_step_size => 1
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_ld => cnt_ld,
- cnt_en => cnt_en,
- cnt_max => cnt_max,
- load => load,
- count => count
- );
+ generic map (
+ g_init => c_cnt_init,
+ g_width => c_cnt_w,
+ g_step_size => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_ld => cnt_ld,
+ cnt_en => cnt_en,
+ cnt_max => cnt_max,
+ load => load,
+ count => count
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index c42ebccaeef4d30440159588d01a6d5368aab779..410f19137e7dace42be3e2ca3f8b45fbe04414b2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -24,9 +24,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_create_strobes_from_valid is
generic (
@@ -121,18 +121,18 @@ begin
end process;
u_in_sync : entity work.common_create_strobes_from_valid
- generic map (
- g_pipeline => g_pipeline,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_nof_clk_per_block => g_nof_clk_per_block
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_nof_clk_per_block => g_nof_clk_per_block
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
index c333692fd14602eaa911499a8f7c072ae5dde85e..a7ad038aae4c2c37d43a2988540e9372bd76afde 100644
--- a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
@@ -27,10 +27,10 @@
-- Description: See common_ddreg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_ddreg_slv is
end tb_common_ddreg_slv;
@@ -66,18 +66,18 @@ begin
end process;
u_common_ddreg_slv : entity work.common_ddreg_slv
- generic map (
- g_in_delay_len => 1,
- g_out_delay_len => c_meta_delay_len
- )
- port map (
- in_clk => in_clk,
- in_dat => in_dat,
- rst => rst,
- out_clk => out_clk,
- out_dat_hi => out_dat_hi,
- out_dat_lo => out_dat_lo
- );
+ generic map (
+ g_in_delay_len => 1,
+ g_out_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_clk => in_clk,
+ in_dat => in_dat,
+ rst => rst,
+ out_clk => out_clk,
+ out_dat_hi => out_dat_hi,
+ out_dat_lo => out_dat_lo
+ );
out_dat <= out_dat_hi & out_dat_lo;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
index bbd52cac8588a2a541d69c918273605e757c32f8..5d920563777f7ebd4820a65b06e11aa63c4ccd4a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
@@ -38,8 +38,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_debounce is
end tb_common_debounce;
@@ -168,46 +168,46 @@ begin
end process;
u_debounce_both : entity work.common_debounce
- generic map (
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_both
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_both
- );
+ generic map (
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_both
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_both
+ );
u_debounce_high : entity work.common_debounce
- generic map (
- g_type => "HIGH",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_high
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_high
- );
+ generic map (
+ g_type => "HIGH",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_high
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_high
+ );
u_debounce_low : entity work.common_debounce
- generic map (
- g_type => "LOW",
- g_delay_len => c_meta_delay_len,
- g_latency => c_latency,
- g_init_level => c_rst_level_low
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- d_in => d_in,
- q_out => q_low
- );
+ generic map (
+ g_type => "LOW",
+ g_delay_len => c_meta_delay_len,
+ g_latency => c_latency,
+ g_init_level => c_rst_level_low
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ d_in => d_in,
+ q_out => q_low
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
index 861bc4118fbebc6162953117875173f6d8be663c..ac59a92fde83e4024a85a2a61f7bfceb74d14ebf 100644
--- a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_duty_cycle is
end tb_common_duty_cycle;
@@ -110,21 +110,21 @@ begin
-----------------------------------------------------------------------------
dut : entity work.common_duty_cycle
- generic map (
- g_rst_lvl => '0',
- g_dis_lvl => '0',
- g_act_lvl => '1',
- g_per_cnt => c_dc_max_period_cnt,
- g_act_cnt => 10
- )
- port map (
- rst => rst,
- clk => clk,
-
- dc_per_cnt => dc_per_cnt,
- dc_act_cnt => dc_act_cnt,
-
- dc_out_en => dc_out_en,
- dc_out => dc_out
- );
+ generic map (
+ g_rst_lvl => '0',
+ g_dis_lvl => '0',
+ g_act_lvl => '1',
+ g_per_cnt => c_dc_max_period_cnt,
+ g_act_cnt => 10
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ dc_per_cnt => dc_per_cnt,
+ dc_act_cnt => dc_act_cnt,
+
+ dc_out_en => dc_out_en,
+ dc_out => dc_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index d5b732914c646908c5fe68787948e8d0aeaca8e5..91f0c033753ec7e585cc9d138c0868521bf75bee 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -27,11 +27,11 @@
-- when the fanout data is not incrementing.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fanout_tree is
generic (
@@ -54,9 +54,9 @@ architecture tb of tb_common_fanout_tree is
constant c_init : natural := 0;
constant c_dat_w : natural := 8;
- constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
+ constant c_nof_output : natural := g_nof_output_per_cell ** g_nof_stages;
constant c_tree_pipeline_arr : t_natural_arr(c_nof_output - 1 downto 0) := func_common_fanout_tree_pipelining(g_nof_stages, g_nof_output_per_cell, c_nof_output,
- g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
+ g_cell_pipeline_factor_arr, g_cell_pipeline_arr);
constant c_tree_pipeline_max : natural := largest(c_tree_pipeline_arr);
type t_data_arr is array (integer range <>) of std_logic_vector(c_dat_w - 1 downto 0);
@@ -94,7 +94,7 @@ begin
proc_common_wait_some_cycles(clk, c_tree_pipeline_max);
verify_en <= '1';
- proc_common_wait_some_cycles(clk, 2**c_dat_w);
+ proc_common_wait_some_cycles(clk, 2 ** c_dat_w);
proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -110,23 +110,23 @@ begin
proc_common_gen_data(c_rl, c_init, rst, clk, cnt_en, ready, in_dat, in_val);
dut : entity work.common_fanout_tree
- generic map (
- g_nof_stages => g_nof_stages,
- g_nof_output_per_cell => g_nof_output_per_cell,
- g_nof_output => g_nof_output,
- g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
- g_cell_pipeline_arr => g_cell_pipeline_arr,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_en => in_en,
- in_dat => in_dat,
- in_val => in_val,
- out_en_vec => out_en_vec,
- out_dat_vec => out_dat_vec,
- out_val_vec => out_val_vec
- );
+ generic map (
+ g_nof_stages => g_nof_stages,
+ g_nof_output_per_cell => g_nof_output_per_cell,
+ g_nof_output => g_nof_output,
+ g_cell_pipeline_factor_arr => g_cell_pipeline_factor_arr,
+ g_cell_pipeline_arr => g_cell_pipeline_arr,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_en => in_en,
+ in_dat => in_dat,
+ in_val => in_val,
+ out_en_vec => out_en_vec,
+ out_dat_vec => out_dat_vec,
+ out_val_vec => out_val_vec
+ );
-- Verify data for fanout output 0
proc_common_verify_data(c_rl, clk, verify_en, ready, out_val_vec(0), out_dat_arr(0), prev_out_dat_arr(0));
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
index 59082dfeef4c8bc1dd5781dee5c4cb58863e24e6..a910a20b33c4624c789e6632d137190a3c5ec313 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
@@ -26,10 +26,10 @@
-- . observe rd_dat in wave window
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_dc_mixed_widths is
generic (
@@ -44,7 +44,7 @@ end tb_common_fifo_dc_mixed_widths;
architecture tb of tb_common_fifo_dc_mixed_widths is
constant clk_period : time := 10 ns;
- constant c_run_interval : natural := 2**g_wr_dat_w;
+ constant c_run_interval : natural := 2 ** g_wr_dat_w;
constant c_wr_fifo_nof_words : natural := 32;
@@ -103,23 +103,23 @@ begin
rd_req <= '1';
u_dut : entity work.common_fifo_dc_mixed_widths
- generic map (
- g_nof_words => c_wr_fifo_nof_words,
- g_wr_dat_w => g_wr_dat_w,
- g_rd_dat_w => g_rd_dat_w
- )
- port map (
- rst => rst,
- wr_clk => wr_clk,
- wr_dat => wr_dat,
- wr_req => wr_val,
- wr_ful => wr_ful,
- wrusedw => wr_usedw,
- rd_clk => rd_clk,
- rd_dat => rd_dat,
- rd_req => rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => rd_val
- );
+ generic map (
+ g_nof_words => c_wr_fifo_nof_words,
+ g_wr_dat_w => g_wr_dat_w,
+ g_rd_dat_w => g_rd_dat_w
+ )
+ port map (
+ rst => rst,
+ wr_clk => wr_clk,
+ wr_dat => wr_dat,
+ wr_req => wr_val,
+ wr_ful => wr_ful,
+ wrusedw => wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => rd_dat,
+ rd_req => rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
index ca6a2b06dc61fe3b6d1cbd86332354e23a0b5115..cb4da944a0a0f1f0302c44ce8beaaffe958664ea 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_fifo_rd is
generic (
@@ -78,19 +78,19 @@ begin
proc_common_verify_valid(c_read_rl, clk, verify_en, rd_req, prev_rd_req, rd_val);
u_dut : entity work.common_fifo_rd
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink: RL = 1
- fifo_req => fifo_req,
- fifo_dat => fifo_dat,
- fifo_val => fifo_val,
- -- ST source: RL = 0
- rd_req => rd_req,
- rd_dat => rd_dat,
- rd_val => rd_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink: RL = 1
+ fifo_req => fifo_req,
+ fifo_dat => fifo_dat,
+ fifo_val => fifo_val,
+ -- ST source: RL = 0
+ rd_req => rd_req,
+ rd_dat => rd_dat,
+ rd_val => rd_val
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
index 4a83e2948f94468b7774b9c71d3b7244063d25b2..f035606ace130f2c6e216462931ba533bb17b890 100644
--- a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_flank_to_pulse is
end tb_common_flank_to_pulse;
@@ -55,10 +55,10 @@ begin
end process;
u_dut: entity work.common_flank_to_pulse
- port map (
- clk => clk,
- rst => rst,
- flank_in => flank_in,
- pulse_out => pulse_out
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ flank_in => flank_in,
+ pulse_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
index 2acc79d324a88d3e76b47d8984d2dc304d8a1e0a..a98da0f5ae156e79398231dd028b9d8a8b89eedf 100644
--- a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
@@ -25,9 +25,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_gcd is
end tb_common_gcd;
diff --git a/libraries/base/common/tb/vhdl/tb_common_init.vhd b/libraries/base/common/tb/vhdl/tb_common_init.vhd
index 04488cf09601e7ff617f3ebb9eb48547810a22a5..5a55a9eb807be7793ce4587c3d8e18be9e54acd7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_init.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_init.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_init is
end tb_common_init;
@@ -41,24 +41,24 @@ begin
clk <= not clk after clk_period / 2;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_init: entity work.common_init
- generic map (
- g_latency_w => c_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- hold => hold,
- init => init
- );
+ generic map (
+ g_latency_w => c_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ hold => hold,
+ init => init
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
index 507ce94cc18fa3fec3f1ba96fe11e5b77d49d721..5a77fc436676e1519f56acbd7da6b4b5f604763b 100644
--- a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
@@ -1,7 +1,7 @@
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_int2float is
end tb_common_int2float;
@@ -12,7 +12,7 @@ architecture tb of tb_common_int2float is
-- use smaller values to ease use of 32 bit integers
constant c_in_dat_w : natural := 8;
constant c_out_dat_w : natural := 6;
- constant c_exp : integer := 2**(c_in_dat_w - c_out_dat_w + 1);
+ constant c_exp : integer := 2 ** (c_in_dat_w - c_out_dat_w + 1);
constant c_pipeline : natural := 2;
signal clk : std_logic := '0';
@@ -73,7 +73,7 @@ begin
in_dat <= TO_SVEC(0, in_dat'length);
wait until rising_edge(clk);
wait until rising_edge(clk);
- for I in - 2**(c_in_dat_w - 1) to 2**(c_in_dat_w - 1) - 1 loop
+ for I in - 2 ** (c_in_dat_w - 1) to 2 ** (c_in_dat_w - 1) - 1 loop
in_val <= '1';
in_dat <= TO_SVEC( I, in_dat'length);
wait until rising_edge(clk);
@@ -83,12 +83,12 @@ begin
end process;
u_float : entity work.common_int2float
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
index 48aad92238cd56c41c2075e933483188d60eb988..87daf9c9633c47f242e35663cad66329d2dccd92 100644
--- a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
@@ -25,9 +25,9 @@
-- in Wave window zoom in and expand out_dat to see the 50 ps delays
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_iobuf_in is
end tb_common_iobuf_in;
@@ -52,14 +52,14 @@ begin
in_dat <= not(in_dat) when rising_edge(clk);
u_dut : entity work.common_iobuf_in
- generic map (
- g_width => c_width,
- g_delay_arr => c_delay_arr
- )
- port map (
- config_rst => rst,
- config_clk => clk,
- in_dat => in_dat,
- out_dat => out_dat
- );
+ generic map (
+ g_width => c_width,
+ g_delay_arr => c_delay_arr
+ )
+ port map (
+ config_rst => rst,
+ config_clk => clk,
+ in_dat => in_dat,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
index 3934f37a7c894d0f54dd11c524adf3e3442c4466..1ea5e0f0705a8751e586443526da2a2798552391 100644
--- a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
@@ -32,8 +32,8 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_common_led_controller is
end tb_common_led_controller;
@@ -101,38 +101,38 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ );
u_common_toggle_ms : entity work.common_toggle
- port map (
- rst => rst,
- clk => clk,
- in_dat => pulse_ms,
- out_dat => toggle_ms
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pulse_ms,
+ out_dat => toggle_ms
+ );
u_common_led_controller : entity work.common_led_controller
- generic map (
- g_nof_ms => c_led_nof_ms
- )
- port map (
- rst => rst,
- clk => clk,
- pulse_ms => pulse_ms,
- -- led control
- ctrl_on => ctrl_on,
- ctrl_evt => ctrl_evt,
- ctrl_input => toggle_ms,
- -- led output
- led => LED
- );
+ generic map (
+ g_nof_ms => c_led_nof_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pulse_ms => pulse_ms,
+ -- led control
+ ctrl_on => ctrl_on,
+ ctrl_evt => ctrl_evt,
+ ctrl_input => toggle_ms,
+ -- led output
+ led => LED
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_log.vhd b/libraries/base/common/tb/vhdl/tb_common_log.vhd
index a93bcbce954186193242527335308a3e5cad1243..67aebd2d997773cac73ef862a097c5d74444ef1f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_log.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_log.vhd
@@ -22,9 +22,9 @@
-- Usage:
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
entity tb_common_log is
end tb_common_log;
@@ -38,29 +38,29 @@ begin
print_str("I: pow2, ceil_pow2");
for I in 1 to 20 loop
print_str(int_to_str(I) & ": " &
- int_to_str(pow2(I)) & ", " &
- int_to_str(ceil_pow2(I)));
+ int_to_str(pow2(I)) & ", " &
+ int_to_str(ceil_pow2(I)));
end loop;
print_str("");
print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
for I in 1 to 20 loop
print_str(int_to_str(I) & ": " &
- int_to_str(ceil_log2(I)) & ", " &
- int_to_str(true_log2(I)) & ", " &
- int_to_str(true_log_pow2(I)) & ", " &
- bool_to_str(is_pow2(I)) & ", " &
- int_to_str(floor_log10(I)));
+ int_to_str(ceil_log2(I)) & ", " &
+ int_to_str(true_log2(I)) & ", " &
+ int_to_str(true_log_pow2(I)) & ", " &
+ bool_to_str(is_pow2(I)) & ", " &
+ int_to_str(floor_log10(I)));
end loop;
print_str("");
print_str("I: ceil_log2, true_log2, true_log_pow2, is_pow2, floor_log10");
for I in c_range'range loop
vI := c_range(I);
print_str(int_to_str(vI) & ": " &
- int_to_str(ceil_log2(vI)) & ", " &
- int_to_str(true_log2(vI)) & ", " &
- int_to_str(true_log_pow2(vI)) & ", " &
- bool_to_str(is_pow2(vI)) & ", " &
- int_to_str(floor_log10(vI)));
+ int_to_str(ceil_log2(vI)) & ", " &
+ int_to_str(true_log2(vI)) & ", " &
+ int_to_str(true_log_pow2(vI)) & ", " &
+ bool_to_str(is_pow2(vI)) & ", " &
+ int_to_str(floor_log10(vI)));
end loop;
wait;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 76794c62a8d87f21ef51923b4c998ac31900e934..86444941778d81a2901dfa017b40ac7c1acb5dbd 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_common_mem_mux is
- generic (
+ generic (
g_nof_mosi : positive := 16; -- Number of memory interfaces in the array.
g_mult_addr_w : positive := 4 -- Address width of each memory-interface element in the array.
);
@@ -42,19 +42,20 @@ architecture tb of tb_common_mem_mux is
constant clk_period : time := 10 ns;
constant c_data_w : natural := 32;
- constant c_test_ram : t_c_mem := (latency => 1,
- adr_w => g_mult_addr_w,
- dat_w => c_data_w,
- nof_dat => 2**g_mult_addr_w,
- init_sl => '0');
- signal rst : std_logic;
- signal clk : std_logic := '1';
- signal tb_end : std_logic;
+ constant c_test_ram : t_c_mem := (
+ latency => 1,
+ adr_w => g_mult_addr_w,
+ dat_w => c_data_w,
+ nof_dat => 2**g_mult_addr_w,
+ init_sl => '0');
+ signal rst : std_logic;
+ signal clk : std_logic := '1';
+ signal tb_end : std_logic;
- signal mosi_arr : t_mem_mosi_arr(g_nof_mosi - 1 downto 0);
- signal miso_arr : t_mem_miso_arr(g_nof_mosi - 1 downto 0);
- signal mosi : t_mem_mosi;
- signal miso : t_mem_miso;
+ signal mosi_arr : t_mem_mosi_arr(g_nof_mosi - 1 downto 0);
+ signal miso_arr : t_mem_miso_arr(g_nof_mosi - 1 downto 0);
+ signal mosi : t_mem_mosi;
+ signal miso : t_mem_miso;
begin
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -67,19 +68,19 @@ begin
-- Write the whole memory range
for I in 0 to g_nof_mosi - 1 loop
- for J in 0 to 2**g_mult_addr_w - 1 loop
- proc_mem_mm_bus_wr(I * 2**g_mult_addr_w + J, I + J, clk, mosi);
+ for J in 0 to 2 ** g_mult_addr_w - 1 loop
+ proc_mem_mm_bus_wr(I * 2 ** g_mult_addr_w + J, I + J, clk, mosi);
end loop;
end loop;
-- Read back the whole range and check if data is as expected
for I in 0 to g_nof_mosi - 1 loop
- for J in 0 to 2**g_mult_addr_w - 1 loop
- proc_mem_mm_bus_rd(I * 2**g_mult_addr_w + J, clk, mosi);
+ for J in 0 to 2 ** g_mult_addr_w - 1 loop
+ proc_mem_mm_bus_rd(I * 2 ** g_mult_addr_w + J, clk, mosi);
proc_common_wait_some_cycles(clk, 1);
temp := TO_UINT(miso.rddata(31 downto 0));
if(temp /= I + J) then
- report "Error! Readvalue is not as expected" severity ERROR;
+ report "Error! Readvalue is not as expected" severity ERROR;
end if;
end loop;
end loop;
@@ -89,33 +90,33 @@ begin
generation_of_test_rams : for I in 0 to g_nof_mosi - 1 generate
u_test_rams : entity work.common_ram_r_w
+ generic map (
+ g_ram => c_test_ram,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ wr_en => mosi_arr(I).wr,
+ wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
+ rd_en => mosi_arr(I).rd,
+ rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
+ rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
+ rd_val => miso_arr(I).rdval
+ );
+ end generate;
+
+ d_dut : entity work.common_mem_mux
generic map (
- g_ram => c_test_ram,
- g_init_file => "UNUSED"
+ g_nof_mosi => g_nof_mosi,
+ g_mult_addr_w => g_mult_addr_w
)
port map (
- rst => rst,
- clk => clk,
- clken => '1',
- wr_en => mosi_arr(I).wr,
- wr_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- wr_dat => mosi_arr(I).wrdata(c_data_w - 1 downto 0),
- rd_en => mosi_arr(I).rd,
- rd_adr => mosi_arr(I).address(g_mult_addr_w - 1 downto 0),
- rd_dat => miso_arr(I).rddata(c_data_w - 1 downto 0),
- rd_val => miso_arr(I).rdval
+ mosi_arr => mosi_arr,
+ miso_arr => miso_arr,
+ mosi => mosi,
+ miso => miso
);
- end generate;
-
- d_dut : entity work.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_mosi,
- g_mult_addr_w => g_mult_addr_w
- )
- port map (
- mosi_arr => mosi_arr,
- miso_arr => miso_arr,
- mosi => mosi,
- miso => miso
- );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
index 94e5f10bbfb7a530bd28415974f67c6a6872c6fe..14d0b751d0a413746a8e1493364d67915ea3979a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.common_mem_pkg.all;
package tb_common_mem_pkg is
------------------------------------------------------------------------------
@@ -35,65 +35,76 @@ package tb_common_mem_pkg is
-- as signal).
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer; -- [31:0]
- signal wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in integer; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural; -- [31:0]
- constant wr_data : in std_logic_vector; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_wr( -- [31:0]
+ constant wr_addr : in natural;
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr( -- [31:0]
+ constant wr_addr : in integer;
+ signal wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr( -- [31:0]
+ constant wr_addr : in natural;
+ constant wr_data : in integer; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_mem_mm_bus_wr( -- [31:0]
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector; -- [31:0]
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read data request to the MM bus
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso; -- used for waitrequest
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd( -- [31:0]
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso; -- used for waitrequest
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural; -- [31:0]
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_mm_bus_rd( -- [31:0]
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Wait for read data valid after read latency mm_clk cycles
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic);
+ procedure proc_mem_mm_bus_rd_latency(
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic);
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_write_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_mem_write_ram(
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
-
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr);
+ procedure proc_mem_read_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
+
+ procedure proc_mem_read_ram(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr);
end tb_common_mem_pkg;
package body tb_common_mem_pkg is
@@ -102,8 +113,9 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Issues a rd or a wr MM access
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access(
+ signal mm_clk : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -111,9 +123,10 @@ package body tb_common_mem_pkg is
end proc_mm_access;
-- Issues a rd or a wr MM access and wait for it to have finished
- procedure proc_mm_access(signal mm_clk : in std_logic;
- signal mm_waitreq : in std_logic;
- signal mm_access : out std_logic) is
+ procedure proc_mm_access(
+ signal mm_clk : in std_logic;
+ signal mm_waitreq : in std_logic;
+ signal mm_access : out std_logic) is
begin
mm_access <= '1';
wait until rising_edge(mm_clk);
@@ -128,42 +141,46 @@ package body tb_common_mem_pkg is
------------------------------------------------------------------------------
-- Write data to the MM bus
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
- signal wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in integer;
+ signal wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in integer;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in integer;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= TO_MEM_DATA(wr_data);
proc_mm_access(mm_clk, mm_mosi.wr);
end proc_mem_mm_bus_wr;
- procedure proc_mem_mm_bus_wr(constant wr_addr : in natural;
- constant wr_data : in std_logic_vector;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_wr(
+ constant wr_addr : in natural;
+ constant wr_data : in std_logic_vector;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(wr_addr);
mm_mosi.wrdata <= RESIZE_UVEC(wr_data, c_mem_data_w);
@@ -173,18 +190,20 @@ package body tb_common_mem_pkg is
-- Read data request to the MM bus
-- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
-- to show the data after some read latency
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.rd);
end proc_mem_mm_bus_rd;
- procedure proc_mem_mm_bus_rd(constant rd_addr : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_mm_bus_rd(
+ constant rd_addr : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
mm_mosi.address <= TO_MEM_ADDRESS(rd_addr);
proc_mm_access(mm_clk, mm_mosi.rd);
@@ -192,18 +211,20 @@ package body tb_common_mem_pkg is
-- Wait for read data valid after read latency mm_clk cycles
-- Directly assign mm_miso.rddata to capture the read data
- procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
- signal mm_clk : in std_logic) is
+ procedure proc_mem_mm_bus_rd_latency(
+ constant c_rd_latency : in natural;
+ signal mm_clk : in std_logic) is
begin
for I in 0 to c_rd_latency - 1 loop wait until rising_edge(mm_clk); end loop;
end proc_mem_mm_bus_rd_latency;
-- Write array of data words to the memory
- procedure proc_mem_write_ram(constant offset : in natural;
- constant nof_data : in natural;
- constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_data_arr : t_slv_32_arr(data_arr'length - 1 downto 0) := data_arr; -- map to fixed range [h:0]
begin
for I in 0 to nof_data - 1 loop
@@ -211,9 +232,10 @@ package body tb_common_mem_pkg is
end loop;
end proc_mem_write_ram;
- procedure proc_mem_write_ram(constant data_arr : in t_slv_32_arr;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_mem_write_ram(
+ constant data_arr : in t_slv_32_arr;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
@@ -221,12 +243,13 @@ package body tb_common_mem_pkg is
end proc_mem_write_ram;
-- Read array of data words from the memory
- procedure proc_mem_read_ram(constant offset : in natural;
- constant nof_data : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram(
+ constant offset : in natural;
+ constant nof_data : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
begin
for I in 0 to nof_data - 1 loop
proc_mem_mm_bus_rd(offset + I, mm_clk, mm_mosi);
@@ -237,10 +260,11 @@ package body tb_common_mem_pkg is
wait until rising_edge(mm_clk);
end proc_mem_read_ram;
- procedure proc_mem_read_ram(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi;
- signal mm_miso : in t_mem_miso;
- signal data_arr : out t_slv_32_arr) is
+ procedure proc_mem_read_ram(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi;
+ signal mm_miso : in t_mem_miso;
+ signal data_arr : out t_slv_32_arr) is
constant c_offset : natural := 0;
constant c_nof_data : natural := data_arr'length;
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index f07dd4db303e5d24c65f76b4c677f1a9cc2c8085..b64358836e9a75d2f2e1f057974fdfd5e7900637 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_multiplexer.vhd and common_demultiplexer.vhd
-- Usage:
@@ -109,7 +109,7 @@ begin
-- . selection
in_sel <= INCR_UVEC(in_sel, 1) when rising_edge(clk) and TO_UINT(in_sel) < g_nof_streams - 1 else
- TO_UVEC(0, c_sel_w) when rising_edge(clk); -- periodic selection over all demultiplexer output and multiplexer input streams
+ TO_UVEC(0, c_sel_w) when rising_edge(clk); -- periodic selection over all demultiplexer output and multiplexer input streams
-- . verification
p_verify_en : process
@@ -127,59 +127,59 @@ begin
-- . Demultiplex single input to output[in_sel]
u_demux : entity work.common_demultiplexer
- generic map (
- g_pipeline_in => g_pipeline_demux_in,
- g_pipeline_out => g_pipeline_demux_out,
- g_nof_out => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map(
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
-
- out_sel => in_sel,
- out_dat => demux_dat_vec,
- out_val => demux_val_vec
- );
+ generic map (
+ g_pipeline_in => g_pipeline_demux_in,
+ g_pipeline_out => g_pipeline_demux_out,
+ g_nof_out => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+
+ out_sel => in_sel,
+ out_dat => demux_dat_vec,
+ out_val => demux_val_vec
+ );
-- . pipeline in_sel to align demux_sel to demux_*_vec
u_pipe_sel : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_pipeline_demux,
- g_in_dat_w => c_sel_w,
- g_out_dat_w => c_sel_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sel,
- out_dat => demux_sel
- );
+ generic map (
+ g_pipeline => c_pipeline_demux,
+ g_in_dat_w => c_sel_w,
+ g_out_dat_w => c_sel_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sel,
+ out_dat => demux_sel
+ );
demux_val <= demux_val_vec(TO_UINT(demux_sel));
-- . Multiplex input[demux_sel] back to a single output
u_mux : entity work.common_multiplexer
- generic map (
- g_pipeline_in => g_pipeline_mux_in,
- g_pipeline_out => g_pipeline_mux_out,
- g_nof_in => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_sel => demux_sel,
- in_dat => demux_dat_vec,
- in_val => demux_val,
-
- out_dat => out_dat,
- out_val => out_val
- );
+ generic map (
+ g_pipeline_in => g_pipeline_mux_in,
+ g_pipeline_out => g_pipeline_mux_out,
+ g_nof_in => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_sel => demux_sel,
+ in_dat => demux_dat_vec,
+ in_val => demux_val,
+
+ out_dat => out_dat,
+ out_val => out_val
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 255bb24dd4a17b7baa968cc131b13373a62edccf..b275d6984b79667e92bae42824bd38d88fd59e90 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -29,11 +29,11 @@
-- not equal
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_operation_tree is
generic (
@@ -52,9 +52,9 @@ architecture tb of tb_common_operation_tree is
constant c_data_vec_w : natural := g_nof_inputs * c_dat_w;
constant c_nof_stages : natural := ceil_log2(g_nof_inputs);
- constant c_smax : integer := 2**(c_dat_w - 1) - 1;
- constant c_smin : integer := -2**(c_dat_w - 1);
- constant c_umax : integer := 2**c_dat_w - 1;
+ constant c_smax : integer := 2 ** (c_dat_w - 1) - 1;
+ constant c_smin : integer := -2 ** (c_dat_w - 1);
+ constant c_umax : integer := 2 ** c_dat_w - 1;
constant c_umin : integer := 0;
constant c_pipeline_tree : natural := g_pipeline * c_nof_stages / g_pipeline_mod;
@@ -149,19 +149,19 @@ begin
-- . Pipeline the in_data_vec to align with the result
-- . Map the concatenated dat in in_data_vec into an in_data_arr_p array
u_data_vec_p : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_data_vec_w,
- g_out_dat_w => c_data_vec_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => in_data_vec_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_data_vec_w,
+ g_out_dat_w => c_data_vec_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => in_data_vec_p
+ );
p_data_arr : process(in_data_vec_p)
begin
@@ -173,47 +173,47 @@ begin
expected_comb <= func_result(g_operation, g_representation, in_data_vec);
u_result : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0,
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => expected_comb,
- out_dat => expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0,
+ g_in_dat_w => c_dat_w,
+ g_out_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => expected_comb,
+ out_dat => expected
+ );
u_expected_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline_tree,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => expected_val
- );
+ generic map (
+ g_pipeline => c_pipeline_tree,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => expected_val
+ );
dut : entity work.common_operation_tree
- generic map (
- g_operation => g_operation,
- g_representation => g_representation,
- g_pipeline => g_pipeline,
- g_pipeline_mod => g_pipeline_mod,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- in_data_vec => in_data_vec,
- in_en_vec => in_en_vec,
- result => result
- );
+ generic map (
+ g_operation => g_operation,
+ g_representation => g_representation,
+ g_pipeline => g_pipeline,
+ g_pipeline_mod => g_pipeline_mod,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => in_data_vec,
+ in_en_vec => in_en_vec,
+ result => result
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
index 05e526c6838c9c5742008eeaac54cc7af1a214df..aa82a865d70458ce3480c72b4d3fa2435a405d06 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
@@ -18,9 +18,9 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Test bench for common_paged_ram_cr_cw
-- Reference:
-- Based on tb_common_paged_ram_crw_crw.vhd
@@ -34,10 +34,10 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_paged_ram_cr_cw is
end tb_common_paged_ram_cr_cw;
@@ -125,91 +125,91 @@ begin
end process;
u_dut_mux : entity work.common_paged_ram_cr_cw
- generic map (
- g_str => "use_mux",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_wr_start_page => c_wr_start_page,
- g_rd_start_page => c_rd_start_page
- )
- port map (
- -- Write port clock domain
- wr_rst => rst,
- wr_clk => clk,
- wr_clken => '1',
- wr_next_page => wr_next_page,
- wr_adr => wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- -- Read port clock domain
- rd_rst => rst,
- rd_clk => clk,
- rd_clken => '1',
- rd_next_page => rd_next_page,
- rd_adr => rd_adr,
- rd_en => rd_en,
- rd_dat => mux_rd_dat,
- rd_val => mux_rd_val
- );
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => mux_rd_dat,
+ rd_val => mux_rd_val
+ );
u_dut_adr : entity work.common_paged_ram_cr_cw
- generic map (
- g_str => "use_adr",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_wr_start_page => c_wr_start_page,
- g_rd_start_page => c_rd_start_page
- )
- port map (
- -- Write port clock domain
- wr_rst => rst,
- wr_clk => clk,
- wr_clken => '1',
- wr_next_page => wr_next_page,
- wr_adr => wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- -- Read port clock domain
- rd_rst => rst,
- rd_clk => clk,
- rd_clken => '1',
- rd_next_page => rd_next_page,
- rd_adr => rd_adr,
- rd_en => rd_en,
- rd_dat => adr_rd_dat,
- rd_val => adr_rd_val
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => adr_rd_dat,
+ rd_val => adr_rd_val
+ );
u_dut_ofs : entity work.common_paged_ram_cr_cw
- generic map (
- g_str => "use_ofs",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_wr_start_page => c_wr_start_page,
- g_rd_start_page => c_rd_start_page
- )
- port map (
- -- Write port clock domain
- wr_rst => rst,
- wr_clk => clk,
- wr_clken => '1',
- wr_next_page => wr_next_page,
- wr_adr => wr_adr,
- wr_en => wr_en,
- wr_dat => wr_dat,
- -- Read port clock domain
- rd_rst => rst,
- rd_clk => clk,
- rd_clken => '1',
- rd_next_page => rd_next_page,
- rd_adr => rd_adr,
- rd_en => rd_en,
- rd_dat => ofs_rd_dat,
- rd_val => ofs_rd_val
- );
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_wr_start_page => c_wr_start_page,
+ g_rd_start_page => c_rd_start_page
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_clken => '1',
+ wr_next_page => wr_next_page,
+ wr_adr => wr_adr,
+ wr_en => wr_en,
+ wr_dat => wr_dat,
+ -- Read port clock domain
+ rd_rst => rst,
+ rd_clk => clk,
+ rd_clken => '1',
+ rd_next_page => rd_next_page,
+ rd_adr => rd_adr,
+ rd_en => rd_en,
+ rd_dat => ofs_rd_dat,
+ rd_val => ofs_rd_val
+ );
-- Verify that the read data is incrementing data
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val, mux_rd_dat, prev_mux_rd_dat);
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index ae4a886e08c4f51afa526f2c194d00ee358f71be..8b584f81a7b0aa07e7086b00cdae7e7aeedb08af 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_paged_ram_crw_crw
--
@@ -123,100 +123,100 @@ begin
end process;
u_dut_mux : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_mux",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => mux_rd_dat_b,
- rd_val_b => mux_rd_val_b
- );
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => mux_rd_dat_b,
+ rd_val_b => mux_rd_val_b
+ );
u_dut_adr : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_adr",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => adr_rd_dat_b,
- rd_val_b => adr_rd_val_b
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => adr_rd_dat_b,
+ rd_val_b => adr_rd_val_b
+ );
u_dut_ofs : entity work.common_paged_ram_crw_crw
- generic map (
- g_str => "use_ofs",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst_a => rst,
- rst_b => rst,
- clk_a => clk,
- clk_b => clk,
- clken_a => '1',
- clken_b => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => ofs_rd_dat_b,
- rd_val_b => ofs_rd_val_b
- );
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst_a => rst,
+ rst_b => rst,
+ clk_a => clk,
+ clk_b => clk,
+ clken_a => '1',
+ clken_b => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => ofs_rd_dat_b,
+ rd_val_b => ofs_rd_val_b
+ );
-- Verify that the read data is incrementing data
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
index 2de05fffb45fc79828ab8ff58ced5d5406787234..580d01f54bafc9be36a8529312d0f2f4d8ad6eee 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
@@ -18,9 +18,9 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Test bench for common_paged_ram_rw_rw
-- Reference:
-- Based on tb_common_paged_ram_crw_crw.vhd
@@ -34,10 +34,10 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_paged_ram_rw_rw is
end tb_common_paged_ram_rw_rw;
@@ -125,91 +125,91 @@ begin
end process;
u_dut_mux : entity work.common_paged_ram_rw_rw
- generic map (
- g_str => "use_mux",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => mux_rd_dat_b,
- rd_val_b => mux_rd_val_b
- );
+ generic map (
+ g_str => "use_mux",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => mux_rd_dat_b,
+ rd_val_b => mux_rd_val_b
+ );
u_dut_adr : entity work.common_paged_ram_rw_rw
- generic map (
- g_str => "use_adr",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => adr_rd_dat_b,
- rd_val_b => adr_rd_val_b
- );
+ generic map (
+ g_str => "use_adr",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => adr_rd_dat_b,
+ rd_val_b => adr_rd_val_b
+ );
u_dut_ofs : entity work.common_paged_ram_rw_rw
- generic map (
- g_str => "use_ofs",
- g_data_w => c_data_w,
- g_nof_pages => c_nof_pages,
- g_page_sz => c_page_sz,
- g_start_page_a => c_start_page_a,
- g_start_page_b => c_start_page_b
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- next_page_a => next_page_a,
- adr_a => adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- rd_en_a => '0',
- rd_dat_a => OPEN,
- rd_val_a => OPEN,
- next_page_b => next_page_b,
- adr_b => adr_b,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- rd_en_b => rd_en_b,
- rd_dat_b => ofs_rd_dat_b,
- rd_val_b => ofs_rd_val_b
- );
+ generic map (
+ g_str => "use_ofs",
+ g_data_w => c_data_w,
+ g_nof_pages => c_nof_pages,
+ g_page_sz => c_page_sz,
+ g_start_page_a => c_start_page_a,
+ g_start_page_b => c_start_page_b
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ next_page_a => next_page_a,
+ adr_a => adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ rd_en_a => '0',
+ rd_dat_a => OPEN,
+ rd_val_a => OPEN,
+ next_page_b => next_page_b,
+ adr_b => adr_b,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ rd_en_b => rd_en_b,
+ rd_dat_b => ofs_rd_dat_b,
+ rd_val_b => ofs_rd_val_b
+ );
-- Verify that the read data is incrementing data
proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
index 5b632a2f4c0e81444eba462f60002dd8d5d24a98..475581616510f4b8afea0845e04b63fc241493ef 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench for common_paged_ram_ww_rr
-- Description:
@@ -131,7 +131,7 @@ begin
wr_adr_a <= in_adr;
wr_en_b <= '0' when in_mod_adr = g_page_sz - 1 and g_page_sz mod 2 = 1 else -- do not write at last address in case of odd g_page_sz
- in_en when in_mod_adr mod 2 = 0 else '0'; -- use port b to write the odd addresses
+ in_en when in_mod_adr mod 2 = 0 else '0'; -- use port b to write the odd addresses
wr_dat_b <= INCR_UVEC(in_dat, 1);
wr_adr_b <= TO_UVEC((TO_UINT(in_adr) + 1) mod g_page_sz, c_addr_w);
@@ -182,66 +182,66 @@ begin
-- Double write - double read
u_dut_ww_rr : entity work.common_paged_ram_ww_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr_a => wr_adr_a,
- wr_en_a => wr_en_a,
- wr_dat_a => wr_dat_a,
- wr_adr_b => wr_adr_b,
- wr_en_b => wr_en_b,
- wr_dat_b => wr_dat_b,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wwrr_rd_dat_a,
- rd_val_a => wwrr_rd_val_a,
- rd_dat_b => wwrr_rd_dat_b,
- rd_val_b => wwrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr_a => wr_adr_a,
+ wr_en_a => wr_en_a,
+ wr_dat_a => wr_dat_a,
+ wr_adr_b => wr_adr_b,
+ wr_en_b => wr_en_b,
+ wr_dat_b => wr_dat_b,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wwrr_rd_dat_a,
+ rd_val_a => wwrr_rd_val_a,
+ rd_dat_b => wwrr_rd_dat_b,
+ rd_val_b => wwrr_rd_val_b
+ );
-- Single write - double read
u_dut_w_rr : entity work.common_paged_ram_w_rr
- generic map (
- g_pipeline_in => g_pipeline_in,
- g_pipeline_out => g_pipeline_out,
- g_data_w => c_data_w,
- g_page_sz => g_page_sz
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- next page control
- next_page => next_page,
- -- double write access to one page
- wr_adr => in_adr,
- wr_en => in_en,
- wr_dat => in_dat,
- -- double read access from the other one page
- rd_adr_a => rd_adr_a,
- rd_en_a => rd_en_a,
- rd_adr_b => rd_adr_b,
- rd_en_b => rd_en_b,
- -- double read data from the other one page after c_rd_latency
- rd_dat_a => wrr_rd_dat_a,
- rd_val_a => wrr_rd_val_a,
- rd_dat_b => wrr_rd_dat_b,
- rd_val_b => wrr_rd_val_b
- );
+ generic map (
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_out => g_pipeline_out,
+ g_data_w => c_data_w,
+ g_page_sz => g_page_sz
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- next page control
+ next_page => next_page,
+ -- double write access to one page
+ wr_adr => in_adr,
+ wr_en => in_en,
+ wr_dat => in_dat,
+ -- double read access from the other one page
+ rd_adr_a => rd_adr_a,
+ rd_en_a => rd_en_a,
+ rd_adr_b => rd_adr_b,
+ rd_en_b => rd_en_b,
+ -- double read data from the other one page after c_rd_latency
+ rd_dat_a => wrr_rd_dat_a,
+ rd_val_a => wrr_rd_val_a,
+ rd_dat_b => wrr_rd_dat_b,
+ rd_val_b => wrr_rd_val_b
+ );
------------------------------------------------------------------------------
-- Verify
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index de11904870898ab5668afb9fe86fa7601b1e149f..7901cb02caabe7d3b81a04e81219f57a1d107433 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -30,11 +30,11 @@
-- . More information can be found in the comments near the code.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all; -- for boolean, integer file IO
-use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all; -- for boolean, integer file IO
+ use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
+ use work.common_pkg.all;
package tb_common_pkg is
-- Constants
@@ -47,282 +47,337 @@ package tb_common_pkg is
constant c_common_cross_clock_domain_latency : natural := 20;
-- Wait for some time or until
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real);
-
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural);
-
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer);
-
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
-
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector);
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in real);
+
+ procedure proc_common_wait_some_cycles(
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural);
+
+ procedure proc_common_wait_some_pulses(
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural);
+
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_evt(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_high(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_high(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_low(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_clk_and_low(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_hi_lo(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_lo_hi(
+ signal clk : in std_logic;
+ signal level : in std_logic);
+
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer);
+
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
+
+ procedure proc_common_wait_until_value(
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector);
-- Wait until absolute simulation time NOW = c_time
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time);
+ procedure proc_common_wait_until_time(
+ signal clk : in std_logic;
+ constant c_time : in time);
-- Exit simulation on timeout failure
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic);
+ procedure proc_common_timeout_failure(
+ constant c_timeout : in time;
+ signal tb_end : in std_logic);
-- Stop simulation using severity FAILURE when g_tb_end=TRUE, else for use in multi tb report as severity NOTE
procedure proc_common_stop_simulation(signal tb_end : in std_logic);
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural; -- latency between tb_done and tb_)end
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural; -- latency between tb_done and tb_)end
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic);
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic);
-- Handle stream ready signal, only support ready latency c_rl = 0 or 1.
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '1' then active output when ready
- signal ready : in std_logic;
- signal out_valid : out std_logic);
+ procedure proc_common_ready_latency(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '1' then active output when ready
+ signal ready : in std_logic;
+ signal out_valid : out std_logic);
-- Wait for clock domain crossing latency, e.g. for MM readback after MM write
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural);
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time);
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time);
-- Generate a single active, inactive pulse
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a single '1', '0' pulse
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic);
+ procedure proc_common_gen_pulse(
+ signal clk : in std_logic;
+ signal pulse : out std_logic);
-- Generate a periodic pulse with arbitrary duty cycle
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
-
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- once enabled, the pulse remains enabled
- signal pulse : out std_logic);
+ procedure proc_common_gen_duty_pulse( -- delay pulse for nof_clk after enable
+ constant c_delay : in natural;
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
+
+ procedure proc_common_gen_duty_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- once enabled, the pulse remains enabled
+ signal pulse : out std_logic);
-- Generate counter data with valid and arbitrary increment or fixed increment=1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
-
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic);
+ procedure proc_common_gen_data( -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_rl : in natural;
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
+
+ procedure proc_common_gen_data( -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_rl : in natural;
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic);
-- Generate frame control
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic);
-
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
-
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic);
-
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic);
+ procedure proc_common_sop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic);
+
+ procedure proc_common_eop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
+
+ procedure proc_common_val(
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_val_duty(
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic);
+
+ procedure proc_common_eop_flush(
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic);
-- Verify the DUT output incrementing data, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_common_verify_data(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT output valid for ready latency, only support ready latency c_rl = 0 or 1.
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic);
+ procedure proc_common_verify_valid(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic);
-- Verify the DUT input to output latency for SL ctrl signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic);
+ procedure proc_common_verify_latency( -- e.g. "valid", "sop", "eop"
+ constant c_str : in string;
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic);
-- Verify the DUT input to output latency for SLV data signals
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector);
+ procedure proc_common_verify_latency( -- e.g. "data"
+ constant c_str : in string;
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector);
-- Verify the expected value, e.g. to check that a test has ran at all
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector);
+ procedure proc_common_verify_value(
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector);
-- open, read line, close file
- procedure proc_common_open_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector);
-
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string);
-
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT);
-
- -- read entire file
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr);
-
- procedure proc_common_read_mif_file(file_name : in string;
- signal return_array : out t_integer_arr);
+ procedure proc_common_open_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector);
+
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string);
+
+ procedure proc_common_close_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT);
+
+ -- read entire file
+ procedure proc_common_read_integer_file(
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr);
+
+ procedure proc_common_read_mif_file(
+ file_name : in string;
+ signal return_array : out t_integer_arr);
-- Complex multiply function with conjugate option for input b
function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector;
@@ -340,21 +395,24 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some clock cycles
------------------------------------------------------------------------------
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in natural) is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in real) is
+ procedure proc_common_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in real) is
begin
proc_common_wait_some_cycles(clk, natural(c_nof_cycles));
end proc_common_wait_some_cycles;
- procedure proc_common_wait_some_cycles(signal clk_in : in std_logic;
- signal clk_out : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_common_wait_some_cycles(
+ signal clk_in : in std_logic;
+ signal clk_out : in std_logic;
+ c_nof_cycles : in natural) is
begin
proc_common_wait_some_cycles(clk_in, c_nof_cycles);
proc_common_wait_some_cycles(clk_out, c_nof_cycles);
@@ -363,9 +421,10 @@ package body tb_common_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait some pulses
------------------------------------------------------------------------------
- procedure proc_common_wait_some_pulses(signal clk : in std_logic;
- signal pulse : in std_logic;
- c_nof_pulses : in natural) is
+ procedure proc_common_wait_some_pulses(
+ signal clk : in std_logic;
+ signal pulse : in std_logic;
+ c_nof_pulses : in natural) is
begin
for I in 0 to c_nof_pulses - 1 loop
proc_common_wait_until_hi_lo(clk, pulse);
@@ -378,8 +437,9 @@ package body tb_common_pkg is
-- PROCEDURE: Wait until the level input is low
-- PROCEDURE: Wait until the input is equal to c_value
------------------------------------------------------------------------------
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
begin
wait until rising_edge(clk);
@@ -389,8 +449,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_evt(
+ signal clk : in std_logic;
+ signal level : in integer) is
variable v_level : integer := level;
begin
wait until rising_edge(clk);
@@ -400,9 +461,10 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_evt(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_evt(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
variable v_level : std_logic := level;
variable v_I : natural := 0;
begin
@@ -418,23 +480,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_evt;
- procedure proc_common_wait_until_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
wait until rising_edge(clk) and level = '1';
end if;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_clk_and_high(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_high(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '1';
end proc_common_wait_until_clk_and_high;
- procedure proc_common_wait_until_high(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_high(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '1' then
@@ -448,23 +513,26 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_high;
- procedure proc_common_wait_until_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
wait until rising_edge(clk) and level = '0';
end if;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_clk_and_low(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_clk_and_low(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
wait until rising_edge(clk) and level = '0';
end proc_common_wait_until_clk_and_low;
- procedure proc_common_wait_until_low(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_low(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
for I in 0 to c_timeout - 1 loop
if level = '0' then
@@ -478,8 +546,9 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_low;
- procedure proc_common_wait_until_hi_lo(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(clk, level);
@@ -487,9 +556,10 @@ package body tb_common_pkg is
proc_common_wait_until_low(clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_hi_lo(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_hi_lo(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '1' then
proc_common_wait_until_high(c_timeout, clk, level);
@@ -497,8 +567,9 @@ package body tb_common_pkg is
proc_common_wait_until_low(c_timeout, clk, level);
end proc_common_wait_until_hi_lo;
- procedure proc_common_wait_until_lo_hi(signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi(
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(clk, level);
@@ -506,9 +577,10 @@ package body tb_common_pkg is
proc_common_wait_until_high(clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_lo_hi(constant c_timeout : in natural;
- signal clk : in std_logic;
- signal level : in std_logic) is
+ procedure proc_common_wait_until_lo_hi(
+ constant c_timeout : in natural;
+ signal clk : in std_logic;
+ signal level : in std_logic) is
begin
if level /= '0' then
proc_common_wait_until_low(c_timeout, clk, level);
@@ -516,28 +588,31 @@ package body tb_common_pkg is
proc_common_wait_until_high(c_timeout, clk, level);
end proc_common_wait_until_lo_hi;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in integer) is
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in integer) is
begin
while level /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value(
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
while signed(level) /= c_value loop
wait until rising_edge(clk);
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_value(constant c_timeout : in natural;
- constant c_value : in integer;
- signal clk : in std_logic;
- signal level : in std_logic_vector) is
+ procedure proc_common_wait_until_value(
+ constant c_timeout : in natural;
+ constant c_value : in integer;
+ signal clk : in std_logic;
+ signal level : in std_logic_vector) is
begin
for I in 0 to c_timeout - 1 loop
if signed(level) = c_value then
@@ -551,16 +626,18 @@ package body tb_common_pkg is
end loop;
end proc_common_wait_until_value;
- procedure proc_common_wait_until_time(signal clk : in std_logic;
- constant c_time : in time) is
+ procedure proc_common_wait_until_time(
+ signal clk : in std_logic;
+ constant c_time : in time) is
begin
while NOW < c_time loop
wait until rising_edge(clk);
end loop;
end procedure;
- procedure proc_common_timeout_failure(constant c_timeout : in time;
- signal tb_end : in std_logic) is
+ procedure proc_common_timeout_failure(
+ constant c_timeout : in time;
+ signal tb_end : in std_logic) is
begin
while tb_end = '0' loop
assert NOW < c_timeout report "Test bench timeout." severity ERROR;
@@ -570,65 +647,83 @@ package body tb_common_pkg is
end procedure;
procedure proc_common_stop_simulation(signal tb_end : in std_logic) is
- begin
- wait until tb_end = '1';
- -- For modelsim_regression_test_vhdl.py:
- -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
- -- stop the simulation using failure, without causing the test to fail.
- wait for 1 ns;
- report "Tb simulation finished." severity FAILURE;
- wait;
- end procedure;
-
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- constant g_latency : in natural;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
- begin
- -- Wait until simulation indicates done
- proc_common_wait_until_high(clk, tb_done);
-
- -- Wait some more cycles
- proc_common_wait_some_cycles(clk, g_latency);
-
- -- Stop the simulation or only report NOTE
- tb_end <= '1';
- -- For modelsim_regression_test_vhdl.py:
- -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
- -- stop the simulation using failure, without causing the test to fail.
- wait for 1 ns;
- if g_tb_end = false then
- report "Tb Simulation finished." severity NOTE;
- else
- report "Tb Simulation finished." severity FAILURE;
- end if;
- wait;
- end procedure;
-
- procedure proc_common_stop_simulation(constant g_tb_end : in boolean;
- signal clk : in std_logic;
- signal tb_done : in std_logic;
- signal tb_end : out std_logic) is
- begin
- proc_common_stop_simulation(g_tb_end, 0, clk, tb_done, tb_end);
- end procedure;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Handle stream ready signal for data valid
- -- . output active when ready='1' and enable='1'
- -- . only support ready latency c_rl = 0 or 1
- ------------------------------------------------------------------------------
- procedure proc_common_ready_latency(constant c_rl : in natural;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal ready : in std_logic;
- signal out_valid : out std_logic) is
- begin
- -- skip ready cycles until enable='1'
- out_valid <= '0';
- while enable = '0' loop
+ begin
+ wait until tb_end = '1';
+ -- For modelsim_regression_test_vhdl.py:
+ -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
+ -- stop the simulation using failure, without causing the test to fail.
+ wait for 1 ns;
+ report "Tb simulation finished." severity FAILURE;
+ wait;
+ end procedure;
+
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ constant g_latency : in natural;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
+ begin
+ -- Wait until simulation indicates done
+ proc_common_wait_until_high(clk, tb_done);
+
+ -- Wait some more cycles
+ proc_common_wait_some_cycles(clk, g_latency);
+
+ -- Stop the simulation or only report NOTE
+ tb_end <= '1';
+ -- For modelsim_regression_test_vhdl.py:
+ -- The tb_end will stop the test verification bases on error or failure. The wait is necessary to
+ -- stop the simulation using failure, without causing the test to fail.
+ wait for 1 ns;
+ if g_tb_end = false then
+ report "Tb Simulation finished." severity NOTE;
+ else
+ report "Tb Simulation finished." severity FAILURE;
+ end if;
+ wait;
+ end procedure;
+
+ procedure proc_common_stop_simulation(
+ constant g_tb_end : in boolean;
+ signal clk : in std_logic;
+ signal tb_done : in std_logic;
+ signal tb_end : out std_logic) is
+ begin
+ proc_common_stop_simulation(g_tb_end, 0, clk, tb_done, tb_end);
+ end procedure;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Handle stream ready signal for data valid
+ -- . output active when ready='1' and enable='1'
+ -- . only support ready latency c_rl = 0 or 1
+ ------------------------------------------------------------------------------
+ procedure proc_common_ready_latency(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : out std_logic) is
+ begin
+ -- skip ready cycles until enable='1'
+ out_valid <= '0';
+ while enable = '0' loop
+ if c_rl = 0 then
+ wait until rising_edge(clk);
+ while ready /= '1' loop
+ wait until rising_edge(clk);
+ end loop;
+ end if;
+ if c_rl = 1 then
+ while ready /= '1' loop
+ wait until rising_edge(clk);
+ end loop;
+ wait until rising_edge(clk);
+ end if;
+ end loop;
+ -- active output when ready
if c_rl = 0 then
+ out_valid <= '1';
wait until rising_edge(clk);
while ready /= '1' loop
wait until rising_edge(clk);
@@ -636,796 +731,811 @@ package body tb_common_pkg is
end if;
if c_rl = 1 then
while ready /= '1' loop
+ out_valid <= '0';
wait until rising_edge(clk);
end loop;
+ out_valid <= '1';
wait until rising_edge(clk);
end if;
- end loop;
- -- active output when ready
- if c_rl = 0 then
- out_valid <= '1';
- wait until rising_edge(clk);
- while ready /= '1' loop
- wait until rising_edge(clk);
- end loop;
- end if;
- if c_rl = 1 then
- while ready /= '1' loop
- out_valid <= '0';
- wait until rising_edge(clk);
- end loop;
- out_valid <= '1';
- wait until rising_edge(clk);
- end if;
- end proc_common_ready_latency;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Wait for clock domain crossing latency, e.g. for MM readback after MM write
- ------------------------------------------------------------------------------
-
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic;
- constant c_nof_cycles : in natural) is
- begin
- proc_common_wait_some_cycles(mm_clk, c_nof_cycles);
- proc_common_wait_some_cycles(st_clk, c_nof_cycles);
- end proc_common_wait_cross_clock_domain_latency;
-
- procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
- signal st_clk : in std_logic) is
- begin
- proc_common_wait_some_cycles(mm_clk, c_common_cross_clock_domain_latency);
- proc_common_wait_some_cycles(st_clk, c_common_cross_clock_domain_latency);
- end proc_common_wait_cross_clock_domain_latency;
-
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time;
- constant c_nof_cycles : in natural) is
- begin
- wait for c_nof_cycles * c_mm_clk_period;
- wait for c_nof_cycles * c_st_clk_period;
- end proc_common_wait_cross_clock_domain_latency;
-
- procedure proc_common_wait_cross_clock_domain_latency(constant c_mm_clk_period : in time;
- constant c_st_clk_period : in time) is
- begin
- wait for c_common_cross_clock_domain_latency * c_mm_clk_period;
- wait for c_common_cross_clock_domain_latency * c_st_clk_period;
- end proc_common_wait_cross_clock_domain_latency;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Generate a single active, inactive pulse
- ------------------------------------------------------------------------------
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal clk : in std_logic;
- signal pulse : out std_logic) is
- variable v_cnt : natural range 0 to c_period := 0;
- begin
- while v_cnt < c_period loop
- if v_cnt < c_active then
- pulse <= c_level;
- else
- pulse <= not c_level;
- end if;
- v_cnt := v_cnt + 1;
- wait until rising_edge(clk);
- end loop;
- end proc_common_gen_pulse;
-
- -- Pulse forever after rst was released
- procedure proc_common_gen_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal pulse : out std_logic) is
- variable v_cnt : natural range 0 to c_period := 0;
- begin
- pulse <= not c_level;
- if rst = '0' then
- wait until rising_edge(clk);
- while true loop
- proc_common_gen_pulse(c_active, c_period, c_level, clk, pulse);
- end loop;
- end if;
- end proc_common_gen_pulse;
-
- -- pulse '1', '0'
- procedure proc_common_gen_pulse(signal clk : in std_logic;
- signal pulse : out std_logic) is
- begin
- proc_common_gen_pulse(1, 2, '1', clk, pulse);
- end proc_common_gen_pulse;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Generate a periodic pulse with arbitrary duty cycle
- ------------------------------------------------------------------------------
- procedure proc_common_gen_duty_pulse(constant c_delay : in natural; -- delay pulse for nof_clk after enable
- constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
- variable v_cnt : natural range 0 to c_period - 1 := 0;
- begin
- pulse <= not c_level;
- if rst = '0' then
- proc_common_wait_until_high(clk, enable); -- if enabled then continue immediately else wait here
- proc_common_wait_some_cycles(clk, c_delay); -- apply initial c_delay. Once enabled, the pulse remains enabled
- while true loop
- wait until rising_edge(clk);
+ end proc_common_ready_latency;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Wait for clock domain crossing latency, e.g. for MM readback after MM write
+ ------------------------------------------------------------------------------
+
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic;
+ constant c_nof_cycles : in natural) is
+ begin
+ proc_common_wait_some_cycles(mm_clk, c_nof_cycles);
+ proc_common_wait_some_cycles(st_clk, c_nof_cycles);
+ end proc_common_wait_cross_clock_domain_latency;
+
+ procedure proc_common_wait_cross_clock_domain_latency(
+ signal mm_clk : in std_logic;
+ signal st_clk : in std_logic) is
+ begin
+ proc_common_wait_some_cycles(mm_clk, c_common_cross_clock_domain_latency);
+ proc_common_wait_some_cycles(st_clk, c_common_cross_clock_domain_latency);
+ end proc_common_wait_cross_clock_domain_latency;
+
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time;
+ constant c_nof_cycles : in natural) is
+ begin
+ wait for c_nof_cycles * c_mm_clk_period;
+ wait for c_nof_cycles * c_st_clk_period;
+ end proc_common_wait_cross_clock_domain_latency;
+
+ procedure proc_common_wait_cross_clock_domain_latency(
+ constant c_mm_clk_period : in time;
+ constant c_st_clk_period : in time) is
+ begin
+ wait for c_common_cross_clock_domain_latency * c_mm_clk_period;
+ wait for c_common_cross_clock_domain_latency * c_st_clk_period;
+ end proc_common_wait_cross_clock_domain_latency;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Generate a single active, inactive pulse
+ ------------------------------------------------------------------------------
+ procedure proc_common_gen_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
+ variable v_cnt : natural range 0 to c_period := 0;
+ begin
+ while v_cnt < c_period loop
if v_cnt < c_active then
pulse <= c_level;
else
pulse <= not c_level;
end if;
- if v_cnt < c_period - 1 then
- v_cnt := v_cnt + 1;
- else
- v_cnt := 0;
- end if;
- end loop;
- end if;
- end proc_common_gen_duty_pulse;
-
- procedure proc_common_gen_duty_pulse(constant c_active : in natural; -- pulse active for nof clk
- constant c_period : in natural; -- pulse period for nof clk
- constant c_level : in std_logic; -- pulse level when active
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic;
- signal pulse : out std_logic) is
- begin
- proc_common_gen_duty_pulse(0, c_active, c_period, c_level, rst, clk, enable, pulse);
- end proc_common_gen_duty_pulse;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Generate counter data with valid
- -- . Output counter data dependent on enable and ready
- ------------------------------------------------------------------------------
- -- arbitrary c_incr
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- constant c_incr : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
- constant c_data_w : natural := out_data'length;
- variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_SVEC(c_init, c_data_w);
- begin
- out_valid <= '0';
- out_data <= v_data;
- if rst = '0' then
- wait until rising_edge(clk);
- while true loop
- out_data <= v_data;
- proc_common_ready_latency(c_rl, clk, enable, ready, out_valid);
- v_data := INCR_UVEC(v_data, c_incr);
+ v_cnt := v_cnt + 1;
+ wait until rising_edge(clk);
end loop;
- end if;
- end proc_common_gen_data;
-
- -- c_incr = 1
- procedure proc_common_gen_data(constant c_rl : in natural; -- 0, 1 are supported by proc_common_ready_latency()
- constant c_init : in integer;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
- signal ready : in std_logic;
- signal out_data : out std_logic_vector;
- signal out_valid : out std_logic) is
- begin
- proc_common_gen_data(c_rl, c_init, 1, rst, clk, enable, ready, out_data, out_valid);
- end proc_common_gen_data;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Generate frame control
- ------------------------------------------------------------------------------
- procedure proc_common_sop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_sop : out std_logic) is
- begin
- in_val <= '1';
- in_sop <= '1';
- proc_common_wait_some_cycles(clk, 1);
- in_sop <= '0';
- end proc_common_sop;
-
- procedure proc_common_eop(signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
- begin
- in_val <= '1';
- in_eop <= '1';
- proc_common_wait_some_cycles(clk, 1);
- in_val <= '0';
- in_eop <= '0';
- end proc_common_eop;
-
- procedure proc_common_val(constant c_val_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
- begin
- in_val <= '1';
- proc_common_wait_some_cycles(clk, c_val_len);
- in_val <= '0';
- end proc_common_val;
-
- procedure proc_common_val_duty(constant c_hi_len : in natural;
- constant c_lo_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic) is
- begin
- in_val <= '1';
- proc_common_wait_some_cycles(clk, c_hi_len);
- in_val <= '0';
- proc_common_wait_some_cycles(clk, c_lo_len);
- end proc_common_val_duty;
-
- procedure proc_common_eop_flush(constant c_flush_len : in natural;
- signal clk : in std_logic;
- signal in_val : out std_logic;
- signal in_eop : out std_logic) is
- begin
- -- . eop
- proc_common_eop(clk, in_val, in_eop);
- -- . flush after in_eop to empty the shift register
- proc_common_wait_some_cycles(clk, c_flush_len);
- end proc_common_eop_flush;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Verify incrementing data
- ------------------------------------------------------------------------------
- procedure proc_common_verify_data(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal out_valid : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
- variable v_exp_data : std_logic_vector(out_data'range);
- begin
- if rising_edge(clk) then
- -- out_valid must be active, because only the out_data will it differ from the previous out_data
- if out_valid = '1' then
- -- for ready_latency = 1 out_valid indicates new data
- -- for ready_latency = 0 out_valid only indicates new data when it is confirmed by ready
- if c_rl = 1 or (c_rl = 0 and ready = '1') then
- prev_out_data <= out_data;
- v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
- if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
- report "COMMON : Wrong out_data count" severity ERROR;
+ end proc_common_gen_pulse;
+
+ -- Pulse forever after rst was released
+ procedure proc_common_gen_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
+ variable v_cnt : natural range 0 to c_period := 0;
+ begin
+ pulse <= not c_level;
+ if rst = '0' then
+ wait until rising_edge(clk);
+ while true loop
+ proc_common_gen_pulse(c_active, c_period, c_level, clk, pulse);
+ end loop;
+ end if;
+ end proc_common_gen_pulse;
+
+ -- pulse '1', '0'
+ procedure proc_common_gen_pulse(
+ signal clk : in std_logic;
+ signal pulse : out std_logic) is
+ begin
+ proc_common_gen_pulse(1, 2, '1', clk, pulse);
+ end proc_common_gen_pulse;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Generate a periodic pulse with arbitrary duty cycle
+ ------------------------------------------------------------------------------
+ procedure proc_common_gen_duty_pulse( -- delay pulse for nof_clk after enable
+ constant c_delay : in natural;
+ constant c_active : in natural; -- pulse active for nof clk
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
+ variable v_cnt : natural range 0 to c_period - 1 := 0;
+ begin
+ pulse <= not c_level;
+ if rst = '0' then
+ proc_common_wait_until_high(clk, enable); -- if enabled then continue immediately else wait here
+ proc_common_wait_some_cycles(clk, c_delay); -- apply initial c_delay. Once enabled, the pulse remains enabled
+ while true loop
+ wait until rising_edge(clk);
+ if v_cnt < c_active then
+ pulse <= c_level;
+ else
+ pulse <= not c_level;
+ end if;
+ if v_cnt < c_period - 1 then
+ v_cnt := v_cnt + 1;
+ else
+ v_cnt := 0;
+ end if;
+ end loop;
+ end if;
+ end proc_common_gen_duty_pulse;
+
+ procedure proc_common_gen_duty_pulse( -- pulse active for nof clk
+ constant c_active : in natural;
+ constant c_period : in natural; -- pulse period for nof clk
+ constant c_level : in std_logic; -- pulse level when active
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic;
+ signal pulse : out std_logic) is
+ begin
+ proc_common_gen_duty_pulse(0, c_active, c_period, c_level, rst, clk, enable, pulse);
+ end proc_common_gen_duty_pulse;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Generate counter data with valid
+ -- . Output counter data dependent on enable and ready
+ ------------------------------------------------------------------------------
+ -- arbitrary c_incr
+ procedure proc_common_gen_data( -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_rl : in natural;
+ constant c_init : in integer;
+ constant c_incr : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
+ constant c_data_w : natural := out_data'length;
+ variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_SVEC(c_init, c_data_w);
+ begin
+ out_valid <= '0';
+ out_data <= v_data;
+ if rst = '0' then
+ wait until rising_edge(clk);
+ while true loop
+ out_data <= v_data;
+ proc_common_ready_latency(c_rl, clk, enable, ready, out_valid);
+ v_data := INCR_UVEC(v_data, c_incr);
+ end loop;
+ end if;
+ end proc_common_gen_data;
+
+ -- c_incr = 1
+ procedure proc_common_gen_data( -- 0, 1 are supported by proc_common_ready_latency()
+ constant c_rl : in natural;
+ constant c_init : in integer;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal enable : in std_logic; -- when '0' then no valid output even when ready='1'
+ signal ready : in std_logic;
+ signal out_data : out std_logic_vector;
+ signal out_valid : out std_logic) is
+ begin
+ proc_common_gen_data(c_rl, c_init, 1, rst, clk, enable, ready, out_data, out_valid);
+ end proc_common_gen_data;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Generate frame control
+ ------------------------------------------------------------------------------
+ procedure proc_common_sop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_sop : out std_logic) is
+ begin
+ in_val <= '1';
+ in_sop <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ in_sop <= '0';
+ end proc_common_sop;
+
+ procedure proc_common_eop(
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
+ begin
+ in_val <= '1';
+ in_eop <= '1';
+ proc_common_wait_some_cycles(clk, 1);
+ in_val <= '0';
+ in_eop <= '0';
+ end proc_common_eop;
+
+ procedure proc_common_val(
+ constant c_val_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
+ begin
+ in_val <= '1';
+ proc_common_wait_some_cycles(clk, c_val_len);
+ in_val <= '0';
+ end proc_common_val;
+
+ procedure proc_common_val_duty(
+ constant c_hi_len : in natural;
+ constant c_lo_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic) is
+ begin
+ in_val <= '1';
+ proc_common_wait_some_cycles(clk, c_hi_len);
+ in_val <= '0';
+ proc_common_wait_some_cycles(clk, c_lo_len);
+ end proc_common_val_duty;
+
+ procedure proc_common_eop_flush(
+ constant c_flush_len : in natural;
+ signal clk : in std_logic;
+ signal in_val : out std_logic;
+ signal in_eop : out std_logic) is
+ begin
+ -- . eop
+ proc_common_eop(clk, in_val, in_eop);
+ -- . flush after in_eop to empty the shift register
+ proc_common_wait_some_cycles(clk, c_flush_len);
+ end proc_common_eop_flush;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Verify incrementing data
+ ------------------------------------------------------------------------------
+ procedure proc_common_verify_data(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal out_valid : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
+ variable v_exp_data : std_logic_vector(out_data'range);
+ begin
+ if rising_edge(clk) then
+ -- out_valid must be active, because only the out_data will it differ from the previous out_data
+ if out_valid = '1' then
+ -- for ready_latency = 1 out_valid indicates new data
+ -- for ready_latency = 0 out_valid only indicates new data when it is confirmed by ready
+ if c_rl = 1 or (c_rl = 0 and ready = '1') then
+ prev_out_data <= out_data;
+ v_exp_data := INCR_UVEC(prev_out_data, 1); -- increment first then compare to also support increment wrap around
+ if verify_en = '1' and unsigned(out_data) /= unsigned(v_exp_data) then
+ report "COMMON : Wrong out_data count" severity ERROR;
+ end if;
end if;
end if;
end if;
- end if;
- end proc_common_verify_data;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Verify the DUT output valid
- -- . only support ready latency c_rl = 0 or 1
- ------------------------------------------------------------------------------
- procedure proc_common_verify_valid(constant c_rl : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal ready : in std_logic;
- signal prev_ready : inout std_logic;
- signal out_valid : in std_logic) is
- begin
- if rising_edge(clk) then
- -- for ready latency c_rl = 1 out_valid may only be asserted after ready
- -- for ready latency c_rl = 0 out_valid may always be asserted
- prev_ready <= '0';
- if c_rl = 1 then
- prev_ready <= ready;
- if verify_en = '1' and out_valid = '1' then
- if prev_ready /= '1' then
- report "COMMON : Wrong ready latency between ready and out_valid" severity ERROR;
+ end proc_common_verify_data;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Verify the DUT output valid
+ -- . only support ready latency c_rl = 0 or 1
+ ------------------------------------------------------------------------------
+ procedure proc_common_verify_valid(
+ constant c_rl : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal ready : in std_logic;
+ signal prev_ready : inout std_logic;
+ signal out_valid : in std_logic) is
+ begin
+ if rising_edge(clk) then
+ -- for ready latency c_rl = 1 out_valid may only be asserted after ready
+ -- for ready latency c_rl = 0 out_valid may always be asserted
+ prev_ready <= '0';
+ if c_rl = 1 then
+ prev_ready <= ready;
+ if verify_en = '1' and out_valid = '1' then
+ if prev_ready /= '1' then
+ report "COMMON : Wrong ready latency between ready and out_valid" severity ERROR;
+ end if;
end if;
end if;
end if;
- end if;
- end proc_common_verify_valid;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Verify the DUT input to output latency
- ------------------------------------------------------------------------------
- -- for SL ctrl
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "valid", "sop", "eop"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_ctrl : in std_logic;
- signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
- signal out_ctrl : in std_logic) is
- begin
- if rising_edge(clk) then
- pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1); -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
- if verify_en = '1' then
- if c_latency = 0 then
- if in_ctrl /= out_ctrl then
- report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ end proc_common_verify_valid;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Verify the DUT input to output latency
+ ------------------------------------------------------------------------------
+ -- for SL ctrl
+ procedure proc_common_verify_latency( -- e.g. "valid", "sop", "eop"
+ constant c_str : in string;
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_ctrl : in std_logic;
+ signal pipe_ctrl_vec : inout std_logic_vector; -- range [0:c_latency]
+ signal out_ctrl : in std_logic) is
+ begin
+ if rising_edge(clk) then
+ pipe_ctrl_vec <= in_ctrl & pipe_ctrl_vec(0 to c_latency - 1); -- note: pipe_ctrl_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ if verify_en = '1' then
+ if c_latency = 0 then
+ if in_ctrl /= out_ctrl then
+ report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ end if;
+ else
+ if pipe_ctrl_vec(c_latency - 1) /= out_ctrl then
+ report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ end if;
end if;
- else
- if pipe_ctrl_vec(c_latency - 1) /= out_ctrl then
- report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ end if;
+ end if;
+ end proc_common_verify_latency;
+
+ -- for SLV data
+ procedure proc_common_verify_latency( -- e.g. "data"
+ constant c_str : in string;
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal in_data : in std_logic_vector;
+ signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
+ signal out_data : in std_logic_vector) is
+ constant c_data_w : natural := in_data'length;
+ constant c_data_vec_w : natural := pipe_data_vec'length; -- = (1 + c_latency) * c_data_w
+ begin
+ if rising_edge(clk) then
+ pipe_data_vec <= in_data & pipe_data_vec(0 to c_data_vec_w - c_data_w - 1); -- note: pipe_data_vec(c_latency) is a dummy place holder to avoid [0:-1] range
+ if verify_en = '1' then
+ if c_latency = 0 then
+ if unsigned(in_data) /= unsigned(out_data) then
+ report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ end if;
+ else
+ if unsigned(pipe_data_vec(c_data_vec_w - c_data_w - c_data_w to c_data_vec_w - c_data_w - 1)) /= unsigned(out_data) then
+ report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ end if;
end if;
end if;
end if;
- end if;
- end proc_common_verify_latency;
-
- -- for SLV data
- procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
- constant c_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal in_data : in std_logic_vector;
- signal pipe_data_vec : inout std_logic_vector; -- range [0:(1 + c_latency)*c_data_w-1]
- signal out_data : in std_logic_vector) is
- constant c_data_w : natural := in_data'length;
- constant c_data_vec_w : natural := pipe_data_vec'length; -- = (1 + c_latency) * c_data_w
- begin
- if rising_edge(clk) then
- pipe_data_vec <= in_data & pipe_data_vec(0 to c_data_vec_w - c_data_w - 1); -- note: pipe_data_vec(c_latency) is a dummy place holder to avoid [0:-1] range
- if verify_en = '1' then
- if c_latency = 0 then
- if unsigned(in_data) /= unsigned(out_data) then
- report "COMMON : Wrong zero latency between input " & c_str & " and output " & c_str severity ERROR;
+ end proc_common_verify_latency;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Verify the expected value
+ -- . e.g. to check that a test has ran at all
+ ------------------------------------------------------------------------------
+ procedure proc_common_verify_value(
+ constant mode : in natural;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector) is
+ begin
+ if rising_edge(clk) then
+ if en = '1' then
+ if mode = 0 and unsigned(res) /= unsigned(exp) then
+ report "COMMON : Wrong result value" severity ERROR; -- == (equal)
end if;
- else
- if unsigned(pipe_data_vec(c_data_vec_w - c_data_w - c_data_w to c_data_vec_w - c_data_w - 1)) /= unsigned(out_data) then
- report "COMMON : Wrong latency between input " & c_str & " and output " & c_str severity ERROR;
+ if mode = 1 and unsigned(res) < unsigned(exp) then
+ report "COMMON : Wrong result value too small" severity ERROR; -- >= (at least)
end if;
end if;
end if;
- end if;
- end proc_common_verify_latency;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Verify the expected value
- -- . e.g. to check that a test has ran at all
- ------------------------------------------------------------------------------
- procedure proc_common_verify_value(constant mode : in natural;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector) is
- begin
- if rising_edge(clk) then
- if en = '1' then
- if mode = 0 and unsigned(res) /= unsigned(exp) then
- report "COMMON : Wrong result value" severity ERROR; -- == (equal)
- end if;
- if mode = 1 and unsigned(res) < unsigned(exp) then
- report "COMMON : Wrong result value too small" severity ERROR; -- >= (at least)
- end if;
+ end proc_common_verify_value;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Opens a file for access and reports fail or success of opening.
+ ------------------------------------------------------------------------------
+ procedure proc_common_open_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ file_name : in string;
+ file_mode : in FILE_OPEN_KIND) is
+ begin
+ if file_status = OPEN_OK then
+ file_close(in_file);
end if;
- end if;
- end proc_common_verify_value;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Opens a file for access and reports fail or success of opening.
- ------------------------------------------------------------------------------
- procedure proc_common_open_file( file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- file_name : in string;
- file_mode : in FILE_OPEN_KIND) is
- begin
- if file_status = OPEN_OK then
- file_close(in_file);
- end if;
- file_open (file_status, in_file, file_name, file_mode);
- if file_status = OPEN_OK then
- report "COMMON : file opened " severity NOTE;
- else
- report "COMMON : Unable to open file " severity FAILURE;
- end if;
- end proc_common_open_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads an integer from a file.
- ------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
- else
- if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ file_open (file_status, in_file, file_name, file_mode);
+ if file_status = OPEN_OK then
+ report "COMMON : file opened " severity NOTE;
else
- READLINE(in_file, v_line);
- READ(v_line, read_value_0, v_good);
- if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
- end if;
+ report "COMMON : Unable to open file " severity FAILURE;
end if;
- end if;
- end proc_common_readline_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads two integers from two columns in a file.
- ------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_value_0 : out integer;
- read_value_1 : out integer) is
- variable v_line : LINE;
- variable v_good : boolean;
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
- else
- if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ end proc_common_open_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads an integer from a file.
+ ------------------------------------------------------------------------------
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file is not opened " severity FAILURE;
else
- READLINE(in_file, v_line);
- READ(v_line, read_value_0, v_good);
- if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
- end if;
- READ(v_line, read_value_1, v_good);
- if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ if ENDFILE(in_file) then
+ report "COMMON : end of file " severity NOTE;
+ else
+ READLINE(in_file, v_line);
+ READ(v_line, read_value_0, v_good);
+ if v_good = false then
+ report "COMMON : Read from line unsuccessful " severity FAILURE;
+ end if;
end if;
end if;
- end if;
- end proc_common_readline_file;
-
-------------------------------------------------------------------------------
- -- PROCEDURE: Reads an array of integer from a file.
- ------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- value_array : out t_integer_arr;
- nof_reads : in integer) is
- variable v_line : LINE;
- variable v_good : boolean;
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
- else
- if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ end proc_common_readline_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads two integers from two columns in a file.
+ ------------------------------------------------------------------------------
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_value_0 : out integer;
+ read_value_1 : out integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file is not opened " severity FAILURE;
else
- READLINE(in_file, v_line);
- for I in 0 to nof_reads - 1 loop
- READ(v_line, value_array(I), v_good);
+ if ENDFILE(in_file) then
+ report "COMMON : end of file " severity NOTE;
+ else
+ READLINE(in_file, v_line);
+ READ(v_line, read_value_0, v_good);
if v_good = false then
report "COMMON : Read from line unsuccessful " severity FAILURE;
end if;
- end loop;
+ READ(v_line, read_value_1, v_good);
+ if v_good = false then
+ report "COMMON : Read from line unsuccessful " severity FAILURE;
+ end if;
+ end if;
end if;
- end if;
- end proc_common_readline_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads an std_logic_vector from a file
- ------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- read_slv : out std_logic_vector) is
- variable v_line : LINE;
- variable v_good : boolean;
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
- else
- if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ end proc_common_readline_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads an array of integer from a file.
+ ------------------------------------------------------------------------------
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ value_array : out t_integer_arr;
+ nof_reads : in integer) is
+ variable v_line : LINE;
+ variable v_good : boolean;
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file is not opened " severity FAILURE;
else
- READLINE(in_file, v_line);
- READ(v_line, read_slv, v_good);
- if v_good = false then
- report "COMMON : Read from line unsuccessful " severity FAILURE;
+ if ENDFILE(in_file) then
+ report "COMMON : end of file " severity NOTE;
+ else
+ READLINE(in_file, v_line);
+ for I in 0 to nof_reads - 1 loop
+ READ(v_line, value_array(I), v_good);
+ if v_good = false then
+ report "COMMON : Read from line unsuccessful " severity FAILURE;
+ end if;
+ end loop;
end if;
end if;
- end if;
- end proc_common_readline_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads a string of any length from a file pointer.
- ------------------------------------------------------------------------------
- procedure proc_common_readline_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT;
- res_string : out string) is
- variable v_line : LINE;
- variable v_char : character;
- variable is_string : boolean;
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file is not opened " severity FAILURE;
- else
- if ENDFILE(in_file) then
- report "COMMON : end of file " severity NOTE;
+ end proc_common_readline_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads an std_logic_vector from a file
+ ------------------------------------------------------------------------------
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ read_slv : out std_logic_vector) is
+ variable v_line : LINE;
+ variable v_good : boolean;
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file is not opened " severity FAILURE;
else
- readline(in_file, v_line);
- -- clear the contents of the result string
- for I in res_string'range loop
+ if ENDFILE(in_file) then
+ report "COMMON : end of file " severity NOTE;
+ else
+ READLINE(in_file, v_line);
+ READ(v_line, read_slv, v_good);
+ if v_good = false then
+ report "COMMON : Read from line unsuccessful " severity FAILURE;
+ end if;
+ end if;
+ end if;
+ end proc_common_readline_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads a string of any length from a file pointer.
+ ------------------------------------------------------------------------------
+ procedure proc_common_readline_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT;
+ res_string : out string) is
+ variable v_line : LINE;
+ variable v_char : character;
+ variable is_string : boolean;
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file is not opened " severity FAILURE;
+ else
+ if ENDFILE(in_file) then
+ report "COMMON : end of file " severity NOTE;
+ else
+ readline(in_file, v_line);
+ -- clear the contents of the result string
+ for I in res_string'range loop
res_string(I) := ' ';
- end loop;
- -- read all characters of the line, up to the length
- -- of the results string
- for I in res_string'range loop
- read(v_line, v_char, is_string);
- if not is_string then -- found end of line
+ end loop;
+ -- read all characters of the line, up to the length
+ -- of the results string
+ for I in res_string'range loop
+ read(v_line, v_char, is_string);
+ if not is_string then -- found end of line
exit;
- end if;
- res_string(I) := v_char;
+ end if;
+ res_string(I) := v_char;
+ end loop;
+ end if;
+ end if;
+ end proc_common_readline_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Closes a file.
+ ------------------------------------------------------------------------------
+ procedure proc_common_close_file(
+ file_status : inout FILE_OPEN_STATUS;
+ file in_file : TEXT) is
+ begin
+ if file_status /= OPEN_OK then
+ report "COMMON : file was not opened " severity WARNING;
+ end if;
+ FILE_CLOSE(in_file);
+ report "COMMON : file closed " severity NOTE;
+ end proc_common_close_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads the integer data from nof_rows with nof_col values per
+ -- row from a file and returns it row by row in an array of
+ -- integers.
+ ------------------------------------------------------------------------------
+ procedure proc_common_read_integer_file(
+ file_name : in string;
+ nof_header_lines : natural;
+ nof_row : natural;
+ nof_col : natural;
+ signal return_array : out t_integer_arr) is
+ variable v_file_status : FILE_OPEN_STATUS;
+ file v_in_file : TEXT;
+ variable v_input_line : LINE;
+ variable v_string : string(1 to 80);
+ variable v_row_arr : t_integer_arr(0 to nof_col - 1);
+ begin
+ if file_name /= "UNUSED" and file_name /= "unused" then
+ -- Open the file for reading
+ proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
+ -- Read and skip the header
+ for J in 0 to nof_header_lines - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_string);
end loop;
+ for J in 0 to nof_row - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_row_arr, nof_col);
+ for I in 0 to nof_col - 1 loop
+ return_array(J * nof_col + I) <= v_row_arr(I); -- use loop to be independent of t_integer_arr downto or to range
+ end loop;
+ if ENDFILE(v_in_file) then
+ if J /= nof_row - 1 then
+ report "COMMON : Unexpected end of file" severity FAILURE;
+ end if;
+ exit;
+ end if;
+ end loop;
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
+ else
+ return_array <= (return_array'range => 0);
end if;
- end if;
- end proc_common_readline_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Closes a file.
- ------------------------------------------------------------------------------
- procedure proc_common_close_file(file_status : inout FILE_OPEN_STATUS;
- file in_file : TEXT) is
- begin
- if file_status /= OPEN_OK then
- report "COMMON : file was not opened " severity WARNING;
- end if;
- FILE_CLOSE(in_file);
- report "COMMON : file closed " severity NOTE;
- end proc_common_close_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads the integer data from nof_rows with nof_col values per
- -- row from a file and returns it row by row in an array of
- -- integers.
- ------------------------------------------------------------------------------
- procedure proc_common_read_integer_file(file_name : in string;
- nof_header_lines : natural;
- nof_row : natural;
- nof_col : natural;
- signal return_array : out t_integer_arr) is
- variable v_file_status : FILE_OPEN_STATUS;
- file v_in_file : TEXT;
- variable v_input_line : LINE;
- variable v_string : string(1 to 80);
- variable v_row_arr : t_integer_arr(0 to nof_col - 1);
- begin
- if file_name /= "UNUSED" and file_name /= "unused" then
- -- Open the file for reading
+ end proc_common_read_integer_file;
+
+ ------------------------------------------------------------------------------
+ -- PROCEDURE: Reads the data column from a .mif file and returns it in an
+ -- array of integers
+ ------------------------------------------------------------------------------
+ procedure proc_common_read_mif_file(
+ file_name : in string;
+ signal return_array : out t_integer_arr) is
+ variable v_file_status : FILE_OPEN_STATUS;
+ file v_in_file : TEXT;
+ variable v_input_line : LINE;
+ variable v_string : string(1 to 80);
+ variable v_mem_width : natural := 0;
+ variable v_mem_depth : natural := 0;
+ variable v_up_bound : natural := 0;
+ variable v_low_bound : natural := 0;
+ variable v_end_header : boolean := false;
+ variable v_char : character;
+ begin
+ -- Open the .mif file for reading
proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
- -- Read and skip the header
- for J in 0 to nof_header_lines - 1 loop
+ -- Read the header.
+ while not v_end_header loop
proc_common_readline_file(v_file_status, v_in_file, v_string);
- end loop;
- for J in 0 to nof_row - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_row_arr, nof_col);
- for I in 0 to nof_col - 1 loop
- return_array(J * nof_col + I) <= v_row_arr(I); -- use loop to be independent of t_integer_arr downto or to range
- end loop;
- if ENDFILE(v_in_file) then
- if J /= nof_row - 1 then
- report "COMMON : Unexpected end of file" severity FAILURE;
- end if;
- exit;
- end if;
- end loop;
- -- Close the file
- proc_common_close_file(v_file_status, v_in_file);
- else
- return_array <= (return_array'range => 0);
- end if;
- end proc_common_read_integer_file;
-
- ------------------------------------------------------------------------------
- -- PROCEDURE: Reads the data column from a .mif file and returns it in an
- -- array of integers
- ------------------------------------------------------------------------------
- procedure proc_common_read_mif_file( file_name : in string;
- signal return_array : out t_integer_arr) is
- variable v_file_status : FILE_OPEN_STATUS;
- file v_in_file : TEXT;
- variable v_input_line : LINE;
- variable v_string : string(1 to 80);
- variable v_mem_width : natural := 0;
- variable v_mem_depth : natural := 0;
- variable v_up_bound : natural := 0;
- variable v_low_bound : natural := 0;
- variable v_end_header : boolean := false;
- variable v_char : character;
- begin
- -- Open the .mif file for reading
- proc_common_open_file(v_file_status, v_in_file, file_name, READ_MODE);
- -- Read the header.
- while not v_end_header loop
- proc_common_readline_file(v_file_status, v_in_file, v_string);
- if(func_find_string_in_string(v_string, "WIDTH=")) then -- check for "WIDTH="
+ if(func_find_string_in_string(v_string, "WIDTH=")) then -- check for "WIDTH="
v_up_bound := func_find_char_in_string(v_string, ';');
v_low_bound := func_find_char_in_string(v_string, '=');
v_mem_width := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- elsif(func_find_string_in_string(v_string, "DEPTH=")) then -- check for "DEPTH="
+ elsif(func_find_string_in_string(v_string, "DEPTH=")) then -- check for "DEPTH="
v_up_bound := func_find_char_in_string(v_string, ';');
v_low_bound := func_find_char_in_string(v_string, '=');
v_mem_depth := func_decstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- elsif(func_find_string_in_string(v_string, "CONTENT BEGIN")) then
+ elsif(func_find_string_in_string(v_string, "CONTENT BEGIN")) then
v_end_header := true;
+ end if;
+ end loop;
+ -- Read the data
+ for I in 0 to v_mem_depth - 1 loop
+ proc_common_readline_file(v_file_status, v_in_file, v_string); -- Read the next line from the file.
+ v_low_bound := func_find_char_in_string(v_string, ':'); -- Find the left position of the string that contains the data field
+ v_up_bound := func_find_char_in_string(v_string, ';'); -- Find the right position of the string that contains the data field
+ return_array(I) <= func_hexstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
+ end loop;
+ -- Close the file
+ proc_common_close_file(v_file_status, v_in_file);
+ end proc_common_read_mif_file;
+
+ ------------------------------------------------------------------------------
+ -- FUNCTION: Complex multiply with conjugate option for input b
+ ------------------------------------------------------------------------------
+ function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector is
+ -- Function: Signed complex multiply
+ -- p = a * b when g_conjugate_b = FALSE
+ -- = (ar + j ai) * (br + j bi)
+ -- = ar*br - ai*bi + j ( ar*bi + ai*br)
+ --
+ -- p = a * conj(b) when g_conjugate_b = TRUE
+ -- = (ar + j ai) * (br - j bi)
+ -- = ar*br + ai*bi + j (-ar*bi + ai*br)
+ -- From mti_numeric_std.vhd follows:
+ -- . SIGNED * --> output width = 2 * input width
+ -- . SIGNED + --> output width = largest(input width)
+ constant c_in_w : natural := in_ar'length; -- all input have same width
+ constant c_res_w : natural := 2 * c_in_w + 1; -- *2 for multiply, +1 for sum of two products
+ variable v_ar : signed(c_in_w - 1 downto 0);
+ variable v_ai : signed(c_in_w - 1 downto 0);
+ variable v_br : signed(c_in_w - 1 downto 0);
+ variable v_bi : signed(c_in_w - 1 downto 0);
+ variable v_result_re : signed(c_res_w - 1 downto 0);
+ variable v_result_im : signed(c_res_w - 1 downto 0);
+ begin
+ -- Calculate expected result
+ v_ar := RESIZE_NUM(signed(in_ar), c_in_w);
+ v_ai := RESIZE_NUM(signed(in_ai), c_in_w);
+ v_br := RESIZE_NUM(signed(in_br), c_in_w);
+ v_bi := RESIZE_NUM(signed(in_bi), c_in_w);
+ if conjugate_b = false then
+ v_result_re := RESIZE_NUM(v_ar * v_br, c_res_w) - v_ai * v_bi;
+ v_result_im := RESIZE_NUM(v_ar * v_bi, c_res_w) + v_ai * v_br;
+ else
+ v_result_re := RESIZE_NUM(v_ar * v_br, c_res_w) + v_ai * v_bi;
+ v_result_im := RESIZE_NUM(v_ai * v_br, c_res_w) - v_ar * v_bi;
end if;
- end loop;
- -- Read the data
- for I in 0 to v_mem_depth - 1 loop
- proc_common_readline_file(v_file_status, v_in_file, v_string); -- Read the next line from the file.
- v_low_bound := func_find_char_in_string(v_string, ':'); -- Find the left position of the string that contains the data field
- v_up_bound := func_find_char_in_string(v_string, ';'); -- Find the right position of the string that contains the data field
- return_array(I) <= func_hexstring_to_integer(v_string(v_low_bound + 1 to v_up_bound - 1));
- end loop;
- -- Close the file
- proc_common_close_file(v_file_status, v_in_file);
- end proc_common_read_mif_file;
-
- ------------------------------------------------------------------------------
- -- FUNCTION: Complex multiply with conjugate option for input b
- ------------------------------------------------------------------------------
- function func_complex_multiply(in_ar, in_ai, in_br, in_bi : std_logic_vector; conjugate_b : boolean; str : string; g_out_dat_w : natural) return std_logic_vector is
- -- Function: Signed complex multiply
- -- p = a * b when g_conjugate_b = FALSE
- -- = (ar + j ai) * (br + j bi)
- -- = ar*br - ai*bi + j ( ar*bi + ai*br)
- --
- -- p = a * conj(b) when g_conjugate_b = TRUE
- -- = (ar + j ai) * (br - j bi)
- -- = ar*br + ai*bi + j (-ar*bi + ai*br)
- -- From mti_numeric_std.vhd follows:
- -- . SIGNED * --> output width = 2 * input width
- -- . SIGNED + --> output width = largest(input width)
- constant c_in_w : natural := in_ar'length; -- all input have same width
- constant c_res_w : natural := 2 * c_in_w + 1; -- *2 for multiply, +1 for sum of two products
- variable v_ar : signed(c_in_w - 1 downto 0);
- variable v_ai : signed(c_in_w - 1 downto 0);
- variable v_br : signed(c_in_w - 1 downto 0);
- variable v_bi : signed(c_in_w - 1 downto 0);
- variable v_result_re : signed(c_res_w - 1 downto 0);
- variable v_result_im : signed(c_res_w - 1 downto 0);
- begin
- -- Calculate expected result
- v_ar := RESIZE_NUM(signed(in_ar), c_in_w);
- v_ai := RESIZE_NUM(signed(in_ai), c_in_w);
- v_br := RESIZE_NUM(signed(in_br), c_in_w);
- v_bi := RESIZE_NUM(signed(in_bi), c_in_w);
- if conjugate_b = false then
- v_result_re := RESIZE_NUM(v_ar * v_br, c_res_w) - v_ai * v_bi;
- v_result_im := RESIZE_NUM(v_ar * v_bi, c_res_w) + v_ai * v_br;
- else
- v_result_re := RESIZE_NUM(v_ar * v_br, c_res_w) + v_ai * v_bi;
- v_result_im := RESIZE_NUM(v_ai * v_br, c_res_w) - v_ar * v_bi;
- end if;
- -- Note that for the product needs as many bits as the sum of the input widths. However the
- -- sign bit is then only needed for the case that both inputs have the largest negative
- -- values, only then the MSBits will be "01". For all other inputs the MSbits will always
- -- be "00" for positive numbers or "11" for negative numbers. MSbits "10" can not occur.
- -- For largest negative inputs the complex multiply result becomes:
- --
- -- 3b inputs --> 6b products --> c_res_w = 7b
- -- -4 * -4 + -4 * -4 = +16 + +16 = +64 -- most negative valued inputs
- -- b100 * b100 + b100 * b100 = b010000 + b010000 = b0100000
- --
- -- --> if g_out_dat_w = 6b then
- -- a) IEEE unsigned resizing skips the MSbits so b0100000 = +64 becomes b_100000 = -64
- -- b) IEEE signed resizing preserves the MSbit so b0100000 = +64 becomes b0_00000 = 0
- -- c) detect MSbits = "01" to clip max positive to get _b011111 = +63
- -- Option a) seems to map best on the FPGA hardware multiplier IP.
- if str = "RE" then
- return std_logic_vector(RESIZE_NUM(v_result_re, g_out_dat_w)); -- conform option a)
- else
- return std_logic_vector(RESIZE_NUM(v_result_im, g_out_dat_w)); -- conform option a)
- end if;
- end;
-
- ------------------------------------------------------------------------------
- -- FUNCTION: Converts the decimal value represented in a string to an integer value.
- ------------------------------------------------------------------------------
- function func_decstring_to_integer(in_string: string) return integer is
- constant c_nof_digits : natural := in_string'length; -- Define the length of the string
- variable v_char : character;
- variable v_weight : integer := 1;
- variable v_return_int : integer := 0;
- begin
- -- Walk through the string character by character.
- for I in c_nof_digits - 1 downto 0 loop
- v_char := in_string(I + in_string'low);
- case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when others => null;
- end case;
- if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
- v_weight := v_weight * 10; -- Addapt the weight for the next decimal digit.
- end if;
- end loop;
- return(v_return_int);
- end function func_decstring_to_integer;
-
- ------------------------------------------------------------------------------
- -- FUNCTION: Converts the hexadecimal value represented in a string to an integer value.
- ------------------------------------------------------------------------------
- function func_hexstring_to_integer(in_string: string) return integer is
- constant c_nof_digits : natural := in_string'length; -- Define the length of the string
- variable v_char : character;
- variable v_weight : integer := 1;
- variable v_return_int : integer := 0;
- begin
- -- Walk through the string character by character.
- for I in c_nof_digits - 1 downto 0 loop
- v_char := in_string(I + in_string'low);
- case v_char is
- when '0' => v_return_int := v_return_int + 0 * v_weight;
- when '1' => v_return_int := v_return_int + 1 * v_weight;
- when '2' => v_return_int := v_return_int + 2 * v_weight;
- when '3' => v_return_int := v_return_int + 3 * v_weight;
- when '4' => v_return_int := v_return_int + 4 * v_weight;
- when '5' => v_return_int := v_return_int + 5 * v_weight;
- when '6' => v_return_int := v_return_int + 6 * v_weight;
- when '7' => v_return_int := v_return_int + 7 * v_weight;
- when '8' => v_return_int := v_return_int + 8 * v_weight;
- when '9' => v_return_int := v_return_int + 9 * v_weight;
- when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
- when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
- when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
- when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
- when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
- when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
- when others => null;
- end case;
- if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
- v_weight := v_weight * 16; -- Addapt the weight for the next hexadecimal digit.
+ -- Note that for the product needs as many bits as the sum of the input widths. However the
+ -- sign bit is then only needed for the case that both inputs have the largest negative
+ -- values, only then the MSBits will be "01". For all other inputs the MSbits will always
+ -- be "00" for positive numbers or "11" for negative numbers. MSbits "10" can not occur.
+ -- For largest negative inputs the complex multiply result becomes:
+ --
+ -- 3b inputs --> 6b products --> c_res_w = 7b
+ -- -4 * -4 + -4 * -4 = +16 + +16 = +64 -- most negative valued inputs
+ -- b100 * b100 + b100 * b100 = b010000 + b010000 = b0100000
+ --
+ -- --> if g_out_dat_w = 6b then
+ -- a) IEEE unsigned resizing skips the MSbits so b0100000 = +64 becomes b_100000 = -64
+ -- b) IEEE signed resizing preserves the MSbit so b0100000 = +64 becomes b0_00000 = 0
+ -- c) detect MSbits = "01" to clip max positive to get _b011111 = +63
+ -- Option a) seems to map best on the FPGA hardware multiplier IP.
+ if str = "RE" then
+ return std_logic_vector(RESIZE_NUM(v_result_re, g_out_dat_w)); -- conform option a)
+ else
+ return std_logic_vector(RESIZE_NUM(v_result_im, g_out_dat_w)); -- conform option a)
end if;
- end loop;
- return(v_return_int);
- end function func_hexstring_to_integer;
-
- ------------------------------------------------------------------------------
- -- FUNCTION: Finds the first instance of a given character in a string
- -- and returns its position.
- ------------------------------------------------------------------------------
- function func_find_char_in_string(in_string: string; find_char: character) return integer is
- variable v_char_position : integer := 0;
- begin
- for I in 1 to in_string'length loop
- if(in_string(I) = find_char) then
+ end;
+
+ ------------------------------------------------------------------------------
+ -- FUNCTION: Converts the decimal value represented in a string to an integer value.
+ ------------------------------------------------------------------------------
+ function func_decstring_to_integer(in_string: string) return integer is
+ constant c_nof_digits : natural := in_string'length; -- Define the length of the string
+ variable v_char : character;
+ variable v_weight : integer := 1;
+ variable v_return_int : integer := 0;
+ begin
+ -- Walk through the string character by character.
+ for I in c_nof_digits - 1 downto 0 loop
+ v_char := in_string(I + in_string'low);
+ case v_char is
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when others => null;
+ end case;
+ if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
+ v_weight := v_weight * 10; -- Addapt the weight for the next decimal digit.
+ end if;
+ end loop;
+ return(v_return_int);
+ end function func_decstring_to_integer;
+
+ ------------------------------------------------------------------------------
+ -- FUNCTION: Converts the hexadecimal value represented in a string to an integer value.
+ ------------------------------------------------------------------------------
+ function func_hexstring_to_integer(in_string: string) return integer is
+ constant c_nof_digits : natural := in_string'length; -- Define the length of the string
+ variable v_char : character;
+ variable v_weight : integer := 1;
+ variable v_return_int : integer := 0;
+ begin
+ -- Walk through the string character by character.
+ for I in c_nof_digits - 1 downto 0 loop
+ v_char := in_string(I + in_string'low);
+ case v_char is
+ when '0' => v_return_int := v_return_int + 0 * v_weight;
+ when '1' => v_return_int := v_return_int + 1 * v_weight;
+ when '2' => v_return_int := v_return_int + 2 * v_weight;
+ when '3' => v_return_int := v_return_int + 3 * v_weight;
+ when '4' => v_return_int := v_return_int + 4 * v_weight;
+ when '5' => v_return_int := v_return_int + 5 * v_weight;
+ when '6' => v_return_int := v_return_int + 6 * v_weight;
+ when '7' => v_return_int := v_return_int + 7 * v_weight;
+ when '8' => v_return_int := v_return_int + 8 * v_weight;
+ when '9' => v_return_int := v_return_int + 9 * v_weight;
+ when 'A' | 'a' => v_return_int := v_return_int + 10 * v_weight;
+ when 'B' | 'b' => v_return_int := v_return_int + 11 * v_weight;
+ when 'C' | 'c' => v_return_int := v_return_int + 12 * v_weight;
+ when 'D' | 'd' => v_return_int := v_return_int + 13 * v_weight;
+ when 'E' | 'e' => v_return_int := v_return_int + 14 * v_weight;
+ when 'F' | 'f' => v_return_int := v_return_int + 15 * v_weight;
+ when others => null;
+ end case;
+ if (v_char /= ' ') then -- Only increment the weight when the character is NOT a spacebar.
+ v_weight := v_weight * 16; -- Addapt the weight for the next hexadecimal digit.
+ end if;
+ end loop;
+ return(v_return_int);
+ end function func_hexstring_to_integer;
+
+ ------------------------------------------------------------------------------
+ -- FUNCTION: Finds the first instance of a given character in a string
+ -- and returns its position.
+ ------------------------------------------------------------------------------
+ function func_find_char_in_string(in_string: string; find_char: character) return integer is
+ variable v_char_position : integer := 0;
+ begin
+ for I in 1 to in_string'length loop
+ if(in_string(I) = find_char) then
v_char_position := I;
- end if;
- end loop;
- return(v_char_position);
- end function func_find_char_in_string;
-
- ------------------------------------------------------------------------------
- -- FUNCTION: Checks if a string(find_string) is part of a larger string(in_string).
- -- The result is returned as a BOOLEAN.
- ------------------------------------------------------------------------------
- function func_find_string_in_string(in_string: string; find_string: string) return boolean is
- constant c_in_length : natural := in_string'length; -- Define the length of the string to search in
- constant c_find_length : natural := find_string'length; -- Define the length of the string to be find
- variable v_found_it : boolean := false;
- begin
- for I in 1 to c_in_length - c_find_length loop
- if(in_string(I to (I + c_find_length - 1)) = find_string) then
+ end if;
+ end loop;
+ return(v_char_position);
+ end function func_find_char_in_string;
+
+ ------------------------------------------------------------------------------
+ -- FUNCTION: Checks if a string(find_string) is part of a larger string(in_string).
+ -- The result is returned as a BOOLEAN.
+ ------------------------------------------------------------------------------
+ function func_find_string_in_string(in_string: string; find_string: string) return boolean is
+ constant c_in_length : natural := in_string'length; -- Define the length of the string to search in
+ constant c_find_length : natural := find_string'length; -- Define the length of the string to be find
+ variable v_found_it : boolean := false;
+ begin
+ for I in 1 to c_in_length - c_find_length loop
+ if(in_string(I to (I + c_find_length - 1)) = find_string) then
v_found_it := true;
- end if;
- end loop;
- return(v_found_it);
- end function func_find_string_in_string;
+ end if;
+ end loop;
+ return(v_found_it);
+ end function func_find_string_in_string;
end tb_common_pkg;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 5a9bddeddedb9ae751ca72a87ba36627f5e2c3b8..fc4449fdd387da7e3d71ae3533d7bd14b79033a9 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -30,9 +30,9 @@
-- . if no failure messages are printed, TB ran OK.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_common_pulse_delay is
end tb_common_pulse_delay;
@@ -102,18 +102,18 @@ begin
-- common_pulse_delay
-----------------------------------------------------------------------------
u_common_pulse_delay : entity work.common_pulse_delay
- generic map (
- g_pulse_delay_max => c_pulse_delay_max,
- g_register_out => true
- )
- port map (
- clk => clk,
- rst => rst,
-
- pulse_in => pulse_in,
- pulse_delay => pulse_delay,
- pulse_out => pulse_out
- );
+ generic map (
+ g_pulse_delay_max => c_pulse_delay_max,
+ g_register_out => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ pulse_in => pulse_in,
+ pulse_delay => pulse_delay,
+ pulse_out => pulse_out
+ );
-----------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
index 514326c77b65fcf2a9d36af9e687916ea7ab87dd..aec4e8841076f9662276d5b77b1ce4da2df982fc 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_pulse_extend is
generic (
@@ -36,7 +36,7 @@ architecture tb of tb_common_pulse_extend is
constant clk_period : time := 10 ns;
constant c_extend_w : natural := 3;
- constant c_extend_len : natural := 2**c_extend_w;
+ constant c_extend_len : natural := 2 ** c_extend_w;
constant c_interval_len : natural := 2 * c_extend_len;
signal tb_end : std_logic := '0';
@@ -71,16 +71,16 @@ begin
end process;
u_spulse : entity work.common_pulse_extend
- generic map (
- g_rst_level => '0',
- g_p_in_level => g_p_in_level,
- g_ep_out_level => g_ep_out_level,
- g_extend_w => c_extend_w
- )
- port map (
- rst => rst,
- clk => clk,
- p_in => pulse_in,
- ep_out => pulse_out
- );
+ generic map (
+ g_rst_level => '0',
+ g_p_in_level => g_p_in_level,
+ g_ep_out_level => g_ep_out_level,
+ g_extend_w => c_extend_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ p_in => pulse_in,
+ ep_out => pulse_out
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
index 4dec90a01d91961ed20959663c2c3cf99dde740f..353d3010ce4926245ec3d179a58e97e03582db91 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser is
end tb_common_pulser;
@@ -66,53 +66,53 @@ begin
end process;
u_reset : entity work.common_areset
- generic map (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- port map (
- in_rst => '0', -- release reset after some clock cycles
- clk => clk,
- out_rst => rst
- );
+ generic map (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ port map (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => clk,
+ out_rst => rst
+ );
u_pulse_us : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_us,
- g_pulse_phase => c_pulse_us - 1
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => '1',
- pulse_clr => '0',
- pulse_out => pulse_us
- );
+ generic map (
+ g_pulse_period => c_pulse_us,
+ g_pulse_phase => c_pulse_us - 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => '1',
+ pulse_clr => '0',
+ pulse_out => pulse_us
+ );
u_pulse_ms_via_clk_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => pulse_us,
- pulse_en => '1',
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_clk_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => pulse_us,
+ pulse_en => '1',
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_clk_en
+ );
u_pulse_ms_via_pulse_en : entity work.common_pulser
- generic map (
- g_pulse_period => c_pulse_ms
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- pulse_en => pulse_us,
- pulse_clr => pulse_ms_clr,
- pulse_out => pulse_ms_via_pulse_en
- );
+ generic map (
+ g_pulse_period => c_pulse_ms
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ pulse_en => pulse_us,
+ pulse_clr => pulse_ms_clr,
+ pulse_out => pulse_ms_via_pulse_en
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
index 7f99b1261041ed636b8ed5cf4dce8255d9cec6f7..51c756b706d652d87139ad972fead26bbd589278 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -30,9 +30,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_pulser_us_ms_s is
end tb_common_pulser_us_ms_s;
@@ -89,17 +89,17 @@ begin
end process;
u_common_pulser_us_ms_s : entity work.common_pulser_us_ms_s
- generic map (
- g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
- g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
- g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
- )
- port map (
- rst => rst,
- clk => clk,
- sync => sync,
- pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
- pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
- pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
- );
+ generic map (
+ g_pulse_us => c_pulse_us, -- nof clk cycles to get us period
+ g_pulse_ms => c_1000, -- nof pulse_us pulses to get ms period
+ g_pulse_s => c_1000 -- nof pulse_ms pulses to get s period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sync => sync,
+ pulse_us => pulse_us, -- pulses after every g_pulse_us clock cycles
+ pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
+ pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
index 5cdd3da0d1cc1fbe34409b08b9119736c56381ab..f1d2aa20721940a610b38b81966b652a20526922 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_reg_cross_domain is
end tb_common_reg_cross_domain;
@@ -108,25 +108,25 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_reg_cross_domain : entity work.common_reg_cross_domain
- generic map (
- g_in_new_latency => c_in_new_latency
- )
- port map (
- in_rst => in_rst,
- in_clk => in_clk,
- in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => in_dat,
- in_done => in_done,
- out_rst => out_rst,
- out_clk => out_clk,
- out_dat => out_dat,
- out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ generic map (
+ g_in_new_latency => c_in_new_latency
+ )
+ port map (
+ in_rst => in_rst,
+ in_clk => in_clk,
+ in_new => in_new, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => in_dat,
+ in_done => in_done,
+ out_rst => out_rst,
+ out_clk => out_clk,
+ out_dat => out_dat,
+ out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index 842665e03eaef6b8cf5ee40cc701ac970ca4d0ff..719954b5459ba35f7634aeffd3fdde85c9799522 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
-- Purpose: Test bench to check reinterleave function visually
-- Usage:
@@ -40,7 +40,7 @@ entity tb_common_reinterleave is
g_inter_block_size : natural := 2;
g_concat_id : boolean := true; -- Concatenate a 1 byte stream ID 0xA..F @ MSB so user can follow streams in wave window
g_cnt_sync : boolean := true -- When TRUE all generated streams start at 0, else they're offset by 16 counter values.
- );
+ );
end;
architecture rtl of tb_common_reinterleave is
@@ -123,6 +123,7 @@ begin
-- lower the effective input data rate accordingly by introducing gaps.
-----------------------------------------------------------------------------
gen_dut_in_dat_gaps : if g_nof_in > g_nof_out generate
+
p_cnt_dat_gaps : process
begin
cnt_rdy <= '0';
@@ -143,23 +144,23 @@ begin
-- DUT
-----------------------------------------------------------------------------
u_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_in_dat,
- in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
-
- out_dat => dut_out_dat,
- out_val => dut_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_in_dat,
+ in_val => dut_in_val_arr(0), -- All input streams should be synchronous in terms of timing
+
+ out_dat => dut_out_dat,
+ out_val => dut_out_val
+ );
-----------------------------------------------------------------------------
-- Map DUT output SLV to array of streams (to ease viewing in wave window)
@@ -172,23 +173,23 @@ begin
-- REVERSE FUNCTION; the outputs should match the DUT inputs (with delay)
-----------------------------------------------------------------------------
u_rev_reinterleave : entity work.common_reinterleave
- generic map (
- g_nof_in => g_nof_out, -- Note the reversed generics
- g_deint_block_size => g_inter_block_size,
- g_nof_out => g_nof_in,
- g_inter_block_size => g_deint_block_size,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => dut_out_dat,
- in_val => dut_out_val(0),
-
- out_dat => rev_out_dat,
- out_val => rev_out_val
- );
+ generic map (
+ g_nof_in => g_nof_out, -- Note the reversed generics
+ g_deint_block_size => g_inter_block_size,
+ g_nof_out => g_nof_in,
+ g_inter_block_size => g_deint_block_size,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => dut_out_dat,
+ in_val => dut_out_val(0),
+
+ out_dat => rev_out_dat,
+ out_val => rev_out_val
+ );
-----------------------------------------------------------------------------
-- Map REV output SLV to array of streams
@@ -196,5 +197,4 @@ begin
gen_rev_out : for i in 0 to g_nof_out - 1 generate
rev_out_dat_arr(i) <= rev_out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w);
end generate;
-
end rtl;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index a2e3cb2e3b6db3b0c8b783dabb56c78052c1d16e..01e00e2cc513023f56f11335215a33671b89d460 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_reorder_symbol.vhd
-- Usage:
@@ -45,11 +45,11 @@ use common_lib.common_pkg.all;
entity tb_common_reorder_symbol is
generic (
--- g_nof_input : NATURAL := 3;
--- g_nof_output : NATURAL := 3;
--- g_symbol_w : NATURAL := 8;
--- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
--- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
+ -- g_nof_input : NATURAL := 3;
+ -- g_nof_output : NATURAL := 3;
+ -- g_symbol_w : NATURAL := 8;
+ -- g_select_arr : t_natural_arr := (3, 3, 3); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
+ -- g_pipeline_arr : t_natural_arr := (0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
g_nof_input : natural := 5;
g_nof_output : natural := 5;
g_symbol_w : natural := 8;
@@ -151,32 +151,32 @@ begin
-- DUT
u_reorder_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
-- inverse DUT
inverse_select_arr <= func_common_reorder2_inverse_select(c_N, in_select_arr);
@@ -186,60 +186,60 @@ begin
end generate;
u_inverse_in : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
-
- out_data => inverse_data_vec,
- out_val => inverse_val,
- out_sop => inverse_sop,
- out_eop => inverse_eop,
- out_sync => inverse_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec(c_nof_select * c_select_w - 1 downto 0),
+
+ out_data => inverse_data_vec,
+ out_val => inverse_val,
+ out_sop => inverse_sop,
+ out_eop => inverse_eop,
+ out_sync => inverse_sync
+ );
u_inverse_out : entity work.common_reorder_symbol
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_select_w => c_select_w,
- g_nof_select => c_nof_select,
- g_pipeline_arr => g_pipeline_arr
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => inverse_data_vec,
- in_val => inverse_val,
- in_sop => inverse_sop,
- in_eop => inverse_eop,
- in_sync => inverse_sync,
-
- in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_select_w => c_select_w,
+ g_nof_select => c_nof_select,
+ g_pipeline_arr => g_pipeline_arr
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => inverse_data_vec,
+ in_val => inverse_val,
+ in_sop => inverse_sop,
+ in_eop => inverse_eop,
+ in_sync => inverse_sync,
+
+ in_select => inverse_select_vec(2 * c_nof_select * c_select_w - 1 downto c_nof_select * c_select_w),
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -256,60 +256,60 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
index 2eb0d6329b4ee81480ef6c1b11b5a7ffaa7711c3..067e3c717a0cfc3459b40ff45f697e9e82f97f6d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
@@ -38,11 +38,11 @@
-- works when g_rl_increase_en is FALSE or both are FALSE.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl is
generic (
@@ -151,28 +151,28 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_increase_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
);
- -- RL 1 --> 0
- u_rl_decrease : entity work.common_rl_decrease
+-- RL 1 --> 0
+u_rl_decrease : entity work.common_rl_decrease
generic map (
g_adapt => g_rl_decrease_en,
g_dat_w => c_dat_w
@@ -190,8 +190,8 @@ begin
src_out_val => rl_decrease_out_val
);
- -- RL 0 --> 1
- u_rl_increase : entity work.common_rl_increase
+-- RL 0 --> 1
+u_rl_increase : entity work.common_rl_increase
generic map (
g_adapt => c_rl_increase_en,
g_hold_dat_en => g_rl_increase_hold_dat_en,
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
index f6a168912820278e61ea99cf63f3ae8d3dc15bde..5619563913b3581c4a3cb440616fdea3f66a30e3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
@@ -30,11 +30,11 @@
-- rl_register_in_ready='1' to avoid FIFO overflow.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_rl_register is
generic (
@@ -130,28 +130,28 @@ begin
fifo_out_ready <= '1';
u_fifo_sc : entity work.common_fifo_sc
- generic map (
- g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_dat_w => c_dat_w,
- g_nof_words => g_fifo_size,
- g_af_margin => c_fifo_af_margin
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_in_dat,
- wr_req => fifo_in_val,
- wr_ful => fifo_ful,
- wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
- rd_dat => fifo_out_dat,
- rd_req => fifo_in_ready,
- rd_emp => fifo_emp,
- rd_val => fifo_out_val,
- usedw => fifo_usedw
+ generic map (
+ g_note_is_ful => true, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_dat_w => c_dat_w,
+ g_nof_words => g_fifo_size,
+ g_af_margin => c_fifo_af_margin
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_in_dat,
+ wr_req => fifo_in_val,
+ wr_ful => fifo_ful,
+ wr_aful => fifo_almost_full, -- get FIFO almost full to be used to force rl_register_in_ready
+ rd_dat => fifo_out_dat,
+ rd_req => fifo_in_ready,
+ rd_emp => fifo_emp,
+ rd_val => fifo_out_val,
+ usedw => fifo_usedw
);
- -- RL 1 --> 0 --> 1
- u_rl_register : entity work.common_rl_register
+-- RL 1 --> 0 --> 1
+u_rl_register : entity work.common_rl_register
generic map (
g_adapt => g_rl_register_en,
g_hold_dat_en => g_rl_register_hold_dat_en,
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index 5fc43a60f2effd7296ebfdefaa345d0a7e5ac0e3..7b7dd2a4d562887ce8f90a2b45546a56f4024857 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_select_m_symbols.vhd
-- Usage:
@@ -134,64 +134,64 @@ begin
-- DUT
u_reorder_in : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_output,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
- in_sync => in_sync,
-
- in_select => in_select_vec,
-
- out_data => reorder_data_vec,
- out_val => reorder_val,
- out_sop => reorder_sop,
- out_eop => reorder_eop,
- out_sync => reorder_sync
- );
+ generic map (
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_output,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+ in_sync => in_sync,
+
+ in_select => in_select_vec,
+
+ out_data => reorder_data_vec,
+ out_val => reorder_val,
+ out_sop => reorder_sop,
+ out_eop => reorder_eop,
+ out_sync => reorder_sync
+ );
gen_inverse_select_vec: for K in g_nof_output - 1 downto 0 generate
inverse_select_vec((K + 1) * c_select_w - 1 downto K * c_select_w) <= TO_UVEC(inverse_select_arr(K), c_select_w);
end generate;
u_inverse_out : entity work.common_select_m_symbols
- generic map (
- g_nof_input => g_nof_output,
- g_nof_output => g_nof_input,
- g_symbol_w => g_symbol_w,
- g_pipeline_in => g_pipeline_in,
- g_pipeline_in_m => g_pipeline_in_m,
- g_pipeline_out => g_pipeline_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => reorder_data_vec,
- in_val => reorder_val,
- in_sop => reorder_sop,
- in_eop => reorder_eop,
- in_sync => reorder_sync,
-
- in_select => inverse_select_vec,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop,
- out_sync => out_sync
- );
+ generic map (
+ g_nof_input => g_nof_output,
+ g_nof_output => g_nof_input,
+ g_symbol_w => g_symbol_w,
+ g_pipeline_in => g_pipeline_in,
+ g_pipeline_in_m => g_pipeline_in_m,
+ g_pipeline_out => g_pipeline_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => reorder_data_vec,
+ in_val => reorder_val,
+ in_sop => reorder_sop,
+ in_eop => reorder_eop,
+ in_sync => reorder_sync,
+
+ in_select => inverse_select_vec,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop,
+ out_sync => out_sync
+ );
-- Verification
p_verify : process(rst, clk)
@@ -208,60 +208,60 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => c_total_pipeline,
- g_in_dat_w => g_nof_input * g_symbol_w,
- g_out_dat_w => g_nof_input * g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => c_total_pipeline,
+ g_in_dat_w => g_nof_input * g_symbol_w,
+ g_out_dat_w => g_nof_input * g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
u_out_sync : entity work.common_pipeline_sl
- generic map (
- g_pipeline => c_total_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sync,
- out_dat => exp_sync
- );
+ generic map (
+ g_pipeline => c_total_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sync,
+ out_dat => exp_sync
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index 14f400a91f88f8431654ee96caa00765690b2398..6c662ab8e56d68466f6baa4e178f949314984f7f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -30,10 +30,10 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_shiftram is
generic (
@@ -107,22 +107,22 @@ begin
-- DUT
u_common_shiftram : entity work.common_shiftram
- generic map (
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_in => data_in,
- data_in_val => data_in_val,
- data_in_shift => data_in_shift,
-
- data_out => data_out,
- data_out_val => data_out_val,
- data_out_shift => data_out_shift
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_in => data_in,
+ data_in_val => data_in_val,
+ data_in_shift => data_in_shift,
+
+ data_out => data_out,
+ data_out_val => data_out_val,
+ data_out_shift => data_out_shift
+ );
-- Make sure prev_data_out has been assigned
p_verify_start: process
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
index 306d94849f22786bb7666f0ca151d0a51fe9b173..dddde1528f705a83347bbdbf535385f498791b96 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
-- Purpose: Test bench for common_shiftreg.vhd
-- Usage:
@@ -155,32 +155,32 @@ begin
-- DUT
u_shiftreg : entity work.common_shiftreg
- generic map (
- g_pipeline => g_pipeline,
- g_flush_en => g_flush_en,
- g_nof_dat => g_nof_dat,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => in_dat,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data_vec => out_data_vec,
- out_val_vec => out_val_vec,
- out_sop_vec => out_sop_vec,
- out_eop_vec => out_eop_vec,
- out_cnt => out_cnt,
-
- out_dat => out_dat,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_flush_en => g_flush_en,
+ g_nof_dat => g_nof_dat,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data_vec => out_data_vec,
+ out_val_vec => out_val_vec,
+ out_sop_vec => out_sop_vec,
+ out_eop_vec => out_eop_vec,
+ out_cnt => out_cnt,
+
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_dat, prev_out_dat);
diff --git a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
index 70dfeed5e020ecfcb2ecce4ef8e520fb893d4348..8c3c7e045cd2bff139dc56ed59be9ecd3e5c4c39 100644
--- a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
@@ -27,9 +27,9 @@
-- > run 1 us
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_common_spulse is
end tb_common_spulse;
@@ -67,22 +67,22 @@ begin
end process;
u_out_rst : entity work.common_areset
- port map (
- in_rst => in_rst,
- clk => out_clk,
- out_rst => out_rst
- );
+ port map (
+ in_rst => in_rst,
+ clk => out_clk,
+ out_rst => out_rst
+ );
u_spulse : entity work.common_spulse
- generic map (
- g_delay_len => c_meta_delay
- )
- port map (
- in_clk => in_clk,
- in_rst => in_rst,
- in_pulse => in_pulse,
- out_clk => out_clk,
- out_rst => out_rst,
- out_pulse => out_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay
+ )
+ port map (
+ in_clk => in_clk,
+ in_rst => in_rst,
+ in_pulse => in_pulse,
+ out_clk => out_clk,
+ out_rst => out_rst,
+ out_pulse => out_pulse
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 457290cb5c787750f4466b1c972a8bd425fbcab8..431ec1c23e5605313ef53068b631e978810727e1 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_switch is
end tb_common_switch;
@@ -45,15 +45,16 @@ architecture tb of tb_common_switch is
constant c_nof_generics : natural := 3;
- constant c_nof_dut : natural := 2**c_nof_generics;
- constant c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := ((false, false, false),
- (false, false, true),
- (false, true, false),
- (false, true, true),
- ( true, false, false),
- ( true, false, true),
- ( true, true, false),
- ( true, true, true));
+ constant c_nof_dut : natural := 2 ** c_nof_generics;
+ constant c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := (
+ (false, false, false),
+ (false, false, true),
+ (false, true, false),
+ (false, true, true),
+ ( true, false, false),
+ ( true, false, true),
+ ( true, true, false),
+ ( true, true, true));
-- View constants in Wave window
signal dbg_c_generics_matrix : t_boolean_matrix(0 to c_nof_dut - 1, 0 to c_nof_generics - 1) := c_generics_matrix;
signal dbg_state : natural;
@@ -222,20 +223,19 @@ begin
gen_dut : for I in 0 to c_nof_dut - 1 generate
u_switch : entity work.common_switch
- generic map (
- g_rst_level => '0', -- output level at reset.
- --g_rst_level => '1',
- g_priority_lo => c_generics_matrix(I,0),
- g_or_high => c_generics_matrix(I,1),
- g_and_low => c_generics_matrix(I,2)
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_hi,
- switch_low => in_lo,
- out_level => out_level(I)
- );
+ generic map (
+ g_rst_level => '0', -- output level at reset.
+ --g_rst_level => '1',
+ g_priority_lo => c_generics_matrix(I,0),
+ g_or_high => c_generics_matrix(I,1),
+ g_and_low => c_generics_matrix(I,2)
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_hi,
+ switch_low => in_lo,
+ out_level => out_level(I)
+ );
end generate;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 30de6415c851352612305aeb5f88fc3e38221e26..5ab685a54dc32f59394f99938f8d2f62c176f003 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -42,9 +42,9 @@
-- signals with radix unsigend.
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use work.common_pkg.all;
entity tb_common_to_sreal is
end tb_common_to_sreal;
@@ -54,8 +54,8 @@ architecture tb of tb_common_to_sreal is
constant c_resolution_w : natural := 5;
constant c_width : natural := 4;
- constant c_min : integer := -2**(c_width - 1);
- constant c_max : integer := 2**(c_width - 1) - 1;
+ constant c_min : integer := -2 ** (c_width - 1);
+ constant c_max : integer := 2 ** (c_width - 1) - 1;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -69,8 +69,9 @@ architecture tb of tb_common_to_sreal is
signal dbg_resolution_w : integer := 0;
signal dbg_resolution : real := 0.0;
- procedure proc_wait_some_cycles(signal clk : in std_logic;
- c_nof_cycles : in natural) is
+ procedure proc_wait_some_cycles(
+ signal clk : in std_logic;
+ c_nof_cycles : in natural) is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_wait_some_cycles;
@@ -93,7 +94,7 @@ begin
-- Try all v_slv for c_width and resolutions beyond c_width
for R in - c_resolution_w to c_resolution_w loop
dbg_resolution_w <= R;
- dbg_resolution <= 1.0 / 2.0**REAL(R);
+ dbg_resolution <= 1.0 / 2.0 ** real(R);
for I in c_min to c_max loop
v_slv := TO_SVEC(I, c_width);
-- Convert fixed point v_slv with binary point at resolution width R, to real and back to slv
@@ -131,19 +132,19 @@ begin
v_real := -6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := -6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 6.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 6.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 7.49; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 7.51; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 5);
-- . Just overflow with 4 bit integers for -16.5 : +15.5
v_real := -15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 15.5; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 5);
-- . Negative clip to 0 for unsigned
@@ -160,17 +161,17 @@ begin
v_real := -28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := -18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 18.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 28.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 38.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 48.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 58.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
v_real := 68.0; a_real <= v_real; a_sint <= TO_SINT(v_real, 4, 0); a_slv <= TO_SVEC(v_real, 4, 0); wait until rising_edge(clk);
- a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
+ a_uint <= TO_UINT(v_real, 4, 0); a_ulv <= TO_UVEC(v_real, 4, 0); wait until rising_edge(clk);
proc_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -179,9 +180,9 @@ begin
-- TO_SINT() and TO_SVEC() must always yield same result
assert a_sint = TO_SINT(a_slv) report "Unexpected difference between TO_SINT() and TO_SVEC() :" &
- integer'image(a_sint) & " /= " & integer'image(TO_SINT(a_slv)) severity ERROR;
+ integer'image(a_sint) & " /= " & integer'image(TO_SINT(a_slv)) severity ERROR;
-- TO_UINT() and TO_UVEC() must always yield same result
assert a_uint = TO_UINT(a_ulv) report "Unexpected difference between TO_UINT() and TO_UVEC() :" &
- integer'image(a_uint) & " /= " & integer'image(TO_SINT(a_ulv)) severity ERROR;
+ integer'image(a_uint) & " /= " & integer'image(TO_SINT(a_ulv)) severity ERROR;
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
index fb66383f1a555d8d0fc05702fec2f6a3db27fd37..72d5a8a0e15a415b60b3d8e329f846669b100ee9 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
@@ -26,9 +26,9 @@
-- Observe the out_toggle during the different stimuli indicated by tb_state.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle is
end tb_common_toggle;
@@ -96,16 +96,16 @@ begin
end process;
u_toggle : entity work.common_toggle
- generic map (
- g_evt_type => "RISING",
- g_rst_level => '0'
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_dat,
- in_val => in_val,
- out_dat => out_toggle
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_dat,
+ in_val => in_val,
+ out_dat => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
index e1509488886a238b53c5689b7f54435171269abe..dbc05a985515d0b8ef7b5ce65cc732e91914399f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
@@ -27,9 +27,9 @@
-- Observe out_toggle in Wave Window in relation to in_toggle and align
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_toggle_align is
end tb_common_toggle_align;
@@ -126,15 +126,15 @@ begin
end process;
u_toggle : entity work.common_toggle_align
- generic map (
- g_pipeline => c_pipeline,
- g_nof_clk_per_period => c_toggle_period
- )
- port map (
- rst => rst,
- clk => clk,
- in_align => in_align,
- in_toggle => in_toggle,
- out_toggle => out_toggle
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_clk_per_period => c_toggle_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_align => in_align,
+ in_toggle => in_toggle,
+ out_toggle => out_toggle
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
index 922093695f4ad3b5ecea723503355b9ca98df9f0..bddd76bd56bb4435774934e774b6bdf93f1fcb3c 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
-- Purpose: Test bench for common_transpose.vhd
-- Usage:
@@ -60,9 +60,10 @@ architecture tb of tb_common_transpose is
constant c_frame_len : natural := 7 * g_nof_data;
constant c_frame_eop : natural := (c_frame_len - 1) mod c_frame_len;
- procedure proc_align_eop(signal clk : in std_logic;
- signal stimuli_phase : in std_logic;
- signal in_val : out std_logic) is
+ procedure proc_align_eop(
+ signal clk : in std_logic;
+ signal stimuli_phase : in std_logic;
+ signal in_val : out std_logic) is
begin
while stimuli_phase = '0' loop
in_val <= '1';
@@ -206,58 +207,58 @@ begin
-- DUT
u_transpose_in : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_offset => in_offset,
- in_addr => in_addr,
- in_data => in_data,
- in_val => in_val,
- in_eop => in_eop,
+ in_offset => in_offset,
+ in_addr => in_addr,
+ in_data => in_data,
+ in_val => in_val,
+ in_eop => in_eop,
- out_addr => trans_addr,
- out_data => trans_data,
- out_val => trans_val,
- out_eop => trans_eop
- );
+ out_addr => trans_addr,
+ out_data => trans_data,
+ out_val => trans_val,
+ out_eop => trans_eop
+ );
u_transpose_out : entity common_lib.common_transpose
- generic map (
- g_pipeline_shiftreg => g_pipeline_shiftreg,
- g_pipeline_transpose => g_pipeline_transpose,
- g_pipeline_hold => g_pipeline_hold,
- g_pipeline_select => g_pipeline_select,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w,
- g_addr_w => g_addr_w,
- g_addr_offset => g_addr_offset
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline_shiftreg => g_pipeline_shiftreg,
+ g_pipeline_transpose => g_pipeline_transpose,
+ g_pipeline_hold => g_pipeline_hold,
+ g_pipeline_select => g_pipeline_select,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w,
+ g_addr_w => g_addr_w,
+ g_addr_offset => g_addr_offset
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_offset => trans_offset,
- in_addr => trans_addr,
- in_data => trans_data,
- in_val => trans_val,
- in_eop => trans_eop,
+ in_offset => trans_offset,
+ in_addr => trans_addr,
+ in_data => trans_data,
+ in_val => trans_val,
+ in_eop => trans_eop,
- out_addr => out_addr,
- out_data => out_data,
- out_val => out_val,
- out_eop => out_eop
- );
+ out_addr => out_addr,
+ out_data => out_data,
+ out_val => out_val,
+ out_eop => out_eop
+ );
-- Verification p_verify
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_addr, prev_out_addr);
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
index 7bef3d07b04b22a23836855cf1c84aa3fc1f7a41..aa132e35538c7cf97cd4e341505836a38b56ffad 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Test bench for common_transpose_symbol.vhd
-- Usage:
@@ -93,7 +93,7 @@ begin
end process;
gen_vec: for I in g_nof_data - 1 downto 0 generate
- in_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w) <= INCR_UVEC(in_dat, I * 2**c_symbol_w);
+ in_data_vec((I + 1) * g_data_w - 1 downto I * g_data_w) <= INCR_UVEC(in_dat, I * 2 ** c_symbol_w);
end generate;
in_sop <= in_val when TO_UINT(in_dat) mod c_frame_len = c_frame_sop else '0';
@@ -101,46 +101,46 @@ begin
-- DUT
u_transpose_in : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => in_data_vec,
- in_val => in_val,
- in_sop => in_sop,
- in_eop => in_eop,
-
- out_data => trans_data_vec,
- out_val => trans_val,
- out_sop => trans_sop,
- out_eop => trans_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => in_data_vec,
+ in_val => in_val,
+ in_sop => in_sop,
+ in_eop => in_eop,
+
+ out_data => trans_data_vec,
+ out_val => trans_val,
+ out_sop => trans_sop,
+ out_eop => trans_eop
+ );
u_transpose_out : entity work.common_transpose_symbol
- generic map (
- g_pipeline => g_pipeline,
- g_nof_data => g_nof_data,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_data => trans_data_vec,
- in_val => trans_val,
- in_sop => trans_sop,
- in_eop => trans_eop,
-
- out_data => out_data_vec,
- out_val => out_val,
- out_sop => out_sop,
- out_eop => out_eop
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_data => g_nof_data,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_data => trans_data_vec,
+ in_val => trans_val,
+ in_sop => trans_sop,
+ in_eop => trans_eop,
+
+ out_data => out_data_vec,
+ out_val => out_val,
+ out_sop => out_sop,
+ out_eop => out_eop
+ );
-- Verification
p_verify : process(rst, clk)
@@ -156,49 +156,49 @@ begin
-- pipeline data input
u_out_dat : entity work.common_pipeline
- generic map (
- g_pipeline => g_pipeline * 2,
- g_in_dat_w => g_nof_data * g_data_w,
- g_out_dat_w => g_nof_data * g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_data_vec,
- out_dat => exp_data_vec
- );
+ generic map (
+ g_pipeline => g_pipeline * 2,
+ g_in_dat_w => g_nof_data * g_data_w,
+ g_out_dat_w => g_nof_data * g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_data_vec,
+ out_dat => exp_data_vec
+ );
-- pipeline control input
u_out_val : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_val,
- out_dat => exp_val
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_val,
+ out_dat => exp_val
+ );
u_out_sop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_sop,
- out_dat => exp_sop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_sop,
+ out_dat => exp_sop
+ );
u_out_eop : entity work.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_eop,
- out_dat => exp_eop
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_eop,
+ out_dat => exp_eop
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index e83313ab6c22d2cff4fc02624756da9f8a84821d..d94f3bb6dfccb614b43a1db06eb3d04a438f6e87 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -26,11 +26,11 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_variable_delay is
end tb_common_variable_delay;
@@ -67,7 +67,7 @@ begin
proc_common_gen_pulse(1, c_trigger_interval, '1', rst, clk, trigger);
p_in_stimuli : process
- variable clk_cnt : natural := 0;
+ variable clk_cnt : natural := 0;
begin
delay <= 0;
enable <= '0';
@@ -105,13 +105,13 @@ begin
-- device under test
u_dut : entity work.common_variable_delay
- port map (
- rst => rst,
- clk => clk,
-
- delay => delay,
- enable => enable,
- in_pulse => trigger,
- out_pulse => trigger_dly
- );
+ port map (
+ rst => rst,
+ clk => clk,
+
+ delay => delay,
+ enable => enable,
+ in_pulse => trigger,
+ out_pulse => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index 5dd2390947c3888e8d984f4ca02987e3f5e12370..49b4700411646c1fd83c5e213570afb5315877fa 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -29,11 +29,11 @@
-- to the out_dat vector.
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_lfsr_sequences_pkg.all;
-use work.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_lfsr_sequences_pkg.all;
+ use work.tb_common_pkg.all;
entity tb_common_zip is
generic (
@@ -76,16 +76,16 @@ begin
enable <= ena and ena_mask;
u_dut : entity work.common_zip
- generic map (
- g_nof_streams => g_nof_streams,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_val => in_val,
- in_dat_arr => in_dat_arr,
- out_val => out_val,
- out_dat => out_dat
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_val => in_val,
+ in_dat_arr => in_dat_arr,
+ out_val => out_val,
+ out_dat => out_dat
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
index 352ac9ae479ec356510e109d8fa68a7e444f5cba..079f7e44efc8790c06aa10eb1c32396d8f24f6cb 100644
--- a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
+++ b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
@@ -86,8 +86,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
entity tb_delta_cycle_demo is
end tb_delta_cycle_demo;
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 93022fd6a2b4ad09ec80851a04d49f1816a61e74..9a6c58aad2eaa291c9086feae9bf1e89c6bf3d81 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -29,13 +29,13 @@
-- --------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
-use work.common_str_pkg.all;
-use work.tb_common_pkg.all;
-use work.common_mem_pkg.all;
-use work.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
+ use work.common_str_pkg.all;
+ use work.tb_common_pkg.all;
+ use work.common_mem_pkg.all;
+ use work.tb_common_mem_pkg.all;
entity tb_mms_common_variable_delay is
end tb_mms_common_variable_delay;
@@ -93,17 +93,17 @@ begin
-- device under test
u_dut : entity work.mms_common_variable_delay
- port map (
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
-
- reg_enable_mosi => mm_mosi,
- reg_enable_miso => mm_miso,
-
- delay => delay,
- trigger => trigger,
- trigger_dly => trigger_dly
- );
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+
+ reg_enable_mosi => mm_mosi,
+ reg_enable_miso => mm_miso,
+
+ delay => delay,
+ trigger => trigger,
+ trigger_dly => trigger_dly
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_requantize.vhd b/libraries/base/common/tb/vhdl/tb_requantize.vhd
index 68fd97cdd1457e0e60a444f7718ecbf7cccf736f..6d8b506441da461c90938dcb1c86c56bcdd323f9 100644
--- a/libraries/base/common/tb/vhdl/tb_requantize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_requantize.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, tst_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
-- Purpose: Test bench for common_requantize.vhd
-- Usage:
@@ -135,190 +135,190 @@ begin
in_vec <= in_val & in_dat;
u_pipe : entity work.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_in_dat_w => c_in_dat_w + 1,
- g_out_dat_w => c_in_dat_w + 1
- )
- port map (
- clk => clk,
- in_dat => in_vec,
- out_dat => reg_vec
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_in_dat_w => c_in_dat_w + 1,
+ g_out_dat_w => c_in_dat_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => in_vec,
+ out_dat => reg_vec
+ );
reg_val <= reg_vec(c_in_dat_w);
reg_dat <= reg_vec(c_in_dat_w - 1 downto 0);
-- DUT for "SIGNED"
u_s_r_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_c_dat,
- out_ovr => out_s_r_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_c_dat,
+ out_ovr => out_s_r_c_ovr
+ );
u_s_r_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_r_w_dat,
- out_ovr => out_s_r_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_r_w_dat,
+ out_ovr => out_s_r_w_ovr
+ );
u_s_t_c : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_c_dat,
- out_ovr => out_s_t_c_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_c_dat,
+ out_ovr => out_s_t_c_ovr
+ );
u_s_t_w : entity work.common_requantize
- generic map (
- g_representation => "SIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_s_t_w_dat,
- out_ovr => out_s_t_w_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_s_t_w_dat,
+ out_ovr => out_s_t_w_ovr
+ );
-- DUT for "UNSIGNED"
u_u_r_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_c_dat,
- out_ovr => out_u_r_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_c_dat,
+ out_ovr => out_u_r_c_ovr
+ );
u_u_r_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => true,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_r_w_dat,
- out_ovr => out_u_r_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => true,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_r_w_dat,
+ out_ovr => out_u_r_w_ovr
+ );
u_u_t_c : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => true,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_c_dat,
- out_ovr => out_u_t_c_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => true,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_c_dat,
+ out_ovr => out_u_t_c_ovr
+ );
u_u_t_w : entity work.common_requantize
- generic map (
- g_representation => "UNSIGNED",
- g_lsb_w => c_lsb_w,
- g_lsb_round => false,
- g_lsb_round_clip => c_lsb_round_clip,
- g_lsb_round_even => c_lsb_round_even,
- g_msb_clip => false,
- g_msb_clip_symmetric => c_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => c_in_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_u_t_w_dat,
- out_ovr => out_u_t_w_ovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_lsb_w => c_lsb_w,
+ g_lsb_round => false,
+ g_lsb_round_clip => c_lsb_round_clip,
+ g_lsb_round_even => c_lsb_round_even,
+ g_msb_clip => false,
+ g_msb_clip_symmetric => c_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => c_in_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_u_t_w_dat,
+ out_ovr => out_u_t_w_ovr
+ );
-- Verification usign golden results from file
p_verify : process
@@ -338,126 +338,126 @@ begin
out_u_ovr_vec <= out_u_r_c_ovr & out_u_r_w_ovr & out_u_t_c_ovr & out_u_t_w_ovr;
u_output_file_s_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_s_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_dat_vec,
- out_val => ref_val,
- out_eof => ref_eof
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_dat_vec,
+ out_val => ref_val,
+ out_eof => ref_eof
+ );
u_output_file_s_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_s_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_s_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_s_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_s_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_s_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_s_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_dat : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_dat_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_dat_vec,
+ in_val => reg_val
+ );
u_ref_file_u_dat : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => c_out_dat_w,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_dat_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_dat.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => c_out_dat_w,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_dat_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
u_output_file_u_ovr : entity tst_lib.tst_output
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "UNSIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => out_u_ovr_vec,
- in_val => reg_val
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.out",
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "UNSIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => out_u_ovr_vec,
+ in_val => reg_val
+ );
u_ref_file_u_ovr : entity tst_lib.tst_input
- generic map (
- g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
- g_file_repeat => 1,
- g_nof_data => c_nof_dut,
- g_data_width => 1,
- g_data_type => "SIGNED"
- )
- port map (
- clk => clk,
- rst => rst,
- en => in_val,
- out_dat => ref_u_ovr_vec,
- out_val => OPEN,
- out_eof => open
- );
+ generic map (
+ g_file_name => c_output_file_dir & "tb_requantize_u_ovr.gold",
+ g_file_repeat => 1,
+ g_nof_data => c_nof_dut,
+ g_data_width => 1,
+ g_data_type => "SIGNED"
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ en => in_val,
+ out_dat => ref_u_ovr_vec,
+ out_val => OPEN,
+ out_eof => open
+ );
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index 01c561206458156c024ae06aeb2b78d6676ef6ae..14916f5b07908c48cd8b8e1fccffec31f93d94e7 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -34,9 +34,9 @@
-- . Observe reg_dat with respect to out_udat, out_uovr for unsigned
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_resize is
generic (
@@ -83,9 +83,9 @@ architecture tb of tb_resize is
signal rst : std_logic;
constant c_init : std_logic_vector(in_dat'range) := (others => '0');
- constant g_clip_umax : natural := 2**g_out_dat_w - 1;
- constant g_clip_smax : natural := 2**(g_out_dat_w - 1) - 1;
- constant g_clip_smin : integer := -2**(g_out_dat_w - 1);
+ constant g_clip_umax : natural := 2 ** g_out_dat_w - 1;
+ constant g_clip_smax : natural := 2 ** (g_out_dat_w - 1) - 1;
+ constant g_clip_smin : integer := -2 ** (g_out_dat_w - 1);
begin
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
@@ -126,6 +126,7 @@ begin
reg_udat <= reg_dat;
gen_extend_lowrange : if g_out_dat_w >= g_in_dat_w generate
+
p_extend_lowrange : process(clk)
begin
if rising_edge(clk) then
@@ -139,6 +140,7 @@ begin
end generate;
gen_reduce_lowrange : if g_out_dat_w < g_in_dat_w generate
+
p_reduce_lowrange : process(clk)
begin
if rising_edge(clk) then
@@ -159,39 +161,39 @@ begin
-- DUT for "SIGNED"
u_s_resize : entity work.common_resize
- generic map (
- g_representation => "SIGNED",
- g_clip => g_clip,
- g_clip_symmetric => g_clip_symmetric,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_sdat,
- out_ovr => out_sovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_clip => g_clip,
+ g_clip_symmetric => g_clip_symmetric,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_sdat,
+ out_ovr => out_sovr
+ );
-- DUT for "UNSIGNED"
u_u_resize : entity work.common_resize
- generic map (
- g_representation => "UNSIGNED",
- g_clip => g_clip,
- g_clip_symmetric => g_clip_symmetric,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => out_udat,
- out_ovr => out_uovr
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_clip => g_clip,
+ g_clip_symmetric => g_clip_symmetric,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => out_udat,
+ out_ovr => out_uovr
+ );
-- Verification
p_verify : process
@@ -213,7 +215,7 @@ begin
assert unsigned( resize_udat) = unsigned(lowrange_udat) report "Wrong wrapped resize_udat" severity ERROR;
assert unsigned(resize_num_udat) = unsigned(lowrange_udat) report "Wrong wrapped resize_num_udat" severity ERROR;
assert unsigned( out_udat) = unsigned(lowrange_udat) or
- unsigned( out_udat) = g_clip_umax report "Wrong clipped out_udat" severity ERROR;
+ unsigned( out_udat) = g_clip_umax report "Wrong clipped out_udat" severity ERROR;
-- For reduced width compare signed with lowrange
-- . no need to verify RESIZE(), because it is part of IEEE.NUMERIC_STD
@@ -222,11 +224,11 @@ begin
if g_clip then
if g_clip_symmetric then
assert (signed(out_sdat) = signed(lowrange_sdat) or signed(out_sdat) = -g_clip_smax or signed(out_sdat) = g_clip_smax) and
- signed(out_sdat) /= g_clip_smin and
- signed(out_sdat) /= -g_clip_smin report "Wrong clipped symmetrical out_sdat" severity ERROR;
+ signed(out_sdat) /= g_clip_smin and
+ signed(out_sdat) /= -g_clip_smin report "Wrong clipped symmetrical out_sdat" severity ERROR;
else
assert (signed(out_sdat) = signed(lowrange_sdat) or signed(out_sdat) = g_clip_smin or signed(out_sdat) = g_clip_smax)
- report "Wrong clipped out_sdat" severity ERROR;
+ report "Wrong clipped out_sdat" severity ERROR;
end if;
else
assert signed(out_sdat) = signed(lowrange_sdat) report "Wrong wrapped out_sdat" severity ERROR;
@@ -238,5 +240,4 @@ begin
assert unsigned(resize_num_udat) = unsigned(lowrange_udat) report "Wrong resize_num_udat /= lowrange_udat" severity ERROR;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 59813adae6bea5dcd004310721f07947af8b203b..efd4e2b39bdda37fc8c190fde731d9f034bbf3e5 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -36,9 +36,9 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.common_pkg.all;
entity tb_round is
generic (
@@ -248,7 +248,7 @@ begin
for I in 0 to 3 loop wait until rising_edge(clk); end loop;
in_val <= '1';
wait until rising_edge(clk);
- for I in 0 to 2**g_in_dat_w - 1 loop
+ for I in 0 to 2 ** g_in_dat_w - 1 loop
in_dat <= INCR_UVEC(in_dat, 1);
wait until rising_edge(clk);
end loop;
@@ -271,86 +271,86 @@ begin
-----------------------------------------------------------------------------
s_truncate : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_truncate
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_truncate
+ );
s_round_half_away : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away
+ );
s_round_half_away_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_away_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_away_clip
+ );
s_round_half_even : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even
+ );
s_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_signed_round_half_even_clip
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_signed_round_half_even_clip
+ );
-----------------------------------------------------------------------------
-- UNSIGNED DUTs
@@ -358,86 +358,86 @@ begin
-- DUT for truncate
u_truncate : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => false,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_truncate
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => false,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_truncate
+ );
u_round_half_up : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up
+ );
u_round_half_up_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_up_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_up_clip
+ );
u_round_half_even : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => false,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => false,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even
+ );
u_round_half_even_clip : entity work.common_round
- generic map (
- g_representation => "UNSIGNED",
- g_round => true,
- g_round_clip => true,
- g_round_even => true,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => in_dat,
- out_dat => fs_unsigned_round_half_even_clip
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_round_even => true,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => in_dat,
+ out_dat => fs_unsigned_round_half_even_clip
+ );
-- Observe fixed point SLV values as REAL
-- . signed
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
index 7d7001e00c70289cbc19599507292e353d3f4b06..c411a2debd1501a16345d21f91fc91ee024b1c07 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_add_sub is
end tb_tb_common_add_sub;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
index ac64038aab845870f1cbe72e10dc762f5daca025..664d759d1e07d660c5fef64f018b1b8cc1bd68a3 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_adder_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_adder_tree is
end tb_tb_common_adder_tree;
@@ -60,5 +60,4 @@ begin
u_sum_w_min_1 : entity work.tb_common_adder_tree generic map ("UNSIGNED", 1, I, 8, 8 - 1);
u_sum_w_wider : entity work.tb_common_adder_tree generic map ("UNSIGNED", 1, I, 8, 8 + 8);
end generate;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
index b24e0b6dacd38a4c5b06961d049e09b0724b9084..02e39d860688f3c5f35845afa3d1cc849bb37bb9 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -24,7 +24,7 @@
-- > run -a
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_create_strobes_from_valid is
end tb_tb_common_create_strobes_from_valid;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index d76e0e916dab65fdcc25e62784fa8e02406fb119..6c7afea6b9142a68b0729686012a5721d72b56eb 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_fanout_tree is
end tb_tb_common_fanout_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
index 64bfdbd9cc9226ae3d796e42feeb727418b6cce0..944149548e07062dabe0f8b3bac56c58c48d00b4 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_multiplexer is
end tb_tb_common_multiplexer;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
index 238655a6c46242c876c819de5a50976a430f2ac6..25bd7e5d65a8e140b1d15a0da5792ae2b9bed037 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_operation_tree is
end tb_tb_common_operation_tree;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
index 4a6aa138cac61b38b8c5527351ec791461b52570..de4876f686a9838fb638afcba64cf7027c6888cd 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_paged_ram_ww_rr is
end tb_tb_common_paged_ram_ww_rr;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
index a7ad45d86a59d33c68a26d34797258534b826947..382fe2714aead42ea1276e6d665beffcc88b5250 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_reinterleave is
generic (
g_dat_w : natural
- );
+ );
end;
architecture rtl of tb_tb_common_reinterleave is
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 309b4f2b8c154f874014d7e79b7fc408992e882b..c33d65fa4a9e8971141e2b96c00df8ef292f0f86 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_reorder_symbol is
end tb_tb_common_reorder_symbol;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
index 297df49506fa275b644a311a1da67b66528c504a..1d9a41bb4b5ae55bf6108034c36b1f41de713893 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl is
end tb_tb_common_rl;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
index 77863f33c08dc86ddb65e1d38873fe6cf8682686..60783b83eeb699899a712120b85a0917f54b9ca7 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.common_pkg.all;
entity tb_tb_common_rl_register is
end tb_tb_common_rl_register;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
index 3fd334e1a175212ea76ce8c0417c682c6b59fa60..638a4d5838432f57216327298de5cc5a3f5c064a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
@@ -20,7 +20,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose: Multi-test bench for common_transpose.vhd
-- Usage:
@@ -33,13 +33,13 @@ end tb_tb_common_transpose;
architecture tb of tb_tb_common_transpose is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_pipeline_shiftreg : NATURAL := 0;
--- | g_pipeline_transpose : NATURAL := 0;
--- | | g_pipeline_hold : NATURAL := 0;
--- | | | g_pipeline_select : NATURAL := 1;
--- | | | | g_nof_data : NATURAL := 3;
--- | | | | | g_data_w : NATURAL := 12
--- | | | | | |
+ -- g_pipeline_shiftreg : NATURAL := 0;
+ -- | g_pipeline_transpose : NATURAL := 0;
+ -- | | g_pipeline_hold : NATURAL := 0;
+ -- | | | g_pipeline_select : NATURAL := 1;
+ -- | | | | g_nof_data : NATURAL := 3;
+ -- | | | | | g_data_w : NATURAL := 12
+ -- | | | | | |
u_4_4 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 4);
u_4_8 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 8);
diff --git a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
index af84a20edf01fb0227a6bd82122d160c92b6d46d..fd5ac65da360c21551ae3c37a5a014be2c10d51b 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_resize.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_resize.vhd and RESIZE_NUM() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_resize is
end tb_tb_resize;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_round.vhd b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
index d6d452e9d10be67b639e327e39fc408373150121..a437ca42b2642eb3097fde892c4ced7d1a414e47 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_round.vhd
@@ -20,7 +20,7 @@
-- Purpose: Multi tb for common_round.vhd and s_round(), u_round() in common_pkg.vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_round is
end tb_tb_round;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index 7ecc20e1be586ac59a46ce8c50b1090c84109256..79e51c5d14e109ba7b742031502e5ae10575a3bf 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, tech_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
--
-- Function: Signed complex multiply
@@ -88,75 +88,75 @@ begin
-- User specificied latency must be >= MegaWizard IP dsp_mult_add2 latency
assert c_pipeline >= c_dsp_latency
report "tech_complex_mult: pipeline value not supported"
- severity FAILURE;
+ severity FAILURE;
-- Propagate in_val with c_pipeline latency
u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ out_dat => out_val
+ );
u_complex_mult : entity tech_mult_lib.tech_complex_mult
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- result_re => result_re,
- result_im => result_im
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_re_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result_re),
- out_dat => out_pr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result_re),
+ out_dat => out_pr
+ );
u_output_im_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result_im),
- out_dat => out_pi
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result_im),
+ out_dat => out_pi
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index 1d2064de811449511e1c7f5d9785b3a976d13b07..3261ebf5e9274c856a806593347b9cb8bfae589b 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
entity common_complex_mult_add is
generic (
@@ -72,68 +72,68 @@ architecture str of common_complex_mult_add is
begin
-- u_complex_mult : entity work.common_complex_mult(stratix4) -- requires sum of g_pipeline >= 3
u_complex_mult : entity work.common_complex_mult -- suits sum of g_pipeline >= 0
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => c_prod_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- out_pr => out_pr,
- out_pi => out_pi
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => c_prod_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ out_pr => out_pr,
+ out_pi => out_pi
+ );
add_inr <= RESIZE_SVEC(out_pr, g_out_p_w); -- Connect the output of the multiplier to the adders input
add_ini <= RESIZE_SVEC(out_pi, g_out_p_w);
u_adder_real : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chr,
- in_b => add_inr,
- result => out_sumr
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chr,
+ in_b => add_inr,
+ result => out_sumr
+ );
u_adder_imag : entity common_lib.common_add_sub
- generic map (
- g_direction => c_direction,
- g_representation => "SIGNED",
- g_pipeline_input => c_pipeline_in,
- g_pipeline_output => c_pipeline_out,
- g_in_dat_w => g_out_p_w,
- g_out_dat_w => g_out_p_w
- )
- port map (
- clk => clk,
- clken => '1',
- sel_add => c_sel_add,
- in_a => in_chi,
- in_b => add_ini,
- result => out_sumi
- );
+ generic map (
+ g_direction => c_direction,
+ g_representation => "SIGNED",
+ g_pipeline_input => c_pipeline_in,
+ g_pipeline_output => c_pipeline_out,
+ g_in_dat_w => g_out_p_w,
+ g_out_dat_w => g_out_p_w
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ sel_add => c_sel_add,
+ in_a => in_chi,
+ in_b => add_ini,
+ result => out_sumi
+ );
end str;
-- The rtl architecture follows the syntax that is given as example by Altera for inferring the DSP blocks.
@@ -154,33 +154,33 @@ begin
process (clk, rst, clken)
begin
if(rst = '1') then -- asynchronous reset
- ar_reg <= (others => '0');
- ai_reg <= (others => '0');
- br_reg <= (others => '0');
- bi_reg <= (others => '0');
- chr_reg <= (others => '0');
- chi_reg <= (others => '0');
- pr <= (others => '0');
- pi <= (others => '0');
- sumr <= (others => '0');
- sumi <= (others => '0');
+ ar_reg <= (others => '0');
+ ai_reg <= (others => '0');
+ br_reg <= (others => '0');
+ bi_reg <= (others => '0');
+ chr_reg <= (others => '0');
+ chi_reg <= (others => '0');
+ pr <= (others => '0');
+ pi <= (others => '0');
+ sumr <= (others => '0');
+ sumi <= (others => '0');
elsif(rising_edge(clk) and clken = '1') then -- rising clock edge
- ar_reg <= signed(in_ar);
- ai_reg <= signed(in_ai);
- br_reg <= signed(in_br);
- bi_reg <= signed(in_bi);
- chr_reg <= signed(in_chr);
- chi_reg <= signed(in_chi);
+ ar_reg <= signed(in_ar);
+ ai_reg <= signed(in_ai);
+ br_reg <= signed(in_br);
+ bi_reg <= signed(in_bi);
+ chr_reg <= signed(in_chr);
+ chi_reg <= signed(in_chi);
- pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w); -- Calculate the real part
- pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w); -- Calculate the imaginary part
+ pr <= RESIZE_NUM((ar_reg * br_reg), c_prod_w) - RESIZE_NUM((ai_reg * bi_reg), c_prod_w); -- Calculate the real part
+ pi <= RESIZE_NUM((ar_reg * bi_reg), c_prod_w) + RESIZE_NUM((ai_reg * br_reg), c_prod_w); -- Calculate the imaginary part
- sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
- sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
- end if;
- end process;
+ sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
+ sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
+ end if;
+end process;
- out_sumr <= std_logic_vector(sumr);
- out_sumi <= std_logic_vector(sumi);
+out_sumr <= std_logic_vector(sumr);
+out_sumi <= std_logic_vector(sumi);
end rtl;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult.vhd b/libraries/base/common_mult/src/vhdl/common_mult.vhd
index e533209b2a9c53ec2a53e523cca4009ddc4b843f..9099b154d305e9e7c519c360045935d091b39c87 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library ieee, common_lib, tech_mult_lib, technology_lib;
-use ieee.std_logic_1164.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
-- Function: Default one or more independent products dependent on g_nof_mult
--
@@ -73,56 +73,56 @@ architecture str of common_mult is
signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
begin
u_mult : entity tech_mult_lib.tech_mult
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_out_p_w => g_out_p_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => g_representation
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- out_p => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => result
+ );
-- Propagate in_val with c_pipeline latency
u_out_val : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => in_val,
- out_dat => out_val
- );
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => in_val,
+ out_dat => out_val
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => g_representation,
- g_pipeline => c_pipeline_output,
- g_in_dat_w => result'LENGTH,
- g_out_dat_w => result'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_dat => std_logic_vector(result),
- out_dat => out_p
- );
+ generic map (
+ g_representation => g_representation,
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => result'LENGTH,
+ g_out_dat_w => result'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_dat => std_logic_vector(result),
+ out_dat => out_p
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
index 9c70318d26846e4a5ced66e809acd9d64cf61149..0c5205312e10bf98a54d4df0c9c4f67c000c24af 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
@@ -34,9 +34,9 @@
--
library ieee, common_lib;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use common_lib.common_pkg.all;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+ use common_lib.common_pkg.all;
entity common_mult_add is
generic (
@@ -55,10 +55,10 @@ entity common_mult_add is
in_b1 : in std_logic_vector(g_in_b_w - 1 downto 0);
out_dat : out std_logic_vector(g_out_dat_w - 1 downto 0)
);
-begin
- -- ASSERT g_pipeline=3
+ begin
+ -- ASSERT g_pipeline=3
-- REPORT "pipeline value not supported"
- -- SEVERITY FAILURE;
+ -- SEVERITY FAILURE;
end common_mult_add;
architecture rtl of common_mult_add is
@@ -96,5 +96,4 @@ begin
gen_sub : if g_add_sub = "SUB" generate
nxt_result <= resize(prod0, c_sum_w) - prod1;
end generate;
-
end rtl;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 397a229a0b61e78e80b832e2d0e7a31606fcc191..44d982a568578b1b1c548a51ca333fac3c20ad8f 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
-- Function: vector low part product + or - vector high part product
-- Call:
@@ -70,44 +70,44 @@ architecture str of common_mult_add2 is
signal result : std_logic_vector(res'range);
begin
u_mult_add2 : entity tech_mult_lib.tech_mult_add2
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index 088c8ccc9de1ba7caac16f910f081742e8edb794..2886ad930c0d9f5a2b0d7ed18ebc7f55b9b24e25 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, technology_lib, tech_mult_lib, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
-- Function: vector low part product + or - vector high part product
-- Call:
@@ -75,46 +75,46 @@ architecture str of common_mult_add4 is
signal result : std_logic_vector(res'range);
begin
u_mult_add4 : entity tech_mult_lib.tech_mult_add4
- generic map(
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_a_w,
- g_in_b_w => g_in_b_w,
- g_res_w => g_res_w,
- g_force_dsp => g_force_dsp,
- g_add_sub0 => g_add_sub0,
- g_add_sub1 => g_add_sub1,
- g_add_sub => g_add_sub,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map(
- rst => rst,
- clk => clk,
- clken => clken,
- in_a => in_a,
- in_b => in_b,
- res => result
- );
+ generic map(
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => result
+ );
------------------------------------------------------------------------------
-- Extra output pipelining
------------------------------------------------------------------------------
u_output_pipe : entity common_lib.common_pipeline -- pipeline output
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline_output,
- g_in_dat_w => res'LENGTH,
- g_out_dat_w => res'length
- )
- port map (
- clk => clk,
- clken => clken,
- in_dat => result,
- out_dat => res
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_output,
+ g_in_dat_w => res'LENGTH,
+ g_out_dat_w => res'length
+ )
+ port map (
+ clk => clk,
+ clken => clken,
+ in_dat => result,
+ out_dat => res
+ );
end str;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index bd0dec1fcb3901fe47473d489bf296e7f83c68a7..75237c9b1ca4155bbc9b6fa201f444ff3f91711f 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_complex_mult is
generic (
@@ -54,8 +54,8 @@ architecture tb of tb_common_complex_mult is
-- g_in_dat_w*2 for multiply and +1 for adder to fit largest im product value
constant c_out_dat_w : natural := g_in_dat_w * 2 + 1;
- constant c_max : integer := 2**(g_in_dat_w - 1) - 1;
- constant c_min : integer := -2**(g_in_dat_w - 1);
+ constant c_max : integer := 2 ** (g_in_dat_w - 1) - 1;
+ constant c_min : integer := -2 ** (g_in_dat_w - 1);
constant c_small : integer := smallest(5, c_max);
@@ -217,76 +217,76 @@ begin
ref_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", c_out_dat_w);
u_result_re : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_re,
- out_dat => result_re_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_re,
+ out_dat => result_re_expected
+ );
u_result_im : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => c_out_dat_w,
- g_out_dat_w => c_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => ref_result_im,
- out_dat => result_im_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => c_out_dat_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => ref_result_im,
+ out_dat => result_im_expected
+ );
u_result_val_expected : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline,
- g_reset_value => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_val,
- out_dat => result_val_expected
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_reset_value => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_val,
+ out_dat => result_val_expected
+ );
u_dut : entity work.common_complex_mult
- generic map (
- g_technology => c_technology,
- g_variant => g_variant,
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => c_out_dat_w,
- g_conjugate_b => g_conjugate_b,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_ar => in_ar,
- in_ai => in_ai,
- in_br => in_br,
- in_bi => in_bi,
- in_val => in_val,
- out_pr => result_re_dut,
- out_pi => result_im_dut,
- out_val => result_val_dut
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => c_out_dat_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ in_val => in_val,
+ out_pr => result_re_dut,
+ out_pi => result_im_dut,
+ out_val => result_val_dut
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index 811b71ec89ccee4aec11d0f464f4c09d4cc58ed4..c77b45d52d840d9c1c2be62f60fbe930124b91c7 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -27,11 +27,11 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_common_mult is
generic (
@@ -49,9 +49,9 @@ architecture tb of tb_common_mult is
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
constant c_nof_mult : natural := 2; -- fixed
- constant c_max_p : integer := 2**(g_in_dat_w - 1) - 1;
+ constant c_max_p : integer := 2 ** (g_in_dat_w - 1) - 1;
constant c_min : integer := -c_max_p;
- constant c_max_n : integer := -2**(g_in_dat_w - 1);
+ constant c_max_n : integer := -2 ** (g_in_dat_w - 1);
constant c_technology : natural := c_tech_select_default;
@@ -146,8 +146,8 @@ begin
proc_common_wait_some_cycles(clk, 50);
-- All combinations
- for I in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
- for J in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
+ for I in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
+ for J in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
in_a <= TO_SVEC(I, g_in_dat_w);
in_b <= TO_SVEC(J, g_in_dat_w);
wait until rising_edge(clk);
@@ -161,36 +161,36 @@ begin
-- pipeline inputs to ease comparison in the Wave window
u_in_a_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_a,
- out_dat => in_a_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_a,
+ out_dat => in_a_p
+ );
u_in_b_pipeline : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => in_b,
- out_dat => in_b_p
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => in_b,
+ out_dat => in_b_p
+ );
gen_wires : for I in 0 to g_nof_mult - 1 generate
-- use same input for all multipliers
@@ -211,124 +211,124 @@ begin
uresult_ip <= uresult_arr_ip(g_out_dat_w - 1 downto 0);
u_sresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_sresult,
- out_dat => sresult_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_sresult,
+ out_dat => sresult_expected
+ );
u_uresult : entity common_lib.common_pipeline
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_uresult,
- out_dat => uresult_expected
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_uresult,
+ out_dat => uresult_expected
+ );
u_sdut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_rtl
+ );
u_udut_rtl : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "RTL",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_rtl
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_rtl
+ );
u_sdut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "SIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => sresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "SIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => sresult_arr_ip
+ );
u_udut_ip : entity work.common_mult
- generic map (
- g_technology => c_technology,
- g_variant => "IP",
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_nof_mult => g_nof_mult,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_output => g_pipeline_output,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a_arr,
- in_b => in_b_arr,
- out_p => uresult_arr_ip
- );
+ generic map (
+ g_technology => c_technology,
+ g_variant => "IP",
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a_arr,
+ in_b => in_b_arr,
+ out_p => uresult_arr_ip
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index b2e150e364f970ccc4aa55aaf78c046ef66dbde4..288a08e01ef84dfa82325cf5cc2c08084a0d171c 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -27,10 +27,10 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_common_mult_add2 is
generic (
@@ -52,9 +52,9 @@ architecture tb of tb_common_mult_add2 is
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
constant c_nof_mult : natural := 2; -- fixed
- constant c_max_p : integer := 2**(g_in_dat_w - 1) - 1;
+ constant c_max_p : integer := 2 ** (g_in_dat_w - 1) - 1;
constant c_min : integer := -c_max_p;
- constant c_max_n : integer := -2**(g_in_dat_w - 1);
+ constant c_max_n : integer := -2 ** (g_in_dat_w - 1);
function func_result(in_a0, in_b0, in_a1, in_b1 : std_logic_vector) return std_logic_vector is
-- From mti_numeric_std.vhd follows:
@@ -76,8 +76,8 @@ architecture tb of tb_common_mult_add2 is
if g_add_sub = "ADD" then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) + v_a1 * v_b1; end if;
if g_add_sub = "SUB" then v_result := RESIZE_NUM(v_a0 * v_b0, c_res_w) - v_a1 * v_b1; end if;
-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
- if v_result > 2**(g_out_dat_w - 1) - 1 then v_result := v_result - 2**g_out_dat_w; end if;
- if v_result < - 2**(g_out_dat_w - 1) then v_result := v_result + 2**g_out_dat_w; end if;
+ if v_result > 2 ** (g_out_dat_w - 1) - 1 then v_result := v_result - 2 ** g_out_dat_w; end if;
+ if v_result < - 2 ** (g_out_dat_w - 1) then v_result := v_result + 2 ** g_out_dat_w; end if;
return std_logic_vector(v_result);
end;
@@ -151,10 +151,10 @@ begin
end loop;
-- All combinations
- for I in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
- for J in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
- for K in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
- for L in - 2**(g_in_dat_w - 1) to 2**(g_in_dat_w - 1) - 1 loop
+ for I in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
+ for J in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
+ for K in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
+ for L in - 2 ** (g_in_dat_w - 1) to 2 ** (g_in_dat_w - 1) - 1 loop
in_a0 <= TO_SVEC(I, g_in_dat_w);
in_b0 <= TO_SVEC(J, g_in_dat_w);
in_a1 <= TO_SVEC(K, g_in_dat_w);
@@ -175,42 +175,42 @@ begin
out_result <= func_result(in_a0, in_b0, in_a1, in_b1);
u_result : entity common_lib.common_pipeline
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_reset_value => 0,
- g_in_dat_w => g_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_dat => out_result,
- out_dat => result_expected
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_reset_value => 0,
+ g_in_dat_w => g_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_dat => out_result,
+ out_dat => result_expected
+ );
u_dut_rtl : entity work.common_mult_add2
- generic map (
- g_in_a_w => g_in_dat_w,
- g_in_b_w => g_in_dat_w,
- g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
- g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
- g_add_sub => g_add_sub,
- g_nof_mult => 2,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_product => g_pipeline_product,
- g_pipeline_adder => g_pipeline_adder,
- g_pipeline_output => g_pipeline_output
- )
- port map (
- rst => '0',
- clk => clk,
- clken => '1',
- in_a => in_a,
- in_b => in_b,
- res => result_rtl
- );
+ generic map (
+ g_in_a_w => g_in_dat_w,
+ g_in_b_w => g_in_dat_w,
+ g_res_w => g_out_dat_w, -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp => g_force_dsp, -- not applicable for 'rtl'
+ g_add_sub => g_add_sub,
+ g_nof_mult => 2,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => '0',
+ clk => clk,
+ clken => '1',
+ in_a => in_a,
+ in_b => in_b,
+ res => result_rtl
+ );
p_verify : process(rst, clk)
begin
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index a8b7dfd246c23d01cad3ff677bd4397cfa55d4c2..3c540b41a9eb45e70277842e3332be5c6754cfc9 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -26,9 +26,9 @@
-- --------------------------------------------------------------------------
library IEEE, technology_lib;
-use IEEE.std_logic_1164.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity tb_tb_common_complex_mult is
end tb_tb_common_complex_mult;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
index d08b84661010615219ddb40fb60a75f2f8d6e2ce..4728866d9450a648e603fa463bf093b679f5550f 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
@@ -24,7 +24,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_tb_common_mult is
end tb_tb_common_mult;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 7163a9b310a821795ca5beac075d067d72bf765b..80e5681f9ae2b4635c7e797164e2ce6c110e854c 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -73,11 +73,11 @@
-- . out_sosi.re(g_buf_dat_w/2-1: 0)
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diag_block_gen is
generic (
@@ -113,10 +113,10 @@ architecture rtl of diag_block_gen is
sop : std_logic;
eop : std_logic;
rd_ena : std_logic;
- samples_cnt : natural range 0 to 2**c_diag_bg_gapsize_w - 1;
- blocks_cnt : natural range 0 to 2**c_diag_bg_blocks_per_sync_w - 1;
+ samples_cnt : natural range 0 to 2 ** c_diag_bg_gapsize_w - 1;
+ blocks_cnt : natural range 0 to 2 ** c_diag_bg_blocks_per_sync_w - 1;
bsn_cnt : std_logic_vector(c_diag_bg_bsn_init_w - 1 downto 0); -- = c_dp_stream_bsn_w
- mem_cnt : natural range 0 to 2**g_buf_addr_w - 1;
+ mem_cnt : natural range 0 to 2 ** g_buf_addr_w - 1;
state : state_type; -- The state machine.
end record;
@@ -124,175 +124,175 @@ architecture rtl of diag_block_gen is
signal out_sosi_i : t_dp_sosi := c_dp_sosi_rst; -- Signal used to assign reset values to output
signal xon_reg : std_logic := '0';
begin
- -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
- xon_reg <= out_siso.xon when rising_edge(clk);
+ -- xon is not clk cycle timing critical, so can use register xon to ease timing closure
+ xon_reg <= out_siso.xon when rising_edge(clk);
- p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
- variable v : reg_type;
- variable v_samples_per_packet : natural;
- variable v_gapsize : natural;
- variable v_blocks_per_sync : natural;
- variable v_mem_low_adrs : natural;
- variable v_mem_high_adrs : natural;
- begin
- v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
- v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
- v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
- v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
- v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
+ p_comb : process(r, rst, ctrl, en_sync, out_siso, xon_reg)
+ variable v : reg_type;
+ variable v_samples_per_packet : natural;
+ variable v_gapsize : natural;
+ variable v_blocks_per_sync : natural;
+ variable v_mem_low_adrs : natural;
+ variable v_mem_high_adrs : natural;
+ begin
+ v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
+ v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
+ v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
+ v_mem_low_adrs := TO_UINT(r.ctrl_hold.mem_low_adrs);
+ v_mem_high_adrs := TO_UINT(r.ctrl_hold.mem_high_adrs);
- v := r; -- default hold all r fields
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
+ v := r; -- default hold all r fields
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
- -- Control block generator enable
- if ctrl.enable_sync = '0' then
- -- apply ctrl.enable immediately
+ -- Control block generator enable
+ if ctrl.enable_sync = '0' then
+ -- apply ctrl.enable immediately
+ v.blk_en := ctrl.enable;
+ else
+ -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
+ if en_sync = '1' then
v.blk_en := ctrl.enable;
- else
- -- keep blk_en and apply ctrl.enable (on or off) at input sync pulse
- if en_sync = '1' then
- v.blk_en := ctrl.enable;
- end if;
end if;
+ end if;
- -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
- if r.eop = '1' then
- v.blk_sync := '0';
- end if;
+ -- The pulse sync is high at the sop of the first block, the block sync is high during the entire block until the eop
+ if r.eop = '1' then
+ v.blk_sync := '0';
+ end if;
- -- Increment the block sequence number counter after each block
- if r.eop = '1' then
- v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
- end if;
+ -- Increment the block sequence number counter after each block
+ if r.eop = '1' then
+ v.bsn_cnt := incr_uvec(r.bsn_cnt, 1);
+ end if;
- case r.state is
- when s_idle =>
- v.blk_xon := xon_reg;
- v.blk_sync := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.mem_cnt := v_mem_low_adrs;
- if r.blk_en = '1' then -- Wait until enabled
- if xon_reg = '1' then -- Wait until XON is 1
- v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
- v.bsn_cnt := ctrl.bsn_init;
- v.rd_ena := '1';
- v.state := s_block;
- end if;
+ case r.state is
+ when s_idle =>
+ v.blk_xon := xon_reg;
+ v.blk_sync := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.mem_cnt := v_mem_low_adrs;
+ if r.blk_en = '1' then -- Wait until enabled
+ if xon_reg = '1' then -- Wait until XON is 1
+ v.ctrl_hold := ctrl; -- hold new control settings while BG is enabled
+ v.bsn_cnt := ctrl.bsn_init;
+ v.rd_ena := '1';
+ v.state := s_block;
end if;
+ end if;
- when s_block =>
- if out_siso.ready = '1' then
-
- v.rd_ena := '1'; -- read next data
- if r.samples_cnt = 0 and r.blocks_cnt = 0 then
- v.pls_sync := '1'; -- Always start with a pulse sync
- v.blk_sync := '1';
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt = 0 then
- v.sop := '1';
- v.samples_cnt := v.samples_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.blocks_cnt := r.blocks_cnt + 1;
- elsif r.samples_cnt >= v_samples_per_packet - 1 then
- v.eop := '1';
- v.samples_cnt := 0;
- v.rd_ena := '0';
- v.state := s_gap;
- else
- v.samples_cnt := r.samples_cnt + 1;
- end if;
- v.valid := '1'; -- output pending data
-
- if r.mem_cnt >= v_mem_high_adrs then
- v.mem_cnt := v_mem_low_adrs;
- else
- v.mem_cnt := r.mem_cnt + 1;
- end if;
+ when s_block =>
+ if out_siso.ready = '1' then
- if v.eop = '1' and r.blk_en = '0' then
- v.state := s_idle; -- accept disable after eop, not during block
- end if;
- end if; -- out_siso.ready='1'
- if r.eop = '1' then
- v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
- end if;
-
- when s_gap =>
- if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.rd_ena := '1'; -- read next data
+ if r.samples_cnt = 0 and r.blocks_cnt = 0 then
+ v.pls_sync := '1'; -- Always start with a pulse sync
+ v.blk_sync := '1';
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt = 0 then
+ v.sop := '1';
+ v.samples_cnt := v.samples_cnt + 1;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := 0;
- v.rd_ena := '1';
- v.state := s_block;
- elsif r.samples_cnt >= v_gapsize-1 then
+ elsif r.samples_cnt >= v_samples_per_packet - 1 and v_gapsize = 0 then
+ v.eop := '1';
v.samples_cnt := 0;
v.blocks_cnt := r.blocks_cnt + 1;
- v.rd_ena := '1';
- v.state := s_block;
+ elsif r.samples_cnt >= v_samples_per_packet - 1 then
+ v.eop := '1';
+ v.samples_cnt := 0;
+ v.rd_ena := '0';
+ v.state := s_gap;
else
v.samples_cnt := r.samples_cnt + 1;
end if;
+ v.valid := '1'; -- output pending data
+
+ if r.mem_cnt >= v_mem_high_adrs then
+ v.mem_cnt := v_mem_low_adrs;
+ else
+ v.mem_cnt := r.mem_cnt + 1;
+ end if;
- if r.blk_en = '0' then
- v.state := s_idle;
+ if v.eop = '1' and r.blk_en = '0' then
+ v.state := s_idle; -- accept disable after eop, not during block
end if;
- v.blk_xon := xon_reg;
+ end if; -- out_siso.ready='1'
+ if r.eop = '1' then
+ v.blk_xon := xon_reg; -- accept XOFF after eop, not during block
+ end if;
+
+ when s_gap =>
+ if r.samples_cnt >= v_gapsize-1 and r.blocks_cnt >= v_blocks_per_sync - 1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.rd_ena := '1';
+ v.state := s_block;
+ elsif r.samples_cnt >= v_gapsize-1 then
+ v.samples_cnt := 0;
+ v.blocks_cnt := r.blocks_cnt + 1;
+ v.rd_ena := '1';
+ v.state := s_block;
+ else
+ v.samples_cnt := r.samples_cnt + 1;
+ end if;
- when others =>
+ if r.blk_en = '0' then
v.state := s_idle;
- end case;
+ end if;
+ v.blk_xon := xon_reg;
- if rst = '1' then
- v.ctrl_hold := c_diag_block_gen_rst;
- v.blk_en := '0';
- v.blk_xon := '0';
- v.blk_sync := '0';
- v.pls_sync := '0';
- v.valid := '0';
- v.sop := '0';
- v.eop := '0';
- v.rd_ena := '0';
- v.samples_cnt := 0;
- v.blocks_cnt := 0;
- v.bsn_cnt := (others => '0');
- v.mem_cnt := 0;
- v.state := s_idle;
- end if;
+ when others =>
+ v.state := s_idle;
+ end case;
- rin <= v;
- end process;
+ if rst = '1' then
+ v.ctrl_hold := c_diag_block_gen_rst;
+ v.blk_en := '0';
+ v.blk_xon := '0';
+ v.blk_sync := '0';
+ v.pls_sync := '0';
+ v.valid := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.rd_ena := '0';
+ v.samples_cnt := 0;
+ v.blocks_cnt := 0;
+ v.bsn_cnt := (others => '0');
+ v.mem_cnt := 0;
+ v.state := s_idle;
+ end if;
- p_regs : process(rst, clk)
- begin
- if rising_edge(clk) then
- r <= rin;
- end if;
- end process;
+ rin <= v;
+ end process;
+
+ p_regs : process(rst, clk)
+ begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+ end process;
- -- Connect to the outside world
- out_sosi_i.sop <= r.sop and r.blk_xon;
- out_sosi_i.eop <= r.eop and r.blk_xon;
- out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
- out_sosi_i.valid <= r.valid and r.blk_xon;
- out_sosi_i.bsn <= r.bsn_cnt;
- out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
- out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
- out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
+ -- Connect to the outside world
+ out_sosi_i.sop <= r.sop and r.blk_xon;
+ out_sosi_i.eop <= r.eop and r.blk_xon;
+ out_sosi_i.sync <= r.pls_sync and r.blk_xon when g_blk_sync = false else r.blk_sync and r.blk_xon;
+ out_sosi_i.valid <= r.valid and r.blk_xon;
+ out_sosi_i.bsn <= r.bsn_cnt;
+ out_sosi_i.re <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w / 2 - 1 downto 0)); -- treat as signed
+ out_sosi_i.im <= RESIZE_DP_DSP_DATA(buf_rddat(g_buf_dat_w - 1 downto g_buf_dat_w / 2)); -- treat as signed
+ out_sosi_i.data <= RESIZE_DP_DATA( buf_rddat(g_buf_dat_w - 1 downto 0)); -- treat as unsigned
- out_sosi <= out_sosi_i;
- buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
- buf_rden <= r.rd_ena;
+ out_sosi <= out_sosi_i;
+ buf_addr <= TO_UVEC(r.mem_cnt, g_buf_addr_w);
+ buf_rden <= r.rd_ena;
- ctrl_hold <= r.ctrl_hold;
+ ctrl_hold <= r.ctrl_hold;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 018ca44aef18e5794d40feaa22ddabc49ca2b3a5..5ca8ba585d17b936f917217f9477ec36c81127e0 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
entity diag_block_gen_reg is
generic (
@@ -58,87 +58,88 @@ begin
p_mm_reg : process (mm_rst, mm_clk)
begin
if(mm_rst = '1') then
- mm_miso <= c_mem_miso_rst;
- mm_bg_ctrl <= g_diag_block_gen_rst;
+ mm_miso <= c_mem_miso_rst;
+ mm_bg_ctrl <= g_diag_block_gen_rst;
elsif(rising_edge(mm_clk)) then
- -- Read access defaults
- mm_miso.rdval <= '0';
- -- Write access: set register value
- if(mm_mosi.wr = '1') then
- case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
- when 0 =>
- mm_bg_ctrl.enable <= mm_mosi.wrdata(0);
- mm_bg_ctrl.enable_sync <= mm_mosi.wrdata(1);
- when 1 =>
- mm_bg_ctrl.samples_per_packet <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w - 1 downto 0);
- when 2 =>
- mm_bg_ctrl.blocks_per_sync <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w - 1 downto 0);
- when 3 =>
- mm_bg_ctrl.gapsize <= mm_mosi.wrdata(c_diag_bg_gapsize_w - 1 downto 0);
- when 4 =>
- mm_bg_ctrl.mem_low_adrs <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w - 1 downto 0);
- when 5 =>
- mm_bg_ctrl.mem_high_adrs <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w - 1 downto 0);
- when 6 =>
- mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
- when 7 =>
- mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
- when others => null; -- not used MM addresses
- end case;
- -- Read access: get register value
- elsif mm_mosi.rd = '1' then
- mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
- mm_miso.rdval <= '1';
- case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
- -- Read Block Sync
- when 0 =>
- mm_miso.rddata(0) <= mm_bg_ctrl.enable;
- mm_miso.rddata(1) <= mm_bg_ctrl.enable_sync;
- when 1 =>
- mm_miso.rddata(c_diag_bg_samples_per_packet_w - 1 downto 0) <= mm_bg_ctrl.samples_per_packet;
- when 2 =>
- mm_miso.rddata(c_diag_bg_blocks_per_sync_w - 1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
- when 3 =>
- mm_miso.rddata(c_diag_bg_gapsize_w - 1 downto 0) <= mm_bg_ctrl.gapsize;
- when 4 =>
- mm_miso.rddata(c_diag_bg_mem_low_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
- when 5 =>
- mm_miso.rddata(c_diag_bg_mem_high_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
- when 6 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
- when 7 =>
- mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
- when others => null; -- not used MM addresses
- end case;
- end if;
- end if;
- end process;
+ -- Read access defaults
+ mm_miso.rdval <= '0';
+ -- Write access: set register value
+ if(mm_mosi.wr = '1') then
+ case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
+ when 0 =>
+ mm_bg_ctrl.enable <= mm_mosi.wrdata(0);
+ mm_bg_ctrl.enable_sync <= mm_mosi.wrdata(1);
+ when 1 =>
+ mm_bg_ctrl.samples_per_packet <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w - 1 downto 0);
+ when 2 =>
+ mm_bg_ctrl.blocks_per_sync <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w - 1 downto 0);
+ when 3 =>
+ mm_bg_ctrl.gapsize <= mm_mosi.wrdata(c_diag_bg_gapsize_w - 1 downto 0);
+ when 4 =>
+ mm_bg_ctrl.mem_low_adrs <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w - 1 downto 0);
+ when 5 =>
+ mm_bg_ctrl.mem_high_adrs <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w - 1 downto 0);
+ when 6 =>
+ mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
+ when 7 =>
+ mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
+ when others => null; -- not used MM addresses
+ end case;
+ -- Read access: get register value
+ elsif mm_mosi.rd = '1' then
+ mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
+ mm_miso.rdval <= '1';
+ case TO_UINT(mm_mosi.address(c_adrs_width - 1 downto 0)) is
+ -- Read Block Sync
+ when 0 =>
+ mm_miso.rddata(0) <= mm_bg_ctrl.enable;
+ mm_miso.rddata(1) <= mm_bg_ctrl.enable_sync;
+ when 1 =>
+ mm_miso.rddata(c_diag_bg_samples_per_packet_w - 1 downto 0) <= mm_bg_ctrl.samples_per_packet;
+ when 2 =>
+ mm_miso.rddata(c_diag_bg_blocks_per_sync_w - 1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
+ when 3 =>
+ mm_miso.rddata(c_diag_bg_gapsize_w - 1 downto 0) <= mm_bg_ctrl.gapsize;
+ when 4 =>
+ mm_miso.rddata(c_diag_bg_mem_low_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
+ when 5 =>
+ mm_miso.rddata(c_diag_bg_mem_high_adrs_w - 1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
+ when 6 =>
+ mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
+ when 7 =>
+ mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
+ when others => null; -- not used MM addresses
+ end case;
+ end if;
+end if;
- ------------------------------------------------------------------------------
- -- Transfer register value between mm_clk and dp_clk domain.
- -- If the function of the register ensures that the value will not be used
- -- immediately when it was set, then the transfer between the clock domains
- -- can be done by wires only. Otherwise if the change in register value can
- -- have an immediate effect then the bit or word value needs to be transfered
- -- using:
- --
- -- . common_async --> for single-bit level signal
- -- . common_spulse --> for single-bit pulse signal
- -- . common_reg_cross_domain --> for a multi-bit (a word) signal
- --
- -- Typically always use a crossing component for the single bit signals (to
- -- be on the save side) and only use a crossing component for the word
- -- signals if it is necessary (to avoid using more logic than necessary).
- ------------------------------------------------------------------------------
+end process;
+
+------------------------------------------------------------------------------
+-- Transfer register value between mm_clk and dp_clk domain.
+-- If the function of the register ensures that the value will not be used
+-- immediately when it was set, then the transfer between the clock domains
+-- can be done by wires only. Otherwise if the change in register value can
+-- have an immediate effect then the bit or word value needs to be transfered
+-- using:
+--
+-- . common_async --> for single-bit level signal
+-- . common_spulse --> for single-bit pulse signal
+-- . common_reg_cross_domain --> for a multi-bit (a word) signal
+--
+-- Typically always use a crossing component for the single bit signals (to
+-- be on the save side) and only use a crossing component for the word
+-- signals if it is necessary (to avoid using more logic than necessary).
+------------------------------------------------------------------------------
- no_cross : if g_cross_clock_domain = false generate
- dp_bg_ctrl <= mm_bg_ctrl;
- end generate; -- no_cross
+no_cross : if g_cross_clock_domain = false generate
+ dp_bg_ctrl <= mm_bg_ctrl;
+end generate; -- no_cross
- gen_crossing : if g_cross_clock_domain = true generate
- -- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
- -- the other diag BG control fields are stable as well
- u_bg_enable : entity common_lib.common_async
+gen_crossing : if g_cross_clock_domain = true generate
+ -- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
+ -- the other diag BG control fields are stable as well
+ u_bg_enable : entity common_lib.common_async
generic map (
g_rst_level => '0'
)
@@ -148,14 +149,14 @@ begin
din => mm_bg_ctrl.enable,
dout => dp_bg_ctrl.enable
);
- dp_bg_ctrl.enable_sync <= mm_bg_ctrl.enable_sync;
- dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
- dp_bg_ctrl.blocks_per_sync <= mm_bg_ctrl.blocks_per_sync;
- dp_bg_ctrl.gapsize <= mm_bg_ctrl.gapsize;
- dp_bg_ctrl.mem_low_adrs <= mm_bg_ctrl.mem_low_adrs;
- dp_bg_ctrl.mem_high_adrs <= mm_bg_ctrl.mem_high_adrs;
- dp_bg_ctrl.bsn_init <= mm_bg_ctrl.bsn_init;
- end generate; -- gen_crossing
+ dp_bg_ctrl.enable_sync <= mm_bg_ctrl.enable_sync;
+ dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
+ dp_bg_ctrl.blocks_per_sync <= mm_bg_ctrl.blocks_per_sync;
+ dp_bg_ctrl.gapsize <= mm_bg_ctrl.gapsize;
+ dp_bg_ctrl.mem_low_adrs <= mm_bg_ctrl.mem_low_adrs;
+ dp_bg_ctrl.mem_high_adrs <= mm_bg_ctrl.mem_high_adrs;
+ dp_bg_ctrl.bsn_init <= mm_bg_ctrl.bsn_init;
+end generate; -- gen_crossing
- bg_ctrl <= dp_bg_ctrl;
+bg_ctrl <= dp_bg_ctrl;
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_bypass.vhd b/libraries/base/diag/src/vhdl/diag_bypass.vhd
index 506398a3d59c6fdb2bcd1ba0deeea9033a145842..dc8a7771cca9a5449c46e13114911bbaabec5844 100644
--- a/libraries/base/diag/src/vhdl/diag_bypass.vhd
+++ b/libraries/base/diag/src/vhdl/diag_bypass.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity diag_bypass is
generic (
@@ -84,7 +84,7 @@ begin
end process;
output_switch_proc : process (bypass_en, mod_out_dat_x, mod_out_val, mod_out_sync,
- in_dat_x, in_val, in_sync, mod_out_dat_y, in_dat_y)
+ in_dat_x, in_val, in_sync, mod_out_dat_y, in_dat_y)
begin
nxt_out_dat_x <= RESIZE_SVEC(mod_out_dat_x, out_dat_x'length);
nxt_out_dat_y <= RESIZE_SVEC(mod_out_dat_y, out_dat_y'length);
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index f0211b988e02efcb26a0db4e683659a837eb458c..59e59d16c3117b5fbf5a76027818c6b3b313ee44 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -44,12 +44,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer is
generic (
@@ -85,109 +85,112 @@ architecture rtl of diag_data_buffer is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
-
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
-
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
- init_sl => '0');
-
- signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
-
- signal rd_last : std_logic;
- signal wr_sync : std_logic;
-
- signal wr_done : std_logic;
- signal nxt_wr_done : std_logic;
-
- signal wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
- signal nxt_wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
- signal wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
- signal nxt_wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
- signal wr_en : std_logic;
- signal nxt_wr_en : std_logic;
-
- signal reg_rd_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
- signal reg_slv : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
-
- signal sync_cnt_clr : std_logic := '0';
- signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
- signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0');
+
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0');
+
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_reg_nof_dat, -- 1: word_cnt; 0:sync_cnt
+ init_sl => '0');
+
+ signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+
+ signal rd_last : std_logic;
+ signal wr_sync : std_logic;
+
+ signal wr_done : std_logic;
+ signal nxt_wr_done : std_logic;
+
+ signal wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
+ signal nxt_wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
+ signal wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
+ signal nxt_wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
+ signal wr_en : std_logic;
+ signal nxt_wr_en : std_logic;
+
+ signal reg_rd_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
+ signal reg_slv : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
+
+ signal sync_cnt_clr : std_logic := '0';
+ signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
+ signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
begin
- assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
+ assert c_mm_factor = 2 ** true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
ram_mm_miso <= i_ram_mm_miso;
rd_last <= '1' when unsigned(ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0)) = c_nof_data_mm - 1 and ram_mm_mosi.rd = '1' else '0';
-- Determine the write trigger
- use_rd_last : if g_use_in_sync = false generate
+ use_rd_last : if g_use_in_sync = false generate
u_wr_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => wr_sync
- );
- end generate;
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => wr_sync
+ );
+ end generate;
use_in_sync : if g_use_in_sync = true generate
sync_cnt_clr <= rd_last; -- clear sync_cnt register on read of last data
- wr_sync <= in_sync;
- end generate;
-
- p_st_clk : process (st_clk, st_rst)
- begin
- if st_rst = '1' then
- wr_data <= (others => '0');
- wr_addr <= (others => '0');
- wr_en <= '0';
- wr_done <= '0';
- elsif rising_edge(st_clk) then
- wr_data <= nxt_wr_data;
- wr_addr <= nxt_wr_addr;
- wr_en <= nxt_wr_en;
- wr_done <= nxt_wr_done;
- end if;
- end process;
-
- -- Write access control
- nxt_wr_data <= in_data;
- nxt_wr_en <= in_val and not nxt_wr_done;
-
- p_wr_addr : process (wr_done, wr_addr, wr_sync, wr_en)
- begin
- nxt_wr_done <= wr_done;
- nxt_wr_addr <= wr_addr;
- if wr_sync = '1' then
- nxt_wr_done <= '0';
- nxt_wr_addr <= (others => '0');
- elsif wr_en = '1' then
- if unsigned(wr_addr) = g_nof_data - 1 then
- nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
- else
- nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
- end if;
+wr_sync <= in_sync;
+end generate;
+
+p_st_clk : process (st_clk, st_rst)
+begin
+ if st_rst = '1' then
+ wr_data <= (others => '0');
+ wr_addr <= (others => '0');
+ wr_en <= '0';
+ wr_done <= '0';
+ elsif rising_edge(st_clk) then
+ wr_data <= nxt_wr_data;
+ wr_addr <= nxt_wr_addr;
+ wr_en <= nxt_wr_en;
+ wr_done <= nxt_wr_done;
+ end if;
+end process;
+
+-- Write access control
+nxt_wr_data <= in_data;
+nxt_wr_en <= in_val and not nxt_wr_done;
+
+p_wr_addr : process (wr_done, wr_addr, wr_sync, wr_en)
+begin
+ nxt_wr_done <= wr_done;
+ nxt_wr_addr <= wr_addr;
+ if wr_sync = '1' then
+ nxt_wr_done <= '0';
+ nxt_wr_addr <= (others => '0');
+ elsif wr_en = '1' then
+ if unsigned(wr_addr) = g_nof_data - 1 then
+ nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ else
+ nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
end if;
- end process;
+ end if;
+end process;
- u_buf : entity common_lib.common_ram_crw_crw_ratio
+u_buf : entity common_lib.common_ram_crw_crw_ratio
generic map (
g_technology => g_technology,
g_ram_a => c_buf_mm,
@@ -216,7 +219,7 @@ begin
rd_val_b => open
);
- u_reg : entity common_lib.common_reg_r_w_dc
+u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_reg => c_reg
)
@@ -238,9 +241,9 @@ begin
out_reg => open
);
- reg_slv <= word_cnt & sync_cnt;
+reg_slv <= word_cnt & sync_cnt;
- u_word_cnt : entity common_lib.common_counter
+u_word_cnt : entity common_lib.common_counter
port map (
rst => st_rst,
clk => st_clk,
@@ -249,7 +252,7 @@ begin
count => word_cnt
);
- u_sync_cnt : entity common_lib.common_counter
+u_sync_cnt : entity common_lib.common_counter
port map (
rst => st_rst,
clk => st_clk,
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index 278e607ea21c93de95a9e902c8e8020b5a4aa49a..24f86e2d514d006c03ee3b82461db17c4652ff8e 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -65,12 +65,12 @@
-- a c_word_w parts.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_data_buffer_dev is
generic (
@@ -108,62 +108,65 @@ architecture rtl of diag_data_buffer_dev is
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
constant g_data_mm_w : natural := g_data_w / c_mm_factor;
- constant c_buf_mm : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_data_mm),
- dat_w => g_data_mm_w,
- nof_dat => c_nof_data_mm,
- init_sl => '0');
-
- constant c_buf_st : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_data),
- dat_w => g_data_w,
- nof_dat => g_nof_data,
- init_sl => '0');
-
- constant c_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_db_dev_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
- init_sl => '0');
-
- signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
-
- signal rd_last : std_logic;
- signal rd_last_st : std_logic;
- signal wr_sync : std_logic;
-
- signal wr_done : std_logic;
- signal nxt_wr_done : std_logic;
-
- signal wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
- signal nxt_wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
- signal wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
- signal nxt_wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
- signal wr_en : std_logic;
- signal nxt_wr_en : std_logic;
-
- signal reg_rd_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
- signal reg_wr_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
- signal reg_slv_rd : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
- signal reg_slv_wr : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
-
- signal arm_enable : std_logic := '0';
- signal sync_cnt_clr : std_logic := '0';
- signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
- signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- signal valid_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- signal reg_sync_delay : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
-
- type state_type is (s_idle, s_sync_count, s_wait_for_rd_last, s_armed);
-
- type reg_type is record
- wr_sync : std_logic;
- state : state_type; -- The state machine.
- end record;
-
- signal r, rin : reg_type;
+ constant c_buf_mm : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_data_mm),
+ dat_w => g_data_mm_w,
+ nof_dat => c_nof_data_mm,
+ init_sl => '0');
+
+ constant c_buf_st : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_data),
+ dat_w => g_data_w,
+ nof_dat => g_nof_data,
+ init_sl => '0');
+
+ constant c_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_db_dev_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_db_dev_reg_nof_dat, -- 3: reg_sync_delay 2: valid_cnt 1: word_cnt; 0:sync_cnt
+ init_sl => '0');
+
+ signal i_ram_mm_miso : t_mem_miso := c_mem_miso_rst; -- used to avoid vsim-8684 error "No drivers exist" for the unused fields
+
+ signal rd_last : std_logic;
+ signal rd_last_st : std_logic;
+ signal wr_sync : std_logic;
+
+ signal wr_done : std_logic;
+ signal nxt_wr_done : std_logic;
+
+ signal wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
+ signal nxt_wr_data : std_logic_vector(c_buf_st.dat_w - 1 downto 0);
+ signal wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
+ signal nxt_wr_addr : std_logic_vector(c_buf_st.adr_w - 1 downto 0);
+ signal wr_en : std_logic;
+ signal nxt_wr_en : std_logic;
+
+ signal reg_rd_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
+ signal reg_wr_arr : std_logic_vector(c_reg.nof_dat - 1 downto 0);
+ signal reg_slv_rd : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
+ signal reg_slv_wr : std_logic_vector(c_reg.nof_dat * c_word_w - 1 downto 0);
+
+ signal arm_enable : std_logic := '0';
+ signal sync_cnt_clr : std_logic := '0';
+ signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
+ signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ signal valid_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ signal reg_sync_delay : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+
+ type state_type is (s_idle, s_sync_count, s_wait_for_rd_last, s_armed);
+
+ type reg_type is record
+ wr_sync : std_logic;
+ state : state_type; -- The state machine.
+ end record;
+
+ signal r, rin : reg_type;
begin
- assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
+ assert c_mm_factor = 2 ** true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
out_wr_done <= nxt_wr_done;
@@ -172,118 +175,119 @@ begin
rd_last <= '1' when unsigned(ram_mm_mosi.address(c_buf_mm.adr_w - 1 downto 0)) = c_nof_data_mm - 1 and ram_mm_mosi.rd = '1' else '0';
u_rd_last_clock_cross : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => rd_last,
- out_rst => st_rst,
- out_clk => st_clk,
- out_pulse => rd_last_st
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => rd_last,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_pulse => rd_last_st
+ );
-- Determine the write trigger in NON-SYNC MODE
- use_rd_last : if g_use_in_sync = false generate
+ use_rd_last : if g_use_in_sync = false generate
wr_sync <= rd_last_st;
- end generate;
+end generate;
- -- Determine the write trigger in SYNC MODE and ARM MODE
+-- Determine the write trigger in SYNC MODE and ARM MODE
use_in_sync : if g_use_in_sync = true generate
- comb : process(st_rst, r, in_sync, rd_last_st, reg_sync_delay, arm_enable, valid_cnt)
- variable v : reg_type;
- begin
- v := r;
-
- v.wr_sync := '0';
- case r.state is
-
- when s_idle =>
- if arm_enable = '1' then
- v.state := s_armed;
- end if;
-
- when s_armed =>
- if (in_sync = '1' and TO_UINT(reg_sync_delay) = 1) then
- v.wr_sync := '1';
- v.state := s_wait_for_rd_last;
- elsif(in_sync = '1' and TO_UINT(reg_sync_delay) > 1) then
- v.state := s_sync_count;
- end if;
-
- when s_sync_count =>
- if ((TO_UINT(valid_cnt) + 2) >= TO_UINT(reg_sync_delay)) then
- v.wr_sync := '1';
- v.state := s_wait_for_rd_last;
- end if;
-
- when s_wait_for_rd_last =>
- if rd_last_st = '1' then
- v.state := s_idle;
- elsif arm_enable = '1' then
- v.state := s_armed;
- end if;
-
- when others =>
- v.state := s_idle;
- end case;
- if st_rst = '1' then
- v.wr_sync := '0';
- v.state := s_idle;
- end if;
+ comb : process(st_rst, r, in_sync, rd_last_st, reg_sync_delay, arm_enable, valid_cnt)
+ variable v : reg_type;
+ begin
+ v := r;
+
+ v.wr_sync := '0';
+ case r.state is
+
+ when s_idle =>
+ if arm_enable = '1' then
+ v.state := s_armed;
+ end if;
+
+ when s_armed =>
+ if (in_sync = '1' and TO_UINT(reg_sync_delay) = 1) then
+ v.wr_sync := '1';
+ v.state := s_wait_for_rd_last;
+ elsif(in_sync = '1' and TO_UINT(reg_sync_delay) > 1) then
+ v.state := s_sync_count;
+ end if;
+
+ when s_sync_count =>
+ if ((TO_UINT(valid_cnt) + 2) >= TO_UINT(reg_sync_delay)) then
+ v.wr_sync := '1';
+ v.state := s_wait_for_rd_last;
+ end if;
+
+ when s_wait_for_rd_last =>
+ if rd_last_st = '1' then
+ v.state := s_idle;
+ elsif arm_enable = '1' then
+ v.state := s_armed;
+ end if;
- rin <= v;
- end process comb;
+ when others =>
+ v.state := s_idle;
+ end case;
- regs : process(st_clk)
- begin
- if rising_edge(st_clk) then
- r <= rin;
- end if;
- end process;
+ if st_rst = '1' then
+ v.wr_sync := '0';
+ v.state := s_idle;
+ end if;
- -- Choose between SYNC MODE and ARM MODE.
- wr_sync <= in_sync when TO_UINT(reg_sync_delay) = 0 else r.wr_sync;
- end generate;
+ rin <= v;
+ end process comb;
- p_st_clk : process (st_clk, st_rst)
+ regs : process(st_clk)
begin
- if st_rst = '1' then
- wr_data <= (others => '0');
- wr_addr <= (others => '0');
- wr_en <= '0';
- wr_done <= '0';
- elsif rising_edge(st_clk) then
- wr_data <= nxt_wr_data;
- wr_addr <= nxt_wr_addr;
- wr_en <= nxt_wr_en;
- wr_done <= nxt_wr_done;
+ if rising_edge(st_clk) then
+ r <= rin;
end if;
end process;
- -- Write access control
- nxt_wr_data <= in_data;
- nxt_wr_en <= in_val and not nxt_wr_done;
+ -- Choose between SYNC MODE and ARM MODE.
+ wr_sync <= in_sync when TO_UINT(reg_sync_delay) = 0 else r.wr_sync;
+end generate;
- p_wr_addr : process (wr_done, wr_addr, wr_sync, wr_en)
- begin
- nxt_wr_done <= wr_done;
- nxt_wr_addr <= wr_addr;
- if wr_sync = '1' then
- nxt_wr_done <= '0';
- nxt_wr_addr <= (others => '0');
- elsif wr_en = '1' then
- if unsigned(wr_addr) = g_nof_data - 1 then
- nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
- else
- nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
- end if;
+p_st_clk : process (st_clk, st_rst)
+begin
+ if st_rst = '1' then
+ wr_data <= (others => '0');
+ wr_addr <= (others => '0');
+ wr_en <= '0';
+ wr_done <= '0';
+ elsif rising_edge(st_clk) then
+ wr_data <= nxt_wr_data;
+ wr_addr <= nxt_wr_addr;
+ wr_en <= nxt_wr_en;
+ wr_done <= nxt_wr_done;
+ end if;
+end process;
+
+-- Write access control
+nxt_wr_data <= in_data;
+nxt_wr_en <= in_val and not nxt_wr_done;
+
+p_wr_addr : process (wr_done, wr_addr, wr_sync, wr_en)
+begin
+ nxt_wr_done <= wr_done;
+ nxt_wr_addr <= wr_addr;
+ if wr_sync = '1' then
+ nxt_wr_done <= '0';
+ nxt_wr_addr <= (others => '0');
+ elsif wr_en = '1' then
+ if unsigned(wr_addr) = g_nof_data - 1 then
+ nxt_wr_done <= '1'; -- keep wr_addr, do not allow wr_addr increment >= g_nof_data to avoid RAM address out-of-bound warning in Modelsim in case c_buf.nof_dat < 2**c_buf.adr_w
+ else
+ nxt_wr_addr <= INCR_UVEC(wr_addr, 1);
end if;
- end process;
+ end if;
+end process;
- u_buf : entity common_lib.common_ram_crw_crw_ratio
+u_buf : entity common_lib.common_ram_crw_crw_ratio
generic map (
g_technology => g_technology,
g_ram_a => c_buf_mm,
@@ -312,7 +316,7 @@ begin
rd_val_b => open
);
- u_reg : entity common_lib.common_reg_r_w_dc
+u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_reg => c_reg
)
@@ -334,12 +338,12 @@ begin
out_reg => reg_slv_wr
);
- arm_enable <= reg_wr_arr(2);
- reg_sync_delay <= reg_slv_wr(4 * c_word_w - 1 downto 3 * c_word_w);
- reg_slv_rd <= TO_UVEC(c_version, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) &
- reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
+arm_enable <= reg_wr_arr(2);
+reg_sync_delay <= reg_slv_wr(4 * c_word_w - 1 downto 3 * c_word_w);
+reg_slv_rd <= TO_UVEC(c_version, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) & TO_UVEC(0, c_word_w) &
+reg_sync_delay & valid_cnt & word_cnt & sync_cnt;
- u_word_cnt : entity common_lib.common_counter
+u_word_cnt : entity common_lib.common_counter
port map (
rst => st_rst,
clk => st_clk,
@@ -348,7 +352,7 @@ begin
count => word_cnt
);
- u_sync_cnt : entity common_lib.common_counter
+u_sync_cnt : entity common_lib.common_counter
port map (
rst => st_rst,
clk => st_clk,
@@ -357,7 +361,7 @@ begin
count => sync_cnt
);
- u_valid_cnt : entity common_lib.common_counter
+u_valid_cnt : entity common_lib.common_counter
port map (
rst => st_rst,
clk => st_clk,
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index cccb660269ccd0b07ac18b1f035d3a4168cc7ede..22e8dd3e9a57e79e0f67727a85cc424b19263c24 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Generate a stream of frames with test sequence data.
-- Description:
@@ -41,7 +41,7 @@ entity diag_frm_generator is
g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
g_frame_len : natural := 2; -- >= 2, test frame length in nof dat words
g_sof_period : natural := 1; -- >= 1, nof cycles between sop that start a frame, typically >> g_frame_len
- -- to generate frames with idle in between
+ -- to generate frames with idle in between
g_frame_cnt_w : natural := 32;
g_dat_w : natural := 16; -- >= 1, test data width
g_symbol_w : natural := 16; -- >= 1, and nof_symbols_per_dat = g_dat_w/g_symbol_w, must be an integer
@@ -93,17 +93,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
p_clk : process (rst, clk)
begin
@@ -121,62 +121,62 @@ begin
nxt_diag_init <= TO_UVEC(c_init, g_dat_w) when diag_en = '0' else INCR_UVEC(diag_init, 1) when i_out_sop = '1';
u_pulse_sop : entity common_lib.common_pulser
- generic map (
- g_pulse_period => g_sof_period
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- pulse_period => diag_sof_period,
- pulse_en => diag_en,
- pulse_clr => diag_en_revt,
- pulse_out => diag_sop
- );
+ generic map (
+ g_pulse_period => g_sof_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ pulse_period => diag_sof_period,
+ pulse_en => diag_en,
+ pulse_clr => diag_en_revt,
+ pulse_out => diag_sop
+ );
-- Hold last frame count also when the generator is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => i_out_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => i_out_eop,
+ count => frame_cnt
+ );
u_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => g_sel,
- g_init => c_init,
- g_frame_len => g_frame_len,
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
-
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_frame_len => diag_frame_len,
-
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
-
- -- ST output
- out_ready => out_ready,
- out_dat => out_dat,
- out_val => out_val,
- out_sop => i_out_sop,
- out_eop => i_out_eop
- );
+ generic map (
+ g_sel => g_sel,
+ g_init => c_init,
+ g_frame_len => g_frame_len,
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_frame_len => diag_frame_len,
+
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+
+ -- ST output
+ out_ready => out_ready,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sop => i_out_sop,
+ out_eop => i_out_eop
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
index 1993a7509844865d3d8727e06c807a64d203b910..f22f33b62d1fce50277351f348bf21c3a4470e4c 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose: Monitor a stream of frames with test sequence data.
-- Description:
@@ -87,17 +87,17 @@ begin
-- Signal begin of diag_en
u_diag_en_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- in_sig => diag_en,
- out_evt => diag_en_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_sig => diag_en,
+ out_evt => diag_en_revt
+ );
-- Hold last frame and error counts also when the monitor is disabled, clear when it is restarted
nxt_diag_frame_cnt <= (others => '0') when diag_en_revt = '1' else frame_cnt;
@@ -105,31 +105,31 @@ begin
-- Count all received frames
u_frm_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => in_eop,
- count => frame_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => in_eop,
+ count => frame_cnt
+ );
-- Count the received frames that had an error
frm_error <= in_eop and in_error;
u_err_cnt : entity common_lib.common_counter
- generic map (
- g_width => g_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_en_revt,
- cnt_en => frm_error,
- count => error_cnt
- );
+ generic map (
+ g_width => g_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_en_revt,
+ cnt_en => frm_error,
+ count => error_cnt
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 8f88945551725e4a93ed9d88fd2714e027a73f0e..430983373746c228cb73504c8cdabbe00739d72d 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
package diag_pkg is
-----------------------------------------------------------------------------
@@ -59,7 +59,7 @@ package diag_pkg is
constant c_diag_wg_phase_w : natural := 16; -- = c_diag_wg_nofsamples_w
constant c_diag_wg_freq_w : natural := 31; -- >> c_diag_wg_nofsamples_w, determines the minimum frequency = Fs / 2**c_diag_wg_freq_w
constant c_diag_wg_ampl_w : natural := 17; -- Typically fit DSP multiply 18x18 element so use <= 17, to fit unsigned in 18 bit signed,
- -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
+ -- = waveform data width-1 (sign bit) to be able to make a 1 LSBit amplitude sinus
constant c_diag_wg_mode_off : natural := 0;
constant c_diag_wg_mode_calc : natural := 1;
@@ -75,23 +75,24 @@ package diag_pkg is
end record;
constant c_diag_wg_ampl_norm : real := 1.0; -- Use this default amplitude norm = 1.0 when WG data width = WG waveform buffer data width,
- -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
+ -- else use extra amplitude unit scaling by (WG data max)/(WG data max + 1)
constant c_diag_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
- -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
- -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
- -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
- constant c_diag_wg_ampl_unit : real := 2**REAL(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
- constant c_diag_wg_freq_unit : real := 2**REAL(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
- constant c_diag_wg_phase_unit : real := 2**REAL(c_diag_wg_phase_w) / 360.0; -- ^= 1 degree
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- For c_diag_wg_gain_w = 1 there is clipping from [1 2> For normalized values >= 2**c_diag_wg_gain_w = 2
+ -- the behaviour becomes more or less undefined. Due to wrapping it appears that normalized values [2 3>
+ -- result in a sinus again. Therefore use normalized range [0 2**c_diag_wg_gain_w>.
+ constant c_diag_wg_ampl_unit : real := 2 ** real(c_diag_wg_ampl_w - c_diag_wg_gain_w) * c_diag_wg_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
+ constant c_diag_wg_freq_unit : real := 2 ** real(c_diag_wg_freq_w); -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
+ constant c_diag_wg_phase_unit : real := 2 ** real(c_diag_wg_phase_w) / 360.0; -- ^= 1 degree
constant c_diag_wg_latency : natural := 10; -- WG starts 10 cycles after trigger
- constant c_diag_wg_rst : t_diag_wg := (TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
- TO_UVEC( 1024, c_diag_wg_nofsamples_w),
- TO_UVEC( 0, c_diag_wg_phase_w),
- TO_UVEC( 0, c_diag_wg_freq_w),
- TO_UVEC( 0, c_diag_wg_ampl_w));
+ constant c_diag_wg_rst : t_diag_wg := (
+ TO_UVEC(c_diag_wg_mode_off, c_diag_wg_mode_w),
+ TO_UVEC( 1024, c_diag_wg_nofsamples_w),
+ TO_UVEC( 0, c_diag_wg_phase_w),
+ TO_UVEC( 0, c_diag_wg_freq_w),
+ TO_UVEC( 0, c_diag_wg_ampl_w));
type t_diag_wg_arr is array (integer range <>) of t_diag_wg;
@@ -102,7 +103,7 @@ package diag_pkg is
-- control register
constant c_diag_bg_reg_nof_dat : natural := 8;
constant c_diag_bg_reg_adr_w : natural := ceil_log2(c_diag_bg_reg_nof_dat);
- constant c_diag_bg_reg_adr_span : natural := 2**c_diag_bg_reg_adr_w;
+ constant c_diag_bg_reg_adr_span : natural := 2 ** c_diag_bg_reg_adr_w;
-- Use c_diag_bg_gapsize_w = 31 to fit gapsize in 31 bit NATURAL. At 200 MHz
-- clock this allows a gap of 2**31 / 200e6 = 10.7 s
@@ -114,7 +115,7 @@ package diag_pkg is
constant c_diag_bg_mem_adrs_w : natural := 24;
constant c_diag_bg_mem_low_adrs_w : natural := c_diag_bg_mem_adrs_w;
constant c_diag_bg_mem_high_adrs_w : natural := c_diag_bg_mem_adrs_w;
- constant c_diag_bg_mem_max_adr : natural := 2**c_diag_bg_mem_adrs_w - 1;
+ constant c_diag_bg_mem_max_adr : natural := 2 ** c_diag_bg_mem_adrs_w - 1;
constant c_diag_bg_bsn_init_w : natural := 64;
type t_diag_block_gen is record
@@ -139,23 +140,25 @@ package diag_pkg is
bsn_init : natural;
end record;
- constant c_diag_block_gen_rst : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 128, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- constant c_diag_block_gen_enabled : t_diag_block_gen := ( '1',
- '0',
- TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 7, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_diag_block_gen_rst : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC( 256, c_diag_bg_samples_per_packet_w),
+ TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 128, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( 1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ constant c_diag_block_gen_enabled : t_diag_block_gen := (
+ '1',
+ '0',
+ TO_UVEC( 50, c_diag_bg_samples_per_packet_w),
+ TO_UVEC( 10, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 7, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( 15, c_diag_bg_mem_high_adrs_w), -- fits any BG buffer that has address width >= 4
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
type t_diag_block_gen_arr is array (integer range <>) of t_diag_block_gen;
type t_diag_block_gen_integer_arr is array (integer range <>) of t_diag_block_gen_integer;
@@ -218,7 +221,6 @@ package diag_pkg is
constant c_diag_seq_tx_reg_en_cntr : natural := 3;
type t_diag_seq_mm_reg_arr is array (integer range <>) of t_diag_seq_mm_reg;
-
end diag_pkg;
package body diag_pkg is
@@ -235,25 +237,25 @@ package body diag_pkg is
function func_diag_bg_ctrl_integer_to_slv(bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen is
begin
return ( bg_ctrl_int.enable,
- bg_ctrl_int.enable_sync,
- TO_UVEC(bg_ctrl_int.samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(bg_ctrl_int.blocks_per_sync , c_diag_bg_blocks_per_sync_w),
- TO_UVEC(bg_ctrl_int.gapsize , c_diag_bg_gapsize_w),
- TO_UVEC(bg_ctrl_int.mem_low_adrs , c_diag_bg_mem_low_adrs_w),
- TO_UVEC(bg_ctrl_int.mem_high_adrs , c_diag_bg_mem_high_adrs_w),
- TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
+ bg_ctrl_int.enable_sync,
+ TO_UVEC(bg_ctrl_int.samples_per_packet, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(bg_ctrl_int.blocks_per_sync , c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(bg_ctrl_int.gapsize , c_diag_bg_gapsize_w),
+ TO_UVEC(bg_ctrl_int.mem_low_adrs , c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(bg_ctrl_int.mem_high_adrs , c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
end;
function func_diag_bg_ctrl_slv_to_integer(bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer is
begin
return ( bg_ctrl_slv.enable,
- bg_ctrl_slv.enable_sync,
- TO_UINT(bg_ctrl_slv.samples_per_packet),
- TO_UINT(bg_ctrl_slv.blocks_per_sync),
- TO_UINT(bg_ctrl_slv.gapsize),
- TO_UINT(bg_ctrl_slv.mem_low_adrs),
- TO_UINT(bg_ctrl_slv.mem_high_adrs),
- TO_UINT(bg_ctrl_slv.bsn_init));
+ bg_ctrl_slv.enable_sync,
+ TO_UINT(bg_ctrl_slv.samples_per_packet),
+ TO_UINT(bg_ctrl_slv.blocks_per_sync),
+ TO_UINT(bg_ctrl_slv.gapsize),
+ TO_UINT(bg_ctrl_slv.mem_low_adrs),
+ TO_UINT(bg_ctrl_slv.mem_high_adrs),
+ TO_UINT(bg_ctrl_slv.bsn_init));
end;
end diag_pkg;
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 4bf373e254343579497acde7c1872eda9cc6fd26..576f213a407ebcb502cc1bd4c83f671471bc8ac4 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -90,11 +90,11 @@
-- in case they occur.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.diag_pkg.all;
entity diag_rx_seq is
generic (
@@ -193,6 +193,7 @@ begin
diag_sample_diff <= i_diag_sample_diff;
gen_input_reg : if g_input_reg = true generate
+
p_reg : process (clk)
begin
if rising_edge(clk) then
@@ -212,19 +213,19 @@ begin
-- Use initialisation to set initial diag_res to invalid
diag_res <= diag_res_int; -- use initialisation of internal signal diag_res_int rather than initialisation of entity output diag_res
--- -- Use rst to set initial diag_res to invalid
--- p_rst_clk : PROCESS (rst, clk)
--- BEGIN
--- IF rst='1' THEN
--- diag_res <= c_diag_res_invalid;
--- ELSIF rising_edge(clk) THEN
--- IF clken='1' THEN
--- -- Internal.
--- diag_res <= nxt_diag_res;
--- -- Outputs.
--- END IF;
--- END IF;
--- END PROCESS;
+ -- -- Use rst to set initial diag_res to invalid
+ -- p_rst_clk : PROCESS (rst, clk)
+ -- BEGIN
+ -- IF rst='1' THEN
+ -- diag_res <= c_diag_res_invalid;
+ -- ELSIF rising_edge(clk) THEN
+ -- IF clken='1' THEN
+ -- -- Internal.
+ -- diag_res <= nxt_diag_res;
+ -- -- Outputs.
+ -- END IF;
+ -- END IF;
+ -- END PROCESS;
p_clk : process (clk)
begin
@@ -269,24 +270,24 @@ begin
------------------------------------------------------------------------------
u_in_val_1 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_reg,
- switch_low => diag_dis,
- out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_reg,
+ switch_low => diag_dis,
+ out_level => in_val_1 -- first in_val has been detected, but this one was used as seed for common_lfsr_nxt_seq
+ );
in_val_act <= in_val_1 and in_val_reg; -- Signal the second valid in_dat after diag_en='1'
u_in_val_2 : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => in_val_act,
- switch_low => diag_dis,
- out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => in_val_act,
+ switch_low => diag_dis,
+ out_level => in_val_2 -- second in_val has been detected, representing a true next sequence value
+ );
-- Use in_val_2_act instead of in_val_2 to have stable start in case diag_dis takes just a pulse and in_val is continue high
in_val_2_act <= vector_and(in_val_2 & in_val_2_dly);
@@ -300,14 +301,14 @@ begin
no_steps : if g_use_steps = false generate
-- Determine next reference dat based on current input dat
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- ref_en, -- IN
- in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
- in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- nxt_cntr); -- OUT
+ g_cnt_incr, -- IN
+ ref_en, -- IN
+ in_val_reg, -- IN, use in_val_reg to allow gaps in the input data valid stream
+ in_dat_reg, -- IN, used only to init nxt_prsg and nxt_cntr when ref_en='0'
+ prsg, -- IN
+ cntr, -- IN
+ nxt_prsg, -- OUT
+ nxt_cntr); -- OUT
nxt_ref_dat <= prsg when diag_sel = '0' else cntr;
@@ -335,17 +336,17 @@ begin
-- Hold any difference on the in_dat bus lines
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_dat(I),
- switch_low => diff_dis,
- out_level => diff_res(I)
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_dat(I),
+ switch_low => diff_dis,
+ out_level => diff_res(I)
+ );
end generate;
end generate;
- use_steps : if g_use_steps = true generate
+ use_steps : if g_use_steps = true generate
-- Determine next reference data for all steps increments of current input dat
p_ref_dat_arr : process(in_dat_reg, in_val_reg, ref_dat_arr)
begin
@@ -385,38 +386,38 @@ begin
-- hold detected diff detect
u_dat : entity common_lib.common_switch
- port map(
- clk => clk,
- rst => rst,
- switch_high => diff_detect,
- switch_low => diff_dis,
- out_level => diff_hold
- );
+ port map(
+ clk => clk,
+ rst => rst,
+ switch_high => diff_detect,
+ switch_low => diff_dis,
+ out_level => diff_hold
+ );
diff_res <= (others => diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
- end generate;
+end generate;
- ------------------------------------------------------------------------------
- -- Report valid diag_res
- ------------------------------------------------------------------------------
-
- nxt_diag_res_en <= diag_en and in_val_2_act;
- nxt_diag_res_val <= diag_res_en;
+------------------------------------------------------------------------------
+-- Report valid diag_res
+------------------------------------------------------------------------------
- p_diag_res : process (diff_res, diag_res_en)
- begin
- nxt_diag_res <= c_diag_res_invalid;
- if diag_res_en = '1' then
- -- The test runs AND there have been valid input samples to verify
- nxt_diag_res <= (others => '0'); -- MSBits of valid diag_res are 0
- nxt_diag_res(diff_res'range) <= diff_res; -- diff_res of dat[]
- end if;
- end process;
+nxt_diag_res_en <= diag_en and in_val_2_act;
+nxt_diag_res_val <= diag_res_en;
- ------------------------------------------------------------------------------
- -- Count number of valid input data
- ------------------------------------------------------------------------------
- u_common_counter : entity common_lib.common_counter
+p_diag_res : process (diff_res, diag_res_en)
+begin
+ nxt_diag_res <= c_diag_res_invalid;
+ if diag_res_en = '1' then
+ -- The test runs AND there have been valid input samples to verify
+ nxt_diag_res <= (others => '0'); -- MSBits of valid diag_res are 0
+ nxt_diag_res(diff_res'range) <= diff_res; -- diff_res of dat[]
+ end if;
+end process;
+
+------------------------------------------------------------------------------
+-- Count number of valid input data
+------------------------------------------------------------------------------
+u_common_counter : entity common_lib.common_counter
generic map (
g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
g_width => g_cnt_w
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index 0f392a8179f1357c5ecf7e6848dbb7b576332d25..e164f0ba8dd7646934898daac3a70006fe4ec24c 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
-- Purpose: Transmit a frame with PRSG or COUNTER test sequence data.
-- Description:
@@ -120,7 +120,7 @@ begin
frm_sop <= i_diag_ready and diag_sop;
nxt_frm_busy <= '1' when frm_sop = '1' else
- '0' when cnt_done = '1' else frm_busy;
+ '0' when cnt_done = '1' else frm_busy;
cnt_clr <= frm_sop;
cnt_en <= '1' when frm_busy = '1' and out_ready = '1' and unsigned(cnt) <= g_frame_len - 1 else '0';
@@ -137,32 +137,32 @@ begin
nxt_out_eop <= cnt_done;
u_cnt_len : entity common_lib.common_counter
- generic map (
- g_width => diag_frame_len'length
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_width => diag_frame_len'length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
u_frame_dat : entity work.diag_tx_seq
- generic map (
- g_dat_w => g_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_dc => diag_dc,
- diag_init => diag_init,
- diag_req => out_ready,
- out_dat => out_dat,
- out_val => open
- );
+ generic map (
+ g_dat_w => g_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_dc => diag_dc,
+ diag_init => diag_init,
+ diag_req => out_ready,
+ out_dat => out_dat,
+ out_val => open
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index 6b00fcfb0d0b1643d8b08c7fc35da4f3376c0045..be01f60e5a369b922e801e2912eaadc2c86fb961 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
-- Purpose: Transmit continuous PRSG or COUNTER test sequence data.
-- Description:
@@ -97,6 +97,7 @@ begin
end process;
gen_latency : if g_latency /= 0 generate
+
p_clk : process (rst, clk)
begin
if rst = '1' then
@@ -117,14 +118,14 @@ begin
end generate;
common_lfsr_nxt_seq(c_lfsr_nr, -- IN
- g_cnt_incr, -- IN
- diag_en, -- IN
- diag_req, -- IN
- diag_init, -- IN
- prsg, -- IN
- cntr, -- IN
- nxt_prsg, -- OUT
- next_cntr); -- OUT
+ g_cnt_incr, -- IN
+ diag_en, -- IN
+ diag_req, -- IN
+ diag_init, -- IN
+ prsg, -- IN
+ cntr, -- IN
+ nxt_prsg, -- OUT
+ next_cntr); -- OUT
nxt_cntr <= next_cntr when unsigned(next_cntr) < unsigned(diag_mod) else SUB_UVEC(next_cntr, diag_mod);
@@ -133,16 +134,16 @@ begin
-- Count number of valid output data
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => g_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => clken,
- cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
- cnt_en => nxt_out_val,
- count => out_cnt
- );
+ generic map (
+ g_latency => g_latency, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => nxt_out_val,
+ count => out_cnt
+ );
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 93592adee83c80033b3e9f51e3de6b6070170d7a..b4c8dda6e0203e158a859ada9f09f076124d32be 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -46,25 +46,25 @@
-- CW with fractional frequency is SNR ~= 56 dB, even if g_calc_dat_w > 9.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg is
generic (
g_technology : natural := c_tech_select_default;
g_buf_dat_w : natural := 18; -- Use >= g_calc_dat_w and typically <= DSP multiply 18x18 element
g_buf_addr_w : natural := 11; -- Waveform buffer size 2**g_buf_addr_w nof samples
- -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
- -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
+ -- . in calc mode fill the entire buffer with one sinus wave, ctrl.phase and ctrl.freq will map on the entire range
+ -- . in single or repeat mode fill the buffer with an arbitrary signal and define actual the period via ctrl.nof_samples
g_rate_factor : natural := 1; -- Default 1 for unit frequency Fs, else g_rate_factor * Fs using g_rate_factor nof parallel outputs
g_rate_offset : natural := 0; -- Selects which of the parallel outputs [0:g_rate_factor-1] this WG should generate
g_calc_support : boolean := true; -- When FALSE then calc mode falls back to repeat mode to save logic.
g_calc_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have full scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have full scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
g_calc_dat_w : natural := 12 -- Effective range of the WG out_dat
);
port (
@@ -109,7 +109,7 @@ architecture rtl of diag_wg is
constant c_round_w : natural := g_calc_dat_w + g_calc_gain_w;
-- Clip to account for the gain factor
- constant c_calc_full_scale : natural := 2**(g_calc_dat_w - 1) - 1;
+ constant c_calc_full_scale : natural := 2 ** (g_calc_dat_w - 1) - 1;
type state_enum is (
s_off,
@@ -128,7 +128,7 @@ architecture rtl of diag_wg is
signal nxt_mon_ctrl : t_diag_wg;
signal nof_samples : std_logic_vector(g_buf_addr_w downto 0); -- only use effective range of nof_samples+1
signal nxt_nof_samples : std_logic_vector(g_buf_addr_w downto 0);
- signal sample_cnt : natural range 0 to 2**g_buf_addr_w - 1;
+ signal sample_cnt : natural range 0 to 2 ** g_buf_addr_w - 1;
signal nxt_sample_cnt : natural;
signal sample_step : natural range 0 to g_rate_factor;
signal nxt_sample_step : natural;
@@ -227,7 +227,7 @@ begin
when c_diag_wg_mode_single => if init_repeat_done = '1' then nxt_state <= s_single; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_repeat => if init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
when c_diag_wg_mode_calc => if g_calc_support = false and init_repeat_done = '1' then nxt_state <= s_repeat; nxt_init_sync <= '1'; end if;
- if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
+ if g_calc_support = true and init_calc_done = '1' then nxt_state <= s_calc; nxt_init_sync <= '1'; end if;
when others => nxt_state <= s_off;
end case;
when s_single =>
@@ -346,98 +346,98 @@ begin
end process;
mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => g_buf_dat_w,
- g_in_b_w => c_ampl_w,
- g_out_p_w => c_mult_w,
- g_pipeline_input => c_mult_pipeline_input,
- g_pipeline_product => c_mult_pipeline_product,
- g_pipeline_output => c_mult_pipeline_output
- )
- port map (
- rst => rst,
- clk => clk,
- in_a => buf_rddat,
- in_b => ctrl_ampl,
- out_p => mult_dat
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => g_buf_dat_w,
+ g_in_b_w => c_ampl_w,
+ g_out_p_w => c_mult_w,
+ g_pipeline_input => c_mult_pipeline_input,
+ g_pipeline_product => c_mult_pipeline_product,
+ g_pipeline_output => c_mult_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_a => buf_rddat,
+ in_b => ctrl_ampl,
+ out_p => mult_dat
+ );
-- Skip the double-sign bit
prod_dat <= mult_dat(c_prod_w - 1 downto 0);
u_round : entity common_lib.common_round
- generic map(
- g_representation => "SIGNED",
- g_round => true,
- g_round_clip => true,
- g_pipeline_input => 0,
- g_pipeline_output => c_round_pipeline,
- g_in_dat_w => c_prod_w,
- g_out_dat_w => c_round_w
- )
- port map (
- clk => clk,
- in_dat => prod_dat,
- out_dat => round_dat
- );
+ generic map(
+ g_representation => "SIGNED",
+ g_round => true,
+ g_round_clip => true,
+ g_pipeline_input => 0,
+ g_pipeline_output => c_round_pipeline,
+ g_in_dat_w => c_prod_w,
+ g_out_dat_w => c_round_w
+ )
+ port map (
+ clk => clk,
+ in_dat => prod_dat,
+ out_dat => round_dat
+ );
u_clip : entity common_lib.common_clip
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_clip_pipeline,
- g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => round_dat,
- out_dat => clip_dat,
- out_ovr => clip_ovr
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_clip_pipeline,
+ g_full_scale => to_unsigned(c_calc_full_scale, g_calc_dat_w)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => round_dat,
+ out_dat => clip_dat,
+ out_ovr => clip_ovr
+ );
u_rdval_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(buf_rdval),
- sl(out_dat) => buf_rdval_dly
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(buf_rdval),
+ sl(out_dat) => buf_rdval_dly
+ );
u_sync_default_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_sync_dly,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(init_sync),
- sl(out_dat) => sync_dly_default
- );
+ generic map (
+ g_pipeline => c_sync_dly,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(init_sync),
+ sl(out_dat) => sync_dly_default
+ );
u_sync_calc_delay : entity common_lib.common_pipeline
- generic map (
- g_pipeline => c_calc_pipeline,
- g_in_dat_w => 1,
- g_out_dat_w => 1
- )
- port map (
- rst => rst,
- clk => clk,
- in_clr => idle,
- in_dat => slv(sync_dly_default),
- sl(out_dat) => sync_dly_calc
- );
+ generic map (
+ g_pipeline => c_calc_pipeline,
+ g_in_dat_w => 1,
+ g_out_dat_w => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_clr => idle,
+ in_dat => slv(sync_dly_default),
+ sl(out_dat) => sync_dly_calc
+ );
output_proc : process(state, buf_rdval_dly, clip_dat, clip_ovr, buf_rdval, buf_rddat, sync_dly_default, sync_dly_calc)
begin
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index bb2657dbd84c20cf1fc44d553717566f55a69238..bc3311fb2425d78fc567a7dcac02efd86ed0d6f5 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -25,12 +25,12 @@
-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity diag_wg_wideband is
generic (
@@ -76,28 +76,29 @@ entity diag_wg_wideband is
end diag_wg_wideband;
architecture str of diag_wg_wideband is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
- init_sl => '0');
- constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
-
- type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
- type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
-
- signal st_mon_ctrl_arr : t_diag_wg_arr(0 to g_wideband_factor - 1);
-
- -- Use same address and data widths for both MM side and ST side memory ports
- signal buf_rdval : std_logic_vector(0 to g_wideband_factor - 1);
- signal buf_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
-
- signal st_address : t_buf_adr_arr(0 to g_wideband_factor - 1);
- signal st_rd : std_logic_vector(0 to g_wideband_factor - 1);
- signal st_rdval : std_logic_vector(0 to g_wideband_factor - 1);
- signal st_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_addr_w, -- = 2**adr_w
+ init_sl => '0');
+ constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_2048x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, g_buf_dir & "diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, g_buf_dir & "diag_sin_1024x8.hex", "UNUSED")));
+
+ type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
+ type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
+
+ signal st_mon_ctrl_arr : t_diag_wg_arr(0 to g_wideband_factor - 1);
+
+ -- Use same address and data widths for both MM side and ST side memory ports
+ signal buf_rdval : std_logic_vector(0 to g_wideband_factor - 1);
+ signal buf_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
+
+ signal st_address : t_buf_adr_arr(0 to g_wideband_factor - 1);
+ signal st_rd : std_logic_vector(0 to g_wideband_factor - 1);
+ signal st_rdval : std_logic_vector(0 to g_wideband_factor - 1);
+ signal st_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
begin
assert c_buf_file /= "UNUSED" report "diag_wg_wideband : no buffer waveform file available" severity FAILURE;
@@ -111,60 +112,59 @@ begin
gen_wg : for I in 0 to g_wideband_factor - 1 generate
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_dat_a => mm_wrdata,
- adr_a => mm_address,
- wr_en_a => mm_wr,
- rd_en_a => mm_rd,
- rd_val_a => buf_rdval(I),
- rd_dat_a => buf_rddata(I),
- rst_b => st_rst,
- clk_b => st_clk,
- wr_dat_b => (others => '0'),
- adr_b => st_address(I),
- wr_en_b => '0',
- rd_en_b => st_rd(I),
- rd_val_b => st_rdval(I),
- rd_dat_b => st_rddata(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_dat_a => mm_wrdata,
+ adr_a => mm_address,
+ wr_en_a => mm_wr,
+ rd_en_a => mm_rd,
+ rd_val_a => buf_rdval(I),
+ rd_dat_a => buf_rddata(I),
+ rst_b => st_rst,
+ clk_b => st_clk,
+ wr_dat_b => (others => '0'),
+ adr_b => st_address(I),
+ wr_en_b => '0',
+ rd_en_b => st_rd(I),
+ rd_val_b => st_rdval(I),
+ rd_dat_b => st_rddata(I)
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_technology => g_technology,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_rate_factor => g_wideband_factor,
- g_rate_offset => I,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- restart => st_restart,
-
- buf_rddat => st_rddata(I),
- buf_rdval => st_rdval(I),
- buf_addr => st_address(I),
- buf_rden => st_rd(I),
-
- ctrl => st_ctrl,
- mon_ctrl => st_mon_ctrl_arr(I),
-
- out_ovr => out_ovr( g_wideband_factor - I - 1),
- out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
- out_val => out_val( g_wideband_factor - I - 1),
- out_sync => out_sync( g_wideband_factor - I - 1)
- );
+ generic map (
+ g_technology => g_technology,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_rate_factor => g_wideband_factor,
+ g_rate_offset => I,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ restart => st_restart,
+
+ buf_rddat => st_rddata(I),
+ buf_rdval => st_rdval(I),
+ buf_addr => st_address(I),
+ buf_rden => st_rd(I),
+
+ ctrl => st_ctrl,
+ mon_ctrl => st_mon_ctrl_arr(I),
+
+ out_ovr => out_ovr( g_wideband_factor - I - 1),
+ out_dat => out_dat((g_wideband_factor - I) * g_buf_dat_w - 1 downto (g_wideband_factor - I - 1) * g_buf_dat_w),
+ out_val => out_val( g_wideband_factor - I - 1),
+ out_sync => out_sync( g_wideband_factor - I - 1)
+ );
end generate;
-
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index b0d7b45dc644122ff823691236470fd37bf97c8e..34bfe7662c2f4a51b2635a714dcef87c820842ca 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -41,10 +41,10 @@
-- diag_wg_reg.vhd.
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diag_wg_wideband_reg is
generic (
@@ -69,19 +69,20 @@ end diag_wg_wideband_reg;
architecture rtl of diag_wg_wideband_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_wg_ctrl : t_diag_wg;
- signal mm_wg_ctrl_mode_wr : std_logic;
+ -- Registers in mm_clk domain
+ signal mm_wg_ctrl : t_diag_wg;
+ signal mm_wg_ctrl_mode_wr : std_logic;
- signal mm_mon_ctrl : t_diag_wg;
+ signal mm_mon_ctrl : t_diag_wg;
- -- Registers in st_clk domain
+ -- Registers in st_clk domain
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -122,7 +123,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -181,17 +182,17 @@ begin
-- Assume diag WG mode gets written last, so when diag WG mode is transfered properly to the st_clk domain, then
-- the other diag WG control fields are stable as well
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
- in_dat => mm_wg_ctrl.mode,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_wg_ctrl.mode,
- out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_wg_ctrl_mode_wr, -- when '1' then new in_dat is available after g_in_new_latency
+ in_dat => mm_wg_ctrl.mode,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_wg_ctrl.mode,
+ out_new => open -- when '1' then the out_dat was updated with in_dat due to in_new
+ );
end generate;
-- The other wg_ctrl only take effect in diag_wg after the mode has been set
@@ -203,54 +204,53 @@ begin
-- Read: ST to MM clock domain
gen_cross_rd : if g_cross_clock_domain = true generate
u_mode : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.mode,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.mode
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.mode,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.mode
+ );
u_nof_samples : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.nof_samples,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.nof_samples
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.nof_samples,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.nof_samples
+ );
u_freq : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.freq,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.freq
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.freq,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.freq
+ );
u_phase : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.phase,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.phase
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.phase,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.phase
+ );
u_ampl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_dat => st_mon_ctrl.ampl,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_mon_ctrl.ampl
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.ampl,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.ampl
+ );
end generate;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 60095ffc8cd08aad6673de21d5b4b13f759ecbe8..45bb9050172f379729d8c15dabdfb6f29c5535bf 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -93,13 +93,13 @@
-- . A nice new feature would be to support a BG burst of N blocks.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_block_gen is
generic (
@@ -148,43 +148,44 @@ entity mms_diag_block_gen is
end mms_diag_block_gen;
architecture rtl of mms_diag_block_gen is
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_addr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_addr_w,
- init_sl => '0');
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_addr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_addr_w,
+ init_sl => '0');
- constant c_post_buf_file : string := ".hex";
+ constant c_post_buf_file : string := ".hex";
- constant c_use_mux : boolean := g_use_usr_input and g_use_bg;
- constant c_use_tx_seq_input : boolean := g_use_usr_input or g_use_bg;
- constant c_mux_nof_input : natural := 2; -- fixed
+ constant c_use_mux : boolean := g_use_usr_input and g_use_bg;
+ constant c_use_tx_seq_input : boolean := g_use_usr_input or g_use_bg;
+ constant c_mux_nof_input : natural := 2; -- fixed
- constant c_reg_tx_seq_broadcast : boolean := false; -- fixed use dedicated MM register per stream
+ constant c_reg_tx_seq_broadcast : boolean := false; -- fixed use dedicated MM register per stream
- type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
- type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
+ type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
+ type t_buf_adr_arr is array (natural range <>) of std_logic_vector(g_buf_addr_w - 1 downto 0);
- signal st_addr_arr : t_buf_adr_arr(g_nof_streams - 1 downto 0);
- signal st_rd_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal st_rdval_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal st_rddata_arr : t_buf_dat_arr(g_nof_streams - 1 downto 0);
- signal ram_bg_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
- signal ram_bg_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- signal bg_ctrl : t_diag_block_gen;
+ signal st_addr_arr : t_buf_adr_arr(g_nof_streams - 1 downto 0);
+ signal st_rd_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal st_rdval_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal st_rddata_arr : t_buf_dat_arr(g_nof_streams - 1 downto 0);
+ signal ram_bg_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
+ signal ram_bg_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
+ signal bg_ctrl : t_diag_block_gen;
- signal mux_ctrl : natural range 0 to c_mux_nof_input - 1;
- signal mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
- signal mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
+ signal mux_ctrl : natural range 0 to c_mux_nof_input - 1;
+ signal mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
+ signal mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_streams - 1 downto 0); -- [g_nof_streams-1:0][c_mux_nof_input-1:0] = [1:0]
- signal usr_xflow_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- optionally use dp_xonoff to add siso.xon flow control to use input when g_usr_bypass_xonoff=FALSE
- signal usr_xflow_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal usr_xflow_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- optionally use dp_xonoff to add siso.xon flow control to use input when g_usr_bypass_xonoff=FALSE
+ signal usr_xflow_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal bg_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- BG has siso.xon flow control but no siso.ready flow control
- signal bg_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal bg_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- BG has siso.xon flow control but no siso.ready flow control
+ signal bg_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal mux_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
- signal mux_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal mux_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
+ signal mux_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
-----------------------------------------------------------------------------
-- BG
@@ -201,34 +202,35 @@ begin
mux_ctrl <= 0 when bg_ctrl.enable = '0' else 1;
u_bg_ctrl : entity work.diag_block_gen_reg
- generic map(
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_diag_block_gen_rst => g_diag_block_gen_rst
- )
- port map (
- mm_rst => mm_rst, -- Clocks and reset
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_mosi => reg_bg_ctrl_mosi,
- mm_miso => reg_bg_ctrl_miso,
- bg_ctrl => bg_ctrl
- );
+ generic map(
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_diag_block_gen_rst => g_diag_block_gen_rst
+ )
+ port map (
+ mm_rst => mm_rst, -- Clocks and reset
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_mosi => reg_bg_ctrl_mosi,
+ mm_miso => reg_bg_ctrl_miso,
+ bg_ctrl => bg_ctrl
+ );
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux_bg_data : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => ram_bg_data_mosi,
- miso => ram_bg_data_miso,
- mosi_arr => ram_bg_data_mosi_arr,
- miso_arr => ram_bg_data_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
+ )
+ port map (
+ mosi => ram_bg_data_mosi,
+ miso => ram_bg_data_miso,
+ mosi_arr => ram_bg_data_mosi_arr,
+ miso_arr => ram_bg_data_miso_arr
+ );
gen_streams : for I in 0 to g_nof_streams - 1 generate
+
no_buffer_ram : if g_use_bg_buffer_ram = false generate
ram_bg_data_miso_arr(I) <= c_mem_miso_rst;
@@ -239,53 +241,53 @@ begin
gen_buffer_ram : if g_use_bg_buffer_ram = true generate
u_buffer_ram : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_buf,
+ -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
+ g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => ram_bg_data_mosi_arr(I).wr,
+ wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
+ adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => ram_bg_data_mosi_arr(I).rd,
+ rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => ram_bg_data_miso_arr(I).rdval,
+ -- Waveform side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => st_addr_arr(I),
+ rd_en_b => st_rd_arr(I),
+ rd_dat_b => st_rddata_arr(I),
+ rd_val_b => st_rdval_arr(I)
+ );
+ end generate;
+
+ u_diag_block_gen : entity work.diag_block_gen
generic map (
- g_technology => g_technology,
- g_ram => c_buf,
- -- Sequence number and ".hex" extension are added to the relative path in case a ram file is provided.
- g_init_file => sel_a_b(g_file_name_prefix = "UNUSED", g_file_name_prefix, g_file_name_prefix & "_" & natural'image(g_file_index_arr(I)) & c_post_buf_file)
+ g_blk_sync => g_blk_sync,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => ram_bg_data_mosi_arr(I).wr,
- wr_dat_a => ram_bg_data_mosi_arr(I).wrdata(c_buf.dat_w - 1 downto 0),
- adr_a => ram_bg_data_mosi_arr(I).address(c_buf.adr_w - 1 downto 0),
- rd_en_a => ram_bg_data_mosi_arr(I).rd,
- rd_dat_a => ram_bg_data_miso_arr(I).rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => ram_bg_data_miso_arr(I).rdval,
- -- Waveform side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => st_addr_arr(I),
- rd_en_b => st_rd_arr(I),
- rd_dat_b => st_rddata_arr(I),
- rd_val_b => st_rdval_arr(I)
+ rst => dp_rst,
+ clk => dp_clk,
+ buf_addr => st_addr_arr(I),
+ buf_rden => st_rd_arr(I),
+ buf_rddat => st_rddata_arr(I),
+ buf_rdval => st_rdval_arr(I),
+ ctrl => bg_ctrl, -- same BG control for all streams
+ ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
+ en_sync => en_sync,
+ out_siso => bg_src_in_arr(I),
+ out_sosi => bg_src_out_arr(I)
);
- end generate;
-
- u_diag_block_gen : entity work.diag_block_gen
- generic map (
- g_blk_sync => g_blk_sync,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- buf_addr => st_addr_arr(I),
- buf_rden => st_rd_arr(I),
- buf_rddat => st_rddata_arr(I),
- buf_rdval => st_rdval_arr(I),
- ctrl => bg_ctrl, -- same BG control for all streams
- ctrl_hold => bg_ctrl_hold_arr(I), -- active BG control can differ in time per stream
- en_sync => en_sync,
- out_siso => bg_src_in_arr(I),
- out_sosi => bg_src_out_arr(I)
- );
end generate;
end generate;
@@ -300,7 +302,7 @@ begin
-- User input only, BG only or no input
mux_src_out_arr <= usr_sosi_arr when g_use_usr_input = true else
bg_src_out_arr when g_use_bg = true else
- (others => c_dp_sosi_rst);
+ (others => c_dp_sosi_rst);
end generate;
-----------------------------------------------------------------------------
@@ -311,19 +313,19 @@ begin
gen_streams : for I in 0 to g_nof_streams - 1 generate
-- Add user xon flow control if the user input does not already support it
u_dp_xonoff : entity dp_lib.dp_xonoff
- generic map (
- g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Frame in
- in_siso => usr_siso_arr(I),
- in_sosi => usr_sosi_arr(I),
- -- Frame out
- out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
- out_sosi => usr_xflow_src_out_arr(I)
- );
+ generic map (
+ g_bypass => g_usr_bypass_xonoff -- if the user input already has xon flow control then bypass using g_usr_bypass_xonoff=TRUE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Frame in
+ in_siso => usr_siso_arr(I),
+ in_sosi => usr_sosi_arr(I),
+ -- Frame out
+ out_siso => usr_xflow_src_in_arr(I), -- flush control via out_siso.xon
+ out_sosi => usr_xflow_src_out_arr(I)
+ );
-- Multiplex the inputs:
-- . [0] = usr input
@@ -335,30 +337,30 @@ begin
mux_snk_in_2arr_2(I)(1) <= bg_src_out_arr(I);
u_dp_mux : entity dp_lib.dp_mux
- generic map (
- g_technology => g_technology,
- -- MUX
- g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
- g_nof_input => c_mux_nof_input, -- >= 1
- g_append_channel_lo => false,
- g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
- -- ST sinks
- snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
- snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
- -- ST source
- src_in => mux_src_in_arr(I),
- src_out => mux_src_out_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 4, -- g_mode=4 for framed input select via sel_ctrl
+ g_nof_input => c_mux_nof_input, -- >= 1
+ g_append_channel_lo => false,
+ g_sel_ctrl_invert => true, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, c_mux_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, c_mux_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ sel_ctrl => mux_ctrl, -- 0 = usr, 1 = BG
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => mux_src_in_arr(I),
+ src_out => mux_src_out_arr(I)
+ );
end generate;
end generate;
@@ -371,29 +373,28 @@ begin
gen_tx_seq : if g_use_tx_seq = true generate
u_mms_diag_tx_seq : entity work.mms_diag_tx_seq
- generic map (
- g_use_usr_input => c_use_tx_seq_input,
- g_mm_broadcast => c_reg_tx_seq_broadcast,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_seq_mosi,
- reg_miso => reg_tx_seq_miso,
-
- -- DP streaming interface
- usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
- usr_snk_in_arr => mux_src_out_arr,
- tx_src_out_arr => out_sosi_arr,
- tx_src_in_arr => out_siso_arr
- );
+ generic map (
+ g_use_usr_input => c_use_tx_seq_input,
+ g_mm_broadcast => c_reg_tx_seq_broadcast,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_seq_mosi,
+ reg_miso => reg_tx_seq_miso,
+
+ -- DP streaming interface
+ usr_snk_out_arr => mux_src_in_arr, -- connect when g_use_usr_input=TRUE, else leave not connected
+ usr_snk_in_arr => mux_src_out_arr,
+ tx_src_out_arr => out_sosi_arr,
+ tx_src_in_arr => out_siso_arr
+ );
end generate;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index 481104862a93ecb6f5472cdc59622b9bff0f40c0..c595e2b3546fbd395719dbfefd29208df1d7a12c 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer is
generic (
@@ -131,61 +131,61 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
in_sosi_arr(I).re(g_data_w - 1 downto 0) when g_data_type = e_real else
in_sosi_arr(I).im(g_data_w - 1 downto 0) when g_data_type = e_imag else
- in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
+ in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid
+ );
end generate;
end generate;
@@ -195,27 +195,26 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
-
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
index 6bfbb0dab81cfb0eead674bfed767537174eca87..4059d0678752f081dfd7a2c5d09ecf8746f3ad0d 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -58,13 +58,13 @@
-- capture some data before and after the trigger event.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_data_buffer_dev is
generic (
@@ -132,62 +132,62 @@ begin
gen_db : if g_use_db = true generate
-- Combine the internal array of mm interfaces for the data_buf to one array that is connected to the port of the MM bus
u_mem_mux_data_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_buf_adr_w
- )
- port map (
- mosi => ram_data_buf_mosi,
- miso => ram_data_buf_miso,
- mosi_arr => ram_data_buf_mosi_arr,
- miso_arr => ram_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_buf_adr_w
+ )
+ port map (
+ mosi => ram_data_buf_mosi,
+ miso => ram_data_buf_miso,
+ mosi_arr => ram_data_buf_mosi_arr,
+ miso_arr => ram_data_buf_miso_arr
+ );
u_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_data_buf_mosi,
- miso => reg_data_buf_miso,
- mosi_arr => reg_data_buf_mosi_arr,
- miso_arr => reg_data_buf_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_data_buf_mosi,
+ miso => reg_data_buf_miso,
+ mosi_arr => reg_data_buf_mosi_arr,
+ miso_arr => reg_data_buf_miso_arr
+ );
gen_stream : for I in 0 to g_nof_streams - 1 generate
in_data_arr(I) <= in_sosi_arr(I).im(g_data_w / 2 - 1 downto 0) & in_sosi_arr(I).re(g_data_w / 2 - 1 downto 0) when g_data_type = e_complex else
in_sosi_arr(I).re(g_data_w - 1 downto 0) when g_data_type = e_real else
in_sosi_arr(I).im(g_data_w - 1 downto 0) when g_data_type = e_imag else
- in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
+ in_sosi_arr(I).data(g_data_w - 1 downto 0); -- g_data_type=e_data is default
u_diag_data_buffer : entity work.diag_data_buffer_dev
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_data => g_buf_nof_data,
- g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- ram_mm_mosi => ram_data_buf_mosi_arr(I),
- ram_mm_miso => ram_data_buf_miso_arr(I),
-
- reg_mm_mosi => reg_data_buf_mosi_arr(I),
- reg_mm_miso => reg_data_buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- in_data => in_data_arr(I),
- in_sync => in_sync,
- in_val => in_sosi_arr(I).valid,
- out_wr_done => out_wr_done_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_data => g_buf_nof_data,
+ g_use_in_sync => g_buf_use_sync -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ ram_mm_mosi => ram_data_buf_mosi_arr(I),
+ ram_mm_miso => ram_data_buf_miso_arr(I),
+
+ reg_mm_mosi => reg_data_buf_mosi_arr(I),
+ reg_mm_miso => reg_data_buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ in_data => in_data_arr(I),
+ in_sync => in_sync,
+ in_val => in_sosi_arr(I).valid,
+ out_wr_done => out_wr_done_arr(I)
+ );
end generate;
end generate;
@@ -197,27 +197,26 @@ begin
gen_rx_seq : if g_use_rx_seq = true generate
u_mms_diag_rx_seq : entity work.mms_diag_rx_seq
- generic map (
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
- g_data_w => g_data_w -- >= g_seq_dat_w, user data width
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- Memory Mapped Slave
- reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
- reg_miso => reg_rx_seq_miso,
-
- -- Streaming interface
- rx_snk_in_arr => in_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_seq_dat_w => g_seq_dat_w, -- >= 1, test sequence data width
+ g_data_w => g_data_w -- >= g_seq_dat_w, user data width
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Memory Mapped Slave
+ reg_mosi => reg_rx_seq_mosi, -- multiplexed port for g_nof_streams MM control/status registers
+ reg_miso => reg_rx_seq_miso,
+
+ -- Streaming interface
+ rx_snk_in_arr => in_sosi_arr
+ );
end generate;
-
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index f3c7d796454e03e08a8990fb66ca7c26beabd44d..6484287dd31465e8775b17a8b3a704d0d0c37b72 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -1,4 +1,4 @@
- -------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -95,13 +95,13 @@
-- COUNTER increment values.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_rx_seq is
generic (
@@ -129,57 +129,59 @@ end mms_diag_rx_seq;
architecture str of mms_diag_rx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_rx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_rx_reg_nof_dat,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_rx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_rx_reg_nof_dat,
+ init_sl => '0');
- -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
- constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ), -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
- ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
- ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
- ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
- ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
- ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
- ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
- ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
+ -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
+ constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
+ ( field_name_pad("step_3"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("step_2"), "RW", c_word_w, field_default(0) ), -- [6] = diag_steps_arr[2]
+ ( field_name_pad("step_1"), "RW", c_word_w, field_default(0) ), -- [5] = diag_steps_arr[1]
+ ( field_name_pad("step_0"), "RW", c_word_w, field_default(0) ), -- [4] = diag_steps_arr[0]
+ ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ), -- [3]
+ ( field_name_pad("rx_cnt"), "RO", c_word_w, field_default(0) ), -- [2]
+ ( field_name_pad("result"), "RO", 2, field_default(0) ), -- [1] = result[1:0] = res_val_n & res_ok_n
+ ( field_name_pad("control"), "RW", 2, field_default(0) )); -- [0] = control[1:0] = diag_sel & diag_en
- constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
- constant c_reg_dat_w : natural := smallest(c_word_w, g_seq_dat_w);
+ constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
+ constant c_reg_dat_w : natural := smallest(c_word_w, g_seq_dat_w);
- constant c_nof_steps_wi : natural := c_diag_seq_rx_reg_nof_steps_wi;
+ constant c_nof_steps_wi : natural := c_diag_seq_rx_reg_nof_steps_wi;
- type t_reg_slv_arr is array (integer range <>) of std_logic_vector(c_reg_slv_w - 1 downto 0);
- type t_seq_dat_arr is array (integer range <>) of std_logic_vector(g_seq_dat_w - 1 downto 0);
- type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
- type t_steps_2arr is array (integer range <>) of t_integer_arr(g_nof_steps - 1 downto 0);
+ type t_reg_slv_arr is array (integer range <>) of std_logic_vector(c_reg_slv_w - 1 downto 0);
+ type t_seq_dat_arr is array (integer range <>) of std_logic_vector(g_seq_dat_w - 1 downto 0);
+ type t_data_arr is array (integer range <>) of std_logic_vector(g_data_w - 1 downto 0);
+ type t_steps_2arr is array (integer range <>) of t_integer_arr(g_nof_steps - 1 downto 0);
- signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
- signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
+ signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
+ signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- -- Registers in dp_clk domain
- signal ctrl_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal stat_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ -- Registers in dp_clk domain
+ signal ctrl_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ signal stat_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal diag_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_steps_2arr : t_steps_2arr(g_nof_streams - 1 downto 0);
+ signal diag_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_steps_2arr : t_steps_2arr(g_nof_streams - 1 downto 0);
- signal rx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
- signal rx_sample_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
- signal rx_sample_diff_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
- signal rx_sample_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal rx_seq_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
- signal rx_seq_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal rx_data_arr : t_data_arr(g_nof_streams - 1 downto 0);
- signal rx_data_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal rx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal rx_sample_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
+ signal rx_sample_diff_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
+ signal rx_sample_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal rx_seq_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
+ signal rx_seq_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal rx_data_arr : t_data_arr(g_nof_streams - 1 downto 0);
+ signal rx_data_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_res_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
- signal diag_res_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_res_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
+ signal diag_res_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal stat_res_ok_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal stat_res_val_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal stat_res_ok_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal stat_res_val_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
begin
assert g_data_w >= g_seq_dat_w report "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." severity FAILURE;
@@ -212,34 +214,34 @@ begin
-- detect rx sequence errors
u_diag_rx_seq: entity WORK.diag_rx_seq
- generic map (
- g_use_steps => g_use_steps,
- g_nof_steps => g_nof_steps,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_use_steps => g_use_steps,
+ g_nof_steps => g_nof_steps,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_steps_arr => diag_steps_2arr(I),
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_steps_arr => diag_steps_2arr(I),
- -- Read only registers:
- diag_res => diag_res_arr(I),
- diag_res_val => diag_res_val_arr(I),
- diag_sample => rx_sample_arr(I),
- diag_sample_diff => rx_sample_diff_arr(I),
- diag_sample_val => rx_sample_val_arr(I),
+ -- Read only registers:
+ diag_res => diag_res_arr(I),
+ diag_res_val => diag_res_val_arr(I),
+ diag_sample => rx_sample_arr(I),
+ diag_sample_diff => rx_sample_diff_arr(I),
+ diag_sample_val => rx_sample_val_arr(I),
- -- Streaming
- in_cnt => rx_cnt_arr(I),
- in_dat => rx_seq_arr(I),
- in_val => rx_seq_val_arr(I)
- );
+ -- Streaming
+ in_cnt => rx_cnt_arr(I),
+ in_dat => rx_seq_arr(I),
+ in_val => rx_seq_val_arr(I)
+ );
-- Map diag_res to single bit and register it to ease timing closure
stat_res_ok_n_arr(I) <= orv(diag_res_arr(I)) when rising_edge(dp_clk);
@@ -267,38 +269,38 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I),
- out_reg => ctrl_reg_arr(I)
- );
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I),
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 879b31e63223a9fea3b2d43bb5e8465c5d81e3be..762c5d7ddec0ca3cf7a76ed0021465604a434e9e 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -1,4 +1,4 @@
- -------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
@@ -150,12 +150,12 @@
-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
library IEEE, common_lib, dp_lib; -- init value for out_dat when diag_en = '0'
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity mms_diag_tx_seq is
generic (
@@ -185,83 +185,83 @@ end mms_diag_tx_seq;
architecture str of mms_diag_tx_seq is
-- Define MM slave register size
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_diag_seq_tx_reg_adr_w,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_diag_seq_tx_reg_nof_dat,
- init_sl => '0');
-
- -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
- constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
- ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
- ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_diag_seq_tx_reg_adr_w,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_diag_seq_tx_reg_nof_dat,
+ init_sl => '0');
- constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
+ -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
+ constant c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat - 1 downto 0) := (
+ ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
+ ( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
+ ( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
- constant c_latency : natural := sel_a_b(g_use_usr_input, 0, 1); -- default 1 for registered diag_tx_seq out_cnt/dat/val output, use 0 for immediate combinatorial diag_tx_seq out_cnt/dat/val output
+ constant c_reg_slv_w : natural := c_mm_reg.nof_dat * c_mm_reg.dat_w;
- type t_reg_slv_arr is array (integer range <>) of std_logic_vector(c_reg_slv_w - 1 downto 0);
- type t_seq_dat_arr is array (integer range <>) of std_logic_vector(g_seq_dat_w - 1 downto 0);
- type t_replicate_arr is array (integer range <>) of std_logic_vector(c_dp_stream_data_w - 1 downto 0);
+ constant c_latency : natural := sel_a_b(g_use_usr_input, 0, 1); -- default 1 for registered diag_tx_seq out_cnt/dat/val output, use 0 for immediate combinatorial diag_tx_seq out_cnt/dat/val output
- signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
- signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
+ type t_reg_slv_arr is array (integer range <>) of std_logic_vector(c_reg_slv_w - 1 downto 0);
+ type t_seq_dat_arr is array (integer range <>) of std_logic_vector(g_seq_dat_w - 1 downto 0);
+ type t_replicate_arr is array (integer range <>) of std_logic_vector(c_dp_stream_data_w - 1 downto 0);
- -- Registers in dp_clk domain
- signal ctrl_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal stat_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
+ signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- signal diag_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_dc_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ -- Registers in dp_clk domain
+ signal ctrl_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ signal stat_reg_arr : t_reg_slv_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal diag_init_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
- signal diag_init_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ signal diag_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_sel_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_dc_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal diag_mod_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c -- init value for out_dat when diag_en = '0'_mm_reg.dat_w = c_word_w = 32 fixed
- signal diag_mod_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
+ signal diag_init_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal diag_init_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal tx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
- signal tx_dat_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
- signal tx_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal tx_req_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal diag_mod_mm_arr : t_slv_32_arr(g_nof_streams - 1 downto 0) := (others => (others => '0')); -- can use t_slv_32_arr because c -- init value for out_dat when diag_en = '0'_mm_reg.dat_w = c_word_w = 32 fixed
+ signal diag_mod_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0) := (others => (others => '0'));
- signal tx_replicate_dat_arr : t_dp_data_slv_arr(g_nof_streams - 1 downto 0);
+ signal tx_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
+ signal tx_dat_arr : t_seq_dat_arr(g_nof_streams - 1 downto 0);
+ signal tx_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal tx_req_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal tx_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
- signal tx_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- default set all other fields then data and valid to inactive.
+ signal tx_replicate_dat_arr : t_dp_data_slv_arr(g_nof_streams - 1 downto 0);
- -- Use user input or self generate
- signal mux_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- multiplex user sosi control with tx_seq data
- signal mux_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal tx_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
+ signal tx_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst); -- default set all other fields then data and valid to inactive.
+ -- Use user input or self generate
+ signal mux_seq_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0); -- multiplex user sosi control with tx_seq data
+ signal mux_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
-
gen_nof_streams: for I in 0 to g_nof_streams - 1 generate
u_diag_tx_seq: entity WORK.diag_tx_seq
- generic map (
- g_latency => c_latency,
- g_cnt_w => c_word_w,
- g_dat_w => g_seq_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Write and read back registers:
- diag_en => diag_en_arr(I),
- diag_sel => diag_sel_arr(I),
- diag_dc => diag_dc_arr(I),
- diag_init => diag_init_arr(I),
- diag_mod => diag_mod_arr(I),
-
- -- Streaming
- diag_req => tx_req_arr(I),
- out_cnt => tx_cnt_arr(I),
- out_dat => tx_dat_arr(I),
- out_val => tx_val_arr(I)
- );
+ generic map (
+ g_latency => c_latency,
+ g_cnt_w => c_word_w,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Write and read back registers:
+ diag_en => diag_en_arr(I),
+ diag_sel => diag_sel_arr(I),
+ diag_dc => diag_dc_arr(I),
+ diag_init => diag_init_arr(I),
+ diag_mod => diag_mod_arr(I),
+
+ -- Streaming
+ diag_req => tx_req_arr(I),
+ out_cnt => tx_cnt_arr(I),
+ out_dat => tx_dat_arr(I),
+ out_val => tx_val_arr(I)
+ );
tx_req_arr(I) <= tx_seq_src_in_arr(I).ready;
@@ -290,41 +290,41 @@ begin
end process;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(I),
- sla_out => reg_miso_arr(I),
-
- -- MM registers in dp_clk domain
- in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
- out_reg => ctrl_reg_arr(I)
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(I),
+ sla_out => reg_miso_arr(I),
+
+ -- MM registers in dp_clk domain
+ in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
+ out_reg => ctrl_reg_arr(I)
+ );
end generate;
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_broadcast => g_mm_broadcast,
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg.adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_broadcast => g_mm_broadcast,
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg.adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
ignore_usr_input : if g_use_usr_input = false generate
-- flow control
@@ -343,7 +343,7 @@ begin
end process;
end generate;
- use_usr_input : if g_use_usr_input = true generate
+ use_usr_input : if g_use_usr_input = true generate
-- Request tx_seq data at user data valid rate
p_tx_seq_src_in_arr : process(usr_snk_in_arr)
begin
@@ -355,31 +355,31 @@ begin
-- Default output the user input or BG data, else when tx_seq is enabled overrule output with tx_seq data
usr_snk_out_arr <= mux_seq_src_in_arr;
- p_mux_seq_src_out_arr : process (usr_snk_in_arr, tx_seq_src_out_arr, diag_en_arr)
- begin
- mux_seq_src_out_arr <= usr_snk_in_arr;
- for I in 0 to g_nof_streams - 1 loop
- if diag_en_arr(I) = '1' then
- mux_seq_src_out_arr(I).data <= tx_seq_src_out_arr(I).data;
- end if;
- end loop;
- end process;
-
- -- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
- u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out_arr => mux_seq_src_in_arr,
- snk_in_arr => mux_seq_src_out_arr,
- -- ST source
- src_in_arr => tx_src_in_arr,
- src_out_arr => tx_src_out_arr
- );
- end generate;
+p_mux_seq_src_out_arr : process (usr_snk_in_arr, tx_seq_src_out_arr, diag_en_arr)
+begin
+ mux_seq_src_out_arr <= usr_snk_in_arr;
+ for I in 0 to g_nof_streams - 1 loop
+ if diag_en_arr(I) = '1' then
+ mux_seq_src_out_arr(I).data <= tx_seq_src_out_arr(I).data;
+ end if;
+ end loop;
+end process;
+
+-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
+u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
+ generic map (
+ g_nof_streams => g_nof_streams
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out_arr => mux_seq_src_in_arr,
+ snk_in_arr => mux_seq_src_out_arr,
+ -- ST source
+ src_in_arr => tx_src_in_arr,
+ src_out_arr => tx_src_out_arr
+ );
+end generate;
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index f23fda685ab1f622c0321940856a5ca84a576d68..8840d62fb3fb5563dc2b076d5653b01ba10ab126 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -28,12 +28,12 @@
--
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband is
generic (
@@ -82,64 +82,64 @@ architecture str of mms_diag_wg_wideband is
signal st_mon_ctrl : t_diag_wg; -- read
begin
u_mm_reg : entity work.diag_wg_wideband_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- st_wg_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl
- );
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ st_wg_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl
+ );
u_wg_wideband : entity work.diag_wg_wideband
- generic map (
- g_technology => g_technology,
- -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
- g_buf_dir => g_buf_dir,
-
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
- mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
- mm_wr => buf_mosi.wr,
- mm_rd => buf_mosi.rd,
- mm_rdval => buf_miso.rdval,
- mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
-
- st_ctrl => st_wg_ctrl,
- st_mon_ctrl => st_mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ g_technology => g_technology,
+ -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
+ g_buf_dir => g_buf_dir,
+
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ mm_wrdata => buf_mosi.wrdata(g_buf_dat_w - 1 downto 0),
+ mm_address => buf_mosi.address(g_buf_addr_w - 1 downto 0),
+ mm_wr => buf_mosi.wr,
+ mm_rd => buf_mosi.rd,
+ mm_rdval => buf_miso.rdval,
+ mm_rddata => buf_miso.rddata(g_buf_dat_w - 1 downto 0),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ st_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index aa5b1be2c4a74ae4c5562355099407b9ae6428c3..3bd3d7c99d6c09daa715f797c07441add0bcf5f7 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -27,13 +27,13 @@
-- no need to make a mms_diag_wg.vhd.
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_diag_wg_wideband_arr is
generic (
@@ -89,63 +89,63 @@ architecture str of mms_diag_wg_wideband_arr is
signal wg_sync : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
begin
u_common_mem_mux_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
u_common_mem_mux_buf : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => g_buf_addr_w
- )
- port map (
- mosi => buf_mosi,
- miso => buf_miso,
- mosi_arr => buf_mosi_arr,
- miso_arr => buf_miso_arr
- );
-
- gen_wg : for I in 0 to g_nof_streams - 1 generate
- u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
generic map (
- g_technology => g_technology,
- g_cross_clock_domain => g_cross_clock_domain,
- g_buf_dir => g_buf_dir,
- g_wideband_factor => g_wideband_factor,
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => g_calc_support,
- g_calc_gain_w => g_calc_gain_w,
- g_calc_dat_w => g_calc_dat_w
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => g_buf_addr_w
)
port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mosi => buf_mosi,
+ miso => buf_miso,
+ mosi_arr => buf_mosi_arr,
+ miso_arr => buf_miso_arr
+ );
- reg_mosi => reg_mosi_arr(I),
- reg_miso => reg_miso_arr(I),
-
- buf_mosi => buf_mosi_arr(I),
- buf_miso => buf_miso_arr(I),
-
- -- Streaming clock domain
- st_rst => st_rst,
- st_clk => st_clk,
- st_restart => st_restart,
-
- out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
- out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
- out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
- );
+ gen_wg : for I in 0 to g_nof_streams - 1 generate
+ u_mms_diag_wg_wideband : entity work.mms_diag_wg_wideband
+ generic map (
+ g_technology => g_technology,
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_buf_dir => g_buf_dir,
+ g_wideband_factor => g_wideband_factor,
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => g_calc_support,
+ g_calc_gain_w => g_calc_gain_w,
+ g_calc_dat_w => g_calc_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi_arr(I),
+ reg_miso => reg_miso_arr(I),
+
+ buf_mosi => buf_mosi_arr(I),
+ buf_miso => buf_miso_arr(I),
+
+ -- Streaming clock domain
+ st_rst => st_rst,
+ st_clk => st_clk,
+ st_restart => st_restart,
+
+ out_ovr => wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_dat => wg_dat( (I + 1) * g_wideband_factor * g_buf_dat_w - 1 downto I * g_wideband_factor * g_buf_dat_w),
+ out_val => wg_val( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ),
+ out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
+ );
-- wire the wg signals to sosi outputs
-- This is done as per the method used in unb1_bn_capture_input (Apertif)
@@ -156,7 +156,6 @@ begin
out_sosi_arr(I).sync <= vector_or(wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor ));
out_sosi_arr(I).err <= TO_DP_ERROR(0) when
vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
- TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
+ TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
end generate;
-
end str;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index 4ec82902c6ca8e98b25b9a1fada143f717c71bd9..4ff4c7defe45a1b67b50f3beeb1a8ba75b1969ae 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -28,17 +28,17 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_math_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_math_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_block_gen is
generic (
@@ -51,7 +51,7 @@ entity tb_diag_block_gen is
g_buf_adr_w : natural := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
g_buf_dat_w : natural := 32; -- Waveform buffer stored data width (requires corresponding c_buf_file)
g_try_phasor : boolean := false -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
);
end tb_diag_block_gen;
@@ -62,88 +62,91 @@ architecture tb of tb_diag_block_gen is
constant c_runtime : natural := 1500;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w,
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
-
- constant c_buf_file : string := sel_a_b(c_buf.adr_w = 7 and c_buf.dat_w = 32, "data/diag_block.hex", "UNUSED");
-
- constant c_cntr_init : integer := 0;
- constant c_cntr_incr : integer := 1;
- constant c_cntr_arr : t_slv_32_arr(c_buf.nof_dat - 1 downto 0) := flip(array_init(c_cntr_init, c_buf.nof_dat, c_cntr_incr));
-
- -- Phasor: exp(j*angle) = cos(angle) + j*sin(angle)
- -- A complex FFT of N points has N bins or channels: ch = -N/2:0:N/2-1.
- -- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
- constant c_phasor_nof_points : natural := 96;
- constant c_phasor_dat_w : natural := g_buf_dat_w / c_nof_complex;
- constant c_phasor_unit_ampl : real := real(2**(c_phasor_dat_w - 1) - 1); -- max = full scale - 1
- constant c_phasor_ampl : real := 1.0 * c_phasor_unit_ampl; -- use g_phasor_ampl <= 1.0 to avoid wrapping
- constant c_phasor_freq : real := 2.0; -- in range -N/2 : N/2-1
- constant c_phasor_phase : real := 0.0;
- constant c_phasor_exp_arr : t_slv_32_arr := common_math_create_look_up_table_phasor(c_phasor_nof_points,
- c_phasor_dat_w,
- c_phasor_ampl,
- c_phasor_freq,
- c_phasor_phase);
-
- -- Default BG control
- constant c_bg_ctrl : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
- TO_UVEC(42, c_diag_bg_bsn_init_w));
- constant c_bg_period : natural := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
-
- -- Some alternative BG control settings
- constant c_alternative_mem_low_adrs : natural := 1;
- constant c_alternative_mem_high_adrs : natural := 64;
- constant c_alternative_data_gap : natural := 1 + c_alternative_mem_low_adrs;
-
- -- Another BG control for verifying XON
- constant c_bg_ctrl2 : t_diag_block_gen := ( '0',
- '0',
- TO_UVEC(17, c_diag_bg_samples_per_packet_w),
- TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 0, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
- constant c_bg_period2 : natural := TO_UINT(c_bg_ctrl2.samples_per_packet) + TO_UINT(c_bg_ctrl2.gapsize);
-
- signal tb_end : std_logic := '0';
- signal rst : std_logic;
- signal clk : std_logic := '1';
-
- signal verify_en : std_logic := '0';
- signal verify_en_data : std_logic;
-
- signal mm_buf_arr : t_slv_32_arr(c_buf.nof_dat - 1 downto 0);
- signal mm_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal mm_buf_miso : t_mem_miso;
-
- signal bg_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
- signal bg_buf_miso : t_mem_miso;
-
- signal bg_ctrl : t_diag_block_gen;
- signal bg_ctrl_hold : t_diag_block_gen;
-
- signal random : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
- signal toggle : std_logic := '0';
- signal out_siso_bg : t_dp_siso := c_dp_siso_rdy;
- signal out_siso : t_dp_siso;
- signal out_sosi : t_dp_sosi;
- signal prev_out_sosi : t_dp_sosi;
- signal hold_sop : std_logic := '0';
- signal last_size : natural;
- signal exp_size : natural;
- signal cnt_size : natural;
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w,
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0');
+
+ constant c_buf_file : string := sel_a_b(c_buf.adr_w = 7 and c_buf.dat_w = 32, "data/diag_block.hex", "UNUSED");
+
+ constant c_cntr_init : integer := 0;
+ constant c_cntr_incr : integer := 1;
+ constant c_cntr_arr : t_slv_32_arr(c_buf.nof_dat - 1 downto 0) := flip(array_init(c_cntr_init, c_buf.nof_dat, c_cntr_incr));
+
+ -- Phasor: exp(j*angle) = cos(angle) + j*sin(angle)
+ -- A complex FFT of N points has N bins or channels: ch = -N/2:0:N/2-1.
+ -- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
+ constant c_phasor_nof_points : natural := 96;
+ constant c_phasor_dat_w : natural := g_buf_dat_w / c_nof_complex;
+ constant c_phasor_unit_ampl : real := real(2 ** (c_phasor_dat_w - 1) - 1); -- max = full scale - 1
+ constant c_phasor_ampl : real := 1.0 * c_phasor_unit_ampl; -- use g_phasor_ampl <= 1.0 to avoid wrapping
+ constant c_phasor_freq : real := 2.0; -- in range -N/2 : N/2-1
+ constant c_phasor_phase : real := 0.0;
+ constant c_phasor_exp_arr : t_slv_32_arr := common_math_create_look_up_table_phasor(c_phasor_nof_points,
+ c_phasor_dat_w,
+ c_phasor_ampl,
+ c_phasor_freq,
+ c_phasor_phase);
+
+ -- Default BG control
+ constant c_bg_ctrl : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(g_nof_samples_per_packet, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(g_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(95, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(42, c_diag_bg_bsn_init_w));
+ constant c_bg_period : natural := TO_UINT(c_bg_ctrl.samples_per_packet) + TO_UINT(c_bg_ctrl.gapsize);
+
+ -- Some alternative BG control settings
+ constant c_alternative_mem_low_adrs : natural := 1;
+ constant c_alternative_mem_high_adrs : natural := 64;
+ constant c_alternative_data_gap : natural := 1 + c_alternative_mem_low_adrs;
+
+ -- Another BG control for verifying XON
+ constant c_bg_ctrl2 : t_diag_block_gen := (
+ '0',
+ '0',
+ TO_UVEC(17, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(g_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( 0, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(16, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
+ constant c_bg_period2 : natural := TO_UINT(c_bg_ctrl2.samples_per_packet) + TO_UINT(c_bg_ctrl2.gapsize);
+
+ signal tb_end : std_logic := '0';
+ signal rst : std_logic;
+ signal clk : std_logic := '1';
+
+ signal verify_en : std_logic := '0';
+ signal verify_en_data : std_logic;
+
+ signal mm_buf_arr : t_slv_32_arr(c_buf.nof_dat - 1 downto 0);
+ signal mm_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal mm_buf_miso : t_mem_miso;
+
+ signal bg_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
+ signal bg_buf_miso : t_mem_miso;
+
+ signal bg_ctrl : t_diag_block_gen;
+ signal bg_ctrl_hold : t_diag_block_gen;
+
+ signal random : std_logic_vector(14 downto 0) := (others => '0'); -- use different lengths to have different random sequences
+ signal toggle : std_logic := '0';
+ signal out_siso_bg : t_dp_siso := c_dp_siso_rdy;
+ signal out_siso : t_dp_siso;
+ signal out_sosi : t_dp_sosi;
+ signal prev_out_sosi : t_dp_sosi;
+ signal hold_sop : std_logic := '0';
+ signal last_size : natural;
+ signal exp_size : natural;
+ signal cnt_size : natural;
begin
rst <= '1', '0' after clk_period * 10;
@@ -226,46 +229,46 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => mm_buf_mosi.wr,
- wr_en_b => '0',
- wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
- wr_dat_b => (others => '0'),
- adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- rd_en_a => mm_buf_mosi.rd,
- rd_en_b => bg_buf_mosi.rd,
- rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- rd_val_a => mm_buf_miso.rdval,
- rd_val_b => bg_buf_miso.rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => mm_buf_mosi.wr,
+ wr_en_b => '0',
+ wr_dat_a => mm_buf_mosi.wrdata(c_buf.dat_w - 1 downto 0),
+ wr_dat_b => (others => '0'),
+ adr_a => mm_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ adr_b => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ rd_en_a => mm_buf_mosi.rd,
+ rd_en_b => bg_buf_mosi.rd,
+ rd_dat_a => mm_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_dat_b => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ rd_val_a => mm_buf_miso.rdval,
+ rd_val_b => bg_buf_miso.rdval
+ );
u_dut : entity work.diag_block_gen
- generic map(
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w
- )
- port map (
- rst => rst,
- clk => clk,
- buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
- buf_rden => bg_buf_mosi.rd,
- buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
- buf_rdval => bg_buf_miso.rdval,
- ctrl => bg_ctrl,
- ctrl_hold => bg_ctrl_hold,
- out_siso => out_siso_bg,
- out_sosi => out_sosi
- );
+ generic map(
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ buf_addr => bg_buf_mosi.address(c_buf.adr_w - 1 downto 0),
+ buf_rden => bg_buf_mosi.rd,
+ buf_rddat => bg_buf_miso.rddata(c_buf.dat_w - 1 downto 0),
+ buf_rdval => bg_buf_miso.rdval,
+ ctrl => bg_ctrl,
+ ctrl_hold => bg_ctrl_hold,
+ out_siso => out_siso_bg,
+ out_sosi => out_sosi
+ );
random <= func_common_random(random) when rising_edge(clk);
toggle <= not toggle when rising_edge(clk);
@@ -273,5 +276,5 @@ begin
out_siso_bg.xon <= out_siso.xon;
out_siso_bg.ready <= '1' when g_flow_control_verify = e_active else
random(random'high) when g_flow_control_verify = e_random else
- toggle when g_flow_control_verify = e_pulse;
+ toggle when g_flow_control_verify = e_pulse;
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
index 730f6e6fd09da0c50d49770af15a43ab66d7cb46..16324f99d604d84307ffac4294f5827dd1f71c9f 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
@@ -38,17 +38,17 @@
-- > Evalute the WAVE window.
library IEEE, common_lib, mm_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_data_buffer is
generic(
@@ -111,14 +111,15 @@ architecture tb of tb_diag_data_buffer is
constant c_bg_nof_blocks_per_sync : natural := 8;
constant c_bg_mem_high_addr : natural := g_nof_data - 1;
- constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
- '0', -- enable_sync
- TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable: On by default in simulation; MM enable required on hardware.
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_nof_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_mem_high_addr, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- Configuration of the databuffers:
constant c_db_nof_streams : positive := g_nof_streams;
@@ -151,7 +152,7 @@ begin
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
- ----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
@@ -213,10 +214,10 @@ begin
end loop;
nof_valids <= 1;
--- WHILE nof_valids /= 0 LOOP
- proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
- nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
--- END LOOP;
+ -- WHILE nof_valids /= 0 LOOP
+ proc_mem_mm_bus_rd( 2, mm_clk, reg_diag_data_buf_mosi);
+ nof_valids <= TO_UINT(reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0));
+ -- END LOOP;
proc_common_wait_some_cycles(mm_clk, 10);
-- Arm the databuffer
@@ -229,55 +230,55 @@ begin
-- Source: block generator
----------------------------------------------------------------------------
u_bg : entity work.mms_diag_block_gen
- generic map(
- g_nof_streams => c_bg_nof_output_streams,
- g_buf_dat_w => c_bg_buf_dat_w,
- g_buf_addr_w => c_bg_buf_adr_w,
- g_file_index_arr => c_bg_data_file_index_arr,
- g_diag_block_gen_rst => c_bg_ctrl,
- g_file_name_prefix => c_bg_data_file_prefix
- )
- port map(
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- en_sync => dp_pps,
- -- MM interface
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso,
- -- ST interface
- out_siso_arr => bg_siso_arr,
- out_sosi_arr => bg_sosi_arr
- );
+ generic map(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_diag_block_gen_rst => c_bg_ctrl,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ port map(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut : entity work.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_db_nof_streams,
- g_data_type => c_db_data_type_re,
- g_data_w => c_db_data_w,
- g_buf_nof_data => c_db_buf_nof_data,
- g_buf_use_sync => c_db_buf_use_sync
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM interface
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
- -- ST interface
- in_sync => bg_sosi_arr(0).sync,
- in_sosi_arr => bg_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => bg_sosi_arr(0).sync,
+ in_sosi_arr => bg_sosi_arr
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 0156020ba1138a03ae236d87d53eddbba45c1bfb..e6868681137b0aa3d6715270aecf490809848026 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_generator is
end tb_diag_frm_generator;
@@ -72,7 +72,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 200 us
+ -- run 200 us
begin
diag_sel <= c_sel;
diag_frame_len <= TO_UVEC(c_frame_len, c_frame_len_w);
@@ -124,35 +124,35 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_symbol_w,
- g_empty => c_empty
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- diag_sof_period => diag_sof_period,
- diag_frame_cnt => diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop,
- out_empty => seq_empty
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_symbol_w,
+ g_empty => c_empty
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ diag_sof_period => diag_sof_period,
+ diag_frame_cnt => diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop,
+ out_empty => seq_empty
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index ef5aa9aa48e93ec8f7de2ecba6b89e29951dab31..797720e3c5dbfd6e1deb68ac1f56c895cd6fc255 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_frm_monitor is
end tb_diag_frm_monitor;
@@ -75,7 +75,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 200 us
+ -- run 200 us
begin
gen_diag_sel <= c_sel;
gen_diag_frame_len <= TO_UVEC(c_frame_len, c_frame_len_w);
@@ -125,53 +125,53 @@ begin
end process;
u_frm_gen : entity work.diag_frm_generator
- generic map (
- g_sel => c_sel,
- g_frame_len => c_frame_len,
- g_sof_period => c_sof_period,
- g_frame_cnt_w => c_frame_cnt_w,
- g_dat_w => c_dat_w,
- g_symbol_w => c_dat_w,
- g_empty => 0
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM or leave open to use default)
- diag_en => gen_diag_en,
- diag_sel => gen_diag_sel,
- diag_frame_len => gen_diag_frame_len,
- diag_sof_period => gen_diag_sof_period,
- diag_frame_cnt => gen_diag_frame_cnt,
-
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_frame_len => c_frame_len,
+ g_sof_period => c_sof_period,
+ g_frame_cnt_w => c_frame_cnt_w,
+ g_dat_w => c_dat_w,
+ g_symbol_w => c_dat_w,
+ g_empty => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM or leave open to use default)
+ diag_en => gen_diag_en,
+ diag_sel => gen_diag_sel,
+ diag_frame_len => gen_diag_frame_len,
+ diag_sof_period => gen_diag_sof_period,
+ diag_frame_cnt => gen_diag_frame_cnt,
+
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
u_frm_mon : entity work.diag_frm_monitor
- generic map (
- g_frame_cnt_w => c_frame_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
-
- -- Static control input (connect via MM)
- diag_en => mon_diag_en,
- diag_frame_cnt => mon_diag_frame_cnt,
- diag_error_cnt => mon_diag_error_cnt,
-
- -- ST input
- in_eop => seq_eop,
- in_error => seq_error
- );
+ generic map (
+ g_frame_cnt_w => c_frame_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+
+ -- Static control input (connect via MM)
+ diag_en => mon_diag_en,
+ diag_frame_cnt => mon_diag_frame_cnt,
+ diag_error_cnt => mon_diag_error_cnt,
+
+ -- ST input
+ in_eop => seq_eop,
+ in_error => seq_error
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 7e2bccd25837d6336000f2f54d2946ec59638424..3b432e72ceeb2ef95a65899220793fefdf3ee6ae 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -23,16 +23,16 @@
-- Purpose: Test bench package for diag library
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
package tb_diag_pkg is
-- Test modes for diag seq
@@ -43,163 +43,176 @@ package tb_diag_pkg is
s_expect_no_result
);
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
-
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
+ procedure proc_diag_seq_read_all(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_tx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_rx_write_steps(
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg); -- read all MM reg
+
+ procedure proc_diag_seq_verify(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg); -- read all MM reg
-- Measure ADC/WG input power and determine effective sine amplitude
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real); -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics( -- number of samples per in_start interval
+ constant c_nof_samples : in natural;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real); -- corresponding sine amplitude
-- Measure ADC/WG amplitude and phase using local sin and cos
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real); -- measured CW phase in sample periods
-
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real);
+ procedure proc_diag_measure_cw_ampl_and_phase( -- number of samples per in_start interval
+ constant c_nof_samples : in natural;
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real); -- measured CW phase in sample periods
+
+ procedure proc_diag_measure_cw_ampl_and_phase( -- number of points of FFT = number of samples per in_start interval
+ constant c_fft_size : in natural;
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real);
-- Use estimated CW to determine noise power in input sine (e.g. WG sine)
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real); -- measured noise power in in_dat
-
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real);
+ procedure proc_diag_measure_cw_noise_power( -- number of samples per integration interval
+ constant c_nof_samples : in natural;
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real); -- measured noise power in in_dat
+
+ procedure proc_diag_measure_cw_noise_power( -- number of points of FFT = number of samples per in_start interval
+ constant c_fft_size : in natural;
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real);
end tb_diag_pkg;
package body tb_diag_pkg is
- procedure proc_diag_seq_read_all(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
- constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
+ procedure proc_diag_seq_read_all(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_tx_offset : natural := c_stream * 2 ** c_diag_seq_tx_reg_adr_w;
+ constant c_rx_offset : natural := c_stream * 2 ** c_diag_seq_rx_reg_adr_w;
begin
---------------------------------------------------------------------------
-- Readback ctrl
@@ -251,18 +264,19 @@ package body tb_diag_pkg is
rd_reg.rx_sample <= rx_miso.rddata(c_word_w - 1 downto 0);
end proc_diag_seq_read_all;
- procedure proc_diag_seq_tx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- constant c_tx_init : in natural;
- constant c_tx_mod : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
+ procedure proc_diag_seq_tx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ constant c_tx_init : in natural;
+ constant c_tx_mod : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_tx_offset : natural := c_stream * 2 ** c_diag_seq_tx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
variable v_ctlr : natural;
@@ -281,16 +295,17 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_enable;
- procedure proc_diag_seq_rx_enable(constant c_stream : in natural;
- constant c_pattern : in string; -- "PSRG", "CNTR"
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
+ procedure proc_diag_seq_rx_enable(
+ constant c_stream : in natural;
+ constant c_pattern : in string; -- "PSRG", "CNTR"
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_rx_offset : natural := c_stream * 2 ** c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
variable v_ctlr : natural;
@@ -306,46 +321,49 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_enable;
- procedure proc_diag_seq_tx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_tx_offset : natural := c_stream * 2**c_diag_seq_tx_reg_adr_w;
+ procedure proc_diag_seq_tx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_tx_offset : natural := c_stream * 2 ** c_diag_seq_tx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_tx_offset + 0, 0, mm_clk, tx_miso, tx_mosi);
proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_tx_disable;
- procedure proc_diag_seq_rx_disable(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
+ procedure proc_diag_seq_rx_disable(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_rx_offset : natural := c_stream * 2 ** c_diag_seq_rx_reg_adr_w;
begin
proc_mem_mm_bus_wr(c_rx_offset + 0, 0, mm_clk, rx_miso, rx_mosi);
proc_common_wait_some_cycles(mm_clk, dp_clk, 10); -- wait for clock domain crossing
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_disable;
- procedure proc_diag_seq_rx_write_steps(constant c_stream : in natural;
- constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
- signal mm_clk : in std_logic;
- signal dp_clk : in std_logic;
- signal tx_miso : in t_mem_miso; -- tx ctrl
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso; -- rx ctrl
- signal rx_mosi : out t_mem_mosi;
- signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
- constant c_rx_offset : natural := c_stream * 2**c_diag_seq_rx_reg_adr_w;
+ procedure proc_diag_seq_rx_write_steps(
+ constant c_stream : in natural;
+ constant c_steps_arr : in t_integer_arr(c_diag_seq_rx_reg_nof_steps - 1 downto 0);
+ signal mm_clk : in std_logic;
+ signal dp_clk : in std_logic;
+ signal tx_miso : in t_mem_miso; -- tx ctrl
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso; -- rx ctrl
+ signal rx_mosi : out t_mem_mosi;
+ signal rd_reg : out t_diag_seq_mm_reg) is -- read all MM reg
+ constant c_rx_offset : natural := c_stream * 2 ** c_diag_seq_rx_reg_adr_w;
constant c_en : natural := 1;
variable v_sel : natural;
variable v_ctlr : natural;
@@ -358,19 +376,20 @@ package body tb_diag_pkg is
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
end proc_diag_seq_rx_write_steps;
- procedure proc_diag_seq_verify(constant c_stream : in natural;
- signal mm_clk : in std_logic;
- signal tx_miso : in t_mem_miso;
- signal tx_mosi : out t_mem_mosi;
- signal rx_miso : in t_mem_miso;
- signal rx_mosi : out t_mem_mosi;
- signal tb_mode : inout t_tb_diag_seq_mode_enum;
- signal tb_verify : out std_logic;
- signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
- variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
- variable v_rx_cnt : natural;
- variable v_tx_cnt : natural;
+ procedure proc_diag_seq_verify(
+ constant c_stream : in natural;
+ signal mm_clk : in std_logic;
+ signal tx_miso : in t_mem_miso;
+ signal tx_mosi : out t_mem_mosi;
+ signal rx_miso : in t_mem_miso;
+ signal rx_mosi : out t_mem_mosi;
+ signal tb_mode : inout t_tb_diag_seq_mode_enum;
+ signal tb_verify : out std_logic;
+ signal rd_reg : inout t_diag_seq_mm_reg) is -- read all MM reg
+ variable v_rx_stat : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_sample : std_logic_vector(c_word_w - 1 downto 0);
+ variable v_rx_cnt : natural;
+ variable v_tx_cnt : natural;
begin
-- Read all
proc_diag_seq_read_all(c_stream, mm_clk, tx_miso, tx_mosi, rx_miso, rx_mosi, rd_reg);
@@ -459,20 +478,21 @@ package body tb_diag_pkg is
-- measure DC.
-- . accumulate samples during interval and calculate effective amplitude.
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_statistics(constant c_nof_samples : in natural; -- number of samples per in_start interval
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal track_max : inout real; -- store local tracker in signal
- signal track_min : inout real; -- store local tracker in signal
- signal accum_mean : inout real; -- store local accumulator in signal
- signal accum_power : inout real; -- store local accumulator in signal
- signal measured_max : out real; -- maximum sample value
- signal measured_min : out real; -- minimum sample value
- signal measured_mean : out real; -- average sample value (DC)
- signal measured_power : out real; -- average sample power
- signal measured_ampl : out real) is -- corresponding sine amplitude
+ procedure proc_diag_measure_cw_statistics( -- number of samples per in_start interval
+ constant c_nof_samples : in natural;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal track_max : inout real; -- store local tracker in signal
+ signal track_min : inout real; -- store local tracker in signal
+ signal accum_mean : inout real; -- store local accumulator in signal
+ signal accum_power : inout real; -- store local accumulator in signal
+ signal measured_max : out real; -- maximum sample value
+ signal measured_min : out real; -- minimum sample value
+ signal measured_mean : out real; -- average sample value (DC)
+ signal measured_power : out real; -- average sample power
+ signal measured_ampl : out real) is -- corresponding sine amplitude
constant c_Nsamples : real := real(c_nof_samples);
constant c_dat : real := real(TO_SINT(in_dat));
constant c_mean : real := accum_mean / c_Nsamples;
@@ -490,13 +510,13 @@ package body tb_diag_pkg is
track_max <= real'low;
track_min <= real'high;
accum_mean <= c_dat;
- accum_power <= (abs(c_dat))**2.0; -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
+ accum_power <= (abs(c_dat)) ** 2.0; -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
elsif in_val = '1' then
-- Detect and accumulate during interval
track_max <= largest(track_max, c_dat);
track_min <= smallest(track_min, c_dat);
accum_mean <= accum_mean + c_dat;
- accum_power <= accum_power + (abs(c_dat))**2.0;
+ accum_power <= accum_power + (abs(c_dat)) ** 2.0;
end if;
end if;
end proc_diag_measure_cw_statistics;
@@ -539,21 +559,22 @@ package body tb_diag_pkg is
-- . the sine power of the perfect reference CW (carrier wave) is:
-- cwPower = (A**2)/2
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_nof_samples : in natural; -- number of samples per in_start interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal ref_I : out real; -- output local I as signal for debugging in wave window
- signal ref_Q : out real; -- output local Q as signal for debugging in wave window
- signal accum_I : inout real; -- store local I accumulator in signal
- signal accum_Q : inout real; -- store local Q accumulator in signal
- signal measured_ampl : out real; -- measured CW amplitude
- signal measured_phase : out real; -- measured CW phase in radials
- signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
+ procedure proc_diag_measure_cw_ampl_and_phase( -- number of samples per in_start interval
+ constant c_nof_samples : in natural;
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal ref_I : out real; -- output local I as signal for debugging in wave window
+ signal ref_Q : out real; -- output local Q as signal for debugging in wave window
+ signal accum_I : inout real; -- store local I accumulator in signal
+ signal accum_Q : inout real; -- store local Q accumulator in signal
+ signal measured_ampl : out real; -- measured CW amplitude
+ signal measured_phase : out real; -- measured CW phase in radials
+ signal measured_phase_Ts : out real) is -- measured CW phase in sample periods
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -588,25 +609,26 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_ampl_and_phase;
- procedure proc_diag_measure_cw_ampl_and_phase(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal ref_I : out real;
- signal ref_Q : out real;
- signal accum_I : inout real;
- signal accum_Q : inout real;
- signal measured_ampl : out real;
- signal measured_phase : out real;
- signal measured_phase_Ts : out real) is
+ procedure proc_diag_measure_cw_ampl_and_phase( -- number of points of FFT = number of samples per in_start interval
+ constant c_fft_size : in natural;
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal ref_I : out real;
+ signal ref_Q : out real;
+ signal accum_I : inout real;
+ signal accum_Q : inout real;
+ signal measured_ampl : out real;
+ signal measured_phase : out real;
+ signal measured_phase_Ts : out real) is
begin
proc_diag_measure_cw_ampl_and_phase(c_fft_size, c_fft_size, c_sub, dp_clk,
- in_dat, in_start, in_val, in_cnt,
- ref_I, ref_Q, accum_I, accum_Q,
- measured_ampl, measured_phase, measured_phase_Ts);
+ in_dat, in_start, in_val, in_cnt,
+ ref_I, ref_Q, accum_I, accum_Q,
+ measured_ampl, measured_phase, measured_phase_Ts);
end proc_diag_measure_cw_ampl_and_phase;
---------------------------------------------------------------------------
@@ -629,20 +651,21 @@ package body tb_diag_pkg is
--
-- SNR = 10*log10(cwPower / noisePower) [dB]
---------------------------------------------------------------------------
- procedure proc_diag_measure_cw_noise_power(constant c_nof_samples : in natural; -- number of samples per integration interval
- constant c_fft_size : in natural; -- number of points of FFT
- constant c_sub : in real; -- subband index
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
- signal in_val : in std_logic;
- signal in_cnt : in natural; -- sample index in c_fft_size
- signal cw_ampl : in real; -- estimated CW amplitude of in_dat
- signal cw_phase : in real; -- estimated CW phase of in_dat
- signal cw_dat : out integer; -- estimated CW
- signal cw_noise : out real; -- estimated CW quantization noise
- signal accum_noise_power : inout real; -- store noise power accumulator in signal
- signal measured_noise_power : out real) is -- measured noise power in in_dat
+ procedure proc_diag_measure_cw_noise_power( -- number of samples per integration interval
+ constant c_nof_samples : in natural;
+ constant c_fft_size : in natural; -- number of points of FFT
+ constant c_sub : in real; -- subband index
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic; -- start of integration interval, e.g. sop or sync
+ signal in_val : in std_logic;
+ signal in_cnt : in natural; -- sample index in c_fft_size
+ signal cw_ampl : in real; -- estimated CW amplitude of in_dat
+ signal cw_phase : in real; -- estimated CW phase of in_dat
+ signal cw_dat : out integer; -- estimated CW
+ signal cw_noise : out real; -- estimated CW quantization noise
+ signal accum_noise_power : inout real; -- store noise power accumulator in signal
+ signal measured_noise_power : out real) is -- measured noise power in in_dat
constant c_Nsamples : real := real(c_nof_samples);
constant c_Nfft : real := real(c_fft_size);
constant c_omega : real := MATH_2_PI * c_sub / c_Nfft;
@@ -652,7 +675,7 @@ package body tb_diag_pkg is
constant c_angle : real := (c_k * c_omega + cw_phase + c_lat) mod MATH_2_PI; -- keep angle in SIN(), COS() within 2pi to avoid "Error: XLOCAL <= 0.0 after reduction in COS(X)"
constant c_cw : real := cw_ampl * SIN(c_angle);
constant c_noise : real := c_cw - c_dat;
- constant c_noise_power : real := (abs(c_noise))**2.0;
+ constant c_noise_power : real := (abs(c_noise)) ** 2.0;
begin
if rising_edge(dp_clk) then
if in_val = '1' then
@@ -671,24 +694,25 @@ package body tb_diag_pkg is
end if;
end proc_diag_measure_cw_noise_power;
- procedure proc_diag_measure_cw_noise_power(constant c_fft_size : in natural; -- number of points of FFT = number of samples per in_start interval
- constant c_sub : in real;
- signal dp_clk : in std_logic;
- signal in_dat : in std_logic_vector;
- signal in_start : in std_logic;
- signal in_val : in std_logic;
- signal in_cnt : in natural;
- signal cw_ampl : in real;
- signal cw_phase : in real;
- signal cw_dat : out integer;
- signal cw_noise : out real;
- signal accum_noise_power : inout real;
- signal measured_noise_power : out real) is
+ procedure proc_diag_measure_cw_noise_power( -- number of points of FFT = number of samples per in_start interval
+ constant c_fft_size : in natural;
+ constant c_sub : in real;
+ signal dp_clk : in std_logic;
+ signal in_dat : in std_logic_vector;
+ signal in_start : in std_logic;
+ signal in_val : in std_logic;
+ signal in_cnt : in natural;
+ signal cw_ampl : in real;
+ signal cw_phase : in real;
+ signal cw_dat : out integer;
+ signal cw_noise : out real;
+ signal accum_noise_power : inout real;
+ signal measured_noise_power : out real) is
begin
proc_diag_measure_cw_noise_power(c_fft_size, c_fft_size, c_sub, dp_clk,
- in_dat, in_start, in_val, in_cnt,
- cw_ampl, cw_phase, cw_dat, cw_noise,
- accum_noise_power, measured_noise_power);
+ in_dat, in_start, in_val, in_cnt,
+ cw_ampl, cw_phase, cw_dat, cw_noise,
+ accum_noise_power, measured_noise_power);
end proc_diag_measure_cw_noise_power;
end tb_diag_pkg;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
index e34799d1dcbe04b9a48f2fbb2651bc366f212a2c..546d2f36b1f209d70d4242ed1a94a04c6c3b218e 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
@@ -29,7 +29,7 @@
-- > run -all
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
entity tb_diag_regression is
end tb_diag_regression;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 35316f212a397ab0d11e1ec96573a1e7135f494a..fb85179a0eae2ca514a656ce08fd6126f3b9cbdd 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -21,10 +21,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
-- Purpose: test bench for diag_rx_seq control
-- Usage:
@@ -56,7 +56,7 @@ architecture tb of tb_diag_rx_seq is
constant c_diag_res_w : natural := g_seq_dat_w + 1;
constant c_diag_res_ok : std_logic_vector(c_diag_res_w - 1 downto 0) := '0' & TO_UVEC( 0, c_diag_res_w - 1);
- constant c_diag_res_wrong : std_logic_vector(c_diag_res_w - 1 downto 0) := '0' & TO_UVEC(2**g_seq_dat_w - 1, c_diag_res_w - 1);
+ constant c_diag_res_wrong : std_logic_vector(c_diag_res_w - 1 downto 0) := '0' & TO_UVEC(2 ** g_seq_dat_w - 1, c_diag_res_w - 1);
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -83,7 +83,7 @@ begin
clk <= not clk or tb_end after c_period / 2;
stimuli: process
- -- run 100 us
+ -- run 100 us
begin
tx_diag_en <= '0';
rx_diag_en <= '0';
@@ -254,39 +254,39 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_cnt_incr => g_tx_cnt_incr,
- g_dat_w => g_seq_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => tx_diag_en,
- diag_sel => tx_diag_sel,
- diag_mod => tx_diag_mod,
- diag_req => tx_diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_cnt_incr => g_tx_cnt_incr,
+ g_dat_w => g_seq_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => tx_diag_en,
+ diag_sel => tx_diag_sel,
+ diag_mod => tx_diag_mod,
+ diag_req => tx_diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
u_diag_rx_seq : entity work.diag_rx_seq
- generic map (
- g_use_steps => g_rx_use_steps,
- g_nof_steps => c_rx_nof_steps,
- g_dat_w => g_seq_dat_w,
- g_diag_res_w => c_diag_res_w
- )
- port map (
- clk => clk,
- rst => rst,
- in_dat => seq_dat,
- in_val => seq_val,
- diag_en => rx_diag_en,
- diag_sel => rx_diag_sel,
- diag_steps_arr => rx_diag_steps_arr,
- diag_res => diag_res,
- diag_res_val => diag_res_val
- );
+ generic map (
+ g_use_steps => g_rx_use_steps,
+ g_nof_steps => c_rx_nof_steps,
+ g_dat_w => g_seq_dat_w,
+ g_diag_res_w => c_diag_res_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ in_dat => seq_dat,
+ in_val => seq_val,
+ diag_en => rx_diag_en,
+ diag_sel => rx_diag_sel,
+ diag_steps_arr => rx_diag_steps_arr,
+ diag_res => diag_res,
+ diag_res_val => diag_res_val
+ );
p_report : process (clk)
begin
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index d526a763f07a372d583673d579eb1e007570c098..945144ec22c20cd7e48fa24a8a476a71548cf44a 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_frm is
end tb_diag_tx_frm;
@@ -58,7 +58,7 @@ begin
clk <= not clk after c_period / 2;
stimuli: process
- -- run 100 us
+ -- run 100 us
begin
diag_sel <= c_sel;
diag_init <= TO_UVEC(c_init, c_dat_w);
@@ -153,30 +153,30 @@ begin
end process;
u_diag_tx_frm : entity work.diag_tx_frm
- generic map (
- g_sel => c_sel,
- g_init => c_init,
- g_frame_len => c_frame_len,
- g_dat_w => c_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- -- Static control input (connect via MM or leave open to use default)
- diag_sel => diag_sel,
- diag_frame_len => diag_frame_len,
- -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
- diag_ready => diag_ready,
- diag_init => diag_init,
- diag_sop => diag_sop,
- -- ST output
- out_ready => seq_req,
- out_dat => seq_dat,
- out_val => seq_val,
- out_sop => seq_sop,
- out_eop => seq_eop
- );
+ generic map (
+ g_sel => c_sel,
+ g_init => c_init,
+ g_frame_len => c_frame_len,
+ g_dat_w => c_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ -- Static control input (connect via MM or leave open to use default)
+ diag_sel => diag_sel,
+ diag_frame_len => diag_frame_len,
+ -- Dynamic control input (connect via MM or via ST input or leave open to use defaults)
+ diag_ready => diag_ready,
+ diag_init => diag_init,
+ diag_sop => diag_sop,
+ -- ST output
+ out_ready => seq_req,
+ out_dat => seq_dat,
+ out_val => seq_val,
+ out_sop => seq_sop,
+ out_eop => seq_eop
+ );
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index a172bb172d22a2ec0f08150157428394181ee8a2..f0328027788eefd7f7f56b114b0388f2cff03c71 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -26,9 +26,9 @@
-- > run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity tb_diag_tx_seq is
end tb_diag_tx_seq;
@@ -104,16 +104,16 @@ begin
end process;
u_diag_tx_seq : entity work.diag_tx_seq
- generic map (
- g_dat_w => c_dat_w
- )
- port map (
- clk => clk,
- rst => rst,
- diag_en => diag_en,
- diag_sel => diag_sel,
- diag_req => diag_req,
- out_dat => seq_dat,
- out_val => seq_val
- );
+ generic map (
+ g_dat_w => c_dat_w
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ diag_en => diag_en,
+ diag_sel => diag_sel,
+ diag_req => diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index db0f7c42fe152b2ed7565cf2c64ee70674aa00b7..efb389b3f44911b3b7dbca20e924a1012c765f5e 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -21,12 +21,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.diag_pkg.all;
-- Usage:
-- > do wave_diag_wg_wideband.do
@@ -45,57 +45,58 @@ entity tb_diag_wg is
end tb_diag_wg;
architecture tb of tb_diag_wg is
- constant c_clk_freq : natural := 200 * 10**6; -- Hz
- constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
+ constant c_clk_freq : natural := 200 * 10 ** 6; -- Hz
+ constant c_clk_period : time := (10 ** 9 / c_clk_freq) * 1 ns;
-- Default settings
- constant c_buf : t_c_mem := (latency => 1,
- adr_w => g_buf_adr_w,
- dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
- nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
- init_sl => '0');
- constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
- sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
-
- constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
- constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
-
- constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
- constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
- constant c_ampl_norm : real := sel_a_b(g_wg_dat_w < g_buf_dat_w, real(c_wg_full_scale) / real(c_wg_full_scale+1), 1.0);
- --CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
- --CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
- --CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
-
- constant c_freq_unit : real := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
- constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
- constant c_phase_unit : real := c_diag_wg_phase_unit; -- ^= 1 degree
-
- signal tb_end : std_logic;
- signal rst : std_logic;
- signal clk : std_logic := '1';
- signal restart : std_logic;
-
- signal buf_rddat : std_logic_vector(c_buf.dat_w - 1 downto 0);
- signal buf_rdval : std_logic;
- signal buf_addr : std_logic_vector(c_buf.adr_w - 1 downto 0);
- signal buf_rden : std_logic;
-
- signal wg_ctrl : t_diag_wg;
-
- signal wg_mode : natural;
- signal wg_freq : natural;
- signal wg_ampl : natural;
- signal wg_nof_samples : natural;
- signal wg_phase : natural;
-
- signal wg_ovr : std_logic;
- signal wg_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
- signal wg_val : std_logic;
- signal wg_sync : std_logic;
+ constant c_buf : t_c_mem := (
+ latency => 1,
+ adr_w => g_buf_adr_w,
+ dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
+ nof_dat => 2**g_buf_adr_w, -- = 2**adr_w
+ init_sl => '0');
+ constant c_buf_file : string := sel_a_b(c_buf.adr_w = 11 and c_buf.dat_w = 18, "data/diag_sin_2048x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
+ sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
+
+ constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
+ constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+
+ constant c_buf_full_scale : natural := 2 ** (g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ constant c_wg_full_scale : natural := 2 ** (g_wg_dat_w - 1) - 1;
+ constant c_ampl_norm : real := sel_a_b(g_wg_dat_w < g_buf_dat_w, real(c_wg_full_scale) / real(c_wg_full_scale+1), 1.0);
+ --CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
+ --CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
+ --CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
+
+ constant c_freq_unit : real := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
+ constant c_ampl_unit : real := c_diag_wg_ampl_unit * c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
+ constant c_phase_unit : real := c_diag_wg_phase_unit; -- ^= 1 degree
+
+ signal tb_end : std_logic;
+ signal rst : std_logic;
+ signal clk : std_logic := '1';
+ signal restart : std_logic;
+
+ signal buf_rddat : std_logic_vector(c_buf.dat_w - 1 downto 0);
+ signal buf_rdval : std_logic;
+ signal buf_addr : std_logic_vector(c_buf.adr_w - 1 downto 0);
+ signal buf_rden : std_logic;
+
+ signal wg_ctrl : t_diag_wg;
+
+ signal wg_mode : natural;
+ signal wg_freq : natural;
+ signal wg_ampl : natural;
+ signal wg_nof_samples : natural;
+ signal wg_phase : natural;
+
+ signal wg_ovr : std_logic;
+ signal wg_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
+ signal wg_val : std_logic;
+ signal wg_sync : std_logic;
begin
rst <= '1', '0' after c_clk_period / 10;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -118,13 +119,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -134,12 +135,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
wait for c_clk_period * 200;
@@ -203,53 +204,53 @@ begin
-- Waveform buffer
u_buf : entity common_lib.common_ram_crw_crw
- generic map (
- g_ram => c_buf,
- g_init_file => c_buf_file
- )
- port map (
- rst_a => '0',
- rst_b => '0',
- clk_a => clk,
- clk_b => clk,
- wr_en_a => '0',
- wr_en_b => '0',
- wr_dat_a => (others => '0'),
- wr_dat_b => (others => '0'),
- adr_a => (others => '0'),
- adr_b => buf_addr,
- rd_en_a => '0',
- rd_en_b => buf_rden,
- rd_dat_a => OPEN,
- rd_dat_b => buf_rddat,
- rd_val_a => OPEN,
- rd_val_b => buf_rdval
- );
+ generic map (
+ g_ram => c_buf,
+ g_init_file => c_buf_file
+ )
+ port map (
+ rst_a => '0',
+ rst_b => '0',
+ clk_a => clk,
+ clk_b => clk,
+ wr_en_a => '0',
+ wr_en_b => '0',
+ wr_dat_a => (others => '0'),
+ wr_dat_b => (others => '0'),
+ adr_a => (others => '0'),
+ adr_b => buf_addr,
+ rd_en_a => '0',
+ rd_en_b => buf_rden,
+ rd_dat_a => OPEN,
+ rd_dat_b => buf_rddat,
+ rd_val_a => OPEN,
+ rd_val_b => buf_rdval
+ );
-- Waveform generator
u_wg : entity work.diag_wg
- generic map (
- g_buf_dat_w => c_buf.dat_w,
- g_buf_addr_w => c_buf.adr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- restart => restart,
-
- buf_rddat => buf_rddat,
- buf_rdval => buf_rdval,
- buf_addr => buf_addr,
- buf_rden => buf_rden,
-
- ctrl => wg_ctrl,
-
- out_ovr => wg_ovr,
- out_dat => wg_dat,
- out_val => wg_val,
- out_sync => wg_sync
- );
+ generic map (
+ g_buf_dat_w => c_buf.dat_w,
+ g_buf_addr_w => c_buf.adr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ restart => restart,
+
+ buf_rddat => buf_rddat,
+ buf_rdval => buf_rdval,
+ buf_addr => buf_addr,
+ buf_rden => buf_rden,
+
+ ctrl => wg_ctrl,
+
+ out_ovr => wg_ovr,
+ out_dat => wg_dat,
+ out_val => wg_val,
+ out_sync => wg_sync
+ );
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 8521629f7d0dbcaf8913ce9dbdb4c9504dd19d68..c3a8931f0df5b74e786c1e47d103c0adb7978455 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -29,17 +29,17 @@
-- . Observe state in diag_wg(0).
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use work.diag_pkg.all;
entity tb_diag_wg_wideband is
generic (
-- Wideband parameters
g_wideband_factor : natural := 4; -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
- -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
+ -- Take care that the g_wideband_factor and c_clk_freq match the simulation time resolution of integer 1 ps
-- Basic WG parameters, see diag_wg.vhd for their meaning
g_buf_addr_w : natural := 10;
g_buf_dat_w : natural := 8;
@@ -49,17 +49,17 @@ end tb_diag_wg_wideband;
architecture tb of tb_diag_wg_wideband is
constant c_clk_freq : natural := 200; -- MHz
- constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps;
+ constant c_clk_period : time := (10 ** 6 / c_clk_freq) * 1 ps;
-- Default WG settings
- constant c_buf_nof_dat : natural := 2**g_buf_addr_w;
+ constant c_buf_nof_dat : natural := 2 ** g_buf_addr_w;
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
- -- . use gain 2**0 = 1 to have fulle scale without clipping
- -- . use gain 2**g_calc_gain_w > 1 to cause clipping
+ -- . use gain 2**0 = 1 to have fulle scale without clipping
+ -- . use gain 2**g_calc_gain_w > 1 to cause clipping
- constant c_buf_full_scale : natural := 2**(g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
- constant c_wg_full_scale : natural := 2**(g_wg_dat_w - 1) - 1;
+ constant c_buf_full_scale : natural := 2 ** (g_buf_dat_w - 1) - 1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
+ constant c_wg_full_scale : natural := 2 ** (g_wg_dat_w - 1) - 1;
constant c_ampl_norm : real := sel_a_b(g_wg_dat_w < g_buf_dat_w, real(c_wg_full_scale) / real(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
@@ -70,7 +70,7 @@ architecture tb of tb_diag_wg_wideband is
constant c_phase_unit : real := c_diag_wg_phase_unit; -- ^= 1 degree
-- Wideband WG settings
- constant c_sample_period : time := (10**6 / (c_clk_freq * g_wideband_factor)) * 1 ps;
+ constant c_sample_period : time := (10 ** 6 / (c_clk_freq * g_wideband_factor)) * 1 ps;
type t_buf_dat_arr is array (natural range <>) of std_logic_vector(g_buf_dat_w - 1 downto 0);
@@ -130,13 +130,13 @@ begin
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
--- wg_freq <= INTEGER(0.5 * c_freq_unit);
--- wg_phase <= INTEGER(90.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(0.5 * c_freq_unit);
+ -- wg_phase <= INTEGER(90.0 * c_phase_unit);
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
-- this also applies to 2.0, 3.0, 4.0 etc
--- wg_freq <= INTEGER(1.0 * c_freq_unit);
--- wg_phase <= INTEGER(45.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(45.0 * c_phase_unit);
-- Sinus Fs/16
wg_freq <= integer(0.0625 * c_freq_unit);
@@ -146,12 +146,12 @@ begin
wg_phase <= integer(0.0 * c_phase_unit);
-- Sinus Fs/17
--- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
--- wg_phase <= INTEGER(0.0 * c_phase_unit);
+ -- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
+ -- wg_phase <= INTEGER(0.0 * c_phase_unit);
wg_ampl <= integer(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
--- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
--- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
+ -- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
+ -- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
wait until rising_edge(clk); -- align to rising edge
cur_ctrl <= wg_ctrl;
@@ -261,41 +261,41 @@ begin
end process;
u_wideband_wg : entity work.diag_wg_wideband
- generic map (
- -- Wideband parameters
- g_wideband_factor => g_wideband_factor,
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => g_buf_dat_w,
- g_buf_addr_w => g_buf_addr_w,
- g_calc_support => true,
- g_calc_gain_w => c_wg_gain_w,
- g_calc_dat_w => g_wg_dat_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => '0',
- mm_clk => '0',
-
- mm_wrdata => (others => '0'),
- mm_address => (others => '0'),
- mm_wr => '0',
- mm_rd => '0',
- mm_rdval => OPEN,
- mm_rddata => OPEN,
-
- -- Streaming clock domain
- st_rst => rst,
- st_clk => clk,
- st_restart => restart,
-
- st_ctrl => wg_ctrl,
- st_mon_ctrl => mon_ctrl,
-
- out_ovr => out_ovr,
- out_dat => out_dat,
- out_val => out_val,
- out_sync => out_sync
- );
+ generic map (
+ -- Wideband parameters
+ g_wideband_factor => g_wideband_factor,
+ -- Basic WG parameters, see diag_wg.vhd for their meaning
+ g_buf_dat_w => g_buf_dat_w,
+ g_buf_addr_w => g_buf_addr_w,
+ g_calc_support => true,
+ g_calc_gain_w => c_wg_gain_w,
+ g_calc_dat_w => g_wg_dat_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => '0',
+ mm_clk => '0',
+
+ mm_wrdata => (others => '0'),
+ mm_address => (others => '0'),
+ mm_wr => '0',
+ mm_rd => '0',
+ mm_rdval => OPEN,
+ mm_rddata => OPEN,
+
+ -- Streaming clock domain
+ st_rst => rst,
+ st_clk => clk,
+ st_restart => restart,
+
+ st_ctrl => wg_ctrl,
+ st_mon_ctrl => mon_ctrl,
+
+ out_ovr => out_ovr,
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sync => out_sync
+ );
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : for I in 0 to g_wideband_factor - 1 generate
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index f18f50f775d9317d6b96af634b670d2b0abf2c81..5f1697b1f05f4a1a4c62aad86652e3d3579e291f 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -27,17 +27,17 @@
-- Observe tb_state and check the out_sosi_0 fields if data is OK.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use std.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
entity tb_mms_diag_block_gen is
generic (
@@ -212,24 +212,24 @@ begin
-- User input modelled by another BG
-------------------------------------------------
u_user : entity work.mms_diag_block_gen
- generic map (
- g_nof_streams => g_nof_streams,
- g_buf_dat_w => c_buf_dat_w,
- g_buf_addr_w => c_buf_addr_w,
- g_file_name_prefix => c_file_name_prefix,
- g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
- )
- port map (
- -- System
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- en_sync => '0',
- -- ST interface
- out_siso_arr => usr_src_in_arr,
- out_sosi_arr => usr_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_buf_dat_w => c_buf_dat_w,
+ g_buf_addr_w => c_buf_addr_w,
+ g_file_name_prefix => c_file_name_prefix,
+ g_diag_block_gen_rst => c_diag_block_gen_enabled -- user BG is default enabled
+ )
+ port map (
+ -- System
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ en_sync => '0',
+ -- ST interface
+ out_siso_arr => usr_src_in_arr,
+ out_sosi_arr => usr_src_out_arr
+ );
-- Use sufficiently large FIFO to provide siso.ready flow control to the user input
no_user_fifo : if c_use_user_fifo = false generate
@@ -238,67 +238,68 @@ begin
end generate;
gen_user_fifo : if c_use_user_fifo = true generate
+
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_user_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_buf_dat_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true,
- g_use_complex => false,
- g_fifo_size => c_usr_fifo_size,
- g_fifo_af_margin => 4,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => OPEN,
- usedw => OPEN,
- rd_emp => OPEN,
- -- ST sink
- snk_out => usr_src_in_arr(I),
- snk_in => usr_src_out_arr(I),
- -- ST source
- src_in => usr_fifo_src_in_arr(I),
- src_out => usr_fifo_src_out_arr(I)
+ generic map (
+ g_data_w => c_buf_dat_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true,
+ g_use_complex => false,
+ g_fifo_size => c_usr_fifo_size,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => OPEN,
+ usedw => OPEN,
+ rd_emp => OPEN,
+ -- ST sink
+ snk_out => usr_src_in_arr(I),
+ snk_in => usr_src_out_arr(I),
+ -- ST source
+ src_in => usr_fifo_src_in_arr(I),
+ src_out => usr_fifo_src_out_arr(I)
);
- end generate;
- end generate;
+end generate;
+end generate;
- ------------------------------------------------------------------------------
- -- STREAM CONTROL
- ------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- STREAM CONTROL
+------------------------------------------------------------------------------
- random <= func_common_random(random) when rising_edge(clk);
+random <= func_common_random(random) when rising_edge(clk);
- out_siso_ready <= '1' when g_flow_control_verify = e_active else
+out_siso_ready <= '1' when g_flow_control_verify = e_active else
random(random'high) when g_flow_control_verify = e_random else
- '1';
-
- p_out_siso_arr : process(out_siso_ready, out_siso_xon)
- begin
- for I in 0 to g_nof_streams - 1 loop
- out_siso_arr(I).ready <= '1';
- out_siso_arr(I).xon <= out_siso_xon;
- end loop;
- if c_verify_usr_rflow = true then
- out_siso_arr(0).ready <= out_siso_ready; -- only verify flow control via stream 0
- end if;
- end process;
+'1';
- -------------------------------------------------
- -- Device under test
- -------------------------------------------------
- u_dut : entity work.mms_diag_block_gen
+p_out_siso_arr : process(out_siso_ready, out_siso_xon)
+begin
+ for I in 0 to g_nof_streams - 1 loop
+ out_siso_arr(I).ready <= '1';
+ out_siso_arr(I).xon <= out_siso_xon;
+ end loop;
+ if c_verify_usr_rflow = true then
+ out_siso_arr(0).ready <= out_siso_ready; -- only verify flow control via stream 0
+ end if;
+end process;
+
+-------------------------------------------------
+-- Device under test
+-------------------------------------------------
+u_dut : entity work.mms_diag_block_gen
generic map (
-- Generate configurations
g_use_usr_input => g_use_usr_input,
@@ -338,102 +339,103 @@ begin
out_sosi_arr => out_sosi_arr
);
- -------------------------------------------------
- -- Verification
- -------------------------------------------------
+-------------------------------------------------
+-- Verification
+-------------------------------------------------
- prev_tb_state <= tb_state when rising_edge(clk);
+prev_tb_state <= tb_state when rising_edge(clk);
- usr_src_out_0_data <= usr_src_out_arr(0).data(c_buf_dat_w - 1 downto 0);
+usr_src_out_0_data <= usr_src_out_arr(0).data(c_buf_dat_w - 1 downto 0);
- out_sosi_0 <= out_sosi_arr(0); -- use BG[0] as reference
- out_sosi_0_data <= out_sosi_0.data(c_buf_dat_w - 1 downto 0);
+out_sosi_0 <= out_sosi_arr(0); -- use BG[0] as reference
+out_sosi_0_data <= out_sosi_0.data(c_buf_dat_w - 1 downto 0);
- -- Verify : Equal data in all g_nof_streams
- verify_sosi_arr_en <= '1' when bg_en_dly = '1';
+-- Verify : Equal data in all g_nof_streams
+verify_sosi_arr_en <= '1' when bg_en_dly = '1';
- p_compare_out_sosi_arr : process(clk)
- begin
- if rising_edge(clk) then
- if verify_sosi_arr_en = '1' then
- for I in 0 to g_nof_streams - 1 loop
- -- All outputs have the same framing
- assert out_sosi_0.sync = out_sosi_arr(I).sync report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sync";
- assert out_sosi_0.bsn = out_sosi_arr(I).bsn report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).bsn";
- assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
- assert out_sosi_0.valid = out_sosi_arr(I).valid report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).valid";
- assert out_sosi_0.sop = out_sosi_arr(I).sop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sop";
- assert out_sosi_0.eop = out_sosi_arr(I).eop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).eop";
-
- if g_use_bg_buffer_ram = true then
- -- Only the re part differs per output given the BG buffer data from c_file_name_prefix = "data/bf_in_data"
- assert TO_UINT(out_sosi_0.re) = TO_UINT(out_sosi_arr(I).re) - I * 4 report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).re";
- else
- assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
- end if;
- end loop;
- end if;
+p_compare_out_sosi_arr : process(clk)
+begin
+ if rising_edge(clk) then
+ if verify_sosi_arr_en = '1' then
+ for I in 0 to g_nof_streams - 1 loop
+ -- All outputs have the same framing
+ assert out_sosi_0.sync = out_sosi_arr(I).sync report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sync";
+ assert out_sosi_0.bsn = out_sosi_arr(I).bsn report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).bsn";
+ assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
+ assert out_sosi_0.valid = out_sosi_arr(I).valid report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).valid";
+ assert out_sosi_0.sop = out_sosi_arr(I).sop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).sop";
+ assert out_sosi_0.eop = out_sosi_arr(I).eop report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).eop";
+
+ if g_use_bg_buffer_ram = true then
+ -- Only the re part differs per output given the BG buffer data from c_file_name_prefix = "data/bf_in_data"
+ assert TO_UINT(out_sosi_0.re) = TO_UINT(out_sosi_arr(I).re) - I * 4 report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).re";
+ else
+ assert out_sosi_0.im = out_sosi_arr(I).im report "tb_mms_diag_block_gen: Wrong out_sosi_arr(*).im";
+ end if;
+ end loop;
end if;
- end process;
+ end if;
+end process;
- -- Verify : BSN
- p_verify_bsn_en : process
- begin
- proc_common_wait_until_evt(clk, bg_en);
- verify_bsn_en <= '0';
- proc_common_wait_some_cycles(clk, 3 * c_period_size);
- verify_bsn_en <= '1';
- wait until rising_edge(clk);
- end process;
+-- Verify : BSN
+p_verify_bsn_en : process
+begin
+ proc_common_wait_until_evt(clk, bg_en);
+ verify_bsn_en <= '0';
+ proc_common_wait_some_cycles(clk, 3 * c_period_size);
+ verify_bsn_en <= '1';
+ wait until rising_edge(clk);
+end process;
- proc_dp_verify_data("BSN", c_bsn_max, c_bsn_gap, clk, verify_bsn_en, out_sosi_0.sop, out_sosi_0.bsn, prev_out_sosi_0.bsn); -- verify both BG and user
+proc_dp_verify_data("BSN", c_bsn_max, c_bsn_gap, clk, verify_bsn_en, out_sosi_0.sop, out_sosi_0.bsn, prev_out_sosi_0.bsn); -- verify both BG and user
- -- Verify : sync
- bg_en_dly <= bg_en'delayed(5 * clk_period);
- verify_sync_en <= verify_bsn_en and bg_en_dly when g_use_bg = true else '0'; -- only verify BG sync interval (ignore user sync interval)
+-- Verify : sync
+bg_en_dly <= bg_en'delayed(5 * clk_period);
+verify_sync_en <= verify_bsn_en and bg_en_dly when g_use_bg = true else '0'; -- only verify BG sync interval (ignore user sync interval)
- proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync_en, out_sosi_0.sync, out_sosi_0.sop, out_sosi_0.bsn);
+proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_sync_en, out_sosi_0.sync, out_sosi_0.sop, out_sosi_0.bsn);
- -- Verify : Tx counter data
- -- . g_use_tx_seq=TRUE
- -- . g_use_bg_buffer_ram=FALSE
- p_verify_data_en : process
- begin
- verify_data_en <= '0';
- if g_use_usr_input = true then
- proc_common_wait_until_high(clk, usr_fifo_src_out_arr(0).valid);
- end if;
- if g_use_bg = true then
- proc_common_wait_until_evt(clk, bg_en);
+-- Verify : Tx counter data
+-- . g_use_tx_seq=TRUE
+-- . g_use_bg_buffer_ram=FALSE
+p_verify_data_en : process
+begin
+ verify_data_en <= '0';
+ if g_use_usr_input = true then
+ proc_common_wait_until_high(clk, usr_fifo_src_out_arr(0).valid);
+ end if;
+ if g_use_bg = true then
+ proc_common_wait_until_evt(clk, bg_en);
+ end if;
+ proc_common_wait_some_cycles(clk, 2 * c_period_size);
+ verify_data_en <= '1';
+
+ while true loop
+ if tb_state = s_xoff then
+ verify_data_en <= '0';
+ elsif prev_tb_state = s_xoff then
+ proc_common_wait_some_cycles(clk, 2 * c_period_size);
+ verify_data_en <= '1';
end if;
- proc_common_wait_some_cycles(clk, 2 * c_period_size);
- verify_data_en <= '1';
-
- while true loop
- if tb_state = s_xoff then
- verify_data_en <= '0';
- elsif prev_tb_state = s_xoff then
- proc_common_wait_some_cycles(clk, 2 * c_period_size);
- verify_data_en <= '1';
- end if;
- wait until rising_edge(clk);
- end loop;
- end process;
+ wait until rising_edge(clk);
+ end loop;
+end process;
- verify_tx_seq_en <= '1' when verify_data_en = '1' and g_use_tx_seq = true else '0';
- verify_no_bg_buffer_ram_en <= '1' when verify_data_en = '1' and g_use_tx_seq = false and g_use_bg_buffer_ram = false else '0';
+verify_tx_seq_en <= '1' when verify_data_en = '1' and g_use_tx_seq = true else '0';
+verify_no_bg_buffer_ram_en <= '1' when verify_data_en = '1' and g_use_tx_seq = false and g_use_bg_buffer_ram = false else '0';
- proc_dp_verify_data("Tx sequence counter data", 0, 0, clk, verify_tx_seq_en, out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u0);
- proc_dp_verify_data("No BG buffer RAM counter data", c_block_size-1, 0, clk, verify_no_bg_buffer_ram_en, out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u1);
+proc_dp_verify_data("Tx sequence counter data", 0, 0, clk, verify_tx_seq_en, out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u0);
+proc_dp_verify_data("No BG buffer RAM counter data", c_block_size-1, 0, clk, verify_no_bg_buffer_ram_en, out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u1);
- -- Verify : User input bypass all
- p_compare_usr_bypass_all : process(clk)
- begin
- if g_use_usr_input = true and g_use_bg = false and g_use_tx_seq = false then
- if rising_edge(clk) then
- assert out_sosi_arr = usr_fifo_src_out_arr report "tb_mms_diag_block_gen: out_sosi_arr /= usr_src_out_arr";
- assert usr_fifo_src_in_arr = out_siso_arr report "tb_mms_diag_block_gen: usr_src_in_arr /= out_siso_arr";
- end if;
+-- Verify : User input bypass all
+p_compare_usr_bypass_all : process(clk)
+begin
+ if g_use_usr_input = true and g_use_bg = false and g_use_tx_seq = false then
+ if rising_edge(clk) then
+ assert out_sosi_arr = usr_fifo_src_out_arr report "tb_mms_diag_block_gen: out_sosi_arr /= usr_src_out_arr";
+ assert usr_fifo_src_in_arr = out_siso_arr report "tb_mms_diag_block_gen: usr_src_in_arr /= out_siso_arr";
end if;
- end process;
+ end if;
+end process;
+
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 57222de7e020adf7b3ca690ef9292a3d09157086..1d54cfd2ddb2430cf3f01d51b6064723325fd3f5 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -27,17 +27,17 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
-use work.diag_pkg.all;
-use work.tb_diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
+ use work.diag_pkg.all;
+ use work.tb_diag_pkg.all;
entity tb_mms_diag_seq is
generic (
@@ -102,7 +102,7 @@ begin
ready <= '1' when g_flow_control_verify = e_active else
random(random'high) when g_flow_control_verify = e_random else
- '1';
+ '1';
tx_src_in_arr <= func_dp_stream_arr_set(tx_src_in_arr, ready, "READY");
@@ -274,66 +274,67 @@ begin
for I in 1 to g_nof_streams - 1 loop
if v_snk_in /= rx_snk_in_arr(I) then
report "Wrong diag result: for g_mm_broadcast_tx=TRUE all streams should carry the same data." severity ERROR;
- exit;
+ exit;
+ end if;
+ end loop;
end if;
- end loop;
- end if;
- end process;
-
- u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
- generic map(
- g_mm_broadcast => g_mm_broadcast_tx,
- g_nof_streams => g_nof_streams,
- g_seq_dat_w => g_seq_dat_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_tx_mosi,
- reg_miso => reg_tx_miso,
-
- -- DP streaming interface
- tx_src_out_arr => tx_src_out_arr,
- tx_src_in_arr => tx_src_in_arr
- );
-
- u_mms_diag_rx_seq: entity WORK.mms_diag_rx_seq
- generic map(
- g_nof_streams => g_nof_streams,
- g_use_steps => g_use_steps,
- g_seq_dat_w => g_seq_dat_w,
- g_data_w => g_data_w
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM interface
- reg_mosi => reg_rx_mosi,
- reg_miso => reg_rx_miso,
-
- -- DP streaming interface
- rx_snk_in_arr => rx_snk_in_arr
- );
-
- p_connect : process(tx_src_out_arr, force_low_error, force_replicate_error)
- begin
- -- Default lopoback all streams
- rx_snk_in_arr <= tx_src_out_arr;
- -- Optionally apply errors on stream 0
- if force_low_error = '1' then
- rx_snk_in_arr(0).data(0) <= not tx_src_out_arr(0).data(0);
- end if;
- if force_replicate_error = '1' then
- rx_snk_in_arr(0).data(g_seq_dat_w) <= not tx_src_out_arr(0).data(g_seq_dat_w);
- end if;
- end process;
-end architecture str;
+ end process;
+
+ u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
+ generic map(
+ g_mm_broadcast => g_mm_broadcast_tx,
+ g_nof_streams => g_nof_streams,
+ g_seq_dat_w => g_seq_dat_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_tx_mosi,
+ reg_miso => reg_tx_miso,
+
+ -- DP streaming interface
+ tx_src_out_arr => tx_src_out_arr,
+ tx_src_in_arr => tx_src_in_arr
+ );
+
+ u_mms_diag_rx_seq: entity WORK.mms_diag_rx_seq
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_use_steps => g_use_steps,
+ g_seq_dat_w => g_seq_dat_w,
+ g_data_w => g_data_w
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM interface
+ reg_mosi => reg_rx_mosi,
+ reg_miso => reg_rx_miso,
+
+ -- DP streaming interface
+ rx_snk_in_arr => rx_snk_in_arr
+ );
+
+ p_connect : process(tx_src_out_arr, force_low_error, force_replicate_error)
+ begin
+ -- Default lopoback all streams
+ rx_snk_in_arr <= tx_src_out_arr;
+ -- Optionally apply errors on stream 0
+ if force_low_error = '1' then
+ rx_snk_in_arr(0).data(0) <= not tx_src_out_arr(0).data(0);
+ end if;
+ if force_replicate_error = '1' then
+ rx_snk_in_arr(0).data(g_seq_dat_w) <= not tx_src_out_arr(0).data(g_seq_dat_w);
+ end if;
+ end process;
+
+ end architecture str;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index 6417e9d67f26ab6f9751be29c46d4892b68e9377..529803a62c820083156d463f92e8145d158554d8 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -29,8 +29,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_block_gen is
end tb_tb_diag_block_gen;
@@ -47,7 +47,7 @@ begin
-- g_buf_adr_w : NATURAL := 7; -- Waveform buffer address width (requires corresponding c_buf_file)
-- g_buf_dat_w : NATURAL := 32 -- Waveform buffer stored data width (requires corresponding c_buf_file)
-- g_try_phasor : BOOLEAN := FALSE -- use TRUE to see BG phasor in wave window with out_sosi.re/im in radix
- -- decimal and analogue format, no self test
+ -- decimal and analogue format, no self test
u_bg : entity work.tb_diag_block_gen generic map (e_active, 96, 10, 32, 7, 32, false);
u_bg_ready : entity work.tb_diag_block_gen generic map (e_random, 96, 10, 32, 7, 32, false);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index 09ecb0650a2a86b472f7f15fc096efcd0147a150..b97341a951e6f6adbaab623f464b71ec2424a717 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -20,8 +20,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_rx_seq is
end tb_tb_diag_rx_seq;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
index 812024f273884f4a11e9362a4315ccb056723c59..48ccad2ed51398f4a9628fc6ebf70489e7500255 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
@@ -28,8 +28,8 @@
-- > run -all
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_block_gen is
end tb_tb_mms_diag_block_gen;
@@ -39,15 +39,15 @@ architecture tb of tb_tb_mms_diag_block_gen is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
--- g_use_usr_input : BOOLEAN := TRUE;
--- g_use_bg : BOOLEAN := TRUE;
--- g_use_tx_seq : BOOLEAN := FALSE;
--- g_use_bg_buffer_ram : BOOLEAN := TRUE;
--- g_usr_bypass_xonoff : BOOLEAN := FALSE;
--- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
--- g_nof_repeat : NATURAL := 2;
--- g_nof_streams : NATURAL := 16;
--- g_gap_size : NATURAL := 160
+ -- g_use_usr_input : BOOLEAN := TRUE;
+ -- g_use_bg : BOOLEAN := TRUE;
+ -- g_use_tx_seq : BOOLEAN := FALSE;
+ -- g_use_bg_buffer_ram : BOOLEAN := TRUE;
+ -- g_usr_bypass_xonoff : BOOLEAN := FALSE;
+ -- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
+ -- g_nof_repeat : NATURAL := 2;
+ -- g_nof_streams : NATURAL := 16;
+ -- g_gap_size : NATURAL := 160
u_bg_one_stream : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 1, 0);
u_bg_gap_0 : entity work.tb_mms_diag_block_gen generic map (false, true, false, true, false, e_active, 1, 3, 0);
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
index 416cb26dec25e7b533578aa08175cf62ed7db77b..9324000d7f54942f78187931b8ae6e5065986703 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, dp_lib;
-use IEEE.std_logic_1164.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_seq is
end tb_tb_mms_diag_seq;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 2fceec4f1a5a59d0e6a04d0a1d485ec702535944..2ff909b9baa506e420ee875f887dca9c5b781e45 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -32,11 +32,11 @@
-- All control inputs and status outputs apply to an individual stream.
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity diagnostics is
generic (
@@ -46,7 +46,7 @@ entity diagnostics is
g_src_latency : natural := 1;
g_snk_latency : natural := 1;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
rst : in std_logic := '0';
clk : in std_logic := '0';
@@ -120,6 +120,7 @@ begin
end generate;
gen_nof_streams : for i in 0 to g_nof_streams - 1 generate
+
gen_one_clk : if g_separate_clk = false generate
tx_clk(i) <= clk;
tx_rst(i) <= rst;
@@ -132,56 +133,56 @@ begin
snk_diag_res_val(i) <= andv(substream_snk_diag_res_val(i)); -- If all substream diag results are valid, the stream's diag_res is valid.
u_tx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_src_latency
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_src_latency
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- snk_out => tx_dpmon_siso_arr(i),
- snk_in => tx_dpmon_sosi_arr(i),
+ snk_out => tx_dpmon_siso_arr(i),
+ snk_in => tx_dpmon_sosi_arr(i),
- src_out => src_out_arr(i),
- src_in => src_in_arr(i)
- );
+ src_out => src_out_arr(i),
+ src_in => src_in_arr(i)
+ );
u_rx_latency_adpt: entity dp_lib.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
- src_out => rx_dpmon_sosi_arr(i),
- src_in => rx_dpmon_siso_arr(i)
- );
+ src_out => rx_dpmon_sosi_arr(i),
+ src_in => rx_dpmon_siso_arr(i)
+ );
tx_diag_req(i) <= tx_siso_arr(i).ready and tx_siso_arr(i).xon;
gen_bg : if g_block_len > 0 generate
u_dp_block_gen: entity dp_lib.dp_block_gen
- generic map (
- g_nof_data => g_block_len,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
+ generic map (
+ g_nof_data => g_block_len,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
- src_in => tx_bg_siso_arr(i),
- src_out => tx_bg_sosi_arr(i),
+ src_in => tx_bg_siso_arr(i),
+ src_out => tx_bg_sosi_arr(i),
- en => src_diag_en(i)
- );
+ en => src_diag_en(i)
+ );
tx_sosi_arr(i).sop <= tx_bg_sosi_arr(i).sop;
tx_sosi_arr(i).eop <= tx_bg_sosi_arr(i).eop;
@@ -194,41 +195,41 @@ begin
gen_nof_substreams : for j in c_nof_substreams - 1 downto 0 generate
u_diag_tx_seq: entity diag_lib.diag_tx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w
)
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- clken => tb_clken(i),
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ clken => tb_clken(i),
- diag_en => src_diag_en(i),
- diag_sel => src_diag_md(i),
- diag_init => (others => '0'),
+ diag_en => src_diag_en(i),
+ diag_sel => src_diag_md(i),
+ diag_init => (others => '0'),
- diag_req => tx_diag_req(i),
- out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
- out_val => tx_seq_out_val(i)(j)
- );
+ diag_req => tx_diag_req(i),
+ out_dat => tx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w ),
+ out_val => tx_seq_out_val(i)(j)
+ );
u_diag_rx_seq: entity diag_lib.diag_rx_seq
- generic map (
- g_dat_w => c_sub_stream_dat_w,
- g_diag_res_w => c_sub_stream_dat_w
+ generic map (
+ g_dat_w => c_sub_stream_dat_w,
+ g_diag_res_w => c_sub_stream_dat_w
)
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
- diag_en => snk_diag_en(i),
- diag_sel => snk_diag_md(i),
+ diag_en => snk_diag_en(i),
+ diag_sel => snk_diag_md(i),
- orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
- diag_res_val => substream_snk_diag_res_val(i)(j),
+ orv(diag_res) => substream_snk_diag_res(i)(j), -- vector-wise OR to create a one-bit diag_result per substream
+ diag_res_val => substream_snk_diag_res_val(i)(j),
- in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
- in_val => rx_sosi_arr(i).valid
- );
+ in_dat => rx_sosi_arr(i).data( (j + 1) * c_sub_stream_dat_w - 1 downto (j + 1) * c_sub_stream_dat_w - c_sub_stream_dat_w),
+ in_val => rx_sosi_arr(i).valid
+ );
end generate;
tx_sosi_arr(i).valid <= tx_seq_out_val(i)(0);
@@ -237,41 +238,41 @@ begin
rx_siso_arr(i).xon <= '1'; -- snk_diag_en(i);
u_tx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => tx_rst(i),
- clk => tx_clk(i),
- en => src_diag_en(i),
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => tx_rst(i),
+ clk => tx_clk(i),
+ en => src_diag_en(i),
- snk_out => tx_siso_arr(i),
- snk_in => tx_sosi_arr(i),
+ snk_out => tx_siso_arr(i),
+ snk_in => tx_sosi_arr(i),
- src_in => tx_dpmon_siso_arr(i),
- src_out => tx_dpmon_sosi_arr(i),
+ src_in => tx_dpmon_siso_arr(i),
+ src_out => tx_dpmon_sosi_arr(i),
- clr => src_val_cnt_clr(i),
- word_cnt => src_val_cnt(i)
- );
+ clr => src_val_cnt_clr(i),
+ word_cnt => src_val_cnt(i)
+ );
u_rx_dpmon : entity dp_lib.dp_mon
- generic map (
- g_latency => 1
- )
- port map (
- rst => rx_rst(i),
- clk => rx_clk(i),
- en => snk_diag_en(i),
-
- snk_out => rx_dpmon_siso_arr(i),
- snk_in => rx_dpmon_sosi_arr(i),
-
- src_in => rx_siso_arr(i),
- src_out => rx_sosi_arr(i),
-
- clr => snk_val_cnt_clr(i),
- word_cnt => snk_val_cnt(i)
- );
+ generic map (
+ g_latency => 1
+ )
+ port map (
+ rst => rx_rst(i),
+ clk => rx_clk(i),
+ en => snk_diag_en(i),
+
+ snk_out => rx_dpmon_siso_arr(i),
+ snk_in => rx_dpmon_sosi_arr(i),
+
+ src_in => rx_siso_arr(i),
+ src_out => rx_sosi_arr(i),
+
+ clr => snk_val_cnt_clr(i),
+ word_cnt => snk_val_cnt(i)
+ );
end generate;
end str;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index 6fd9e3ac98be7dc3c51517b8c11c03d38582c56d..eca42b85863a9f15def5d1849d5da09c022a041d 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use diag_lib.diag_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use diag_lib.diag_pkg.all;
entity diagnostics_reg is
generic (
g_nof_streams : natural;
g_separate_clk : boolean := false -- Use separate SRC and SNK clock domains
- );
+ );
port (
-- Clocks and reset
mm_rst : in std_logic; -- reset synchronous with mm_clk
@@ -60,38 +60,39 @@ entity diagnostics_reg is
st_snk_cnt_clr_evt : out std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_val : in std_logic_vector(g_nof_streams - 1 downto 0);
st_snk_diag_res : in std_logic_vector(g_nof_streams - 1 downto 0)
- );
+ );
end diagnostics_reg;
architecture rtl of diagnostics_reg is
constant c_nof_registers : natural := 40; -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_registers),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_registers,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_registers),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_registers,
+ init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_src_en : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_src_md : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_src_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
- signal mm_src_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
+ -- Registers in mm_clk domain
+ signal mm_src_en : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_src_md : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_src_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ signal mm_src_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_en : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_md : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
+ signal mm_snk_en : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_snk_md : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_snk_cnt : t_slv_32_arr(16 - 1 downto 0); -- g_nof_streams not used as we must support 16 (fixed number of regs)
- signal mm_snk_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_snk_cnt_clr_evt : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_diag_val : std_logic_vector(g_nof_streams - 1 downto 0);
- signal mm_snk_diag_res : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_snk_diag_val : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal mm_snk_diag_res : std_logic_vector(g_nof_streams - 1 downto 0);
- signal i_src_clk : std_logic_vector(g_nof_streams - 1 downto 0);
- signal i_src_rst : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal i_src_clk : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal i_src_rst : std_logic_vector(g_nof_streams - 1 downto 0);
- signal i_snk_clk : std_logic_vector(g_nof_streams - 1 downto 0);
- signal i_snk_rst : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal i_snk_clk : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal i_snk_rst : std_logic_vector(g_nof_streams - 1 downto 0);
begin
gen_sep_clk : if g_separate_clk = true generate
i_src_clk <= src_clk;
@@ -102,6 +103,7 @@ begin
end generate;
gen_one_clk : if g_separate_clk = false generate
+
gen_nof_streams : for i in 0 to g_nof_streams - 1 generate
i_src_clk(i) <= st_clk;
i_src_rst(i) <= st_rst;
@@ -140,7 +142,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_src_en <= sla_in.wrdata(g_nof_streams - 1 downto 0);
when 1 =>
@@ -156,7 +158,7 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
@@ -349,8 +351,8 @@ begin
-- Diag_res and related signals are polled after a certain nof words has been
-- received - data will be stable.
--- mm_snk_diag_val(i) <= st_snk_diag_val(i);
--- mm_snk_diag_res(i) <= st_snk_diag_res(i);
+ -- mm_snk_diag_val(i) <= st_snk_diag_val(i);
+ -- mm_snk_diag_res(i) <= st_snk_diag_res(i);
end generate;
u_cross_domain_snk_diag_val : entity common_lib.common_reg_cross_domain
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 3f93466da3deca5dc5c350011a771d610a795da3..02bbbb2646ed3db6566d9c138ec7ee53c3100564 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -21,20 +21,20 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_rx_logger is
generic (
g_technology : natural := c_tech_select_default;
g_dat_w : natural;
g_fifo_wr_depth : natural := 128 -- Only put powers of 2 here.
- );
+ );
port (
rx_rst : in std_logic;
rx_clk : in std_logic;
@@ -92,7 +92,7 @@ architecture str of mm_rx_logger is
signal trig_log_en : std_logic;
signal log_en : std_logic;
signal mm_ovr : std_logic := '0'; -- Normal operation (mm_over='0') : trigger enable/disable inputs control log_en
- -- Overridden operation (mm_over='1'): MM master controls log_en
+ -- Overridden operation (mm_over='1'): MM master controls log_en
signal mm_trig_on : std_logic;
signal mm_trig_one_shot : std_logic;
@@ -118,17 +118,17 @@ begin
-- FSM to enable/disable logging based on trigger inputs
u_mm_rx_logger_trig : entity work.mm_rx_logger_trig
- port map (
- clk => rx_clk,
- rst => rx_rst,
- trig_on => mm_trig_on,
- one_shot => mm_trig_one_shot,
- log_en_evt => trig_en_evt,
- log_dis_evt => trig_dis_evt,
- log_nof_words => mm_trig_nof_words,
- log_cnt => mm_trig_nof_logged_words,
- log_en => trig_log_en
- );
+ port map (
+ clk => rx_clk,
+ rst => rx_rst,
+ trig_on => mm_trig_on,
+ one_shot => mm_trig_one_shot,
+ log_en_evt => trig_en_evt,
+ log_dis_evt => trig_dis_evt,
+ log_nof_words => mm_trig_nof_words,
+ log_cnt => mm_trig_nof_logged_words,
+ log_en => trig_log_en
+ );
log_en <= trig_log_en or sla_log_en; -- Allow slave input to enable logging
mst_log_en <= log_en; -- Forward log_en signal to master output
@@ -140,41 +140,41 @@ begin
-- The FIFO's almost_full will de-assert it's snk ready signal. We'll use
-- that to flush the FIFO on the src side.
u_data_log_fifo : entity dp_lib.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_use_ctrl => false,
- g_fifo_size => g_fifo_wr_depth
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
-
- snk_out => data_log_fifo_siso,
- snk_in => data_log_fifo_sosi,
-
- src_in => data_flusher_siso,
- src_out => data_flusher_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_use_ctrl => false,
+ g_fifo_size => g_fifo_wr_depth
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+
+ snk_out => data_log_fifo_siso,
+ snk_in => data_log_fifo_sosi,
+
+ src_in => data_flusher_siso,
+ src_out => data_flusher_sosi
+ );
-- dp_flush to flush data log FIFO when almost full.
u_data_flush: entity dp_lib.dp_flush
- generic map (
- g_framed_xon => false,
- g_framed_xoff => false
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- -- ST sink
- snk_in => data_flusher_sosi,
- snk_out => data_flusher_siso,
- -- ST source
- src_in => ovr_data_dpmm_fifo_siso,
- src_out => data_dpmm_fifo_sosi,
- -- Enable flush
- flush_en => flush_en
- );
+ generic map (
+ g_framed_xon => false,
+ g_framed_xoff => false
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ -- ST sink
+ snk_in => data_flusher_sosi,
+ snk_out => data_flusher_siso,
+ -- ST source
+ src_in => ovr_data_dpmm_fifo_siso,
+ src_out => data_dpmm_fifo_sosi,
+ -- Enable flush
+ flush_en => flush_en
+ );
flush_en <= not data_log_fifo_siso.ready; -- We'll flush when the data log fifo is almost full.
@@ -185,56 +185,56 @@ begin
ovr_data_dpmm_fifo_siso.xon <= data_dpmm_fifo_siso.xon; -- leave xon as it is
u_data_dpmm_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_wr_data_w => g_dat_w,
- g_rd_data_w => c_word_w,
- g_use_ctrl => false,
- g_wr_fifo_size => c_dpmm_fifo_wr_depth
- )
- port map (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => mm_rst,
- rd_clk => mm_clk,
-
- snk_out => data_dpmm_fifo_siso,
- snk_in => data_dpmm_fifo_sosi,
-
- wr_usedw => OPEN,
- rd_usedw => data_dpmm_fifo_rd_usedw,
- rd_emp => OPEN,
-
- src_in => data_mm_siso,
- src_out => data_mm_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_wr_data_w => g_dat_w,
+ g_rd_data_w => c_word_w,
+ g_use_ctrl => false,
+ g_wr_fifo_size => c_dpmm_fifo_wr_depth
+ )
+ port map (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+
+ snk_out => data_dpmm_fifo_siso,
+ snk_in => data_dpmm_fifo_sosi,
+
+ wr_usedw => OPEN,
+ rd_usedw => data_dpmm_fifo_rd_usedw,
+ rd_emp => OPEN,
+
+ src_in => data_mm_siso,
+ src_out => data_mm_sosi
+ );
u_data_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => c_data_dpmm_fifo_rd_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
-
- snk_out => data_mm_siso,
- snk_in => data_mm_sosi,
- usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
-
- mm_rd => data_mm_rd,
- mm_rddata => data_mm_rd_data,
- mm_rdval => data_mm_rd_val,
- mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
+ generic map(
+ g_fifo_size => c_data_dpmm_fifo_rd_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+
+ snk_out => data_mm_siso,
+ snk_in => data_mm_sosi,
+ usedw => data_dpmm_fifo_rd_usedw, -- used words from the clock crossing FIFO (NOT the logging FIFO)
+
+ mm_rd => data_mm_rd,
+ mm_rddata => data_mm_rd_data,
+ mm_rdval => data_mm_rd_val,
+ mm_usedw => data_mm_rd_usedw -- used words resized to 32 bits
);
- -- data read output to mm bus
- data_miso.rddata(c_word_w - 1 downto 0) <= data_mm_rd_data;
- data_miso.rdval <= data_mm_rd_val;
- data_mm_rd <= data_mosi.rd;
+-- data read output to mm bus
+data_miso.rddata(c_word_w - 1 downto 0) <= data_mm_rd_data;
+data_miso.rdval <= data_mm_rd_val;
+data_mm_rd <= data_mosi.rd;
- -- ============== MM control ========================================================================
+-- ============== MM control ========================================================================
- u_ctrl_reg : entity work.mm_rx_logger_reg
+u_ctrl_reg : entity work.mm_rx_logger_reg
port map (
mm_rst => mm_rst,
mm_clk => mm_clk,
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index fb6107194a79b5345849866333b306241a0f3e83..e9a6a8205636e3a9951734e0e4b6a24b8085c0e3 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_rx_logger_reg is
port (
@@ -48,24 +48,25 @@ entity mm_rx_logger_reg is
-- MM registers
mm_data_usedw : in std_logic_vector(31 downto 0)
- );
+ );
end mm_rx_logger_reg;
architecture rtl of mm_rx_logger_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(8),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 8,
- init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_trig_on : std_logic;
- signal mm_trig_one_shot : std_logic;
- signal mm_trig_nof_words : std_logic_vector(c_word_w - 1 downto 0);
- signal mm_trig_nof_logged_words : std_logic_vector(c_word_w - 1 downto 0);
-
- signal mm_ovr : std_logic;
- signal mm_log_en_evt : std_logic;
- signal mm_log_dis_evt : std_logic;
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(8),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 8,
+ init_sl => '0');
+ -- Registers in mm_clk domain
+ signal mm_trig_on : std_logic;
+ signal mm_trig_one_shot : std_logic;
+ signal mm_trig_nof_words : std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_trig_nof_logged_words : std_logic_vector(c_word_w - 1 downto 0);
+
+ signal mm_ovr : std_logic;
+ signal mm_log_en_evt : std_logic;
+ signal mm_log_dis_evt : std_logic;
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -97,7 +98,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_trig_on <= sla_in.wrdata(0);
when 1 =>
@@ -114,17 +115,17 @@ begin
when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 3 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_trig_nof_logged_words;
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_data_usedw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -148,59 +149,59 @@ begin
------------------------------------------------------------------------------
u_spulse_log_en_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_en_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_en_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_en_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_en_evt
+ );
u_spulse_log_dis_evt : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_log_dis_evt,
- in_busy => OPEN,
- out_rst => rx_rst,
- out_clk => rx_clk,
- out_pulse => rx_log_dis_evt
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_log_dis_evt,
+ in_busy => OPEN,
+ out_rst => rx_rst,
+ out_clk => rx_clk,
+ out_pulse => rx_log_dis_evt
+ );
u_async_mm_ovr : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_ovr,
- dout => rx_mm_ovr
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_ovr,
+ dout => rx_mm_ovr
+ );
u_async_mm_trig_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_on,
- dout => rx_trig_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_on,
+ dout => rx_trig_on
+ );
u_async_mm_trig_one_shot : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => rx_rst,
- clk => rx_clk,
- din => mm_trig_one_shot,
- dout => rx_trig_one_shot
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => rx_rst,
+ clk => rx_clk,
+ din => mm_trig_one_shot,
+ dout => rx_trig_one_shot
+ );
rx_trig_nof_words <= mm_trig_nof_words;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index cfe4fe951f828fd7bdd7b8fe289fac2d394e31ea..386b3094982f7ad1a8cc1a4ebae1139ed67727e8 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -21,9 +21,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity mm_rx_logger_trig is
port (
@@ -36,7 +36,7 @@ entity mm_rx_logger_trig is
log_nof_words : in std_logic_vector(c_word_w - 1 downto 0); -- unlimited (as long as there's no dis_evt) when zero (log FIFO keeps flushing then)
log_cnt : out std_logic_vector(c_word_w - 1 downto 0);
log_en : out std_logic
- );
+ );
end mm_rx_logger_trig;
architecture str of mm_rx_logger_trig is
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 6f31fd34b9a9b09fcd37b8ace2fa311475040de6..f6bb319fde9ff37b542dfb955b0753cf9864ff49 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -21,19 +21,19 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mm_tx_framer is
generic(
g_technology : natural := c_tech_select_default;
g_dat_out_w : natural;
g_rd_fifo_depth : natural := 128
- );
+ );
port (
mm_clk : in std_logic;
mm_rst : in std_logic;
@@ -52,8 +52,8 @@ entity mm_tx_framer is
master_release : out std_logic; -- If used this instance will provide master release control for other instance(s)
slave_release : in std_logic := '0' -- If this instance is slave of another instance, the an MM write to the master's MM release will
- -- also release the frames in the slave(s)
- );
+ -- also release the frames in the slave(s)
+ );
end mm_tx_framer;
architecture str of mm_tx_framer is
@@ -72,23 +72,23 @@ begin
master_release <= release;
u_data_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map (
- g_fifo_size => c_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- -- ST soure connected to FIFO input
- src_out => mm_to_fifo_sosi,
- usedw => wr_usedw,
- -- Control for FIFO read access
- mm_wr => data_mosi.wr,
- mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
- mm_usedw => OPEN,
- mm_availw => mm_availw
+ generic map (
+ g_fifo_size => c_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ -- ST soure connected to FIFO input
+ src_out => mm_to_fifo_sosi,
+ usedw => wr_usedw,
+ -- Control for FIFO read access
+ mm_wr => data_mosi.wr,
+ mm_wrdata => data_mosi.wrdata(c_word_w - 1 downto 0),
+ mm_usedw => OPEN,
+ mm_availw => mm_availw
);
- u_mm_to_dp_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
+u_mm_to_dp_fifo : entity dp_lib.dp_fifo_dc_mixed_widths
generic map (
g_technology => g_technology,
g_wr_data_w => c_word_w,
@@ -113,10 +113,10 @@ begin
src_out => fifo_out_sosi
);
- data_out <= fifo_out_sosi.data(g_dat_out_w - 1 downto 0) when fifo_out_sosi.valid = '1' and (release = '1' or slave_release = '1') else data_out_default;
- fifo_siso.ready <= release or slave_release;
+data_out <= fifo_out_sosi.data(g_dat_out_w - 1 downto 0) when fifo_out_sosi.valid = '1' and (release = '1' or slave_release = '1') else data_out_default;
+fifo_siso.ready <= release or slave_release;
- u_reg : entity work.mm_tx_framer_reg
+u_reg : entity work.mm_tx_framer_reg
port map (
mm_rst => mm_rst,
mm_clk => mm_clk,
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 97ef6ed9f100d8c45d1336f8928e7f2762218ead..8093c9047c90a08e922574edf87680f654383b70 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mm_tx_framer_reg is
port (
@@ -42,17 +42,18 @@ entity mm_tx_framer_reg is
-- MM registers
mm_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end mm_tx_framer_reg;
architecture rtl of mm_tx_framer_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_release : std_logic;
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
+ -- Registers in mm_clk domain
+ signal mm_release : std_logic;
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -79,21 +80,21 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 1 =>
mm_release <= sla_in.wrdata(0);
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_availw;
- when others => null; -- unused MM addresses
+ when others => null; -- unused MM addresses
end case;
end if;
end if;
@@ -117,13 +118,13 @@ begin
------------------------------------------------------------------------------
u_async_release : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => tx_rst,
- clk => tx_clk,
- din => mm_release,
- dout => tx_release
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => tx_rst,
+ clk => tx_clk,
+ din => mm_release,
+ dout => tx_release
+ );
end rtl;
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index a1c02e233098a2c5af52e6a1ce68cf92b02410cc..7b03bab114a34dc2050e13c8bfb982a093e99020 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity mms_diagnostics is
generic (
@@ -85,72 +85,72 @@ begin
snk_en_out <= snk_diag_en;
u_diagnostics: entity work.diagnostics
- generic map (
- g_dat_w => g_data_w,
- g_block_len => g_block_len,
- g_nof_streams => g_nof_streams,
- g_src_latency => g_src_latency,
- g_snk_latency => g_snk_latency,
- g_separate_clk => g_separate_clk
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- snk_diag_en => snk_diag_en,
- snk_diag_md => snk_diag_md,
- snk_diag_res => snk_diag_res,
- snk_diag_res_val => snk_diag_res_val,
- snk_val_cnt => snk_val_cnt,
- snk_val_cnt_clr => snk_val_cnt_clr,
-
- src_out_arr => src_out_arr,
- src_in_arr => src_in_arr,
- src_diag_en => src_diag_en,
- src_diag_md => src_diag_md,
- src_val_cnt => src_val_cnt,
- src_val_cnt_clr => src_val_cnt_clr
- );
+ generic map (
+ g_dat_w => g_data_w,
+ g_block_len => g_block_len,
+ g_nof_streams => g_nof_streams,
+ g_src_latency => g_src_latency,
+ g_snk_latency => g_snk_latency,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ snk_diag_en => snk_diag_en,
+ snk_diag_md => snk_diag_md,
+ snk_diag_res => snk_diag_res,
+ snk_diag_res_val => snk_diag_res_val,
+ snk_val_cnt => snk_val_cnt,
+ snk_val_cnt_clr => snk_val_cnt_clr,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+ src_diag_en => src_diag_en,
+ src_diag_md => src_diag_md,
+ src_val_cnt => src_val_cnt,
+ src_val_cnt_clr => src_val_cnt_clr
+ );
u_diagnostics_reg: entity work.diagnostics_reg
- generic map(
- g_nof_streams => g_nof_streams,
- g_separate_clk => g_separate_clk
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- src_rst => src_rst,
- src_clk => src_clk,
-
- snk_rst => snk_rst,
- snk_clk => snk_clk,
-
- sla_in => mm_mosi,
- sla_out => mm_miso,
-
- st_src_en => src_diag_en,
- st_src_md => src_diag_md,
- st_src_cnt => src_val_cnt,
- st_src_cnt_clr_evt => src_val_cnt_clr,
-
- st_snk_en => snk_diag_en,
- st_snk_md => snk_diag_md,
- st_snk_cnt => snk_val_cnt,
- st_snk_cnt_clr_evt => snk_val_cnt_clr,
- st_snk_diag_val => snk_diag_res_val,
- st_snk_diag_res => snk_diag_res
- );
+ generic map(
+ g_nof_streams => g_nof_streams,
+ g_separate_clk => g_separate_clk
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ src_rst => src_rst,
+ src_clk => src_clk,
+
+ snk_rst => snk_rst,
+ snk_clk => snk_clk,
+
+ sla_in => mm_mosi,
+ sla_out => mm_miso,
+
+ st_src_en => src_diag_en,
+ st_src_md => src_diag_md,
+ st_src_cnt => src_val_cnt,
+ st_src_cnt_clr_evt => src_val_cnt_clr,
+
+ st_snk_en => snk_diag_en,
+ st_snk_md => snk_diag_md,
+ st_snk_cnt => snk_val_cnt,
+ st_snk_cnt_clr_evt => snk_val_cnt_clr,
+ st_snk_diag_val => snk_diag_res_val,
+ st_snk_diag_res => snk_diag_res
+ );
end str;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index 4df9f42fa1e970a993f3cb0115e8d9cde1271639..e2cd5669438fd0a5b33dbed6106076660b1d2b38 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -27,12 +27,12 @@
-- > run -a
library IEEE, common_lib, dp_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_unsigned.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_diagnostics is
end entity tb_diagnostics;
@@ -58,13 +58,14 @@ architecture str of tb_diagnostics is
signal src_diag_en : std_logic_vector(c_nof_streams - 1 downto 0);
signal src_val_cnt : t_slv_32_arr(c_nof_streams - 1 downto 0);
- begin
+begin
-- Run for 1us
rst <= '0' after 100 ns;
clk <= not clk or tb_end after clk_period / 2;
gen_tb_processes: for i in 0 to c_nof_streams - 1 generate
+
p_stimuli : process
begin
for rpt in 0 to 1 loop
@@ -97,14 +98,13 @@ architecture str of tb_diagnostics is
wait for 100 ns;
wait;
end process;
-
end generate;
u_dut: entity WORK.diagnostics
generic map (
g_dat_w => c_dat_w,
g_nof_streams => c_nof_streams
- )
+ )
port map (
rst => rst,
clk => clk,
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 796aeba35b4cfc5f86b12b1aa6ac3f6a783a4873..bf7309d9e70364df9d31f5cff9879b61b53a3d0b 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -20,43 +20,48 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use STD.textio.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use STD.textio.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
package tb_diagnostics_trnb_pkg is
type t_e_diagnostics_trnb_mode is (e_prbs, e_counter);
-- Global procedures
- procedure proc_diagnostics_trnb_tx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_rx_set_mode_prbs( signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi);
-
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi);
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_tx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_rx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi);
+
+ procedure proc_diagnostics_trnb_run_and_verify(
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi);
-- Private procedures
end tb_diagnostics_trnb_pkg;
@@ -66,14 +71,16 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Set all gx to default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, 0, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_prbs;
- procedure proc_diagnostics_trnb_rx_set_mode_prbs(signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_prbs(
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi); -- set sink mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_prbs;
@@ -83,16 +90,18 @@ package body tb_diagnostics_trnb_pkg is
-- default mode PRBS
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_tx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_tx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr( 1, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_tx_set_mode_counter;
- procedure proc_diagnostics_trnb_rx_set_mode_counter(constant c_nof_gx_mask : in natural;
- signal mm_clk : in std_logic;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_rx_set_mode_counter(
+ constant c_nof_gx_mask : in natural;
+ signal mm_clk : in std_logic;
+ signal mm_mosi : out t_mem_mosi) is
begin
proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_counter;
@@ -101,16 +110,17 @@ package body tb_diagnostics_trnb_pkg is
-- PROCEDURE: Run a diagnostic measurement and verify the result
------------------------------------------------------------------------------
- procedure proc_diagnostics_trnb_run_and_verify(constant c_chip_id : in natural;
- constant c_nof_gx : in natural;
- constant c_nof_gx_mask : in integer;
- constant c_link_delay : in real;
- constant c_diag_on_interval : in real;
- constant c_diag_off_interval : in real;
- constant c_mm_clk_1us : in real;
- signal mm_clk : in std_logic;
- signal mm_miso : in t_mem_miso;
- signal mm_mosi : out t_mem_mosi) is
+ procedure proc_diagnostics_trnb_run_and_verify(
+ constant c_chip_id : in natural;
+ constant c_nof_gx : in natural;
+ constant c_nof_gx_mask : in integer;
+ constant c_link_delay : in real;
+ constant c_diag_on_interval : in real;
+ constant c_diag_off_interval : in real;
+ constant c_mm_clk_1us : in real;
+ signal mm_clk : in std_logic;
+ signal mm_miso : in t_mem_miso;
+ signal mm_mosi : out t_mem_mosi) is
constant c_nof_gx_mask_slv : std_logic_vector(c_nof_gx - 1 downto 0) := TO_UVEC(c_nof_gx_mask, c_nof_gx);
variable v_diag_results_valid : std_logic_vector(c_nof_gx - 1 downto 0);
variable v_diag_results : std_logic_vector(c_nof_gx - 1 downto 0);
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 9500074a594f10eb0193d53b0478c7a074c12758..335dc90e3ed3f3b3b5c9f82de191ea1e4ecb88b0 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -20,14 +20,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use IEEE.math_real.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use IEEE.math_real.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_mm_tx_framer is
end tb_mm_tx_framer;
@@ -135,41 +135,41 @@ begin
-- simultaneously.
------------------------------------------------------------------------------
u_mm_tx_framer_mst: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 64
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
+ generic map(
+ g_dat_out_w => 64
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- ctrl_mosi => ctrl_mosi,
- ctrl_miso => ctrl_miso,
+ ctrl_mosi => ctrl_mosi,
+ ctrl_miso => ctrl_miso,
- data_mosi => mst_data_mosi,
- data_miso => mst_data_miso,
+ data_mosi => mst_data_mosi,
+ data_miso => mst_data_miso,
- data_out => mst_data_out,
- master_release => mst_release
- );
+ data_out => mst_data_out,
+ master_release => mst_release
+ );
u_mm_tx_framer_sla: entity work.mm_tx_framer
- generic map(
- g_dat_out_w => 32
- )
- port map(
- tx_rst => tx_rst,
- tx_clk => tx_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- data_mosi => sla_data_mosi,
- data_miso => sla_data_miso,
-
- data_out => sla_data_out,
- slave_release => mst_release
- );
+ generic map(
+ g_dat_out_w => 32
+ )
+ port map(
+ tx_rst => tx_rst,
+ tx_clk => tx_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ data_mosi => sla_data_mosi,
+ data_miso => sla_data_miso,
+
+ data_out => sla_data_out,
+ slave_release => mst_release
+ );
end tb;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 8e84c4b54cefa76aca3a7e8fbfb249f343f8a738..25b6ef1cacf5c537a3ca029fc8bde06546c8cac9 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -38,22 +38,22 @@
-- used to target hardware (--unb # --fn # --bn #)
library IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tech_tse_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use technology_lib.technology_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use mm_lib.mm_file_pkg.all;
-use mm_lib.mm_file_unb_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use tech_tse_lib.tb_tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use technology_lib.technology_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use mm_lib.mm_file_pkg.all;
+ use mm_lib.mm_file_unb_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use tech_tse_lib.tb_tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
entity mmm_unb1_dp_offload is
generic (
@@ -158,7 +158,7 @@ architecture str of mmm_unb1_dp_offload is
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
- constant c_sim_eth_control_rx_en : natural := 2**c_eth_mm_reg_control_bi.rx_en;
+ constant c_sim_eth_control_rx_en : natural := 2 ** c_eth_mm_reg_control_bi.rx_en;
signal sim_eth_mm_bus_switch : std_logic;
signal sim_eth_psc_access : std_logic;
@@ -185,41 +185,53 @@ begin
eth1g_ram_mosi <= c_mem_mosi_rst;
- u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ port map(mm_rst, i_mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ port map(mm_rst, i_mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ port map(mm_rst, i_mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_eth : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ port map(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_reg_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
- port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+ u_mm_file_reg_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
+ port map(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
- u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
- port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+ u_mm_file_ram_diag_bg : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
+ port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
- u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ port map(mm_rst, i_mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
- u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
- port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ port map(mm_rst, i_mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
- u_mm_file_reg_bsn_monitor : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
- port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
+ u_mm_file_reg_bsn_monitor : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
+ port map(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
- u_mm_file_ram_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+ u_mm_file_ram_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
- u_mm_file_reg_diag_data_buffer : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
- port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+ u_mm_file_reg_diag_data_buffer : mm_file
+ generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUF")
+ port map(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
@@ -243,10 +255,10 @@ begin
p_switch : process(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
begin
if sim_eth_mm_bus_switch = '1' then
- eth1g_reg_mosi <= sim_eth1g_reg_mosi;
- else
- eth1g_reg_mosi <= i_eth1g_reg_mosi;
- end if;
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ else
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ end if;
end process;
----------------------------------------------------------------------------
@@ -261,145 +273,144 @@ begin
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
u_sopc : entity work.sopc_unb1_dp_offload
- port map (
- clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => i_mm_clk, -- 125 MHz system clock
- tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
- dp_clk => i_dp_clk,
- cal_reconf_clk => OPEN,
-
- -- the_altpll_0
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
- areset_to_the_altpll_0 => xo_rst,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
-
- -- the_reg_unb_sens
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => OPEN,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_dp_offload_rx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
- );
+ port map (
+ clk_0 => xo_clk, -- 25 MHz from ETH_clk pin
+ reset_n => xo_rst_n,
+ mm_clk => i_mm_clk, -- 125 MHz system clock
+ tse_clk => i_tse_clk, -- PLL clk[2] = 125 MHz calibration clock for the TSE
+ dp_clk => i_dp_clk,
+ cal_reconf_clk => OPEN,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_tech_tse_byte_addr_w - 1 downto 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w - 1 downto 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_eth_reg_addr_w - 1 downto 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w - 1 downto 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_eth_ram_addr_w - 1 downto 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w - 1 downto 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w - 1 downto 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w - 1 downto 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_system_info: actually a avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w - 1 downto 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w - 1 downto 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_bg
+ coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_bg => OPEN,
+ coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_bg => OPEN,
+ coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_bg
+ coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_bg => OPEN,
+ coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_bg => OPEN,
+ coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_tx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_dp_offload_rx_hdr_dat
+ coe_address_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.address(c_reg_dp_offload_rx_hdr_dat_multi_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_read_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_dp_offload_rx_hdr_dat => OPEN,
+ coe_write_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_offload_rx_hdr_dat => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_bsn_monitor
+ coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_reg_rsp_bsn_monitor_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_bsn_monitor => OPEN,
+ coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
+ coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_bsn_monitor => OPEN,
+ coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
+ coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_ram_diag_data_buffer
+ coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
+ coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0),
+
+ -- the_reg_diag_data_buffer
+ coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w - 1 downto 0),
+ coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
+ coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w - 1 downto 0),
+ coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
+ coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
+ coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w - 1 downto 0)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 52877cb0357bc723d4edcafd150e1e950d0a9733..737dd71ef69e7616c6776639ad39d82f164017e2 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -27,19 +27,19 @@
-- instances via 1GbE (32b user interface)
library IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use unb1_board_lib.unb1_board_peripherals_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use tech_tse_lib.tech_tse_pkg.all;
-use eth_lib.eth_pkg.all;
-use common_lib.common_network_layers_pkg.all;
-use diag_lib.diag_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use unb1_board_lib.unb1_board_peripherals_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use tech_tse_lib.tech_tse_pkg.all;
+ use eth_lib.eth_pkg.all;
+ use common_lib.common_network_layers_pkg.all;
+ use diag_lib.diag_pkg.all;
+ use common_lib.common_field_pkg.all;
entity unb1_dp_offload is
generic (
@@ -52,7 +52,7 @@ entity unb1_dp_offload is
);
port (
-- GENERAL
--- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
+ -- CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
PPS : in std_logic;
WDI : out std_logic;
INTA : inout std_logic;
@@ -83,46 +83,48 @@ architecture str of unb1_dp_offload is
constant c_bg_block_size : natural := 900;
constant c_bg_gapsize : natural := 100;
constant c_bg_blocks_per_sync : natural := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable
- '0', -- enable_sync
- TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
- TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+ constant c_bg_ctrl : t_diag_block_gen := ( -- enable
+ '0',
+ '0', -- enable_sync
+ TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
+ TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC( c_bg_gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC( 0, c_diag_bg_bsn_init_w));
-- dp_offload_tx
constant c_nof_hdr_fields : natural := 4 + 12 + 4 + 9; -- Total header bits = 512
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_word_align" ), " ", 16, field_default(0) ),
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"002286080000") ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(128) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(108) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(0) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1101" & "111111111100" & "1111" & "001111111";
@@ -206,28 +208,28 @@ begin
-- TX: Block generator
-----------------------------------------------------------------------------
u_mms_diag_block_gen : entity diag_lib.mms_diag_block_gen
- generic map (
- g_nof_streams => c_nof_streams,
- g_buf_dat_w => c_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
- g_diag_block_gen_rst => c_bg_ctrl
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => block_gen_src_out_arr,
- out_siso_arr => block_gen_src_in_arr,
-
- reg_bg_ctrl_mosi => reg_diag_bg_mosi,
- reg_bg_ctrl_miso => reg_diag_bg_miso,
- ram_bg_data_mosi => ram_diag_bg_mosi,
- ram_bg_data_miso => ram_diag_bg_miso
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_buf_dat_w => c_data_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/counter_data_" & natural'image(c_data_w),
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => block_gen_src_out_arr,
+ out_siso_arr => block_gen_src_in_arr,
+
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso
+ );
---------------------------------------------------------------------------------------
-- Use a FIFO when the source has no flow control
@@ -235,56 +237,56 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_sc : for i in 0 to c_nof_streams - 1 generate
u_dp_fifo_sc : entity dp_lib.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_use_bsn => true,
- g_bsn_w => 64,
- g_use_sync => true,
- g_fifo_size => 100
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => block_gen_src_out_arr(i),
- snk_out => block_gen_src_in_arr(i),
-
- src_out => dp_offload_tx_snk_in_arr(i),
- src_in => dp_offload_tx_snk_out_arr(i)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_use_bsn => true,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_fifo_size => 100
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => block_gen_src_out_arr(i),
+ snk_out => block_gen_src_in_arr(i),
+
+ src_out => dp_offload_tx_snk_in_arr(i),
+ src_in => dp_offload_tx_snk_out_arr(i)
+ );
end generate;
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
u_dp_offload_tx : entity dp_lib.dp_offload_tx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_use_complex => false,
- g_nof_words_per_block => c_nof_words_per_block,
- g_nof_blocks_per_packet => c_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => dp_offload_tx_src_out_arr,
- src_in_arr => dp_offload_tx_src_in_arr,
-
- hdr_fields_in_arr => hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_use_complex => false,
+ g_nof_words_per_block => c_nof_words_per_block,
+ g_nof_blocks_per_packet => c_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
gen_hdr_in_fields : for i in 0 to c_nof_streams - 1 generate
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -300,30 +302,30 @@ begin
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
u_dp_offload_rx : entity dp_lib.dp_offload_rx
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_hdr_field_arr => c_hdr_field_arr,
- g_remove_crc => true,
- g_crc_nof_words => 1
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => true,
+ g_crc_nof_words => 1
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
);
gen_hdr_out_fields : for i in 0 to c_nof_streams - 1 generate
@@ -345,199 +347,199 @@ begin
end generate;
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
- generic map (
- g_nof_streams => c_nof_streams,
- g_cross_clock_domain => true,
- g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
- g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
- g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
- g_log_first_bsn => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => diag_data_buf_snk_out_arr,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_cross_clock_domain => true,
+ g_sync_timeout => 2 * c_bg_blocks_per_sync * (c_bg_block_size + c_bg_gapsize),
+ g_cnt_sop_w => ceil_log2(c_bg_blocks_per_sync + 1),
+ g_cnt_valid_w => ceil_log2(c_bg_blocks_per_sync * c_bg_block_size+1),
+ g_log_first_bsn => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => diag_data_buf_snk_out_arr,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
- generic map (
- g_nof_streams => c_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => 1024,
- g_buf_use_sync => true
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_data_buf_miso => ram_diag_data_buf_miso,
- reg_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_data_buf_miso => reg_diag_data_buf_miso,
-
- in_sync => diag_data_buf_snk_in_arr(0).sop,
- in_sosi_arr => diag_data_buf_snk_in_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_data_w => c_data_w,
+ g_buf_nof_data => 1024,
+ g_buf_use_sync => true
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+
+ in_sync => diag_data_buf_snk_in_arr(0).sop,
+ in_sosi_arr => diag_data_buf_snk_in_arr
+ );
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb1_board : entity unb1_board_lib.ctrl_unb1_board
- generic map (
- g_sim => g_sim,
- g_design_name => c_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
- g_udp_offload => true,
- g_udp_offload_nof_streams => c_nof_streams,
- g_dp_clk_use_pll => false
- )
- port map (
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => OPEN,
- dp_pps => OPEN,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
- udp_tx_siso_arr => dp_offload_tx_src_in_arr,
- udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
- udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- UniBoard FPGA pins
- CLK => '0',
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- sens_sc => sens_sc,
- sens_sd => sens_sd,
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
+ generic map (
+ g_sim => g_sim,
+ g_design_name => c_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_udp_offload => true,
+ g_udp_offload_nof_streams => c_nof_streams,
+ g_dp_clk_use_pll => false
+ )
+ port map (
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
+ udp_tx_siso_arr => dp_offload_tx_src_in_arr,
+ udp_rx_sosi_arr => dp_offload_rx_snk_in_arr,
+ udp_rx_siso_arr => dp_offload_rx_snk_out_arr,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- UniBoard FPGA pins
+ CLK => '0',
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm_unb1_dp_offload : entity work.mmm_unb1_dp_offload
- generic map (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_nof_streams => c_nof_streams,
- g_bg_block_size => c_bg_block_size,
- g_hdr_field_arr => c_hdr_field_arr
- )
- port map(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
-
- dp_clk => dp_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- ram_diag_bg_mosi => ram_diag_bg_mosi,
- ram_diag_bg_miso => ram_diag_bg_miso,
- reg_diag_bg_mosi => reg_diag_bg_mosi,
- reg_diag_bg_miso => reg_diag_bg_miso,
-
- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
- reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-
- ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
- ram_diag_data_buf_miso => ram_diag_data_buf_miso,
- reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
- reg_diag_data_buf_miso => reg_diag_data_buf_miso
- );
+ generic map (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_nof_streams => c_nof_streams,
+ g_bg_block_size => c_bg_block_size,
+ g_hdr_field_arr => c_hdr_field_arr
+ )
+ port map(
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+
+ dp_clk => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ ram_diag_bg_mosi => ram_diag_bg_mosi,
+ ram_diag_bg_miso => ram_diag_bg_miso,
+ reg_diag_bg_mosi => reg_diag_bg_mosi,
+ reg_diag_bg_miso => reg_diag_bg_miso,
+
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
+ reg_bsn_monitor_miso => reg_bsn_monitor_miso,
+
+ ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_diag_data_buf_miso => ram_diag_data_buf_miso,
+ reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_diag_data_buf_miso => reg_diag_data_buf_miso
+ );
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
index 9faac986ed33160b6a3cb042cdb017a7fc23d1df..c85e61e80c50d1592b72e915d9283ac25978e23c 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
@@ -38,11 +38,11 @@
-- . run -a
library IEEE, common_lib, unb1_board_lib, i2c_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use unb1_board_lib.unb1_board_pkg.all;
-use common_lib.tb_common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use unb1_board_lib.unb1_board_pkg.all;
+ use common_lib.tb_common_pkg.all;
entity tb_unb1_dp_offload is
end tb_unb1_dp_offload;
@@ -94,5 +94,5 @@ begin
ETH_clk => eth_clk,
ETH_SGIN => eth_lpbk,
ETH_SGOUT => eth_lpbk
- );
+ );
end tb;
diff --git a/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd b/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
index 739917a35ef9a1b434fd9992a04d6b3eebe57d5d..3862de45bf4d4db4a252b5cafab87a64e341da0a 100644
--- a/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
+++ b/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
@@ -117,7 +117,8 @@ begin
src_out <= snk_in_reg;
end generate;
- use_flow_control : if g_use_ready = true generate
+ use_flow_control : if g_use_ready = true generate
+
gen_dp_pipeline : if g_pipeline_ready = false generate
u_dp_pipeline : entity work.dp_pipeline
port map (
@@ -149,5 +150,6 @@ begin
src_out => src_out
);
end generate;
+
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
index 2c4615062225e116938992f2938b63e0af3a1bfd..1d10b83dce56c1cf6aabb7a4dff0ee943531ea29 100644
--- a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
+++ b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
@@ -23,10 +23,10 @@
-- Description:
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_barrel_shift is
generic (
@@ -51,10 +51,11 @@ architecture str of dp_barrel_shift is
shift_out : std_logic_vector(ceil_log2(g_nof_streams) - 1 downto 0);
end record;
- constant c_reg_defaults : t_reg := ( (others => c_dp_sosi_rst),
- (others => '0') );
+ constant c_reg_defaults : t_reg := (
+ (others => c_dp_sosi_rst),
+ (others => '0') );
- signal r, nxt_r : t_reg := c_reg_defaults;
+ signal r, nxt_r : t_reg := c_reg_defaults;
begin
r <= nxt_r when rising_edge(clk);
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 96e84bff329d7f69694decb02a38a5b9c9ec8825..9e8a7fb4f1f189250773504e429247677cb37145 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -64,11 +64,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm is
generic (
@@ -107,29 +107,29 @@ architecture rtl of dp_block_from_mm is
eop : std_logic;
sync_in_detected : std_logic;
bsn : std_logic_vector(g_bsn_w - 1 downto 0);
- user_index : natural range 0 to g_user_size; -- word index in g_user_size
- data_index : natural range 0 to g_data_size; -- default word order index in g_data_size
- word_index : natural range 0 to g_data_size; -- default or reversed word order index in g_data_size
- step_address : natural range 0 to c_mem_size; -- step address offset
- end record;
-
- constant c_reg_rst : t_reg := ('0', '0', '0', '0', '0', (others => '0'), 0, 0, 0, 0);
-
- signal r : t_reg;
- signal nxt_r : t_reg;
-
- signal last_mm_address : natural := 0;
- signal mm_address : natural := 0;
- signal mm_address_rev : natural := 0;
-
- signal r_sop_p : std_logic;
- signal r_eop_p : std_logic;
- signal r_sync_p : std_logic;
- signal r_bsn_p : std_logic_vector(g_bsn_w - 1 downto 0);
- signal out_sop : std_logic;
- signal out_eop : std_logic;
- signal out_sync : std_logic;
- signal out_bsn : std_logic_vector(g_bsn_w - 1 downto 0);
+ user_index : natural range 0 to g_user_size; -- word index in g_user_size
+data_index : natural range 0 to g_data_size; -- default word order index in g_data_size
+word_index : natural range 0 to g_data_size; -- default or reversed word order index in g_data_size
+step_address : natural range 0 to c_mem_size; -- step address offset
+end record;
+
+constant c_reg_rst : t_reg := ('0', '0', '0', '0', '0', (others => '0'), 0, 0, 0, 0);
+
+signal r : t_reg;
+signal nxt_r : t_reg;
+
+signal last_mm_address : natural := 0;
+signal mm_address : natural := 0;
+signal mm_address_rev : natural := 0;
+
+signal r_sop_p : std_logic;
+signal r_eop_p : std_logic;
+signal r_sync_p : std_logic;
+signal r_bsn_p : std_logic_vector(g_bsn_w - 1 downto 0);
+signal out_sop : std_logic;
+signal out_eop : std_logic;
+signal out_sync : std_logic;
+signal out_bsn : std_logic_vector(g_bsn_w - 1 downto 0);
begin
last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
mm_address <= start_address + r.data_index + r.step_address; -- default word order per g_user_size
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index a5dbf8136b58958fbfc2b228b8f53ed13d73e326..1c36c28cffa9adbf60b43f15fc56fb76b33eb07f 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -40,11 +40,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_from_mm_dc is
generic (
@@ -110,17 +110,17 @@ begin
-- if mm_start_pulse arrive one clock cycle early and mm_sync_hi arrives one
-- clock cycle late.
u_common_spulse_start_pulse : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len + 4
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => start_pulse,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_start_pulse
- );
+ generic map (
+ g_delay_len => c_meta_delay_len + 4
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => start_pulse,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_start_pulse
+ );
-- The synchronous start_pulse and sync_in in the dp_clk domain cannot be
-- passed on via two separate common_spulse instances, because then they may
@@ -128,17 +128,17 @@ begin
-- dp_clk and mm_clk are asynchronous on HW. Therefore use mm_sync_level to
-- pass on sync_in.
u_common_spulse_sync : entity common_lib.common_spulse
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- in_rst => dp_rst,
- in_clk => dp_clk,
- in_pulse => sync_in,
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_pulse => mm_sync_hi
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => sync_in,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_sync_hi
+ );
p_mm_sync : process(mm_clk)
begin
@@ -158,75 +158,75 @@ begin
mm_start_address <= TO_UINT(mm_start_address_slv);
u_common_async_slv_start_address : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => start_address_slv,
- dout => mm_start_address_slv
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => start_address_slv,
+ dout => mm_start_address_slv
+ );
u_common_async_slv_bsn : entity common_lib.common_async_slv
- generic map (
- g_delay_len => c_meta_delay_len
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => bsn_at_sync,
- dout => mm_bsn_at_sync
- );
+ generic map (
+ g_delay_len => c_meta_delay_len
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => bsn_at_sync,
+ dout => mm_bsn_at_sync
+ );
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => true,
- g_data_w => c_word_w,
- g_bsn_w => g_bsn_w,
- g_use_bsn => true,
- g_use_sync => true,
- g_fifo_fill => c_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- -- ST sink
- snk_in => mm_fifo_sosi,
- snk_out => mm_fifo_siso,
- -- ST source
- src_out => dp_out_sosi,
- src_in => dp_out_siso
- );
+ generic map (
+ g_use_dual_clock => true,
+ g_data_w => c_word_w,
+ g_bsn_w => g_bsn_w,
+ g_use_bsn => true,
+ g_use_sync => true,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ -- ST sink
+ snk_in => mm_fifo_sosi,
+ snk_out => mm_fifo_siso,
+ -- ST source
+ src_out => dp_out_sosi,
+ src_in => dp_out_siso
+ );
u_dp_block_from_mm : entity work.dp_block_from_mm
- generic map (
- g_user_size => g_user_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data,
- g_word_w => g_word_w,
- g_reverse_word_order => g_reverse_word_order,
- g_bsn_w => g_bsn_w,
- g_bsn_incr_enable => g_bsn_incr_enable
- )
- port map (
- clk => mm_clk,
- rst => mm_rst,
-
- start_pulse => mm_start_pulse,
- sync_in => mm_sync,
- bsn_at_sync => mm_bsn_at_sync,
- start_address => mm_start_address,
- mm_done => mm_done, -- = mm_fifo_sosi.eop
- mm_mosi => mm_mosi,
- mm_miso => mm_miso,
- out_sosi => mm_fifo_sosi,
- out_siso => mm_fifo_siso
- );
+ generic map (
+ g_user_size => g_user_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data,
+ g_word_w => g_word_w,
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => g_bsn_w,
+ g_bsn_incr_enable => g_bsn_incr_enable
+ )
+ port map (
+ clk => mm_clk,
+ rst => mm_rst,
+
+ start_pulse => mm_start_pulse,
+ sync_in => mm_sync,
+ bsn_at_sync => mm_bsn_at_sync,
+ start_address => mm_start_address,
+ mm_done => mm_done, -- = mm_fifo_sosi.eop
+ mm_mosi => mm_mosi,
+ mm_miso => mm_miso,
+ out_sosi => mm_fifo_sosi,
+ out_siso => mm_fifo_siso
+ );
-- Wire output
out_sop <= dp_out_sosi.sop;
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index a9f997127f73a8d6713931cab1ede931fe4f6546..8155470706c6664ce6f3cae7b6cd137011021b9f 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -63,10 +63,10 @@
-- dp_block_reshape.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 0abb80fa529abc405fd5e652a2418086253a1683..dcd1813109e5ea42ac64adfa88b67b565958c5f0 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -140,10 +140,10 @@
-- allow for a fractional amount of blocks per sync period.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_gen_valid_arr is
generic (
@@ -226,17 +226,17 @@ begin
in_sync_wr_en <= (others => snk_in.sync);
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => in_sync_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => in_bsn_buffer
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => in_sync_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => in_bsn_buffer
+ );
p_snk_in : process(snk_in, in_bsn_buffer)
begin
@@ -326,12 +326,12 @@ begin
end process;
-- Use local BSN that counts from 0 during sync interval, or restore global BSN between syncs
- use_local_bsn : if g_restore_global_bsn = false generate
+ use_local_bsn : if g_restore_global_bsn = false generate
out_sosi <= nxt_r.reg_sosi;
- end generate;
+end generate;
use_global_bsn : if g_restore_global_bsn = true generate
- u_dp_bsn_restore_global : entity work.dp_bsn_restore_global
+ u_dp_bsn_restore_global : entity work.dp_bsn_restore_global
generic map (
g_bsn_w => c_dp_stream_bsn_w,
g_pipeline => 0 -- pipeline registering is done via nxt_src_out_arr
@@ -346,6 +346,6 @@ begin
);
end generate;
- -- Combine input data with the same out_put info and output ctrl for all streams
- nxt_src_out_arr <= func_dp_stream_arr_combine_data_info_ctrl(snk_in_arr, out_sosi, out_sosi);
+-- Combine input data with the same out_put info and output ctrl for all streams
+nxt_src_out_arr <= func_dp_stream_arr_combine_data_info_ctrl(snk_in_arr, out_sosi, out_sosi);
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 5e1dce61c28cd8686f0af5b7fc9d5db06be4f3af..f59acd8dcbe0d34900ac3db258de98534973d65d 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -72,10 +72,10 @@
-- an input block stream.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape is
generic (
@@ -99,9 +99,9 @@ end dp_block_reshape;
architecture str of dp_block_reshape is
constant c_nof_counters : natural := 2; -- counter [0] is used for block reshape and valid index,
- -- counter [1] is only used for sop_index
+ -- counter [1] is only used for sop_index
constant c_nof_block_per_sync : natural := sel_a_b(g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
- g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
+ g_input_nof_data_per_sync / g_reshape_nof_data_per_blk, 1);
constant c_range_start : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 0);
constant c_range_stop : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (c_nof_block_per_sync, g_reshape_nof_data_per_blk);
@@ -111,26 +111,26 @@ architecture str of dp_block_reshape is
signal input_src_out : t_dp_sosi;
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in => snk_in,
- snk_out => snk_out,
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => input_src_out,
- src_in => src_in,
+ src_out => input_src_out,
+ src_in => src_in,
- count_src_out_arr => cnt_sosi_arr
- );
+ count_src_out_arr => cnt_sosi_arr
+ );
src_index_arr(1) <= TO_UINT(cnt_sosi_arr(1).data); -- sop index
src_index_arr(0) <= TO_UINT(cnt_sosi_arr(0).data); -- valid index
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d0d7039eca77f37147710560ded3f457982c4f40..9ba397219a108de468415bfb116e46a671f0500b 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -33,10 +33,10 @@
--
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_arr is
generic (
@@ -125,23 +125,23 @@ begin
-- Instantiate dp_block_reshape per stream
gen_streams : for I in 0 to g_nof_streams - 1 generate
u_block_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => g_input_nof_data_per_sync,
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
+ generic map (
+ g_input_nof_data_per_sync => g_input_nof_data_per_sync,
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
- snk_in => in_sosi_arr(I),
- snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ snk_out => in_siso_arr(I),
- src_out => out_sosi_arr(I),
- src_in => out_siso_arr(I),
- src_index_arr => out_index_2arr_2(I)
- );
+ src_out => out_sosi_arr(I),
+ src_in => out_siso_arr(I),
+ src_index_arr => out_index_2arr_2(I)
+ );
end generate;
-- Wire index arr
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index 2934cf719e37345e6970b6e9ab2353f0db9fd976..813d5ff1c5f2a9884e281592181711615470009b 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -65,10 +65,10 @@
-- dp_sync_insert.vhd.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_reshape_sync is
generic (
@@ -98,7 +98,7 @@ architecture str of dp_block_reshape_sync is
-- If g_input_nof_data_per_sync <= c_reshape_nof_data_per_sync then c_nof_output_sync_per_input_sync = 1, else the
-- assumption is that g_input_nof_data_per_sync is an integer multiple of c_reshape_nof_data_per_sync.
constant c_nof_output_sync_per_input_sync : natural := sel_a_b(g_input_nof_data_per_sync > c_reshape_nof_data_per_sync,
- g_input_nof_data_per_sync / c_reshape_nof_data_per_sync, 1);
+ g_input_nof_data_per_sync / c_reshape_nof_data_per_sync, 1);
-- counter [0] is use for block reshape,
-- counter [1] is used for sync reshape,
@@ -106,8 +106,8 @@ architecture str of dp_block_reshape_sync is
constant c_nof_counters : natural := sel_a_b(c_nof_output_sync_per_input_sync > 1, 3, 2);
constant c_range_start : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 0);
constant c_range_stop : t_nat_natural_arr(c_nof_counters - 1 downto 0) := sel_a_b(c_nof_output_sync_per_input_sync > 1,
- (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
- (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
+ (c_nof_output_sync_per_input_sync, g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk),
+ (g_reshape_nof_blk_per_sync, g_reshape_nof_data_per_blk));
constant c_range_step : t_nat_natural_arr(c_nof_counters - 1 downto 0) := (others => 1);
signal cnt_sosi_arr : t_dp_sosi_arr(c_nof_counters - 1 downto 0);
@@ -131,26 +131,26 @@ architecture str of dp_block_reshape_sync is
signal reg_global_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
begin
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => c_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => input_sosi,
- src_in => input_siso,
-
- count_src_out_arr => cnt_sosi_arr
- );
+ generic map (
+ g_nof_counters => c_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => input_sosi,
+ src_in => input_siso,
+
+ count_src_out_arr => cnt_sosi_arr
+ );
gen_sync_index : if c_nof_output_sync_per_input_sync > 1 generate
sync_index <= TO_UINT(cnt_sosi_arr(2).data);
diff --git a/libraries/base/dp/src/vhdl/dp_block_resize.vhd b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
index db89a827502ab817b05dbe32f386bf4a6b1f0b75..388a3dcdc34e8e92902f9a383e54a2964ee68613 100644
--- a/libraries/base/dp/src/vhdl/dp_block_resize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 16 Mar 2018
-- Purpose:
@@ -62,8 +62,8 @@ entity dp_block_resize is
end dp_block_resize;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_resize is
signal cnt_reg : natural range 0 to g_input_block_size-1;
@@ -126,17 +126,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_select.vhd b/libraries/base/dp/src/vhdl/dp_block_select.vhd
index 773adcfb0d7a252de34f76baf399f7701a04fd35..33ebfc92bc5707594aa0957820f323449bbe5462 100644
--- a/libraries/base/dp/src/vhdl/dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_select.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 14 Dec 2018
-- Purpose:
@@ -74,8 +74,8 @@ entity dp_block_select is
end dp_block_select;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture rtl of dp_block_select is
signal cnt_reg : natural range 0 to true_log_pow2(g_nof_blocks_per_sync);
@@ -140,17 +140,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 0c1cb305606823ade252d499f0f6e54719c9547b..bb6f2cf94730a11bec126a52bf1261724b796374 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -26,11 +26,11 @@
-- --------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_block_to_mm is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index a9a587e8e43db9ad4f0e69d1abf47775d610c930..ebf583da03b72441b97ec632a940d8b4eb334545 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -61,11 +61,11 @@
-- =====================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_bsn_at_sync is
generic (
@@ -93,30 +93,31 @@ architecture rtl of dp_block_validate_bsn_at_sync is
constant c_nof_regs : natural := 3;
constant c_clear_adr : natural := c_nof_regs - 1;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs, -- total counter + discarded counter
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs, -- total counter + discarded counter
+ init_sl => '0');
- -- Registers in st_clk domain
- signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
+ -- Registers in st_clk domain
+ signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
- signal mm_cnt_clr : std_logic;
- signal cnt_clr : std_logic;
- signal cnt_sync : std_logic_vector(c_word_w - 1 downto 0);
- signal cnt_sync_en : std_logic;
- signal cnt_discarded : std_logic_vector(c_word_w - 1 downto 0);
- signal cnt_discarded_en : std_logic;
+ signal mm_cnt_clr : std_logic;
+ signal cnt_clr : std_logic;
+ signal cnt_sync : std_logic_vector(c_word_w - 1 downto 0);
+ signal cnt_sync_en : std_logic;
+ signal cnt_discarded : std_logic_vector(c_word_w - 1 downto 0);
+ signal cnt_discarded_en : std_logic;
- signal out_valid : std_logic;
- signal out_valid_reg : std_logic;
- signal bsn_ok : std_logic;
- signal bsn_ok_reg : std_logic;
- signal bsn_at_sync : std_logic_vector(g_bsn_w - 1 downto 0);
- signal bsn_at_sync_reg : std_logic_vector(g_bsn_w - 1 downto 0);
+ signal out_valid : std_logic;
+ signal out_valid_reg : std_logic;
+ signal bsn_ok : std_logic;
+ signal bsn_ok_reg : std_logic;
+ signal bsn_at_sync : std_logic_vector(g_bsn_w - 1 downto 0);
+ signal bsn_at_sync_reg : std_logic_vector(g_bsn_w - 1 downto 0);
- signal block_sosi : t_dp_sosi;
+ signal block_sosi : t_dp_sosi;
begin
mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
@@ -131,61 +132,61 @@ begin
-- discarded counter
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
+ );
-- sync counter
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => c_word_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => c_word_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => in_sosi.sync,
- count => cnt_sync
- );
+ cnt_clr => cnt_clr,
+ cnt_en => in_sosi.sync,
+ count => cnt_sync
+ );
-- Register mapping
count_reg( c_word_w - 1 downto 0 ) <= cnt_discarded;
count_reg(2 * c_word_w - 1 downto c_word_w ) <= cnt_sync;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
-- Process to check the bsn at sync. It captures the bsn at the sync of bs_sosi. Then compares that bsn to
-- the bsn at sync of in_sosi. If they are unequal all packets during that sync period with in_sosi.channel
@@ -254,15 +255,15 @@ begin
end process;
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => block_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => block_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 32c4a07830c6a5f317ef2d24be6d37f6d5332ca0..b2c7e24746b31bda8c094e7baab82100192d5534 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -32,11 +32,11 @@
-- Remarks:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_channel is
generic (
@@ -63,17 +63,20 @@ architecture rtl of dp_block_validate_channel is
signal keep_sosi : t_dp_sosi;
begin
assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
+
gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) = unsigned(remove_channel) else '0';
end generate;
+
gen_smaller : if g_mode = "<" generate -- remove all blocks with ch < remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) < unsigned(remove_channel) else '0';
end generate;
+
gen_larger : if g_mode = ">" generate -- remove all blocks with ch > remove_channel
- remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
- '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
+ remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
+ '1' when unsigned(in_sosi.channel) > unsigned(remove_channel) else '0';
end generate;
p_dp_clk : process(dp_rst, dp_clk)
@@ -102,28 +105,28 @@ begin
end process;
u_pipe_remove : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => remove_sosi,
- -- ST source
- src_out => out_remove_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => remove_sosi,
+ -- ST source
+ src_out => out_remove_sosi
+ );
u_pipe_keep : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => keep_sosi,
- -- ST source
- src_out => out_keep_sosi
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => keep_sosi,
+ -- ST source
+ src_out => out_keep_sosi
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index ed166c70ddf87284ebbf0a8e0e9dfe0d4cbebf1e..7fcc864e08af3caf9cf1d6e74767033435d76508 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -72,11 +72,11 @@
-- ====================================================================================
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_block_validate_err is
generic (
@@ -128,43 +128,44 @@ architecture rtl of dp_block_validate_err is
type t_cnt_err_arr is array (integer range <>) of std_logic_vector(g_cnt_w - 1 downto 0);
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_nof_regs,
- init_sl => '0');
-
- -- Registers in st_clk domain
- signal ref_sync_reg : std_logic := '0';
- signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
-
- signal nxt_cnt_en : std_logic;
- signal cnt_en : std_logic := '0';
- signal cnt_this_eop : std_logic;
-
- signal mm_cnt_clr : std_logic;
- signal cnt_clr : std_logic;
- signal cnt_blk : std_logic_vector(g_blk_cnt_w - 1 downto 0);
- signal cnt_blk_en : std_logic;
- signal cnt_discarded : std_logic_vector(g_cnt_w - 1 downto 0);
- signal cnt_discarded_en : std_logic;
- signal cnt_err_arr : t_cnt_err_arr(g_nof_err_counts - 1 downto 0);
- signal cnt_err_en_arr : std_logic_vector(g_nof_err_counts - 1 downto 0);
-
- signal hold_cnt_blk : std_logic_vector(g_blk_cnt_w - 1 downto 0) := (others => '0');
- signal hold_cnt_discarded : std_logic_vector(g_cnt_w - 1 downto 0) := (others => '0');
- signal hold_cnt_err_arr : t_cnt_err_arr(g_nof_err_counts - 1 downto 0) := (others => (others => '0'));
-
- signal err_ok : std_logic;
- signal err_ok_reg : std_logic;
- signal fifo_err_ok : std_logic;
- signal fifo_err_ok_val : std_logic;
- signal out_valid : std_logic;
- signal out_valid_reg : std_logic;
-
- signal block_sosi : t_dp_sosi;
- signal block_siso : t_dp_siso;
- signal block_sosi_piped : t_dp_sosi;
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_nof_regs,
+ init_sl => '0');
+
+ -- Registers in st_clk domain
+ signal ref_sync_reg : std_logic := '0';
+ signal count_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
+
+ signal nxt_cnt_en : std_logic;
+ signal cnt_en : std_logic := '0';
+ signal cnt_this_eop : std_logic;
+
+ signal mm_cnt_clr : std_logic;
+ signal cnt_clr : std_logic;
+ signal cnt_blk : std_logic_vector(g_blk_cnt_w - 1 downto 0);
+ signal cnt_blk_en : std_logic;
+ signal cnt_discarded : std_logic_vector(g_cnt_w - 1 downto 0);
+ signal cnt_discarded_en : std_logic;
+ signal cnt_err_arr : t_cnt_err_arr(g_nof_err_counts - 1 downto 0);
+ signal cnt_err_en_arr : std_logic_vector(g_nof_err_counts - 1 downto 0);
+
+ signal hold_cnt_blk : std_logic_vector(g_blk_cnt_w - 1 downto 0) := (others => '0');
+ signal hold_cnt_discarded : std_logic_vector(g_cnt_w - 1 downto 0) := (others => '0');
+ signal hold_cnt_err_arr : t_cnt_err_arr(g_nof_err_counts - 1 downto 0) := (others => (others => '0'));
+
+ signal err_ok : std_logic;
+ signal err_ok_reg : std_logic;
+ signal fifo_err_ok : std_logic;
+ signal fifo_err_ok_val : std_logic;
+ signal out_valid : std_logic;
+ signal out_valid_reg : std_logic;
+
+ signal block_sosi : t_dp_sosi;
+ signal block_siso : t_dp_siso;
+ signal block_sosi_piped : t_dp_sosi;
begin
mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
@@ -190,39 +191,22 @@ begin
-- block counter
cnt_blk_en <= cnt_this_eop;
u_blk_counter : entity common_lib.common_counter
- generic map (
- g_width => g_blk_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_blk_en,
- count => cnt_blk
- );
+ generic map (
+ g_width => g_blk_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_blk_en,
+ count => cnt_blk
+ );
-- discarded block counter
cnt_discarded_en <= cnt_this_eop when TO_UINT(snk_in.err(g_nof_err_counts - 1 downto 0)) > 0 else '0';
u_discarded_counter : entity common_lib.common_counter
- generic map (
- g_width => g_cnt_w,
- g_clip => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- cnt_clr => cnt_clr,
- cnt_en => cnt_discarded_en,
- count => cnt_discarded
- );
-
- -- error counters
- gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
- cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
- u_blk_counter : entity common_lib.common_counter
generic map (
g_width => g_cnt_w,
g_clip => true
@@ -232,9 +216,26 @@ begin
clk => dp_clk,
cnt_clr => cnt_clr,
- cnt_en => cnt_err_en_arr(I),
- count => cnt_err_arr(I)
+ cnt_en => cnt_discarded_en,
+ count => cnt_discarded
);
+
+ -- error counters
+ gen_err_counters : for I in 0 to g_nof_err_counts - 1 generate
+ cnt_err_en_arr(I) <= cnt_this_eop and snk_in.err(I);
+ u_blk_counter : entity common_lib.common_counter
+ generic map (
+ g_width => g_cnt_w,
+ g_clip => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_err_en_arr(I),
+ count => cnt_err_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg to have stable values for MM read for comparision between nodes
@@ -271,69 +272,69 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => count_reg, -- read only
- out_reg => open -- no write
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => count_reg, -- read only
+ out_reg => open -- no write
+ );
u_fifo_fill_eop_sc : entity work.dp_fifo_fill_eop_sc
- generic map (
- g_note_is_ful => g_fifo_note_is_ful,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_max_block_size,
- g_fifo_size => g_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => block_siso,
- src_out => block_sosi
- );
+ generic map (
+ g_note_is_ful => g_fifo_note_is_ful,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_max_block_size,
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => block_siso,
+ src_out => block_sosi
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_out => block_siso,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => block_sosi_piped
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => block_siso,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => block_sosi_piped
+ );
p_dp_clk : process(dp_rst, dp_clk)
begin
@@ -349,20 +350,20 @@ begin
err_ok <= not vector_or(snk_in.err(g_nof_err_counts - 1 downto 0)) when snk_in.eop = '1' else err_ok_reg;
u_fifo_err_ok : entity common_lib.common_fifo_sc
- generic map (
- g_note_is_ful => g_fifo_note_is_ful,
- g_dat_w => 1,
- g_nof_words => c_nof_err_ok
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_dat(0) => err_ok,
- wr_req => snk_in.eop,
- rd_req => block_sosi.sop,
- rd_dat(0) => fifo_err_ok,
- rd_val => fifo_err_ok_val
- );
+ generic map (
+ g_note_is_ful => g_fifo_note_is_ful,
+ g_dat_w => 1,
+ g_nof_words => c_nof_err_ok
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_dat(0) => err_ok,
+ wr_req => snk_in.eop,
+ rd_req => block_sosi.sop,
+ rd_dat(0) => fifo_err_ok,
+ rd_val => fifo_err_ok_val
+ );
out_valid <= fifo_err_ok when fifo_err_ok_val = '1' else out_valid_reg;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
index d523cc1506b921a52ff9e8f18b7ad7ee970946b8..321909ee5967a1e6512da99342e4770c756d22c8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
@@ -43,8 +43,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_block_validate_length is
generic (
@@ -111,17 +111,17 @@ begin
-- Register block_sosi to easy timing closure
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1 -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => block_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1 -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => block_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index f8c6daeaf27d4dc1e0a86bd3b0f4d462fa7e7f8f..55d87297a539d27f37f866a2386631f75a2fcaf9 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Future note:
-- The dp_bsn_align aligns at BSN level. In retrospect it is probably
@@ -233,67 +233,67 @@ begin
-- control user input enable updates to not occur during a block
u_in_en_new : entity common_lib.common_switch
- generic map (
- g_rst_level => '0',
- g_priority_lo => false,
- g_or_high => false,
- g_and_low => false
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_en_evt,
- switch_low => in_en_ack,
- out_level => in_en_new
- );
+ generic map (
+ g_rst_level => '0',
+ g_priority_lo => false,
+ g_or_high => false,
+ g_and_low => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_en_evt,
+ switch_low => in_en_ack,
+ out_level => in_en_new
+ );
-- block reference
u_block_gen : entity work.dp_block_gen
- generic map (
- g_nof_data => g_block_size,
- g_empty => 0,
- g_channel => 0,
- g_error => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming source
- src_in => blk_siso,
- src_out => blk_sosi,
- -- MM control
- en => blk_en
- );
+ generic map (
+ g_nof_data => g_block_size,
+ g_empty => 0,
+ g_channel => 0,
+ g_error => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming source
+ src_in => blk_siso,
+ src_out => blk_sosi,
+ -- MM control
+ en => blk_en
+ );
-- Hold the sink input to be able to register the source output
u_block_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => blk_siso, -- wired blk_siso = hold_blk_in
- snk_in => blk_sosi,
- -- ST source
- src_in => hold_blk_in,
- next_src_out => next_blk_buf,
- pend_src_out => OPEN,
- src_out_reg => r.blk_buf
- );
-
- gen_inputs : for I in g_nof_input - 1 downto 0 generate
- u_hold : entity work.dp_hold_input
port map (
rst => rst,
clk => clk,
-- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
+ snk_out => blk_siso, -- wired blk_siso = hold_blk_in
+ snk_in => blk_sosi,
-- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_buf_arr(I),
- pend_src_out => pend_src_buf_arr(I),
- src_out_reg => r.src_buf_arr(I)
+ src_in => hold_blk_in,
+ next_src_out => next_blk_buf,
+ pend_src_out => OPEN,
+ src_out_reg => r.blk_buf
);
+
+ gen_inputs : for I in g_nof_input - 1 downto 0 generate
+ u_hold : entity work.dp_hold_input
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_buf_arr(I),
+ pend_src_out => pend_src_buf_arr(I),
+ src_out_reg => r.src_buf_arr(I)
+ );
end generate;
-- This is not Erlang or Haskell, but that does not mean that we can not do some functional programming in VHDL as well.
@@ -325,38 +325,38 @@ begin
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_max <= func_dp_stream_arr_bsn_max(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_max : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MAX",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_max
- );
+ generic map (
+ g_operation => "MAX",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_max
+ );
-- Use tree instead of folding to ease timing closure:
-- pend_bsn_min <= func_dp_stream_arr_bsn_min(pend_src_buf_arr, r.in_en_arr, c_bsn_align_w);
u_pend_bsn_min : entity common_lib.common_operation_tree
- generic map (
- g_operation => "MIN",
- g_representation => "UNSIGNED",
- g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
- g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
- g_nof_inputs => g_nof_input,
- g_dat_w => c_bsn_align_w
- )
- port map (
- clk => clk,
- in_data_vec => pend_bsn_vec,
- in_en_vec => r.in_en_arr,
- result => pend_bsn_min
- );
+ generic map (
+ g_operation => "MIN",
+ g_representation => "UNSIGNED",
+ g_pipeline => c_bsn_stage_pipeline, -- amount of output pipelining per stage
+ g_pipeline_mod => c_bsn_stage_pipeline_mod, -- only pipeline the stage output by g_pipeline when the stage number MOD g_pipeline_mod = 0
+ g_nof_inputs => g_nof_input,
+ g_dat_w => c_bsn_align_w
+ )
+ port map (
+ clk => clk,
+ in_data_vec => pend_bsn_vec,
+ in_en_vec => r.in_en_arr,
+ result => pend_bsn_min
+ );
-- Hold input registers
nxt_r.blk_buf <= next_blk_buf;
@@ -461,7 +461,7 @@ begin
nxt_r.timeout_cnt <= (others => '0');
nxt_r.state <= s_xoff;
end if;
- -- check user input enable control (must use 'ELSIF' and not 'END IF; IF', to properly handle case where both conditions are TRUE at same clock cycle)
+ -- check user input enable control (must use 'ELSIF' and not 'END IF; IF', to properly handle case where both conditions are TRUE at same clock cycle)
elsif in_en_new = '1' then
-- need to use updated user input enable settings, so flush all inputs and try to align again
nxt_r.timeout_cnt <= (others => '0');
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index e2f93b3baf63e0f68a8f584f62748b3f2ab159ec..4ffb55563ec32256536af09365749e42f7f05348 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -40,9 +40,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_align_reg is
generic (
@@ -68,49 +68,49 @@ end dp_bsn_align_reg;
architecture str of dp_bsn_align_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_input),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_input,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_input),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_input,
+ init_sl => '0');
- -- FUNCTION array_init(init : NATURAL; nof, width : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init an unconstrained std_logic_vector with repetitive content
- constant c_reg_init : std_logic_vector(g_nof_input * c_word_w - 1 downto 0) := array_init(1, g_nof_input, c_word_w);
+ -- FUNCTION array_init(init : NATURAL; nof, width : NATURAL) RETURN STD_LOGIC_VECTOR; -- useful to init an unconstrained std_logic_vector with repetitive content
+ constant c_reg_init : std_logic_vector(g_nof_input * c_word_w - 1 downto 0) := array_init(1, g_nof_input, c_word_w);
- -- Registers in st_clk domain
- signal out_en_arr_reg : std_logic_vector(g_nof_input * c_word_w - 1 downto 0); -- := (OTHERS => '1');
- signal reg_wr_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
+ -- Registers in st_clk domain
+ signal out_en_arr_reg : std_logic_vector(g_nof_input * c_word_w - 1 downto 0); -- := (OTHERS => '1');
+ signal reg_wr_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
begin
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => RESIZE_UVEC(c_reg_init, c_mem_reg_init_w) -- RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w)
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => out_en_arr_reg, -- read
- out_reg => out_en_arr_reg, -- write
- out_new => out_en_evt
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => out_en_arr_reg, -- read
+ out_reg => out_en_arr_reg, -- write
+ out_new => out_en_evt
+ );
gen_out_arr : for I in 0 to g_nof_input - 1 generate
out_en_arr(I) <= out_en_arr_reg(I * c_word_w);
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 9042f050f7797b53fec3194857d70a0b6aac009c..13e4ac8ce850d441942178176204bc44e469914c 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -48,11 +48,11 @@
-- robust.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_align_v2 is
generic (
@@ -96,127 +96,130 @@ architecture rtl of dp_bsn_align_v2 is
constant c_buffer_nof_blocks : natural := true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
constant c_ram_size : natural := c_buffer_nof_blocks * g_block_size;
- constant c_ram_buf : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_size),
- dat_w => g_data_w,
- nof_dat => c_ram_size,
- init_sl => '0');
-
- -- Use +1 to ensure that g_block_size that is power of 2 also fits in c_block_size_slv
- constant c_block_size_w : natural := ceil_log2(g_block_size + 1);
- constant c_block_size_slv : std_logic_vector(c_block_size_w - 1 downto 0) := TO_UVEC(g_block_size, c_block_size_w);
- constant c_blk_pointer_w : natural := ceil_log2(c_buffer_nof_blocks);
-
- -- Use fixed slv width instead of using naturals for address calculation, to
- -- avoid that synthesis may infer a too larger multiplier
- constant c_product_w : natural := c_blk_pointer_w + c_block_size_w;
-
- -- Output on lost data flag via out_sosi_arr().channel bit 0
- constant c_channel_w : natural := 1;
-
- type t_bsn_arr is array (integer range <>) of std_logic_vector(g_bsn_w - 1 downto 0);
- type t_channel_arr is array (integer range <>) of std_logic_vector(c_channel_w - 1 downto 0);
- type t_adr_arr is array (integer range <>) of std_logic_vector(c_ram_buf.adr_w - 1 downto 0);
- type t_filled_arr is array (integer range <>) of std_logic_vector(c_buffer_nof_blocks - 1 downto 0);
-
- -- State
- type t_reg is record
- -- p_write_arr
- wr_blk_pointer : natural;
- wr_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0);
- -- all streams
- filled_arr : t_filled_arr(g_nof_streams - 1 downto 0);
- use_replacement_data : std_logic_vector(g_nof_streams - 1 downto 0);
- -- local reference
- sync_arr : std_logic_vector(c_buffer_nof_blocks - 1 downto 0);
- bsn_arr : t_bsn_arr(c_buffer_nof_blocks - 1 downto 0);
- mm_sosi : t_dp_sosi;
- dp_sosi : t_dp_sosi;
- -- p_read
- rd_blk_pointer : integer; -- use integer to detect need to wrap to natural
- rd_offset : std_logic_vector(c_ram_buf.adr_w - 1 downto 0);
- rd_copi : t_mem_copi;
- fill_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
- out_bsn : std_logic_vector(g_bsn_w - 1 downto 0); -- hold BSN until next sop, for easy view in Wave window
- out_channel_arr : t_channel_arr(g_nof_streams - 1 downto 0); -- hold channel until next sop per stream, for easy view in Wave window
- replace_cnt_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- end record;
-
- -- Wires and auxiliary variables in p_comb
- -- . For unique representation as signal wire, the p_comb should assign each
- -- field in t_comb only once to a variable. It is allowed to reasign a
- -- t_comb variable in p_comb, but then only the last assignment value will
- -- be visible via the signal dbg_wires in the Wave window.
- type t_comb is record
- ref_sosi : t_dp_sosi;
- blk_pointer_slv : std_logic_vector(c_blk_pointer_w - 1 downto 0);
- product_slv : std_logic_vector(c_product_w - 1 downto 0);
- lost_data_flags_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- end record;
-
- constant c_reg_rst : t_reg := (0,
- (others => c_mem_copi_rst),
- (others => (others => '0')),
- (others => '0'),
- (others => '0'),
- (others => (others => '0')),
- c_dp_sosi_rst,
- c_dp_sosi_rst,
- 0,
- (others => '0'),
- c_mem_copi_rst,
- (others => c_mem_cipo_rst),
- (others => '0'),
- (others => (others => '0')),
- (others => '0'));
-
- constant c_comb_rst : t_comb := (c_dp_sosi_rst,
- (others => '0'),
- (others => '0'),
- (others => '0'),
- (others => c_dp_sosi_rst));
-
- -- State registers for p_comb
- signal r : t_reg;
- signal nxt_r : t_reg;
-
- -- Memoryless signals in p_comb (wires used as local variables)
- signal dbg_wires : t_comb;
-
- -- Structural signals (wires used to connect components and IO)
- signal dp_done : std_logic;
- signal dp_done_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal dp_copi : t_mem_copi;
- signal dp_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0);
-
- signal rd_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal rd_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0) := (others => c_mem_cipo_rst);
-
- -- Pipeline registers
- signal in_sosi_arr_p : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal rd_copi : t_mem_copi;
- signal comb_out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
- -- Counter signals
-
- signal replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
- signal nxt_hold_replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
- signal hold_replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
-
- -- Debug signals
- signal dbg_nof_streams : natural := g_nof_streams;
- signal dbg_bsn_latency_max : natural := g_bsn_latency_max;
- signal dbg_nof_aligners_max : natural := g_nof_aligners_max;
- signal dbg_block_size : natural := g_block_size;
- signal dbg_bsn_w : natural := g_bsn_w;
- signal dbg_data_w : natural := g_data_w;
- signal dbg_data_replacement_value : integer := g_data_replacement_value;
- signal dbg_use_mm_output : boolean := g_use_mm_output;
- signal dbg_pipeline_input : natural := g_pipeline_input;
- signal dbg_rd_latency : natural := g_rd_latency;
- signal dbg_c_buffer_nof_blocks : natural := c_buffer_nof_blocks;
- signal dbg_c_product_w : natural := c_product_w;
+ constant c_ram_buf : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_size),
+ dat_w => g_data_w,
+ nof_dat => c_ram_size,
+ init_sl => '0');
+
+ -- Use +1 to ensure that g_block_size that is power of 2 also fits in c_block_size_slv
+ constant c_block_size_w : natural := ceil_log2(g_block_size + 1);
+ constant c_block_size_slv : std_logic_vector(c_block_size_w - 1 downto 0) := TO_UVEC(g_block_size, c_block_size_w);
+ constant c_blk_pointer_w : natural := ceil_log2(c_buffer_nof_blocks);
+
+ -- Use fixed slv width instead of using naturals for address calculation, to
+ -- avoid that synthesis may infer a too larger multiplier
+ constant c_product_w : natural := c_blk_pointer_w + c_block_size_w;
+
+ -- Output on lost data flag via out_sosi_arr().channel bit 0
+ constant c_channel_w : natural := 1;
+
+ type t_bsn_arr is array (integer range <>) of std_logic_vector(g_bsn_w - 1 downto 0);
+ type t_channel_arr is array (integer range <>) of std_logic_vector(c_channel_w - 1 downto 0);
+ type t_adr_arr is array (integer range <>) of std_logic_vector(c_ram_buf.adr_w - 1 downto 0);
+ type t_filled_arr is array (integer range <>) of std_logic_vector(c_buffer_nof_blocks - 1 downto 0);
+
+ -- State
+ type t_reg is record
+ -- p_write_arr
+ wr_blk_pointer : natural;
+ wr_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0);
+ -- all streams
+ filled_arr : t_filled_arr(g_nof_streams - 1 downto 0);
+ use_replacement_data : std_logic_vector(g_nof_streams - 1 downto 0);
+-- local reference
+sync_arr : std_logic_vector(c_buffer_nof_blocks - 1 downto 0);
+bsn_arr : t_bsn_arr(c_buffer_nof_blocks - 1 downto 0);
+mm_sosi : t_dp_sosi;
+dp_sosi : t_dp_sosi;
+-- p_read
+rd_blk_pointer : integer; -- use integer to detect need to wrap to natural
+rd_offset : std_logic_vector(c_ram_buf.adr_w - 1 downto 0);
+rd_copi : t_mem_copi;
+fill_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
+out_bsn : std_logic_vector(g_bsn_w - 1 downto 0); -- hold BSN until next sop, for easy view in Wave window
+out_channel_arr : t_channel_arr(g_nof_streams - 1 downto 0); -- hold channel until next sop per stream, for easy view in Wave window
+replace_cnt_en_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+end record;
+
+-- Wires and auxiliary variables in p_comb
+-- . For unique representation as signal wire, the p_comb should assign each
+-- field in t_comb only once to a variable. It is allowed to reasign a
+-- t_comb variable in p_comb, but then only the last assignment value will
+-- be visible via the signal dbg_wires in the Wave window.
+type t_comb is record
+ ref_sosi : t_dp_sosi;
+ blk_pointer_slv : std_logic_vector(c_blk_pointer_w - 1 downto 0);
+ product_slv : std_logic_vector(c_product_w - 1 downto 0);
+ lost_data_flags_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+end record;
+
+constant c_reg_rst : t_reg := (
+ 0,
+ (others => c_mem_copi_rst),
+ (others => (others => '0')),
+ (others => '0'),
+ (others => '0'),
+ (others => (others => '0')),
+ c_dp_sosi_rst,
+ c_dp_sosi_rst,
+ 0,
+ (others => '0'),
+ c_mem_copi_rst,
+ (others => c_mem_cipo_rst),
+ (others => '0'),
+ (others => (others => '0')),
+ (others => '0'));
+
+ constant c_comb_rst : t_comb := (
+ c_dp_sosi_rst,
+ (others => '0'),
+ (others => '0'),
+ (others => '0'),
+ (others => c_dp_sosi_rst));
+
+ -- State registers for p_comb
+ signal r : t_reg;
+ signal nxt_r : t_reg;
+
+ -- Memoryless signals in p_comb (wires used as local variables)
+ signal dbg_wires : t_comb;
+
+ -- Structural signals (wires used to connect components and IO)
+ signal dp_done : std_logic;
+ signal dp_done_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal dp_copi : t_mem_copi;
+ signal dp_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0);
+
+ signal rd_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal rd_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0) := (others => c_mem_cipo_rst);
+
+ -- Pipeline registers
+ signal in_sosi_arr_p : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal rd_copi : t_mem_copi;
+ signal comb_out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+
+ -- Counter signals
+
+ signal replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
+ signal nxt_hold_replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
+ signal hold_replace_cnt_arr : t_slv_32_arr(g_nof_streams - 1 downto 0);
+
+ -- Debug signals
+ signal dbg_nof_streams : natural := g_nof_streams;
+ signal dbg_bsn_latency_max : natural := g_bsn_latency_max;
+ signal dbg_nof_aligners_max : natural := g_nof_aligners_max;
+ signal dbg_block_size : natural := g_block_size;
+ signal dbg_bsn_w : natural := g_bsn_w;
+ signal dbg_data_w : natural := g_data_w;
+ signal dbg_data_replacement_value : integer := g_data_replacement_value;
+ signal dbg_use_mm_output : boolean := g_use_mm_output;
+ signal dbg_pipeline_input : natural := g_pipeline_input;
+ signal dbg_rd_latency : natural := g_rd_latency;
+ signal dbg_c_buffer_nof_blocks : natural := c_buffer_nof_blocks;
+ signal dbg_c_product_w : natural := c_product_w;
begin
-- Output mm_sosi, also when g_use_mm_output = FALSE.
mm_sosi <= r.mm_sosi;
@@ -364,7 +367,7 @@ begin
-- . pass on input data from the buffer
w.out_sosi_arr := rd_sosi_arr; -- = v.fill_cipo_arr in streaming format, contains the
- -- input data from the buffer or replacement data
+ -- input data from the buffer or replacement data
if rd_sosi_arr(0).sop = '1' then
-- . at sop pass on input info from r.dp_sosi to all streams in out_sosi_arr
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.dp_sosi.sync, "SYNC");
@@ -383,8 +386,8 @@ begin
-- . until next sop pass on BSN to all streams, to ease view in wave window
w.out_sosi_arr := func_dp_stream_arr_set(w.out_sosi_arr, r.out_bsn, "BSN");
for I in 0 to g_nof_streams - 1 loop
- -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
- w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
+ -- . until next sop pass on channel bit 0 per stream, to ease view in wave window
+ w.out_sosi_arr(I).channel := RESIZE_DP_CHANNEL(r.out_channel_arr(I));
end loop;
end if;
@@ -410,20 +413,20 @@ begin
gen_data_buffer : for I in 0 to g_nof_streams - 1 generate
u_data_buffer : entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram_buf
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- wr_en => r.wr_copi_arr(I).wr,
- wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
- wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
- rd_en => rd_copi.rd,
- rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
- rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
- rd_val => rd_cipo_arr(I).rdval
- );
+ generic map (
+ g_ram => c_ram_buf
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ wr_en => r.wr_copi_arr(I).wr,
+ wr_adr => r.wr_copi_arr(I).address(c_ram_buf.adr_w - 1 downto 0),
+ wr_dat => r.wr_copi_arr(I).wrdata(c_ram_buf.dat_w - 1 downto 0),
+ rd_en => rd_copi.rd,
+ rd_adr => rd_copi.address(c_ram_buf.adr_w - 1 downto 0),
+ rd_dat => rd_cipo_arr(I).rddata(c_ram_buf.dat_w - 1 downto 0),
+ rd_val => rd_cipo_arr(I).rdval
+ );
end generate;
------------------------------------------------------------------------------
@@ -431,28 +434,29 @@ begin
------------------------------------------------------------------------------
gen_streaming_output : if not g_use_mm_output generate
+
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
- generic map (
- g_user_size => 1,
- g_data_size => 1,
- g_step_size => 1,
- g_nof_data => g_block_size,
- g_word_w => g_data_w,
- g_mm_rd_latency => g_rd_latency,
- g_reverse_word_order => false
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- start_pulse => r.mm_sosi.sop,
- start_address => 0,
- mm_done => dp_done_arr(I),
- mm_mosi => dp_copi_arr(I),
- mm_miso => nxt_r.fill_cipo_arr(I),
- out_sosi => rd_sosi_arr(I),
- out_siso => c_dp_siso_rdy
- );
+ generic map (
+ g_user_size => 1,
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => g_block_size,
+ g_word_w => g_data_w,
+ g_mm_rd_latency => g_rd_latency,
+ g_reverse_word_order => false
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ start_pulse => r.mm_sosi.sop,
+ start_address => 0,
+ mm_done => dp_done_arr(I),
+ mm_mosi => dp_copi_arr(I),
+ mm_miso => nxt_r.fill_cipo_arr(I),
+ out_sosi => rd_sosi_arr(I),
+ out_siso => c_dp_siso_rdy
+ );
end generate;
-- Use dp_copi_arr(0) to read same addresses in parallel for all streams
@@ -465,16 +469,16 @@ begin
------------------------------------------------------------------------------
gen_cnt_replace : for I in 0 to g_nof_streams - 1 generate
u_cnt_replace : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- cnt_clr => in_sosi_arr_p(0).sync,
- cnt_en => r.replace_cnt_en_arr(I),
- count => replace_cnt_arr(I)
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ cnt_clr => in_sosi_arr_p(0).sync,
+ cnt_en => r.replace_cnt_en_arr(I),
+ count => replace_cnt_arr(I)
+ );
end generate;
nxt_hold_replace_cnt_arr <= replace_cnt_arr when in_sosi_arr_p(0).sync = '1' else hold_replace_cnt_arr;
@@ -487,34 +491,34 @@ begin
-- . input streams
u_in_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_p
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_input -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_p
+ );
-- . read RAM
rd_copi <= nxt_r.rd_copi when g_rd_latency = 1 else r.rd_copi;
-- . output streams
u_out_sosi_arr_p : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => g_pipeline_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => comb_out_sosi_arr,
- -- ST source
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => g_pipeline_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => comb_out_sosi_arr,
+ -- ST source
+ src_out_arr => out_sosi_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index fe7e3680603b023a0f66d06a3ef9fe760958e123..9c680ce7fb382527768ba45c2cbeed5490ff61f4 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : Delay the input sync and BSN so they remain aligned to the data
-- path processing.
@@ -109,18 +109,18 @@ begin
-- Hold the in_sync during the block until the in_eop
u_hold_sync : entity common_lib.common_switch
- generic map (
- g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
- g_or_high => false, -- hold_sync goes high after in_sync
- g_and_low => false -- hold_sync goes low after in_eop
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_sync,
- switch_low => in_eop,
- out_level => hold_sync
- );
+ generic map (
+ g_priority_lo => false, -- in_sync has priority over in_eop, because they may occur simultaneously
+ g_or_high => false, -- hold_sync goes high after in_sync
+ g_and_low => false -- hold_sync goes low after in_eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_sync,
+ switch_low => in_eop,
+ out_level => hold_sync
+ );
-- Delay line for in_sync and in_bsn at block level
sync_dly(0) <= hold_sync;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index e32360c2085b7c1ce82fb1c07541d21957308aba..b114d40b1ded6cd599f03c5c2e68657ba2bd9389 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -41,10 +41,10 @@
-- valid remains active until an acknowledge by ready)
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor is
generic (
@@ -162,33 +162,33 @@ begin
nof_valid <= INCR_UVEC(cnt_valid, 1); -- +1 because the valid at the sync also counts
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -243,24 +243,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -287,50 +287,50 @@ begin
end generate;
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sop,
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sop,
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => valid,
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => valid,
+ count => cnt_valid
+ );
u_cnt_cycle : entity common_lib.common_counter
- generic map (
- g_width => c_word_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => in_sosi.sop,
- cnt_en => '1',
- count => cnt_cycle
- );
+ generic map (
+ g_width => c_word_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => in_sosi.sop,
+ cnt_en => '1',
+ count => cnt_cycle
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
index 1eab6bd1e082841b8170239f4c1d338304203622..279221fb48241aceeccbcc7853096429f67c4775 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
@@ -46,9 +46,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg is
generic (
@@ -83,14 +83,15 @@ end dp_bsn_monitor_reg;
architecture str of dp_bsn_monitor_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 4,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 9,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 4,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 9,
+ init_sl => '0');
- -- Registers in st_clk domain
- signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
+ -- Registers in st_clk domain
+ signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
begin
-- Register mapping
mon_reg( 3 - 1 downto 0) <= mon_sync_timeout & mon_ready_stable & mon_xon_stable;
@@ -103,28 +104,28 @@ begin
mon_reg(9 * c_word_w - 1 downto 8 * c_word_w) <= RESIZE_UVEC(mon_bsn_first_cycle_cnt, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
index 6f01dc61b677e6f289406c5eae62ebb6a52fb33c..7e195783f741b673ae609e442719fe5a8b668199 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
@@ -43,9 +43,9 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_monitor_reg_v2 is
generic (
@@ -79,14 +79,15 @@ end dp_bsn_monitor_reg_v2;
architecture str of dp_bsn_monitor_reg_v2 is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 7,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 7,
+ init_sl => '0');
- -- Registers in st_clk domain
- signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
+ -- Registers in st_clk domain
+ signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
begin
-- Register mapping
mon_reg( 3 - 1 downto 0) <= mon_sync_timeout & mon_ready_stable & mon_xon_stable;
@@ -98,28 +99,28 @@ begin
mon_reg(7 * c_word_w - 1 downto 6 * c_word_w) <= RESIZE_UVEC(mon_latency, c_word_w);
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1, -- mon_evt to mon_reg has latency 1 in dp_bsn_monitor
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => mon_evt,
- in_reg => mon_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => mon_evt,
+ in_reg => mon_reg, -- read only
+ out_reg => open -- no write
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index 339533f55ebd8422d8fff957ae7cfeee69b0e07c..f28745ed4491bf5506a76957fefa03bb79098fe2 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -40,10 +40,10 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_monitor_v2 is
generic (
@@ -173,33 +173,33 @@ begin
ref_sync_reg <= ref_sync when rising_edge(clk);
u_sync_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_sync_timeout_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => sync_timeout_n,
- count => sync_timeout_cnt
- );
+ generic map (
+ g_width => c_sync_timeout_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => sync_timeout_n,
+ count => sync_timeout_cnt
+ );
sync_timeout_n <= not nxt_sync_timeout;
nxt_sync_timeout <= '1' when unsigned(sync_timeout_cnt) >= g_sync_timeout else '0';
u_sync_timeout_revt : entity common_lib.common_evt
- generic map (
- g_evt_type => "RISING",
- g_out_invert => false,
- g_out_reg => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_sig => sync_timeout,
- out_evt => sync_timeout_revt
- );
+ generic map (
+ g_evt_type => "RISING",
+ g_out_invert => false,
+ g_out_reg => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sig => sync_timeout,
+ out_evt => sync_timeout_revt
+ );
p_clk : process(rst, clk)
begin
@@ -255,24 +255,24 @@ begin
nxt_xon <= in_siso.xon;
u_ready_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => ready,
- r_stable => ready_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => ready,
+ r_stable => ready_stable,
+ r_stable_ack => sync
+ );
u_xon_stable : entity common_lib.common_stable_monitor
- port map (
- rst => rst,
- clk => clk,
- -- MM
- r_in => xon,
- r_stable => xon_stable,
- r_stable_ack => sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- MM
+ r_in => xon,
+ r_stable => xon_stable,
+ r_stable_ack => sync
+ );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else i_current_bsn;
@@ -287,52 +287,52 @@ begin
nxt_bsn <= in_sosi.bsn(c_bsn_w - 1 downto 0) when in_sosi.sop = '1' else bsn; -- keep bsn as defined at sop
u_cnt_sop : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
- cnt_en => sop,
- load => TO_SVEC(1, c_cnt_sop_w),
- count => cnt_sop
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
+ cnt_en => sop,
+ load => TO_SVEC(1, c_cnt_sop_w),
+ count => cnt_sop
+ );
u_nof_err : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_sop_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => sync,
- cnt_en => err,
- count => cnt_err
- );
+ generic map (
+ g_width => c_cnt_sop_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => sync,
+ cnt_en => err,
+ count => cnt_err
+ );
u_cnt_valid : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_valid_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
- cnt_en => valid,
- load => TO_SVEC(1, c_cnt_valid_w),
- count => cnt_valid
- );
+ generic map (
+ g_width => c_cnt_valid_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
+ cnt_en => valid,
+ load => TO_SVEC(1, c_cnt_valid_w),
+ count => cnt_valid
+ );
u_cnt_latency : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_latency_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => ref_sync_reg,
- cnt_en => '1',
- count => cnt_latency
- );
+ generic map (
+ g_width => c_cnt_latency_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => ref_sync_reg,
+ cnt_en => '1',
+ count => cnt_latency
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
index b4c524a869d42b2230682245fb7aa476432c610d..b12c2339fd25816c7e4ee9a6d6272d1ac58aa7b6 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author: Eric Kooistra, 17 nov 2017
-- Purpose:
@@ -79,19 +79,19 @@ begin
-- Create block sync from snk_in.sync, this blk_sync is active during entire first sop-eop block of sync interval
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => blk_sync
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => false, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sync, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => blk_sync
+ );
-- Use stored global BSN at sync and add local BSN to restore the global BSN for every next sop
bsn_restored <= snk_in.bsn when blk_sync = '1' else ADD_UVEC(bsn_at_sync, snk_in.bsn, g_bsn_w);
@@ -100,17 +100,17 @@ begin
-- Add pipeline to ensure timing closure for the restored BSN summation
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in_restored,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in_restored,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index b095b03d52a965135e7aac88a20526843d3bd7a1..b492fd83fcdc82b9ce3fa3288e8f2a8ff11445d5 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : Schedule an output trigger based on the Data Path BSN[]
-- Description:
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
index 36d2d553ae37566374c310a39e4f1f0c651429fa..8cfad67789b4b7179b86965a9ace13ad4c3e11bc 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
@@ -32,9 +32,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_scheduler_reg is
generic (
@@ -61,17 +61,18 @@ architecture rtl of dp_bsn_scheduler_reg is
constant c_bsn_w : natural := st_current_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
-
- -- Registers in mm_clk domain
- signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
- signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- signal mm_scheduled_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
- signal mm_scheduled_bsn_wr : std_logic;
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
+
+ -- Registers in mm_clk domain
+ signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
+ signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ signal mm_scheduled_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
+ signal mm_scheduled_bsn_wr : std_logic;
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -100,7 +101,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write scheduled BSN
+ -- Write scheduled BSN
when 0 =>
mm_scheduled_bsn(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 1 =>
@@ -110,12 +111,12 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read current BSN
+ -- Read current BSN
when 0 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn(31 downto 0);
mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
@@ -163,31 +164,30 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_scheduled_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_scheduled_bsn_wr, -- use wr of mm_scheduled_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_scheduled_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_scheduled_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index b1909332630be2e4e9bc92977b5009de29141226..a186032cb0b89fccdc89a75cd92b98e47d283ce9 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -33,10 +33,10 @@
-- has to disable (dp_on='0') the data path before restarting it.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
index e6310abb8fd4fe3e288e0643536d7321e766a073..6220fb87f3add4bb25b6b4f490eafd422ed8a429 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
@@ -39,9 +39,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg is
generic (
@@ -73,27 +73,28 @@ architecture rtl of dp_bsn_source_reg is
constant c_bsn_w : natural := st_init_bsn'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**2,
+ init_sl => '0');
- -- Registers in mm_clk domain
- signal mm_on : std_logic;
- signal mm_on_pps : std_logic;
- signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
- signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
- signal mm_on_status : std_logic;
+ -- Registers in mm_clk domain
+ signal mm_on : std_logic;
+ signal mm_on_pps : std_logic;
+ signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
+ signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
+ signal mm_on_status : std_logic;
- signal mm_nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
+ signal mm_nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
- signal mm_init_bsn : std_logic_vector(c_longword_w - 1 downto 0);
- signal mm_init_bsn_wr : std_logic;
- signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
- signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+ signal mm_init_bsn : std_logic_vector(c_longword_w - 1 downto 0);
+ signal mm_init_bsn_wr : std_logic;
+ signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
+ signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
- -- Registers in st_clk domain
+ -- Registers in st_clk domain
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -125,14 +126,14 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_on <= sla_in.wrdata(0);
mm_on_pps <= sla_in.wrdata(1);
when 1 =>
mm_nof_block_per_sync <= sla_in.wrdata(31 downto 0);
- -- Write init BSN
+ -- Write init BSN
when 2 =>
mm_init_bsn(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 3 =>
@@ -142,19 +143,19 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(0) <= mm_on_status;
sla_out.rddata(1) <= mm_on_pps;
when 1 =>
sla_out.rddata(31 downto 0) <= mm_nof_block_per_sync;
- -- Read current BSN
+ -- Read current BSN
when 2 =>
sla_out.rddata(31 downto 0) <= mm_current_bsn(31 downto 0);
mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
@@ -207,16 +208,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -225,56 +226,55 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_block_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_block_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_block_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_block_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
- in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_init_bsn,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_init_bsn_wr, -- use wr of mm_init_bsn high part for in_new to ensure proper transfer of double word
+ in_dat => mm_init_bsn(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_init_bsn,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
end generate; -- gen_cross
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 71eab87eda14396b01034520b7417afaf2385af0..1d25404bee65c6e92cc84b753e074bfced29a950 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -40,9 +40,9 @@
-- ====================================================================================
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_bsn_source_reg_v2 is
generic (
@@ -76,30 +76,31 @@ architecture rtl of dp_bsn_source_reg_v2 is
constant c_bsn_time_offset_w : natural := st_bsn_time_offset'length;
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 3,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**3,
- init_sl => '0');
-
- -- Registers in mm_clk domain
- signal mm_on : std_logic;
- signal mm_on_pps : std_logic;
- signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
- signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
- signal mm_on_status : std_logic;
-
- signal mm_nof_clk_per_sync : std_logic_vector(c_word_w - 1 downto 0);
-
- signal mm_bsn_init : std_logic_vector(c_longword_w - 1 downto 0);
- signal mm_bsn_init_wr : std_logic;
- signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
- signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
-
- signal mm_bsn_time_offset : std_logic_vector(c_bsn_time_offset_w - 1 downto 0) := (others => '0');
- signal mm_bsn_time_offset_wr : std_logic;
-
- -- Registers in st_clk domain
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 3,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2**3,
+ init_sl => '0');
+
+ -- Registers in mm_clk domain
+ signal mm_on : std_logic;
+ signal mm_on_pps : std_logic;
+ signal mm_on_ctrl : std_logic_vector(1 downto 0); -- = mm_on_pps & mm_on
+ signal st_on_ctrl : std_logic_vector(1 downto 0); -- = st_on_pps & st_on
+ signal mm_on_status : std_logic;
+
+ signal mm_nof_clk_per_sync : std_logic_vector(c_word_w - 1 downto 0);
+
+ signal mm_bsn_init : std_logic_vector(c_longword_w - 1 downto 0);
+ signal mm_bsn_init_wr : std_logic;
+ signal mm_current_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
+ signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
+
+ signal mm_bsn_time_offset : std_logic_vector(c_bsn_time_offset_w - 1 downto 0) := (others => '0');
+ signal mm_bsn_time_offset_wr : std_logic;
+
+ -- Registers in st_clk domain
begin
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
@@ -134,21 +135,21 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_on <= sla_in.wrdata(0);
mm_on_pps <= sla_in.wrdata(1);
when 1 =>
mm_nof_clk_per_sync <= sla_in.wrdata(31 downto 0);
- -- Write init BSN
+ -- Write init BSN
when 2 =>
mm_bsn_init(31 downto 0) <= sla_in.wrdata(31 downto 0);
when 3 =>
mm_bsn_init(63 downto 32) <= sla_in.wrdata(31 downto 0);
mm_bsn_init_wr <= '1';
- -- write bsn_time_offset
+ -- write bsn_time_offset
when 4 =>
mm_bsn_time_offset <= sla_in.wrdata(c_bsn_time_offset_w - 1 downto 0);
mm_bsn_time_offset_wr <= '1';
@@ -156,26 +157,26 @@ begin
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(0) <= mm_on_status;
sla_out.rddata(1) <= mm_on_pps;
when 1 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_nof_clk_per_sync;
- -- Read current BSN
+ -- Read current BSN
when 2 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn(31 downto 0);
mm_current_bsn_hi <= mm_current_bsn(63 downto 32); -- first read low part and preserve high part
when 3 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_current_bsn_hi; -- then read preserved high part
- -- Read current bsn_time_offset
+ -- Read current bsn_time_offset
when 4 =>
sla_out.rddata(c_word_w - 1 downto 0) <= RESIZE_UVEC(mm_bsn_time_offset, c_word_w);
@@ -231,16 +232,16 @@ begin
gen_cross : if g_cross_clock_domain = true generate
-- Block sync registers
u_dp_on_ctrl : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_on_ctrl,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_on_ctrl,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_on_ctrl,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_on_ctrl,
+ out_new => open
+ );
mm_on_ctrl(0) <= mm_on;
mm_on_ctrl(1) <= mm_on_pps;
@@ -249,70 +250,69 @@ begin
st_on_pps <= st_on_ctrl(1);
u_mm_on_status : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- din => st_on_status,
- dout => mm_on_status
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => st_on_status,
+ dout => mm_on_status
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_nof_block_per_sync : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_nof_clk_per_sync,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_nof_clk_per_sync,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_nof_clk_per_sync,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_nof_clk_per_sync,
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_init : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
- in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_init,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_init_wr, -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ in_dat => mm_bsn_init(c_bsn_w - 1 downto 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_init,
+ out_new => open
+ );
-- thanks to mm_current_bsn_hi the double word can be read reliably
u_current_bsn : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => st_rst,
- in_clk => st_clk,
- in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
- in_dat => st_current_bsn,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => mm_rst,
- out_clk => mm_clk,
- out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
- out_new => open
- );
+ port map (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1', -- could use t_dp_sosi sop here to indicate in_new, but using default '1' is fine too
+ in_dat => st_current_bsn,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
+ out_new => open
+ );
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_bsn_time_offset : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_new => mm_bsn_time_offset_wr,
- in_dat => mm_bsn_time_offset,
- in_done => OPEN, -- pulses when no more pending in_new
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => st_bsn_time_offset,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_time_offset_wr,
+ in_dat => mm_bsn_time_offset,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_time_offset,
+ out_new => open
+ );
end generate; -- gen_cross
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index 1d2ebf0fbbdcdbe4107083f2e8c8dbfafd8c45a2..18889ce1fea7e3251b8eae532dd714d752aaabee 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -55,10 +55,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_source_v2 is
generic (
@@ -125,8 +125,8 @@ begin
bs_new_interval <= i_bs_new_interval;
p_state : process(sync, sync_size_cnt, nof_clk_per_sync,
- state, i_src_out, block_size_cnt, bsn_time_offset_cnt,
- bsn_init, dp_on, dp_on_pps, pps, bsn_time_offset, prev_state)
+ state, i_src_out, block_size_cnt, bsn_time_offset_cnt,
+ bsn_init, dp_on, dp_on_pps, pps, bsn_time_offset, prev_state)
begin
-- Maintain sync_size_cnt for nof_clk_per_sync
-- . nof_clk_per_sync is the number of clk per pps interval and the
@@ -185,9 +185,9 @@ begin
nxt_bsn_time_offset_cnt <= INCR_UVEC(bsn_time_offset_cnt, 1);
end if;
- -- using separate states s_dp_on_sop and s_dp_on_eop instead of only
- -- s_dp_on state and block_size_cnt, cause that g_block_size must be
- -- >= 3, but that is fine.
+ -- using separate states s_dp_on_sop and s_dp_on_eop instead of only
+ -- s_dp_on state and block_size_cnt, cause that g_block_size must be
+ -- >= 3, but that is fine.
when s_dp_on_sop =>
-- Start of block
nxt_src_out.sop <= '1';
@@ -236,7 +236,7 @@ begin
i_bs_new_interval <= '1' when i_bs_restart = '1' else
'0' when i_src_out.sync = '1' else
- reg_bs_new_interval;
+ reg_bs_new_interval;
p_clk : process(rst, clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index f92809dc5488820c280468926a5ee741233aee97..520a3ea35abdb6c5c38ce01b271e099de9912664 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,10 +111,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_bsn_sync_scheduler is
generic (
@@ -424,17 +424,17 @@ begin
-- Pipeline output to avoid timing closure problems due to use of output_enable
-----------------------------------------------------------------------------
u_out_sosi : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => output_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => output_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
gen_pipe_out_start : if g_pipeline = 1 generate
out_start <= output_start when rising_edge(clk);
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index 0326cf21388a40649729228785f7f2148441ed95..b1f2d4561721a3dc8e8c7bcee770cce76ca26021 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -26,15 +26,15 @@
-- snk_in.eop of that block.
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-use easics_lib.PCK_CRC8_D8.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC28_D28.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC8_D8.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC28_D28.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D64.all;
entity dp_calculate_crc is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index 046cd7f80aff6a37fff1dbfddd8e936d75e57bde..5e0ca91110602b67ee0a5da1b9f07805a680db55 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -37,7 +37,7 @@ entity dp_complex_add is
g_technology : natural := c_tech_select_default;
g_nof_inputs : natural;
g_data_w : natural -- Complex input data width
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -74,33 +74,33 @@ begin
-- One adder tree for the real part
u_adder_tree_re : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_re_in_dat,
- sum => common_adder_tree_re_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_re_in_dat,
+ sum => common_adder_tree_re_sum
+ );
-- One adder tree for the imaginary part
u_adder_tree_im : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "SIGNED",
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_inputs,
- g_dat_w => g_data_w,
- g_sum_w => c_common_adder_tree_sum_w
- )
- port map (
- clk => clk,
- in_dat => common_adder_tree_im_in_dat,
- sum => common_adder_tree_im_sum
- );
+ generic map (
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_inputs,
+ g_dat_w => g_data_w,
+ g_sum_w => c_common_adder_tree_sum_w
+ )
+ port map (
+ clk => clk,
+ in_dat => common_adder_tree_im_in_dat,
+ sum => common_adder_tree_im_sum
+ );
p_src_out : process(snk_in_pipe, common_adder_tree_re_sum, common_adder_tree_im_sum)
begin
@@ -117,15 +117,15 @@ begin
snk_in <= snk_in_arr(0);
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_adder_tree
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_pipe
- );
+ generic map (
+ g_pipeline => c_pipeline_adder_tree
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_pipe
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index b41f0cfdf0a6008a676933865c476b5c2efb8e5e..4a59d2364f391e555ddc81b5c321aa1414847968 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -43,7 +43,7 @@ entity dp_complex_mult is
g_conjugate_b : boolean := false; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
g_data_w : natural; -- Input data width. Output data width = 2*input data width.
g_variant : string := "IP"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -65,27 +65,27 @@ begin
-----------------------------------------------------------------------------
gen_common_complex_mult : for i in 0 to g_nof_multipliers - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => g_variant,
- g_in_a_w => g_data_w,
- g_in_b_w => g_data_w,
- g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
- g_conjugate_b => g_conjugate_b
- )
- port map (
- clk => clk,
- clken => '1',
- rst => '0',
- in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
- in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
- in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
- in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
- in_val => snk_in_2arr_2(i)(0).valid,
- out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
- out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
- out_val => common_complex_mult_src_out_arr(i).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => g_variant,
+ g_in_a_w => g_data_w,
+ g_in_b_w => g_data_w,
+ g_out_p_w => 2 * g_data_w, -- default use g_out_p_w = g_in_a_w+g_in_b_w
+ g_conjugate_b => g_conjugate_b
+ )
+ port map (
+ clk => clk,
+ clken => '1',
+ rst => '0',
+ in_ar => snk_in_2arr_2(i)(0).re(g_data_w - 1 downto 0),
+ in_ai => snk_in_2arr_2(i)(0).im(g_data_w - 1 downto 0),
+ in_br => snk_in_2arr_2(i)(1).re(g_data_w - 1 downto 0),
+ in_bi => snk_in_2arr_2(i)(1).im(g_data_w - 1 downto 0),
+ in_val => snk_in_2arr_2(i)(0).valid,
+ out_pr => common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0),
+ out_pi => common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0),
+ out_val => common_complex_mult_src_out_arr(i).valid
+ );
src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).re(2 * g_data_w - 1 downto 0));
src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).im(2 * g_data_w - 1 downto 0));
@@ -96,14 +96,14 @@ begin
-- Forward the input sync with the correct latency
-----------------------------------------------------------------------------
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => c_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_dat => snk_in_2arr_2(0)(0).sync,
- out_dat => src_out_arr(0).sync
- );
+ in_dat => snk_in_2arr_2(0)(0).sync,
+ out_dat => src_out_arr(0).sync
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 2fafe0a210809bd5849bd512b51dc11ff4a022de..9888fd2819513c464ce4292310486505f7409b28 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -24,21 +24,21 @@
-- Description:
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_components_pkg is
constant c_dp_clk_MHz : natural := 200;
- constant c_dp_sync_timeout : natural := c_dp_clk_MHz * 10**6 + c_dp_clk_MHz * 10**5; -- 10% margin for nominal 1 s
+ constant c_dp_sync_timeout : natural := c_dp_clk_MHz * 10 ** 6 + c_dp_clk_MHz * 10 ** 5; -- 10% margin for nominal 1 s
constant c_dp_bsn_monitor_v2_reg_adr_w : natural := ceil_log2(7); -- = 3
- constant c_dp_bsn_monitor_v2_reg_adr_span : natural := 2**c_dp_bsn_monitor_v2_reg_adr_w; -- = 8
+ constant c_dp_bsn_monitor_v2_reg_adr_span : natural := 2 ** c_dp_bsn_monitor_v2_reg_adr_w; -- = 8
constant c_dp_strobe_total_count_reg_nof_words : natural := 15 * 2 + 2; -- = 32
constant c_dp_strobe_total_count_reg_adr_w : natural := ceil_log2(c_dp_strobe_total_count_reg_nof_words); -- = 5
- constant c_dp_strobe_total_count_reg_adr_span : natural := 2**c_dp_strobe_total_count_reg_adr_w; -- = 32
- constant c_dp_strobe_total_count_reg_nof_counts_max : natural := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1; -- = 15
+ constant c_dp_strobe_total_count_reg_adr_span : natural := 2 ** c_dp_strobe_total_count_reg_adr_w; -- = 32
+ constant c_dp_strobe_total_count_reg_nof_counts_max : natural := 2 ** c_dp_strobe_total_count_reg_adr_w / 2 - 1; -- = 15
constant c_dp_strobe_total_count_reg_clear_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2; -- after counters in REGMAP
constant c_dp_strobe_total_count_reg_flush_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2 + 1;
end dp_components_pkg;
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index e2d6a58f0de31b72bf1c5cebac263981e076a05b..1a57d71881370866c34d749efda19e90fbacd8ef 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Concat two frames into one frame.
@@ -153,18 +153,18 @@ begin
gen_input : for I in c_head to c_tail generate
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => hold_src_in_arr(I),
- next_src_out => next_src_out_arr(I),
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_buf_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => hold_src_in_arr(I),
+ next_src_out => next_src_out_arr(I),
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_buf_arr(I)
+ );
end generate;
-- default ready for hold input when ready for sink input or also ready for hold input when the eop is there
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index c115e41e883e85637f1ea7bc9eac1a4fbb1e4d4d..ac8949dd5cb05e3476ad0a98e6e54e59f07278f2 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -36,13 +36,13 @@
-- the header and data are an integer number of g_data_w.
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_concat_field_blk is
generic (
@@ -98,6 +98,7 @@ begin
-- Create header block & concatenate header to offload stream.
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
+
p_wire_valid : process(snk_in_arr, hdr_fields_in_arr)
begin
for i in 0 to g_nof_streams - 1 loop
@@ -122,31 +123,31 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
end generate;
@@ -157,34 +158,34 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index 9748348ee2a86f2031e137f3ef2834fb75fdf7eb..3d0302fc45ed631dedce1c3e12bf392535731500 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -63,10 +63,10 @@
-- Any other useage will break counters >= stage i
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter is
generic (
@@ -108,55 +108,55 @@ begin
-- dp_counter_func
------------------------------------------------------------------------------
u_dp_counter_func : entity work.dp_counter_func
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => c_range_start,
- g_range_stop => c_range_stop,
- g_range_step => c_range_step
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => snk_in.valid,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => dp_counter_func_src_out_arr
- );
-
- ------------------------------------------------------------------------------
- -- dp_pipeline
- ------------------------------------------------------------------------------
- gen_dp_pipeline : if c_use_dp_pipeline = true generate
- u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
- g_pipeline => g_pipeline_src_out
+ g_nof_counters => g_nof_counters,
+ g_range_start => c_range_start,
+ g_range_stop => c_range_stop,
+ g_range_step => c_range_step
)
port map (
- clk => clk,
- rst => rst,
+ rst => rst,
+ clk => clk,
- snk_in => snk_in,
- snk_out => snk_out,
+ count_en => snk_in.valid,
- src_out => src_out,
- src_in => src_in
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => dp_counter_func_src_out_arr
);
- gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ ------------------------------------------------------------------------------
+ -- dp_pipeline
+ ------------------------------------------------------------------------------
+ gen_dp_pipeline : if c_use_dp_pipeline = true generate
+ u_dp_pipeline_snk_in : entity work.dp_pipeline
generic map (
g_pipeline => g_pipeline_src_out
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_count_src_out_arr : entity work.dp_pipeline
+ generic map (
+ g_pipeline => g_pipeline_src_out
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
@@ -165,34 +165,34 @@ begin
------------------------------------------------------------------------------
gen_dp_pipeline_ready : if c_use_dp_pipeline_ready = true generate
u_dp_pipeline_ready : entity work.dp_pipeline_ready
- generic map (
- g_in_latency => 1
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in
- );
-
- gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
- u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
generic map (
- g_in_latency => 1
+ g_in_latency => 1
)
port map (
- clk => clk,
- rst => rst,
+ clk => clk,
+ rst => rst,
- snk_in => dp_counter_func_src_out_arr(i),
+ snk_in => snk_in,
+ snk_out => snk_out,
- src_out => count_src_out_arr(i),
- src_in => src_in
+ src_out => src_out,
+ src_in => src_in
);
+
+ gen_dp_pipeline_ready_count_src_out_arr : for i in 0 to g_nof_counters - 1 generate
+ u_dp_pipeline_ready_count_src_out_arr : entity work.dp_pipeline_ready
+ generic map (
+ g_in_latency => 1
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => dp_counter_func_src_out_arr(i),
+
+ src_out => count_src_out_arr(i),
+ src_in => src_in
+ );
end generate;
end generate;
@@ -205,5 +205,4 @@ begin
count_src_out_arr <= dp_counter_func_src_out_arr;
end generate;
-
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 89431450ddc9d374bc5029dfa76a666ae1b79374..dfd4b4e2d774ece97d14efe6b788f89ddae6ef0a 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -38,10 +38,10 @@
-- logic when minimum/maximum values per dimension are reached.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func is
generic (
@@ -82,16 +82,16 @@ begin
-- Counter control inputs
-------------------------------------------------------------------------------
gen_dp_counter_func_single_input : for i in 0 to g_nof_counters - 1 generate
+
gen_c0 : if i = 0 generate
count_en_arr(i) <= count_en;
check_max_arr(i) <= count_en;
end generate;
gen_c1_upwards : if i > 0 generate
- count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
- check_max_arr(i) <= count_max_arr(i - 1);
+ count_en_arr(i) <= count_init_arr(i - 1) or count_min_arr(i - 1);
+ check_max_arr(i) <= count_max_arr(i - 1);
end generate;
-
end generate;
--------------------------------------------------------------------------------
@@ -99,24 +99,24 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single : for i in 0 to g_nof_counters - 1 generate
u_dp_counter_func_single : entity work.dp_counter_func_single
- generic map (
- g_range_start => c_range_start(i),
- g_range_stop => c_range_stop(i),
- g_range_step => c_range_step(i)
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_range_start => c_range_start(i),
+ g_range_stop => c_range_stop(i),
+ g_range_step => c_range_step(i)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- count_en => count_en_arr(i),
- check_max => check_max_arr(i),
- count_offset => count_offset_in_arr(i),
+ count_en => count_en_arr(i),
+ check_max => check_max_arr(i),
+ count_offset => count_offset_in_arr(i),
- count => count_arr(i),
- count_init => count_init_arr(i),
- count_min => count_min_arr(i),
- count_max => count_max_arr(i)
- );
+ count => count_arr(i),
+ count_init => count_init_arr(i),
+ count_min => count_min_arr(i),
+ count_max => count_max_arr(i)
+ );
end generate;
--------------------------------------------------------------------------------
@@ -124,11 +124,10 @@ begin
-------------------------------------------------------------------------------
gen_dp_counter_func_single_output : for i in 0 to g_nof_counters - 1 generate
count_src_out_arr(i).sync <= '0'; -- not used, force to '0' to avoid toggling between '0' and 'X' in Wave window
- -- when sync is passed on through other components
+ -- when sync is passed on through other components
count_src_out_arr(i).sop <= count_min_arr(i);
count_src_out_arr(i).eop <= count_max_arr(i);
count_src_out_arr(i).valid <= count_en;
count_src_out_arr(i).data <= RESIZE_DP_DATA(count_arr(i));
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index 01c3d94c4a083a11f3794596d02ae05a34bf6f91..cf45e5aa1b70064e078ef290eb88e1d4a950957f 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -29,10 +29,10 @@
-- . Not for standalone use; part of dp_counter_func.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_counter_func_single is -- FIXME move this to common
generic (
@@ -56,7 +56,7 @@ entity dp_counter_func_single is -- FIXME move this to common
end dp_counter_func_single;
architecture rtl of dp_counter_func_single is
- -- The user defines the counters like a Python range(start,stop,step) in which the stop value
+ -- The user defines the counters like a Python range(start,stop,step) in which the stop value
-- is never actually reached. Calculate the actual maximum values here.
-- . Example:
-- . range(0,4,2) = [0, 2]
@@ -98,7 +98,7 @@ begin
v.count := TO_UVEC(g_range_start + count_offset, c_count_w);
v.count_min := '1';
v.count_init := '1';
- -- keep counting
+ -- keep counting
else
v.count := INCR_UVEC(r.count, g_range_step);
if c_count_max > 0 and check_max = '1' and r.count = TO_UVEC(c_count_max - g_range_step, c_count_w) then -- count max almost reached
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index e652bad0f33602eaf96897dd7ae3742d9a380e17..d05fb85cfa79179a01548ec091a4a661a443d969 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -84,27 +84,28 @@ begin
common_deinterleave_in_val <= snk_in.valid;
u_deinterleave : entity common_lib.common_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size => g_block_size_int,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_deinterleave_in_dat,
- in_val => common_deinterleave_in_val,
-
- out_dat => common_deinterleave_out_dat,
- out_val => common_deinterleave_out_val
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size => g_block_size_int,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_deinterleave_in_dat,
+ in_val => common_deinterleave_in_val,
+
+ out_dat => common_deinterleave_out_dat,
+ out_val => common_deinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Use complex fields if required
-----------------------------------------------------------------------------
gen_wires_out : for i in 0 to g_nof_out - 1 generate
+
gen_sosi_dat_out: if g_use_complex = false generate
common_deinterleave_src_out_arr(i).data(g_dat_w - 1 downto 0) <= common_deinterleave_out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w);
end generate;
@@ -121,21 +122,22 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_use_ctrl = true generate
+
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_deinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_deinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -147,27 +149,27 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
align_out : if g_use_sync_bsn = true generate
+
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in, -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in, -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
no_align_out : if g_use_sync_bsn = false generate
src_out_arr <= dp_block_gen_src_out_arr;
end generate;
-
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index aea3de86d75eeb404cded71d73fb6ba2e9b20b91..fea9d2c721ed130307e149d2a5c521abcd64bc81 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra
@@ -149,18 +149,18 @@ begin
snk_out <= out_siso_arr(0); -- all out_siso_arr have the same siso, so wire output 0
u_pipeline_outputs : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_outputs,
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out_arr => out_siso_arr,
- snk_in_arr => out_sosi_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_outputs,
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out_arr => out_siso_arr,
+ snk_in_arr => out_sosi_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index f70721856d148527ca0ca2e041dab4a0107c098d..e70d7cb818dacfc02c0e8ebb3cff1cc0f456d289 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- De-multiplex frames from one input stream with one or more channels onto
@@ -116,6 +116,7 @@ begin
-- Use eop to select next output.
gen_mode_1 : if g_mode = 1 generate
+
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -134,6 +135,7 @@ begin
-- Use external MM control input to select the output
gen_mode_2 : if g_mode = 2 generate
+
no_pkt_ctrl: if g_sel_ctrl_pkt = false generate
-- Select new output immediately (registered: one cycle after sel_ctrl change)
p_clk : process(rst, clk)
@@ -165,8 +167,8 @@ begin
else
output_select <= g_nof_output - 1 - sel_ctrl;
end if;
- -- User might need this status port to indicate if/when the output has actually been switched
- sel_stat <= output_select;
+ -- User might need this status port to indicate if/when the output has actually been switched
+ sel_stat <= output_select;
end if;
end process;
@@ -182,18 +184,17 @@ begin
-- The dp_packet_detect component simply asserts its output from SOP to EOP
u_dp_packet_detect : entity work.dp_packet_detect
- generic map (
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- sosi => adapt_sosi,
- siso => adapt_siso, -- We're using the adapted sink_in with RL=0
- pkt_det => pkt_det
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ sosi => adapt_sosi,
+ siso => adapt_siso, -- We're using the adapted sink_in with RL=0
+ pkt_det => pkt_det
+ );
end generate;
-
end generate;
------------------------------------------------------------------------------
@@ -235,20 +236,20 @@ begin
gen_individual : if g_combined = false and g_nof_output > 1 generate
-- Adapt input to RL = 0 to have show-ahead
u_rl_0 : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => adapt_siso,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => adapt_siso,
+ src_out => adapt_sosi
+ );
sel_channel <= adapt_sosi.channel;
sel_eop <= adapt_sosi.eop and adapt_siso.ready; -- RL = 0, so eop is only valid when the ready acknowledges it
@@ -282,20 +283,20 @@ begin
-- Back to output RL = 1
gen_rl_1 : for I in 0 to g_nof_output - 1 generate
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => prev_src_in_arr(I),
- snk_in => pend_src_out_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => prev_src_in_arr(I),
+ snk_in => pend_src_out_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 4165fd637055cd2ac3a3fb7b73ad9388147200f9..613748759eb72c84613fcba2cec7c3a6f0c3fcd9 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -76,11 +76,11 @@
-- gets lost or an input is not used.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_distribute is
generic (
@@ -155,35 +155,36 @@ begin
end generate;
gen_fifo : if g_use_fifo = true generate
+
gen_input : for I in 0 to g_nof_input - 1 generate
u_fifo : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => in_siso_arr(I),
- src_out => in_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => in_siso_arr(I),
+ src_out => in_sosi_arr(I)
+ );
end generate;
end generate;
@@ -193,22 +194,23 @@ begin
end generate;
gen_dec : if g_decode_channel_lo = true generate
+
gen_i : for I in 0 to g_nof_input - 1 generate
u_dec : entity work.dp_packet_dec_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => in_siso_arr(I),
- snk_in => in_sosi_arr(I),
- -- ST source
- src_in => rx_siso_arr(I),
- src_out => rx_sosi_arr(I)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => in_siso_arr(I),
+ snk_in => in_sosi_arr(I),
+ -- ST source
+ src_in => rx_siso_arr(I),
+ src_out => rx_sosi_arr(I)
+ );
end generate;
end generate;
@@ -218,28 +220,30 @@ begin
end generate;
gen_transpose : if g_nof_input /= g_nof_output or g_transpose = true generate
+
gen_demux : for I in 0 to g_nof_input - 1 generate
u_demux : entity work.dp_demux
- generic map (
- g_mode => c_demux_mode,
- g_nof_output => g_nof_output,
- g_remove_channel_lo => c_demux_remove_channel_lo,
- g_combined => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => rx_siso_arr(I),
- snk_in => rx_sosi_arr(I),
- -- ST source
- src_in_arr => demux_siso_2arr(I),
- src_out_arr => demux_sosi_2arr(I)
- );
+ generic map (
+ g_mode => c_demux_mode,
+ g_nof_output => g_nof_output,
+ g_remove_channel_lo => c_demux_remove_channel_lo,
+ g_combined => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => rx_siso_arr(I),
+ snk_in => rx_sosi_arr(I),
+ -- ST source
+ src_in_arr => demux_siso_2arr(I),
+ src_out_arr => demux_sosi_2arr(I)
+ );
end generate;
-- Rewire to distribute
gen_in : for I in 0 to g_nof_input - 1 generate
+
gen_out : for J in 0 to g_nof_output - 1 generate
demux_siso_2arr(I)(J) <= mux_siso_2arr(J)(I);
mux_sosi_2arr(J)(I) <= demux_sosi_2arr(I)(J);
@@ -248,26 +252,26 @@ begin
gen_mux : for J in 0 to g_nof_output - 1 generate
u_mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mux_mode,
- g_nof_input => g_nof_input,
- g_append_channel_lo => c_mux_append_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_2arr(J),
- snk_in_arr => mux_sosi_2arr(J),
- -- ST source
- src_in => tx_siso_arr(J),
- src_out => tx_sosi_arr(J)
- );
+ generic map (
+ -- MUX
+ g_mode => c_mux_mode,
+ g_nof_input => g_nof_input,
+ g_append_channel_lo => c_mux_append_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, g_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => mux_siso_2arr(J),
+ snk_in_arr => mux_sosi_2arr(J),
+ -- ST source
+ src_in => tx_siso_arr(J),
+ src_out => tx_sosi_arr(J)
+ );
end generate;
end generate;
@@ -277,20 +281,21 @@ begin
end generate;
gen_enc : if g_encode_channel_lo = true generate
+
gen_j : for J in 0 to g_nof_output - 1 generate
u_enc : entity work.dp_packet_enc_channel_lo
- generic map (
- g_data_w => g_data_w,
- g_channel_lo => c_link_channel_lo
- )
- port map (
- -- ST sinks
- snk_out => tx_siso_arr(J),
- snk_in => tx_sosi_arr(J),
- -- ST source
- src_in => src_in_arr(J),
- src_out => src_out_arr(J)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_channel_lo => c_link_channel_lo
+ )
+ port map (
+ -- ST sinks
+ snk_out => tx_siso_arr(J),
+ snk_in => tx_sosi_arr(J),
+ -- ST source
+ src_in => src_in_arr(J),
+ src_out => src_out_arr(J)
+ );
end generate;
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 33b96ad56573de75c40d0db3be6ade34afc6d8a7..c8030b00b28e4751ec513faa6f7aad5fcf751367 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -23,10 +23,10 @@
-- Provide packetized dummy values when sink is ready
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_dummy_source is
generic (
@@ -38,7 +38,7 @@ entity dp_dummy_source is
g_dummy_empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0) := x"DD";
g_dummy_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := x"DDDDDDDD";
g_dummy_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := x"DDDDDDDD"
- );
+ );
port (
rst : in std_logic;
clk : in std_logic;
@@ -67,16 +67,16 @@ begin
src_out.err <= c_dp_sosi_dummy.err;
u_dp_block_gen: entity work.dp_block_gen
- generic map (
- g_nof_data => g_dummy_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_nof_data => g_dummy_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- src_in => src_in,
- src_out => block_sosi,
+ src_in => src_in,
+ src_out => block_sosi,
- en => '1'
- );
+ en => '1'
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
index c32b6480ea4253445887590078cb47b52bc63fbd..cef0bc5d553462a4de7e80a0487ffce11f5f278c 100644
--- a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
+++ b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Purpose:
-- The extended eop output can be used to gate valid eop related stream info
@@ -45,13 +45,13 @@ architecture rtl of dp_eop_extend is
signal extend : std_logic;
begin
u_extend : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => in_eop,
- switch_low => in_sop,
- out_level => extend
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => in_eop,
+ switch_low => in_sop,
+ out_level => extend
+ );
eop_extend <= (in_eop or extend) and not in_sop;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_example_dut.vhd b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
index 5492efb3861b530acbbba5423b04ea2eace9526c..2c3a31f3ab2d5408e02d6cce41515587fc210529 100644
--- a/libraries/base/dp/src/vhdl/dp_example_dut.vhd
+++ b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
@@ -163,9 +163,9 @@
-- the test bench.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_example_dut is
port (
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index abab9714879e983e963cad92c815c9542e56e933..70497c7174f62951f649efc820e0e060bf7d6e5d 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Source a DP data block of which the contents are read from snk_in.data when snk_in.valid = '1'
@@ -109,26 +109,26 @@ entity dp_field_blk is
-- Source mode
-- . Single cycle SLV input
--- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
--- slv_in_val : IN STD_LOGIC := '0';
+ -- slv_in : IN STD_LOGIC_VECTOR(g_snk_data_w-1 DOWNTO 0) := (OTHERS=> '0'); -- Input for the RW fields defined in g_field_arr
+ -- slv_in_val : IN STD_LOGIC := '0';
-- . Multi cycle block output
-- Sink mode
-- . Multi cycle block input
-- . Single cycle SLV output
--- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
--- slv_out_val : OUT STD_LOGIC;
+ -- slv_out : OUT STD_LOGIC_VECTOR(g_src_data_w-1 DOWNTO 0); -- Output for the RO fields defined in g_field_arr
+ -- slv_out_val : OUT STD_LOGIC;
reg_slv_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_slv_miso : out t_mem_miso
--- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
--- reg_ovr_miso : OUT t_mem_miso
+ -- reg_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ -- reg_ovr_miso : OUT t_mem_miso
);
end dp_field_blk;
architecture str of dp_field_blk is
--- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
+ -- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
-- Mode: fields to data block (c_field_to_block=True) or data block to fields (c_field_to_block=False)
-- a.k.a. wire to narrow or narrow to wide
@@ -163,7 +163,7 @@ begin
gen_field_wires: for i in g_field_arr'range generate
dp_repack_data_snk_in.data(field_hi(g_field_arr, i) downto field_lo(g_field_arr, i)) <= mm_fields_slv_out(field_hi(g_field_arr, i) downto field_lo(g_field_arr, i))
when field_override_arr(i) = '1' else
- snk_in.data(field_hi(g_field_arr, i) downto field_lo(g_field_arr, i));
+ snk_in.data(field_hi(g_field_arr, i) downto field_lo(g_field_arr, i));
end generate;
src_out <= dp_repack_data_src_out;
@@ -191,65 +191,65 @@ begin
snk_out <= dp_repack_data_snk_out;
u_dp_repack_data : entity work.dp_repack_data
- generic map (
- g_in_dat_w => g_snk_data_w,
- g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
- g_out_dat_w => g_src_data_w,
- g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
- g_in_symbol_w => g_in_symbol_w,
- g_out_symbol_w => g_out_symbol_w,
- g_pipeline_ready => g_pipeline_ready
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_repack_data_snk_out,
- snk_in => dp_repack_data_snk_in,
-
- src_in => dp_repack_data_src_in,
- src_out => dp_repack_data_src_out
- );
+ generic map (
+ g_in_dat_w => g_snk_data_w,
+ g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
+ g_out_dat_w => g_src_data_w,
+ g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_symbol_w => g_out_symbol_w,
+ g_pipeline_ready => g_pipeline_ready
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_repack_data_snk_out,
+ snk_in => dp_repack_data_snk_in,
+
+ src_in => dp_repack_data_src_in,
+ src_out => dp_repack_data_src_out
+ );
---------------------------------------------------------------------------------------
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => g_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => reg_slv_mosi,
- mm_miso => reg_slv_miso,
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in,
- slv_in_val => mm_fields_slv_in_val,
- slv_out => mm_fields_slv_out
- );
+ generic map(
+ g_field_arr => g_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => reg_slv_mosi,
+ mm_miso => reg_slv_miso,
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in,
+ slv_in_val => mm_fields_slv_in_val,
+ slv_out => mm_fields_slv_out
+ );
---------------------------------------------------------------------------------------
-- mm_fields to set override bits
--- ---------------------------------------------------------------------------------------
--- u_mm_fields_ovr: ENTITY mm_lib.mm_fields
--- GENERIC MAP(
--- g_field_arr => field_arr_set_mode(c_ovr_field_arr, "RW") -- override fields are always RW
--- )
--- PORT MAP (
--- mm_clk => mm_clk,
--- mm_rst => mm_rst,
---
--- mm_mosi => reg_ovr_mosi,
--- mm_miso => reg_ovr_miso,
---
--- slv_clk => dp_clk,
--- slv_rst => dp_rst,
---
--- slv_out => field_override_arr
--- );
+ -- ---------------------------------------------------------------------------------------
+ -- u_mm_fields_ovr: ENTITY mm_lib.mm_fields
+ -- GENERIC MAP(
+ -- g_field_arr => field_arr_set_mode(c_ovr_field_arr, "RW") -- override fields are always RW
+ -- )
+ -- PORT MAP (
+ -- mm_clk => mm_clk,
+ -- mm_rst => mm_rst,
+ --
+ -- mm_mosi => reg_ovr_mosi,
+ -- mm_miso => reg_ovr_miso,
+ --
+ -- slv_clk => dp_clk,
+ -- slv_rst => dp_rst,
+ --
+ -- slv_out => field_override_arr
+ -- );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index 7cba26788d16425b89a47c66e7b5f45cb44a9946..3583e479edfce142074f6181ef44a49755c034fd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -40,11 +40,11 @@
-- ready signal.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core is
generic (
@@ -98,7 +98,7 @@ architecture str of dp_fifo_core is
constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl,
- g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
+ g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w); -- concat via FIFO
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -159,7 +159,7 @@ begin
snk_in.channel(g_channel_w - 1 downto 0),
snk_in.err( g_error_w - 1 downto 0),
wr_sync,
- wr_ctrl);
+ wr_ctrl);
-- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
-- add flow contol dependent on whether the fifo can fit another block
@@ -170,32 +170,32 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
);
- wr_init <= '0'; -- to avoid no driver warning in synthesis
- fifo_wr_usedw <= fifo_rd_usedw;
- end generate;
+wr_init <= '0'; -- to avoid no driver warning in synthesis
+fifo_wr_usedw <= fifo_rd_usedw;
+end generate;
- gen_common_fifo_dc : if g_use_dual_clock = true generate
- u_common_fifo_dc : entity common_lib.common_fifo_dc
+gen_common_fifo_dc : if g_use_dual_clock = true generate
+ u_common_fifo_dc : entity common_lib.common_fifo_dc
generic map (
g_technology => g_technology,
g_note_is_ful => g_note_is_ful,
@@ -218,33 +218,33 @@ begin
rd_val => fifo_rd_val
);
- arst <= wr_rst or rd_rst;
- end generate;
+ arst <= wr_rst or rd_rst;
+end generate;
- -- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
- rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 0);
+-- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
+rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 0);
- -- fifo rd wires
- -- SISO
- fifo_rd_req <= rd_siso.ready;
+-- fifo rd wires
+-- SISO
+fifo_rd_req <= rd_siso.ready;
- -- SOSI
- rd_sosi.data <= RESIZE_DP_SDATA(rd_data) when g_data_signed = true else RESIZE_DP_DATA(rd_data);
- rd_sosi.re <= RESIZE_DP_DSP_DATA(rd_data( c_complex_w - 1 downto 0));
- rd_sosi.im <= RESIZE_DP_DSP_DATA(rd_data(2 * c_complex_w - 1 downto c_complex_w));
- rd_sosi.bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 1));
- rd_sosi.empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 2));
- rd_sosi.channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 3));
- rd_sosi.err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 4));
- rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 5);
- rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 6);
+-- SOSI
+rd_sosi.data <= RESIZE_DP_SDATA(rd_data) when g_data_signed = true else RESIZE_DP_DATA(rd_data);
+rd_sosi.re <= RESIZE_DP_DSP_DATA(rd_data( c_complex_w - 1 downto 0));
+rd_sosi.im <= RESIZE_DP_DSP_DATA(rd_data(2 * c_complex_w - 1 downto c_complex_w));
+rd_sosi.bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 1));
+rd_sosi.empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 2));
+rd_sosi.channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 3));
+rd_sosi.err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 4));
+rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 5);
+rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, fifo_rd_dat, 6);
- rd_sosi.sync <= fifo_rd_val and rd_sync(0);
- rd_sosi.valid <= fifo_rd_val;
- rd_sosi.sop <= fifo_rd_val and rd_ctrl(1);
- rd_sosi.eop <= fifo_rd_val and rd_ctrl(0);
+rd_sosi.sync <= fifo_rd_val and rd_sync(0);
+rd_sosi.valid <= fifo_rd_val;
+rd_sosi.sop <= fifo_rd_val and rd_ctrl(1);
+rd_sosi.eop <= fifo_rd_val and rd_ctrl(0);
- u_ready_latency : entity work.dp_latency_adapter
+u_ready_latency : entity work.dp_latency_adapter
generic map (
g_in_latency => 1,
g_out_latency => g_fifo_rl
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index b3a020284e31c610dbf1859094006f769ec39299..751da74df2bdc97911525e9bb77e79bbcd52bfb4 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -44,11 +44,11 @@
-- . It is possible to add additonal signals to the fifo using in_aux/out_aux.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_core_arr is
generic (
@@ -108,7 +108,7 @@ architecture str of dp_fifo_core_arr is
constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level for snk_out.ready
constant c_fifo_almost_xon : natural := g_fifo_size - g_fifo_af_xon; -- FIFO almost full level for snk_out.xon
constant c_fifo_dat_w : natural := func_slv_concat_w(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
- c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
+ c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w); -- concat via FIFO
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
@@ -182,7 +182,7 @@ begin
snk_in_arr(0).err( g_error_w - 1 downto 0),
wr_sync,
wr_ctrl,
- wr_aux);
+ wr_aux);
-- pass on frame level flow control from src_in.xon to upstream snk_out.xon, and
-- add flow contol dependent on whether the fifo can fit another block
@@ -193,31 +193,31 @@ begin
gen_common_fifo_sc : if g_use_dual_clock = false generate
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_lut => g_use_lut_sc,
- g_dat_w => c_fifo_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => fifo_rd_emp,
- rd_val => fifo_rd_val,
- usedw => fifo_rd_usedw
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_lut => g_use_lut_sc,
+ g_dat_w => c_fifo_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => fifo_rd_emp,
+ rd_val => fifo_rd_val,
+ usedw => fifo_rd_usedw
);
- fifo_wr_usedw <= fifo_rd_usedw;
- end generate;
+fifo_wr_usedw <= fifo_rd_usedw;
+end generate;
- gen_common_fifo_dc : if g_use_dual_clock = true generate
- u_common_fifo_dc : entity common_lib.common_fifo_dc
+gen_common_fifo_dc : if g_use_dual_clock = true generate
+ u_common_fifo_dc : entity common_lib.common_fifo_dc
generic map (
g_technology => g_technology,
g_dat_w => c_fifo_dat_w,
@@ -238,41 +238,41 @@ begin
rd_val => fifo_rd_val
);
- arst <= wr_rst or rd_rst;
- end generate;
+ arst <= wr_rst or rd_rst;
+end generate;
- -- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
- rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
+-- Extract the data from the wide FIFO output SLV. rd_data will be assigned to rd_sosi.data or rd_sosi.im & rd_sosi.re depending on g_use_complex.
+rd_data <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w,
- fifo_rd_dat, 0);
+fifo_rd_dat, 0);
- -- fifo rd wires
- -- SISO
- fifo_rd_req <= rd_siso_arr(0).ready;
- rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 5);
- rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 6);
+-- fifo rd wires
+-- SISO
+fifo_rd_req <= rd_siso_arr(0).ready;
+rd_sync <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 5);
+rd_ctrl <= func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 6);
- -- AUX
- in_aux_sosi.data <= RESIZE_DP_DATA(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 7));
- in_aux_sosi.valid <= fifo_rd_val;
- out_aux <= out_aux_sosi.data(g_aux_w - 1 downto 0);
+-- AUX
+in_aux_sosi.data <= RESIZE_DP_DATA(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 7));
+in_aux_sosi.valid <= fifo_rd_val;
+out_aux <= out_aux_sosi.data(g_aux_w - 1 downto 0);
- -- SOSI
- gen_rd_streams : for I in 0 to g_nof_streams - 1 generate
- rd_data_arr(I) <= rd_data( (I + 1) * g_data_w - 1 downto I * g_data_w);
- rd_sosi_arr(I).data <= RESIZE_DP_SDATA(rd_data_arr(I)) when g_data_signed = true else RESIZE_DP_DATA(rd_data_arr(I));
- rd_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(rd_data_arr(I)( c_complex_w - 1 downto 0));
- rd_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(rd_data_arr(I)(2 * c_complex_w - 1 downto c_complex_w));
- rd_sosi_arr(I).bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 1));
- rd_sosi_arr(I).empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 2));
- rd_sosi_arr(I).channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 3));
- rd_sosi_arr(I).err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 4));
- rd_sosi_arr(I).sync <= fifo_rd_val and rd_sync(0);
- rd_sosi_arr(I).valid <= fifo_rd_val;
- rd_sosi_arr(I).sop <= fifo_rd_val and rd_ctrl(1);
- rd_sosi_arr(I).eop <= fifo_rd_val and rd_ctrl(0);
+-- SOSI
+gen_rd_streams : for I in 0 to g_nof_streams - 1 generate
+ rd_data_arr(I) <= rd_data( (I + 1) * g_data_w - 1 downto I * g_data_w);
+ rd_sosi_arr(I).data <= RESIZE_DP_SDATA(rd_data_arr(I)) when g_data_signed = true else RESIZE_DP_DATA(rd_data_arr(I));
+ rd_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(rd_data_arr(I)( c_complex_w - 1 downto 0));
+ rd_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(rd_data_arr(I)(2 * c_complex_w - 1 downto c_complex_w));
+ rd_sosi_arr(I).bsn <= RESIZE_DP_BSN(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 1));
+ rd_sosi_arr(I).empty <= RESIZE_DP_EMPTY(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 2));
+ rd_sosi_arr(I).channel <= RESIZE_DP_CHANNEL(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 3));
+ rd_sosi_arr(I).err <= RESIZE_DP_ERROR(func_slv_extract(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux, c_total_data_w, g_bsn_w, g_empty_w, g_channel_w, g_error_w, 1, c_ctrl_w, g_aux_w, fifo_rd_dat, 4));
+ rd_sosi_arr(I).sync <= fifo_rd_val and rd_sync(0);
+ rd_sosi_arr(I).valid <= fifo_rd_val;
+ rd_sosi_arr(I).sop <= fifo_rd_val and rd_ctrl(1);
+ rd_sosi_arr(I).eop <= fifo_rd_val and rd_ctrl(0);
- u_ready_latency : entity work.dp_latency_adapter
+ u_ready_latency : entity work.dp_latency_adapter
generic map (
g_in_latency => 1,
g_out_latency => g_fifo_rl
@@ -287,10 +287,10 @@ begin
src_in => src_in_arr(I),
src_out => src_out_arr(I)
);
- end generate;
+end generate;
- -- Using extra dp_latency_adapter for aux signal
- u_ready_latency_aux : entity work.dp_latency_adapter
+-- Using extra dp_latency_adapter for aux signal
+u_ready_latency_aux : entity work.dp_latency_adapter
generic map (
g_in_latency => 1,
g_out_latency => g_fifo_rl
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 3ec0c419a8368a0b4a1730d264765f4a3405d620..b4b3561e22f336b3820d85f7d5d0b77e5fd02d67 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc is
generic (
@@ -72,42 +72,42 @@ end dp_fifo_dc;
architecture str of dp_fifo_dc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 5bc9dffb7f286cb79db7b3d6c6994c6cd236657c..8c897f84244ad580fe411c77c137293e450587ca 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -25,11 +25,11 @@
-- Description: See dp_fifo_core_arr.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_arr is
generic (
@@ -79,47 +79,47 @@ end dp_fifo_dc_arr;
architecture str of dp_fifo_dc_arr is
begin
u_dp_fifo_core_arr : entity work.dp_fifo_core_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_aux_w => g_aux_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_aux => g_use_aux,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- in_aux => in_aux,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- out_aux => out_aux
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => g_nof_streams,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_aux_w => g_aux_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_aux => g_use_aux,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ in_aux => in_aux,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ out_aux => out_aux
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 2162fd4be1fbdf97b097a5e316bee168eca6e6cd..a6eb44298930bdcee5e7ba583afb08b68d477f0b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -101,11 +101,11 @@
-- . add this multi tb-tb test bench to tb_tb_tb_dp_backpressure.vhd
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_dc_mixed_widths is
generic (
@@ -197,41 +197,40 @@ begin
gen_equal : if c_nof_narrow = 1 generate -- fall back to equal width FIFO
u_dp_fifo_dc : entity work.dp_fifo_dc
- generic map (
- g_technology => g_technology,
- g_data_w => g_wr_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => g_use_ctrl,
- g_fifo_size => g_wr_fifo_size,
- g_fifo_af_margin => g_wr_fifo_af_margin,
- g_fifo_rl => g_rd_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_wr_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => g_use_ctrl,
+ g_fifo_size => g_wr_fifo_size,
+ g_fifo_af_margin => g_wr_fifo_af_margin,
+ g_fifo_rl => g_rd_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_equal
gen_mixed : if c_nof_narrow > 1 generate -- mixed width FIFO
-
arst <= wr_rst or rd_rst;
wr_ful <= fifo_wr_ful;
@@ -266,29 +265,30 @@ begin
fifo_rd_req <= rd_siso.ready;
u_fifo_mw : entity common_lib.common_fifo_dc_mixed_widths
- generic map (
- g_technology => g_technology,
- g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
- g_wr_dat_w => c_fifo_wr_dat_w,
- g_rd_dat_w => c_fifo_rd_dat_w
- )
- port map (
- rst => arst,
- wr_clk => wr_clk,
- wr_dat => fifo_wr_dat,
- wr_req => fifo_wr_req,
- wr_ful => fifo_wr_ful,
- wrusedw => i_wr_usedw,
- rd_clk => rd_clk,
- rd_dat => fifo_rd_dat,
- rd_req => fifo_rd_req,
- rd_emp => rd_emp,
- rdusedw => rd_usedw,
- rd_val => fifo_rd_val
- );
+ generic map (
+ g_technology => g_technology,
+ g_nof_words => g_wr_fifo_size, -- FIFO size in nof wr_dat words
+ g_wr_dat_w => c_fifo_wr_dat_w,
+ g_rd_dat_w => c_fifo_rd_dat_w
+ )
+ port map (
+ rst => arst,
+ wr_clk => wr_clk,
+ wr_dat => fifo_wr_dat,
+ wr_req => fifo_wr_req,
+ wr_ful => fifo_wr_ful,
+ wrusedw => i_wr_usedw,
+ rd_clk => rd_clk,
+ rd_dat => fifo_rd_dat,
+ rd_req => fifo_rd_req,
+ rd_emp => rd_emp,
+ rdusedw => rd_usedw,
+ rd_val => fifo_rd_val
+ );
-- FIFO write multiple parallel --> read one serial
gen_wr_wide : if c_wr_wide = true generate
+
gen_ctrl : if g_use_ctrl = true generate
-- Write the wide SOSI
p_fifo_wr_dat : process(snk_in)
@@ -355,11 +355,11 @@ begin
rd_sosi.data <= RESIZE_DP_DATA(fifo_rd_dat(c_narrow_data_w - 1 downto 0));
rd_sosi.valid <= fifo_rd_val;
end generate;
-
end generate; -- gen_wr_wide
-- FIFO write one serial --> read multiple parallel
gen_rd_wide : if c_wr_wide = false generate
+
gen_ctrl : if g_use_ctrl = true generate
-- Write the narrow SOSI
fifo_wr_dat <= snk_in.data(c_narrow_data_w - 1 downto 0) & snk_in.sop & snk_in.eop;
@@ -445,19 +445,19 @@ begin
-- Support show ahead FIFO with ready latency = 0 at read output
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => 1,
- g_out_latency => g_rd_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso,
- snk_in => rd_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 1,
+ g_out_latency => g_rd_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate; -- gen_mixed
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 5ba44fca042bd7a1f6e631bf2f9108469fc3c4e0..e2aa340244fe333d2285698fa78eb7e66fda6222 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -26,11 +26,11 @@
-- for new designs.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill is
generic (
@@ -58,64 +58,64 @@ entity dp_fifo_fill is
-- Monitor FIFO filling
wr_ful : out std_logic;
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_emp : out std_logic;
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+rd_emp : out std_logic;
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
- rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
+-- MM control FIFO filling (assume 32 bit MM interface)
+wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
+rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
- -- ST sink
- snk_out : out t_dp_siso;
- snk_in : in t_dp_sosi;
- -- ST source
- src_in : in t_dp_siso;
- src_out : out t_dp_sosi
- );
+-- ST sink
+snk_out : out t_dp_siso;
+snk_in : in t_dp_sosi;
+-- ST source
+src_in : in t_dp_siso;
+src_out : out t_dp_sosi
+);
end dp_fifo_fill;
architecture str of dp_fifo_fill is
begin
u_dp_fifo_fill_sc : entity work.dp_fifo_fill_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => usedw,
- rd_emp => rd_emp,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => usedw,
+ rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index f7c848b155e35b766066af8650195b02bf80287c..de8e8319e7d517457446384b474700d9e7f2253f 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -57,11 +57,11 @@
-- directly.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_core is
generic (
@@ -156,46 +156,46 @@ begin
gen_dp_fifo_sc : if g_use_dual_clock = false generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
);
- wr_fifo_usedw <= rd_fifo_usedw;
- end generate;
+wr_fifo_usedw <= rd_fifo_usedw;
+end generate;
- gen_dp_fifo_dc : if g_use_dual_clock = true generate
- u_dp_fifo_dc : entity work.dp_fifo_dc
+gen_dp_fifo_dc : if g_use_dual_clock = true generate
+ u_dp_fifo_dc : entity work.dp_fifo_dc
generic map (
g_technology => g_technology,
g_data_w => g_data_w,
@@ -233,99 +233,100 @@ begin
src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
src_out => rd_sosi
);
- end generate;
-
- no_fill : if g_fifo_fill = 0 generate
- rd_siso <= src_in; -- SISO
- src_out <= rd_sosi; -- SOSI
- end generate; -- no_fill
-
- gen_fill : if g_fifo_fill > 0 generate
- src_out <= i_src_out;
-
- p_rd_clk: process(rd_clk, rd_rst)
+end generate;
+
+no_fill : if g_fifo_fill = 0 generate
+ rd_siso <= src_in; -- SISO
+ src_out <= rd_sosi; -- SOSI
+end generate; -- no_fill
+
+gen_fill : if g_fifo_fill > 0 generate
+ src_out <= i_src_out;
+
+ p_rd_clk: process(rd_clk, rd_rst)
+ begin
+ if rd_rst = '1' then
+ xon_reg <= '0';
+ state <= s_idle;
+ i_src_out <= c_dp_sosi_rst;
+ elsif rising_edge(rd_clk) then
+ xon_reg <= nxt_xon_reg;
+ state <= nxt_state;
+ i_src_out <= nxt_src_out;
+ end if;
+ end process;
+
+ nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
+
+ gen_rl_0 : if g_fifo_rl = 0 generate
+
+ p_state : process(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl)
begin
- if rd_rst = '1' then
- xon_reg <= '0';
- state <= s_idle;
- i_src_out <= c_dp_sosi_rst;
- elsif rising_edge(rd_clk) then
- xon_reg <= nxt_xon_reg;
- state <= nxt_state;
- i_src_out <= nxt_src_out;
- end if;
- end process;
-
- nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
-
- gen_rl_0 : if g_fifo_rl = 0 generate
- p_state : process(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl)
- begin
- nxt_state <= state;
-
- rd_siso <= src_in; -- default acknowledge (RL=1) this input when output is ready
-
- -- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
- nxt_src_out <= rd_sosi;
- nxt_src_out.valid <= '0'; -- default no output
- nxt_src_out.sop <= '0';
- nxt_src_out.eop <= '0';
- nxt_src_out.sync <= '0';
-
- case state is
- when s_idle =>
- if xon_reg = '0' then
- nxt_state <= s_xoff;
+ nxt_state <= state;
+
+ rd_siso <= src_in; -- default acknowledge (RL=1) this input when output is ready
+
+ -- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
+ nxt_src_out <= rd_sosi;
+ nxt_src_out.valid <= '0'; -- default no output
+ nxt_src_out.sop <= '0';
+ nxt_src_out.eop <= '0';
+ nxt_src_out.sync <= '0';
+
+ case state is
+ when s_idle =>
+ if xon_reg = '0' then
+ nxt_state <= s_xoff;
+ else
+ -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
+ if rd_sosi.sop = '0' then
+ rd_siso <= c_dp_siso_rdy; -- acknowledge (RL=0) this input independent of output ready
else
- -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
- if rd_sosi.sop = '0' then
- rd_siso <= c_dp_siso_rdy; -- acknowledge (RL=0) this input independent of output ready
- else
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
- nxt_state <= s_fill;
- end if;
+ rd_siso <= c_dp_siso_hold; -- stop the input, hold the rd_sosi.sop at FIFO output (RL=0)
+ nxt_state <= s_fill;
end if;
- when s_fill =>
- if xon_reg = '0' then
- nxt_state <= s_xoff;
+ end if;
+ when s_fill =>
+ if xon_reg = '0' then
+ nxt_state <= s_xoff;
+ else
+ -- stop reading until the FIFO has been filled sufficiently
+ if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
+ rd_siso <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
else
- -- stop reading until the FIFO has been filled sufficiently
- if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
- rd_siso <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
- else
- -- if the output is ready, then start outputting the frame
- if src_in.ready = '1' then
- nxt_src_out <= rd_sosi; -- output sop that is still at FIFO output (RL=0)
- nxt_state <= s_output;
- end if;
+ -- if the output is ready, then start outputting the frame
+ if src_in.ready = '1' then
+ nxt_src_out <= rd_sosi; -- output sop that is still at FIFO output (RL=0)
+ nxt_state <= s_output;
end if;
end if;
- when s_output =>
- -- if the output is ready continue outputting the frame, ignore xon_reg during this frame
- if src_in.ready = '1' then
- nxt_src_out <= rd_sosi; -- output valid
- if rd_sosi.eop = '1' then
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
- end if;
- end if;
- when others => -- s_xoff
- -- Flush the fill FIFO when xon='0'
- rd_siso <= c_dp_siso_flush;
- if xon_reg = '1' then
- nxt_state <= s_idle;
+ end if;
+ when s_output =>
+ -- if the output is ready continue outputting the frame, ignore xon_reg during this frame
+ if src_in.ready = '1' then
+ nxt_src_out <= rd_sosi; -- output valid
+ if rd_sosi.eop = '1' then
+ nxt_state <= s_idle; -- output eop, so stop reading the FIFO
end if;
- end case;
-
- -- Pass on frame level flow control
- rd_siso.xon <= src_in.xon;
- end process;
- end generate; -- gen_rl_0
+ end if;
+ when others => -- s_xoff
+ -- Flush the fill FIFO when xon='0'
+ rd_siso <= c_dp_siso_flush;
+ if xon_reg = '1' then
+ nxt_state <= s_idle;
+ end if;
+ end case;
+
+ -- Pass on frame level flow control
+ rd_siso.xon <= src_in.xon;
+ end process;
+ end generate; -- gen_rl_0
- gen_rl_1 : if g_fifo_rl = 1 generate
- -- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
+ gen_rl_1 : if g_fifo_rl = 1 generate
+ -- Use dp_hold_input to get equivalent implementation with default RL=1 FIFO.
- -- Hold the sink input for source output
- u_snk : entity work.dp_hold_input
+ -- Hold the sink input for source output
+ u_snk : entity work.dp_hold_input
port map (
rst => rd_rst,
clk => rd_clk,
@@ -339,66 +340,67 @@ begin
src_out_reg => i_src_out
);
- p_state : process(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl)
- begin
- nxt_state <= state;
-
- hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
-
- -- The output register stage matches RL = 1 for src_in.ready
- nxt_src_out <= pend_src_out;
- nxt_src_out.valid <= '0'; -- default no output
- nxt_src_out.sop <= '0';
- nxt_src_out.eop <= '0';
- nxt_src_out.sync <= '0';
-
- case state is
- when s_idle =>
- if xon_reg = '0' then
- nxt_state <= s_xoff;
+ p_state : process(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl)
+ begin
+ nxt_state <= state;
+
+ hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
+
+ -- The output register stage matches RL = 1 for src_in.ready
+ nxt_src_out <= pend_src_out;
+ nxt_src_out.valid <= '0'; -- default no output
+ nxt_src_out.sop <= '0';
+ nxt_src_out.eop <= '0';
+ nxt_src_out.sync <= '0';
+
+ case state is
+ when s_idle =>
+ if xon_reg = '0' then
+ nxt_state <= s_xoff;
+ else
+ -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
+ if pend_src_out.sop = '0' then
+ hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
else
- -- read the FIFO until the sop is pending at the output, so discard any valid data between eop and sop
- if pend_src_out.sop = '0' then
- hold_src_in <= c_dp_siso_rdy; -- request (RL=1) new input independent of output ready
- else
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop in dp_hold_input
- nxt_state <= s_fill;
- end if;
+ hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop in dp_hold_input
+ nxt_state <= s_fill;
end if;
- when s_fill =>
- if xon_reg = '0' then
- nxt_state <= s_xoff;
+ end if;
+ when s_fill =>
+ if xon_reg = '0' then
+ nxt_state <= s_xoff;
+ else
+ -- stop reading until the FIFO has been filled sufficiently
+ if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
+ hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
else
- -- stop reading until the FIFO has been filled sufficiently
- if unsigned(rd_fifo_usedw) < unsigned(rd_fill_ctrl) then
- hold_src_in <= c_dp_siso_hold; -- stop the input, hold the pend_src_out.sop
- else
- -- if the output is ready, then start outputting the input frame
- if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output sop that is still pending in dp_hold_input
- nxt_state <= s_output;
- end if;
+ -- if the output is ready, then start outputting the input frame
+ if src_in.ready = '1' then
+ nxt_src_out <= pend_src_out; -- output sop that is still pending in dp_hold_input
+ nxt_state <= s_output;
end if;
end if;
- when s_output =>
- -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
- if src_in.ready = '1' then
- nxt_src_out <= pend_src_out; -- output valid
- if pend_src_out.eop = '1' then
- nxt_state <= s_idle; -- output eop, so stop reading the FIFO
- end if;
- end if;
- when others => -- s_xon
- -- Flush the fill FIFO when xon='0'
- hold_src_in <= c_dp_siso_flush;
- if xon_reg = '1' then
- nxt_state <= s_idle;
+ end if;
+ when s_output =>
+ -- if the output is ready continue outputting the input frame, ignore xon_reg during this frame
+ if src_in.ready = '1' then
+ nxt_src_out <= pend_src_out; -- output valid
+ if pend_src_out.eop = '1' then
+ nxt_state <= s_idle; -- output eop, so stop reading the FIFO
end if;
- end case;
+ end if;
+ when others => -- s_xon
+ -- Flush the fill FIFO when xon='0'
+ hold_src_in <= c_dp_siso_flush;
+ if xon_reg = '1' then
+ nxt_state <= s_idle;
+ end if;
+ end case;
+
+ -- Pass on frame level flow control
+ hold_src_in.xon <= src_in.xon;
+ end process;
+ end generate; -- gen_rl_1
+end generate; -- gen_fill
- -- Pass on frame level flow control
- hold_src_in.xon <= src_in.xon;
- end process;
- end generate; -- gen_rl_1
- end generate; -- gen_fill
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index e766edd8f673e76a7ca4f1af85467fc55e8ce88b..f75621af44eb12cee6032b94941f08a23f7afee5 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_dc is
generic (
@@ -76,45 +76,45 @@ end dp_fifo_fill_dc;
architecture str of dp_fifo_fill_dc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => true,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_usedw,
- rd_usedw => rd_usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => true,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_usedw,
+ rd_usedw => rd_usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index c7b793d0b5d61acaf586ec16a5808f174d31aae3..3fc307a26507c0d7d4a186467d2a7e60428368a0 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -53,11 +53,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop is
generic (
@@ -166,61 +166,61 @@ begin
rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w - 1 downto 0);
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => g_use_dual_clock,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => c_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => c_fifo_rl
- )
- port map (
- wr_rst => wr_rst,
- wr_clk => wr_clk,
- rd_rst => rd_rst,
- rd_clk => rd_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => wr_fifo_usedw,
- rd_usedw => rd_fifo_usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
- src_out => rd_sosi
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => g_use_dual_clock,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => c_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => c_fifo_rl
+ )
+ port map (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => wr_fifo_usedw,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => rd_siso, -- for RL = 0 rd_siso.ready acts as read acknowledge, -- for RL = 1 rd_siso.ready acts as read request
+ src_out => rd_sosi
+ );
-- Transfer eop counter across clock domains for dual clock
gen_rd_eop_cnt_dc : if g_use_dual_clock = true generate
reg_wr_eop_cnt <= TO_UVEC(wr_eop_cnt, c_word_w);
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => wr_rst,
- in_clk => wr_clk,
- in_dat => reg_wr_eop_cnt,
- in_new => wr_eop_new,
- in_done => wr_eop_done,
- out_rst => rd_rst,
- out_clk => rd_clk,
- out_dat => reg_rd_eop_cnt,
- out_new => rd_eop_new
- );
+ port map (
+ in_rst => wr_rst,
+ in_clk => wr_clk,
+ in_dat => reg_wr_eop_cnt,
+ in_new => wr_eop_new,
+ in_done => wr_eop_done,
+ out_rst => rd_rst,
+ out_clk => rd_clk,
+ out_dat => reg_rd_eop_cnt,
+ out_new => rd_eop_new
+ );
end generate;
-- No need to transfer eop counter across clock domains for single clock
@@ -235,6 +235,7 @@ begin
rd_eop_cnt <= TO_UINT(reg_rd_eop_cnt) when g_use_dual_clock else wr_eop_cnt;
gen_dual_clk : if g_use_dual_clock = true generate
+
p_eop_cnt_comb_dc: process(wr_eop_cnt, wr_eop_new, wr_eop_busy, wr_eop_done, snk_in)
variable v_wr_eop_cnt: natural;
variable v_wr_eop_new: std_logic;
@@ -329,18 +330,18 @@ begin
-- Hold the sink input for source output
u_snk : entity work.dp_hold_input
- port map (
- rst => rd_rst,
- clk => rd_clk,
- -- ST sink
- snk_out => rd_siso, -- SISO ready
- snk_in => rd_sosi, -- SOSI
- -- ST source
- src_in => hold_src_in, -- SISO ready
- next_src_out => OPEN, -- SOSI
- pend_src_out => pend_src_out,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rd_rst,
+ clk => rd_clk,
+ -- ST sink
+ snk_out => rd_siso, -- SISO ready
+ snk_in => rd_sosi, -- SOSI
+ -- ST source
+ src_in => hold_src_in, -- SISO ready
+ next_src_out => OPEN, -- SOSI
+ pend_src_out => pend_src_out,
+ src_out_reg => i_src_out
+ );
end generate;
gen_rl_0 : if g_fifo_rl = 0 generate
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
index f7d22ea5bd6053f27f8290e42c3681052db1c360..a58540f6a28f999d54735102d0cebc84fccebb0b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
@@ -25,11 +25,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_eop_sc is
generic (
@@ -58,65 +58,65 @@ entity dp_fifo_fill_eop_sc is
clk : in std_logic;
-- Monitor FIFO filling
wr_ful : out std_logic; -- corresponds to the carry bit of wr_usedw when FIFO is full
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_emp : out std_logic;
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
- rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
- -- ST sink
- snk_out : out t_dp_siso;
- snk_in : in t_dp_sosi;
- -- ST source
- src_in : in t_dp_siso := c_dp_siso_rdy;
- src_out : out t_dp_sosi
- );
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+rd_emp : out std_logic;
+-- MM control FIFO filling (assume 32 bit MM interface)
+wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
+rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
+-- ST sink
+snk_out : out t_dp_siso;
+snk_in : in t_dp_sosi;
+-- ST source
+src_in : in t_dp_siso := c_dp_siso_rdy;
+src_out : out t_dp_sosi
+);
end dp_fifo_fill_eop_sc;
architecture wrap of dp_fifo_fill_eop_sc is
begin
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false, -- single clock
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false, -- single clock
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw, -- use rd_usedw, similar as in dp_fifo_sc, dp_fifo_fill_sc
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index d5dabeee58c1845758e978fef65d98da8efc2b78..7c7b00a07477ac9500459258bff79d973dee65d6 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -50,9 +50,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_fill_reg is
generic (
@@ -71,10 +71,10 @@ entity dp_fifo_fill_reg is
sla_out : out t_mem_miso; -- actual ranges defined by c_mm_reg
-- MM registers in st_clk domain
- used_w : in std_logic_vector; -- Actual used word of the fifo
- rd_emp : in std_logic_vector;
- wr_ful : in std_logic_vector
- );
+ used_w : in std_logic_vector; -- Actual used word of the fifo
+rd_emp : in std_logic_vector;
+wr_ful : in std_logic_vector
+);
end dp_fifo_fill_reg;
architecture str of dp_fifo_fill_reg is
@@ -82,17 +82,18 @@ architecture str of dp_fifo_fill_reg is
constant c_nof_regs_per_stream : natural := 4; -- Must always be a power of 2 in order to meet the python register definition.
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => g_nof_streams * c_nof_regs_per_stream,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_nof_streams * c_nof_regs_per_stream),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => g_nof_streams * c_nof_regs_per_stream,
+ init_sl => '0');
- -- Registers in st_clk domain
- signal in_arr_reg : std_logic_vector(g_nof_streams * c_nof_regs_per_stream * c_word_w - 1 downto 0) := (others => '0');
- signal reg_wr_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
- signal reg_rd_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
- signal peak_used_w : std_logic_vector(g_nof_streams * c_word_w - 1 downto 0) := (others => '0');
+ -- Registers in st_clk domain
+ signal in_arr_reg : std_logic_vector(g_nof_streams * c_nof_regs_per_stream * c_word_w - 1 downto 0) := (others => '0');
+ signal reg_wr_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
+ signal reg_rd_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
+ signal peak_used_w : std_logic_vector(g_nof_streams * c_word_w - 1 downto 0) := (others => '0');
begin
gen_in_arr_reg : for I in 0 to g_nof_streams - 1 generate
in_arr_reg((c_nof_regs_per_stream * I + 1) * c_word_w - 1 downto c_nof_regs_per_stream * I * c_word_w) <= used_w((I + 1) * c_word_w - 1 downto I * c_word_w);
@@ -101,47 +102,46 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1')
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1')
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => sla_in,
- sla_out => sla_out,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => sla_in,
+ sla_out => sla_out,
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => in_arr_reg, -- read
- out_reg => OPEN, -- write
- out_new => open
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => in_arr_reg, -- read
+ out_reg => OPEN, -- write
+ out_new => open
+ );
gen_peak_meters : for I in 0 to g_nof_streams - 1 generate
u_peak_meter : entity common_lib.common_peak
- generic map(
- g_dat_w => c_word_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- in_val => '1',
- in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
- out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
- out_val => open
- );
+ generic map(
+ g_dat_w => c_word_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ in_dat => used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ in_val => '1',
+ in_clear => reg_rd_arr(I * c_nof_regs_per_stream + c_reg_max_used_words_offset),
+ out_dat => peak_used_w((I + 1) * c_word_w - 1 downto I * c_word_w),
+ out_val => open
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 2fc428f43218ee08a63c43c492cb3959b532feac..27405f34c068705b8a39491c696006d9975e7b0c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -24,11 +24,11 @@
-- Description: See dp_fifo_fill_core.vhd.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_fill_sc is
generic (
@@ -57,66 +57,66 @@ entity dp_fifo_fill_sc is
-- Monitor FIFO filling
wr_ful : out std_logic;
- usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
- rd_emp : out std_logic;
+ usedw : out std_logic_vector(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2)) - 1 downto 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+rd_emp : out std_logic;
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
- rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
- rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
+-- MM control FIFO filling (assume 32 bit MM interface)
+wr_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = wr_usedw
+rd_usedw_32b : out std_logic_vector(c_word_w - 1 downto 0); -- = rd_usedw
+rd_fill_32b : in std_logic_vector(c_word_w - 1 downto 0) := TO_UVEC(g_fifo_fill, c_word_w);
- -- ST sink
- snk_out : out t_dp_siso;
- snk_in : in t_dp_sosi;
- -- ST source
- src_in : in t_dp_siso := c_dp_siso_rdy;
- src_out : out t_dp_sosi
- );
+-- ST sink
+snk_out : out t_dp_siso;
+snk_in : in t_dp_sosi;
+-- ST source
+src_in : in t_dp_siso := c_dp_siso_rdy;
+src_out : out t_dp_sosi
+);
end dp_fifo_fill_sc;
architecture str of dp_fifo_fill_sc is
begin
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
- generic map (
- g_technology => g_technology,
- g_use_dual_clock => false,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- MM control FIFO filling (assume 32 bit MM interface)
- wr_usedw_32b => wr_usedw_32b,
- rd_usedw_32b => rd_usedw_32b,
- rd_fill_32b => rd_fill_32b,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_use_dual_clock => false,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- MM control FIFO filling (assume 32 bit MM interface)
+ wr_usedw_32b => wr_usedw_32b,
+ rd_usedw_32b => rd_usedw_32b,
+ rd_fill_32b => rd_fill_32b,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index 0ee926636df22b24bad3747be5df24c262dbfafe..08359c73f9ed12dcc3bd141ad6d2d90f296bfaee 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Provide MM access to the ST input of a FIFO.
@@ -56,13 +56,13 @@ entity dp_fifo_from_mm is
clk : in std_logic;
-- ST soure connected to FIFO input
src_out : out t_dp_sosi;
- usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
- -- Control for FIFO read access
- mm_wr : in std_logic; -- MM write pulse to write the mm_wrdata to src_out.data
- mm_wrdata : in std_logic_vector(g_mm_word_w - 1 downto 0);
- mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0);
- mm_availw : out std_logic_vector(g_mm_word_w - 1 downto 0)
- );
+ usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
+-- Control for FIFO read access
+mm_wr : in std_logic; -- MM write pulse to write the mm_wrdata to src_out.data
+mm_wrdata : in std_logic_vector(g_mm_word_w - 1 downto 0);
+mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0);
+mm_availw : out std_logic_vector(g_mm_word_w - 1 downto 0)
+);
end dp_fifo_from_mm;
architecture str of dp_fifo_from_mm is
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index 56aa6909193970fe9fe24cbfadce3f3725cf3f49..9fc8e35963ae89c5d47f4fd1be874d7977ebd04c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_from_mm_reg is
port (
@@ -37,15 +37,16 @@ entity dp_fifo_from_mm_reg is
-- MM registers
mm_wr_usedw : in std_logic_vector(c_word_w - 1 downto 0);
mm_wr_availw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_from_mm_reg;
architecture rtl of dp_fifo_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(2),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(2),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 2,
+ init_sl => '0');
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -62,7 +63,7 @@ begin
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_wr_usedw;
when 1 =>
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index 05cdd07ee2c625ba31234ac61505d6e6fa31d82c..7e6c732a1fa344e2e2d24f0af5f1f6f799fcf83f 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -71,11 +71,11 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_info is
generic (
@@ -155,19 +155,19 @@ begin
-- Data pipeline register to compensate for the fifo rd_req to rd_val latency of 1
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => data_snk_out,
- snk_in => data_snk_in,
- -- ST source
- src_in => dp_pipeline_data_src_in,
- src_out => dp_pipeline_data_src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => data_snk_out,
+ snk_in => data_snk_in,
+ -- ST source
+ src_in => dp_pipeline_data_src_in,
+ src_out => dp_pipeline_data_src_out
+ );
-- Buffer sop info
gen_info_sop : if c_fifo_sop_dat_w > 0 generate
@@ -179,74 +179,74 @@ begin
fifo_sop_wr_dat <= func_slv_concat(g_use_sync, g_use_bsn, g_use_channel,
wr_sync,
info_snk_in.bsn(g_bsn_w - 1 downto 0),
- info_snk_in.channel(g_channel_w - 1 downto 0));
+ info_snk_in.channel(g_channel_w - 1 downto 0));
u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_sop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_sop_wr_dat,
- wr_req => fifo_sop_wr_req,
- wr_ful => fifo_sop_wr_ful,
- rd_dat => fifo_sop_rd_dat,
- rd_req => fifo_sop_rd_req,
- rd_emp => fifo_sop_rd_emp,
- rd_val => fifo_sop_rd_val,
- usedw => fifo_sop_usedw
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_sop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_sop_wr_dat,
+ wr_req => fifo_sop_wr_req,
+ wr_ful => fifo_sop_wr_ful,
+ rd_dat => fifo_sop_rd_dat,
+ rd_req => fifo_sop_rd_req,
+ rd_emp => fifo_sop_rd_emp,
+ rd_val => fifo_sop_rd_val,
+ usedw => fifo_sop_usedw
);
- -- Extract the sop data from the FIFO output SLV
- info_src_out.sync <= rd_sync(0);
- rd_sync <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 0);
- info_src_out.bsn( g_bsn_w - 1 downto 0) <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 1);
- info_src_out.channel(g_channel_w - 1 downto 0) <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 2);
- end generate;
+-- Extract the sop data from the FIFO output SLV
+info_src_out.sync <= rd_sync(0);
+rd_sync <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 0);
+info_src_out.bsn( g_bsn_w - 1 downto 0) <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 1);
+info_src_out.channel(g_channel_w - 1 downto 0) <= func_slv_extract(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w, fifo_sop_rd_dat, 2);
+end generate;
- -- Buffer eop info
- gen_info_eop : if c_fifo_eop_dat_w > 0 generate
- fifo_eop_wr_req <= info_snk_in.eop;
- fifo_eop_rd_req <= data_snk_in.eop;
+-- Buffer eop info
+gen_info_eop : if c_fifo_eop_dat_w > 0 generate
+ fifo_eop_wr_req <= info_snk_in.eop;
+ fifo_eop_rd_req <= data_snk_in.eop;
- -- concatenate the eop data to use a single FIFO
- fifo_eop_wr_dat <= func_slv_concat(g_use_empty, g_use_error,
+ -- concatenate the eop data to use a single FIFO
+ fifo_eop_wr_dat <= func_slv_concat(g_use_empty, g_use_error,
info_snk_in.empty(g_empty_w - 1 downto 0),
- info_snk_in.err(g_error_w - 1 downto 0));
+ info_snk_in.err(g_error_w - 1 downto 0));
- u_common_fifo_sc : entity common_lib.common_fifo_sc
- generic map (
- g_technology => g_technology,
- g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
- g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
- g_dat_w => c_fifo_eop_dat_w,
- g_nof_words => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- wr_dat => fifo_eop_wr_dat,
- wr_req => fifo_eop_wr_req,
- wr_ful => fifo_eop_wr_ful,
- rd_dat => fifo_eop_rd_dat,
- rd_req => fifo_eop_rd_req,
- rd_emp => fifo_eop_rd_emp,
- rd_val => fifo_eop_rd_val,
+ u_common_fifo_sc : entity common_lib.common_fifo_sc
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => false, -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+ g_use_lut => true, -- when TRUE then force using LUTs via Altera eab="OFF",
+ g_dat_w => c_fifo_eop_dat_w,
+ g_nof_words => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_dat => fifo_eop_wr_dat,
+ wr_req => fifo_eop_wr_req,
+ wr_ful => fifo_eop_wr_ful,
+ rd_dat => fifo_eop_rd_dat,
+ rd_req => fifo_eop_rd_req,
+ rd_emp => fifo_eop_rd_emp,
+ rd_val => fifo_eop_rd_val,
usedw => fifo_eop_usedw
);
- -- Extract the eop data from the FIFO output SLV
- info_src_out.empty(g_empty_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 0);
- info_src_out.err(g_error_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 1);
- end generate;
+-- Extract the eop data from the FIFO output SLV
+info_src_out.empty(g_empty_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 0);
+info_src_out.err(g_error_w - 1 downto 0) <= func_slv_extract(g_use_empty, g_use_error, g_empty_w, g_error_w, fifo_eop_rd_dat, 1);
+end generate;
- -- Realign the info with the data
- dp_pipeline_data_src_in <= src_in;
- src_out <= func_dp_stream_combine_info_and_data(info_src_out, dp_pipeline_data_src_out);
- end generate;
+-- Realign the info with the data
+dp_pipeline_data_src_in <= src_in;
+src_out <= func_dp_stream_combine_info_and_data(info_src_out, dp_pipeline_data_src_out);
+end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index fd0011ecacc88e7089e2ce55e3ffb927ba922d59..f2cad3d29ea29a872a94aef4943d1a671f685f91 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -28,12 +28,12 @@
-- desired monitoring inputs and control outputs.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor is
port (
@@ -56,11 +56,12 @@ entity dp_fifo_monitor is
end dp_fifo_monitor;
architecture str of dp_fifo_monitor is
- constant c_field_arr : t_common_field_arr(4 downto 0) := ( (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
- (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
- (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
- (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
+ constant c_field_arr : t_common_field_arr(4 downto 0) := (
+ (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
+ (field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
+ (field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
+ (field_name_pad("wr_full" ), "RO", 1, field_default(0) ),
+ (field_name_pad("rd_fill" ), "RW", 32, field_default(0) ));
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -71,25 +72,25 @@ begin
mm_fields_in(field_hi(c_field_arr, "wr_full") downto field_lo(c_field_arr, "wr_full")) <= slv(wr_full);
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_in => mm_fields_in,
- slv_in_val => '1',
+ slv_in => mm_fields_in,
+ slv_in_val => '1',
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") downto field_lo(c_field_arr, "rd_fill"));
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index 4ec10842d177934e3c4ed29051f3fb59d074c03a..c4a32479896bffe9b73991b843e167dc84f133c4 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -27,12 +27,12 @@
-- . see dp_fifo_monitor.vhd
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_fifo_monitor_arr is
generic (
@@ -64,35 +64,34 @@ architecture str of dp_fifo_monitor_arr is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(c_nof_regs)
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(c_nof_regs)
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_dp_fifo_monitor : for i in 0 to g_nof_streams - 1 generate
u_dp_fifo_monitor: entity work.dp_fifo_monitor
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- reg_mosi => reg_mosi_arr(i),
- reg_miso => reg_miso_arr(i),
+ reg_mosi => reg_mosi_arr(i),
+ reg_miso => reg_miso_arr(i),
- rd_usedw_32b => rd_usedw_32b_arr(i),
- wr_usedw_32b => wr_usedw_32b_arr(i),
- rd_emp => rd_emp_arr(i),
- wr_full => wr_full_arr(i),
- rd_fill_32b => rd_fill_32b_arr(i)
- );
+ rd_usedw_32b => rd_usedw_32b_arr(i),
+ wr_usedw_32b => wr_usedw_32b_arr(i),
+ rd_emp => rd_emp_arr(i),
+ wr_full => wr_full_arr(i),
+ rd_fill_32b => rd_fill_32b_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 1ff22a1a71f019ff5204f1c73543dc5581a91022..8997d345e86ac6b5ebaafcd2e6aa9cafb49b5ac2 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -23,11 +23,11 @@
-- Description: See dp_fifo_core.vhd.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_fifo_sc is
generic (
@@ -57,58 +57,58 @@ entity dp_fifo_sc is
clk : in std_logic;
-- Monitor FIFO filling
wr_ful : out std_logic;
- usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
- rd_emp : out std_logic;
- -- ST sink
- snk_out : out t_dp_siso;
- snk_in : in t_dp_sosi;
- -- ST source
- src_in : in t_dp_siso := c_dp_siso_rdy;
- src_out : out t_dp_sosi
- );
+ usedw : out std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
+rd_emp : out std_logic;
+-- ST sink
+snk_out : out t_dp_siso;
+snk_in : in t_dp_sosi;
+-- ST source
+src_in : in t_dp_siso := c_dp_siso_rdy;
+src_out : out t_dp_sosi
+);
end dp_fifo_sc;
architecture str of dp_fifo_sc is
begin
u_dp_fifo_core : entity work.dp_fifo_core
- generic map (
- g_technology => g_technology,
- g_note_is_ful => g_note_is_ful,
- g_use_dual_clock => false,
- g_use_lut_sc => g_use_lut,
- g_data_w => g_data_w,
- g_data_signed => g_data_signed,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_ctrl => g_use_ctrl,
- g_use_complex => g_use_complex,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- wr_rst => rst,
- wr_clk => clk,
- rd_rst => rst,
- rd_clk => clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful,
- wr_usedw => OPEN,
- rd_usedw => usedw,
- rd_emp => rd_emp,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_technology => g_technology,
+ g_note_is_ful => g_note_is_ful,
+ g_use_dual_clock => false,
+ g_use_lut_sc => g_use_lut,
+ g_data_w => g_data_w,
+ g_data_signed => g_data_signed,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_ctrl => g_use_ctrl,
+ g_use_complex => g_use_complex,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => clk,
+ rd_rst => rst,
+ rd_clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful,
+ wr_usedw => OPEN,
+ rd_usedw => usedw,
+ rd_emp => rd_emp,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
index 2c5adb850c1178c2c5db189113b50c86a1495f9b..48e1642b9371e4390b3acc2f737724d38754eef3 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Provide MM access to the ST output of a FIFO.
@@ -55,13 +55,13 @@ entity dp_fifo_to_mm is
-- ST sink connected to FIFO output
snk_out : out t_dp_siso;
snk_in : in t_dp_sosi;
- usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
- -- Control for FIFO read access
- mm_rd : in std_logic; -- MM read pulse to read the mm_rddata from snk_in.data
- mm_rddata : out std_logic_vector(g_mm_word_w - 1 downto 0);
- mm_rdval : out std_logic;
- mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0)
- );
+ usedw : in std_logic_vector(ceil_log2(g_fifo_size) - 1 downto 0);
+-- Control for FIFO read access
+mm_rd : in std_logic; -- MM read pulse to read the mm_rddata from snk_in.data
+mm_rddata : out std_logic_vector(g_mm_word_w - 1 downto 0);
+mm_rdval : out std_logic;
+mm_usedw : out std_logic_vector(g_mm_word_w - 1 downto 0)
+);
end dp_fifo_to_mm;
architecture str of dp_fifo_to_mm is
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index 364603eeaef910666ddf261ddd658e02ba435483..83c1aef1992b106eb305204211fe07f4243d1131 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_fifo_to_mm_reg is
port (
@@ -37,15 +37,16 @@ entity dp_fifo_to_mm_reg is
-- MM registers
mm_rd_usedw : in std_logic_vector(c_word_w - 1 downto 0)
- );
+ );
end dp_fifo_to_mm_reg;
architecture rtl of dp_fifo_to_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -62,7 +63,7 @@ begin
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(c_word_w - 1 downto 0) <= mm_rd_usedw;
when others => null; -- unused MM addresses
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index c800903a5ba46b3b4726c03b18eda17e58a71d6b..93f4a5fea5d3b0ff0780129fcb358cedd52a1976 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Flush snk_in when src_in will be not ready for a long time.
-- Description:
@@ -95,6 +95,7 @@ architecture rtl of dp_flush is
begin
-- Combine MM control flush_en and streaming control src_in.xon
flush_dly(0) <= flush_en or not src_in.xon; -- use flush_dly(0) combinatorially, so that flush_dly supports all g_ready_latency >= 0
+
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -146,19 +147,19 @@ begin
end process;
u_src_en : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => src_en_hi,
- switch_low => src_en_lo,
- out_level => src_en
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => src_en_hi,
+ switch_low => src_en_lo,
+ out_level => src_en
+ );
p_snk_flush : process(snk_in, flush_dly)
variable v_hi : std_logic;
@@ -191,17 +192,17 @@ begin
end process;
u_snk_flush : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => true, -- priority does not matter
- g_or_high => true,
- g_and_low => true
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_flush_hi,
- switch_low => snk_flush_lo,
- out_level => snk_flush
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => true, -- priority does not matter
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_flush_hi,
+ switch_low => snk_flush_lo,
+ out_level => snk_flush
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 7b49530966b8140e84a36a88e751ae7407d0283f..fb54ca6d43e9ea8f8e9f66e2d019161ddc5de663 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Status:
-- . Active (recommended for new designs)
@@ -189,22 +189,23 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_output_block_size > 0 generate
+
gen_dp_block_gen : for i in 0 to c_nof_muxes - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -216,22 +217,23 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
gen_sync_bsn : if g_fwd_sync_bsn = true generate
+
gen_dp_fifo_info: for i in 0 to c_nof_muxes - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
@@ -247,5 +249,4 @@ begin
gen_wire_out_to_in: if g_nof_folds = 0 generate
dp_block_gen_snk_in_arr <= snk_in_arr;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
index 7de5defbcacb7bec071fa47c44267f6e4aae3637..df591c619d5a4210c4eeb997b694662629257604 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
@@ -61,10 +61,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_parallel is
generic (
@@ -100,8 +100,8 @@ entity dp_force_data_parallel is
end dp_force_data_parallel;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_force_data_parallel is
signal data_in : t_dp_sosi;
@@ -146,19 +146,19 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => data_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => data_out
+ );
src_out <= data_out;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
index 85b4568abdd09dc6f0c369f4d25f6d78c44c0f82..491dcdc0ac48fd63937818b40212e2133e2d8a00 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
@@ -76,10 +76,10 @@
-- then the force_data is void.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_force_data_serial is
generic (
@@ -123,18 +123,18 @@ begin
force_zero <= not force_zero_n;
u_common_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
- g_width => c_cnt_w,
- g_max => g_index_period
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cnt
- );
+ generic map (
+ g_latency => 0, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => c_cnt_w,
+ g_max => g_index_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cnt
+ );
p_comb : process(snk_in, cnt, force_en, force_index, force_value, force_zero, force_data, force_re, force_im)
begin
@@ -161,17 +161,17 @@ begin
end process;
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => data_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => data_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index c60355be35a771512e0c64b922e20d5eecd30133..b4f6109f1d963ab1228837e7baa398a768dae841 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame.vhd and rad_frame(rtl).vhd
@@ -115,6 +115,7 @@ begin
out_dat <= i_out_dat;
gen_input_reg : if c_input_reg = true generate
+
p_reg : process (clk, rst)
begin
if rst = '1' then
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
index 96e79e56f23fbc49a20294ae0568b61637825b17..7acd3af0bbcbec3c10ac73621576f8d5557430f9 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
@@ -27,9 +27,9 @@
-- Use g_pipeline > 0 to register snk_in_busy to ease timing closure.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy is
generic (
@@ -47,30 +47,30 @@ architecture str of dp_frame_busy is
signal busy : std_logic;
begin
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '0', -- Defines the output level at reset.
- g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
- g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
- g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
- )
- port map (
- rst => rst,
- clk => clk,
- switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
- switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
- out_level => busy
- );
+ generic map (
+ g_rst_level => '0', -- Defines the output level at reset.
+ g_priority_lo => true, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
+ g_or_high => true, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
+ g_and_low => false -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
+ switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
+ out_level => busy
+ );
u_common_pipeline_sl : entity common_lib.common_pipeline_sl
- generic map (
- g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
- g_reset_value => 0, -- 0 or 1, bit reset value,
- g_out_invert => false
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => busy,
- out_dat => snk_in_busy
- );
+ generic map (
+ g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
+ g_reset_value => 0, -- 0 or 1, bit reset value,
+ g_out_invert => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => busy,
+ out_dat => snk_in_busy
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
index 8b2e689ec4b6465c2b48bc0507f420d92bca15e4..dceec41f777830ca76a9845b1f1bd39fb0dd1ab2 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
@@ -24,8 +24,8 @@
-- See dp_frame_busy.
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_busy_arr is
generic (
@@ -44,15 +44,14 @@ architecture str of dp_frame_busy_arr is
begin
gen_nof_inputs : for I in 0 to g_nof_inputs - 1 generate
u_dp_frame_busy : entity work.dp_frame_busy
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in => snk_in_arr(I),
- snk_in_busy => snk_in_busy_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in => snk_in_arr(I),
+ snk_in_busy => snk_in_busy_arr(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
index 76ab9717de7b403a02aea8eb7c09b693429c5ea9..d08db0fa590bf9165c846730e0b26c43b3c30a3e 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_frame_hdr.vhd and rad_frame_hdr(rtl).vhd
@@ -137,6 +137,7 @@ begin
out_fsn <= fsync & fsn;
gen_input_reg : if c_input_reg = true generate
+
p_reg : process (clk, rst)
begin
if rst = '1' then
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
index 0a1b077acf385964ac688ecc358b7dcaff1186cc..71eba5beb0d8ffa6c0a4008e3c1d1e2385374586 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
@@ -23,7 +23,7 @@
-- Reuse from LOFAR rad_rdframe.vhd and rad_rdframe(rtl).vhd
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Read or flush one frame from a FIFO.
@@ -212,7 +212,7 @@ begin
end process;
next_out_throttle <= nxt_out_throttle; -- note next_out_throttle high in is same cycle as out_throttle when g_throttle_den=1
- -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
+ -- else next_out_throttle is high one cycle before out_throttle when g_throttle_den>1
p_frm_cnt : process(frm_cnt, frm_req, nxt_frm_done)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
index 41dbe3e5e8d7d9a21f5067063ecf6e4b986e1e5b..a759084469215f14dac09e6cf8a3031315dcf4a8 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_frame_remove is
generic (
@@ -63,65 +63,64 @@ architecture str of dp_frame_remove is
begin
no_bypass : if g_internal_bypass = false generate
u_dp_latency_adpapter: entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_snk_latency,
- g_out_latency => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_in_latency => g_snk_latency,
+ g_out_latency => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_out => snk_in_rl_1,
- src_in => snk_out_rl_1
- );
+ src_out => snk_in_rl_1,
+ src_in => snk_out_rl_1
+ );
u_dp_hdr_remove : entity work.dp_hdr_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- snk_out => snk_out_rl_1,
- snk_in => snk_in_rl_1,
+ snk_out => snk_out_rl_1,
+ snk_in => snk_in_rl_1,
- sla_in => sla_in,
- sla_out => sla_out,
+ sla_in => sla_in,
+ sla_out => sla_out,
- src_in => hdr_rem_siso,
- src_out => hdr_rem_sosi
- );
+ src_in => hdr_rem_siso,
+ src_out => hdr_rem_sosi
+ );
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_tail_nof_symbols
- )
- port map (
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => hdr_rem_siso,
- snk_in => hdr_rem_sosi,
-
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_tail_nof_symbols
+ )
+ port map (
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => hdr_rem_siso,
+ snk_in => hdr_rem_sosi,
+
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
src_out <= snk_in;
snk_out <= src_in;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index 7bda823b126ca1c283b9e3f0855b50426fbcf909..dd35b74c064d68d7808af768fc9e029fb7cc0369 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -22,8 +22,8 @@
-- Reuse from LOFAR rad_frame_repack.vhd and rad_frame_repack(rtl).vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
entity dp_frame_repack is
generic (
@@ -62,7 +62,7 @@ architecture str of dp_frame_repack is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -70,67 +70,66 @@ begin
gen_pack : if g_in_nof_words /= g_out_nof_words generate
unframe : entity work.dp_unframe
- generic map (
- g_dat_w => g_in_dat_w,
- g_fsn_w => g_in_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => in_dat,
- in_val => in_val,
- in_sof => in_sof,
- in_eof => in_eof,
- out_fsn => pack_fsn,
- out_sync => OPEN,
- out_dat => pack_dat,
- out_val => pack_val,
- out_sof => pack_sof,
- out_eof => pack_eof,
- out_err => pack_err
- );
+ generic map (
+ g_dat_w => g_in_dat_w,
+ g_fsn_w => g_in_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => in_dat,
+ in_val => in_val,
+ in_sof => in_sof,
+ in_eof => in_eof,
+ out_fsn => pack_fsn,
+ out_sync => OPEN,
+ out_dat => pack_dat,
+ out_val => pack_val,
+ out_sof => pack_sof,
+ out_eof => pack_eof,
+ out_err => pack_err
+ );
repack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
- in_dat => pack_dat,
- in_val => pack_val,
- in_sof => pack_sof,
- in_eof => pack_eof,
- out_dat => repack_dat,
- out_val => repack_val,
- out_sof => repack_sof,
- out_eof => repack_eof
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_dat => pack_dat,
+ in_val => pack_val,
+ in_sof => pack_sof,
+ in_eof => pack_eof,
+ out_dat => repack_dat,
+ out_val => repack_val,
+ out_sof => repack_sof,
+ out_eof => repack_eof
+ );
repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length); -- pack_fsn remains valid
frame : entity work.dp_frame
- generic map (
- g_dat_w => g_out_dat_w,
- g_fsn_w => g_out_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
- in_fsn => repack_fsn,
- in_dat => repack_dat,
- in_val => repack_val,
- in_sof => repack_sof,
- in_eof => repack_eof,
- in_err => pack_err, -- pack_err remains valid
- out_dat => out_dat,
- out_val => out_val,
- out_sof => out_sof,
- out_eof => out_eof
- );
+ generic map (
+ g_dat_w => g_out_dat_w,
+ g_fsn_w => g_out_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_fsn => repack_fsn,
+ in_dat => repack_dat,
+ in_val => repack_val,
+ in_sof => repack_sof,
+ in_eof => repack_eof,
+ in_err => pack_err, -- pack_err remains valid
+ out_dat => out_dat,
+ out_val => out_val,
+ out_sof => out_sof,
+ out_eof => out_eof
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6a5304e97b99986ec0aa59e0d2326aacebfceae3..ee11107f6b8072dc091fd7c28e09f62117770d4b 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame_rx.vhd and rad_frame_rx(rtl).vhd
@@ -140,177 +140,180 @@ architecture rtl of dp_frame_rx is
signal nxt_flush_en : std_logic;
signal flush_val : std_logic;
- procedure proc_handle_rx_timeout(signal valid : in std_logic;
- signal timeout_evt : in std_logic;
- signal clr : out std_logic;
- variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
- begin
- if valid = '1' then
- clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
- else
- clr <= '0'; -- let valid inactive timeout count increment
- if timeout_evt = '1' then -- can only occur when g_timeout_w>0
- v_state := s_flush; -- exit to flush state to finish the current rx frame with void data
- end if;
- end if;
- end proc_handle_rx_timeout;
-begin
- gen_input_reg : if c_input_reg = true generate
- p_reg : process (clk, rst)
+ procedure proc_handle_rx_timeout(
+ signal valid : in std_logic;
+ signal timeout_evt : in std_logic;
+ signal clr : out std_logic;
+ variable v_state : inout t_state) is -- use variable v_state instead of signal to avoid getting latches
+ begin
+ if valid = '1' then
+ clr <= '1'; -- restart timeout_cnt during frame rx and remain in current state
+ else
+ clr <= '0'; -- let valid inactive timeout count increment
+ if timeout_evt = '1' then -- can only occur when g_timeout_w>0
+ v_state := s_flush; -- exit to flush state to finish the current rx frame with void data
+ end if;
+ end if;
+ end proc_handle_rx_timeout;
begin
- if rst = '1' then
- in_val_reg <= '0';
- in_dat_reg <= (others => '0');
- elsif rising_edge(clk) then
- in_val_reg <= in_val;
- in_dat_reg <= in_dat;
- end if;
- end process;
- end generate;
+ gen_input_reg : if c_input_reg = true generate
- no_input_reg : if c_input_reg = false generate
- in_val_reg <= in_val;
- in_dat_reg <= in_dat;
- end generate;
+ p_reg : process (clk, rst)
+ begin
+ if rst = '1' then
+ in_val_reg <= '0';
+ in_dat_reg <= (others => '0');
+ elsif rising_edge(clk) then
+ in_val_reg <= in_val;
+ in_dat_reg <= in_dat;
+ end if;
+ end process;
+ end generate;
- p_clk : process (clk, rst)
- begin
- if rst = '1' then
- timeout_cnt_clr <= '1';
- flush_en <= '0';
- crc <= (others => '1');
- cnt <= 0;
- prev_in_dat_reg <= (others => '0');
- out_dat <= (others => '0');
- out_val <= '0';
- out_sof <= '0';
- out_eof <= '0';
- xon_reg <= '0';
- state <= s_sof;
- elsif rising_edge(clk) then
- timeout_cnt_clr <= nxt_timeout_cnt_clr;
- flush_en <= nxt_flush_en;
- crc <= nxt_crc;
- cnt <= nxt_cnt;
- prev_in_dat_reg <= in_dat_reg;
- out_dat <= nxt_out_dat;
- out_val <= nxt_out_val;
- out_sof <= nxt_out_sof;
- out_eof <= nxt_out_eof;
- xon_reg <= nxt_xon_reg;
- state <= nxt_state;
- end if;
- end process;
+ no_input_reg : if c_input_reg = false generate
+ in_val_reg <= in_val;
+ in_dat_reg <= in_dat;
+ end generate;
- ------------------------------------------------------------------------------
- -- Rx timeout control
- ------------------------------------------------------------------------------
- no_timeout : if g_timeout_w = 0 generate
- timeout_evt <= '0';
- flush_val <= '0';
- end generate;
+ p_clk : process (clk, rst)
+ begin
+ if rst = '1' then
+ timeout_cnt_clr <= '1';
+ flush_en <= '0';
+ crc <= (others => '1');
+ cnt <= 0;
+ prev_in_dat_reg <= (others => '0');
+ out_dat <= (others => '0');
+ out_val <= '0';
+ out_sof <= '0';
+ out_eof <= '0';
+ xon_reg <= '0';
+ state <= s_sof;
+ elsif rising_edge(clk) then
+ timeout_cnt_clr <= nxt_timeout_cnt_clr;
+ flush_en <= nxt_flush_en;
+ crc <= nxt_crc;
+ cnt <= nxt_cnt;
+ prev_in_dat_reg <= in_dat_reg;
+ out_dat <= nxt_out_dat;
+ out_val <= nxt_out_val;
+ out_sof <= nxt_out_sof;
+ out_eof <= nxt_out_eof;
+ xon_reg <= nxt_xon_reg;
+ state <= nxt_state;
+ end if;
+ end process;
- gen_timeout : if g_timeout_w > 0 generate
- u_timeout_cnt : entity common_lib.common_counter
- generic map (
- g_width => c_timeout_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => timeout_cnt_clr,
- count => timeout_cnt
- );
+ ------------------------------------------------------------------------------
+ -- Rx timeout control
+ ------------------------------------------------------------------------------
+ no_timeout : if g_timeout_w = 0 generate
+ timeout_evt <= '0';
+ flush_val <= '0';
+ end generate;
- timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
+ gen_timeout : if g_timeout_w > 0 generate
+ u_timeout_cnt : entity common_lib.common_counter
+ generic map (
+ g_width => c_timeout_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => timeout_cnt_clr,
+ count => timeout_cnt
+ );
- assert not(rising_edge(clk) and timeout_evt = '1') report "rad_frame_rx timeout occurred!" severity WARNING;
+ timeout_evt <= timeout_cnt(g_timeout_w); -- check MSbit for timeout of 2**g_timeout_w clk cycles
- -- define flush_val to prepare for throttle support of out_val during flush, default no throttle support yet
- flush_val <= flush_en;
- end generate;
+ assert not(rising_edge(clk) and timeout_evt = '1') report "rad_frame_rx timeout occurred!" severity WARNING;
- ------------------------------------------------------------------------------
- -- XON/XOFF rx frame flow control
- ------------------------------------------------------------------------------
- nxt_xon_reg <= out_xon; -- register out_xon to ease timing closure, because out_xon may come from far on the chip and some more cycles latency for xon is acceptable
+ -- define flush_val to prepare for throttle support of out_val during flush, default no throttle support yet
+ flush_val <= flush_en;
+ end generate;
- ------------------------------------------------------------------------------
- -- Rx state machine
- ------------------------------------------------------------------------------
- p_state: process(state, crc, cnt, in_val_reg, in_dat_reg, prev_in_dat_reg, xon_reg, timeout_evt, flush_val)
- variable v_nxt_state : t_state; -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
- begin
- nxt_timeout_cnt_clr <= '1'; -- default no timeout_cnt
- nxt_flush_en <= '0';
+ ------------------------------------------------------------------------------
+ -- XON/XOFF rx frame flow control
+ ------------------------------------------------------------------------------
+ nxt_xon_reg <= out_xon; -- register out_xon to ease timing closure, because out_xon may come from far on the chip and some more cycles latency for xon is acceptable
- nxt_crc <= crc;
- nxt_cnt <= cnt;
- nxt_out_dat <= in_dat_reg; -- default pass on input dat
- nxt_out_val <= '0';
- nxt_out_sof <= '0';
- nxt_out_eof <= '0';
- v_nxt_state := state;
+ ------------------------------------------------------------------------------
+ -- Rx state machine
+ ------------------------------------------------------------------------------
+ p_state: process(state, crc, cnt, in_val_reg, in_dat_reg, prev_in_dat_reg, xon_reg, timeout_evt, flush_val)
+ variable v_nxt_state : t_state; -- use variable instead of signal to avoid getting latches with proc_handle_rx_timeout()
+ begin
+ nxt_timeout_cnt_clr <= '1'; -- default no timeout_cnt
+ nxt_flush_en <= '0';
- if in_val_reg = '1' then
- nxt_crc <= func_dp_next_crc(g_lofar, in_dat_reg, crc);
- end if;
+ nxt_crc <= crc;
+ nxt_cnt <= cnt;
+ nxt_out_dat <= in_dat_reg; -- default pass on input dat
+ nxt_out_val <= '0';
+ nxt_out_sof <= '0';
+ nxt_out_eof <= '0';
+ v_nxt_state := state;
- case state is
- when s_sof =>
- nxt_crc <= (others => '1');
- nxt_cnt <= 0;
- if xon_reg = '1' then -- flush any input rx frame if xon_reg is XOFF
- if in_val_reg = '1' then
- if in_dat_reg = c_sfd and prev_in_dat_reg = c_idle then -- ignore in_val during c_idle
- v_nxt_state := s_fsn;
- end if;
- end if;
- end if;
- when s_fsn =>
if in_val_reg = '1' then
- nxt_out_val <= '1';
- nxt_out_sof <= '1';
- v_nxt_state := s_eof;
+ nxt_crc <= func_dp_next_crc(g_lofar, in_dat_reg, crc);
end if;
- -- Exit to s_flush in case of rx timeout
- proc_handle_rx_timeout(in_val_reg, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
- when s_eof =>
- if in_val_reg = '1' then
- nxt_out_val <= '1';
- if cnt = g_block_size then -- fill in brc based on rx crc result
- nxt_out_eof <= '1';
- nxt_out_dat <= c_brc_ok;
- if c_dp_crc_w > g_dat_w then
- if crc(in_dat'range) /= in_dat_reg then
- nxt_out_dat <= c_brc_err;
+
+ case state is
+ when s_sof =>
+ nxt_crc <= (others => '1');
+ nxt_cnt <= 0;
+ if xon_reg = '1' then -- flush any input rx frame if xon_reg is XOFF
+ if in_val_reg = '1' then
+ if in_dat_reg = c_sfd and prev_in_dat_reg = c_idle then -- ignore in_val during c_idle
+ v_nxt_state := s_fsn;
+ end if;
end if;
- else
- if crc /= in_dat_reg(crc'range) then
- nxt_out_dat <= c_brc_err;
+ end if;
+ when s_fsn =>
+ if in_val_reg = '1' then
+ nxt_out_val <= '1';
+ nxt_out_sof <= '1';
+ v_nxt_state := s_eof;
+ end if;
+ -- Exit to s_flush in case of rx timeout
+ proc_handle_rx_timeout(in_val_reg, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
+ when s_eof =>
+ if in_val_reg = '1' then
+ nxt_out_val <= '1';
+ if cnt = g_block_size then -- fill in brc based on rx crc result
+ nxt_out_eof <= '1';
+ nxt_out_dat <= c_brc_ok;
+ if c_dp_crc_w > g_dat_w then
+ if crc(in_dat'range) /= in_dat_reg then
+ nxt_out_dat <= c_brc_err;
+ end if;
+ else
+ if crc /= in_dat_reg(crc'range) then
+ nxt_out_dat <= c_brc_err;
+ end if;
+ end if;
+ v_nxt_state := s_sof;
+ else
+ nxt_cnt <= cnt + 1; -- count payload data
end if;
end if;
- v_nxt_state := s_sof;
- else
- nxt_cnt <= cnt + 1; -- count payload data
- end if;
- end if;
- -- Exit to s_flush in case of rx timeout
- proc_handle_rx_timeout(in_val_reg, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
- when others => -- s_flush -- this state can only be reached if g_timeout_w>0
- nxt_flush_en <= '1'; -- enable flush frame due to in_val_reg inactive timeout
- if flush_val = '1' then
- nxt_out_val <= '1'; -- flush rx frame with void data
- if cnt >= g_block_size then
- nxt_out_eof <= '1';
- nxt_out_dat <= c_brc_err; -- fill in c_brc_err for flushed rx frame
- v_nxt_state := s_sof;
- else
- nxt_cnt <= cnt + 1; -- count payload data
- end if;
- end if;
- end case;
+ -- Exit to s_flush in case of rx timeout
+ proc_handle_rx_timeout(in_val_reg, timeout_evt, nxt_timeout_cnt_clr, v_nxt_state);
+ when others => -- s_flush -- this state can only be reached if g_timeout_w>0
+ nxt_flush_en <= '1'; -- enable flush frame due to in_val_reg inactive timeout
+ if flush_val = '1' then
+ nxt_out_val <= '1'; -- flush rx frame with void data
+ if cnt >= g_block_size then
+ nxt_out_eof <= '1';
+ nxt_out_dat <= c_brc_err; -- fill in c_brc_err for flushed rx frame
+ v_nxt_state := s_sof;
+ else
+ nxt_cnt <= cnt + 1; -- count payload data
+ end if;
+ end if;
+ end case;
+
+ nxt_state <= v_nxt_state;
+ end process;
- nxt_state <= v_nxt_state;
- end process;
-end rtl;
+ end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 6d587242c714b91955a5a045c0c90bd96e81b6fc..5e09e7ac2223cb75ec1699f8ca6a0dc498e267d3 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -41,11 +41,11 @@
-- they are written into the input FIFO.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_frame_scheduler is
generic (
@@ -117,6 +117,7 @@ architecture rtl of dp_frame_scheduler is
signal nxt_out_eof : std_logic;
begin
gen_input_reg : if c_input_reg = true generate
+
p_reg : process (clk, rst)
begin
if rst = '1' then
@@ -136,6 +137,7 @@ begin
end generate;
no_input_reg : if c_input_reg = false generate
+
p_in_reg : process(in_dat, in_val, in_sof, in_eof)
begin
for I in 0 to g_nof_input - 1 loop
@@ -158,16 +160,16 @@ begin
wr_siso(I).xon <= not in_dis(I);
u_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => OPEN,
- in_sosi => snk_in(I),
- -- Frame out
- out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
- out_sosi => wr_sosi(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => OPEN,
+ in_sosi => snk_in(I),
+ -- Frame out
+ out_siso => wr_siso(I), -- flush control via xon, ready is not used and only passed on
+ out_sosi => wr_sosi(I)
+ );
-- Input FIFO
rd_siso(I).ready <= rd_req(I);
@@ -178,31 +180,31 @@ begin
rd_eof(I) <= rd_sosi(I).eop;
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => wr_sosi(I),
- -- ST source
- src_in => rd_siso(I), -- IN = request from downstream ST sink
- src_out => rd_sosi(I),
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => wr_sosi(I),
+ -- ST source
+ src_in => rd_siso(I), -- IN = request from downstream ST sink
+ src_out => rd_sosi(I),
- wr_ful => gp_out(I)
- );
+ wr_ful => gp_out(I)
+ );
end generate;
-- Output select
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index abff3ccbce1c083e43e0999622f2285906f6e407..94165eccced2b4ce0fd0c2a90ed21f546f35297f 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -30,9 +30,9 @@
-- status applies to the interval before the previous sync interval, due to the data processing latency.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
entity dp_frame_status is
generic (
@@ -126,33 +126,33 @@ begin
-- frame sync detection
u_fsync_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => fsync, -- frame sync
- switch_low => sync_dly, -- system sync
- out_level => fsync_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => fsync, -- frame sync
+ switch_low => sync_dly, -- system sync
+ out_level => fsync_det
+ );
-- any frame brc over fsync interval
u_brc_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => brc, -- frame brc
- switch_low => fsync, -- frame sync
- out_level => brc_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => brc, -- frame brc
+ switch_low => fsync, -- frame sync
+ out_level => brc_det
+ );
-- any frame discarded over fsync interval
u_dis_det : entity common_lib.common_switch
- port map (
- clk => clk,
- rst => rst,
- switch_high => in_dis, -- frame discarded
- switch_low => fsync, -- frame sync
- out_level => dis_det
- );
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => in_dis, -- frame discarded
+ switch_low => fsync, -- frame sync
+ out_level => dis_det
+ );
-- frame count over fsync interval
p_frame_cnt : process(cnt, fsync, in_eof)
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index 01dbbf256a3037d038122e4ba592fdce060154ab..204136bf5c9efe4daaa8778e59f5b2374e71eb2a 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_frame_tx.vhd and rad_frame_tx(rtl).vhd
@@ -118,6 +118,7 @@ architecture rtl of dp_frame_tx is
signal nxt_out_eof : std_logic;
begin
gen_input_reg : if c_input_reg = true generate
+
p_reg : process (clk, rst)
begin
if rst = '1' then
@@ -211,8 +212,8 @@ begin
elsif in_val_dly2 = '0' then
if frame_busy = '0' then
nxt_out_dat <= c_idle; -- insert idle word when out_val is inactive between frames
- --ELSE
- -- do not transmit idle when out_val is inactive during a frame to reduce potential false sync at receiver
+ --ELSE
+ -- do not transmit idle when out_val is inactive during a frame to reduce potential false sync at receiver
end if;
end if;
end process;
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 9f487ec1c7bec965e72ac55474c6c4f6720bea57..0f1f1fa55dc6bd34ac01fd0cc5c20464f78f1782 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -34,17 +34,17 @@
-- valid data work comes in.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
entity dp_gap is
generic (
g_dat_len : natural := 1000000;
g_gap_len : natural := 5;
g_gap_extend : boolean := false -- if TRUE, the first valid='0' cycle is extended to g_gap_len by de-assertion of snk_out.ready.
- ); -- This results in all gaps having a minimum length of g_gap_len.
+ ); -- This results in all gaps having a minimum length of g_gap_len.
port (
clk : in std_logic;
rst : in std_logic;
@@ -75,6 +75,7 @@ begin
src_out <= snk_in;
gen_rtl : if g_gap_len > 0 generate
+
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -97,48 +98,47 @@ begin
case state is
- when s_wait_for_val => -- Wait for valid data to come in
- if snk_in.valid = '1' then
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
- nxt_gap_cnt <= (others => '0');
- nxt_state <= s_counting;
- end if;
-
- when s_counting => -- Start counting cycles
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
- nxt_state <= s_force_not_rdy;
- snk_out.ready <= '0';
- nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
- end if;
- if snk_in.valid = '0' then -- Also start counting any invalid cycles
- if g_gap_extend = true then
- snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ when s_wait_for_val => -- Wait for valid data to come in
+ if snk_in.valid = '1' then
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w);
+ nxt_gap_cnt <= (others => '0');
+ nxt_state <= s_counting;
+ end if;
+
+ when s_counting => -- Start counting cycles
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_dat_len - 1, c_dat_len_w) then -- time to force a gap
+ nxt_state <= s_force_not_rdy;
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= TO_UVEC(1, c_dat_len_w); -- we already have 1 clk cycle with ready='0' here
+ end if;
+ if snk_in.valid = '0' then -- Also start counting any invalid cycles
+ if g_gap_extend = true then
+ snk_out.ready <= '0'; -- Keep ready de-asserted. Gap_cnt will increment so it will be released again after g_gap_len.
+ end if;
+ nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
+ else
+ nxt_gap_cnt <= (others => '0');
end if;
- nxt_gap_cnt <= INCR_UVEC(gap_cnt, 1);
- else
- nxt_gap_cnt <= (others => '0');
- end if;
- if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
- -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
- nxt_gap_cnt <= (others => '0');
- nxt_clk_cnt <= (others => '0');
- nxt_state <= s_wait_for_val;
- if g_gap_extend = true then
- snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ if gap_cnt = TO_UVEC(g_gap_len - 1, c_gap_len_w) and snk_in.valid = '0' then -- A gap of sufficient length occured by itself (or valid='0' was extended); no need to force gap
+ -- We've counted g_gap_len-1, plus the current gap cycle = g_gap_len
+ nxt_gap_cnt <= (others => '0');
+ nxt_clk_cnt <= (others => '0');
+ nxt_state <= s_wait_for_val;
+ if g_gap_extend = true then
+ snk_out.ready <= src_in.ready; -- Release the ready signal again if it was forced down because of gap extension
+ end if;
+ end if;
+
+ when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
+ snk_out.ready <= '0';
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
+ nxt_state <= s_wait_for_val;
+ nxt_clk_cnt <= (others => '0');
end if;
- end if;
-
- when s_force_not_rdy => -- Force snk_out.ready to '0' for g_gap_len clk cycles
- snk_out.ready <= '0';
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- if clk_cnt = TO_UVEC(g_gap_len - 1, c_dat_len_w) then
- nxt_state <= s_wait_for_val;
- nxt_clk_cnt <= (others => '0');
- end if;
end case;
end process;
-
end generate;
no_rtl : if g_gap_len = 0 generate -- bypass
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
index 4de916688351f6f59cc3429bbab94ce4432705dd..f0e67db1d411c1254324c21b2912279b8be26e3e 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
@@ -25,10 +25,10 @@
-- and g_symbol_w.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_insert is
generic (
@@ -67,25 +67,25 @@ architecture str of dp_hdr_insert is
begin
no_bypass: if g_internal_bypass = false generate
u_dp_ram_from_mm : entity work.mms_dp_ram_from_mm
- generic map (
- g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_rd_dat_w => g_data_w,
- g_init_file => g_init_hdr,
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- reg_mosi => reg_mosi,
- ram_mosi => ram_mosi,
-
- src_in => hdr_siso,
- src_out => hdr_sosi
- );
+ generic map (
+ g_ram_wr_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_rd_dat_w => g_data_w,
+ g_init_file => g_init_hdr,
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ reg_mosi => reg_mosi,
+ ram_mosi => ram_mosi,
+
+ src_in => hdr_siso,
+ src_out => hdr_sosi
+ );
hdr_siso <= concat_siso_arr(0);
snk_out <= concat_siso_arr(1);
@@ -93,25 +93,24 @@ begin
concat_sosi_arr(1) <= snk_in;
u_dp_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
src_out <= snk_in;
snk_out <= src_in;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
index c924c29515f109ca45763b7073f08a7e6e3641e1..5ba1d3185e51fd1bb0d307a3f94b9291308ac266 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_hdr_remove is
generic (
@@ -57,41 +57,41 @@ architecture str of dp_hdr_remove is
signal split_sosi_arr : t_dp_sosi_arr(0 to 1);
begin
u_dp_ram_to_mm : entity work.dp_ram_to_mm
- generic map (
- g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
- g_ram_wr_dat_w => g_data_w
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
+ g_ram_wr_dat_w => g_data_w
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- sla_out => sla_out,
- sla_in => sla_in,
+ sla_out => sla_out,
+ sla_in => sla_in,
- snk_in => split_sosi_arr(0),
- snk_out => split_siso_arr(0)
- );
+ snk_in => split_sosi_arr(0),
+ snk_out => split_siso_arr(0)
+ );
split_siso_arr(1) <= src_in;
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_nof_symbols
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_nof_symbols
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
index 18f45d4172772ae7d951e0ba97e3e48587ac4d40..8a533782734157475d0da541c6cd5f92b81eb5f5 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Hold hld_ctrl active until next ready high when in_ctrl is active while
@@ -55,11 +55,11 @@ begin
lo_ctrl <= not in_ctrl and ready; -- release
u_hld_ctrl : entity common_lib.common_switch
- port map (
- rst => rst,
- clk => clk,
- switch_high => hi_ctrl,
- switch_low => lo_ctrl,
- out_level => hld_ctrl
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ switch_high => hi_ctrl,
+ switch_low => lo_ctrl,
+ out_level => hld_ctrl
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_data.vhd b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
index 73323f54a670ad0964049c4abab32b1f73d155fe..dfe08d216edf0bf97a208fcdf84b4d4bf043cbbe 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Hold the in_data value when in_en is inactive. The held data can then be
diff --git a/libraries/base/dp/src/vhdl/dp_hold_input.vhd b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
index f5e5dd457290a39832a7dcdf3dffa7825be25b59..9a5f8afccae83f65b55374e94986b49ff704e8db 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_input.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Hold the sink input
@@ -90,40 +90,40 @@ begin
-- of a next packet to get pushed out.
u_hold_val : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.valid,
- hld_ctrl => hold_in.valid
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.valid,
+ hld_ctrl => hold_in.valid
+ );
u_hold_sync : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sync,
- hld_ctrl => hold_in.sync
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sync,
+ hld_ctrl => hold_in.sync
+ );
u_hold_sop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.sop,
- hld_ctrl => hold_in.sop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.sop,
+ hld_ctrl => hold_in.sop
+ );
u_hold_eop : entity work.dp_hold_ctrl
- port map (
- rst => rst,
- clk => clk,
- ready => src_in.ready,
- in_ctrl => snk_in.eop,
- hld_ctrl => hold_in.eop
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ ready => src_in.ready,
+ in_ctrl => snk_in.eop,
+ hld_ctrl => hold_in.eop
+ );
p_pend_src_out : process(snk_in, src_out_reg, hold_in)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 5335ee16ed78480f4a624009dcb6de60297a4bb6..7f5f4bbbd59cfe8f1cb6b4cd53f54be41042d93b 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra
@@ -189,17 +189,17 @@ begin
-- Pipeline output to easy timing closure
u_pipeline_output : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => out_siso,
- snk_in => out_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_pipeline => g_pipeline -- 0 for wires, > 0 for registers
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => out_siso,
+ snk_in => out_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
index 237ba315c23b67c8082df66a5a01bf0b5e270a41..b9a8a777f57e64dc20cb4997586af27eb2051187 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Adapt the g_in_latency input ready to the g_out_latency output latency.
@@ -103,20 +103,20 @@ begin
no_fifo : if c_diff_latency > 0 generate -- g_out_latency > g_in_latency
-- Go from g_in_latency to required larger g_out_latency
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => c_diff_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => c_diff_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate no_fifo;
gen_fifo : if c_diff_latency < 0 generate -- g_out_latency < g_in_latency
@@ -235,19 +235,19 @@ begin
-- Go from 0 FIFO latency to required g_out_latency (only wires when g_out_latency=0)
u_latency : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => ff_siso,
- snk_in => ff_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => ff_siso,
+ snk_in => ff_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate gen_fifo;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
index 77c10e03b932bb464eae94ee8ad2a69cc47d5968..aa47b3f121210d37ba2d266b6097a0f36127cfe1 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Simple DP fifo in registers.
-- Description:
@@ -48,16 +48,16 @@ entity dp_latency_fifo is
rst : in std_logic;
clk : in std_logic;
-- Monitor FIFO filling
- usedw : out std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0); -- +3 to match dp_latency_adapter usedw width
- wr_ful : out std_logic;
- rd_emp : out std_logic;
- -- ST sink
- snk_out : out t_dp_siso;
- snk_in : in t_dp_sosi;
- -- ST source
- src_in : in t_dp_siso;
- src_out : out t_dp_sosi
- );
+ usedw : out std_logic_vector(ceil_log2(2 + g_input_rl + g_fifo_size) - 1 downto 0); -- +3 to match dp_latency_adapter usedw width
+wr_ful : out std_logic;
+rd_emp : out std_logic;
+-- ST sink
+snk_out : out t_dp_siso;
+snk_in : in t_dp_sosi;
+-- ST source
+src_in : in t_dp_siso;
+src_out : out t_dp_sosi
+);
end dp_latency_fifo;
architecture rtl of dp_latency_fifo is
@@ -75,50 +75,49 @@ begin
no_bypass : if g_bypass = false generate
snk_out <= i_snk_out;
- usedw <= i_usedw;
+ usedw <= i_usedw;
- -- pass on frame level flow control
- i_snk_out.xon <= src_in.xon;
+-- pass on frame level flow control
+i_snk_out.xon <= src_in.xon;
- -- pass on sample level flow control similar as in dp_latency_adapter but now with extra margin of g_fifo_size
- p_snk_out_ready : process(i_usedw, fifo_snk_out, snk_in) -- equivalent to p_snk_out_ready in dp_latency_adapter
- begin
- i_snk_out.ready <= '0';
- if fifo_snk_out.ready = '1' then -- equivalent to ff_siso.ready in dp_latency_adapter
- -- Default snk_out ready when the source is ready.
- i_snk_out.ready <= '1';
- else
- -- Extra snk_out ready to look ahead for fifo_snk_out RL = 0 and to fill the FIFO.
- if TO_UINT(i_usedw) < c_adapter_input_rl then -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
- i_snk_out.ready <= '1';
- elsif TO_UINT(i_usedw) = c_adapter_input_rl then -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
- i_snk_out.ready <= not(snk_in.valid);
- end if;
- end if;
- end process;
+-- pass on sample level flow control similar as in dp_latency_adapter but now with extra margin of g_fifo_size
+p_snk_out_ready : process(i_usedw, fifo_snk_out, snk_in) -- equivalent to p_snk_out_ready in dp_latency_adapter
+begin
+ i_snk_out.ready <= '0';
+ if fifo_snk_out.ready = '1' then -- equivalent to ff_siso.ready in dp_latency_adapter
+ -- Default snk_out ready when the source is ready.
+ i_snk_out.ready <= '1';
+ else
+ -- Extra snk_out ready to look ahead for fifo_snk_out RL = 0 and to fill the FIFO.
+ if TO_UINT(i_usedw) < c_adapter_input_rl then -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
+ i_snk_out.ready <= '1';
+ elsif TO_UINT(i_usedw) = c_adapter_input_rl then -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
+ i_snk_out.ready <= not(snk_in.valid);
+ end if;
+ end if;
+end process;
- -- define FIFO full as not ready for new input
- wr_ful <= not i_snk_out.ready;
-
- u_dp_latency_adapter : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_adapter_input_rl,
- g_out_latency => c_adapter_output_rl
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor internal FIFO filling
- fifo_usedw => i_usedw,
- fifo_ful => OPEN,
- fifo_emp => rd_emp,
- -- ST sink
- snk_out => fifo_snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
- end generate;
+-- define FIFO full as not ready for new input
+wr_ful <= not i_snk_out.ready;
+u_dp_latency_adapter : entity work.dp_latency_adapter
+ generic map (
+ g_in_latency => c_adapter_input_rl,
+ g_out_latency => c_adapter_output_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor internal FIFO filling
+ fifo_usedw => i_usedw,
+ fifo_ful => OPEN,
+ fifo_emp => rd_emp,
+ -- ST sink
+ snk_out => fifo_snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
+end generate;
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
index 4ac0f424655f72c0f6114bed98c449bfec17a798..6f5f972bfb308f5e2d936e2a6ce162f9a9d142ee 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Typically used in dp_latency_adapter.
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index c28f0223b38c2075e710c0decdd323ac3b4d3bc6..5dcdd4d6a86d032a30d0ce958fa6e1cd3089033b 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -19,10 +19,10 @@
--
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- General function:
-- =================
@@ -141,82 +141,82 @@ begin
demux_1_siso_arr(2) <= c_dp_siso_flush;
u_dp_demux_0: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(0),
- snk_in => snk_in_arr(0),
-
- src_in_arr => demux_0_siso_arr,
- src_out_arr => demux_0_sosi_arr,
-
- sel_ctrl => demux_0_sel_ctrl,
- sel_stat => demux_0_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(0),
+ snk_in => snk_in_arr(0),
+
+ src_in_arr => demux_0_siso_arr,
+ src_out_arr => demux_0_sosi_arr,
+
+ sel_ctrl => demux_0_sel_ctrl,
+ sel_stat => demux_0_sel_stat
+ );
u_dp_demux_1: entity work.dp_demux
- generic map (
- g_mode => 2,
- g_nof_output => c_nof_demux_out,
- g_combined => false,
- g_sel_ctrl_invert => true,
- g_sel_ctrl_pkt => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => snk_out_arr(1),
- snk_in => snk_in_arr(1),
-
- src_in_arr => demux_1_siso_arr,
- src_out_arr => demux_1_sosi_arr,
-
- sel_ctrl => demux_1_sel_ctrl,
- sel_stat => demux_1_sel_stat
- );
+ generic map (
+ g_mode => 2,
+ g_nof_output => c_nof_demux_out,
+ g_combined => false,
+ g_sel_ctrl_invert => true,
+ g_sel_ctrl_pkt => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => snk_out_arr(1),
+ snk_in => snk_in_arr(1),
+
+ src_in_arr => demux_1_siso_arr,
+ src_out_arr => demux_1_sosi_arr,
+
+ sel_ctrl => demux_1_sel_ctrl,
+ sel_stat => demux_1_sel_stat
+ );
u_dp_mux_0 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => mux_0_siso_arr,
- snk_in_arr => mux_0_sosi_arr,
+ snk_out_arr => mux_0_siso_arr,
+ snk_in_arr => mux_0_sosi_arr,
- src_in => src_in_arr(0),
- src_out => src_out_arr(0),
+ src_in => src_in_arr(0),
+ src_out => src_out_arr(0),
- sel_ctrl => mux_0_sel_ctrl
- );
+ sel_ctrl => mux_0_sel_ctrl
+ );
u_dp_mux_1 : entity work.dp_mux
- generic map (
- g_mode => 2,
- g_sel_ctrl_invert => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => mux_1_siso_arr,
- snk_in_arr => mux_1_sosi_arr,
-
- src_in => src_in_arr(1),
- src_out => src_out_arr(1),
-
- sel_ctrl => mux_1_sel_ctrl
- );
+ generic map (
+ g_mode => 2,
+ g_sel_ctrl_invert => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => mux_1_siso_arr,
+ snk_in_arr => mux_1_sosi_arr,
+
+ src_in => src_in_arr(1),
+ src_out => src_out_arr(1),
+
+ sel_ctrl => mux_1_sel_ctrl
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index e1d72e765470b99f38d81a638c15b4030bac8aaa..19ba3df61bf4d9bf362cd77002de7704602abd4d 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -23,10 +23,10 @@
-- passing stream in any way - it monitors the stream and keeps useful stats.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_mon is
generic (
@@ -59,16 +59,16 @@ begin
snk_accept <= snk_in.valid when g_latency > 0 else snk_in.valid and src_in.ready;
u_word_cntr : entity common_lib.common_counter
- generic map (
- g_width => 32,
- g_step_size => 1,
- g_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => clr,
- cnt_en => snk_accept,
- count => word_cnt
- );
+ generic map (
+ g_width => 32,
+ g_step_size => 1,
+ g_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => clr,
+ cnt_en => snk_accept,
+ count => word_cnt
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 9e15141bf0d0e2ed1434f088636abf7a57a8c1ce..b2e13601b472fc53fbb282edd06c48dca61ce193 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -79,11 +79,11 @@
-- use g_append_channel_lo=FALSE in combination with g_mode=2.
library IEEE,common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_mux is
generic (
@@ -209,36 +209,37 @@ begin
end process;
gen_input : for I in 0 to g_nof_input - 1 generate
+
gen_fifo : if g_use_fifo = true generate
u_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_fill => c_fifo_fill(I),
- g_fifo_size => c_fifo_size(I),
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_af_xon => g_fifo_af_xon,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => i_snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => rd_siso_arr(I),
- src_out => rd_sosi_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_fill => c_fifo_fill(I),
+ g_fifo_size => c_fifo_size(I),
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_af_xon => g_fifo_af_xon,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => i_snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => rd_siso_arr(I),
+ src_out => rd_sosi_arr(I)
+ );
end generate;
no_fifo : if g_use_fifo = false generate
@@ -248,18 +249,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN, -- SISO ready
- snk_in => rd_sosi_arr(I), -- SOSI
- -- ST source
- src_in => hold_src_in_arr(I), -- SISO ready
- next_src_out => next_src_out_arr(I), -- SOSI
- pend_src_out => pend_src_out_arr(I),
- src_out_reg => src_out_hi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN, -- SISO ready
+ snk_in => rd_sosi_arr(I), -- SOSI
+ -- ST source
+ src_in => hold_src_in_arr(I), -- SISO ready
+ next_src_out => next_src_out_arr(I), -- SOSI
+ pend_src_out => pend_src_out_arr(I),
+ src_out_reg => src_out_hi
+ );
end generate;
-- Register and adjust external MM sel_ctrl for g_sel_ctrl_invert
@@ -289,16 +290,16 @@ begin
gen_sel_ctrl_framed : if g_mode = 4 generate
u_dp_frame_busy_arr : entity work.dp_frame_busy_arr
- generic map (
- g_nof_inputs => g_nof_input,
- g_pipeline => 1 -- register snk_in_busy to ease timing closure
- )
- port map (
- rst => rst,
- clk => clk,
- snk_in_arr => rd_sosi_arr,
- snk_in_busy_arr => rd_sosi_busy_arr
- );
+ generic map (
+ g_nof_inputs => g_nof_input,
+ g_pipeline => 1 -- register snk_in_busy to ease timing closure
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_in_arr => rd_sosi_arr,
+ snk_in_busy_arr => rd_sosi_busy_arr
+ );
hold_src_in_arr <= (others => c_dp_siso_rdy); -- effectively bypass the dp_hold_input
@@ -337,6 +338,7 @@ begin
end generate;
gen_framed : if g_mode = 0 or g_mode = 1 or g_mode = 3 generate
+
p_hold_src_in_arr : process(rd_siso_arr, pend_src_out_arr, in_sel, src_in)
begin
hold_src_in_arr <= rd_siso_arr; -- default ready for hold input when ready for sink input
@@ -410,7 +412,5 @@ begin
end if;
end loop;
end process;
-
end generate;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 374201d300f1a3efa12bd2673c87a690242d40b7..983a796812ab73ed859c1c9eef441f40959fb4a9 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -40,12 +40,12 @@
-- control the snk_out_arr empty field.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx is
generic (
@@ -109,21 +109,21 @@ begin
---------------------------------------------------------------------------------------
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => c_nof_header_symbols
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => c_nof_header_symbols
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
-- In dp_split index 0 is head and index 1 is tail, but dp_split uses 0 TO
-- 1 range and dp_split_src_in_2arr()() uses 1 DOWNTO 0 range, so:
@@ -138,32 +138,32 @@ begin
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
- g_field_sel => c_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
- g_in_symbol_w => c_symbol_w,
- g_out_symbol_w => c_symbol_w,
- g_mode => 2 -- sink mode
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
+ g_field_sel => c_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
+ g_in_symbol_w => c_symbol_w,
+ g_out_symbol_w => c_symbol_w,
+ g_mode => 2 -- sink mode
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
- src_out => dp_field_blk_src_out_arr(i),
+ src_out => dp_field_blk_src_out_arr(i),
--- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
--- slv_out_val => dp_field_blk_slv_out_val(i),
+ -- slv_out => dp_field_blk_slv_out(i)(field_slv_len(g_hdr_field_arr)-1 DOWNTO 0),
+ -- slv_out_val => dp_field_blk_slv_out_val(i),
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_slv_out(i)(c_dp_field_blk_src_data_w - 1 downto 0) <= dp_field_blk_src_out_arr(i).data(c_dp_field_blk_src_data_w - 1 downto 0);
dp_field_blk_slv_out_val(i) <= dp_field_blk_src_out_arr(i).valid;
@@ -174,21 +174,21 @@ begin
---------------------------------------------------------------------------------------
gen_dp_tail_remove : for i in 0 to g_nof_streams - 1 generate
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_symbol_w,
- g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- snk_out => dp_split_src_in_2arr(i)(0),
- snk_in => dp_split_src_out_2arr(i)(0), -- tail part
-
- src_in => dp_tail_remove_src_in_arr(i),
- src_out => dp_tail_remove_src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_symbol_w,
+ g_nof_symbols => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(0),
+ snk_in => dp_split_src_out_2arr(i)(0), -- tail part
+
+ src_in => dp_tail_remove_src_in_arr(i),
+ src_out => dp_tail_remove_src_out_arr(i)
+ );
end generate;
src_out_arr <= dp_tail_remove_src_out_arr;
@@ -224,14 +224,14 @@ begin
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index fe450e22c104ff81613d9c0de21b3d25672d2217..fe1fe3240b80541c4c689de4f7d46c494b61eecf 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -20,16 +20,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter is
generic (
- g_bypass : boolean := false;
+ g_bypass : boolean := false;
g_nof_streams : positive := 1;
g_data_w : natural;
g_hdr_field_arr : t_common_field_arr;
@@ -80,6 +80,7 @@ begin
end generate;
no_bypass : if g_bypass = false generate
+
p_comb : process(hdr_fields_out_arr, snk_in_arr, r, dp_rst)
variable v : reg_type;
begin
@@ -106,31 +107,32 @@ begin
v.valid(i) := '0';
end if;
end if;
- end loop check;
+ end loop check;
- if(dp_rst = '1') then
+ if(dp_rst = '1') then
v.src_out_arr := (others => c_dp_sosi_rst);
v.valid := (others => '0');
- end if;
-
- rin <= v;
- end process;
+ end if;
- process(r)
- begin
- src_out_arr <= r.src_out_arr;
- set_val : for i in 0 to g_nof_streams - 1 loop
- src_out_arr(i).valid <= r.valid(i) and r.src_out_arr(i).valid;
- src_out_arr(i).sop <= r.valid(i) and r.src_out_arr(i).sop;
- src_out_arr(i).eop <= r.valid(i) and r.src_out_arr(i).eop;
- end loop set_val;
- end process;
-
- p_regs : process(dp_clk)
- begin
- if rising_edge(dp_clk) then
- r <= rin;
- end if;
- end process;
- end generate;
-end str;
+ rin <= v;
+ end process;
+
+ process(r)
+ begin
+ src_out_arr <= r.src_out_arr;
+ set_val : for i in 0 to g_nof_streams - 1 loop
+ src_out_arr(i).valid <= r.valid(i) and r.src_out_arr(i).valid;
+ src_out_arr(i).sop <= r.valid(i) and r.src_out_arr(i).sop;
+ src_out_arr(i).eop <= r.valid(i) and r.src_out_arr(i).eop;
+ end loop set_val;
+ end process;
+
+ p_regs : process(dp_clk)
+ begin
+ if rising_edge(dp_clk) then
+ r <= rin;
+ end if;
+ end process;
+
+ end generate;
+ end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index d091171e52e44be574bade197cb2ce51d162e2b2..af6a025a5e220b91f062dcbb969ac3a9ccb5011f 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter_mm is
generic (
@@ -112,6 +112,7 @@ begin
end generate;
no_bypass : if g_bypass = false generate
+
p_comb : process(hdr_fields_to_check_arr, snk_in_arr, r, dp_rst)
variable v : reg_type;
begin
@@ -138,109 +139,109 @@ begin
v.valid(i) := '0';
end if;
end if;
- end loop check;
+ end loop check;
- if(dp_rst = '1') then
+ if(dp_rst = '1') then
v.src_out_arr := (others => c_dp_sosi_rst);
v.valid := (others => '0');
- end if;
-
- rin <= v;
- end process;
-
- process(r)
- begin
- src_out_arr <= r.src_out_arr;
- set_val : for i in 0 to g_nof_streams - 1 loop
- src_out_arr(i).valid <= r.valid(i) and r.src_out_arr(i).valid;
- src_out_arr(i).sop <= r.valid(i) and r.src_out_arr(i).sop;
- src_out_arr(i).eop <= r.valid(i) and r.src_out_arr(i).eop;
- end loop set_val;
- end process;
-
- p_regs : process(dp_clk)
- begin
- if rising_edge(dp_clk) then
- r <= rin;
- end if;
- end process;
-
- -------------------------------------------
- -- mm_fields for MM access to each field --
- -------------------------------------------
- u_mult_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
- )
- port map (
- mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
- miso => reg_dp_offload_rx_filter_hdr_fields_miso,
- mosi_arr => mult_streams_mosi_arr,
- miso_arr => mult_streams_miso_arr
- );
-
- gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
- u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => 2,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => mult_streams_mosi_arr(i),
- miso => mult_streams_miso_arr(i),
- mosi_arr => common_mosi_arr,
- miso_arr => common_miso_arr
- );
-
- eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
- ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
- ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
- udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
-
- cr : entity common_lib.common_reg_r_w_dc
- generic map(
- g_reg => c_ena_reg
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
- st_rst => dp_rst, -- reset synchronous with st_clk
- st_clk => dp_clk, -- other clock domain clock
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => reg_ena_sig(i),
- out_reg => reg_ena_sig(i),
- out_new => open
- );
-
- u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- mm_mosi => common_mosi_arr(0),
- mm_miso => common_miso_arr(0),
-
- slv_clk => dp_clk,
- slv_rst => dp_rst,
-
- slv_in => mm_fields_slv_in_arr(i),
- slv_in_val => hdr_fields_val,
- slv_out => mm_fields_slv_out_arr(i)
- );
- end generate;
+ end if;
- end generate;
-end str;
+ rin <= v;
+ end process;
+
+ process(r)
+ begin
+ src_out_arr <= r.src_out_arr;
+ set_val : for i in 0 to g_nof_streams - 1 loop
+ src_out_arr(i).valid <= r.valid(i) and r.src_out_arr(i).valid;
+ src_out_arr(i).sop <= r.valid(i) and r.src_out_arr(i).sop;
+ src_out_arr(i).eop <= r.valid(i) and r.src_out_arr(i).eop;
+ end loop set_val;
+ end process;
+
+ p_regs : process(dp_clk)
+ begin
+ if rising_edge(dp_clk) then
+ r <= rin;
+ end if;
+ end process;
+
+ -------------------------------------------
+ -- mm_fields for MM access to each field --
+ -------------------------------------------
+ u_mult_mem_mux : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w)) + 1
+ )
+ port map (
+ mosi => reg_dp_offload_rx_filter_hdr_fields_mosi,
+ miso => reg_dp_offload_rx_filter_hdr_fields_miso,
+ mosi_arr => mult_streams_mosi_arr,
+ miso_arr => mult_streams_miso_arr
+ );
+
+ gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
+ u_common_mem_mux : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => 2,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => mult_streams_mosi_arr(i),
+ miso => mult_streams_miso_arr(i),
+ mosi_arr => common_mosi_arr,
+ miso_arr => common_miso_arr
+ );
+
+ eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
+ ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
+ ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
+ udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
+
+ cr : entity common_lib.common_reg_r_w_dc
+ generic map(
+ g_reg => c_ena_reg
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+ st_rst => dp_rst, -- reset synchronous with st_clk
+ st_clk => dp_clk, -- other clock domain clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => reg_ena_sig(i),
+ out_reg => reg_ena_sig(i),
+ out_new => open
+ );
+
+ u_mm_fields_slv: entity mm_lib.mm_fields
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_mosi => common_mosi_arr(0),
+ mm_miso => common_miso_arr(0),
+
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
+
+ slv_in => mm_fields_slv_in_arr(i),
+ slv_in_val => hdr_fields_val,
+ slv_out => mm_fields_slv_out_arr(i)
+ );
+ end generate;
+
+ end generate;
+ end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
index cbe97b4e0fe8285b53674c2a8d6ce65844a04c4c..1f9eeadbdf95b9efd48038ea374262e2ccba3ef0 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_offload_rx_legacy is
generic (
@@ -63,63 +63,62 @@ architecture str of dp_offload_rx_legacy is
signal ram_hdr_remove_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_remove_ram_addr_w
- )
- port map (
- mosi => ram_hdr_remove_mosi,
- miso => ram_hdr_remove_miso,
- mosi_arr => ram_hdr_remove_mosi_arr,
- miso_arr => ram_hdr_remove_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_remove_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_remove_mosi,
+ miso => ram_hdr_remove_miso,
+ mosi_arr => ram_hdr_remove_mosi_arr,
+ miso_arr => ram_hdr_remove_miso_arr
+ );
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- RX: Unframe: remove header (and CRC if phy link is used) from DP packets
---------------------------------------------------------------------------------------
u_frame_remove : entity dp_lib.dp_frame_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words,
- g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => rx_siso_arr(i),
- snk_in => rx_sosi_arr(i),
-
- -- dp_frame_remove uses hdr_remove internally
- sla_in => ram_hdr_remove_mosi_arr(i),
- sla_out => ram_hdr_remove_miso_arr(i),
-
- src_in => rx_pkt_siso_arr(i),
- src_out => rx_pkt_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words,
+ g_tail_nof_words => sel_a_b(g_remove_crc, g_crc_nof_words, 0)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => rx_siso_arr(i),
+ snk_in => rx_sosi_arr(i),
+
+ -- dp_frame_remove uses hdr_remove internally
+ sla_in => ram_hdr_remove_mosi_arr(i),
+ sla_out => ram_hdr_remove_miso_arr(i),
+
+ src_in => rx_pkt_siso_arr(i),
+ src_out => rx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- RX: Convert DP packets to DP stream
---------------------------------------------------------------------------------------
u_dp_packet_dec : entity dp_lib.dp_packet_dec
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => rx_pkt_siso_arr(i),
- snk_in => rx_pkt_sosi_arr(i),
-
- src_in => dp_siso_arr(i),
- src_out => dp_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => rx_pkt_siso_arr(i),
+ snk_in => rx_pkt_sosi_arr(i),
+
+ src_in => dp_siso_arr(i),
+ src_out => dp_sosi_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index e88d96a678f6c1bb1baa800c0e18d7eba17b0c01..b82fb01a632d197cf1c321b2522e7fb7754410d9 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -41,13 +41,13 @@
-- Remarks:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx is
generic (
@@ -130,6 +130,7 @@ begin
---------------------------------------------------------------------------------------
-- use complex or data field
gen_wires_complex : if g_use_complex = true generate
+
p_wires_complex : process(snk_in_arr)
begin
for i in 0 to g_nof_streams - 1 loop
@@ -157,79 +158,79 @@ begin
snk_out_arr(i).xon <= src_in_arr(i).xon; -- Pass on XON from source side
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols => g_nof_words_per_block
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_split_snk_out_arr(i),
- snk_in => dp_split_snk_in_arr(i),
-
- src_in_arr => dp_split_src_in_2arr(i),
- src_out_arr => dp_split_src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols => g_nof_words_per_block
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_snk_out_arr(i),
+ snk_in => dp_split_snk_in_arr(i),
+
+ src_in_arr => dp_split_src_in_2arr(i),
+ src_out_arr => dp_split_src_out_2arr(i)
+ );
dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy; -- Always ready to throw away the tail
end generate;
-- Introduce the same delay (as dp_plit) on the corresponding header fields
u_dp_pipeline_arr_dp_split : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_split_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_snk_in_arr,
- snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
-
- src_out_arr => dp_split_hdr_fields_src_out_arr,
- src_in_arr => dp_split_hdr_fields_src_in_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_split_val_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => dp_split_hdr_fields_snk_in_arr,
+ snk_out_arr => OPEN, -- Flow control is already taken care of by dp_split
+
+ src_out_arr => dp_split_hdr_fields_src_out_arr,
+ src_in_arr => dp_split_hdr_fields_src_in_arr
+ );
---------------------------------------------------------------------------------------
-- Merge nof_blocks_per_packet
---------------------------------------------------------------------------------------
gen_dp_packet_merge : for i in 0 to g_nof_streams - 1 generate
u_dp_packet_merge : entity work.dp_packet_merge
+ generic map (
+ g_nof_pkt => g_nof_blocks_per_packet,
+ g_align_at_sync => g_pkt_merge_align_at_sync
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_split_src_in_2arr(i)(1),
+ snk_in => dp_split_src_out_2arr(i)(1),
+
+ src_in => dp_packet_merge_src_in_arr(i),
+ src_out => dp_packet_merge_src_out_arr(i)
+ );
+ end generate;
+
+ -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
+ u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
generic map (
- g_nof_pkt => g_nof_blocks_per_packet,
- g_align_at_sync => g_pkt_merge_align_at_sync
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_dp_packet_merge_val_latency
)
port map (
rst => dp_rst,
clk => dp_clk,
- snk_out => dp_split_src_in_2arr(i)(1),
- snk_in => dp_split_src_out_2arr(i)(1),
+ snk_in_arr => dp_split_hdr_fields_src_out_arr,
+ snk_out_arr => dp_split_hdr_fields_src_in_arr,
- src_in => dp_packet_merge_src_in_arr(i),
- src_out => dp_packet_merge_src_out_arr(i)
+ src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
+ src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
);
- end generate;
-
- -- Introduce the same delay (as dp_packet_merge) on the corresponding header fields
- u_dp_pipeline_arr_dp_packet_merge : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_dp_packet_merge_val_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in_arr => dp_split_hdr_fields_src_out_arr,
- snk_out_arr => dp_split_hdr_fields_src_in_arr,
-
- src_out_arr => dp_packet_merge_hdr_fields_src_out_arr,
- src_in_arr => dp_packet_merge_hdr_fields_src_in_arr
- );
-- dp_packet_merge_hdr_fields_src_out_arr contains a valid header for each block that was merged
-- into one packet. We want only the first valid header per merged block to be forwarded to
@@ -259,22 +260,22 @@ begin
---------------------------------------------------------------------------------------
gen_dp_fifo_fill : for i in 0 to sel_a_b(g_use_post_split_fifo, g_nof_streams, 0) - 1 generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_fifo_fill => c_dp_fifo_fill,
- g_fifo_size => c_dp_fifo_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_packet_merge_src_out_arr(i),
- snk_out => dp_packet_merge_src_in_arr(i),
-
- src_out => dp_fifo_fill_src_out_arr(i),
- src_in => dp_fifo_fill_src_in_arr(i)
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_packet_merge_src_out_arr(i),
+ snk_out => dp_packet_merge_src_in_arr(i),
+
+ src_out => dp_fifo_fill_src_out_arr(i),
+ src_in => dp_fifo_fill_src_in_arr(i)
+ );
dp_fifo_fill_src_in_arr(i).ready <= dp_concat_snk_out_2arr(i)(0).ready;
dp_fifo_fill_src_in_arr(i).xon <= '1'; -- Prevents flushing of frames
@@ -293,60 +294,60 @@ begin
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_in => dp_concat_snk_out_2arr(i)(1),
- src_out => dp_concat_snk_in_2arr(i)(1),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_in => dp_concat_snk_out_2arr(i)(1),
+ src_out => dp_concat_snk_in_2arr(i)(1),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
end generate;
gen_dp_concat : for i in 0 to g_nof_streams - 1 generate
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b3101b542d49ef12cdf05b2c8b84defdf25134d4..59a205f860b8484ecf12a154bc594df528c05b52 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, work;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_offload_tx_legacy is
generic (
@@ -113,30 +113,31 @@ architecture str of dp_offload_tx_legacy is
signal ram_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux_hdr_reg : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_reg_addr_w
- )
- port map (
- mosi => reg_hdr_insert_mosi,
- mosi_arr => reg_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_reg_addr_w
+ )
+ port map (
+ mosi => reg_hdr_insert_mosi,
+ mosi_arr => reg_hdr_insert_mosi_arr
+ );
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_hdr_insert_ram_addr_w
- )
- port map (
- mosi => ram_hdr_insert_mosi,
- mosi_arr => ram_hdr_insert_mosi_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_hdr_insert_ram_addr_w
+ )
+ port map (
+ mosi => ram_hdr_insert_mosi,
+ mosi_arr => ram_hdr_insert_mosi_arr
+ );
gen_nof_streams0: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- Select complex input if required
---------------------------------------------------------------------------------------
gen_complex_in : if g_use_complex = true generate
+
p_connect : process(dp_sosi_arr(i))
begin
dp_sel_sosi_arr(i) <= dp_sosi_arr(i);
@@ -154,60 +155,59 @@ begin
---------------------------------------------------------------------------------------
gen_input_buffer : if g_use_input_fifo = true generate
u_buf : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => 10 -- Use 10 as there's a FIFO margin
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_siso_arr(i),
- snk_in => dp_sel_sosi_arr(i),
-
- src_in => dp_to_split_siso_arr(i),
- src_out => dp_to_split_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => 10 -- Use 10 as there's a FIFO margin
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_siso_arr(i),
+ snk_in => dp_sel_sosi_arr(i),
+
+ src_in => dp_to_split_siso_arr(i),
+ src_out => dp_to_split_sosi_arr(i)
+ );
end generate;
-
end generate;
---------------------------------------------------------------------------------------
-- Throw away words 0..g_block_nof_sel_words-1 of block (0..g_block_size-1)
---------------------------------------------------------------------------------------
u_mms_dp_split : entity work.mms_dp_split
- generic map (
- g_nof_streams => g_nof_streams,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
-
- snk_out_arr => dp_to_split_siso_arr,
- snk_in_arr => dp_to_split_sosi_arr,
-
- src_in_2arr => dp_from_split_siso_2arr,
- src_out_2arr => dp_from_split_sosi_2arr,
-
- reg_mosi => reg_dp_split_mosi,
- reg_miso => reg_dp_split_miso
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_nof_symbols_max => g_block_nof_sel_words * (g_data_w / c_byte_w)
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ snk_out_arr => dp_to_split_siso_arr,
+ snk_in_arr => dp_to_split_sosi_arr,
+
+ src_in_2arr => dp_from_split_siso_2arr,
+ src_out_2arr => dp_from_split_sosi_2arr,
+
+ reg_mosi => reg_dp_split_mosi,
+ reg_miso => reg_dp_split_miso
+ );
gen_nof_streams1: for i in 0 to g_nof_streams - 1 generate
dp_from_split_siso_2arr(i)(0) <= c_dp_siso_rdy;
@@ -220,37 +220,36 @@ begin
---------------------------------------------------------------------------------------
gen_input_fifo : if g_use_input_fifo = true generate
u_input_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => g_input_fifo_bsn_w,
- g_empty_w => g_input_fifo_empty_w,
- g_channel_w => g_input_fifo_channel_w,
- g_error_w => g_input_fifo_error_w,
- g_use_bsn => g_input_fifo_use_bsn,
- g_use_empty => g_input_fifo_use_empty,
- g_use_channel => g_input_fifo_use_channel,
- g_use_error => g_input_fifo_use_error,
- g_use_sync => g_input_fifo_use_sync,
- g_use_ctrl => true,
- g_fifo_size => c_input_fifo_size
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => dp_from_split_siso_2arr(i)(1),
- snk_in => dp_from_split_sosi_2arr(i)(1),
-
- src_in => dp_to_pkt_merge_siso_arr(i),
- src_out => dp_to_pkt_merge_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => g_input_fifo_bsn_w,
+ g_empty_w => g_input_fifo_empty_w,
+ g_channel_w => g_input_fifo_channel_w,
+ g_error_w => g_input_fifo_error_w,
+ g_use_bsn => g_input_fifo_use_bsn,
+ g_use_empty => g_input_fifo_use_empty,
+ g_use_channel => g_input_fifo_use_channel,
+ g_use_error => g_input_fifo_use_error,
+ g_use_sync => g_input_fifo_use_sync,
+ g_use_ctrl => true,
+ g_fifo_size => c_input_fifo_size
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_from_split_siso_2arr(i)(1),
+ snk_in => dp_from_split_sosi_2arr(i)(1),
+
+ src_in => dp_to_pkt_merge_siso_arr(i),
+ src_out => dp_to_pkt_merge_sosi_arr(i)
+ );
end generate;
no_input_fifo : if g_use_input_fifo = false generate
dp_to_pkt_merge_sosi_arr(i) <= dp_from_split_sosi_2arr(i)(1);
dp_siso_arr(i) <= dp_to_pkt_merge_siso_arr(i);
end generate;
-
end generate;
---------------------------------------------------------------------------------------
@@ -259,102 +258,102 @@ begin
-- G_nof_pkt packets are merged into 1.
---------------------------------------------------------------------------------------
u_dp_packet_merge : entity work.mms_dp_packet_merge
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_pkt => g_nof_words_per_pkt -- Support merging 360*1 word
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_rst => st_rst,
- dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_clk => st_clk,
- snk_out_arr => dp_to_pkt_merge_siso_arr,
- snk_in_arr => dp_to_pkt_merge_sosi_arr,
+ snk_out_arr => dp_to_pkt_merge_siso_arr,
+ snk_in_arr => dp_to_pkt_merge_sosi_arr,
- src_in_arr => dp_merged_siso_arr,
- src_out_arr => dp_merged_sosi_arr,
+ src_in_arr => dp_merged_siso_arr,
+ src_out_arr => dp_merged_sosi_arr,
- reg_mosi => reg_dp_pkt_merge_mosi,
- reg_miso => reg_dp_pkt_merge_miso
- );
+ reg_mosi => reg_dp_pkt_merge_mosi,
+ reg_miso => reg_dp_pkt_merge_miso
+ );
gen_nof_streams3: for i in 0 to g_nof_streams - 1 generate
---------------------------------------------------------------------------------------
-- Convert DP to packetized DP
---------------------------------------------------------------------------------------
u_dp_packet_enc : entity work.dp_packet_enc
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => st_rst,
- clk => st_clk,
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
- snk_out => dp_merged_siso_arr(i),
- snk_in => dp_merged_sosi_arr(i),
+ snk_out => dp_merged_siso_arr(i),
+ snk_in => dp_merged_sosi_arr(i),
- src_in => udp_tx_pkt_siso_arr(i),
- src_out => udp_tx_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_pkt_siso_arr(i),
+ src_out => udp_tx_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- Add header to DP packet
---------------------------------------------------------------------------------------
u_hdr_insert : entity work.dp_hdr_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => c_byte_w,
- g_hdr_nof_words => g_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => c_byte_w,
+ g_hdr_nof_words => g_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- reg_mosi => reg_hdr_insert_mosi_arr(i),
- ram_mosi => ram_hdr_insert_mosi_arr(i),
+ reg_mosi => reg_hdr_insert_mosi_arr(i),
+ ram_mosi => ram_hdr_insert_mosi_arr(i),
- snk_out => udp_tx_pkt_siso_arr(i),
- snk_in => udp_tx_pkt_sosi_arr(i),
+ snk_out => udp_tx_pkt_siso_arr(i),
+ snk_in => udp_tx_pkt_sosi_arr(i),
- src_in => udp_tx_hdr_pkt_siso_arr(i),
- src_out => udp_tx_hdr_pkt_sosi_arr(i)
- );
+ src_in => udp_tx_hdr_pkt_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_sosi_arr(i)
+ );
---------------------------------------------------------------------------------------
-- FIFO so we can deliver packets to the ETH module fast enough
---------------------------------------------------------------------------------------
gen_output_fifo: if g_use_output_fifo = true generate
u_dp_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 0,
- g_empty_w => 0,
- g_channel_w => 0,
- g_error_w => 0,
- g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
- g_fifo_size => c_output_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => st_rst,
- clk => st_clk,
-
- snk_out => udp_tx_hdr_pkt_siso_arr(i),
- snk_in => udp_tx_hdr_pkt_sosi_arr(i),
-
- src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
- src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 0,
+ g_empty_w => 0,
+ g_channel_w => 0,
+ g_error_w => 0,
+ g_use_bsn => false, -- Don't forward these as all have been encoded by dp_packet_enc
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_fifo_fill => c_output_fifo_fill, -- Release packet only when available
+ g_fifo_size => c_output_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => udp_tx_hdr_pkt_siso_arr(i),
+ snk_in => udp_tx_hdr_pkt_sosi_arr(i),
+
+ src_in => udp_tx_hdr_pkt_fifo_siso_arr(i),
+ src_out => udp_tx_hdr_pkt_fifo_sosi_arr(i)
+ );
udp_tx_hdr_pkt_fifo_siso_arr(i) <= tx_siso_arr(i);
tx_sosi_arr(i) <= udp_tx_hdr_pkt_fifo_sosi_arr(i);
@@ -364,6 +363,5 @@ begin
udp_tx_hdr_pkt_siso_arr(i) <= tx_siso_arr(i);
tx_sosi_arr(i) <= udp_tx_hdr_pkt_sosi_arr(i);
end generate;
-
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
index e95ac25810282d2f48184619c5af08280dfee4f5..875790d779c48017ffd80afd88f080a5c696e393 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use technology_lib.technology_select_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.common_field_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use technology_lib.technology_select_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_field_pkg.all;
-- Purpose:
-- . Calculate UDP total length and IP total length fields
@@ -82,25 +82,25 @@ begin
-- Calculate number of payload words
---------------------------------------------------------------------------------------
u_common_mult: entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "RTL",
- g_in_a_w => nof_words_per_block'LENGTH,
- g_in_b_w => nof_blocks_per_packet'LENGTH,
- g_out_p_w => c_product_w,
- g_pipeline_input => 0,
- g_pipeline_product => 0,
- g_pipeline_output => 0,
- g_representation => "UNSIGNED"
- )
- port map (
- rst => rst,
- clk => clk,
- clken => '1',
- in_a => nof_words_per_block,
- in_b => nof_blocks_per_packet,
- out_p => nof_data_words
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "RTL",
+ g_in_a_w => nof_words_per_block'LENGTH,
+ g_in_b_w => nof_blocks_per_packet'LENGTH,
+ g_out_p_w => c_product_w,
+ g_pipeline_input => 0,
+ g_pipeline_product => 0,
+ g_pipeline_output => 0,
+ g_representation => "UNSIGNED"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => '1',
+ in_a => nof_words_per_block,
+ in_b => nof_blocks_per_packet,
+ out_p => nof_data_words
+ );
---------------------------------------------------------------------------------------
-- Calculate number of payload bytes by bit shifting to the left
@@ -113,18 +113,18 @@ begin
udp_adder_in <= RESIZE_UVEC(nof_data_bytes, c_adder_in_w) & TO_UVEC(c_udp_header_len, c_adder_in_w) & TO_UVEC(c_user_hdr_len, c_adder_in_w);
u_common_adder_tree_udp : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 3,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 2
- )
- port map (
- clk => clk,
- in_dat => udp_adder_in,
- sum => udp_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 3,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 2
+ )
+ port map (
+ clk => clk,
+ in_dat => udp_adder_in,
+ sum => udp_adder_out
+ );
udp_total_length <= udp_adder_out(c_adder_in_w - 1 downto 0);
@@ -134,18 +134,18 @@ begin
ip_adder_in <= RESIZE_UVEC(udp_adder_out, c_adder_in_w) & TO_UVEC(c_ip_header_len, c_adder_in_w);
u_common_adder_tree_ip : entity common_lib.common_adder_tree(str)
- generic map (
- g_representation => "UNSIGNED",
- g_pipeline => 0,
- g_nof_inputs => 2,
- g_dat_w => c_adder_in_w,
- g_sum_w => c_adder_in_w + 1
- )
- port map (
- clk => clk,
- in_dat => ip_adder_in,
- sum => ip_adder_out
- );
+ generic map (
+ g_representation => "UNSIGNED",
+ g_pipeline => 0,
+ g_nof_inputs => 2,
+ g_dat_w => c_adder_in_w,
+ g_sum_w => c_adder_in_w + 1
+ )
+ port map (
+ clk => clk,
+ in_dat => ip_adder_in,
+ sum => ip_adder_out
+ );
ip_total_length <= ip_adder_out(c_adder_in_w - 1 downto 0);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index 4242e252a3c9ef2f0df6c281231fb367de73f503..02c4b9e35c61b7d14c790d98177eeb2e174907ca 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -40,13 +40,13 @@
-- bits in the header and data are an integer number of g_data_w.
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_offload_tx_v3 is
generic (
@@ -151,50 +151,50 @@ begin
-- mm_fields for MM access to each field
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
- generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_hdr_dat_mosi_arr(i),
- mm_miso => OPEN, -- Not used
+ mm_mosi => reg_hdr_dat_mosi_arr(i),
+ mm_miso => OPEN, -- Not used
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
- );
+ slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
+ );
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
- generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w,
- g_in_symbol_w => g_symbol_w,
- g_out_symbol_w => g_symbol_w,
- g_pipeline_ready => g_pipeline_ready,
- g_mode => 1 -- source mode
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in => dp_field_blk_snk_in_arr(i),
- snk_out => dp_field_blk_snk_out_arr(i),
-
- src_out => dp_field_blk_src_out_arr(i),
- src_in => dp_field_blk_src_in_arr(i),
-
- reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
- reg_slv_miso => reg_hdr_dat_miso_arr(i)
- );
+ generic map (
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_symbol_w,
+ g_out_symbol_w => g_symbol_w,
+ g_pipeline_ready => g_pipeline_ready,
+ g_mode => 1 -- source mode
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in => dp_field_blk_snk_in_arr(i),
+ snk_out => dp_field_blk_snk_out_arr(i),
+
+ src_out => dp_field_blk_src_out_arr(i),
+ src_in => dp_field_blk_src_in_arr(i),
+
+ reg_slv_mosi => reg_hdr_dat_mosi_arr(i),
+ reg_slv_miso => reg_hdr_dat_miso_arr(i)
+ );
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
end generate;
@@ -205,34 +205,34 @@ begin
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_concat_snk_out_2arr(i),
- snk_in_arr => dp_concat_snk_in_2arr(i),
-
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_concat_snk_out_2arr(i),
+ snk_in_arr => dp_concat_snk_in_2arr(i),
+
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
---------------------------------------------------------------------------------------
-- MM control & monitoring
---------------------------------------------------------------------------------------
u_common_mem_mux_hdr_dat : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
- )
- port map (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(g_hdr_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_hdr_dat_mosi,
+ miso => reg_hdr_dat_miso,
+ mosi_arr => reg_hdr_dat_mosi_arr,
+ miso_arr => reg_hdr_dat_miso_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 6839ff8a6e9c3ed0002b16aa24b6797b05d973a1..5dc1a3f73a9419d36fd3a52ef74ddacf9c00d9e6 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -20,11 +20,11 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
-- Purpose: Decode DP packet to DP sosi.
-- Description:
@@ -176,18 +176,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, src_in, channel, bsn, cnt, blk_sosi, next_src_buf)
@@ -282,25 +282,25 @@ begin
-- Handle output error field and eop
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_shiftreg_len
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => blk_sosi,
- -- Control shift register contents
- cur_shiftreg_inputs => cur_src_out_inputs,
- new_shiftreg_inputs => new_src_out_inputs,
- -- ST source
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_shiftreg_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => blk_sosi,
+ -- Control shift register contents
+ cur_shiftreg_inputs => cur_src_out_inputs,
+ new_shiftreg_inputs => new_src_out_inputs,
+ -- ST source
+ src_in => src_in,
+ src_out => i_src_out
+ );
p_src_err : process(cur_src_out_inputs)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index 2fe927abf47a45fb41f062c448edc272edc57107..34ba272f9da58b5a618e2b07a7feb57751c73f39 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Decode sosi.channel low bits from the high part of the CHAN field
-- of a DP packet.
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 08011772520ca371f8a98548e918e3421cd0749a..9b2b5f7c60a8d5985f7761b6daacef8e24d292b0 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Assert output during a packet on the input:
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 489bdc80ecd39d220969de42577ec54e6c80d6ab..3466dd66341406c43b3aca05d0671cc2723edcb2 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packet_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packet_pkg.all;
-- Purpose: Encode DP sosi to DP packet.
-- Description:
@@ -151,18 +151,18 @@ begin
nxt_src_buf <= next_src_buf;
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => pend_src_buf,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => pend_src_buf,
+ src_out_reg => src_buf
+ );
-- State machine
p_state : process(state, cnt, src_in, pend_src_buf, i_src_out, in_err)
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index 9ce09443d742a8d82c09aa0a9806371148a39306..93b3b66207aa7e1fe2da55c52c2053427a512eb8 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose: Encode sosi.channel low bit into the high part of the CHAN field of
-- a DP packet.
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 2de0853cc9f7d0b773b10ae9a3b8dd7e0e7944e0..9f96a14329d123e4b3753344e69319cb039f3eda 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -49,12 +49,11 @@
-- . The input packets do not have to have equal length, because they are
-- merged based on counting their eop.
-
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_merge is
generic (
@@ -95,7 +94,7 @@ architecture rtl of dp_packet_merge is
src_out : t_dp_sosi;
end record;
- constant c_reg_rst : t_reg := (0, 0, 0, '0', '0', (others =>'0'), '0', c_dp_sosi_rst);
+ constant c_reg_rst : t_reg := (0, 0, 0, '0', '0', (others => '0'), '0', c_dp_sosi_rst);
signal r, nxt_r : t_reg;
begin
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index 76c65b3a90f6e54de9e7edd5d6a88f58d74c8f24..5d3b55f0408520c3820ac1e8d2f8aa87e38e7e96 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -20,8 +20,8 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
package dp_packet_pkg is
------------------------------------------------------------------------------
@@ -60,8 +60,8 @@ package body dp_packet_pkg is
begin
-- Calculate the total DP PACKET overhead length of header (channel and bsn words) + lenght of tail (error words).
return ceil_div(c_dp_packet_channel_w, c_data_w) +
- ceil_div(c_dp_packet_bsn_w, c_data_w) +
- ceil_div(c_dp_packet_error_w, c_data_w);
+ ceil_div(c_dp_packet_bsn_w, c_data_w) +
+ ceil_div(c_dp_packet_error_w, c_data_w);
end;
end dp_packet_pkg;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 8f706fe08b9b1afe5fab7b674ae91aedd939696d..b0ebeabbf602715186bf634888c7ac80cdfcc422 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -64,10 +64,10 @@
-- sets the maximum number length of the unmerged packets.
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_packet_unmerge is
generic (
@@ -110,7 +110,6 @@ architecture rtl of dp_packet_unmerge is
signal r : t_reg;
signal d : t_reg;
-
begin
-- Map logic function outputs to entity outputs
pkt_len_out <= to_uvec(r.pkt_len, c_pkt_len_w);
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index cbc94af7224cb6c9b209aee2dfd9ec18a17a88c9..96007803766f0eb2b533ebc0be6748637bfc794e 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -20,38 +20,38 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, easics_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-
-use easics_lib.RAD_CRC16_D16.all;
-use easics_lib.RAD_CRC18_D18.all;
-use easics_lib.RAD_CRC20_D20.all;
-
-use easics_lib.PCK_CRC16_D4.all;
-use easics_lib.PCK_CRC16_D8.all;
-use easics_lib.PCK_CRC16_D9.all;
-use easics_lib.PCK_CRC16_D10.all;
-use easics_lib.PCK_CRC16_D16.all;
-use easics_lib.PCK_CRC16_D18.all;
-use easics_lib.PCK_CRC16_D20.all;
-use easics_lib.PCK_CRC16_D32.all;
-use easics_lib.PCK_CRC16_D36.all;
-use easics_lib.PCK_CRC16_D48.all;
-use easics_lib.PCK_CRC16_D64.all;
-use easics_lib.PCK_CRC16_D72.all;
-
-use easics_lib.PCK_CRC32_D4.all;
-use easics_lib.PCK_CRC32_D8.all;
-use easics_lib.PCK_CRC32_D9.all;
-use easics_lib.PCK_CRC32_D10.all;
-use easics_lib.PCK_CRC32_D16.all;
-use easics_lib.PCK_CRC32_D18.all;
-use easics_lib.PCK_CRC32_D20.all;
-use easics_lib.PCK_CRC32_D32.all;
-use easics_lib.PCK_CRC32_D36.all;
-use easics_lib.PCK_CRC32_D48.all;
-use easics_lib.PCK_CRC32_D64.all;
-use easics_lib.PCK_CRC32_D72.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+
+ use easics_lib.RAD_CRC16_D16.all;
+ use easics_lib.RAD_CRC18_D18.all;
+ use easics_lib.RAD_CRC20_D20.all;
+
+ use easics_lib.PCK_CRC16_D4.all;
+ use easics_lib.PCK_CRC16_D8.all;
+ use easics_lib.PCK_CRC16_D9.all;
+ use easics_lib.PCK_CRC16_D10.all;
+ use easics_lib.PCK_CRC16_D16.all;
+ use easics_lib.PCK_CRC16_D18.all;
+ use easics_lib.PCK_CRC16_D20.all;
+ use easics_lib.PCK_CRC16_D32.all;
+ use easics_lib.PCK_CRC16_D36.all;
+ use easics_lib.PCK_CRC16_D48.all;
+ use easics_lib.PCK_CRC16_D64.all;
+ use easics_lib.PCK_CRC16_D72.all;
+
+ use easics_lib.PCK_CRC32_D4.all;
+ use easics_lib.PCK_CRC32_D8.all;
+ use easics_lib.PCK_CRC32_D9.all;
+ use easics_lib.PCK_CRC32_D10.all;
+ use easics_lib.PCK_CRC32_D16.all;
+ use easics_lib.PCK_CRC32_D18.all;
+ use easics_lib.PCK_CRC32_D20.all;
+ use easics_lib.PCK_CRC32_D32.all;
+ use easics_lib.PCK_CRC32_D36.all;
+ use easics_lib.PCK_CRC32_D48.all;
+ use easics_lib.PCK_CRC32_D64.all;
+ use easics_lib.PCK_CRC32_D72.all;
package dp_packetizing_pkg is
--<types>--
diff --git a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
index 7a0fe1975a1eb11518ad87dcc0650ae48120c3cc..e4968de202c08e739981c3c8012ddcd6f869f8c8 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Prepend one word with empty symbols at the head of a frame
@@ -105,18 +105,18 @@ begin
end process;
u_hold_snk_in : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => in_siso,
- next_src_out => next_in_sosi,
- pend_src_out => pend_in_sosi,
- src_out_reg => in_sosi
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => in_siso,
+ next_src_out => next_in_sosi,
+ pend_src_out => pend_in_sosi,
+ src_out_reg => in_sosi
+ );
-- Prepend the padding octets to snk_in
pad_siso <= concat_siso_arr(0);
@@ -125,25 +125,24 @@ begin
concat_sosi_arr(1) <= in_sosi; -- = tail frame with in_sosi eop info
u_concat : entity work.dp_concat -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => concat_siso_arr,
- snk_in_arr => concat_sosi_arr,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => concat_siso_arr,
+ snk_in_arr => concat_sosi_arr,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
src_out <= snk_in;
snk_out <= src_in;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
index 134fc740effe0bb5ddbd1251b300d03b4ed8e30b..a2bf51f4e1c3acbd4e34238acbeeb6376fe82d39 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Remove padding octects from the head of a padded frame
@@ -65,26 +65,25 @@ begin
src_out <= split_sosi_arr(1);
u_split : entity work.dp_split -- RL = 1
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in_arr => split_siso_arr,
- src_out_arr => split_sosi_arr
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in_arr => split_siso_arr,
+ src_out_arr => split_sosi_arr
+ );
end generate;
gen_bypass : if g_internal_bypass = true generate
src_out <= snk_in;
snk_out <= src_in;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
index a2b024710c6caadc676a06a68937987cc0afd607..2dde43ee21f40171f8e4dc252c7c26697014cecd 100644
--- a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
@@ -40,10 +40,10 @@
-- - dp_block_gen_valid_arr
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_paged_sop_eop_reg is
generic (
@@ -71,68 +71,68 @@ begin
src_out.sync <= src_out_sync(0); -- convert slv to sl
u_paged_sync : entity common_lib.common_paged_reg
- generic map (
- g_data_w => 1,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in_sync,
- out_dat => src_out_sync
- );
+ generic map (
+ g_data_w => 1,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in_sync,
+ out_dat => src_out_sync
+ );
u_paged_bsn : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_bsn_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.bsn,
- out_dat => src_out.bsn
- );
+ generic map (
+ g_data_w => c_dp_stream_bsn_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.bsn,
+ out_dat => src_out.bsn
+ );
u_paged_channel : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_channel_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => sop_wr_en,
- wr_dat => snk_in.channel,
- out_dat => src_out.channel
- );
+ generic map (
+ g_data_w => c_dp_stream_channel_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => sop_wr_en,
+ wr_dat => snk_in.channel,
+ out_dat => src_out.channel
+ );
-- Sosi info at eop
u_paged_empty : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_empty_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.empty,
- out_dat => src_out.empty
- );
+ generic map (
+ g_data_w => c_dp_stream_empty_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.empty,
+ out_dat => src_out.empty
+ );
u_paged_err : entity common_lib.common_paged_reg
- generic map (
- g_data_w => c_dp_stream_error_w,
- g_nof_pages => g_nof_pages
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => eop_wr_en,
- wr_dat => snk_in.err,
- out_dat => src_out.err
- );
+ generic map (
+ g_data_w => c_dp_stream_error_w,
+ g_nof_pages => g_nof_pages
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => eop_wr_en,
+ wr_dat => snk_in.err,
+ out_dat => src_out.err
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline.vhd b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
index 63f860246cf717d911bbb9282398d93d9ca88a97..38031db5911dc40e95694fdf8be39abd16264350 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline the source output by one cycle or by g_pipeline cycles.
@@ -61,8 +61,8 @@ entity dp_pipeline is
end dp_pipeline;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_pipeline_one is
port (
@@ -78,8 +78,8 @@ entity dp_pipeline_one is
end dp_pipeline_one;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline is
signal snk_out_arr : t_dp_siso_arr(0 to g_pipeline);
@@ -95,23 +95,22 @@ begin
gen_p : for I in 1 to g_pipeline generate
u_p : entity work.dp_pipeline_one
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I - 1),
- snk_in => snk_in_arr(I - 1),
- -- ST source
- src_in => snk_out_arr(I),
- src_out => snk_in_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I - 1),
+ snk_in => snk_in_arr(I - 1),
+ -- ST source
+ src_in => snk_out_arr(I),
+ src_out => snk_in_arr(I)
+ );
end generate;
-
end str;
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
architecture str of dp_pipeline_one is
signal nxt_src_out : t_dp_sosi;
@@ -131,16 +130,16 @@ begin
-- Input control
u_hold_input : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- next_src_out => nxt_src_out,
- pend_src_out => OPEN,
- src_out_reg => i_src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ next_src_out => nxt_src_out,
+ pend_src_out => OPEN,
+ src_out_reg => i_src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
index 57e45e045e4a8c287749f8c4c494ea63e4bda484..99c42a813f50cea6eadb1f49fd40762e4491e168 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline array of g_nof_streams by g_pipeline cycles.
@@ -50,19 +50,18 @@ architecture str of dp_pipeline_arr is
begin
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_p : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
index b4dcc11aac1b11163a0422c6ac6a81bfc92136ac..a2f805b7db1f281d9e6e2526115b393c5d2290b5 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
@@ -21,8 +21,8 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Pipeline the source input
@@ -62,92 +62,91 @@ begin
gen_out_incr_rl : if g_out_latency > g_in_latency generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => g_out_latency - g_in_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => g_out_latency - g_in_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl_0 : if g_out_latency <= g_in_latency and g_out_latency = 0 generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => g_in_latency,
- g_incr_latency => 1
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_incr_latency => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency + 1,
- g_out_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => g_in_latency + 1,
+ g_out_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
gen_out_rl : if g_out_latency <= g_in_latency and g_out_latency > 0 generate
-- First adapt the input RL --> 0
u_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_in_latency,
- g_out_latency => 0
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => internal_siso,
- src_out => internal_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_out_latency => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => internal_siso,
+ src_out => internal_sosi
+ );
-- Register siso by incrementing the internal RL = 0 --> the output RL
u_incr : entity work.dp_latency_increase
- generic map (
- g_in_latency => 0,
- g_incr_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => internal_siso,
- snk_in => internal_sosi,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_in_latency => 0,
+ g_incr_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => internal_siso,
+ snk_in => internal_sosi,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index bc4a05d652f25deedd986c36e7eebce07dd26b32..f7714e7613acb9a499d7ffc8dd0d5579dbfa7941 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_from_mm is
generic (
@@ -53,33 +53,35 @@ entity dp_ram_from_mm is
end dp_ram_from_mm;
architecture rtl of dp_ram_from_mm is
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_wr_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_wr_nof_words,
- init_sl => '0');
-
- constant c_ram_rd_nof_words : natural := (c_word_w * g_ram_wr_nof_words) / g_ram_rd_dat_w;
-
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_rd_nof_words),
- dat_w => g_ram_rd_dat_w,
- nof_dat => c_ram_rd_nof_words,
- init_sl => '0');
-
- type t_state_enum is (s_init, s_wait_for_rdy, s_read);
-
- signal state : t_state_enum;
- signal nxt_state : t_state_enum;
-
- signal src_out_ctrl_val : t_dp_sosi;
- signal nxt_src_out_ctrl_val : t_dp_sosi;
-
- signal rd_en : std_logic;
- signal rd_val : std_logic;
- signal rd_data : std_logic_vector(c_mm_ram_rd.dat_w - 1 downto 0);
- signal rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
- signal nxt_rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_wr_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_wr_nof_words,
+ init_sl => '0');
+
+ constant c_ram_rd_nof_words : natural := (c_word_w * g_ram_wr_nof_words) / g_ram_rd_dat_w;
+
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_rd_nof_words),
+ dat_w => g_ram_rd_dat_w,
+ nof_dat => c_ram_rd_nof_words,
+ init_sl => '0');
+
+ type t_state_enum is (s_init, s_wait_for_rdy, s_read);
+
+ signal state : t_state_enum;
+ signal nxt_state : t_state_enum;
+
+ signal src_out_ctrl_val : t_dp_sosi;
+ signal nxt_src_out_ctrl_val : t_dp_sosi;
+
+ signal rd_en : std_logic;
+ signal rd_val : std_logic;
+ signal rd_data : std_logic_vector(c_mm_ram_rd.dat_w - 1 downto 0);
+ signal rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
+ signal nxt_rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
begin
p_src_out : process(src_out_ctrl_val, rd_data)
begin
@@ -150,25 +152,25 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => g_init_file
- )
- port map (
- -- Write port clock domain
- wr_rst => mm_rst,
- wr_clk => mm_clk,
- wr_en => mm_wr,
- wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
- wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => st_rst,
- rd_clk => st_clk,
- rd_en => rd_en,
- rd_adr => rd_addr,
- rd_dat => rd_data,
- rd_val => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => g_init_file
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ wr_en => mm_wr,
+ wr_adr => mm_addr(c_mm_ram_wr.adr_w - 1 downto 0),
+ wr_dat => mm_wrdata(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => st_rst,
+ rd_clk => st_clk,
+ rd_en => rd_en,
+ rd_adr => rd_addr,
+ rd_dat => rd_data,
+ rd_val => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index 25446267eae777e47c8216628519119729ec59e3..f0d20566b85d8682323a390c3888fd343727f523 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_ram_from_mm_reg is
generic (
@@ -38,17 +38,18 @@ entity dp_ram_from_mm_reg is
sla_in : in t_mem_mosi;
dp_on : out std_logic
- );
+ );
end dp_ram_from_mm_reg;
architecture rtl of dp_ram_from_mm_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(1),
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(1),
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
- signal mm_dp_on : std_logic;
+ signal mm_dp_on : std_logic;
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -58,7 +59,7 @@ begin
-- Write access: set register value
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Write Block Sync
+ -- Write Block Sync
when 0 =>
mm_dp_on <= sla_in.wrdata(0);
when others => null; -- unused MM addresses
@@ -68,13 +69,13 @@ begin
end process;
u_async_dp_on : entity common_lib.common_async
- generic map (
- g_rst_level => '0'
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- din => mm_dp_on,
- dout => dp_on
- );
+ generic map (
+ g_rst_level => '0'
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ din => mm_dp_on,
+ dout => dp_on
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index eab525722aa4aa3411ced649b62f02f23d4390ae..626fbfc8047f0020323b7373db67d2f539d4ed3a 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -20,12 +20,12 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_ram_to_mm is
generic (
@@ -49,31 +49,33 @@ entity dp_ram_to_mm is
end dp_ram_to_mm;
architecture rtl of dp_ram_to_mm is
- constant c_mm_ram_rd : t_c_mem := (latency => 1,
- adr_w => ceil_log2(g_ram_rd_nof_words),
- dat_w => c_word_w,
- nof_dat => g_ram_rd_nof_words,
- init_sl => '0');
+ constant c_mm_ram_rd : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(g_ram_rd_nof_words),
+ dat_w => c_word_w,
+ nof_dat => g_ram_rd_nof_words,
+ init_sl => '0');
- constant c_ram_wr_nof_words : natural := (c_word_w * g_ram_rd_nof_words) / g_ram_wr_dat_w;
+ constant c_ram_wr_nof_words : natural := (c_word_w * g_ram_rd_nof_words) / g_ram_wr_dat_w;
- constant c_mm_ram_wr : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_ram_wr_nof_words),
- dat_w => g_ram_wr_dat_w,
- nof_dat => c_ram_wr_nof_words,
- init_sl => '0');
+ constant c_mm_ram_wr : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_ram_wr_nof_words),
+ dat_w => g_ram_wr_dat_w,
+ nof_dat => c_ram_wr_nof_words,
+ init_sl => '0');
- type t_state_enum is (s_init, s_wait_for_sop, s_write);
+ type t_state_enum is (s_init, s_wait_for_sop, s_write);
- signal state : t_state_enum;
- signal nxt_state : t_state_enum;
+ signal state : t_state_enum;
+ signal nxt_state : t_state_enum;
- signal nxt_snk_out : t_dp_siso;
+ signal nxt_snk_out : t_dp_siso;
- signal wr_en : std_logic;
- signal wr_data : std_logic_vector(c_mm_ram_wr.dat_w - 1 downto 0);
- signal wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
- signal nxt_wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
+ signal wr_en : std_logic;
+ signal wr_data : std_logic_vector(c_mm_ram_wr.dat_w - 1 downto 0);
+ signal wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
+ signal nxt_wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
begin
p_state : process(state, wr_addr, snk_in, wr_data)
begin
@@ -128,25 +130,25 @@ begin
end process;
u_ram : entity common_lib.common_ram_cr_cw_ratio
- generic map (
- g_technology => g_technology,
- g_ram_wr => c_mm_ram_wr,
- g_ram_rd => c_mm_ram_rd,
- g_init_file => "UNUSED"
- )
- port map (
- -- Write port clock domain
- wr_rst => st_rst,
- wr_clk => st_clk,
- wr_en => snk_in.valid,
- wr_adr => wr_addr,
- wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
- -- Read port clock domain
- rd_rst => mm_rst,
- rd_clk => mm_clk,
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
- rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
- rd_val => sla_out.rdval
- );
+ generic map (
+ g_technology => g_technology,
+ g_ram_wr => c_mm_ram_wr,
+ g_ram_rd => c_mm_ram_rd,
+ g_init_file => "UNUSED"
+ )
+ port map (
+ -- Write port clock domain
+ wr_rst => st_rst,
+ wr_clk => st_clk,
+ wr_en => snk_in.valid,
+ wr_adr => wr_addr,
+ wr_dat => snk_in.data(c_mm_ram_wr.dat_w - 1 downto 0),
+ -- Read port clock domain
+ rd_rst => mm_rst,
+ rd_clk => mm_clk,
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(c_mm_ram_rd.adr_w - 1 downto 0),
+ rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
+ rd_val => sla_out.rdval
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index f1f8532c37cc45f6c750c6937012ad9fdff2068f..aeac60cc38a5e61d459a0bb73dbb1437be90f8a5 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- =======
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index d0f65d7299734d6a4c435283a0e453714cb7a57e..9f16b8654bd20ba38851f3c41a9092d178b9022f 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -89,6 +89,7 @@ begin
-- Map input sosi_arr to SLV
-----------------------------------------------------------------------------
gen_wires_in : for i in 0 to g_nof_in - 1 generate
+
gen_sosi_dat_in: if g_use_complex = false generate
-----------------------------------------------------------------------------
-- Forward SOSI data field
@@ -107,29 +108,30 @@ begin
common_reinterleave_in_val <= snk_in_arr(0).valid;
u_common_reinterleave : entity common_lib.common_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => common_reinterleave_in_dat,
- in_val => common_reinterleave_in_val,
-
- out_dat => common_reinterleave_out_dat,
- out_val => common_reinterleave_out_val
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => common_reinterleave_in_dat,
+ in_val => common_reinterleave_in_val,
+
+ out_dat => common_reinterleave_out_dat,
+ out_val => common_reinterleave_out_val
+ );
-----------------------------------------------------------------------------
-- Map output SLV to sosi_arr
-----------------------------------------------------------------------------
gen_wires_out : for i in 0 to g_nof_out - 1 generate
+
gen_sosi_dat_out: if g_use_complex = false generate
-----------------------------------------------------------------------------
-- Forward SOSI data field
@@ -152,21 +154,22 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_use_ctrl = true generate
+
gen_dp_block_gen : for i in 0 to g_nof_out - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_block_size_output,
- g_preserve_sync => true,
- g_preserve_bsn => true
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => common_reinterleave_src_out_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_block_size_output,
+ g_preserve_sync => true,
+ g_preserve_bsn => true
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => common_reinterleave_src_out_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -178,27 +181,27 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
align_out : if g_use_sync_bsn = true generate
+
gen_dp_fifo_info: for i in 0 to g_nof_out - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
no_align_out : if g_use_sync_bsn = false generate
src_out_arr <= dp_block_gen_src_out_arr;
end generate;
-
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index ebc3dd4c1b829e0f05476741b0623d7f483619e9..a2d2c9b6e0ed6a7dab73cf341c589675b44075ee 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
@@ -96,7 +96,7 @@ architecture rtl of dp_repack is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -104,6 +104,7 @@ begin
end generate;
gen_pack : if g_in_nof_words /= g_out_nof_words generate
+
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -149,11 +150,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -217,11 +218,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index fbc1849f6a79eb003fcbabc5ed3a4a8e6db5a95a..1c06ee369ed7692c01ae12eb11e13a2cd82fe446 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -175,9 +175,9 @@
-- useful to be able to isolate a component for debugging.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_in is
generic (
@@ -244,6 +244,7 @@ begin
end generate;
no_bypass : if g_bypass = false generate
+
p_comb : process(rst, r, snk_in, data_vec, src_in)
variable v : t_reg;
begin
@@ -382,13 +383,12 @@ begin
snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
end generate;
-
end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_out is
generic (
@@ -470,6 +470,7 @@ begin
end generate;
no_bypass : if g_bypass = false generate
+
p_comb : process(rst, snk_in, r, data_vec, src_in)
variable v : t_reg;
begin
@@ -622,13 +623,12 @@ begin
snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
end generate;
-
end rtl;
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity dp_repack_data is
generic (
@@ -675,16 +675,16 @@ architecture str of dp_repack_data is
begin
gen_dp_pipeline_ready: if g_pipeline_ready = true generate
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_in => i_snk_out,
- src_out => i_snk_in
- );
+ src_in => i_snk_out,
+ src_out => i_snk_in
+ );
end generate;
gen_no_dp_pipeline_ready: if g_pipeline_ready = false generate
@@ -705,23 +705,23 @@ begin
gen_dp_repack_in : if g_enable_repack_in = true generate
u_dp_repack_in : entity work.dp_repack_in
- generic map (
- g_bypass => g_in_bypass,
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_in_symbol_w => g_in_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => i_snk_out,
- snk_in => i_snk_in,
-
- src_in => pack_siso,
- src_out => pack_sosi,
- src_out_data => pack_sosi_data
- );
+ generic map (
+ g_bypass => g_in_bypass,
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_in_symbol_w => g_in_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => i_snk_out,
+ snk_in => i_snk_in,
+
+ src_in => pack_siso,
+ src_out => pack_sosi,
+ src_out_data => pack_sosi_data
+ );
end generate;
no_dp_repack_out : if g_enable_repack_out = false generate
@@ -731,24 +731,24 @@ begin
gen_dp_repack_out : if g_enable_repack_out = true generate
u_dp_repack_out : entity work.dp_repack_out
- generic map (
- g_bypass => g_out_bypass,
- g_in_buf_dat_w => c_in_buf_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_out_nof_words => g_out_nof_words,
- g_out_symbol_w => g_out_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => pack_siso,
- snk_in => pack_sosi,
- snk_in_data => pack_sosi_data,
-
- src_in => src_in,
- src_out => i_src_out
- );
+ generic map (
+ g_bypass => g_out_bypass,
+ g_in_buf_dat_w => c_in_buf_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_out_nof_words => g_out_nof_words,
+ g_out_symbol_w => g_out_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => pack_siso,
+ snk_in => pack_sosi,
+ snk_in_data => pack_sosi_data,
+
+ src_in => src_in,
+ src_out => i_src_out
+ );
end generate;
-- Simulation only: internal stream RL verification
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index 5149b5f2aa0e10f745d397dc9562715acf3a1058..5c5ae71ce50792f93d981b4337c71c98667d3ea3 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
-- Reuse from LOFAR rad_repack.vhd and rad_repack(rtl).vhd
@@ -96,7 +96,7 @@ architecture rtl of dp_repack_legacy is
begin
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack_legacy at the other end,
- -- typically g_out_dat_w=g_in_dat_w
+ -- typically g_out_dat_w=g_in_dat_w
out_val <= in_val;
out_sof <= in_sof;
out_eof <= in_eof;
@@ -104,6 +104,7 @@ begin
end generate;
gen_pack : if g_in_nof_words /= g_out_nof_words generate
+
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -149,11 +150,11 @@ begin
out_eof <= out_eof_vec(0);
buf_load <= '1' when signed(in_val_vec) = -1 else '0';
- -- in_val_vec=-1: input set complete, ready to be repacked
+ -- in_val_vec=-1: input set complete, ready to be repacked
buf_flush <= '1' when (unsigned(out_val_vec) = 1 or unsigned(out_val_vec) = 0) and buf_val = '1' else '0';
- -- out_val_vec=0: ready to repack first input set
- -- out_val_vec=1: ready to repack next input set
- -- buf_val: new input set available
+ -- out_val_vec=0: ready to repack first input set
+ -- out_val_vec=1: ready to repack next input set
+ -- buf_val: new input set available
p_in: process(in_sof, buf_load, in_val, in_val_vec, in_dat, in_dat_vec)
begin
@@ -217,11 +218,11 @@ begin
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
- out_dat_vec(out_dat_vec'high downto out_dat'length);
+ out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0,out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index c063da2ad8305ae55fb422bd0f9299401e8a9d26..65620556677c84254082fc41e445f1dd0dc82222 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.all;
+ use common_lib.common_pkg.all;
-- Purpose: Requantize the data in the re, im or data field of the sosi record.
-- Description:
@@ -37,14 +37,14 @@ entity dp_requantize is
g_complex : boolean := true; -- when TRUE, the re and im field are processed, when false, the data field is processed
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_lsb_w : integer := 4; -- when > 0, number of LSbits to remove from in_dat
- -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
- -- when 0 then no effect
+ -- when < 0, number of LSBits to insert as a gain before resize to out_dat'LENGTH
+ -- when 0 then no effect
g_lsb_round : boolean := true; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_lsb_round_even : boolean := true; -- when TRUE round half to even, else round half away from zero
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
g_gain_w : natural := 0; -- do not use, must be 0, use negative g_lsb_w instead
g_pipeline_remove_lsb : natural := 0; -- >= 0
g_pipeline_remove_msb : natural := 0; -- >= 0, use g_pipeline_remove_lsb=0 and g_pipeline_remove_msb=0 for combinatorial output
@@ -81,25 +81,25 @@ begin
---------------------------------------------------------------
gen_requantize_data : if g_complex = false generate
u_requantize_data : entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.data,
- out_dat => quantized_data,
- out_ovr => out_ovr
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.data,
+ out_dat => quantized_data,
+ out_ovr => out_ovr
+ );
end generate;
---------------------------------------------------------------
@@ -107,46 +107,46 @@ begin
---------------------------------------------------------------
gen_requantize_complex : if g_complex = true generate
u_requantize_re: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.re,
- out_dat => quantized_re,
- out_ovr => out_ovr_re
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.re,
+ out_dat => quantized_re,
+ out_ovr => out_ovr_re
+ );
u_requantize_im: entity common_lib.common_requantize
- generic map (
- g_representation => g_representation,
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_lsb_round_even => g_lsb_round_even,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_pipeline_remove_lsb => g_pipeline_remove_lsb,
- g_pipeline_remove_msb => g_pipeline_remove_msb,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- clk => clk,
- in_dat => snk_in.im,
- out_dat => quantized_im,
- out_ovr => out_ovr_im
- );
+ generic map (
+ g_representation => g_representation,
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_lsb_round_even => g_lsb_round_even,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_pipeline_remove_lsb => g_pipeline_remove_lsb,
+ g_pipeline_remove_msb => g_pipeline_remove_msb,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => snk_in.im,
+ out_dat => quantized_im,
+ out_ovr => out_ovr_im
+ );
out_ovr <= out_ovr_re or out_ovr_im;
end generate;
@@ -155,17 +155,17 @@ begin
-- Pipeline to align the other sosi fields
--------------------------------------------------------------
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_piped
- );
+ generic map (
+ g_pipeline => c_pipeline -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_piped
+ );
process(snk_in_piped, quantized_data, quantized_re, quantized_im)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 7e76bc93ba2fda5f3dbb0ee1e46025cd77b1f1a0..85a66c04f95ea05090b0d5237d9a07b8933c1388 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -19,10 +19,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -66,8 +66,8 @@ end dp_reverse_n_data;
architecture str of dp_reverse_n_data is
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
- g_reverse_len - 1 +
- g_pipeline_mux_in + g_pipeline_mux_out;
+ g_reverse_len - 1 +
+ g_pipeline_mux_in + g_pipeline_mux_out;
constant c_complex_w : natural := g_data_w / 2;
signal in_data : std_logic_vector(g_data_w - 1 downto 0);
@@ -87,39 +87,39 @@ begin
end process;
u_common_reverse_n : entity common_lib.common_reverse_n_data
- generic map (
- -- Pipeline: 0 for combinatorial, > 0 for registers
- g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
- g_pipeline_demux_out => g_pipeline_demux_out,
- g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
- g_pipeline_mux_out => g_pipeline_mux_out,
- g_reverse_len => g_reverse_len,
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ -- Pipeline: 0 for combinatorial, > 0 for registers
+ g_pipeline_demux_in => g_pipeline_demux_in, -- serial to parallel demux
+ g_pipeline_demux_out => g_pipeline_demux_out,
+ g_pipeline_mux_in => g_pipeline_mux_in, -- parallel to serial mux
+ g_pipeline_mux_out => g_pipeline_mux_out,
+ g_reverse_len => g_reverse_len,
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- in_data => in_data,
- in_val => snk_in.valid,
- in_eop => snk_in.eop,
- out_data => reversed_data,
- out_val => reversed_val -- = snk_in_delayed.valid
- );
+ in_data => in_data,
+ in_val => snk_in.valid,
+ in_eop => snk_in.eop,
+ out_data => reversed_data,
+ out_val => reversed_val -- = snk_in_delayed.valid
+ );
-- Pipeline other sosi fields
u_pipe_input : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline_total
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- -- ST source
- src_out => snk_in_delayed
- );
+ generic map (
+ g_pipeline => c_pipeline_total
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ -- ST source
+ src_out => snk_in_delayed
+ );
p_src_out : process(snk_in_delayed, reversed_data)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 77741d7694fc2fd2e24368c07c94994743ee86ab..714034dbab1493d0e08a52c83315d0832e672ca6 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -19,10 +19,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Author:
-- . Eric Kooistra, 14 Feb 2023
@@ -67,19 +67,19 @@ architecture str of dp_reverse_n_data_fc is
signal reverse_sosi_arr : t_dp_sosi_arr(g_reverse_len - 1 downto 0);
begin
u_demux_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline_in,
- g_nof_outputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_in,
+ g_nof_outputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
gen_reverse : for I in 0 to g_reverse_len - 1 generate
demux_siso_arr(g_reverse_len - 1 - I) <= reverse_siso_arr(I);
@@ -87,17 +87,17 @@ begin
end generate;
u_mux_n_to_one : entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => g_pipeline_out,
- g_nof_inputs => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_pipeline => g_pipeline_out,
+ g_nof_inputs => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out_arr => reverse_siso_arr,
- snk_in_arr => reverse_sosi_arr,
- src_in => src_in,
- src_out => src_out
- );
+ snk_out_arr => reverse_siso_arr,
+ snk_in_arr => reverse_sosi_arr,
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
index db1c3512342323fb01cfcf219686b085bd84b435..10b28ac5996638af1ac75d078ea1339dface1a04 100644
--- a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
@@ -62,10 +62,10 @@
-- [1] https://support.astron.nl/confluence/display/L2M/L2+STAT+Decision%3A+Timing+in+Station
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_rsn_source is
generic (
@@ -125,8 +125,8 @@ begin
rsn <= MULT_UVEC(bs_sosi.bsn(g_bsn_w - 1 downto 0), TO_UVEC(g_bs_block_size, c_bs_block_size_cnt_w));
p_state : process(bs_sosi, nxt_sync, sync, sync_size_cnt, nof_clk_per_sync,
- state, prev_state,
- i_rs_sosi, rs_block_size_cnt, rsn)
+ state, prev_state,
+ i_rs_sosi, rs_block_size_cnt, rsn)
begin
-- Maintain sync_size_cnt for nof_clk_per_sync
-- . nof_clk_per_sync is the number of clk per sync interval and the
@@ -169,9 +169,9 @@ begin
nxt_state <= s_on;
end if;
- -- using separate states s_on_sop and s_on_eop instead of only
- -- s_on state and rs_block_size_cnt, cause that g_rs_block_size must be
- -- >= 3, but that is fine.
+ -- using separate states s_on_sop and s_on_eop instead of only
+ -- s_on state and rs_block_size_cnt, cause that g_rs_block_size must be
+ -- >= 3, but that is fine.
when s_on_sop =>
-- Start of block
nxt_rs_sosi.sop <= '1';
@@ -220,7 +220,7 @@ begin
i_rs_new_interval <= '1' when i_rs_restart = '1' else
'0' when i_rs_sosi.sync = '1' else
- reg_rs_new_interval;
+ reg_rs_new_interval;
p_clk : process(rst, clk)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_selector.vhd b/libraries/base/dp/src/vhdl/dp_selector.vhd
index 79aea5699354607b65eb042ed3d080162e1b5ec9..673baae8cbf943110dd3616a463ffe61f6aa364a 100644
--- a/libraries/base/dp/src/vhdl/dp_selector.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector.vhd
@@ -28,12 +28,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector is
generic (
@@ -60,23 +60,23 @@ end dp_selector;
architecture str of dp_selector is
begin
u_dp_selector_arr : entity work.dp_selector_arr
- generic map (
- g_nof_arr => 1,
- g_pipeline => g_pipeline
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_nof_arr => 1,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- reg_selector_mosi => reg_selector_mosi,
- reg_selector_miso => reg_selector_miso,
+ reg_selector_mosi => reg_selector_mosi,
+ reg_selector_miso => reg_selector_miso,
- pipe_sosi_arr(0) => pipe_sosi,
- ref_sosi_arr(0) => ref_sosi,
- out_sosi_arr(0) => out_sosi,
+ pipe_sosi_arr(0) => pipe_sosi,
+ ref_sosi_arr(0) => ref_sosi,
+ out_sosi_arr(0) => out_sosi,
- selector_en => selector_en
- );
+ selector_en => selector_en
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index 33b96c99a3e941fe4b52cf4eabaf4abe82f1abfc..5b1ed899fb7c485350628f852b27daabaa323337 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -31,12 +31,12 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_selector_arr is
generic (
@@ -74,21 +74,21 @@ begin
selector_en <= reg_selector_en(0);
u_mms_common_reg : entity common_lib.mms_common_reg
- generic map (
- g_mm_reg => c_selector_mem_reg
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- reg_mosi => reg_selector_mosi,
- reg_miso => reg_selector_miso,
-
- in_reg => reg_selector_en,
- out_reg => reg_selector_en
- );
+ generic map (
+ g_mm_reg => c_selector_mem_reg
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ reg_mosi => reg_selector_mosi,
+ reg_miso => reg_selector_miso,
+
+ in_reg => reg_selector_en,
+ out_reg => reg_selector_en
+ );
n_en <= not reg_selector_en(0);
@@ -100,31 +100,31 @@ begin
switch_high => reg_selector_en(0),
switch_low => n_en,
out_level => switch_select
- );
+ );
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => g_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => pipe_sosi_arr,
- src_out_arr => pipelined_pipe_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => pipe_sosi_arr,
+ src_out_arr => pipelined_pipe_sosi_arr
+ );
select_sosi_arr <= pipelined_pipe_sosi_arr when switch_select = '1' else ref_sosi_arr;
u_pipeline_arr_out : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_arr,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => select_sosi_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_arr,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => select_sosi_arr,
+ src_out_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftram.vhd b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
index f63fd0c4d9a8830d8340939a3e4f26ada9a05ab9..00d1743ca674e40eeb76ef9f18e102ee064112fc 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftram.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
@@ -23,13 +23,13 @@
-- Description:
library IEEE, common_lib, technology_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_shiftram is
generic (
@@ -76,74 +76,75 @@ begin
-----------------------------------------------------------------------------
gen_common_shiftram : for i in 0 to g_nof_streams - 1 generate
u_common_shiftram : entity common_lib.common_shiftram
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_nof_words => g_nof_words
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
- data_in_val => snk_in_arr(i).valid,
- data_in_shift => common_shiftram_shift_in_arr(i),
-
- data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
- data_out_val => src_out_arr(i).valid,
- data_out_shift => open
- );
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_nof_words => g_nof_words
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ data_in => snk_in_arr(i).data(g_data_w - 1 downto 0),
+ data_in_val => snk_in_arr(i).valid,
+ data_in_shift => common_shiftram_shift_in_arr(i),
+
+ data_out => src_out_arr(i).data(g_data_w - 1 downto 0),
+ data_out_val => src_out_arr(i).valid,
+ data_out_shift => open
+ );
end generate;
-----------------------------------------------------------------------------
-- MM control
-----------------------------------------------------------------------------
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
gen_no_sync : if g_use_sync_in = false generate
common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
end generate;
gen_sync : if g_use_sync_in = true generate
+
p_clk : process(dp_rst, dp_clk, sync_in, mm_fields_out_arr)
begin
if dp_rst = '1' then
common_shiftram_shift_in_arr(i) <= (others => '0');
elsif rising_edge(dp_clk) then
if(sync_in = '1') then
- common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
- end if;
+ common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
end if;
+ end if;
+
end process;
end generate;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
index 0a6c63afa81d0216065f4c21d79df4095509133b..eabc7cf5f352c65b8992043b7948a325e325205c 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Move the valid input data through a shift register to have access to
@@ -113,6 +113,7 @@ begin
end generate;
gen_flush_eop : if g_flush_eop = true generate
+
p_eop : process(prev_src_in, shiftreg)
variable v_eop : std_logic := '0';
begin
@@ -177,16 +178,15 @@ begin
gen_output_reg : if g_output_reg = true generate
u_output : entity work.dp_pipeline
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => shiftreg_out,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => shiftreg_out,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index 19ac1fb2b5140c73dc0ba9b4000292b702788c65..3650eb193503b3ab6806b0a9641b97630b6a8018 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Split one frame into two frames.
@@ -189,18 +189,18 @@ begin
-- Hold the sink input to be able to register the source output
u_hold : entity work.dp_hold_input
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- ST source
- src_in => hold_src_in,
- next_src_out => next_src_buf,
- pend_src_out => OPEN,
- src_out_reg => src_buf
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- ST source
+ src_in => hold_src_in,
+ next_src_out => next_src_buf,
+ pend_src_out => OPEN,
+ src_out_reg => src_buf
+ );
-- Hold input register
nxt_src_buf <= next_src_buf;
@@ -275,7 +275,7 @@ begin
-- preserve tail data information for next state
nxt_tail <= tail; -- keep the tail data part in case the split is at symbol boundary and not at word boundary,
- -- keep the sop of the tail output, the valid and eop of tail are not used.
+ -- keep the sop of the tail output, the valid and eop of tail are not used.
-- pass on output
nxt_state <= state;
@@ -362,7 +362,7 @@ begin
if next_src_buf.eop = '1' then
i_snk_out <= c_dp_siso_rst; -- no input request for at least one clock cycle, to allow change in nof_symbols_reg and/or for state s_eop
if TO_UINT(v_input_empty) >= TO_UINT(head_empty_reg) then
- -- this is the last tail output, the input eop marks the tail output eop
+ -- this is the last tail output, the input eop marks the tail output eop
nxt_src_out_arr(c_tail).empty <= RESIZE_DP_EMPTY(func_dp_empty_split(v_input_empty, head_empty_reg, c_nof_symbols_per_data));
nxt_state <= s_head;
else -- need one more tail word to output the last tail part
diff --git a/libraries/base/dp/src/vhdl/dp_split_reg.vhd b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
index dc7a67f30eac44f750775c73f8a7c851ede10554..f780ec6afefceb98f30beb61b1fd4f5faba899b1 100644
--- a/libraries/base/dp/src/vhdl/dp_split_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
@@ -30,9 +30,9 @@
-- |-----------------------------------------------------------------------|
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_split_reg is
generic (
@@ -55,13 +55,14 @@ entity dp_split_reg is
end dp_split_reg;
architecture str of dp_split_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => '0');
-
- signal mm_nof_symbols : std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => '0');
+
+ signal mm_nof_symbols : std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -81,17 +82,17 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
+ mm_nof_symbols <= sla_in.wrdata(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(ceil_log2(g_nof_symbols + 1) - 1 downto 0) <= mm_nof_symbols;
@@ -102,15 +103,15 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_nof_symbols,
+ in_dat => mm_nof_symbols,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => nof_symbols
- );
+ out_dat => nof_symbols
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index e47aa13cbc082f269f16527fd5c4d6bcc6e09aa2..286adbef5cddca3f9d7eb97c0b79d5643f45852a 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE,common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Control a source's output rate by toggling its ready input.
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index 5f121726fe81f2f5338d6368fd25567015649795..861844b481eb265f94c58b5953c7bc22d5909b33 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -20,9 +20,9 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
package dp_stream_pkg is
------------------------------------------------------------------------------
@@ -120,15 +120,16 @@ package dp_stream_pkg is
end record;
constant c_dp_sosi_unsigned_rst : t_dp_sosi_unsigned := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'), (others => '0'));
- constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := ('1',
- to_unsigned(1, c_dp_stream_bsn_w),
- to_unsigned(1, c_dp_stream_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- to_unsigned(1, c_dp_stream_dsp_data_w),
- '1', '1', '1',
- to_unsigned(1, c_dp_stream_empty_w),
- to_unsigned(1, c_dp_stream_channel_w),
- to_unsigned(1, c_dp_stream_error_w));
+ constant c_dp_sosi_unsigned_ones : t_dp_sosi_unsigned := (
+ '1',
+ to_unsigned(1, c_dp_stream_bsn_w),
+ to_unsigned(1, c_dp_stream_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ to_unsigned(1, c_dp_stream_dsp_data_w),
+ '1', '1', '1',
+ to_unsigned(1, c_dp_stream_empty_w),
+ to_unsigned(1, c_dp_stream_channel_w),
+ to_unsigned(1, c_dp_stream_error_w));
-- Use boolean to define whether a t_dp_siso, t_dp_sosi field is used ('1') or not ('0')
type t_dp_siso_sl is record
@@ -207,30 +208,34 @@ package dp_stream_pkg is
type t_dp_sosi_mat is array (integer range <>, integer range <>) of t_dp_sosi;
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector);
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector);
-- Reset only the control fields of the DP sosi record
function RESET_DP_SOSI_CTRL(sosi : t_dp_sosi) return t_dp_sosi;
@@ -365,11 +370,11 @@ package dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string ) return t_dp_sosi_arr;
function func_dp_stream_set_data(dp : t_dp_sosi_arr; slv : std_logic_vector; str : string; mask : std_logic_vector) return t_dp_sosi_arr;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
- -- . data_order_im_re defines the concatenation order data = im&re or re&im
- -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
- -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
- -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- . data_order_im_re defines the concatenation order data = im&re or re&im
+ -- . nof_data defines the number of concatenated streams that are concatenated in the sosi.data or sosi.re,im
+ -- . rewire nof_data streams from data to re,im and force data = X to show that sosi data is used
+ -- . rewire nof_data streams from re,im to data and force re,im = X to show that sosi complex is used
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi;
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural ) return t_dp_sosi; -- data_order_im_re = TRUE
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural ) return t_dp_sosi; -- data_order_im_re = TRUE, nof_data = 1
@@ -407,16 +412,16 @@ package dp_stream_pkg is
-- Return TRUE when the sosi.data of both streams matches (and is valid)
function func_dp_data_match(snk_in_a, snk_in_b: t_dp_sosi; data_w: natural) return boolean;
function func_dp_data_match(snk_in_a, snk_in_b, snk_in_c: t_dp_sosi; data_w: natural) return boolean;
-
end dp_stream_pkg;
package body dp_stream_pkg is
-- Check sosi.valid against siso.ready
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
ready_reg(0) <= siso.ready;
-- Register siso.ready in c_ready_latency registers
@@ -431,20 +436,22 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- Default RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi : in t_dp_sosi;
- signal siso : in t_dp_siso;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi : in t_dp_sosi;
+ signal siso : in t_dp_siso;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi, siso, ready_reg);
end proc_dp_siso_alert;
-- SOSI/SISO array version
- procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
for i in 0 to sosi_arr'length - 1 loop
ready_reg(i * (c_ready_latency + 1)) <= siso_arr(i).ready; -- SLV is used as an array: nof_streams*(0..c_ready_latency)
@@ -462,10 +469,11 @@ package body dp_stream_pkg is
end proc_dp_siso_alert;
-- SOSI/SISO array version with RL=1
- procedure proc_dp_siso_alert(signal clk : in std_logic;
- signal sosi_arr : in t_dp_sosi_arr;
- signal siso_arr : in t_dp_siso_arr;
- signal ready_reg : inout std_logic_vector) is
+ procedure proc_dp_siso_alert(
+ signal clk : in std_logic;
+ signal sosi_arr : in t_dp_sosi_arr;
+ signal siso_arr : in t_dp_siso_arr;
+ signal ready_reg : inout std_logic_vector) is
begin
proc_dp_siso_alert(1, clk, sosi_arr, siso_arr, ready_reg);
end proc_dp_siso_alert;
@@ -927,7 +935,7 @@ package body dp_stream_pkg is
elsif str = "SOP" then v_dp(I).sop := v_slv(I);
elsif str = "EOP" then v_dp(I).eop := v_slv(I);
elsif str = "SYNC" then v_dp(I).sync := v_slv(I);
- -- use slv to set individual slv field
+ -- use slv to set individual slv field
elsif str = "BSN" then v_dp(I).bsn := RESIZE_DP_BSN(slv);
elsif str = "CHANNEL" then v_dp(I).channel := RESIZE_DP_CHANNEL(slv);
elsif str = "EMPTY" then v_dp(I).empty := RESIZE_DP_EMPTY(slv);
@@ -1302,16 +1310,16 @@ package body dp_stream_pkg is
function func_dp_stream_set_data(dp : t_dp_sosi; slv : std_logic_vector; str : string) return t_dp_sosi is
variable v_dp : t_dp_sosi := dp;
begin
- if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
- elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
- elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
- elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
- v_dp.re := RESIZE_DP_DSP_DATA(slv);
- v_dp.im := RESIZE_DP_DSP_DATA(slv);
- else report "Error in func_dp_stream_set_data for t_dp_sosi";
- end if;
+ if str = "DATA" then v_dp.data := RESIZE_DP_DATA(slv);
+ elsif str = "DSP" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "RE" then v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "IM" then v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ elsif str = "ALL" then v_dp.data := RESIZE_DP_DATA(slv);
+ v_dp.re := RESIZE_DP_DSP_DATA(slv);
+ v_dp.im := RESIZE_DP_DSP_DATA(slv);
+ else report "Error in func_dp_stream_set_data for t_dp_sosi";
+ end if;
return v_dp;
end;
@@ -1335,7 +1343,7 @@ package body dp_stream_pkg is
return v_dp;
end;
- -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
+ -- Functions to rewire between concatenated sosi.data and concatenated sosi.re,im
function func_dp_stream_complex_to_data(dp : t_dp_sosi; data_w : natural; nof_data : natural; data_order_im_re : boolean) return t_dp_sosi is
constant c_compl_data_w : natural := data_w / 2;
variable v_dp : t_dp_sosi := dp;
@@ -1487,11 +1495,11 @@ package body dp_stream_pkg is
if data_order_im_re = true then
-- data = im&re
v_out_data := RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w) &
- RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
+ RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w);
else
-- data = re&im
v_out_data := RESIZE_SVEC(v_in_data( c_compl_in_w - 1 downto 0), c_compl_out_w) &
- RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
+ RESIZE_SVEC(v_in_data(2 * c_compl_in_w - 1 downto c_compl_in_w), c_compl_out_w);
end if;
end if;
end if;
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 82eb03aa00a6e8cd9e06eea8c36635d510a6a146..4698c8fab9c623882339d5694835be39c4122fe6 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -74,11 +74,11 @@
-- ref_sync stopped already.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_components_pkg.all;
entity dp_strobe_total_count is
generic (
@@ -110,29 +110,30 @@ architecture rtl of dp_strobe_total_count is
constant c_flush_adr : natural := c_dp_strobe_total_count_reg_flush_adr;
-- Define the size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => c_dp_strobe_total_count_reg_adr_w,
- dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => c_dp_strobe_total_count_reg_nof_words,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => c_dp_strobe_total_count_reg_adr_w,
+ dat_w => g_mm_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => c_dp_strobe_total_count_reg_nof_words,
+ init_sl => '0');
- type t_cnt_arr is array (integer range <>) of std_logic_vector(g_count_w - 1 downto 0);
+ type t_cnt_arr is array (integer range <>) of std_logic_vector(g_count_w - 1 downto 0);
- -- Registers in dp_clk domain
- signal ref_sync_reg : std_logic := '0';
- signal ref_sync_reg2 : std_logic := '0';
- signal in_strobe_reg_arr : std_logic_vector(g_nof_counts - 1 downto 0) := (others => '0');
- signal in_strobe_reg2_arr : std_logic_vector(g_nof_counts - 1 downto 0) := (others => '0');
- signal rd_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
- signal mm_cnt_clear : std_logic;
- signal mm_cnt_flush : std_logic;
- signal dp_cnt_clear : std_logic;
- signal dp_cnt_flush : std_logic;
- signal cnt_clr : std_logic := '0';
- signal cnt_en : std_logic := '0';
- signal cnt_en_arr : std_logic_vector(g_nof_counts - 1 downto 0);
- signal cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0);
- signal hold_cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0) := (others => (others => '0'));
+ -- Registers in dp_clk domain
+ signal ref_sync_reg : std_logic := '0';
+ signal ref_sync_reg2 : std_logic := '0';
+ signal in_strobe_reg_arr : std_logic_vector(g_nof_counts - 1 downto 0) := (others => '0');
+ signal in_strobe_reg2_arr : std_logic_vector(g_nof_counts - 1 downto 0) := (others => '0');
+ signal rd_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
+ signal mm_cnt_clear : std_logic;
+ signal mm_cnt_flush : std_logic;
+ signal dp_cnt_clear : std_logic;
+ signal dp_cnt_flush : std_logic;
+ signal cnt_clr : std_logic := '0';
+ signal cnt_en : std_logic := '0';
+ signal cnt_en_arr : std_logic_vector(g_nof_counts - 1 downto 0);
+ signal cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0);
+ signal hold_cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0) := (others => (others => '0'));
begin
assert g_nof_counts <= c_nof_counts_max report "Too many counters to fit REGMAP." severity FAILURE;
assert g_count_w <= g_mm_w * 2 report "Too wide counter to fit REGMAP." severity FAILURE;
@@ -142,28 +143,28 @@ begin
mm_cnt_flush <= reg_mosi.wr when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_flush_adr else '0';
u_common_spulse_clear : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_clear,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_clear
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_clear,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_clear
+ );
-- Support cnt clear via either MM or via an input strobe, use register
-- to ease timing closure
cnt_clr <= dp_cnt_clear or in_clr when rising_edge(dp_clk);
u_common_spulse_flush : entity common_lib.common_spulse
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_pulse => mm_cnt_flush,
- out_rst => dp_rst,
- out_clk => dp_clk,
- out_pulse => dp_cnt_flush
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_pulse => mm_cnt_flush,
+ out_rst => dp_rst,
+ out_clk => dp_clk,
+ out_pulse => dp_cnt_flush
+ );
-- Register inputs to ease timing closure
-- . register ref_sync to ease timing closure for ref_sync fanout
@@ -199,18 +200,18 @@ begin
cnt_en_arr(I) <= cnt_en and in_strobe_reg2_arr(I);
u_counter : entity common_lib.common_counter
- generic map (
- g_width => g_count_w,
- g_clip => g_clip
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_width => g_count_w,
+ g_clip => g_clip
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en_arr(I),
- count => cnt_arr(I)
- );
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en_arr(I),
+ count => cnt_arr(I)
+ );
end generate;
-- Hold counter values at ref_sync_reg2 to have stable values for MM read
@@ -229,6 +230,7 @@ begin
-- Register mapping
gen_cnt : for I in 0 to g_nof_counts - 1 generate
+
gen_reg_32b : if g_count_w <= g_mm_w generate
rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w); -- low part
rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= (others => '0'); -- high part (not used)
@@ -241,26 +243,26 @@ begin
end generate;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => rd_reg, -- read only
- out_reg => open -- no write
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => rd_reg, -- read only
+ out_reg => open -- no write
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index e11631038321181d17ceb3c567f5fb6f25d21a0b..9118a87444eab53646748cd8701876ad644c44ba 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -33,11 +33,11 @@
-- . So this does not work for continuous streams!
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_switch is
generic (
@@ -93,37 +93,37 @@ begin
-- A single MM register contains input to select
------------------------------------------------------------------------------
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
------------------------------------------------------------------------------
-- put dp_xonoff block inbetween data path to control data flow.
------------------------------------------------------------------------------
gen_dp_xonoff_arr : for i in 0 to g_nof_inputs - 1 generate
u_dp_xonoff: entity work.dp_xonoff
- port map (
- clk => dp_clk,
- rst => dp_rst,
- -- Frame in
- in_sosi => snk_in_arr(i),
- in_siso => snk_out_arr(i),
- -- Frame out
- out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
- out_sosi => xonoff_src_out_arr(i)
- );
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+ -- Frame in
+ in_sosi => snk_in_arr(i),
+ in_siso => snk_out_arr(i),
+ -- Frame out
+ out_siso => xonoff_src_in_arr(i), -- flush control done by dp_mux.snk_out_arr
+ out_sosi => xonoff_src_out_arr(i)
+ );
end generate;
------------------------------------------------------------------------------
@@ -145,35 +145,35 @@ begin
-- DP mux forwards input based on dp_mux_sel_ctrl
------------------------------------------------------------------------------
u_dp_mux : entity work.dp_mux
- generic map (
- g_mode => 4, -- Use sel_ctrl
- g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
- g_nof_input => g_nof_inputs,
- g_use_fifo => g_use_fifo,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_empty_w => g_empty_w,
- g_in_channel_w => g_in_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_in_channel => g_use_in_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
- g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
- )
- port map (
- clk => dp_clk,
- rst => dp_rst,
-
- sel_ctrl => dp_mux_sel_ctrl,
-
- snk_in_arr => inverted_snk_in_arr,
- snk_out_arr => inverted_snk_out_arr,
-
- src_out => src_out,
- src_in => src_in
- );
+ generic map (
+ g_mode => 4, -- Use sel_ctrl
+ g_sel_ctrl_invert => false, -- Dont invert, data is already reverse mapped from DOWNTO >> TO arrays.
+ g_nof_input => g_nof_inputs,
+ g_use_fifo => g_use_fifo,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_empty_w => g_empty_w,
+ g_in_channel_w => g_in_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_in_channel => g_use_in_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_size => array_init(g_fifo_size, g_nof_inputs),
+ g_fifo_fill => array_init(g_fifo_fill, g_nof_inputs)
+ )
+ port map (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ sel_ctrl => dp_mux_sel_ctrl,
+
+ snk_in_arr => inverted_snk_in_arr,
+ snk_out_arr => inverted_snk_out_arr,
+
+ src_out => src_out,
+ src_in => src_in
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index e17d04d777c8dd8c0464dc8658e8a8d563dc6122..411f67c5659df60f32a771ac0a1e1ba7e6d1147c 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_checker is
generic(
@@ -102,72 +102,73 @@ begin
v.snk_in := snk_in;
if(snk_in.sync = '1') then
- v.wait_for_next_sync := '0';
- v.sync_too_early := '0';
- end if;
-
- -- Check on incoming SOP if things are OK
- if (snk_in.sop = '1') then
- if(r.wait_for_next_sync = '0') then
- v.cnt_sop := r.cnt_sop + 1;
- end if;
- if(r.cnt_sop = c_nof_blk_per_sync) then
- v.cnt_sop := 0;
- if(r.sync_too_early = '1') then
- -- Too early
- v.wait_for_next_sync := '1';
- elsif(snk_in.sync = '0') then
- -- Too late
- v.wait_for_next_sync := '1';
- v.nof_late_syncs := r.nof_late_syncs + 1;
- end if;
- end if;
- end if;
-
- -- Detect SYNC that is too early
- if (snk_in.sync = '1' and r.cnt_sop < c_nof_blk_per_sync and r.wait_for_next_sync = '0') then
- v.sync_too_early := '1';
- v.snk_in.sync := '0'; -- Remove sync from input.
- v.nof_early_syncs := r.nof_early_syncs + 1;
- end if;
-
- -- Only pass input to output when not waiting for valid SYNC.
+ v.wait_for_next_sync := '0';
+ v.sync_too_early := '0';
+ end if;
+
+ -- Check on incoming SOP if things are OK
+ if (snk_in.sop = '1') then
if(r.wait_for_next_sync = '0') then
- v.src_out := r.snk_in;
- else
- v.src_out := c_dp_sosi_rst;
- end if;
-
- -- Reset the early and late sync counter
- if(clear_nof_early_syncs = '1') then
- v.nof_early_syncs := 0;
- end if;
-
- if(clear_nof_late_syncs = '1') then
- v.nof_late_syncs := 0;
- end if;
-
- if(dp_rst = '1') then
- v.snk_in := c_dp_sosi_rst;
- v.src_out := c_dp_sosi_rst;
- v.cnt_sop := 0;
- v.sync_too_early := '0';
- v.wait_for_next_sync := '1';
- v.nof_early_syncs := 0;
- v.nof_late_syncs := 0;
- end if;
-
- rin <= v;
- end process;
-
- p_regs : process(dp_clk)
- begin
- if rising_edge(dp_clk) then
- r <= rin;
- end if;
- end process;
-
- src_out <= r.src_out;
- nof_early_syncs <= TO_UVEC(r.nof_early_syncs, c_word_w);
- nof_late_syncs <= TO_UVEC(r.nof_late_syncs, c_word_w);
+ v.cnt_sop := r.cnt_sop + 1;
+ end if;
+ if(r.cnt_sop = c_nof_blk_per_sync) then
+ v.cnt_sop := 0;
+ if(r.sync_too_early = '1') then
+ -- Too early
+ v.wait_for_next_sync := '1';
+ elsif(snk_in.sync = '0') then
+ -- Too late
+ v.wait_for_next_sync := '1';
+ v.nof_late_syncs := r.nof_late_syncs + 1;
+end if;
+
+end if;
+end if;
+
+-- Detect SYNC that is too early
+if (snk_in.sync = '1' and r.cnt_sop < c_nof_blk_per_sync and r.wait_for_next_sync = '0') then
+ v.sync_too_early := '1';
+ v.snk_in.sync := '0'; -- Remove sync from input.
+ v.nof_early_syncs := r.nof_early_syncs + 1;
+end if;
+
+-- Only pass input to output when not waiting for valid SYNC.
+if(r.wait_for_next_sync = '0') then
+v.src_out := r.snk_in;
+else
+v.src_out := c_dp_sosi_rst;
+end if;
+
+-- Reset the early and late sync counter
+if(clear_nof_early_syncs = '1') then
+v.nof_early_syncs := 0;
+end if;
+
+if(clear_nof_late_syncs = '1') then
+v.nof_late_syncs := 0;
+end if;
+
+if(dp_rst = '1') then
+v.snk_in := c_dp_sosi_rst;
+v.src_out := c_dp_sosi_rst;
+v.cnt_sop := 0;
+v.sync_too_early := '0';
+v.wait_for_next_sync := '1';
+v.nof_early_syncs := 0;
+v.nof_late_syncs := 0;
+end if;
+
+rin <= v;
+end process;
+
+p_regs : process(dp_clk)
+begin
+ if rising_edge(dp_clk) then
+ r <= rin;
+ end if;
+end process;
+
+src_out <= r.src_out;
+nof_early_syncs <= TO_UVEC(r.nof_early_syncs, c_word_w);
+nof_late_syncs <= TO_UVEC(r.nof_late_syncs, c_word_w);
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
index d1da545d1af2c068b214a8ac38babc8c2b7865da..9a8439dc64ebf09334a421b1c561202b55c41a9a 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
@@ -35,10 +35,10 @@
-- incoming data is perfectly aligned. Use a dp_sync_checker to assure the incoming data is perfect.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index d5d54d2a23d6e683fe8936711552399d3e5bec2f..1ca272d041a70ddb0e72809e1c46fa8cdf6c221c 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -33,11 +33,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_insert_v2 is
generic (
@@ -120,27 +120,27 @@ begin
end process;
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_nof_blk_per_sync_mm_reg,
- g_init_reg => c_init_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => reg_nof_blk_per_sync,
- out_reg => reg_nof_blk_per_sync
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_nof_blk_per_sync_mm_reg,
+ g_init_reg => c_init_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => reg_nof_blk_per_sync,
+ out_reg => reg_nof_blk_per_sync
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 60fee25c8b2c1db2cef921d309acde526dcd4587..2f0620bbd8820a01b60659206f0a05aeecbb7458 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -38,11 +38,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_sync_recover is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
index d27a5f17436bb879a14cf9b7a40a9b01b9df2dc0..0f9395c66585d98e5c96a824c7b9e09ef60b9e4b 100644
--- a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
@@ -29,18 +29,18 @@
-- remove 0 or more head data and 0 or more tail data from the input block.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_tail_remove is
generic (
g_data_w : natural;
g_symbol_w : natural;
g_nof_symbols : natural -- Nof symbols to be stripped from end of the packet,
- -- and accounting for the nof empty symbols.
+ -- and accounting for the nof empty symbols.
);
port (
st_rst : in std_logic;
@@ -68,25 +68,25 @@ begin
snk_out <= src_in;
u_src_shift : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_output_reg,
- g_flush_eop => true,
- g_modify_support => true,
- g_nof_words => c_nof_shiftreg_words
- )
- port map (
- rst => st_rst,
- clk => st_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => snk_in,
- -- Control shift register contents
- cur_shiftreg_inputs => rd_sosi_arr,
- new_shiftreg_inputs => wr_sosi_arr,
- -- ST source
- src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
- src_out => src_out -- the shiftreg sources everything but the tail.
- );
+ generic map (
+ g_output_reg => c_output_reg,
+ g_flush_eop => true,
+ g_modify_support => true,
+ g_nof_words => c_nof_shiftreg_words
+ )
+ port map (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => snk_in,
+ -- Control shift register contents
+ cur_shiftreg_inputs => rd_sosi_arr,
+ new_shiftreg_inputs => wr_sosi_arr,
+ -- ST source
+ src_in => src_in, -- We correct the stream via new_shiftreg_inputs, so
+ src_out => src_out -- the shiftreg sources everything but the tail.
+ );
p_shift: process(rd_sosi_arr)
variable v_wr_sosi_arr : t_dp_sosi_arr(0 to c_nof_shiftreg_words - 1);
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index 0c1ab51619cf7a0d151571c9c38778bfd870ed3f..1bc951f435155acfe0030362484f6a3511a272c3 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -20,15 +20,15 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle is
generic (
g_dc_period : natural := 100; -- provides a resolution of 1% (1/100..100/100)
g_throttle_valid : boolean := false -- FALSE: Stream passes through, snk_out.ready is AND'ed with pulse
- -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
+ -- TRUE : Throttles src_out.valid instead of snk_out.ready; Onther entity I/O unused.
);
port (
rst : in std_logic;
@@ -60,20 +60,20 @@ begin
end generate;
u_common_duty_cycle : entity common_lib.common_duty_cycle
- generic map (
- g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
- g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
- g_act_lvl => '1',
- g_per_cnt => g_dc_period,
- g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
- )
- port map (
- rst => rst,
- clk => clk,
+ generic map (
+ g_rst_lvl => '0', -- Start with '0' on the output so our connected sink is not maxed out after reset
+ g_dis_lvl => '0', -- Don't care - dc_out_en is not used.
+ g_act_lvl => '1',
+ g_per_cnt => g_dc_period,
+ g_act_cnt => 0 -- After init, stay in idle state until we write a new DC value
+ )
+ port map (
+ rst => rst,
+ clk => clk,
- dc_act_cnt => throttle,
+ dc_act_cnt => throttle,
- dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
- dc_out => dc_out
- );
+ dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
+ dc_out => dc_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
index 3d755e41eef38b65af816033f904fbca74f1ee5f..1079d22c52eab7508b44a390443d35266ab2d443 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
@@ -20,9 +20,9 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_throttle_reg is
generic (
@@ -46,20 +46,21 @@ end dp_throttle_reg;
architecture rtl of dp_throttle_reg is
-- Define the actual size of the MM slave register
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
- dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 1,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 2,
+ dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
+ nof_dat => 1,
+ init_sl => '0');
- signal mm_throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
+ signal mm_throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
-- Access event, register values
mm_throttle <= (others => '0');
- elsif rising_edge(mm_clk) then
+ elsif rising_edge(mm_clk) then
-- Read access defaults
sla_out.rdval <= '0';
@@ -78,14 +79,14 @@ begin
end process;
u_common_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
- in_dat => mm_throttle,
- in_done => OPEN,
- out_rst => st_rst,
- out_clk => st_clk,
- out_dat => throttle,
- out_new => open
- );
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_dat => mm_throttle,
+ in_done => OPEN,
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => throttle,
+ out_new => open
+ );
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
index f90a6ffc44cab67006d4ca19d8352d519601b763..8820fc24b76a6d4d170108c50fa9c0c20c854ad8 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
@@ -26,9 +26,9 @@
-- . g_period is
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_sop is
generic (
@@ -57,34 +57,34 @@ begin
snk_out.xon <= '1';
u_common_counter : entity common_lib.common_counter
- generic map (
- g_width => c_cnt_w
- )
- port map (
- rst => rst,
- clk => clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => cycle_cnt
- );
+ generic map (
+ g_width => c_cnt_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => cycle_cnt
+ );
cnt_en <= '1' when TO_UINT(cycle_cnt) < g_period - 2 else '0';
cnt_clr <= snk_in.sop;
u_common_switch : entity common_lib.common_switch
- generic map (
- g_rst_level => '1',
- g_priority_lo => false,
- g_or_high => true,
- g_and_low => true
- )
- port map (
- clk => clk,
- rst => rst,
- switch_high => switch_high,
- switch_low => switch_low,
- out_level => switch_out
- );
+ generic map (
+ g_rst_level => '1',
+ g_priority_lo => false,
+ g_or_high => true,
+ g_and_low => true
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+ switch_high => switch_high,
+ switch_low => switch_low,
+ out_level => switch_out
+ );
switch_high <= not cnt_en;
switch_low <= snk_in.eop;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index dc6307419b85697a32049843aa797a4c6cff1c9c..b3cff3e0c421fbd8f020782a50efccd3141db133 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -29,9 +29,9 @@
-- * (1/'data valid duty_cycle').
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_throttle_xon is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 3df7cc4c185dbc765a534f033d12a27592ae1ab5..40939faf55c05fec7e062a3d87fc5ddb28f3618d 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
-- Author:
-- . Daniel van der Schuur
@@ -142,8 +142,8 @@ begin
-- Wire the 2D demux output array to 1D array to match entity I/O type
-----------------------------------------------------------------------------
gen_demux_inputs_0: for i in 0 to c_nof_demuxes - 1 generate
- demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
- demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
+ demux_src_out_arr(2 * i) <= demux_src_out_2arr_2(i)(0);
+ demux_src_out_arr(2 * i + 1) <= demux_src_out_2arr_2(i)(1);
end generate;
-----------------------------------------------------------------------------
@@ -172,6 +172,7 @@ begin
-- g_nof_unfolds=1, so this is the last stage. Wire up the outputs.
-----------------------------------------------------------------------------
gen_src_out_arr: if g_nof_unfolds = 1 generate
+
gen_output_align : if g_output_align = true generate
dp_pipeline_snk_in_arr <= demux_src_out_arr;
@@ -180,16 +181,16 @@ begin
-----------------------------------------------------------------------------
gen_dp_pipeline : for i in 0 to c_nof_outputs - 1 generate
u_dp_pipeline : entity dp_lib.dp_pipeline
- generic map (
- g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => dp_pipeline_snk_in_arr(i),
- src_out => dp_block_gen_snk_in_arr(i)
- );
+ generic map (
+ g_pipeline => 0 + (pow2(g_nof_unfolds) - i rem pow2(g_nof_unfolds) - 1)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_pipeline_snk_in_arr(i),
+ src_out => dp_block_gen_snk_in_arr(i)
+ );
end generate;
end generate;
@@ -201,22 +202,23 @@ begin
-- Add SOP and EOP to the outputs
-----------------------------------------------------------------------------
gen_ctrl : if g_output_block_size > 0 generate
+
gen_dp_block_gen : for i in 0 to c_nof_outputs - 1 generate
u_dp_block_gen : entity work.dp_block_gen
- generic map (
- g_use_src_in => false,
- g_nof_data => g_output_block_size,
- g_preserve_sync => true,
- g_preserve_bsn => true,
- g_preserve_channel => g_use_channel
- )
- port map(
- rst => rst,
- clk => clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
- src_out => dp_block_gen_src_out_arr(i)
- );
+ generic map (
+ g_use_src_in => false,
+ g_nof_data => g_output_block_size,
+ g_preserve_sync => true,
+ g_preserve_bsn => true,
+ g_preserve_channel => g_use_channel
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+
+ snk_in => dp_block_gen_snk_in_arr(i),
+ src_out => dp_block_gen_src_out_arr(i)
+ );
end generate;
end generate;
@@ -228,31 +230,31 @@ begin
-- Re-add input sync + BSN to all output streams
-----------------------------------------------------------------------------
gen_sync_bsn : if g_fwd_sync_bsn = true generate
+
gen_dp_fifo_info: for i in 0 to c_nof_outputs - 1 generate
u_dp_fifo_info : entity work.dp_fifo_info
- generic map (
- g_use_sync => true,
- g_use_bsn => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
- info_snk_in => snk_in_arr(0), -- original snk_in info
-
- src_in => c_dp_siso_rdy,
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_use_sync => true,
+ g_use_bsn => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ data_snk_in => dp_block_gen_src_out_arr(i), -- delayed snk_in data
+ info_snk_in => snk_in_arr(0), -- original snk_in info
+
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr(i)
+ );
end generate;
end generate;
no_sync_bsn : if g_fwd_sync_bsn = false generate
src_out_arr <= dp_block_gen_src_out_arr;
end generate;
-
- end generate;
- end generate;
+ end generate;
+ end generate;
-----------------------------------------------------------------------------
-- Wire output to input if g_nof_unfolds=0
@@ -260,5 +262,4 @@ begin
gen_wire_out_to_in: if g_nof_unfolds = 0 generate
dp_block_gen_snk_in_arr <= snk_in_arr;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 2e9d0f5b21e5c852c17edee51b699a5beabc3431..cf3dba4991edda99ee684c21aa69839962aa9477 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -20,10 +20,10 @@
--------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_packetizing_pkg.all;
-- Reuse from LOFAR rad_unframe.vhd and rad_unframe(rtl).vhd
@@ -73,12 +73,12 @@ entity dp_unframe is
out_eof : out std_logic;
out_err : out std_logic
);
-begin
--- synthesis translate_off
+ begin
+ -- synthesis translate_off
assert g_fsn_w <= g_dat_w
report "g_fsn_w must be smaller than or equal to g_dat_w"
- severity ERROR;
--- synthesis translate_on
+ severity ERROR;
+ -- synthesis translate_on
end dp_unframe;
architecture rtl of dp_unframe is
@@ -128,6 +128,7 @@ begin
out_dat <= i_out_dat;
gen_input_reg : if c_input_reg = true generate
+
p_reg : process (clk, rst)
begin
if rst = '1' then
diff --git a/libraries/base/dp/src/vhdl/dp_validate.vhd b/libraries/base/dp/src/vhdl/dp_validate.vhd
index 763676ec420ed4cadc52cefbe14d285f82a5714c..64bb3afa6a4056ed1e910bb865d00536b1cd51b9 100644
--- a/libraries/base/dp/src/vhdl/dp_validate.vhd
+++ b/libraries/base/dp/src/vhdl/dp_validate.vhd
@@ -21,9 +21,9 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- Assert valid, sop and eop only when they are valid.
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index a12132a9ea42961ed3a9147d985556f51829be0d..32e321cec811841c4c94c87a4a96475423f3c95b 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -47,10 +47,10 @@
-- data is carried via the sosi array dimension.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_sp_arr_scope is
generic (
@@ -83,48 +83,50 @@ architecture beh of dp_wideband_sp_arr_scope is
signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
sim_only : if g_sim = true generate
- use_sclk : if g_use_sclk = true generate
+ use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
- end generate;
+end generate;
- gen_sclk : if g_use_sclk = false generate
- proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
- end generate;
+gen_sclk : if g_use_sclk = false generate
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+end generate;
- -- View sp_sosi_arr at the sample rate using st_sosi_arr
- gen_arr : for I in 0 to g_nof_streams - 1 generate
- p_st_sosi_arr : process(SCLKi)
- variable vI : natural;
- begin
- if rising_edge(SCLKi) then
- if g_wideband_big_endian = true then
- vI := g_wideband_factor - 1 - scope_cnt_arr(I);
- else
- vI := scope_cnt_arr(I);
- end if;
- scope_cnt_arr(I) <= 0;
- if sp_sosi_arr(I).valid = '1' and scope_cnt_arr(I) < g_wideband_factor - 1 then
- scope_cnt_arr(I) <= scope_cnt_arr(I) + 1;
- end if;
- st_sosi_arr(I) <= sp_sosi_arr(I);
- -- Default set unused sp_sosi_arr(I) fields to 0 to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected within func_dp_stream_slv_to_integer()
- st_sosi_arr(I).data <= (others => '0');
- st_sosi_arr(I).re <= (others => '0');
- st_sosi_arr(I).im <= (others => '0');
- st_sosi_arr(I).empty <= (others => '0');
- st_sosi_arr(I).channel <= (others => '0');
- st_sosi_arr(I).err <= (others => '0');
- if g_complex then
- st_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).re((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
- st_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).im((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
- else
- st_sosi_arr(I).data <= RESIZE_DP_SDATA(sp_sosi_arr(I).data((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
- end if;
- end if;
- end process;
+-- View sp_sosi_arr at the sample rate using st_sosi_arr
+gen_arr : for I in 0 to g_nof_streams - 1 generate
+
+ p_st_sosi_arr : process(SCLKi)
+ variable vI : natural;
+ begin
+ if rising_edge(SCLKi) then
+ if g_wideband_big_endian = true then
+ vI := g_wideband_factor - 1 - scope_cnt_arr(I);
+ else
+ vI := scope_cnt_arr(I);
+ end if;
+ scope_cnt_arr(I) <= 0;
+ if sp_sosi_arr(I).valid = '1' and scope_cnt_arr(I) < g_wideband_factor - 1 then
+ scope_cnt_arr(I) <= scope_cnt_arr(I) + 1;
+ end if;
+ st_sosi_arr(I) <= sp_sosi_arr(I);
+ -- Default set unused sp_sosi_arr(I) fields to 0 to avoid Warning: NUMERIC_STD.TO_INTEGER: metavalue detected within func_dp_stream_slv_to_integer()
+ st_sosi_arr(I).data <= (others => '0');
+ st_sosi_arr(I).re <= (others => '0');
+ st_sosi_arr(I).im <= (others => '0');
+ st_sosi_arr(I).empty <= (others => '0');
+ st_sosi_arr(I).channel <= (others => '0');
+ st_sosi_arr(I).err <= (others => '0');
+ if g_complex then
+ st_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).re((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
+ st_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(sp_sosi_arr(I).im((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
+ else
+ st_sosi_arr(I).data <= RESIZE_DP_SDATA(sp_sosi_arr(I).data((g_wideband_factor - vI) * g_dat_w - 1 downto (g_wideband_factor - vI - 1) * g_dat_w));
+ end if;
+ end if;
+ end process;
+
+ -- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
+ scope_sosi_arr(I) <= func_dp_stream_slv_to_integer(st_sosi_arr(I), g_dat_w);
+end generate;
+end generate;
- -- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
- scope_sosi_arr(I) <= func_dp_stream_slv_to_integer(st_sosi_arr(I), g_dat_w);
- end generate;
- end generate;
end beh;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index fcedf587507c3e5aed27237bcec33f8be5d55e97..a42c202b3778c3b355fbc6f95c2cd960fbeaea09 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -40,9 +40,9 @@
-- field or in the (re, im) fields.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
entity dp_wideband_wb_arr_scope is
generic (
@@ -73,31 +73,32 @@ architecture beh of dp_wideband_wb_arr_scope is
signal st_sosi : t_dp_sosi;
begin
sim_only : if g_sim = true generate
- use_sclk : if g_use_sclk = true generate
+ use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
- end generate;
+end generate;
- gen_sclk : if g_use_sclk = false generate
- proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
- end generate;
+gen_sclk : if g_use_sclk = false generate
+ proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
+end generate;
- -- View wb_sosi_arr at the sample rate using st_sosi
- p_st_sosi : process(SCLKi)
- begin
- if rising_edge(SCLKi) then
- if g_wideband_big_endian = true then
- st_sosi <= wb_sosi_arr(g_wideband_factor - 1 - sample_cnt);
- else
- st_sosi <= wb_sosi_arr(sample_cnt);
- end if;
- sample_cnt <= 0;
- if wb_sosi_arr(0).valid = '1' and sample_cnt < g_wideband_factor - 1 then -- all wb_sosi_arr().valid are the same, so use (0)
- sample_cnt <= sample_cnt + 1;
- end if;
- end if;
- end process;
+-- View wb_sosi_arr at the sample rate using st_sosi
+p_st_sosi : process(SCLKi)
+begin
+ if rising_edge(SCLKi) then
+ if g_wideband_big_endian = true then
+ st_sosi <= wb_sosi_arr(g_wideband_factor - 1 - sample_cnt);
+ else
+ st_sosi <= wb_sosi_arr(sample_cnt);
+ end if;
+ sample_cnt <= 0;
+ if wb_sosi_arr(0).valid = '1' and sample_cnt < g_wideband_factor - 1 then -- all wb_sosi_arr().valid are the same, so use (0)
+ sample_cnt <= sample_cnt + 1;
+ end if;
+ end if;
+end process;
+
+-- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
+scope_sosi <= func_dp_stream_slv_to_integer(st_sosi, g_dat_w);
+end generate;
- -- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
- scope_sosi <= func_dp_stream_slv_to_integer(st_sosi, g_dat_w);
- end generate;
end beh;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff.vhd b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
index e9768eda7a94e66064fb093c00a703b5de5ef37d..2266bd287a0a94a50954cb5c758f0d2376230154 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
@@ -92,8 +92,8 @@
-- . Originally based on rad_frame_onoff from LOFAR RSP firmware
library IEEE;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
entity dp_xonoff is
generic (
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
index 7690cbfe3f5d12f8cafcec558220b4144ed6d28b..2800461d76c15289acf01434d076d6953cd8e979 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg is
generic (
@@ -58,13 +58,14 @@ entity dp_xonoff_reg is
end dp_xonoff_reg;
architecture str of dp_xonoff_reg is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
-
- signal mm_xonoff_reg : std_logic_vector(0 downto 0);
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value);
+
+ signal mm_xonoff_reg : std_logic_vector(0 downto 0);
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -84,17 +85,17 @@ begin
if sla_in.wr = '1' then
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
when 0 =>
- mm_xonoff_reg(0) <= sla_in.wrdata(0);
+ mm_xonoff_reg(0) <= sla_in.wrdata(0);
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(0) <= mm_xonoff_reg(0);
@@ -105,15 +106,15 @@ begin
end process;
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg,
+ in_dat => mm_xonoff_reg,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
index 4fd64c8f6e32acd2b9866efb3fe59b9d78607a17..0909824a42979aa64818ce21613ea53dc52eae78 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
@@ -33,9 +33,9 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
entity dp_xonoff_reg_timeout is
generic (
@@ -60,18 +60,19 @@ entity dp_xonoff_reg_timeout is
end dp_xonoff_reg_timeout;
architecture str of dp_xonoff_reg_timeout is
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 1,
- dat_w => c_word_w,
- nof_dat => 1,
- init_sl => g_default_value);
- constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6)); -- @50MHz
-
- signal mm_xonoff_reg : std_logic_vector(0 downto 0);
- signal mm_xonoff_reg_out : std_logic_vector(0 downto 0);
- signal counter : std_logic_vector(c_word_w - 1 downto 0);
- signal cnt_clr : std_logic := '0';
- signal cnt_en : std_logic := '1';
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => 1,
+ dat_w => c_word_w,
+ nof_dat => 1,
+ init_sl => g_default_value);
+ constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10 ** 6)); -- @50MHz
+
+ signal mm_xonoff_reg : std_logic_vector(0 downto 0);
+ signal mm_xonoff_reg_out : std_logic_vector(0 downto 0);
+ signal counter : std_logic_vector(c_word_w - 1 downto 0);
+ signal cnt_clr : std_logic := '0';
+ signal cnt_en : std_logic := '1';
begin
p_mm_reg : process (mm_rst, mm_clk)
begin
@@ -99,19 +100,19 @@ begin
when 0 =>
mm_xonoff_reg(0) <= sla_in.wrdata(0);
if sla_in.wrdata(0) = '1' then
- cnt_clr <= '1';
- cnt_en <= '1';
+ cnt_clr <= '1';
+ cnt_en <= '1';
end if;
when others => null; -- not used MM addresses
end case;
- -- Read access: get register value
+ -- Read access: get register value
elsif sla_in.rd = '1' then
sla_out <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
case TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) is
- -- Read Block Sync
+ -- Read Block Sync
when 0 =>
sla_out.rddata(0) <= mm_xonoff_reg(0);
@@ -122,27 +123,27 @@ begin
end process;
u_counter : entity common_lib.common_counter
- generic map (
- g_latency => 0
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
- cnt_clr => cnt_clr,
- cnt_en => cnt_en,
- count => counter
- );
+ generic map (
+ g_latency => 0
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
+ cnt_clr => cnt_clr,
+ cnt_en => cnt_en,
+ count => counter
+ );
u_reg_cross_domain : entity common_lib.common_reg_cross_domain
- port map (
- in_rst => mm_rst,
- in_clk => mm_clk,
+ port map (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
- in_dat => mm_xonoff_reg_out,
+ in_dat => mm_xonoff_reg_out,
- out_rst => st_rst,
- out_clk => st_clk,
+ out_rst => st_rst,
+ out_clk => st_clk,
- out_dat => xonoff_reg
- );
+ out_dat => xonoff_reg
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 20456ab387ba3873e6a87d8843bafd78250ac876..08dfd7964c960d1811ed2341a1c4e490e4ca3ebd 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -35,11 +35,11 @@
-- https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+aligner+v2
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_align_v2 is
generic (
@@ -116,29 +116,29 @@ architecture str of mmp_dp_bsn_align_v2 is
begin
-- MM control of BSN aligner
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_bsn_align_copi,
- sla_out => reg_bsn_align_cipo,
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => (others => '1') -- Default all g_nof_streams are enabled.
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_bsn_align_copi,
+ sla_out => reg_bsn_align_cipo,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
gen_reg : for I in 0 to g_nof_streams - 1 generate
stream_en_arr(I) <= sl(reg_wr(2 * I * c_word_w downto 2 * I * c_word_w));
@@ -155,58 +155,58 @@ begin
-- . all input streams (g_nof_input_bsn_monitors = g_nof_streams).
gen_bsn_mon_input : if g_nof_input_bsn_monitors > 0 generate
u_bsn_mon_input : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => g_nof_input_bsn_monitors,
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_input_monitor_copi,
- reg_miso => reg_input_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
- );
+ generic map (
+ g_nof_streams => g_nof_input_bsn_monitors,
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_input_monitor_copi,
+ reg_miso => reg_input_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => in_sosi_arr(g_nof_input_bsn_monitors - 1 downto 0)
+ );
end generate;
gen_bsn_mon_output : if g_use_bsn_output_monitor generate
u_bsn_mon_output : entity work.mms_dp_bsn_monitor_v2
- generic map (
- g_nof_streams => 1, -- all outputs have same BSN monitor information
- g_cross_clock_domain => true,
- g_sync_timeout => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_output_monitor_copi,
- reg_miso => reg_output_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => ref_sync,
-
- in_sosi_arr => mon_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => 1, -- all outputs have same BSN monitor information
+ g_cross_clock_domain => true,
+ g_sync_timeout => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_output_monitor_copi,
+ reg_miso => reg_output_monitor_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => ref_sync,
+
+ in_sosi_arr => mon_out_sosi_arr
+ );
end generate;
-- Use mm_sosi or out_sosi_arr(0) from BSN aligner for output BSN monitor
@@ -217,33 +217,33 @@ begin
out_sosi_arr <= i_out_sosi_arr;
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => g_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- node_index => node_index,
- -- MM control
- stream_en_arr => stream_en_arr,
- stream_replaced_cnt_arr => stream_replaced_cnt_arr,
- -- Streaming input
- in_sosi_arr => in_sosi_arr,
- -- Output via local MM in dp_clk domain
- mm_sosi => i_mm_sosi,
- mm_copi => mm_copi,
- mm_cipo_arr => mm_cipo_arr,
- -- Output via streaming DP interface, when g_use_mm_output = TRUE.
- out_sosi_arr => i_out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => g_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ node_index => node_index,
+ -- MM control
+ stream_en_arr => stream_en_arr,
+ stream_replaced_cnt_arr => stream_replaced_cnt_arr,
+ -- Streaming input
+ in_sosi_arr => in_sosi_arr,
+ -- Output via local MM in dp_clk domain
+ mm_sosi => i_mm_sosi,
+ mm_copi => mm_copi,
+ mm_cipo_arr => mm_cipo_arr,
+ -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+ out_sosi_arr => i_out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 4cab59e25a3a5fb7940625da40cb2af9a33d673f..05c8668aa1d73f7f89a316f219d9fcefc65f334e 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -55,10 +55,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler is
generic (
@@ -127,23 +127,23 @@ begin
-- . Write
wr_ctrl_enable <= reg_wr( 0);
ctrl_interval_size <= TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) when
- g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
+ g_ctrl_interval_size_min < TO_UINT(reg_wr( 2 * c_word_w - 1 downto 1 * c_word_w)) else g_ctrl_interval_size_min;
wr_start_bsn_64( c_word_w - 1 downto 0) <= reg_wr( 3 * c_word_w - 1 downto 2 * c_word_w); -- low word
wr_start_bsn_64(2 * c_word_w - 1 downto 1 * c_word_w) <= reg_wr( 4 * c_word_w - 1 downto 3 * c_word_w); -- high word
-- Derive ctrl_enable_evt from change in wr_ctrl_enable, instead of using
-- reg_wr_arr(0), see description
u_common_evt : entity common_lib.common_evt
- generic map (
- g_evt_type => "BOTH",
- g_out_reg => true
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_sig => wr_ctrl_enable,
- out_evt => wr_ctrl_enable_evt
- );
+ generic map (
+ g_evt_type => "BOTH",
+ g_out_reg => true
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sig => wr_ctrl_enable,
+ out_evt => wr_ctrl_enable_evt
+ );
ctrl_enable <= wr_ctrl_enable when rising_edge(dp_clk) and wr_ctrl_enable_evt = '1';
ctrl_enable_evt <= wr_ctrl_enable_evt when rising_edge(dp_clk);
@@ -163,56 +163,56 @@ begin
reg_rd(12 * c_word_w - 1 downto 11 * c_word_w) <= TO_UVEC(g_block_size, c_word_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
-
- -- MM registers in st_clk domain
- reg_wr_arr => reg_wr_arr,
- reg_rd_arr => OPEN,
- out_reg => reg_wr, -- readback via ST clock domain
- in_reg => reg_rd
- );
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => reg_wr_arr,
+ reg_rd_arr => OPEN,
+ out_reg => reg_wr, -- readback via ST clock domain
+ in_reg => reg_rd
+ );
u_dp_bsn_sync_scheduler : entity work.dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min,
- g_pipeline => 1
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_interval_size => mon_output_interval_size,
- mon_output_sync_bsn => mon_output_sync_bsn,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- M&C
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
index 85a154fa94cf94049225eab31c7d7e19d21e33c3..176e80286aad6aa46dc139824364fba85878a8a7 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -25,10 +25,10 @@
-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mmp_dp_bsn_sync_scheduler_arr is
generic (
@@ -66,42 +66,42 @@ architecture str of mmp_dp_bsn_sync_scheduler_arr is
begin
-- dp_bsn_sync_scheduler
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_ctrl_interval_size_min => g_ctrl_interval_size_min
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
- in_sosi => in_sosi_arr(0),
- out_sosi => single_src_out,
+ in_sosi => in_sosi_arr(0),
+ out_sosi => single_src_out,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
-- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
u_dp_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_out_arr => in_sosi_arr_piped
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_out_arr => in_sosi_arr_piped
+ );
p_streams : process(in_sosi_arr_piped, single_src_out)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 336f7e55650bcfe35676e4a5d72bfc1b5140ce16..c8e01bb8725d5a325705023a3f2874db2e48a33f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -30,12 +30,12 @@
-- The index_lo and index_hi can be read and set via the MM interface.
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_block_select is
generic (
@@ -62,8 +62,9 @@ entity mms_dp_block_select is
end mms_dp_block_select;
architecture str of mms_dp_block_select is
- constant c_field_arr : t_common_field_arr(1 downto 0) := ( (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
- (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
+ constant c_field_arr : t_common_field_arr(1 downto 0) := (
+ (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
+ (field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -72,46 +73,45 @@ architecture str of mms_dp_block_select is
begin
-- Use same control for all streams
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi,
- mm_miso => reg_miso,
+ mm_mosi => reg_mosi,
+ mm_miso => reg_miso,
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out
- );
+ slv_out => mm_fields_out
+ );
index_lo <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_lo") downto field_lo(c_field_arr, "index_lo")));
index_hi <= TO_UINT(mm_fields_out(field_hi(c_field_arr, "index_hi") downto field_lo(c_field_arr, "index_hi")));
gen_dp_block_select : for I in 0 to g_nof_streams - 1 generate
u_dp_block_select : entity work.dp_block_select
- generic map (
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Control
- index_lo => index_lo,
- index_hi => index_hi,
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
- );
+ generic map (
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Control
+ index_lo => index_lo,
+ index_hi => index_hi,
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index fd265dbd4009b7acff0a4d6d6da2de9065916e45..79465f5c5f03eacf55f3da7559533d4ced4e9eed 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_aligner
-- Description: See dp_bsn_aligner.vhd
@@ -64,47 +64,47 @@ architecture str of mms_dp_bsn_align is
signal en_arr : std_logic_vector(g_nof_input - 1 downto 0);
begin
u_align : entity work.dp_bsn_align
- generic map(
- g_block_size => g_block_size,
- g_block_period => g_block_period,
- g_nof_input => g_nof_input,
- g_xoff_timeout => g_xoff_timeout,
- g_sop_timeout => g_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map(
- rst => dp_rst,
- clk => dp_clk,
- -- ST sinks
- snk_out_arr => snk_out_arr,
- snk_in_arr => snk_in_arr,
- -- ST source
- src_in_arr => src_in_arr,
- src_out_arr => src_out_arr,
- -- MM
- in_en_evt => en_evt,
- in_en_arr => en_arr
- );
+ generic map(
+ g_block_size => g_block_size,
+ g_block_period => g_block_period,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => g_xoff_timeout,
+ g_sop_timeout => g_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map(
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sinks
+ snk_out_arr => snk_out_arr,
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_in_arr => src_in_arr,
+ src_out_arr => src_out_arr,
+ -- MM
+ in_en_evt => en_evt,
+ in_en_arr => en_arr
+ );
u_reg : entity work.dp_bsn_align_reg
- generic map (
- g_nof_input => g_nof_input,
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_nof_input => g_nof_input,
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- out_en_evt => en_evt,
- out_en_arr => en_arr
- );
+ -- MM registers in st_clk domain
+ out_en_evt => en_evt,
+ out_en_arr => en_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index 645f43333ff9b7cb54ce3df380b8ba1a0f318484..49b4ae2f71e42ac3cf968017d69cb26b642166d7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_monitor
-- Description: See dp_bsn_monitor.vhd
@@ -81,82 +81,81 @@ architecture str of mms_dp_bsn_monitor is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
- u_reg : entity work.dp_bsn_monitor_reg
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+ u_reg : entity work.dp_bsn_monitor_reg
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi,
- g_log_first_bsn => g_log_first_bsn
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
-
- mon_bsn_first => mon_bsn_first_arr(i),
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi,
+ g_log_first_bsn => g_log_first_bsn
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+
+ mon_bsn_first => mon_bsn_first_arr(i),
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index 5ba8560094d70960cc11046750eb30bdc7120eeb..c81c57cf758751b60caefffade53d55cb5e48ea6 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -24,12 +24,12 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_components_pkg.all;
entity mms_dp_bsn_monitor_v2 is
generic (
@@ -83,77 +83,76 @@ architecture str of mms_dp_bsn_monitor_v2 is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
- u_reg : entity work.dp_bsn_monitor_reg_v2
generic map (
- g_cross_clock_domain => g_cross_clock_domain
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- mon_evt => mon_evt_arr(i),
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
);
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+ u_reg : entity work.dp_bsn_monitor_reg_v2
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ mon_evt => mon_evt_arr(i),
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
+
u_mon : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => g_sync_timeout,
- g_error_bi => g_error_bi
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- ST interface
- in_siso => in_siso_arr(i),
- in_sosi => in_sosi_arr(i),
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
- mon_sync => OPEN,
- mon_sync_timeout => mon_sync_timeout_arr(i),
- -- . siso
- mon_ready_stable => mon_ready_stable_arr(i),
- mon_xon_stable => mon_xon_stable_arr(i),
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
- mon_nof_sop => mon_nof_sop_arr(i),
- mon_nof_err => mon_nof_err_arr(i),
- mon_nof_valid => mon_nof_valid_arr(i),
- mon_latency => mon_latency_arr(i)
- );
+ generic map (
+ g_sync_timeout => g_sync_timeout,
+ g_error_bi => g_error_bi
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- ST interface
+ in_siso => in_siso_arr(i),
+ in_sosi => in_sosi_arr(i),
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt_arr(i), -- pulses when new monitor data is available regarding the previous sync interval
+ mon_sync => OPEN,
+ mon_sync_timeout => mon_sync_timeout_arr(i),
+ -- . siso
+ mon_ready_stable => mon_ready_stable_arr(i),
+ mon_xon_stable => mon_xon_stable_arr(i),
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync_arr(i),
+ mon_nof_sop => mon_nof_sop_arr(i),
+ mon_nof_err => mon_nof_err_arr(i),
+ mon_nof_valid => mon_nof_valid_arr(i),
+ mon_latency => mon_latency_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index bf03acd736f054fe9f9bdb4dd0f619088f8036d7..16f521eda3bc22ecc15e708991d1b9769351cfbe 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose : MMS for dp_bsn_scheduler
-- Description: See dp_bsn_scheduler.vhd
@@ -55,36 +55,36 @@ architecture str of mms_dp_bsn_scheduler is
signal scheduled_bsn : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
begin
u_mm_reg : entity work.dp_bsn_scheduler_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in dp_clk domain
- st_current_bsn => snk_in.bsn,
- st_scheduled_bsn => scheduled_bsn
- );
+ -- MM registers in dp_clk domain
+ st_current_bsn => snk_in.bsn,
+ st_scheduled_bsn => scheduled_bsn
+ );
u_bsn_scheduler : entity work.dp_bsn_scheduler
- generic map (
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- scheduled_bsn => scheduled_bsn,
- -- Streaming
- snk_in => snk_in,
- trigger_out => trigger_out
- );
+ generic map (
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ scheduled_bsn => scheduled_bsn,
+ -- Streaming
+ snk_in => snk_in,
+ trigger_out => trigger_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index 9b7f13a519d752601ba4c88ebfd145c76e89d837..caea7b8ac40acac267e8d7c44ba3adf6d0a3cc74 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source is
generic (
@@ -67,49 +67,49 @@ begin
bs_sosi <= i_bs_sosi;
u_mm_reg : entity work.dp_bsn_source_reg
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_block_per_sync => g_nof_block_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_block_per_sync => g_nof_block_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_block_per_sync => nof_block_per_sync,
- st_init_bsn => init_bsn,
- st_current_bsn => capture_bsn
- );
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_block_per_sync => nof_block_per_sync,
+ st_init_bsn => init_bsn,
+ st_current_bsn => capture_bsn
+ );
u_bsn_source : entity work.dp_bsn_source
- generic map (
- g_block_size => g_block_size,
- g_nof_block_per_sync => g_nof_block_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- init_bsn => init_bsn,
- nof_block_per_sync => nof_block_per_sync,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_block_per_sync => g_nof_block_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ init_bsn => init_bsn,
+ nof_block_per_sync => nof_block_per_sync,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 92388ecf1eaa14e91dc3a24c27d05dd1c1913648..d88e0fdfcb80241fb944000dd4ab6adaafc5973e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -23,10 +23,10 @@
-- Description: See dp_bsn_source.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_bsn_source_v2 is
generic (
@@ -74,53 +74,53 @@ begin
bs_nof_clk_per_sync <= nof_clk_per_sync;
u_mm_reg : entity work.dp_bsn_source_reg_v2
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_clk_per_sync => g_nof_clk_per_sync
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_clk_per_sync => g_nof_clk_per_sync
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- -- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_clk_per_sync => nof_clk_per_sync,
- st_bsn_init => bsn_init,
- st_current_bsn => capture_bsn,
- st_bsn_time_offset => bsn_time_offset
- );
+ -- MM registers in st_clk domain
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_clk_per_sync => nof_clk_per_sync,
+ st_bsn_init => bsn_init,
+ st_current_bsn => capture_bsn,
+ st_bsn_time_offset => bsn_time_offset
+ );
u_bsn_source : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_nof_clk_per_sync,
- g_bsn_w => g_bsn_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- bs_restart => bs_restart,
- bs_new_interval => bs_new_interval,
- bsn_init => bsn_init,
- nof_clk_per_sync => nof_clk_per_sync,
- bsn_time_offset => bsn_time_offset,
- -- Streaming
- src_out => i_bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_nof_clk_per_sync,
+ g_bsn_w => g_bsn_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ bs_restart => bs_restart,
+ bs_new_interval => bs_new_interval,
+ bsn_init => bsn_init,
+ nof_clk_per_sync => nof_clk_per_sync,
+ bsn_time_offset => bsn_time_offset,
+ -- Streaming
+ src_out => i_bs_sosi
+ );
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
index 4cc0b97ba5c903ee48d33521efb305e9d000fda2..ba40aceb42a6ce8e139246ed99bccfa4ae79f230 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
@@ -27,12 +27,12 @@
-- Remarks:
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_fifo_fill is
generic (
@@ -67,9 +67,9 @@ entity mms_dp_fifo_fill is
dp_clk : in std_logic;
-- Monitor FIFO filling
--- wr_ful : OUT STD_LOGIC;
--- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
--- rd_emp : OUT STD_LOGIC;
+ -- wr_ful : OUT STD_LOGIC;
+ -- usedw : OUT STD_LOGIC_VECTOR(ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2))-1 DOWNTO 0); -- = ceil_log2(c_fifo_size)-1 DOWNTO 0
+ -- rd_emp : OUT STD_LOGIC;
-- ST sink
snk_out_arr : out t_dp_siso_arr(g_nof_streams - 1 downto 0);
@@ -89,41 +89,41 @@ architecture str of mms_dp_fifo_fill is
begin
gen_fifos : for I in 0 to g_nof_streams - 1 generate
dp_fifo_sc : entity work.dp_fifo_fill
- generic map (
- g_technology => g_technology,
- g_data_w => g_data_w,
- g_bsn_w => g_bsn_w,
- g_empty_w => g_empty_w,
- g_channel_w => g_channel_w,
- g_error_w => g_error_w,
- g_use_bsn => g_use_bsn,
- g_use_empty => g_use_empty,
- g_use_channel => g_use_channel,
- g_use_error => g_use_error,
- g_use_sync => g_use_sync,
- g_use_complex => g_use_complex,
- g_fifo_fill => g_fifo_fill,
- g_fifo_size => g_fifo_size,
- g_fifo_af_margin => g_fifo_af_margin,
- g_fifo_rl => g_fifo_rl
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- Monitor FIFO filling
- wr_ful => wr_ful_reg(I),
- usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
- rd_emp => rd_emp_reg(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ generic map (
+ g_technology => g_technology,
+ g_data_w => g_data_w,
+ g_bsn_w => g_bsn_w,
+ g_empty_w => g_empty_w,
+ g_channel_w => g_channel_w,
+ g_error_w => g_error_w,
+ g_use_bsn => g_use_bsn,
+ g_use_empty => g_use_empty,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_error,
+ g_use_sync => g_use_sync,
+ g_use_complex => g_use_complex,
+ g_fifo_fill => g_fifo_fill,
+ g_fifo_size => g_fifo_size,
+ g_fifo_af_margin => g_fifo_af_margin,
+ g_fifo_rl => g_fifo_rl
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- Monitor FIFO filling
+ wr_ful => wr_ful_reg(I),
+ usedw => fifo_usedw_reg(I * c_word_w + c_usedw_w - 1 downto I * c_word_w),
+ rd_emp => rd_emp_reg(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
);
- end generate;
+end generate;
- u_reg : entity work.dp_fifo_fill_reg
+u_reg : entity work.dp_fifo_fill_reg
generic map(
g_nof_streams => g_nof_streams,
g_cross_clock_domain => g_cross_clock_domain
@@ -140,8 +140,8 @@ begin
sla_out => reg_miso,
-- MM registers in st_clk domain
- used_w => fifo_usedw_reg,
- rd_emp => rd_emp_reg,
- wr_ful => wr_ful_reg
+ used_w => fifo_usedw_reg,
+ rd_emp => rd_emp_reg,
+ wr_ful => wr_ful_reg
);
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 8298bcacd57667b2e9c8f5eabcc68edbe367e7bb..3bab3dcecea6922af2ff19769427ba59d53f147d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_from_mm is
generic (
@@ -54,23 +54,23 @@ architecture str of mms_dp_fifo_from_mm is
signal mm_wr : std_logic;
begin
u_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
- generic map(
- g_fifo_size => g_wr_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
+ generic map(
+ g_fifo_size => g_wr_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
- src_out => wr_sosi,
- usedw => wr_usedw, -- used words from rd FIFO
+ src_out => wr_sosi,
+ usedw => wr_usedw, -- used words from rd FIFO
- mm_wr => mm_wr,
- mm_wrdata => mm_wr_data,
- mm_usedw => mm_wr_usedw, -- resized to 32 bits
- mm_availw => mm_wr_availw -- resized to 32 bits
+ mm_wr => mm_wr,
+ mm_wrdata => mm_wr_data,
+ mm_usedw => mm_wr_usedw, -- resized to 32 bits
+ mm_availw => mm_wr_availw -- resized to 32 bits
);
- u_dp_fifo_from_mm_reg: entity work.dp_fifo_from_mm_reg
+u_dp_fifo_from_mm_reg: entity work.dp_fifo_from_mm_reg
port map (
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -82,6 +82,6 @@ begin
mm_wr_availw => mm_wr_availw
);
- mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
- mm_wr <= data_mosi.wr;
+mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
+mm_wr <= data_mosi.wr;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index 982363aafe4d003065908446d703ce473d85c329..a9e01c6441b79ae45b2ab6916946f07bd80f222e 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_fifo_to_mm is
generic (
@@ -56,24 +56,24 @@ architecture str of mms_dp_fifo_to_mm is
signal mm_rd : std_logic;
begin
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
- generic map(
- g_fifo_size => g_rd_fifo_depth
- )
- port map (
- rst => mm_rst,
- clk => mm_clk,
+ generic map(
+ g_fifo_size => g_rd_fifo_depth
+ )
+ port map (
+ rst => mm_rst,
+ clk => mm_clk,
- snk_out => rd_siso,
- snk_in => rd_sosi,
- usedw => rd_usedw, -- used words from rd FIFO
+ snk_out => rd_siso,
+ snk_in => rd_sosi,
+ usedw => rd_usedw, -- used words from rd FIFO
- mm_rd => mm_rd,
- mm_rddata => mm_rd_data,
- mm_rdval => mm_rd_val,
- mm_usedw => mm_rd_usedw -- resized to 32 bits
+ mm_rd => mm_rd,
+ mm_rddata => mm_rd_data,
+ mm_rdval => mm_rd_val,
+ mm_usedw => mm_rd_usedw -- resized to 32 bits
);
- u_dp_fifo_to_mm_reg: entity work.dp_fifo_to_mm_reg
+u_dp_fifo_to_mm_reg: entity work.dp_fifo_to_mm_reg
port map (
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -84,7 +84,7 @@ begin
mm_rd_usedw => mm_rd_usedw
);
- data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
- data_miso.rdval <= mm_rd_val;
- mm_rd <= data_mosi.rd;
+data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
+data_miso.rdval <= mm_rd_val;
+mm_rd <= data_mosi.rd;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 78ef7e85f096233c9e3db7bf78bfa5ab55ca2fad..b53b22ac4aaa7590642cfdaccf74d302604fc29f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -33,10 +33,10 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel is
generic (
@@ -102,59 +102,59 @@ begin
reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w) <= reg_force_data_wr(4 * c_mm_reg.dat_w - 1 downto 3 * c_mm_reg.dat_w);
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_parallel : entity work.dp_force_data_parallel
- generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_data => force_data,
- force_re => force_re,
- force_im => force_im,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_data => force_data,
+ force_re => force_re,
+ force_im => force_im,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index 405a23ba8e716ff027a88e514b2db030e8adfbbe..53add18b98302336225e5819b7dd022734c75eec 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -34,10 +34,10 @@
-- etc.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_parallel_arr is
generic (
@@ -81,48 +81,48 @@ architecture str of mms_dp_force_data_parallel_arr is
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
generic map (
- g_dat_w => g_dat_w,
- g_increment_data => g_increment_data,
- g_increment_re => g_increment_re,
- g_increment_im => g_increment_im,
- g_increment_data_on_sop => g_increment_data_on_sop,
- g_increment_re_on_sop => g_increment_re_on_sop,
- g_increment_im_on_sop => g_increment_im_on_sop,
- g_restart_data_on_sync => g_restart_data_on_sync,
- g_restart_re_on_sync => g_restart_re_on_sync,
- g_restart_im_on_sync => g_restart_im_on_sync,
- g_restart_data_on_sop => g_restart_data_on_sop,
- g_restart_re_on_sop => g_restart_re_on_sop,
- g_restart_im_on_sop => g_restart_im_on_sop
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_parallel : entity work.mms_dp_force_data_parallel
+ generic map (
+ g_dat_w => g_dat_w,
+ g_increment_data => g_increment_data,
+ g_increment_re => g_increment_re,
+ g_increment_im => g_increment_im,
+ g_increment_data_on_sop => g_increment_data_on_sop,
+ g_increment_re_on_sop => g_increment_re_on_sop,
+ g_increment_im_on_sop => g_increment_im_on_sop,
+ g_restart_data_on_sync => g_restart_data_on_sync,
+ g_restart_re_on_sync => g_restart_re_on_sync,
+ g_restart_im_on_sync => g_restart_im_on_sync,
+ g_restart_data_on_sop => g_restart_data_on_sop,
+ g_restart_re_on_sop => g_restart_re_on_sop,
+ g_restart_im_on_sop => g_restart_im_on_sop
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 63de286f7c454f9e294ebe2725b020774714f619..a2bf72122782fc1191578613aaf29aad26217825 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -37,10 +37,10 @@
-- See description of dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial is
generic (
@@ -107,62 +107,62 @@ begin
-- read unused bits as '0' to save logic
reg_force_data_rd(1 * c_mm_reg.dat_w - 1 downto 2 + 0 * c_mm_reg.dat_w) <= (others => '0');
if c_index_w < c_mm_reg.dat_w then
- reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(2 * c_mm_reg.dat_w - 1 downto c_index_w + 1 * c_mm_reg.dat_w) <= (others => '0');
end if;
if g_dat_w < c_mm_reg.dat_w then
- reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
- reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(3 * c_mm_reg.dat_w - 1 downto g_dat_w + 2 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(4 * c_mm_reg.dat_w - 1 downto g_dat_w + 3 * c_mm_reg.dat_w) <= (others => '0');
+ reg_force_data_rd(5 * c_mm_reg.dat_w - 1 downto g_dat_w + 4 * c_mm_reg.dat_w) <= (others => '0');
end if;
end process;
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_force_data_mosi,
- sla_out => reg_force_data_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_force_data_mosi,
+ sla_out => reg_force_data_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- out_reg => reg_force_data_wr, -- readback via ST clock domain
- in_reg => reg_force_data_rd
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ out_reg => reg_force_data_wr, -- readback via ST clock domain
+ in_reg => reg_force_data_rd
+ );
u_dp_force_data_serial : entity work.dp_force_data_serial
- generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- MM control
- force_en => force_en,
- force_value => force_value,
- force_zero_n => force_zero_n,
- force_data => force_data ,
- force_re => force_re,
- force_im => force_im,
- force_index => force_index,
- -- ST sink
- snk_out => snk_out,
- snk_in => snk_in,
- -- ST source
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- MM control
+ force_en => force_en,
+ force_value => force_value,
+ force_zero_n => force_zero_n,
+ force_data => force_data ,
+ force_re => force_re,
+ force_im => force_im,
+ force_index => force_index,
+ -- ST sink
+ snk_out => snk_out,
+ snk_in => snk_in,
+ -- ST source
+ src_in => src_in,
+ src_out => src_out
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index 38e1ad0980603a0032a483758b2b3676546ad9ff..0062ec699c2ec4fc25bf0bbb8311299b4b0770f8 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -34,10 +34,10 @@
-- See description of mms_dp_force_data_serial.vhd.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_force_data_serial_arr is
generic (
@@ -71,39 +71,39 @@ architecture str of mms_dp_force_data_serial_arr is
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
begin
u_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_mm_reg_adr_w
- )
- port map (
- mosi => reg_force_data_mosi,
- miso => reg_force_data_miso,
- mosi_arr => reg_force_data_mosi_arr,
- miso_arr => reg_force_data_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
generic map (
- g_dat_w => g_dat_w,
- g_index_period => g_index_period,
- g_index_sample_block_n => g_index_sample_block_n
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_mm_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- -- MM control
- reg_force_data_mosi => reg_force_data_mosi_arr(I),
- reg_force_data_miso => reg_force_data_miso_arr(I),
- -- ST sink
- snk_out => snk_out_arr(I),
- snk_in => snk_in_arr(I),
- -- ST source
- src_in => src_in_arr(I),
- src_out => src_out_arr(I)
+ mosi => reg_force_data_mosi,
+ miso => reg_force_data_miso,
+ mosi_arr => reg_force_data_mosi_arr,
+ miso_arr => reg_force_data_miso_arr
);
+
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ u_mms_dp_force_data_serial : entity work.mms_dp_force_data_serial
+ generic map (
+ g_dat_w => g_dat_w,
+ g_index_period => g_index_period,
+ g_index_sample_block_n => g_index_sample_block_n
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM control
+ reg_force_data_mosi => reg_force_data_mosi_arr(I),
+ reg_force_data_miso => reg_force_data_miso_arr(I),
+ -- ST sink
+ snk_out => snk_out_arr(I),
+ snk_in => snk_in_arr(I),
+ -- ST source
+ src_in => src_in_arr(I),
+ src_out => src_out_arr(I)
+ );
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index cfb48e893704fbe95f331b1cce09c3fc5acb5530..914a300f3a046eb9971f8da8037fd44a3d1fadf8 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_arr which also tests this mms_dp_gain
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain is
generic (
@@ -86,45 +86,45 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_arr
- generic map (
- g_technology => g_technology,
- -- functional
- g_nof_streams => 1,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_technology => g_technology,
+ -- functional
+ g_nof_streams => 1,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM access to gain
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
+ -- MM access to gain
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
- -- ST
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
+ -- ST
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index f6915b5ef663b0b58dff63f1d6d0013cbc16f0e6..8836ceea34ef6a0fd2f2f4741eeaff2970c73498 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -52,11 +52,11 @@
-- . A dp_pipeline is used to pass through the dp_control_fields.
library IEEE, common_lib, common_mult_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_arr is
generic (
@@ -133,65 +133,66 @@ begin
reg_gain_im <= i_reg_gain_im;
u_common_reg_r_w_dc_re : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_re
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_re
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_re_mosi,
- sla_out => reg_gain_re_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_re_mosi,
+ sla_out => reg_gain_re_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_re,
- out_reg => i_reg_gain_re -- readback via ST clock domain
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_re,
+ out_reg => i_reg_gain_re -- readback via ST clock domain
+ );
gen_real_multiply : if c_real_multiply = true generate
+
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid,
- out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_b => in_sosi_arr(I).data(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid,
+ out_p => mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_real_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_real_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
@@ -199,77 +200,77 @@ begin
out_sosi_arr(I).valid <= mult_sosi_arr(I).valid;
out_sosi_arr(I).data <= RESIZE_DP_SDATA(mult_sosi_arr(I).data(g_out_dat_w - 1 downto 0)); -- sign extend
end process;
-
end generate gen_nof_streams;
end generate gen_real_multiply;
gen_complex_multiply : if c_real_multiply = false generate
+
gen_complex_gain : if g_complex_gain = true generate
u_common_reg_r_w_dc_im : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => true,
- g_readback => false,
- g_reg => c_mm_reg,
- g_init_reg => c_mm_reg_init_im
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => true,
+ g_readback => false,
+ g_reg => c_mm_reg,
+ g_init_reg => c_mm_reg_init_im
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_gain_im_mosi,
- sla_out => reg_gain_im_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_gain_im_mosi,
+ sla_out => reg_gain_im_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_reg => i_reg_gain_im,
- out_reg => i_reg_gain_im -- readback via ST clock domain
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_reg => i_reg_gain_im,
+ out_reg => i_reg_gain_im -- readback via ST clock domain
+ );
end generate gen_complex_gain;
-- ELSE: if g_complex_gain=FALSE then use default i_reg_gain_im, which is then typically g_gain_init_im=0 for all streams.
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_conjugate_b => false,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
- in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
- in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
- in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
- out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
- out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
- out_val => mult_sosi_arr(I).valid
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_conjugate_b => false,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => i_reg_gain_re((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_ai => i_reg_gain_im((I + 1) * g_gain_w - 1 downto I * g_gain_w),
+ in_br => in_sosi_arr(I).re(g_in_dat_w - 1 downto 0),
+ in_bi => in_sosi_arr(I).im(g_in_dat_w - 1 downto 0),
+ in_val => in_sosi_arr(I).valid, -- only propagate valid, not used internally
+ out_pr => mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0),
+ out_pi => mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0),
+ out_val => mult_sosi_arr(I).valid
+ );
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_complex_multiply_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in => in_sosi_arr(I),
- src_out => pipelined_in_sosi_arr(I)
- );
+ generic map (
+ g_pipeline => c_complex_multiply_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => in_sosi_arr(I),
+ src_out => pipelined_in_sosi_arr(I)
+ );
p_out_sosi_arr : process(mult_sosi_arr, pipelined_in_sosi_arr)
begin
@@ -278,7 +279,6 @@ begin
out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).re(g_out_dat_w - 1 downto 0)); -- sign extend
out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(mult_sosi_arr(I).im(g_out_dat_w - 1 downto 0)); -- sign extend
end process;
-
end generate gen_nof_streams;
end generate gen_complex_multiply;
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index f84253d771ccd9b74043b71ac88abce1dda33a1f..f4de6214229252013cd3e6b40054a4f5dc80fe13 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -27,11 +27,11 @@
-- . See tb_mms_dp_gain_serial_arr which also tests this mms_dp_gain_serial
library IEEE, common_lib, common_mult_lib, dp_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity mms_dp_gain_serial is
generic (
@@ -84,44 +84,44 @@ begin
out_sosi <= out_sosi_arr(0);
u_one : entity work.mms_dp_gain_serial_arr
- generic map (
- g_technology => g_technology,
- g_nof_streams => 1,
- g_nof_gains => g_nof_gains,
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => g_out_dat_w,
- g_gains_file_name => g_gains_file_name,
- g_gains_write_only => g_gains_write_only,
+ generic map (
+ g_technology => g_technology,
+ g_nof_streams => 1,
+ g_nof_gains => g_nof_gains,
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => g_out_dat_w,
+ g_gains_file_name => g_gains_file_name,
+ g_gains_write_only => g_gains_write_only,
- -- pipelining (typically use defaults)
- -- . real multiplier
- g_pipeline_real_mult_input => g_pipeline_real_mult_input,
- g_pipeline_real_mult_product => g_pipeline_real_mult_product,
- g_pipeline_real_mult_output => g_pipeline_real_mult_output,
- -- . complex multiplier
- g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
- g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
- g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
- g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ -- pipelining (typically use defaults)
+ -- . real multiplier
+ g_pipeline_real_mult_input => g_pipeline_real_mult_input,
+ g_pipeline_real_mult_product => g_pipeline_real_mult_product,
+ g_pipeline_real_mult_output => g_pipeline_real_mult_output,
+ -- . complex multiplier
+ g_pipeline_complex_mult_input => g_pipeline_complex_mult_input,
+ g_pipeline_complex_mult_product => g_pipeline_complex_mult_product,
+ g_pipeline_complex_mult_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_complex_mult_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- ram_gains_mosi => ram_gains_mosi,
- ram_gains_miso => ram_gains_miso,
+ -- MM interface
+ ram_gains_mosi => ram_gains_mosi,
+ ram_gains_miso => ram_gains_miso,
- -- ST interface
- gains_rd_address => gains_rd_address,
+ -- ST interface
+ gains_rd_address => gains_rd_address,
- in_sosi_arr => in_sosi_arr,
- out_sosi_arr => out_sosi_arr
- );
+ in_sosi_arr => in_sosi_arr,
+ out_sosi_arr => out_sosi_arr
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index e81bb5a6d051448e101a2ab40e71e463b3244cc2..4ae3e88844668966748cae124d470168a5b1eecc 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -40,13 +40,13 @@
-- choose the correct avs_common_mm_readlatency2 when creating the qsys system.
--
library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
library common_lib, common_mult_lib, technology_lib;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use technology_lib.technology_select_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_gain_serial_arr is
generic (
@@ -101,115 +101,116 @@ architecture str of mms_dp_gain_serial_arr is
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
- constant c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
- adr_w => ceil_log2(g_nof_gains),
- dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
- nof_dat => g_nof_gains,
- init_sl => '0');
+ constant c_mm_ram : t_c_mem := ( -- set latency to 2 to ease timing
+ latency => 2,
+ adr_w => ceil_log2(g_nof_gains),
+ dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
+ nof_dat => g_nof_gains,
+ init_sl => '0');
- constant c_pipeline_real_latency : natural := g_pipeline_real_mult_input
- + g_pipeline_real_mult_product
- + g_pipeline_real_mult_output
- + c_mm_ram.latency;
+ constant c_pipeline_real_latency : natural := g_pipeline_real_mult_input
+ + g_pipeline_real_mult_product
+ + g_pipeline_real_mult_output
+ + c_mm_ram.latency;
- constant c_pipeline_complex_latency : natural := g_pipeline_complex_mult_input
- + g_pipeline_complex_mult_product
- + g_pipeline_complex_mult_adder
- + g_pipeline_complex_mult_output
- + c_mm_ram.latency;
+ constant c_pipeline_complex_latency : natural := g_pipeline_complex_mult_input
+ + g_pipeline_complex_mult_product
+ + g_pipeline_complex_mult_adder
+ + g_pipeline_complex_mult_output
+ + c_mm_ram.latency;
- constant c_pipeline_latency : natural := sel_a_b(c_real_multiply, c_pipeline_real_latency, c_pipeline_complex_latency);
+ constant c_pipeline_latency : natural := sel_a_b(c_real_multiply, c_pipeline_real_latency, c_pipeline_complex_latency);
- type t_slv_rddata_arr is array (integer range <>) of std_logic_vector(c_mm_ram.dat_w - 1 downto 0);
- type t_slv_gains_arr is array (integer range <>) of std_logic_vector(g_gain_w - 1 downto 0);
- type t_slv_in_dat_arr is array (integer range <>) of std_logic_vector(g_in_dat_w - 1 downto 0);
- type t_slv_out_dat_arr is array (integer range <>) of std_logic_vector(g_out_dat_w - 1 downto 0);
+ type t_slv_rddata_arr is array (integer range <>) of std_logic_vector(c_mm_ram.dat_w - 1 downto 0);
+ type t_slv_gains_arr is array (integer range <>) of std_logic_vector(g_gain_w - 1 downto 0);
+ type t_slv_in_dat_arr is array (integer range <>) of std_logic_vector(g_in_dat_w - 1 downto 0);
+ type t_slv_out_dat_arr is array (integer range <>) of std_logic_vector(g_out_dat_w - 1 downto 0);
- signal mm_gains_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
- signal mm_gains_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
+ signal mm_gains_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
+ signal mm_gains_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
- signal gains_rd_data_arr : t_slv_rddata_arr(g_nof_streams - 1 downto 0);
- signal gains_re_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
- signal gains_im_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
+ signal gains_rd_data_arr : t_slv_rddata_arr(g_nof_streams - 1 downto 0);
+ signal gains_re_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
+ signal gains_im_arr : t_slv_gains_arr(g_nof_streams - 1 downto 0);
- signal in_sosi_arr_pipe : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal in_sosi_arr_pipe_ctrl : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal in_dat_re_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
- signal in_dat_im_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
- signal in_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal in_sosi_arr_pipe : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal in_sosi_arr_pipe_ctrl : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+ signal in_dat_re_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
+ signal in_dat_im_arr : t_slv_in_dat_arr(g_nof_streams - 1 downto 0);
+ signal in_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
- signal out_dat_re_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
- signal out_dat_im_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
- signal out_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
+ signal out_dat_re_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
+ signal out_dat_im_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
+ signal out_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
begin
-- pipeline in_sosi_arr to align it with gains_rd_data_arr
u_pipeline_arr : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_mm_ram.latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe
+ );
-- pipeline in_sosi_arr to add sop, eop and sync back in out_sosi_arr
u_pipeline_arr_ctrl : entity work.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_pipeline_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => in_sosi_arr,
- src_out_arr => in_sosi_arr_pipe_ctrl
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_pipeline_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in_arr => in_sosi_arr,
+ src_out_arr => in_sosi_arr_pipe_ctrl
+ );
u_mem_mux_gains : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(g_nof_gains)
- )
- port map (
- mosi => ram_gains_mosi,
- miso => ram_gains_miso,
- mosi_arr => mm_gains_mosi_arr,
- miso_arr => mm_gains_miso_arr
- );
-
- gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
- -- Instantiate a gains memory for each input stream:
- u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
generic map (
- g_technology => g_technology,
- g_ram => c_mm_ram,
- g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
- g_true_dual_port => not(g_gains_write_only)
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(g_nof_gains)
)
port map (
- -- MM side
- rst_a => mm_rst,
- clk_a => mm_clk,
- wr_en_a => mm_gains_mosi_arr(I).wr,
- wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
- adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
- rd_en_a => mm_gains_mosi_arr(I).rd,
- rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
- rd_val_a => mm_gains_miso_arr(I).rdval,
- -- ST side
- rst_b => dp_rst,
- clk_b => dp_clk,
- wr_en_b => '0',
- wr_dat_b => (others => '0'),
- adr_b => gains_rd_address,
- rd_en_b => '1',
- rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
- rd_val_b => open
+ mosi => ram_gains_mosi,
+ miso => ram_gains_miso,
+ mosi_arr => mm_gains_mosi_arr,
+ miso_arr => mm_gains_miso_arr
);
+ gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
+ -- Instantiate a gains memory for each input stream:
+ u_common_ram_crw_crw : entity common_lib.common_ram_crw_crw
+ generic map (
+ g_technology => g_technology,
+ g_ram => c_mm_ram,
+ g_init_file => sel_a_b(g_gains_file_name = "UNUSED", g_gains_file_name, g_gains_file_name & "_" & natural'image(I) & ".hex"),
+ g_true_dual_port => not(g_gains_write_only)
+ )
+ port map (
+ -- MM side
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+ wr_en_a => mm_gains_mosi_arr(I).wr,
+ wr_dat_a => mm_gains_mosi_arr(I).wrdata(c_mm_ram.dat_w - 1 downto 0),
+ adr_a => mm_gains_mosi_arr(I).address(c_mm_ram.adr_w - 1 downto 0),
+ rd_en_a => mm_gains_mosi_arr(I).rd,
+ rd_dat_a => mm_gains_miso_arr(I).rddata(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_a => mm_gains_miso_arr(I).rdval,
+ -- ST side
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+ wr_en_b => '0',
+ wr_dat_b => (others => '0'),
+ adr_b => gains_rd_address,
+ rd_en_b => '1',
+ rd_dat_b => gains_rd_data_arr(I)(c_mm_ram.dat_w - 1 downto 0),
+ rd_val_b => open
+ );
+
gen_real_multiply : if c_real_multiply = true generate
gains_re_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
@@ -217,27 +218,27 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_mult : entity common_mult_lib.common_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
- g_nof_mult => 1,
- g_pipeline_input => g_pipeline_real_mult_input,
- g_pipeline_product => g_pipeline_real_mult_product,
- g_pipeline_output => g_pipeline_real_mult_output,
- g_representation => "SIGNED" -- or "UNSIGNED"
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_a => gains_re_arr(I),
- in_b => in_dat_re_arr(I),
- in_val => in_val_arr(I),
- out_p => out_dat_re_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w, -- g_out_dat_w = g_gain_w+g_in_dat_w, use smaller g_out_dat_w to truncate MSbits, or larger g_out_dat_w to extend MSbits
+ g_nof_mult => 1,
+ g_pipeline_input => g_pipeline_real_mult_input,
+ g_pipeline_product => g_pipeline_real_mult_product,
+ g_pipeline_output => g_pipeline_real_mult_output,
+ g_representation => "SIGNED" -- or "UNSIGNED"
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_a => gains_re_arr(I),
+ in_b => in_dat_re_arr(I),
+ in_val => in_val_arr(I),
+ out_p => out_dat_re_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, in_sosi_arr_pipe_ctrl)
begin
@@ -252,6 +253,7 @@ begin
end generate gen_real_multiply;
gen_complex_multiply : if c_real_multiply = false generate
+
gen_real_gain : if g_complex_gain = false generate
gains_re_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
gains_im_arr(I) <= gains_rd_data_arr(I)(g_gain_w - 1 downto 0);
@@ -267,30 +269,30 @@ begin
in_val_arr(I) <= in_sosi_arr_pipe(I).valid;
u_common_complex_mult : entity common_mult_lib.common_complex_mult
- generic map (
- g_technology => g_technology,
- g_variant => "IP",
- g_in_a_w => g_gain_w,
- g_in_b_w => g_in_dat_w,
- g_out_p_w => g_out_dat_w,
- g_conjugate_b => c_conjugate,
- g_pipeline_input => g_pipeline_complex_mult_input,
- g_pipeline_product => g_pipeline_complex_mult_product,
- g_pipeline_adder => g_pipeline_complex_mult_adder,
- g_pipeline_output => g_pipeline_complex_mult_output
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- in_ar => gains_re_arr(I),
- in_ai => gains_im_arr(I),
- in_br => in_dat_re_arr(I),
- in_bi => in_dat_im_arr(I),
- in_val => in_val_arr(I),
- out_pr => out_dat_re_arr(I),
- out_pi => out_dat_im_arr(I),
- out_val => out_val_arr(I)
- );
+ generic map (
+ g_technology => g_technology,
+ g_variant => "IP",
+ g_in_a_w => g_gain_w,
+ g_in_b_w => g_in_dat_w,
+ g_out_p_w => g_out_dat_w,
+ g_conjugate_b => c_conjugate,
+ g_pipeline_input => g_pipeline_complex_mult_input,
+ g_pipeline_product => g_pipeline_complex_mult_product,
+ g_pipeline_adder => g_pipeline_complex_mult_adder,
+ g_pipeline_output => g_pipeline_complex_mult_output
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => gains_re_arr(I),
+ in_ai => gains_im_arr(I),
+ in_br => in_dat_re_arr(I),
+ in_bi => in_dat_im_arr(I),
+ in_val => in_val_arr(I),
+ out_pr => out_dat_re_arr(I),
+ out_pi => out_dat_im_arr(I),
+ out_val => out_val_arr(I)
+ );
p_out_sosi_arr : process(out_val_arr, out_dat_re_arr, out_dat_im_arr, in_sosi_arr_pipe_ctrl)
begin
diff --git a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
index 5191eef130c0cbf7c8b564763723026555d413da..d7702463b193b05f0476a26f68b83b940b5df8bb 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
@@ -24,12 +24,12 @@
-- Remarks:
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_packet_merge is
generic (
@@ -70,50 +70,49 @@ architecture str of mms_dp_packet_merge is
signal nof_pkt : t_nof_pkt_arr;
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => ceil_log2(field_nof_words(c_field_arr, c_word_w))
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_stream : for i in 0 to g_nof_streams - 1 generate
u_mm_fields: entity mm_lib.mm_fields
- generic map(
- g_field_arr => c_field_arr
- )
- port map (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ generic map(
+ g_field_arr => c_field_arr
+ )
+ port map (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mm_mosi => reg_mosi_arr(i),
- mm_miso => reg_miso_arr(i),
+ mm_mosi => reg_mosi_arr(i),
+ mm_miso => reg_miso_arr(i),
- slv_clk => dp_clk,
- slv_rst => dp_rst,
+ slv_clk => dp_clk,
+ slv_rst => dp_rst,
- slv_out => mm_fields_out_arr(i)
- );
+ slv_out => mm_fields_out_arr(i)
+ );
nof_pkt(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "nof_pkt") downto field_lo(c_field_arr, "nof_pkt"));
u_dp_merge : entity work.dp_packet_merge
- generic map (
- g_nof_pkt => g_nof_pkt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_pkt => nof_pkt(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in => src_in_arr(i),
- src_out => src_out_arr(i)
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_pkt => nof_pkt(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
index 47d9371bc9aa81f8bafb3e427e274f85ccaa46eb..d663f4355b400ab64d7ca3060523ddccafd6b78a 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity mms_dp_ram_from_mm is
generic (
@@ -48,44 +48,44 @@ entity mms_dp_ram_from_mm is
end mms_dp_ram_from_mm;
architecture str of mms_dp_ram_from_mm is
- signal dp_on : std_logic;
+ signal dp_on : std_logic;
begin
- u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
- generic map(
- g_ram_wr_nof_words => g_ram_wr_nof_words,
- g_ram_rd_dat_w => g_ram_rd_dat_w,
- g_init_file => g_init_file
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
+ generic map(
+ g_ram_wr_nof_words => g_ram_wr_nof_words,
+ g_ram_rd_dat_w => g_ram_rd_dat_w,
+ g_init_file => g_init_file
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- mm_addr => ram_mosi.address,
- mm_wr => ram_mosi.wr,
- mm_wrdata => ram_mosi.wrdata,
+ mm_addr => ram_mosi.address,
+ mm_wr => ram_mosi.wr,
+ mm_wrdata => ram_mosi.wrdata,
- dp_on => dp_on,
+ dp_on => dp_on,
- src_in => src_in,
- src_out => src_out
- );
+ src_in => src_in,
+ src_out => src_out
+ );
u_dp_ram_from_mm_reg: entity work.dp_ram_from_mm_reg
- generic map(
- g_dp_on_at_init => g_dp_on_at_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map(
+ g_dp_on_at_init => g_dp_on_at_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => st_rst,
- st_clk => st_clk,
+ st_rst => st_rst,
+ st_clk => st_clk,
- sla_in => reg_mosi,
+ sla_in => reg_mosi,
- dp_on => dp_on
- );
+ dp_on => dp_on
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
index 37b2b5a73d502da1f556d1c78733a976eae220af..ac25743d8232d46b3aad2a2dbd3a06ce6b20d9ee 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
@@ -29,10 +29,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_scale is
generic (
@@ -51,7 +51,7 @@ entity mms_dp_scale is
g_lsb_round_clip : boolean := false; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
g_msb_clip : boolean := true; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : boolean := false -- when TRUE CLIP signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
- -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
+ -- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
);
port (
-- System
@@ -85,56 +85,56 @@ begin
-- Gain
---------------------------------------------------------------
u_mms_dp_gain : entity work.mms_dp_gain
- generic map (
- g_complex_data => g_complex_data,
- g_complex_gain => g_complex_gain,
- g_gain_init_re => g_gain_init_re,
- g_gain_init_im => g_gain_init_im,
- g_gain_w => g_gain_w,
- g_in_dat_w => g_in_dat_w,
- g_out_dat_w => c_gain_out_dat_w
- )
- port map (
- -- System
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ generic map (
+ g_complex_data => g_complex_data,
+ g_complex_gain => g_complex_gain,
+ g_gain_init_re => g_gain_init_re,
+ g_gain_init_im => g_gain_init_im,
+ g_gain_w => g_gain_w,
+ g_in_dat_w => g_in_dat_w,
+ g_out_dat_w => c_gain_out_dat_w
+ )
+ port map (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- -- MM interface
- reg_gain_re_mosi => reg_gain_re_mosi,
- reg_gain_re_miso => reg_gain_re_miso,
- reg_gain_im_mosi => reg_gain_im_mosi,
- reg_gain_im_miso => reg_gain_im_miso,
+ -- MM interface
+ reg_gain_re_mosi => reg_gain_re_mosi,
+ reg_gain_re_miso => reg_gain_re_miso,
+ reg_gain_im_mosi => reg_gain_im_mosi,
+ reg_gain_im_miso => reg_gain_im_miso,
- reg_gain_re => reg_gain_re,
- reg_gain_im => reg_gain_im,
+ reg_gain_re => reg_gain_re,
+ reg_gain_im => reg_gain_im,
- in_sosi => in_sosi,
- out_sosi => dp_gain_out_sosi
- );
+ in_sosi => in_sosi,
+ out_sosi => dp_gain_out_sosi
+ );
---------------------------------------------------------------
-- Requantize
---------------------------------------------------------------
u_dp_requantize : entity work.dp_requantize
- generic map (
- g_complex => c_dp_requantize_complex,
- g_representation => "SIGNED",
- g_lsb_w => g_lsb_w,
- g_lsb_round => g_lsb_round,
- g_lsb_round_clip => g_lsb_round_clip,
- g_msb_clip => g_msb_clip,
- g_msb_clip_symmetric => g_msb_clip_symmetric,
- g_in_dat_w => c_gain_out_dat_w,
- g_out_dat_w => g_out_dat_w
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_gain_out_sosi,
- -- ST source
- src_out => out_sosi
- );
+ generic map (
+ g_complex => c_dp_requantize_complex,
+ g_representation => "SIGNED",
+ g_lsb_w => g_lsb_w,
+ g_lsb_round => g_lsb_round,
+ g_lsb_round_clip => g_lsb_round_clip,
+ g_msb_clip => g_msb_clip,
+ g_msb_clip_symmetric => g_msb_clip_symmetric,
+ g_in_dat_w => c_gain_out_dat_w,
+ g_out_dat_w => g_out_dat_w
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_gain_out_sosi,
+ -- ST source
+ src_out => out_sosi
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index ee7ade081fde5e7f57217c5313a7238ff945c635..4bdef4cf2533851102fc1dfe738c0bed12eb8401 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_split is
generic (
@@ -67,55 +67,54 @@ architecture str of mms_dp_split is
signal nof_symbols : t_nof_symbols_arr;
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
-
- gen_stream : for i in 0 to g_nof_streams - 1 generate
- out_nof_symbols(i) <= TO_UINT(nof_symbols(i));
-
- u_reg : entity work.dp_split_reg
generic map (
- g_nof_symbols => g_nof_symbols_max
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_reg_adr_w
)
port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
+ gen_stream : for i in 0 to g_nof_streams - 1 generate
+ out_nof_symbols(i) <= TO_UINT(nof_symbols(i));
- -- MM registers in dp_clk domain
- -- . control
- nof_symbols => nof_symbols(i)
- );
+ u_reg : entity work.dp_split_reg
+ generic map (
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ nof_symbols => nof_symbols(i)
+ );
u_dp_split : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- nof_symbols => nof_symbols(i),
- snk_out => snk_out_arr(i),
- snk_in => snk_in_arr(i),
- src_in_arr => src_in_2arr(i),
- src_out_arr => src_out_2arr(i)
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ nof_symbols => nof_symbols(i),
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ src_in_arr => src_in_2arr(i),
+ src_out_arr => src_out_2arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index ad8d312d44271b1ebad5b073a69b28b738348639..07d8cde2b4c3904382e06bbfdae19f90f0fc0f2c 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -48,11 +48,11 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker is
generic(
@@ -83,60 +83,61 @@ end mms_dp_sync_checker;
architecture str of mms_dp_sync_checker is
-- Define the actual size of the MM slave register
constant c_nof_regs : positive := 2;
- constant c_mm_reg : t_c_mem := (latency => 1,
- adr_w => ceil_log2(c_nof_regs),
- dat_w => c_word_w,
- nof_dat => c_nof_regs,
- init_sl => '0');
+ constant c_mm_reg : t_c_mem := (
+ latency => 1,
+ adr_w => ceil_log2(c_nof_regs),
+ dat_w => c_word_w,
+ nof_dat => c_nof_regs,
+ init_sl => '0');
- signal read_register : std_logic_vector(c_nof_regs * c_word_w - 1 downto 0);
- signal nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
- signal nof_late_syncs : std_logic_vector(c_word_w - 1 downto 0);
- signal reg_rd_arr : std_logic_vector(c_nof_regs - 1 downto 0);
+ signal read_register : std_logic_vector(c_nof_regs * c_word_w - 1 downto 0);
+ signal nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
+ signal nof_late_syncs : std_logic_vector(c_word_w - 1 downto 0);
+ signal reg_rd_arr : std_logic_vector(c_nof_regs - 1 downto 0);
begin
u_dp_sync_checker : entity work.dp_sync_checker
- generic map(
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
- snk_out => snk_out,
- snk_in => snk_in,
- src_in => src_in,
- src_out => src_out,
- nof_early_syncs => nof_early_syncs,
- nof_late_syncs => nof_late_syncs,
- clear_nof_early_syncs => reg_rd_arr(0),
- clear_nof_late_syncs => reg_rd_arr(1)
- );
+ generic map(
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ snk_out => snk_out,
+ snk_in => snk_in,
+ src_in => src_in,
+ src_out => src_out,
+ nof_early_syncs => nof_early_syncs,
+ nof_late_syncs => nof_late_syncs,
+ clear_nof_early_syncs => reg_rd_arr(0),
+ clear_nof_late_syncs => reg_rd_arr(1)
+ );
read_register <= nof_late_syncs & nof_early_syncs;
u_reg : entity common_lib.common_reg_r_w_dc
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_in_new_latency => 1,
- g_readback => true,
- g_reg => c_mm_reg
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_in_new_latency => 1,
+ g_readback => true,
+ g_reg => c_mm_reg
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_dp_sync_checker_mosi,
- sla_out => reg_dp_sync_checker_miso,
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_dp_sync_checker_mosi,
+ sla_out => reg_dp_sync_checker_miso,
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => reg_rd_arr,
- in_new => OPEN,
- in_reg => read_register,
- out_reg => OPEN,
- out_new => open
- );
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => reg_rd_arr,
+ in_new => OPEN,
+ in_reg => read_register,
+ out_reg => OPEN,
+ out_new => open
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index 1d6a6bbdefe88010c2d0e35c81db0967b84ede59..713c40105f1c4860355fa04a603e37225b450935 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -28,9 +28,9 @@
-- share the same sync as input 0, as is the case e.g. after a dp_bsn_aligner.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_sync_checker_arr is
generic(
@@ -70,43 +70,43 @@ begin
-- Check sync on input stream 0
u_mms_dp_sync_checker : entity work.mms_dp_sync_checker
- generic map (
- g_cross_clock_domain => g_cross_clock_domain,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ generic map (
+ g_cross_clock_domain => g_cross_clock_domain,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- -- ST sinks
- snk_out => sync_checker_snk_out,
- snk_in => snk_in_arr(0),
- -- ST source
- src_in => src_in_arr(0),
- src_out => sync_checker_src_out,
+ -- ST sinks
+ snk_out => sync_checker_snk_out,
+ snk_in => snk_in_arr(0),
+ -- ST source
+ src_in => src_in_arr(0),
+ src_out => sync_checker_src_out,
- -- Memory Mapped
- reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
- reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
- );
+ -- Memory Mapped
+ reg_dp_sync_checker_mosi => reg_dp_sync_checker_mosi,
+ reg_dp_sync_checker_miso => reg_dp_sync_checker_miso
+ );
-- Pipeline all input streams with same latency as mms_dp_sync_checker
u_dp_pipeline_arr : entity dp_lib.dp_pipeline_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_pipeline => c_latency
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in_arr => snk_in_arr,
- -- ST source
- src_out_arr => pipeline_src_out_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_pipeline => c_latency
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in_arr => snk_in_arr,
+ -- ST source
+ src_out_arr => pipeline_src_out_arr
+ );
-- copy sync_checker control to all output streams, pass on the pipelined data
p_copy_sync_checker_controls : process(sync_checker_src_out, pipeline_src_out_arr)
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 8194cddac1c46f57530f88d33649a57edd6a4d1b..1a343432bde562544a5002f6eaaf16d73373b12d 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -20,10 +20,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_throttle is
generic (
@@ -52,38 +52,38 @@ architecture str of mms_dp_throttle is
signal throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
begin
u_dp_throttle_reg : entity work.dp_throttle_reg
- generic map (
- g_dc_period => g_dc_period
- )
- port map (
+ generic map (
+ g_dc_period => g_dc_period
+ )
+ port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
- sla_in => reg_mosi,
- sla_out => reg_miso,
+ sla_in => reg_mosi,
+ sla_out => reg_miso,
- throttle => throttle
- );
+ throttle => throttle
+ );
u_dp_throttle : entity work.dp_throttle
- generic map (
- g_dc_period => g_dc_period,
- g_throttle_valid => g_throttle_valid
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_dc_period => g_dc_period,
+ g_throttle_valid => g_throttle_valid
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- snk_out => snk_out,
- snk_in => snk_in,
+ snk_out => snk_out,
+ snk_in => snk_in,
- src_in => src_in,
- src_out => src_out,
+ src_in => src_in,
+ src_out => src_out,
- throttle => throttle
- );
+ throttle => throttle
+ );
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index ac9ddc3c2c61bc2adb2aeb61bafddccc6059a8b6..a18362dbdbb5957a9a993350d8ddd72abe0de202 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
entity mms_dp_xonoff is
generic (
@@ -71,62 +71,63 @@ architecture str of mms_dp_xonoff is
signal src_in_arr_i : t_dp_siso_arr(g_nof_streams - 1 downto 0);
begin
u_common_mem_mux : entity common_lib.common_mem_mux
- generic map (
- g_nof_mosi => c_nof_ctrl_streams,
- g_mult_addr_w => c_reg_adr_w
- )
- port map (
- mosi => reg_mosi,
- miso => reg_miso,
- mosi_arr => reg_mosi_arr,
- miso_arr => reg_miso_arr
- );
+ generic map (
+ g_nof_mosi => c_nof_ctrl_streams,
+ g_mult_addr_w => c_reg_adr_w
+ )
+ port map (
+ mosi => reg_mosi,
+ miso => reg_miso,
+ mosi_arr => reg_mosi_arr,
+ miso_arr => reg_miso_arr
+ );
gen_reg : for i in 0 to c_nof_ctrl_streams - 1 generate
+
gen_no_timeout : if g_timeout_time = 0 generate
u_reg : entity work.dp_xonoff_reg
- generic map(
- g_default_value => g_default_value
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
gen_with_timeout : if g_timeout_time > 0 generate
u_reg : entity work.dp_xonoff_reg_timeout
- generic map(
- g_default_value => g_default_value,
- g_mm_timeout => g_timeout_time,
- g_sim => g_sim
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- st_rst => dp_rst,
- st_clk => dp_clk,
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => reg_mosi_arr(i),
- sla_out => reg_miso_arr(i),
-
- -- MM registers in dp_clk domain
- -- . control
- xonoff_reg => xonoff_reg(i downto i)
- );
+ generic map(
+ g_default_value => g_default_value,
+ g_mm_timeout => g_timeout_time,
+ g_sim => g_sim
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => reg_mosi_arr(i),
+ sla_out => reg_miso_arr(i),
+
+ -- MM registers in dp_clk domain
+ -- . control
+ xonoff_reg => xonoff_reg(i downto i)
+ );
end generate;
end generate;
@@ -138,20 +139,19 @@ begin
src_in_arr_i(i).xon <= src_in_arr(i).xon and xonoff_reg_i(i);
u_dp_xonoff : entity work.dp_xonoff
- generic map (
- g_bypass => g_bypass
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
+ generic map (
+ g_bypass => g_bypass
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
- in_siso => snk_out_arr(i),
- in_sosi => snk_in_arr(i),
- out_siso => src_in_arr_i(i),
- out_sosi => src_out_arr(i),
+ in_siso => snk_out_arr(i),
+ in_sosi => snk_in_arr(i),
+ out_siso => src_in_arr_i(i),
+ out_sosi => src_out_arr(i),
- force_xoff => force_xoff_arr(i)
- );
+ force_xoff => force_xoff_arr(i)
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
index bf481437ec77e990024c18bfb14bcf12a04f5b5c..f46956c2166b3392f83b4dbd9392b21a5996231c 100644
--- a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
@@ -21,7 +21,7 @@
-------------------------------------------------------------------------------
library IEEE;
-use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_1164.all;
-- Purpose:
-- Model a transceiver link.
@@ -59,5 +59,4 @@ begin
no_valid : if g_valid_support = false generate
out_val <= '1';
end generate;
-
end beh;
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
index 2df830e9506cd7a143f3bc6129cd843ca2b1edd7..d9d364c8fe1554d642dedb6c31a005cb2f7ba651 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Like dp_sosi_recorder.vhd, but records an array to a file.
@@ -75,6 +75,7 @@ architecture beh of dp_sosi_arr_recorder is
file record_file : TEXT;
begin
gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
+
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
begin
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
index 4fa5cf10e3490970fbfaea866d6668bc5c5837ea..6b8ba54733ae418426d5ee2cba60ee1170662ba2 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Record the DP record fields to a file for later playback by
@@ -91,6 +91,7 @@ architecture beh of dp_sosi_recorder is
file record_file : TEXT;
begin
gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
+
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
begin
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index 90c09b5f2448bf0e3d3462be865e6cb8b8766fa3..45433a298004e2965549121360989e6f4bc9f2df 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -36,13 +36,13 @@
--
library IEEE, common_lib, work, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_field_pkg.all;
-use technology_lib.technology_select_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use technology_lib.technology_select_pkg.all;
entity dp_statistics is
generic (
@@ -51,7 +51,7 @@ entity dp_statistics is
g_check_nof_valid : boolean := false; -- True enables valid count checking at dp_done. Reports Failure in case of mismatch.
g_check_nof_valid_ref : natural := 0; -- Reference (= expected) valid count
g_dp_word_w : natural := 32 -- Used to calculate data rate
- );
+ );
port (
dp_clk : in std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
index 2591a2fa72489cc5919f39008c3c547f7a99e185..fcd7376facde1b31a88a7af0aed3f730b5cc38c8 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use std.textio.all;
-use IEEE.std_logic_textio.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use std.textio.all;
+ use IEEE.std_logic_textio.all;
+ use common_lib.common_str_pkg.all;
-- Purpose:
-- . Play back a stream recorded by dp_stream_recorder.
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
index fe65542bf2fbd85107eb3668b1d835aa1055b805..213d090bccf7d1650e19f1215b317a04a61d9b21 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
@@ -21,10 +21,10 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
-- Purpose:
-- . Combine dp_stream_recorder and dp_stream_player.
@@ -42,7 +42,7 @@ entity dp_stream_rec_play is
g_rec_not_play : boolean := true;
g_rec_play_file : string := "dp_stream_recorder.rec";
g_record_invalid : boolean := true
- );
+ );
port (
dp_clk : in std_logic;
snk_in : in t_dp_sosi;
@@ -61,26 +61,25 @@ begin
gen_dp_sosi_recorder : if g_sim = true and g_rec_not_play = true generate
u_dp_sosi_recorder : entity work.dp_sosi_recorder
- generic map (
- g_record_file => g_rec_play_file,
- g_record_invalid => g_record_invalid
- )
- port map (
- dp_clk => dp_clk,
- snk_in => snk_in
- );
+ generic map (
+ g_record_file => g_rec_play_file,
+ g_record_invalid => g_record_invalid
+ )
+ port map (
+ dp_clk => dp_clk,
+ snk_in => snk_in
+ );
end generate;
gen_dp_stream_player : if g_sim = true and g_pass_through = false and g_rec_not_play = false generate
u_dp_stream_player : entity work.dp_stream_player
- generic map (
- g_playback_file => g_rec_play_file
- )
- port map (
- dp_clk => dp_clk,
- src_in => src_in,
- src_out => src_out
- );
+ generic map (
+ g_playback_file => g_rec_play_file
+ )
+ port map (
+ dp_clk => dp_clk,
+ src_in => src_in,
+ src_out => src_out
+ );
end generate;
-
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index 52c549b540b3532ca22255dfdec2bf6439863af6..78c49049cb340bc64f312bf40077dc93fab7864c 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_stimuli is
generic (
@@ -103,7 +103,7 @@ begin
stimuli_en <= '1' when g_flow_control = e_active else
random(random'high) when g_flow_control = e_random else
- pulse when g_flow_control = e_pulse;
+ pulse when g_flow_control = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -150,12 +150,12 @@ begin
-- Send packet
if g_use_complex = false then
proc_dp_gen_block_data(g_in_dat_w, TO_UINT(v_sosi.data),
- g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
- clk, stimuli_en, src_in, i_src_out);
+ g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
+ clk, stimuli_en, src_in, i_src_out);
else
proc_dp_gen_block_complex(g_in_dat_w, TO_UINT(v_sosi.re), TO_UINT(v_sosi.im),
- g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
- clk, stimuli_en, src_in, i_src_out);
+ g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn,
+ clk, stimuli_en, src_in, i_src_out);
end if;
-- Insert optional gap between the packets
proc_common_wait_some_cycles(clk, g_pkt_gap);
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index df8c655e04b253b189951166fecab8e7dd6aaeaf..1d8fc4ef80f849f310ada796cb63f4db30bfb0b8 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -39,13 +39,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity dp_stream_verify is
generic (
@@ -122,7 +122,7 @@ begin
i_snk_out.ready <= '1' when g_flow_control = e_active else
random(random'high) when g_flow_control = e_random else
- pulse when g_flow_control = e_pulse;
+ pulse when g_flow_control = e_pulse;
------------------------------------------------------------------------------
-- DATA VERIFICATION
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
index a66fd6e3029ac11a1f05c4d16b57d111bb609fba..ea94dd52a0218925a32be577b86cd41f8a4e6c76 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
@@ -45,13 +45,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb2_dp_demux is
generic (
@@ -128,11 +128,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -192,55 +192,55 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => g_mode_demux,
- g_nof_output => g_nof_streams,
- g_remove_channel_lo => g_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
+ generic map (
+ g_mode => g_mode_demux,
+ g_nof_output => g_nof_streams,
+ g_remove_channel_lo => g_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
+ );
------------------------------------------------------------------------------
-- DUT dp_mux
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_mode => g_mode_mux,
- g_nof_input => g_nof_streams,
- g_append_channel_lo => g_use_channel_lo,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => g_in_channel,
- -- ST sinks
- snk_out_arr => demux_siso_arr,
- snk_in_arr => demux_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_mode => g_mode_mux,
+ g_nof_input => g_nof_streams,
+ g_append_channel_lo => g_use_channel_lo,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_streams), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_streams) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => g_in_channel,
+ -- ST sinks
+ snk_out_arr => demux_siso_arr,
+ snk_in_arr => demux_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index de5f5139e019b4afd37b3280ca0e1788e993a306..d590f42e34e457caad3a347a3040e2c0eaa5496e 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -50,13 +50,13 @@
-- . Observe out_* signals in Wave Window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb2_dp_mux is
generic (
@@ -180,11 +180,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
out_siso_2arr <= (others => (others => out_siso));
@@ -194,7 +194,9 @@ begin
-- Generate data path input data
gen_type : for I in 0 to c_nof_type-1 generate
+
gen_input : for J in 0 to c_nof_input - 1 generate
+
p_stimuli : process
constant cK : natural := I * c_nof_input + J;
variable v_data_init : natural;
@@ -227,6 +229,7 @@ begin
prev_count_eop <= count_eop when rising_edge(clk);
gen_verify : for I in 0 to c_nof_type-1 generate
+
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
@@ -250,60 +253,60 @@ begin
-- Input level multiplexing
gen_mux : for I in 0 to c_nof_type-1 generate
u_input_mux : entity dp_lib.dp_mux
+ generic map (
+ -- MUX
+ g_mode => g_mode_mux,
+ g_nof_input => c_nof_input,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => g_mux_use_fifo,
+ g_bsn_w => c_data_w,
+ g_data_w => c_data_w,
+ g_use_bsn => c_use_bsn,
+ g_use_sync => c_use_sync,
+ g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_2arr(I),
+ snk_in_arr => in_sosi_2arr(I),
+ -- ST source
+ src_in => mux_siso_arr(I),
+ src_out => mux_sosi_arr(I)
+ );
+ end generate;
+
+ -- Second level multiplexing
+ u_type_mux : entity dp_lib.dp_mux
generic map (
-- MUX
g_mode => g_mode_mux,
- g_nof_input => c_nof_input,
+ g_nof_input => c_nof_type,
g_append_channel_lo => c_use_channel_lo,
-- Input FIFO
g_use_fifo => g_mux_use_fifo,
g_bsn_w => c_data_w,
g_data_w => c_data_w,
+ g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
+ g_use_in_channel => g_mux_use_fifo,
g_use_bsn => c_use_bsn,
g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_input), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_input) -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
)
port map (
rst => rst,
clk => clk,
-- ST sinks
- snk_out_arr => in_siso_2arr(I),
- snk_in_arr => in_sosi_2arr(I),
+ snk_out_arr => mux_siso_arr,
+ snk_in_arr => mux_sosi_arr,
-- ST source
- src_in => mux_siso_arr(I),
- src_out => mux_sosi_arr(I)
+ src_in => mux_siso,
+ src_out => mux_sosi
);
- end generate;
-
- -- Second level multiplexing
- u_type_mux : entity dp_lib.dp_mux
- generic map (
- -- MUX
- g_mode => g_mode_mux,
- g_nof_input => c_nof_type,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => g_mux_use_fifo,
- g_bsn_w => c_data_w,
- g_data_w => c_data_w,
- g_in_channel_w => c_channel_input_w, -- pass channel due to u_input_mux
- g_use_in_channel => g_mux_use_fifo,
- g_use_bsn => c_use_bsn,
- g_use_sync => c_use_sync,
- g_fifo_size => array_init( 1024, c_nof_type), -- must match g_nof_input, even when g_use_fifo=FALSE
- g_fifo_fill => array_init(g_mux_fifo_fill, c_nof_type) -- must match g_nof_input, even when g_use_fifo=FALSE
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => mux_siso_arr,
- snk_in_arr => mux_sosi_arr,
- -- ST source
- src_in => mux_siso,
- src_out => mux_sosi
- );
-- Map to slv to ease monitoring in wave window
mux_data <= mux_sosi.data(c_data_w - 1 downto 0);
@@ -319,28 +322,9 @@ begin
------------------------------------------------------------------------------
u_type_demux: entity dp_lib.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => c_nof_type,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => g_combined_demux
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso,
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso_arr,
- src_out_arr => demux_sosi_arr
- );
-
- gen_demux : for I in 0 to c_nof_type-1 generate
- u_output_demux : entity dp_lib.dp_demux
generic map (
g_mode => c_mode_demux,
- g_nof_output => c_nof_input,
+ g_nof_output => c_nof_type,
g_remove_channel_lo => c_use_channel_lo,
g_combined => g_combined_demux
)
@@ -348,13 +332,32 @@ begin
rst => rst,
clk => clk,
-- ST sinks
- snk_out => demux_siso_arr(I),
- snk_in => demux_sosi_arr(I),
+ snk_out => mux_siso,
+ snk_in => mux_sosi,
-- ST source
- src_in_arr => out_siso_2arr(I),
- src_out_arr => out_sosi_2arr(I)
+ src_in_arr => demux_siso_arr,
+ src_out_arr => demux_sosi_arr
);
+ gen_demux : for I in 0 to c_nof_type-1 generate
+ u_output_demux : entity dp_lib.dp_demux
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => c_nof_input,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => g_combined_demux
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => demux_siso_arr(I),
+ snk_in => demux_sosi_arr(I),
+ -- ST source
+ src_in_arr => out_siso_2arr(I),
+ src_out_arr => out_sosi_2arr(I)
+ );
+
gen_output : for J in 0 to c_nof_input - 1 generate
out_data(I, J) <= out_sosi_2arr(I)(J).data(c_data_w - 1 downto 0);
out_bsn( I, J) <= out_sosi_2arr(I)(J).bsn(c_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index 47b21dc98e8f1775f5560ee234ef8ac435f5a843..ab4809dce6af09a0fdfab7b904bed587cb194b1d 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -36,13 +36,13 @@
-- . interrupted.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_demux is
generic (
@@ -119,11 +119,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
-- Some random stimuli for sel_ctrl
sel_ctrl <= TO_UINT(random_0) mod g_nof_outputs when rising_edge(clk) and unsigned(in_sosi.data(c_data_w - 1 downto 0)) mod 19 = 0 and in_sosi.valid = '1';
@@ -186,25 +186,25 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_mode => c_mode_demux,
- g_nof_output => g_nof_outputs,
- g_remove_channel_lo => c_use_channel_lo,
- g_combined => c_combined_demux,
- g_sel_ctrl_pkt => c_sel_ctrl_pkt
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_mode => c_mode_demux,
+ g_nof_output => g_nof_outputs,
+ g_remove_channel_lo => c_use_channel_lo,
+ g_combined => c_combined_demux,
+ g_sel_ctrl_pkt => c_sel_ctrl_pkt
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
-- Use same ready stimuli for all outputs to ease verification
out_siso_arr <= (others => out_siso);
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 535656ce91e41885071b00fdc6466233f4bf37f7..97f0c2463310f227f8671ba4f94185b920e16767 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -33,13 +33,13 @@
-- . The verify procedures check the correct output
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb3_dp_mux is
generic (
@@ -114,11 +114,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
-- Some random stimuli for sel_ctrl
sel_ctrl <= TO_UINT(random_0) mod g_nof_inputs when rising_edge(clk) and unsigned(in_sosi.data(c_data_w - 1 downto 0)) mod 19 = 0 and in_sosi.valid = '1';
@@ -189,26 +189,26 @@ begin
------------------------------------------------------------------------------
mux : entity work.dp_mux
- generic map (
- -- MUX
- g_mode => c_mode_mux,
- g_nof_input => g_nof_inputs,
- g_append_channel_lo => c_use_channel_lo,
- -- Input FIFO
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ -- MUX
+ g_mode => c_mode_mux,
+ g_nof_input => g_nof_inputs,
+ g_append_channel_lo => c_use_channel_lo,
+ -- Input FIFO
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_nof_inputs), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_nof_inputs) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index b8030bfb668188ed5d08feab8ba81c3d93ccd442..e9a66b638f790160293dcd08c9b8d05033eb2363 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -42,13 +42,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_from_mm is
generic (
@@ -63,7 +63,7 @@ architecture tb of tb_dp_block_from_mm is
constant c_ram_data_size : natural := g_nof_data * g_data_size * c_nof_blocks;
constant c_ram_adr_w : natural := ceil_log2(c_ram_data_size);
- constant c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
+ constant c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2 ** c_ram_adr_w, '0');
constant c_init : natural := 42; -- inital data counter value, should be > 0 for better test coverage.
@@ -180,6 +180,7 @@ begin
ram_prev_rd_val <= ram_rd_val when rising_edge(clk);
rd_data <= TO_UINT(ram_rd_dat);
+
p_verify_read_ram_data: process
begin
rd_nxt_data <= c_init;
@@ -203,70 +204,70 @@ begin
------------------------------------------------------------------------------
-- RAM with test data
u_ram_rd: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => ram_wr_en,
- wr_adr => ram_wr_adr,
- wr_dat => ram_wr_dat,
- rd_en => rd_mosi.rd,
- rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
- rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
- rd_val => rd_miso.rdval
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => ram_wr_en,
+ wr_adr => ram_wr_adr,
+ wr_dat => ram_wr_dat,
+ rd_en => rd_mosi.rd,
+ rd_adr => rd_mosi.address(c_ram.adr_w - 1 downto 0),
+ rd_dat => rd_miso.rddata(c_ram.dat_w - 1 downto 0),
+ rd_val => rd_miso.rdval
+ );
-- DUT, dp_block_from_mm
u_dp_block_from_mm: entity work.dp_block_from_mm
- generic map (
- g_user_size => g_data_size,
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_pulse => start_pulse,
- start_address => start_address,
- mm_done => block_done,
- mm_mosi => rd_mosi,
- mm_miso => rd_miso,
- out_sosi => blk_sosi,
- out_siso => blk_siso
- );
+ generic map (
+ g_user_size => g_data_size,
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_pulse => start_pulse,
+ start_address => start_address,
+ mm_done => block_done,
+ mm_mosi => rd_mosi,
+ mm_miso => rd_miso,
+ out_sosi => blk_sosi,
+ out_siso => blk_siso
+ );
-- DUT, dp_block_to_mm
u_dp_block_to_mm: entity work.dp_block_to_mm
- generic map (
- g_data_size => g_data_size,
- g_step_size => g_step_size,
- g_nof_data => g_nof_data
- )
- port map (
- rst => rst,
- clk => clk,
- start_address => start_address_dly,
- mm_mosi => wr_mosi,
- in_sosi => blk_sosi
- );
+ generic map (
+ g_data_size => g_data_size,
+ g_step_size => g_step_size,
+ g_nof_data => g_nof_data
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_address => start_address_dly,
+ mm_mosi => wr_mosi,
+ in_sosi => blk_sosi
+ );
-- RAM with transferred data
u_ram_wr: entity common_lib.common_ram_r_w
- generic map (
- g_ram => c_ram
- )
- port map (
- rst => rst,
- clk => clk,
- wr_en => wr_mosi.wr,
- wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
- wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
- rd_en => ram_rd_en,
- rd_adr => ram_rd_adr,
- rd_dat => ram_rd_dat,
- rd_val => ram_rd_val
- );
+ generic map (
+ g_ram => c_ram
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_en => wr_mosi.wr,
+ wr_adr => wr_mosi.address(c_ram.adr_w - 1 downto 0),
+ wr_dat => wr_mosi.wrdata(c_ram.dat_w - 1 downto 0),
+ rd_en => ram_rd_en,
+ rd_adr => ram_rd_adr,
+ rd_dat => ram_rd_dat,
+ rd_val => ram_rd_val
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index 0e4fc37681d2d540ac123e6169f513843cc75464..bdc26d6c40baaba2c7b9bc33c993c414765bb877 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen is
generic (
@@ -95,7 +95,7 @@ begin
ready <= '1' when g_out_ready = e_active else
random(random'high) when g_out_ready = e_random else
- pulse when g_out_ready = e_pulse;
+ pulse when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- STIMULI
@@ -177,26 +177,26 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen
- generic map (
- g_use_src_in => g_use_src_in,
- g_nof_data => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_empty => 1,
- g_channel => 2,
- g_error => 3,
- g_bsn => c_bsn_init,
- g_preserve_sync => false,
- g_preserve_bsn => false
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => ref_sosi,
- -- Streaming source
- src_in => out_siso,
- src_out => out_sosi,
- -- MM control
- en => enable
- );
+ generic map (
+ g_use_src_in => g_use_src_in,
+ g_nof_data => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_empty => 1,
+ g_channel => 2,
+ g_error => 3,
+ g_bsn => c_bsn_init,
+ g_preserve_sync => false,
+ g_preserve_bsn => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => ref_sosi,
+ -- Streaming source
+ src_in => out_siso,
+ src_out => out_sosi,
+ -- MM control
+ en => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
index 52b11dd5ce321c0ea9cc66a9cb3fbaa03a870c2b..2f6e5d699c6b2fdea69a42bfe9d334e98420fc9a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
@@ -28,13 +28,13 @@
-- Observe out_sosi in wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_block_gen_valid_arr is
generic (
@@ -135,49 +135,49 @@ begin
-- input data
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_flow_control => g_flow_control, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => g_nof_blk_per_sync,
- g_sync_offset => c_sync_offset,
- g_data_init => 0,
- g_bsn_init => TO_DP_BSN(c_bsn_init),
- g_err_init => c_err_init,
- g_err_incr => 0,
- g_channel_init => c_channel_init,
- g_channel_incr => 0,
- -- specific
- g_in_dat_w => 32,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_nof_data_per_block,
- g_pkt_gap => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
- tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_flow_control => g_flow_control, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => g_nof_blk_per_sync,
+ g_sync_offset => c_sync_offset,
+ g_data_init => 0,
+ g_bsn_init => TO_DP_BSN(c_bsn_init),
+ g_err_init => c_err_init,
+ g_err_incr => 0,
+ g_channel_init => c_channel_init,
+ g_channel_incr => 0,
+ -- specific
+ g_in_dat_w => 32,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_nof_data_per_block,
+ g_pkt_gap => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ last_snk_in => OPEN, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => OPEN, -- trigger verify to verify the last_snk_in
+ tb_end => tb_input_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Use dp_pipeline to model the latency introduced by upstream DSP components
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => stimuli_sosi,
- -- ST source
- src_out => dsp_sosi
- );
+ generic map (
+ g_pipeline => c_dsp_latency -- 0 for wires, > 0 for registers,
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_out => dsp_sosi
+ );
p_in_sosi : process(dsp_sosi, stimuli_sosi)
begin
@@ -265,23 +265,23 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_block_gen_valid_arr
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_data_per_block => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_check_input_sync => g_check_input_sync,
- g_nof_pages_bsn => g_nof_pages_bsn,
- g_restore_global_bsn => g_restore_global_bsn
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => in_sosi,
- snk_in_arr => in_sosi_arr,
- -- Streaming source
- src_out_arr => out_sosi_arr,
- -- MM control
- enable => enable
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_data_per_block => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_check_input_sync => g_check_input_sync,
+ g_nof_pages_bsn => g_nof_pages_bsn,
+ g_restore_global_bsn => g_restore_global_bsn
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => in_sosi,
+ snk_in_arr => in_sosi_arr,
+ -- Streaming source
+ src_out_arr => out_sosi_arr,
+ -- MM control
+ enable => enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 91d7db77387553a526cad2717875624b73b592fd..3bb29ac41dee54ba57b52b6b7b82e5230b2e27dd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -42,14 +42,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape is
generic (
@@ -98,83 +98,83 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_input_nof_blk_per_sync,
- g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_input_nof_blk_per_sync,
+ g_nof_repeat => c_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
- g_pipeline_src_out => g_pipeline,
- g_pipeline_src_in => 0
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso,
- src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_reshape_nof_data_per_blk,
+ g_pipeline_src_out => g_pipeline,
+ g_pipeline_src_in => 0
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso,
+ src_index_arr => reshape_index_arr -- [1] sop index, [0] valid index
+ );
u_reshape_back : entity work.dp_block_reshape
- generic map (
- g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
- g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
- g_pipeline_src_out => 0,
- g_pipeline_src_in => g_pipeline
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso,
- src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
- );
+ generic map (
+ g_input_nof_data_per_sync => c_input_nof_data_per_sync, -- nof data per input sync interval, used only for sop_index
+ g_reshape_nof_data_per_blk => c_input_nof_data_per_blk,
+ g_pipeline_src_out => 0,
+ g_pipeline_src_in => g_pipeline
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso,
+ src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline * 2
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_siso,
- src_out => pipeline_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline * 2
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_siso,
+ src_out => pipeline_sosi
+ );
p_verify : process(clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index d03c07a6ad4d70297f78a745c37894c86b227ce5..0460b585b64cb28ab3be50f7bba8770f70b0397b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -38,14 +38,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_reshape_sync is
generic (
@@ -100,98 +100,98 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_input_nof_blk_per_sync,
- g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => g_input_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_input_nof_blk_per_sync,
+ g_nof_repeat => g_input_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => g_input_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_reshape_dut : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => stimuli_sosi,
- snk_out => stimuli_siso,
-
- src_out => reshape_sosi,
- src_in => reshape_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_reshape_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_reshape_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => stimuli_sosi,
+ snk_out => stimuli_siso,
+
+ src_out => reshape_sosi,
+ src_in => reshape_siso
+ );
u_reshape_back : entity work.dp_block_reshape_sync
- generic map (
- g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
- g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
- g_reshape_bsn => g_reshape_bsn,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in => reshape_sosi,
- snk_out => reshape_siso,
-
- src_out => verify_sosi,
- src_in => verify_siso
- );
+ generic map (
+ g_reshape_nof_data_per_blk => g_input_nof_data_per_blk,
+ g_reshape_nof_blk_per_sync => g_input_nof_blk_per_sync,
+ g_reshape_bsn => g_reshape_bsn,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in => reshape_sosi,
+ snk_out => reshape_siso,
+
+ src_out => verify_sosi,
+ src_in => verify_siso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline_dut : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_dut_siso,
- src_out => pipeline_dut_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline -- = c_pipeline in u_reshape_dut
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_dut_siso,
+ src_out => pipeline_dut_sosi
+ );
u_pipeline_total : entity work.dp_pipeline
- generic map (
- g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => pipeline_total_siso,
- src_out => pipeline_total_sosi
- );
+ generic map (
+ g_pipeline => c_pipeline * 2 -- = c_pipeline in u_reshape_dut + c_pipeline in u_reshape_back
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => pipeline_total_siso,
+ src_out => pipeline_total_sosi
+ );
prev_reshape_sosi <= reshape_sosi when rising_edge(clk);
prev_verify_sosi <= verify_sosi when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
index 1162980ee84071603c8a4136ccc6a829e737495c..2a9578fb9a5b47981725c5209dcaef7b0c45769b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_select is
generic (
@@ -93,75 +93,75 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => c_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => c_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_select : entity work.dp_block_select
- generic map (
- g_pipeline => g_dut_pipeline,
- g_nof_blocks_per_sync => g_nof_blocks_per_sync,
- g_index_lo => g_index_lo,
- g_index_hi => g_index_hi
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- index_lo => g_index_lo,
- index_hi => g_index_hi,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline,
+ g_nof_blocks_per_sync => g_nof_blocks_per_sync,
+ g_index_lo => g_index_lo,
+ g_index_hi => g_index_hi
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ index_lo => g_index_lo,
+ index_hi => g_index_hi,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => g_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_blk_cnt_reg <= stimuli_blk_cnt when rising_edge(clk);
stimuli_blk_cnt <= 0 when stimuli_sosi.sync = '1' else
stimuli_blk_cnt_reg + 1 when stimuli_sosi.sop = '1' else
- stimuli_blk_cnt_reg;
+ stimuli_blk_cnt_reg;
-- Only support g_dut_pipeline = 0 or 1
reference_blk_cnt <= stimuli_blk_cnt when g_dut_pipeline = 0 else
- stimuli_blk_cnt when rising_edge(clk);
+ stimuli_blk_cnt when rising_edge(clk);
-- Keep BSN at sync
sync_sosi <= reference_sosi when rising_edge(clk) and reference_sosi.sync = '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index 9ec17af29ee826356a73a2f2736357718c22de97..a78ee0cc5cd491722e2da4038ff6e1cce99f8db8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -31,16 +31,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_bsn_at_sync is
generic (
@@ -102,94 +102,94 @@ begin
-- Generate in_sosi with data frames
u_stimuli_in : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(0)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(0)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Generate bs_sosi with data frames
u_stimuli_bs : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => c_nof_blk,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_channel_init => 0,
- g_bsn_init => TO_DP_BSN(g_bsn_init)
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => bs_siso,
- src_out => bs_sosi,
-
- -- End of stimuli
- tb_end => open
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => c_nof_blk,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_channel_init => 0,
+ g_bsn_init => TO_DP_BSN(g_bsn_init)
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => bs_siso,
+ src_out => bs_sosi,
+
+ -- End of stimuli
+ tb_end => open
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_bsn_at_sync
- generic map (
- g_check_channel => c_check_channel
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- mm_rst => rst,
- mm_clk => mm_clk,
- -- ST sink
- in_sosi => stimuli_sosi,
- bs_sosi => bs_sosi,
- -- ST source
- out_sosi => verify_sosi,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_check_channel => c_check_channel
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ bs_sosi => bs_sosi,
+ -- ST source
+ out_sosi => verify_sosi,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
reference_cnt <= reference_cnt_reg + 1 when reference_sosi.sync = '1' else reference_cnt_reg;
p_verify : process(dp_clk)
- variable v_valid_blk : boolean := true;
+ variable v_valid_blk : boolean := true;
begin
if rising_edge(dp_clk) then
if reference_sosi.sop = '1' then -- Decide for each block if it should be valid.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
index d6ba2d4592ef9ae9e0a91591e71bab83ad553479..cdf345c5578a71140de43db1ab65fe44eb275796 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
@@ -30,16 +30,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_channel is
generic (
@@ -86,62 +86,62 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_channel
- generic map (
- g_mode => g_mode
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- -- ST sink
- in_sosi => stimuli_sosi,
- -- ST source
- out_keep_sosi => keep_sosi,
- out_remove_sosi => remove_sosi,
-
- remove_channel => TO_UVEC(g_remove_channel, 32)
- );
+ generic map (
+ g_mode => g_mode
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- ST sink
+ in_sosi => stimuli_sosi,
+ -- ST source
+ out_keep_sosi => keep_sosi,
+ out_remove_sosi => remove_sosi,
+
+ remove_channel => TO_UVEC(g_remove_channel, 32)
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
p_verify : process(dp_clk)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index fd24928a064a105a47c92b0df9334a648f853af9..2c9fd292966009447125dccce326a1d2722a3591 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -34,16 +34,16 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_err is
generic (
@@ -66,8 +66,8 @@ architecture tb of tb_dp_block_validate_err is
constant c_dut_pipeline : natural := g_nof_data_per_blk + 3;
constant c_nof_sync : natural := 5;
constant c_nof_blk : natural := g_nof_blocks_per_sync * (c_nof_sync - 1);
- constant c_nof_discarded : natural := c_nof_blk - ceil_div(c_nof_blk, 2**g_nof_err_counts);
- constant c_max_cnt : natural := 2**g_cnt_w - 1;
+ constant c_nof_discarded : natural := c_nof_blk - ceil_div(c_nof_blk, 2 ** g_nof_err_counts);
+ constant c_max_cnt : natural := 2 ** g_cnt_w - 1;
constant c_mm_addr_dp_clear : natural := g_nof_err_counts + 3;
constant c_mm_addr_dp_blk_cnt : natural := g_nof_err_counts + 1;
@@ -114,87 +114,87 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => g_gap_size,
- g_err_init => 0,
- g_err_incr => 1
- )
- port map (
- rst => stimuli_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => g_gap_size,
+ g_err_init => 0,
+ g_err_incr => 1
+ )
+ port map (
+ rst => stimuli_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_err
- generic map (
- g_cnt_w => g_cnt_w,
- g_blk_cnt_w => g_cnt_w,
- g_max_block_size => g_max_block_size,
- g_nof_err_counts => g_nof_err_counts,
- g_data_w => c_word_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_sync => true
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- ref_sync => stimuli_sosi.sync,
-
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_cnt_w => g_cnt_w,
+ g_blk_cnt_w => g_cnt_w,
+ g_max_block_size => g_max_block_size,
+ g_nof_err_counts => g_nof_err_counts,
+ g_data_w => c_word_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_sync => true
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ ref_sync => stimuli_sosi.sync,
+
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => dp_clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
reference_cnt_reg <= reference_cnt when rising_edge(dp_clk);
- reference_cnt <= 0 when reference_sosi.eop = '1' and ((reference_cnt_reg + 1) mod 2**g_nof_err_counts) = 0 else
+ reference_cnt <= 0 when reference_sosi.eop = '1' and ((reference_cnt_reg + 1) mod 2 ** g_nof_err_counts) = 0 else
reference_cnt_reg + 1 when reference_sosi.eop = '1' else
- reference_cnt_reg;
+ reference_cnt_reg;
p_verify : process(dp_clk)
begin
@@ -238,8 +238,8 @@ begin
rd_blk_cnt <= TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0));
assert c_exp_blk_cnt = TO_UINT(reg_miso.rddata(c_word_w - 1 downto 0)) report "Wrong total block count" severity ERROR;
for I in 0 to g_nof_err_counts - 1 loop
- v_X := 2**I * ((c_nof_blk - 1) / 2**(I + 1));
- v_Y := c_nof_blk - 2 * v_X - 2**I;
+ v_X := 2 ** I * ((c_nof_blk - 1) / 2 ** (I + 1));
+ v_Y := c_nof_blk - 2 * v_X - 2 ** I;
if v_Y < 0 then -- v_N = v_X + v_Y only holds for v_Y > 0.
v_N := v_X;
else
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 2ecc70415eef47ed08d8590555499cf4b2c6cf64..bd857ed109456a719ae8c3d9567325ac188da198 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -29,14 +29,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_block_validate_length is
generic (
@@ -56,7 +56,7 @@ architecture tb of tb_dp_block_validate_length is
constant c_dut_pipeline : natural := 1;
constant c_nof_sync : natural := 5;
constant c_gap_size : natural := 4;
- constant c_exp_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_UVEC(2**g_err_bi, c_dp_stream_error_w);
+ constant c_exp_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_UVEC(2 ** g_err_bi, c_dp_stream_error_w);
signal clk : std_logic := '1';
signal rst : std_logic := '1';
@@ -85,68 +85,68 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
- g_pkt_len => g_nof_data_per_blk,
- g_pkt_gap => c_gap_size,
- g_err_init => 0,
- g_err_incr => 0
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_siso,
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_nof_sync,
+ g_pkt_len => g_nof_data_per_blk,
+ g_pkt_gap => c_gap_size,
+ g_err_init => 0,
+ g_err_incr => 0
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_siso,
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_block_validate_length
- generic map (
- g_err_bi => g_err_bi,
- g_expected_length => g_expected_length
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => stimuli_siso,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => verify_siso,
- src_out => verify_sosi
- );
+ generic map (
+ g_err_bi => g_err_bi,
+ g_expected_length => g_expected_length
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => stimuli_siso,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => verify_siso,
+ src_out => verify_sosi
+ );
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
u_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => c_dut_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => OPEN,
- snk_in => stimuli_sosi,
- -- ST source
- src_in => reference_siso,
- src_out => reference_sosi
- );
+ generic map (
+ g_pipeline => c_dut_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => OPEN,
+ snk_in => stimuli_sosi,
+ -- ST source
+ src_in => reference_siso,
+ src_out => reference_sosi
+ );
stimuli_cnt_reg <= stimuli_cnt when rising_edge(clk);
stimuli_cnt <= 0 when stimuli_sosi.sop = '1' else
stimuli_cnt_reg + 1 when stimuli_sosi.valid = '1' else
- stimuli_cnt_reg;
+ stimuli_cnt_reg;
reference_cnt <= stimuli_cnt when rising_edge(clk);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 5b799b6b68ef81521aa853c858c3d117555e1925..9917a12f1c6c77ccf92a317311dd973e4d641956 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -33,13 +33,13 @@
-- automatically.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align is
generic (
@@ -156,7 +156,7 @@ begin
out_siso.xon <= '1';
out_siso.ready <= '1' when g_out_ready = e_active else
random(random'high) when g_out_ready = e_random else
- pulse when g_out_ready = e_pulse;
+ pulse when g_out_ready = e_pulse;
out_siso_arr <= (others => out_siso);
@@ -166,6 +166,7 @@ begin
-- Generate data path input data
gen_input : for I in g_nof_input - 1 downto 0 generate
+
p_stimuli : process
variable v_sync : std_logic := '0';
variable v_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := c_bsn_init;
@@ -285,7 +286,7 @@ begin
verify_dis_arr <= (others => '0');
proc_common_wait_some_cycles(clk, 1000);
--- verify_dis_arr <= (OTHERS=>'1');
+ -- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
@@ -294,8 +295,8 @@ begin
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
--- proc_common_wait_some_cycles(clk, 100);
--- verify_dis_arr <= (OTHERS=>'0');
+ -- proc_common_wait_some_cycles(clk, 100);
+ -- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (others => '1');
@@ -359,7 +360,7 @@ begin
gen_verify : for I in g_nof_input - 1 downto 0 generate
-- Verification logistics
verify_en_arr(I) <= '1' when rising_edge(clk) and verify_dis_arr(I) = '0' and in_en_arr(I) = '1' and out_sosi_arr(I).sop = '1' else
- '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
+ '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
-- Ease in_siso_arr monitoring
in_ready(I) <= in_siso_arr(I).ready;
@@ -405,25 +406,25 @@ begin
------------------------------------------------------------------------------
u_bsn_align : entity work.dp_bsn_align
- generic map (
- g_block_size => g_block_size,
- g_nof_input => g_nof_input,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr,
- -- MM
- in_en_evt => in_en_event,
- in_en_arr => in_en_arr
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+ -- MM
+ in_en_evt => in_en_event,
+ in_en_arr => in_en_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
index c6db289f9ed18f783f7200c0011a250f934233b7..b50089e0bfae7836e8b18043bf4c992d305c9088 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
@@ -72,14 +72,14 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_align_v2 is
generic (
@@ -103,7 +103,7 @@ entity tb_dp_bsn_align_v2 is
-- TB
g_tb_diff_delay : integer := 0; -- 0 = aligned inputs, -1 = max input delay for no loss,
- -- >~ g_bsn_latency_max * g_block_period will give loss
+ -- >~ g_bsn_latency_max * g_block_period will give loss
g_tb_nof_restart : natural := 2; -- number of times to restart the input stimuli
g_tb_nof_blocks : natural := 20 -- number of input blocks per restart
);
@@ -270,6 +270,7 @@ begin
-- Generate data path input data
gen_stimuli : for I in g_nof_streams - 1 downto 0 generate
+
p_stimuli : process
variable v_sync : std_logic := '0';
variable v_bsn : natural;
@@ -436,6 +437,7 @@ begin
exp_bsn_lost_arr(c_lost_bsn_stream_id) <= '1' when TO_UINT(out_sosi_arr_exp(c_lost_bsn_stream_id).bsn) = g_lost_bsn_id else '0';
gen_verify_streams : for I in g_nof_streams - 1 downto 0 generate
+
p_verify_stream : process(clk)
begin
if rising_edge(clk) then
@@ -446,45 +448,45 @@ begin
dbg_verify_no_lost_flag_arr(I) <= '0';
dbg_verify_lost_flag_arr(I) <= '0';
if verify_sosi_en_arr(I) = '1' and out_sosi_arr_exp(I).valid = '1' then
- -- Verify sosi control fields
- dbg_verify_sosi_control_arr(I) <= '1';
- assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync report "Wrong sync for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop report "Wrong sop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop report "Wrong eop for output " & int_to_str(I) severity ERROR;
- assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid report "Wrong valid for output " & int_to_str(I) severity ERROR;
-
- -- Verify data field
- if stream_en_arr(I) = '1' and stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
- -- verify passed on data
- dbg_verify_passed_on_data_arr(I) <= '1';
- assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data report "Wrong data for output stream " & int_to_str(I) & " : "
- & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
- & int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) severity ERROR;
- else
- -- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id
- dbg_verify_replaced_data_arr(I) <= '1';
- assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value report "Wrong replacement data for output stream " & int_to_str(I) & " : "
- & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
- & int_to_str(g_data_replacement_value) severity ERROR;
- end if;
-
- -- Verify sop info fields
- if out_sosi_arr_exp(I).sop = '1' then
- -- bsn field
- dbg_verify_bsn_arr(I) <= '1';
- assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn report "Wrong bsn for output " & int_to_str(I) severity ERROR;
-
- -- channel field with lost flag bit 0
- if stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
- -- verify no lost stream
- dbg_verify_no_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0) report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) severity ERROR;
- else
- -- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id
- dbg_verify_lost_flag_arr(I) <= '1';
- assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1) report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) severity ERROR;
- end if;
- end if;
+ -- Verify sosi control fields
+ dbg_verify_sosi_control_arr(I) <= '1';
+ assert out_sosi_arr(I).sync = out_sosi_arr_exp(I).sync report "Wrong sync for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).sop = out_sosi_arr_exp(I).sop report "Wrong sop for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).eop = out_sosi_arr_exp(I).eop report "Wrong eop for output " & int_to_str(I) severity ERROR;
+ assert out_sosi_arr(I).valid = out_sosi_arr_exp(I).valid report "Wrong valid for output " & int_to_str(I) severity ERROR;
+
+ -- Verify data field
+ if stream_en_arr(I) = '1' and stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
+ -- verify passed on data
+ dbg_verify_passed_on_data_arr(I) <= '1';
+ assert out_sosi_arr(I).data = out_sosi_arr_exp(I).data report "Wrong data for output stream " & int_to_str(I) & " : "
+ & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
+ & int_to_str(TO_UINT(out_sosi_arr_exp(I).data)) severity ERROR;
+ else
+ -- verify lost data stream at g_disable_stream_id or g_lost_stream_id or g_lost_bsn_id
+ dbg_verify_replaced_data_arr(I) <= '1';
+ assert TO_UINT(out_sosi_arr(I).data) = g_data_replacement_value report "Wrong replacement data for output stream " & int_to_str(I) & " : "
+ & int_to_str(TO_UINT(out_sosi_arr(I).data)) & " /= "
+ & int_to_str(g_data_replacement_value) severity ERROR;
+ end if;
+
+ -- Verify sop info fields
+ if out_sosi_arr_exp(I).sop = '1' then
+ -- bsn field
+ dbg_verify_bsn_arr(I) <= '1';
+ assert out_sosi_arr(I).bsn = out_sosi_arr_exp(I).bsn report "Wrong bsn for output " & int_to_str(I) severity ERROR;
+
+ -- channel field with lost flag bit 0
+ if stream_lost_arr(I) = '0' and exp_bsn_lost_arr(I) = '0' then
+ -- verify no lost stream
+ dbg_verify_no_lost_flag_arr(I) <= '1';
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(0) report "Wrong lost flag bit in channel /= 0 for output " & int_to_str(I) severity ERROR;
+ else
+ -- verify lost stream g_lost_stream_id or lost block g_lost_bsn_id
+ dbg_verify_lost_flag_arr(I) <= '1';
+ assert out_sosi_arr(I).channel = TO_DP_CHANNEL(1) report "Wrong lost flag bit channel /= 1 for output " & int_to_str(I) severity ERROR;
+ end if;
+ end if;
end if;
end if;
end process;
@@ -498,35 +500,35 @@ begin
dut_in_sosi_2arr(0) <= in_sosi_arr;
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => c_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- -- Control
- node_index => node_index_arr(0),
- stream_en_arr => stream_en_arr,
- -- Streaming input
- in_sosi_arr => dut_in_sosi_2arr(0),
- -- Output via local MM interface in dp_clk domain
- mm_copi => mm_copi,
- mm_cipo_arr => mm_cipo_arr,
- mm_sosi => mm_sosi,
-
- -- Output via streaming DP interface
- out_sosi_arr => dut_out_sosi_2arr(0)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => c_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ -- Control
+ node_index => node_index_arr(0),
+ stream_en_arr => stream_en_arr,
+ -- Streaming input
+ in_sosi_arr => dut_in_sosi_2arr(0),
+ -- Output via local MM interface in dp_clk domain
+ mm_copi => mm_copi,
+ mm_cipo_arr => mm_cipo_arr,
+ mm_sosi => mm_sosi,
+
+ -- Output via streaming DP interface
+ out_sosi_arr => dut_out_sosi_2arr(0)
+ );
-- Simulate series of DUT, when g_use_mm_output = FALSE and
-- g_nof_aligners_max > 1. Use same local in_sosi_arr(0) input for all BSN
@@ -550,30 +552,30 @@ begin
--
gen_bsn_align_chain : for I in 1 to c_nof_aligners_max - 1 generate
u_bsn_align : entity work.dp_bsn_align_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_bsn_latency_max => g_bsn_latency_max,
- g_nof_aligners_max => c_nof_aligners_max,
- g_block_size => g_block_size,
- g_bsn_w => g_bsn_w,
- g_data_w => g_data_w,
- g_data_replacement_value => g_data_replacement_value,
- g_use_mm_output => g_use_mm_output,
- g_pipeline_input => g_pipeline_input,
- g_pipeline_output => g_pipeline_output,
- g_rd_latency => g_rd_latency
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- -- Control
- node_index => node_index_arr(I),
- stream_en_arr => stream_en_arr,
- -- Streaming input
- in_sosi_arr => dut_in_sosi_2arr(I),
- -- Output via streaming DP interface
- out_sosi_arr => dut_out_sosi_2arr(I)
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_bsn_latency_max => g_bsn_latency_max,
+ g_nof_aligners_max => c_nof_aligners_max,
+ g_block_size => g_block_size,
+ g_bsn_w => g_bsn_w,
+ g_data_w => g_data_w,
+ g_data_replacement_value => g_data_replacement_value,
+ g_use_mm_output => g_use_mm_output,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_output => g_pipeline_output,
+ g_rd_latency => g_rd_latency
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ -- Control
+ node_index => node_index_arr(I),
+ stream_en_arr => stream_en_arr,
+ -- Streaming input
+ in_sosi_arr => dut_in_sosi_2arr(I),
+ -- Output via streaming DP interface
+ out_sosi_arr => dut_out_sosi_2arr(I)
+ );
-- Connect remote and local between DUTs in the chain of DUTs
p_connect : process(dut_out_sosi_2arr, in_sosi_arr)
@@ -602,26 +604,26 @@ begin
gen_mm_to_dp : for I in 0 to g_nof_streams - 1 generate
u_mm_to_dp: entity work.dp_block_from_mm
- generic map (
- g_user_size => 1,
- g_data_size => 1,
- g_step_size => 1,
- g_nof_data => g_block_size,
- g_word_w => g_data_w,
- g_mm_rd_latency => g_rd_latency,
- g_reverse_word_order => false
- )
- port map (
- rst => rst,
- clk => clk,
- start_pulse => mm_sosi.sop,
- start_address => 0,
- mm_done => mm_done_arr(I),
- mm_mosi => mm_copi_arr(I),
- mm_miso => mm_cipo_arr(I),
- out_sosi => mm_sosi_arr(I),
- out_siso => c_dp_siso_rdy
- );
+ generic map (
+ g_user_size => 1,
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => g_block_size,
+ g_word_w => g_data_w,
+ g_mm_rd_latency => g_rd_latency,
+ g_reverse_word_order => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ start_pulse => mm_sosi.sop,
+ start_address => 0,
+ mm_done => mm_done_arr(I),
+ mm_mosi => mm_copi_arr(I),
+ mm_miso => mm_cipo_arr(I),
+ out_sosi => mm_sosi_arr(I),
+ out_siso => c_dp_siso_rdy
+ );
end generate;
p_comb : process(r, mm_sosi, mm_sosi_arr)
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index 2003d4327fcff14a6b85e468cb94ad4f94db4e84..8f8a292d351356f9e7383c5ae110487e5fd7d1ad 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -28,13 +28,13 @@
-- . The verify procedures check the correct input and monitor results
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor is
generic (
@@ -123,7 +123,7 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
in_siso <= c_dp_siso_rdy;
@@ -305,34 +305,34 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor
- generic map (
- g_log_first_bsn => false,
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- sync_in => sync_in,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
-
- mon_bsn_first => mon_bsn_first,
- mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
- );
+ generic map (
+ g_log_first_bsn => false,
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ sync_in => sync_in,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+
+ mon_bsn_first => mon_bsn_first,
+ mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index 8f76b0058e0f43e23babe9cff785b82e7f463c94..c6cdf8b93d263c5cb98eb327741115bbf75f738c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -28,13 +28,13 @@
-- --------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_monitor_v2 is
generic (
@@ -126,7 +126,7 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
in_siso <= c_dp_siso_rdy;
@@ -305,31 +305,31 @@ begin
-- Tap the stream to the monitor
dut : entity work.dp_bsn_monitor_v2
- generic map (
- g_sync_timeout => c_sync_timeout
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- ST interface
- in_siso => out_siso,
- in_sosi => in_sosi,
- ref_sync => ref_sync,
-
- -- MM interface
- -- . control
- mon_evt => mon_evt,
- mon_sync => mon_sync,
- mon_sync_timeout => mon_sync_timeout,
- -- . siso
- mon_ready_stable => mon_ready_stable,
- mon_xon_stable => mon_xon_stable,
- -- . sosi
- mon_bsn_at_sync => mon_bsn_at_sync,
- mon_nof_sop => mon_nof_sop,
- mon_nof_err => mon_nof_err,
- mon_nof_valid => mon_nof_valid,
- mon_latency => mon_latency
- );
+ generic map (
+ g_sync_timeout => c_sync_timeout
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- ST interface
+ in_siso => out_siso,
+ in_sosi => in_sosi,
+ ref_sync => ref_sync,
+
+ -- MM interface
+ -- . control
+ mon_evt => mon_evt,
+ mon_sync => mon_sync,
+ mon_sync_timeout => mon_sync_timeout,
+ -- . siso
+ mon_ready_stable => mon_ready_stable,
+ mon_xon_stable => mon_xon_stable,
+ -- . sosi
+ mon_bsn_at_sync => mon_bsn_at_sync,
+ mon_nof_sop => mon_nof_sop,
+ mon_nof_err => mon_nof_err,
+ mon_nof_valid => mon_nof_valid,
+ mon_latency => mon_latency
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
index 77429b4b4f377149a3435a54dc6a1463df928a56..ff14aa970ab590c01d76269399de05daac140450 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
@@ -27,12 +27,12 @@
-- and then manually verify on/off in Wave window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source is
end tb_dp_bsn_source;
@@ -155,20 +155,20 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source
- generic map (
- g_block_size => c_block_size,
- g_nof_block_per_sync => c_sync_period,
- g_bsn_w => c_bsn_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- init_bsn => init_bsn,
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => c_sync_period,
+ g_bsn_w => c_bsn_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ init_bsn => init_bsn,
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index d8de93d6138f6fe1a4a6956b3721ea95596ed6c8..b71a6b5b2ed00f2a069b85bf7a4f4d3d3b80f81a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -43,12 +43,12 @@
-- . sync and bsn are verified automatically using the ref_grid
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_source_v2 is
generic (
@@ -259,16 +259,16 @@ begin
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync(0, -- start bsn of PPS grid and BSN grid is 0, see [1]
- g_pps_interval,
- g_block_size,
- clk,
- verify_en,
- bs_sosi.sync,
- bs_sosi.sop,
- bs_sosi.bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ g_pps_interval,
+ g_block_size,
+ clk,
+ verify_en,
+ bs_sosi.sync,
+ bs_sosi.sop,
+ bs_sosi.bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
-- Verify bs_sosi by comparing with exp_grid, this again verifies bs_sosi.sync, sop and bsn
p_verify_bs_sosi_grid : process(clk)
@@ -324,28 +324,28 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w,
- g_bsn_time_offset_w => c_bsn_time_offset_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => ref_grid.pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
-
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
-
- bsn_init => bsn_init,
- bsn_time_offset => bsn_time_offset,
-
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w,
+ g_bsn_time_offset_w => c_bsn_time_offset_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => ref_grid.pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+
+ dp_on_status => dp_on_status, -- = src_out.valid
+ bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
+ bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+
+ bsn_init => bsn_init,
+ bsn_time_offset => bsn_time_offset,
+
+ -- Streaming
+ src_out => bs_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 5a8bde3e8658d01b4f4fe76d577230b2c2f63738..6b119d3a8fbe41aebcd12df94012bacdd27ab212 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -69,13 +69,13 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_bsn_sync_scheduler is
generic (
@@ -190,14 +190,15 @@ architecture tb of tb_dp_bsn_sync_scheduler is
signal dbg_expected_bsn : natural := 0;
-- Local procedures
- procedure proc_output_enable(signal clk : in std_logic;
- signal cnt : in integer;
- signal sync : in std_logic;
- signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
- signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_enable(
+ signal clk : in std_logic;
+ signal cnt : in integer;
+ signal sync : in std_logic;
+ signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
proc_common_wait_until_hi_lo(clk, sync); -- (re)enable at begin of sync interval
stimuli_state <= e_en;
@@ -208,21 +209,23 @@ architecture tb of tb_dp_bsn_sync_scheduler is
ctrl_enable_evt <= '0';
end proc_output_enable;
- procedure proc_output_re_enable(signal clk : in std_logic;
- signal cnt : in integer;
- signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
- signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_re_enable(
+ signal clk : in std_logic;
+ signal cnt : in integer;
+ signal mon_input_bsn_at_sync : in std_logic_vector(c_bsn_w - 1 downto 0);
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_start_bsn : out std_logic_vector(c_bsn_w - 1 downto 0);
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
proc_output_enable(clk, cnt, in_sync, mon_input_bsn_at_sync, stimuli_state, ctrl_start_bsn, ctrl_enable, ctrl_enable_evt);
stimuli_state <= e_re;
end proc_output_re_enable;
- procedure proc_output_disable(signal stimuli_state : out t_stimuli_state_enum;
- signal ctrl_enable : out std_logic;
- signal ctrl_enable_evt : out std_logic) is
+ procedure proc_output_disable(
+ signal stimuli_state : out t_stimuli_state_enum;
+ signal ctrl_enable : out std_logic;
+ signal ctrl_enable_evt : out std_logic) is
begin
stimuli_state <= e_dis;
ctrl_enable <= '0';
@@ -313,26 +316,26 @@ begin
-- Generate data blocks with input sync
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_block_per_input_sync,
- g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_nof_repeat => c_sim_nof_blocks,
- g_pkt_len => g_block_size,
- g_pkt_gap => g_input_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => tb_end
- );
+ generic map (
+ g_sync_period => g_nof_block_per_input_sync,
+ g_err_init => 0,
+ g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_init => 0,
+ g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_nof_repeat => c_sim_nof_blocks,
+ g_pkt_len => g_block_size,
+ g_pkt_gap => g_input_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => tb_end
+ );
-- Input with option to loose data blocks
p_in_sosi : process(stimuli_sosi, in_lost)
@@ -519,16 +522,16 @@ begin
-- Verify that sync is on PPS and BSN grid as defined in [1].
proc_dp_verify_sync(TO_UINT(ctrl_start_bsn),
- ctrl_interval_size,
- g_block_size,
- clk,
- verify_sync,
- out_sosi.sync,
- out_sosi.sop,
- out_sosi.bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ ctrl_interval_size,
+ g_block_size,
+ clk,
+ verify_sync,
+ out_sosi.sync,
+ out_sosi.sop,
+ out_sosi.bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
dbg_out_sosi_sync <= out_sosi.sync;
dbg_out_sosi_sop <= out_sosi.sop;
@@ -551,9 +554,9 @@ begin
v_bsn_max := TO_UINT(mon_current_input_bsn) + c_output_nof_blocks_min + 1;
assert TO_UINT(mon_output_sync_bsn) >= v_bsn_min
- report "Wrong: mon_output_sync_bsn is behind (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " < " & int_to_str(v_bsn_min) & ")" severity ERROR;
+ report "Wrong: mon_output_sync_bsn is behind (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " < " & int_to_str(v_bsn_min) & ")" severity ERROR;
assert TO_UINT(mon_output_sync_bsn) <= v_bsn_max
- report "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")" severity ERROR;
+ report "Wrong: mon_output_sync_bsn is too far ahead (" & int_to_str(TO_UINT(mon_output_sync_bsn)) & " > " & int_to_str(v_bsn_max) & ")" severity ERROR;
--Debug report used to investigate v_bsn_min and v_bsn_max assert conditions
--REPORT int_to_str(TO_UINT(mon_output_sync_bsn)) & " : " & int_to_str(TO_UINT(mon_current_input_bsn)) SEVERITY NOTE;
@@ -567,30 +570,30 @@ begin
-----------------------------------------------------------------------------
dut : entity work.dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => c_bsn_w,
- g_block_size => g_block_size,
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_sync_bsn => mon_output_sync_bsn,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_start_interval => out_start_interval,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => c_bsn_w,
+ g_block_size => g_block_size,
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- M&C
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_sync_bsn => mon_output_sync_bsn,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_start_interval => out_start_interval,
+ out_enable => out_enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
index 9506ca762cb29cc620bc8fca7070245eaa168c8d..088dab377bc61871eed762153eef8286e9427776 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
@@ -31,14 +31,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_calculate_crc is
generic (
@@ -85,22 +85,22 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_nof_blk_per_sync,
- g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
- g_pkt_len => c_nof_data_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_nof_blk_per_sync,
+ g_nof_repeat => c_nof_blk_per_sync * c_nof_sync,
+ g_pkt_len => c_nof_data_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
-- Use same dat for every block to verify restart of CRC calculation
p_snk_in : process(stimuli_sosi)
@@ -113,17 +113,17 @@ begin
-- DUT
------------------------------------------------------------------------------
u_crc : entity work.dp_calculate_crc
- generic map (
- g_data_w => g_data_w,
- g_crc_w => g_crc_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => snk_in,
- blk_crc => blk_crc
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_crc_w => g_crc_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => snk_in,
+ blk_crc => blk_crc
+ );
------------------------------------------------------------------------------
-- Verifycation
@@ -135,11 +135,11 @@ begin
if rising_edge(clk) then
if new_crc = '1' then
--IF g_data_w = 28 AND g_crc_w = 28 AND c_nof_data_per_blk = 9 THEN
- if blk_crc = exp_crc_28 then
- report "OK CRC value." severity NOTE;
- else
- report "Wrong CRC value." severity ERROR;
- end if;
+ if blk_crc = exp_crc_28 then
+ report "OK CRC value." severity NOTE;
+ else
+ report "Wrong CRC value." severity ERROR;
+ end if;
--END IF;
end if;
end if;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index e4ceabe74ded544ff68ac1da6ed7d0e1ece038e7..362d018ed3c6f0633219eec04f18bb9d3e8efd52 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat is
generic (
@@ -148,18 +148,18 @@ begin
end process;
dut : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
-- Input data
in_data_0 <= in_sosi_arr(0).data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index aea02918e9685a84717f4ac60a9619278e7919e2..30f390f0f251e7d1dd7eaf5878c7391b5dabb4fd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -36,15 +36,15 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_concat_field_blk is
generic (
@@ -94,28 +94,28 @@ architecture tb of tb_dp_concat_field_blk is
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := (
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
-- From apertif_unb1_fn_beamformer_udp_offload.vhd:
-- Override ('1') only the Ethernet fields so we can use MM defaults there.
@@ -194,36 +194,36 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- -- specific
- g_in_dat_w => g_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_wait_last_evt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_wait_last_evt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -257,37 +257,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_data_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT offload Tx
@@ -297,23 +297,23 @@ begin
-- Use FIFO to mimic apertif_unb1_fn_beamformer_udp_offload.vhd, without FIFO dp_stream_stimuli
-- would handle the back pressure
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 64,
- g_use_sync => true,
- g_use_bsn => true,
- g_fifo_size => 1024
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN, -- stimuli_src_in
- snk_in => stimuli_src_out,
-
- src_in => dp_fifo_sc_src_in,
- src_out => dp_fifo_sc_src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_use_bsn => true,
+ g_fifo_size => 1024
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN, -- stimuli_src_in
+ snk_in => stimuli_src_out,
+
+ src_in => dp_fifo_sc_src_in,
+ src_out => dp_fifo_sc_src_out
+ );
dp_offload_tx_snk_in_arr(0) <= dp_fifo_sc_src_out;
dp_fifo_sc_src_in <= dp_offload_tx_snk_out_arr(0);
@@ -332,31 +332,31 @@ begin
tx_hdr_fields_in_arr(0)(field_hi(c_udp_offload_hdr_field_arr, "dp_bsn" ) downto field_lo(c_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(0).bsn(63 downto 0);
u_tx : entity work.dp_concat_field_blk
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => tx_offload_sosi_arr,
- src_in_arr => tx_offload_siso_arr,
-
- hdr_fields_in_arr => tx_hdr_fields_in_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => tx_offload_sosi_arr,
+ src_in_arr => tx_offload_siso_arr,
+
+ hdr_fields_in_arr => tx_hdr_fields_in_arr
+ );
------------------------------------------------------------------------------
-- Link
@@ -380,32 +380,32 @@ begin
------------------------------------------------------------------------------
u_rx : entity work.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => link_offload_sosi_arr,
- snk_out_arr => link_offload_siso_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => rx_hdr_fields_out_arr,
- hdr_fields_raw_arr => rx_hdr_fields_raw_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => link_offload_sosi_arr,
+ snk_out_arr => link_offload_siso_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => rx_hdr_fields_out_arr,
+ hdr_fields_raw_arr => rx_hdr_fields_raw_arr
+ );
p_restore_sync_bsn : process(dp_offload_rx_src_out_arr, rx_hdr_fields_out_arr)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 50c0401ffe35f78b823caac59d9754c36cfe1961..d08275a52ef752efa9204a8c51e064e0fcdfa607 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter is
generic (
@@ -124,11 +124,11 @@ begin
in_en <= '1' when g_flow_control_stimuli = e_active else
in_random(in_random'high) when g_flow_control_stimuli = e_random else
- in_pulse when g_flow_control_stimuli = e_pulse;
+ in_pulse when g_flow_control_stimuli = e_pulse;
out_ready <= '1' when g_flow_control_verify = e_active else
out_random(out_random'high) when g_flow_control_verify = e_random else
- out_pulse when g_flow_control_verify = e_pulse;
+ out_pulse when g_flow_control_verify = e_pulse;
src_in.ready <= out_ready;
src_in.xon <= not src_in.xon when rising_edge(clk); -- should have no effect, only passed on from src_in to snk_out
@@ -145,13 +145,13 @@ begin
-- Generate snk_in incrementing data with valid
proc_dp_gen_data(c_rl,
- c_data_w,
- c_data_init,
- rst,
- clk,
- in_en,
- snk_out,
- snk_in);
+ c_data_w,
+ c_data_init,
+ rst,
+ clk,
+ in_en,
+ snk_out,
+ snk_in);
p_stimuli : process
begin
@@ -168,26 +168,26 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index f9ff61dc0cde12b083755783d457d3e0a4726a7e..e8d27550072844004704bcf30bfae2642e1e3365 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter_func is
generic (
@@ -91,7 +91,7 @@ architecture tb of tb_dp_counter_func is
type t_count_arr is array(g_nof_counters - 1 downto 0) of natural;
signal tb_count_arr : t_count_arr := (others => 0);
signal tb_last_count_arr : t_count_arr := (others => 0);
- begin
+begin
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -103,7 +103,7 @@ architecture tb of tb_dp_counter_func is
------------------------------------------------------------------------------
p_stimuli : process
- variable run_clk_cnt: natural := 1;
+ variable run_clk_cnt: natural := 1;
begin
-- wait for reset
proc_common_wait_until_low(clk, rst);
@@ -144,20 +144,20 @@ architecture tb of tb_dp_counter_func is
-- dp_counter_func
------------------------------------------------------------------------------
u_dp_counter_func : entity work.dp_counter_func
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step
- )
- port map (
- rst => rst,
- clk => clk,
-
- count_en => dp_counter_func_count_en,
-
- count_src_out_arr => dp_counter_func_count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ count_en => dp_counter_func_count_en,
+
+ count_src_out_arr => dp_counter_func_count_src_out_arr
+ );
-- Add pipeline to removed combinatorial glitches for viewing in the wave window
dp_counter_func_count_src_out_arr_p <= dp_counter_func_count_src_out_arr when rising_edge(clk);
@@ -172,7 +172,7 @@ architecture tb of tb_dp_counter_func is
if tb_start_en = '1' then
for I in 0 to g_nof_counters - 1 loop
assert tb_count_arr(I) = g_range_start(I)
- report "DP : Wrong start of counter " & int_to_str(I) severity ERROR;
+ report "DP : Wrong start of counter " & int_to_str(I) severity ERROR;
end loop;
end if;
@@ -180,7 +180,7 @@ architecture tb of tb_dp_counter_func is
if tb_stopped_en = '1' then
for I in 0 to g_nof_counters - 1 loop
assert tb_count_arr(I) = TO_UINT(dp_counter_func_count_src_out_arr(I).data(c_max_count_w - 1 downto 0))
- report "DP : Counter " & int_to_str(I) & " not stopped after dp_counter_func_count_en <= 0" severity ERROR;
+ report "DP : Counter " & int_to_str(I) & " not stopped after dp_counter_func_count_en <= 0" severity ERROR;
end loop;
end if;
@@ -189,11 +189,11 @@ architecture tb of tb_dp_counter_func is
-- all counters except the last one should hold the start value
for I in 0 to g_nof_counters - 2 loop
assert tb_count_arr(I) = g_range_start(I)
- report "DP : Wrong carryover, counter:" & int_to_str(I) severity ERROR;
+ report "DP : Wrong carryover, counter:" & int_to_str(I) severity ERROR;
end loop;
-- the last counter should hold the start value + step
assert tb_count_arr(g_nof_counters - 1) = g_range_start(g_nof_counters - 1) + g_range_step(g_nof_counters - 1)
- report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1) severity ERROR;
+ report "DP : Wrong carryover, counter:" & int_to_str(g_nof_counters - 1) severity ERROR;
end if;
-- check counter values on sop and eop
@@ -203,15 +203,15 @@ architecture tb of tb_dp_counter_func is
if dp_counter_func_count_src_out_arr(I).eop = '1' then
assert tb_count_arr(I) = ((g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I)) * g_range_step(I) + g_range_start(I)
report "DP : Wrong stop count on eop, counter:" & int_to_str(I) &
- " is:" & int_to_str(tb_count_arr(I)) &
- " expected:" & int_to_str(((g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I)) * g_range_step(I) + g_range_start(I)) severity ERROR;
+ " is:" & int_to_str(tb_count_arr(I)) &
+ " expected:" & int_to_str(((g_range_stop(I) - 1 - g_range_start(I)) / g_range_step(I)) * g_range_step(I) + g_range_start(I)) severity ERROR;
end if;
-- on sop counter should hold the start_value
if dp_counter_func_count_src_out_arr(I).sop = '1' then
assert tb_count_arr(I) = g_range_start(I)
report "DP : Wrong start count on sop, counter:" & int_to_str(I) &
- " is:" & int_to_str(tb_count_arr(I)) &
- " expected:" & int_to_str(g_range_start(I)) severity ERROR;
+ " is:" & int_to_str(tb_count_arr(I)) &
+ " expected:" & int_to_str(g_range_start(I)) severity ERROR;
end if;
end loop;
end if;
@@ -222,13 +222,13 @@ architecture tb of tb_dp_counter_func is
if tb_count_arr(I) > tb_last_count_arr(I) then
assert (tb_last_count_arr(I) + g_range_step(I)) = tb_count_arr(I)
report "DP : Wrong step count, counter:" & int_to_str(I) &
- " is:" & int_to_str(tb_count_arr(I)) &
- " expected:" & int_to_str(tb_last_count_arr(I) + g_range_step(I)) severity ERROR;
+ " is:" & int_to_str(tb_count_arr(I)) &
+ " expected:" & int_to_str(tb_last_count_arr(I) + g_range_step(I)) severity ERROR;
elsif tb_count_arr(I) < tb_last_count_arr(I) then
assert g_range_start(I) = tb_count_arr(I)
report "DP : Wrong step count, counter:" & int_to_str(I) &
- " is:" & int_to_str(tb_count_arr(I)) &
- " expected:" & int_to_str(g_range_start(I)) & ")" severity ERROR;
+ " is:" & int_to_str(tb_count_arr(I)) &
+ " expected:" & int_to_str(g_range_start(I)) & ")" severity ERROR;
end if;
end loop;
end if;
@@ -240,5 +240,4 @@ architecture tb of tb_dp_counter_func is
gen_tb_count_arr : for i in 0 to g_nof_counters - 1 generate
tb_count_arr(I) <= TO_UINT(dp_counter_func_count_src_out_arr(I).data(c_max_count_w - 1 downto 0)) when dp_counter_func_count_en = '1';
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index 0d79d8e8f69e8bfae23a695169653267af9d8078..9b856ee368be399b1e0698143de414190c5859c5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -32,14 +32,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_counter_offset is
generic (
@@ -127,11 +127,11 @@ begin
in_en <= '1' when g_flow_control_stimuli = e_active else
in_random(in_random'high) when g_flow_control_stimuli = e_random else
- in_pulse when g_flow_control_stimuli = e_pulse;
+ in_pulse when g_flow_control_stimuli = e_pulse;
out_ready <= '1' when g_flow_control_verify = e_active else
out_random(out_random'high) when g_flow_control_verify = e_random else
- out_pulse when g_flow_control_verify = e_pulse;
+ out_pulse when g_flow_control_verify = e_pulse;
src_in.ready <= out_ready;
src_in.xon <= not src_in.xon when rising_edge(clk); -- should have no effect, only passed on from src_in to snk_out
@@ -148,13 +148,13 @@ begin
-- Generate snk_in incrementing data with valid
proc_dp_gen_data(c_rl,
- c_data_w,
- c_data_init,
- rst,
- clk,
- in_en,
- snk_out,
- snk_in);
+ c_data_w,
+ c_data_init,
+ rst,
+ clk,
+ in_en,
+ snk_out,
+ snk_in);
p_stimuli : process
begin
@@ -172,27 +172,27 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dp_counter : entity work.dp_counter
- generic map (
- g_nof_counters => g_nof_counters,
- g_range_start => g_range_start,
- g_range_stop => g_range_stop,
- g_range_step => g_range_step,
- g_pipeline_src_out => g_pipeline_src_out,
- g_pipeline_src_in => g_pipeline_src_in
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- snk_out => snk_out,
-
- src_out => src_out,
- src_in => src_in,
-
- count_offset_in_arr => count_offset_in_arr,
- count_src_out_arr => count_src_out_arr
- );
+ generic map (
+ g_nof_counters => g_nof_counters,
+ g_range_start => g_range_start,
+ g_range_stop => g_range_stop,
+ g_range_step => g_range_step,
+ g_pipeline_src_out => g_pipeline_src_out,
+ g_pipeline_src_in => g_pipeline_src_in
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ snk_out => snk_out,
+
+ src_out => src_out,
+ src_in => src_in,
+
+ count_offset_in_arr => count_offset_in_arr,
+ count_src_out_arr => count_src_out_arr
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
index 033d1fe07974c6468c04f7896a1148591d17e9c2..3211a3df12248da2ef8c36666bf3d58d8c2e0d52 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: Test bench to check deinterleave function on DP level
-- Usage:
@@ -41,7 +41,7 @@ entity tb_dp_deinterleave is
g_nof_out : natural := 2;
g_block_size : natural := 3;
g_use_complex : boolean := true
- );
+ );
end;
architecture tb of tb_dp_deinterleave is
@@ -108,26 +108,26 @@ begin
proc_common_wait_some_cycles(clk, c_input_inval);
v_bsn := INCR_UVEC(v_bsn, 1);
end loop;
- end process;
+ end process;
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_deinterleave : entity work.dp_deinterleave
- generic map (
- g_nof_out => g_nof_out,
- g_block_size_int => g_block_size,
- g_block_size_output => g_block_size,
- g_dat_w => g_dat_w,
- g_use_complex => g_use_complex
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => snk_in,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_out => g_nof_out,
+ g_block_size_int => g_block_size,
+ g_block_size_output => g_block_size,
+ g_dat_w => g_dat_w,
+ g_use_complex => g_use_complex
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => snk_in,
+ src_out_arr => src_out_arr
+ );
-----------------------------------------------------------------------------
-- Wave window monitor
@@ -143,5 +143,4 @@ begin
out_im_arr(I) <= src_out_arr(I).im(g_dat_w / 2 - 1 downto 0);
out_val_arr(I) <= src_out_arr(I).valid;
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
index 9d28335701b636c9b8b312b85bd018a63ecb8759..dfd2def86bfcfa304fa42c491124f76aeea2be76 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
@@ -43,14 +43,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_interleave_to_one is
generic (
@@ -98,8 +98,8 @@ architecture tb of tb_dp_deinterleave_interleave_to_one is
constant c_flow_control_latency_pls : natural := g_nof_repeat * g_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or c_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -142,43 +142,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
-- Throttle stimuli to ensure active = 1, period = 3, level '1'
--proc_common_gen_pulse(1, 3, '1', rst, clk, stimuli_src_in.ready);
@@ -215,108 +215,108 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => c_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_dp_deinterleave : entity work.dp_deinterleave
- generic map (
- g_dat_w => c_data_w,
- g_nof_out => g_nof_streams,
- g_block_size_int => 1,
- g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
- g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
- g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
- g_use_complex => g_use_complex,
- g_align_out => true -- Aligns the output streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out_arr => parallel_snk_in_arr
- );
-
- -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
- gen_fifos : for I in 0 to g_nof_streams - 1 generate
- u_dp_fifo_sc : entity work.dp_fifo_sc
generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_dat_w => c_data_w,
+ g_nof_out => g_nof_streams,
+ g_block_size_int => 1,
+ g_block_size_output => c_par_pkt_len, -- Output block size: The number of samles in the blocks at the output
+ g_use_ctrl => true, -- Requires: [input block size (sop:eop)] / [g_nof_out]/ [g_block_size_output] = integer number!
+ g_use_sync_bsn => true, -- forwards (stored) input Sync+BSN to all output streams
+ g_use_complex => g_use_complex,
+ g_align_out => true -- Aligns the output streams
)
port map (
rst => rst,
clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
+
+ snk_in => stimuli_src_out,
+ src_out_arr => parallel_snk_in_arr
);
+
+ -- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
+ gen_fifos : for I in 0 to g_nof_streams - 1 generate
+ u_dp_fifo_sc : entity work.dp_fifo_sc
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
------------------------------------------------------------------------------
-- DUT: N to 1
------------------------------------------------------------------------------
u_n_to_one: entity work.dp_interleave_n_to_one
- generic map (
- g_pipeline => c_pipeline,
- g_nof_inputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out_arr => parallel_src_in_arr,
- snk_in_arr => parallel_src_out_arr,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline => c_pipeline,
+ g_nof_inputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out_arr => parallel_src_in_arr,
+ snk_in_arr => parallel_src_out_arr,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 85bdf4243f1a90661baa7591005d9f1f51df3cd9..82492bf4b46a2d629675303f0df2ac34e303ad5b 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -37,14 +37,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_deinterleave_one_to_n_to_one is
generic (
@@ -90,8 +90,8 @@ architecture tb of tb_dp_deinterleave_one_to_n_to_one is
constant c_flow_control_latency_pls : natural := g_nof_repeat * g_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * g_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -134,43 +134,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => g_use_complex,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => g_use_complex,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -204,55 +204,55 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_out_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_out_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: 1 to N
------------------------------------------------------------------------------
u_one_to_n : entity work.dp_deinterleave_one_to_n
- generic map (
- g_pipeline => g_pipeline,
- g_nof_outputs => g_nof_streams
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- src_in_arr => parallel_snk_out_arr,
- src_out_arr => parallel_snk_in_arr
- );
+ generic map (
+ g_pipeline => g_pipeline,
+ g_nof_outputs => g_nof_streams
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ src_in_arr => parallel_snk_out_arr,
+ src_out_arr => parallel_snk_in_arr
+ );
no_fifo : if g_use_fifo = false generate
parallel_snk_out_arr <= parallel_src_in_arr;
@@ -260,42 +260,44 @@ begin
end generate;
-- Use FIFO to break flow control between one to N and N to one, so that stimuli see ready = '1'
- use_fifo : if g_use_fifo = true generate
+ use_fifo : if g_use_fifo = true generate
+
gen_fifos : for I in 0 to g_nof_streams - 1 generate
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_dp_stream_dsp_data_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_use_bsn => true,
- g_use_empty => true,
- g_use_channel => true,
- g_use_error => true,
- g_use_sync => true,
- g_use_ctrl => true, -- sop & eop
- g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- -- ST sink
- snk_out => parallel_snk_out_arr(I),
- snk_in => parallel_snk_in_arr(I),
- -- ST source
- src_in => parallel_src_in_arr(I),
- src_out => parallel_src_out_arr(I)
- );
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_dp_stream_dsp_data_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_use_bsn => true,
+ g_use_empty => true,
+ g_use_channel => true,
+ g_use_error => true,
+ g_use_sync => true,
+ g_use_ctrl => true, -- sop & eop
+ g_use_complex => g_use_complex, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
+ g_fifo_size => c_fifo_size -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ -- ST sink
+ snk_out => parallel_snk_out_arr(I),
+ snk_in => parallel_snk_in_arr(I),
+ -- ST source
+ src_in => parallel_src_in_arr(I),
+ src_out => parallel_src_out_arr(I)
+ );
end generate;
+
end generate;
- ------------------------------------------------------------------------------
- -- DUT: N to 1
- ------------------------------------------------------------------------------
- u_n_to_one: entity work.dp_interleave_n_to_one
+------------------------------------------------------------------------------
+-- DUT: N to 1
+------------------------------------------------------------------------------
+u_n_to_one: entity work.dp_interleave_n_to_one
generic map (
g_pipeline => g_pipeline,
g_nof_inputs => g_nof_streams
@@ -310,11 +312,11 @@ begin
src_out => verify_snk_in
);
- ------------------------------------------------------------------------------
- -- Auxiliary
- ------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- Auxiliary
+------------------------------------------------------------------------------
- -- Map to slv to ease monitoring in wave window
- stimuli_src_out_data <= stimuli_src_out.data(c_data_w - 1 downto 0);
- verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
+-- Map to slv to ease monitoring in wave window
+stimuli_src_out_data <= stimuli_src_out.data(c_data_w - 1 downto 0);
+verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index 16b878e5441c78ac0f30b5f18b92ea15c83eb997..fe163083f5dc6e0c5ee9c5ed4ec1741e10ad1ced 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_demux is
generic (
@@ -161,8 +161,8 @@ begin
in_channel_vec((I + 1) * c_dp_data_w - 1 downto I * c_dp_data_w) <= in_channel(I);
-- Stimuli control
--- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
--- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
+ -- proc_dp_count_en(rst, clk, sync, lfsr1(I)(c_random_w-1 DOWNTO 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en behave the same
+ -- proc_dp_out_ready(rst, clk, sync, lfsr2(I)(c_random_w DOWNTO 0), out_ready(I)); -- all out_ready behave the same
proc_dp_count_en(rst, clk, sync_dly(I), lfsr1(I)(c_random_w - 1 downto 0), state(I), verify_done(I), tb_end_vec(I), cnt_en(I)); -- all cnt_en are relatively delayed
proc_dp_out_ready(rst, clk, sync_dly(I), lfsr2(I)(c_random_w downto 0), out_ready(I)); -- all out_ready are relatively delayed
@@ -220,47 +220,47 @@ begin
end process;
mux : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dp_data_w,
- g_error_w => 1,
- g_use_empty => true,
- g_use_in_channel => true,
- g_use_error => false,
- g_nof_input => g_dut_nof_output,
- g_use_fifo => false,
- g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
- g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi,
- -- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
- src_out => mux_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dp_data_w,
+ g_error_w => 1,
+ g_use_empty => true,
+ g_use_in_channel => true,
+ g_use_error => false,
+ g_nof_input => g_dut_nof_output,
+ g_use_fifo => false,
+ g_fifo_size => array_init(1024, g_dut_nof_output), -- FIFO is not used, but generic must match g_nof_input
+ g_fifo_fill => array_init( 0, g_dut_nof_output) -- FIFO is not used, but generic must match g_nof_input
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi,
+ -- ST source
+ src_in => mux_siso, -- IN = request from downstream ST sink
+ src_out => mux_sosi
+ );
------------------------------------------------------------------------------
-- DUT dp_demux
------------------------------------------------------------------------------
dut : entity work.dp_demux
- generic map (
- g_nof_output => g_dut_nof_output,
- g_combined => g_combined
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => mux_siso, -- OUT = request to upstream ST source
- snk_in => mux_sosi,
- -- ST source
- src_in_arr => demux_siso, -- IN = request from downstream ST sink
- src_out_arr => demux_sosi
- );
+ generic map (
+ g_nof_output => g_dut_nof_output,
+ g_combined => g_combined
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => mux_siso, -- OUT = request to upstream ST source
+ snk_in => mux_sosi,
+ -- ST source
+ src_in_arr => demux_siso, -- IN = request from downstream ST sink
+ src_out_arr => demux_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index 6fe69179dad03f809521fe4c9c25d49f673c7552..5faa32681572d7d77ad665cf086a13b1c4e5d49b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -39,13 +39,13 @@
-- would need to use DP packet encoder and decoders.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_distribute is
generic (
@@ -148,11 +148,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
out_siso.xon <= '1';
out_siso_arr <= (others => out_siso);
@@ -163,6 +163,7 @@ begin
-- Generate data path input data
gen_input : for I in 0 to g_nof_input - 1 generate
+
p_stimuli : process
variable v_data_init : natural;
variable v_data_value : natural;
@@ -205,7 +206,7 @@ begin
count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1'; -- count number of output eop
prev_count_eop(I) <= count_eop(I) when rising_edge(clk);
verify_done(I) <= '1' when rising_edge(clk) and count_eop(I) = c_nof_expected and count_eop(I) /= prev_count_eop(I) else
- '0' when rising_edge(clk); -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
+ '0' when rising_edge(clk); -- signal verify done after c_nof_expected frames, use pulse to have only one assert from proc_dp_verify_value()
verify_end(I) <= '1' when rising_edge(clk) and verify_done(I) = '1'; -- signal verify_end after verify_done pulse, use level to ensure tb_end even if the stimuli are still busy
-- Actual verification of the output streams
@@ -239,71 +240,71 @@ begin
-- n --> m
tx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => true,
- g_nof_input => g_nof_input,
- g_nof_output => g_nof_serial,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_tx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_bsn => g_tx_use_fifo,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => g_tx_use_fifo,
- g_fifo_fill => g_tx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => serial_siso_arr,
- src_out_arr => serial_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => true,
+ g_nof_input => g_nof_input,
+ g_nof_output => g_nof_serial,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_tx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => g_tx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => g_tx_use_fifo,
+ g_fifo_fill => g_tx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => serial_siso_arr,
+ src_out_arr => serial_sosi_arr
+ );
-- m --> n
rx : entity work.dp_distribute
- generic map (
- -- Distribution IO
- g_tx => false,
- g_nof_input => g_nof_serial,
- g_nof_output => g_nof_input,
- g_transpose => g_transpose,
- g_code_channel_lo => g_code_channel_lo,
- g_data_w => c_data_w,
- -- Input FIFO
- g_use_fifo => g_rx_use_fifo,
- g_bsn_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
- g_error_w => 1,
- g_use_bsn => g_rx_use_fifo,
- g_use_empty => false,
- g_use_channel => c_rx_use_fifo_link_channel_lo,
- g_use_error => false,
- g_use_sync => g_rx_use_fifo,
- g_fifo_fill => g_rx_fifo_fill,
- g_fifo_size => c_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out_arr => serial_siso_arr,
- snk_in_arr => serial_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ -- Distribution IO
+ g_tx => false,
+ g_nof_input => g_nof_serial,
+ g_nof_output => g_nof_input,
+ g_transpose => g_transpose,
+ g_code_channel_lo => g_code_channel_lo,
+ g_data_w => c_data_w,
+ -- Input FIFO
+ g_use_fifo => g_rx_use_fifo,
+ g_bsn_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => c_link_channel_lo, -- c_link_channel_lo-1 DOWNTO 0
+ g_error_w => 1,
+ g_use_bsn => g_rx_use_fifo,
+ g_use_empty => false,
+ g_use_channel => c_rx_use_fifo_link_channel_lo,
+ g_use_error => false,
+ g_use_sync => g_rx_use_fifo,
+ g_fifo_fill => g_rx_fifo_fill,
+ g_fifo_size => c_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => serial_siso_arr,
+ snk_in_arr => serial_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
index 464fd24ca51e27772f1d3b83c3c6d3d085ec2eb5..2cf406bac193c8527083d2c676807439ed7dfd73 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
@@ -120,13 +120,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_dut is
generic (
@@ -198,39 +198,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -264,37 +264,37 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_dat_w,
- g_pkt_len => g_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_dat_w,
+ g_pkt_len => g_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT
@@ -312,16 +312,16 @@ begin
-- DUT function
gen_dut : if g_no_dut = false generate
u_dut : entity work.dp_example_dut
- port map (
- rst => rst,
- clk => clk,
+ port map (
+ rst => rst,
+ clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out
- );
+ src_in => dut_src_in,
+ src_out => dut_src_out
+ );
end generate;
-- Connect DUT source output stream to verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index 7cf8b884b245a1a100016b9349c80f8aae027225..17dfe20d6cb74ec7339d9bd55f39843abbdeae5d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -111,13 +111,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_example_no_dut is
generic (
@@ -203,11 +203,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index 2c5c009486395e7a4878c2fc6831f797ae1edb3a..41660443ab860a52663d38bc64861fe5a2938cc7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc is
generic (
@@ -196,31 +196,31 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_dc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index 5c75f0d420d57874dea2b76072bc5b1309c7d920..6829d6a1c9505276fdffce6d3b2c882e38187220 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -26,11 +26,11 @@
-- Verifies output data and ctrl signals of DUT. This is configurable using generics.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_dc_arr is
generic (
@@ -213,36 +213,36 @@ begin
out_eop <= out_sosi_arr(0).eop;
dut : entity work.dp_fifo_dc_arr
- generic map (
- g_nof_streams => g_dut_nof_streams,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_aux_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_aux => g_dut_use_aux,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => c_dut_fifo_size,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- wr_rst => rst,
- wr_clk => wr_clk,
- rd_rst => rst,
- rd_clk => rd_clk,
- snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi_arr,
- in_aux(0) => in_aux,
- wr_usedw => usedw,
- rd_usedw => OPEN,
- src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
- src_out_arr => out_sosi_arr,
- out_aux(0) => out_aux
- );
+ generic map (
+ g_nof_streams => g_dut_nof_streams,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_aux_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_aux => g_dut_use_aux,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => c_dut_fifo_size,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ wr_rst => rst,
+ wr_clk => wr_clk,
+ rd_rst => rst,
+ rd_clk => rd_clk,
+ snk_out_arr => in_siso_arr, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi_arr,
+ in_aux(0) => in_aux,
+ wr_usedw => usedw,
+ rd_usedw => OPEN,
+ src_in_arr => out_siso_arr, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi_arr,
+ out_aux(0) => out_aux
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index 58dfd08b6b86182b08636a4040a432cc9bccb9f0..f5f8d9e2f82cc3cc1a848e2a6c6c8f2ac570a972 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -20,13 +20,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- run 50 us
@@ -193,72 +193,72 @@ begin
-- Narrow to wide FIFO
u_dut_n2w : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => g_narrow_w,
- g_rd_data_w => c_wide_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => narrow_rst,
- wr_clk => narrow_clk,
- rd_rst => wide_rst,
- rd_clk => wide_clk,
- -- ST sink
- snk_out => in_siso,
- snk_in => in_sosi,
- -- Monitor FIFO filling
- wr_usedw => fifo_n2w_wr_usedw,
- rd_usedw => fifo_n2w_rd_usedw,
- rd_emp => fifo_n2w_rd_emp,
- -- ST source
- src_in => wide_siso,
- src_out => wide_sosi
- );
+ generic map (
+ g_wr_data_w => g_narrow_w,
+ g_rd_data_w => c_wide_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => narrow_rst,
+ wr_clk => narrow_clk,
+ rd_rst => wide_rst,
+ rd_clk => wide_clk,
+ -- ST sink
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_n2w_wr_usedw,
+ rd_usedw => fifo_n2w_rd_usedw,
+ rd_emp => fifo_n2w_rd_emp,
+ -- ST source
+ src_in => wide_siso,
+ src_out => wide_sosi
+ );
-- Adapt for wide to narrow FIFO input RL=1 in case g_read_rl=0
u_rl : entity work.dp_latency_adapter
- generic map (
- g_in_latency => g_read_rl,
- g_out_latency => c_rl
- )
- port map (
- rst => wide_rst,
- clk => wide_clk,
- -- ST sink
- snk_out => wide_siso,
- snk_in => wide_sosi,
- -- ST source
- src_in => wide_siso_rl1,
- src_out => wide_sosi_rl1
- );
+ generic map (
+ g_in_latency => g_read_rl,
+ g_out_latency => c_rl
+ )
+ port map (
+ rst => wide_rst,
+ clk => wide_clk,
+ -- ST sink
+ snk_out => wide_siso,
+ snk_in => wide_sosi,
+ -- ST source
+ src_in => wide_siso_rl1,
+ src_out => wide_sosi_rl1
+ );
-- Wide to narrow FIFO
u_dut_w2n : entity work.dp_fifo_dc_mixed_widths
- generic map (
- g_wr_data_w => c_wide_w,
- g_rd_data_w => g_narrow_w,
- g_use_ctrl => g_use_ctrl,
- g_wr_fifo_size => c_wr_fifo_size,
- g_rd_fifo_rl => g_read_rl
- )
- port map (
- wr_rst => wide_rst,
- wr_clk => wide_clk,
- rd_rst => narrow_rst,
- rd_clk => narrow_clk,
- -- ST sink
- snk_out => wide_siso_rl1,
- snk_in => wide_sosi_rl1,
- -- Monitor FIFO filling
- wr_usedw => fifo_w2n_wr_usedw,
- rd_usedw => fifo_w2n_rd_usedw,
- rd_emp => fifo_w2n_rd_emp,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_wr_data_w => c_wide_w,
+ g_rd_data_w => g_narrow_w,
+ g_use_ctrl => g_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_size,
+ g_rd_fifo_rl => g_read_rl
+ )
+ port map (
+ wr_rst => wide_rst,
+ wr_clk => wide_clk,
+ rd_rst => narrow_rst,
+ rd_clk => narrow_clk,
+ -- ST sink
+ snk_out => wide_siso_rl1,
+ snk_in => wide_sosi_rl1,
+ -- Monitor FIFO filling
+ wr_usedw => fifo_w2n_wr_usedw,
+ rd_usedw => fifo_w2n_rd_usedw,
+ rd_emp => fifo_w2n_rd_emp,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- 1) Verify intermediate wide data
@@ -288,5 +288,4 @@ begin
gen_exact : if g_use_ctrl = true generate
proc_dp_verify_value(e_equal, narrow_clk, verify_done, expected_exact, prev_out_data); -- for framed data we know exactly what to expect
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index d6ad771c2a194788d7163a489de69e9fd2f48d52..5c79fd0b154b5c384c47e18abcc82c1a9efc2da1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -35,11 +35,11 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill is
generic (
@@ -211,28 +211,28 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index aeceefb25f8bc843758debbb6a078bbd2bd24980..8fca288a0f4b31c777330262d4e06ccd9f6f4aa7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -37,12 +37,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_eop is
generic (
@@ -187,7 +187,7 @@ begin
in_channel <= INCR_UVEC(in_data, c_channel_offset);
-- Stimuli control
- proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
+ proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
gen_random_ctrl : if g_dut_use_random_ctrl generate
proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
@@ -267,33 +267,33 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_eop
- generic map (
- g_use_dual_clock => g_dut_use_dual_clock,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rd_rst => rst,
- rd_clk => clk,
- wr_rst => rst,
- wr_clk => clk,
- wr_ful => wr_ful,
- rd_usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_use_dual_clock => g_dut_use_dual_clock,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rd_rst => rst,
+ rd_clk => clk,
+ wr_rst => rst,
+ wr_clk => clk,
+ wr_ful => wr_ful,
+ rd_usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index bd1ccdaaa0c07ae157a96cc4a067bcf8cd611fcb..8408981ef29ca7c830113a5b6b03e7ddf832ff95 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -35,12 +35,12 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_fill_sc is
generic (
@@ -241,30 +241,30 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_fill_sc
- generic map (
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_fifo_fill => g_dut_fifo_fill,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_rl => g_dut_fifo_rl
- )
- port map (
- rst => rst,
- clk => clk,
- wr_ful => wr_ful,
- usedw => rd_usedw,
- rd_fill_32b => rd_fill_32b,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_fifo_fill => g_dut_fifo_fill,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_rl => g_dut_fifo_rl
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ wr_ful => wr_ful,
+ usedw => rd_usedw,
+ rd_fill_32b => rd_fill_32b,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index aea359818b59eaab5fd1f1bcd8211b06d3c54fd4..2c912fc91eb1f2f2ee3600c1bed4dcf3be7ac4ec 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_info is
generic (
@@ -131,11 +131,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -188,51 +188,51 @@ begin
-- Stimuli data delay
u_dp_pipeline : entity work.dp_pipeline
- generic map (
- g_pipeline => g_data_delay
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- -- ST source
- src_in => dp_pipeline_src_in,
- src_out => dp_pipeline_src_out
- );
+ generic map (
+ g_pipeline => g_data_delay
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ -- ST source
+ src_in => dp_pipeline_src_in,
+ src_out => dp_pipeline_src_out
+ );
------------------------------------------------------------------------------
-- DUT dp_fifo_info
------------------------------------------------------------------------------
dut : entity work.dp_fifo_info
- generic map (
- g_use_sync => g_info_use_sync,
- g_use_bsn => g_info_use_bsn,
- g_use_channel => g_info_use_channel,
- g_use_empty => g_info_use_empty,
- g_use_error => g_info_use_error,
- g_bsn_w => c_dp_stream_bsn_w,
- g_empty_w => c_dp_stream_empty_w,
- g_channel_w => c_dp_stream_channel_w,
- g_error_w => c_dp_stream_error_w,
- g_fifo_size => g_info_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor info FIFO filling
- fifo_wr_ful => fifo_wr_ful,
- fifo_usedw => fifo_usedw,
- fifo_rd_emp => fifo_rd_emp,
- -- ST sink
- data_snk_out => dp_pipeline_src_in,
- data_snk_in => dp_pipeline_src_out, -- delayed snk_in data
- info_snk_in => stimuli_src_out, -- original snk_in info
- -- ST source
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_use_sync => g_info_use_sync,
+ g_use_bsn => g_info_use_bsn,
+ g_use_channel => g_info_use_channel,
+ g_use_empty => g_info_use_empty,
+ g_use_error => g_info_use_error,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_empty_w => c_dp_stream_empty_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_error_w => c_dp_stream_error_w,
+ g_fifo_size => g_info_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor info FIFO filling
+ fifo_wr_ful => fifo_wr_ful,
+ fifo_usedw => fifo_usedw,
+ fifo_rd_emp => fifo_rd_emp,
+ -- ST sink
+ data_snk_out => dp_pipeline_src_in,
+ data_snk_in => dp_pipeline_src_out, -- delayed snk_in data
+ info_snk_in => stimuli_src_out, -- original snk_in info
+ -- ST source
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
index 0597d8e0dc06249db6a37dd459e363922ab17a03..efaaa946f2029abda99eaea3530a67c91628f574 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_sc is
generic (
@@ -194,30 +194,30 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_fifo_sc
- generic map (
- g_use_lut => g_dut_use_lut,
- g_data_w => c_dp_data_w,
- g_bsn_w => c_dp_bsn_w,
- g_empty_w => c_dp_empty_w,
- g_channel_w => c_dp_channel_w,
- g_error_w => 1,
- g_use_bsn => g_dut_use_bsn,
- g_use_empty => g_dut_use_empty,
- g_use_channel => g_dut_use_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_use_ctrl => g_dut_use_ctrl,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_af_margin => g_dut_fifo_af_margin,
- g_fifo_rl => g_dut_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- usedw => usedw,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
+ generic map (
+ g_use_lut => g_dut_use_lut,
+ g_data_w => c_dp_data_w,
+ g_bsn_w => c_dp_bsn_w,
+ g_empty_w => c_dp_empty_w,
+ g_channel_w => c_dp_channel_w,
+ g_error_w => 1,
+ g_use_bsn => g_dut_use_bsn,
+ g_use_empty => g_dut_use_empty,
+ g_use_channel => g_dut_use_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_use_ctrl => g_dut_use_ctrl,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_af_margin => g_dut_fifo_af_margin,
+ g_fifo_rl => g_dut_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ usedw => usedw,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
index 141127e58cb195aa67381dc8d13cf96e47d40e12..b1553752b5c5526ebe1ad13c68d93d4552f1487d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: This test bench verifies both dp_fifo_from_mm and dp_fifo_to_mm.
-- Usage:
@@ -138,7 +138,7 @@ begin
else
state_wr <= s_random;
end if;
- state_wr <= s_one_go;
+ state_wr <= s_one_go;
when s_one_go =>
if unsigned(wr_availw) > 0 then
mm_wr <= '1';
@@ -148,7 +148,7 @@ begin
when s_random =>
if unsigned(wr_availw) > 0 then
mm_wr <= '1';
- v_burst := (TO_UINT(wr_availw) * TO_UINT(random_wr)) / 2**random_wr'length; -- determine a random write burst size < wr_availw to fill part of the FIFO
+ v_burst := (TO_UINT(wr_availw) * TO_UINT(random_wr)) / 2 ** random_wr'length; -- determine a random write burst size < wr_availw to fill part of the FIFO
end if;
state_wr <= s_idle;
end case;
@@ -176,7 +176,7 @@ begin
else
state_rd <= s_random;
end if;
- state_rd <= s_one_go;
+ state_rd <= s_one_go;
when s_one_go =>
if unsigned(rd_usedw) > 0 then
mm_rd <= '1';
@@ -186,7 +186,7 @@ begin
when s_random =>
if unsigned(rd_usedw) > 0 then
mm_rd <= '1';
- v_burst := (TO_UINT(rd_usedw) * TO_UINT(random_rd)) / 2**random_rd'length; -- determine a random read burst size < rd_usedw to empty part of the FIFO
+ v_burst := (TO_UINT(rd_usedw) * TO_UINT(random_rd)) / 2 ** random_rd'length; -- determine a random read burst size < rd_usedw to empty part of the FIFO
end if;
state_rd <= s_idle;
end case;
@@ -197,25 +197,25 @@ begin
end process;
u_from_mm : entity work.dp_fifo_from_mm
- generic map (
- g_fifo_size => c_fifo_size,
- g_fifo_af_margin => c_fifo_af_margin,
- g_mm_word_w => c_mm_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST soure connected to FIFO input
- src_out => wr_sosi,
- usedw => fifo_usedw,
- -- Control for FIFO read access
- mm_wr => mm_wr,
- mm_wrdata => mm_wrdata,
- mm_usedw => OPEN,
- mm_availw => wr_availw
+ generic map (
+ g_fifo_size => c_fifo_size,
+ g_fifo_af_margin => c_fifo_af_margin,
+ g_mm_word_w => c_mm_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST soure connected to FIFO input
+ src_out => wr_sosi,
+ usedw => fifo_usedw,
+ -- Control for FIFO read access
+ mm_wr => mm_wr,
+ mm_wrdata => mm_wrdata,
+ mm_usedw => OPEN,
+ mm_availw => wr_availw
);
- u_fifo : entity work.dp_fifo_sc
+u_fifo : entity work.dp_fifo_sc
generic map (
g_data_w => c_mm_data_w,
g_use_ctrl => false,
@@ -231,16 +231,16 @@ begin
snk_in => wr_sosi,
-- Monitor FIFO filling
wr_ful => fifo_full,
- usedw => fifo_usedw,
- rd_emp => OPEN,
- -- ST source
- src_in => rd_siso,
- src_out => rd_sosi
+ usedw => fifo_usedw,
+ rd_emp => OPEN,
+ -- ST source
+ src_in => rd_siso,
+ src_out => rd_sosi
);
- rd_siso.ready <= mm_rd;
+rd_siso.ready <= mm_rd;
- u_to_mm : entity work.dp_fifo_to_mm
+u_to_mm : entity work.dp_fifo_to_mm
generic map (
g_fifo_size => c_fifo_size,
g_mm_word_w => c_mm_data_w
@@ -251,31 +251,31 @@ begin
-- ST sink connected to FIFO output
snk_out => rd_siso,
snk_in => rd_sosi,
- usedw => fifo_usedw,
- -- Control for FIFO read access
- mm_rd => mm_rd,
- mm_rddata => mm_rddata,
- mm_usedw => rd_usedw
+ usedw => fifo_usedw,
+ -- Control for FIFO read access
+ mm_rd => mm_rd,
+ mm_rddata => mm_rddata,
+ mm_usedw => rd_usedw
);
- p_verify : process(clk)
- begin
- if rising_edge(clk) then
- -- Verify that FIFO never runs full
- assert fifo_full = '0' report "TB : FIFO full must not occur" severity ERROR;
-
- -- Verify that the read data is in not too much behind the write data
- assert unsigned(mm_wrdata) <= unsigned(mm_rddata) + c_fifo_size report "TB : Too large difference value" severity ERROR;
- end if;
- end process;
-
- -- Verify that stimuli have run at all by checking that the read data has reached at least a certain value at the verify done pulse
- expected_mm_rddata <= TO_UVEC(c_run_time / 3, c_mm_data_w);
- verify_done <= '0', '1' after clk_period * c_run_time, '0' after clk_period * (c_run_time+1);
- tb_end <= '0', '1' after clk_period * (c_run_time+100);
- proc_dp_verify_value(e_at_least, clk, verify_done, expected_mm_rddata, mm_rddata);
-
- -- Verify that the read data is incrementing data
- mm_rdval <= mm_rd when rising_edge(clk);
- proc_common_verify_data(c_rl, clk, verify_en, ready, mm_rdval, mm_rddata, prev_mm_rddata);
+p_verify : process(clk)
+begin
+ if rising_edge(clk) then
+ -- Verify that FIFO never runs full
+ assert fifo_full = '0' report "TB : FIFO full must not occur" severity ERROR;
+
+ -- Verify that the read data is in not too much behind the write data
+ assert unsigned(mm_wrdata) <= unsigned(mm_rddata) + c_fifo_size report "TB : Too large difference value" severity ERROR;
+ end if;
+end process;
+
+-- Verify that stimuli have run at all by checking that the read data has reached at least a certain value at the verify done pulse
+expected_mm_rddata <= TO_UVEC(c_run_time / 3, c_mm_data_w);
+verify_done <= '0', '1' after clk_period * c_run_time, '0' after clk_period * (c_run_time+1);
+tb_end <= '0', '1' after clk_period * (c_run_time+100);
+proc_dp_verify_value(e_at_least, clk, verify_done, expected_mm_rddata, mm_rddata);
+
+-- Verify that the read data is incrementing data
+mm_rdval <= mm_rd when rising_edge(clk);
+proc_common_verify_data(c_rl, clk, verify_en, ready, mm_rdval, mm_rddata, prev_mm_rddata);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
index 2c7c60352a14a2f1c1517802ef2d84570db53a80..3042798f15e232a32e8963c301ad66fcadc7f44a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
@@ -75,14 +75,14 @@
-- Self test result is OK when there is no FAILURE due to FIFO overflow.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_fifo_xonoff is
generic (
@@ -162,20 +162,21 @@ begin
-- Stimuli:
------------------------------------------------------------------------------
gen_bg_arr : for I in 0 to g_nof_inputs - 1 generate
+
p_bg_arr : process
begin
while true loop
proc_dp_gen_frame(c_ready_latency,
- c_data_w,
- c_symbol_w,
- c_symbol_init,
- c_nof_symbols,
- c_bsn + I, -- use bsn to identify the inputs
- c_sync,
- clk,
- in_en,
- bg_siso,
- bg_sosi_arr(I));
+ c_data_w,
+ c_symbol_w,
+ c_symbol_init,
+ c_nof_symbols,
+ c_bsn + I, -- use bsn to identify the inputs
+ c_sync,
+ clk,
+ in_en,
+ bg_siso,
+ bg_sosi_arr(I));
wait for g_gap_size * c_clk_period;
end loop;
-- Use WHILE LOOP and WAIT to avoid warning (vcom-1090) Possible infinite loop:
@@ -185,17 +186,17 @@ begin
gen_dp_xonoff : if g_use_in_xonoff generate
u_dp_xonoff : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => OPEN,
- in_sosi => bg_sosi_arr(I),
- -- Frame out
- out_siso => fifo_in_siso_arr(I),
- out_sosi => fifo_in_sosi_arr(I),
- out_en => dp_out_en_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => OPEN,
+ in_sosi => bg_sosi_arr(I),
+ -- Frame out
+ out_siso => fifo_in_siso_arr(I),
+ out_sosi => fifo_in_sosi_arr(I),
+ out_en => dp_out_en_arr(I)
+ );
end generate;
no_dp_xonoff : if not g_use_in_xonoff generate
@@ -204,48 +205,48 @@ begin
end generate;
u_in_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_bsn_w => c_nof_input_w,
- g_use_bsn => true, -- use bsn to identify the inputs
- g_use_ctrl => true, -- sop & eop
- g_fifo_size => c_in_fifo_size,
- g_fifo_af_margin => c_fifo_af_ready,
- g_fifo_af_xon => c_fifo_af_xon,
- g_fifo_rl => c_ready_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- wr_ful => in_fifo_wr_ful_arr(I),
- usedw => in_fifo_usedw_arr(I),
- rd_emp => in_fifo_rd_emp_arr(I),
- -- ST sink
- snk_out => fifo_in_siso_arr(I), -- flush control via out_siso.xon
- snk_in => fifo_in_sosi_arr(I),
- -- ST source
- src_in => mux_in_siso_arr(I),
- src_out => mux_in_sosi_arr(I)
+ generic map (
+ g_data_w => c_data_w,
+ g_bsn_w => c_nof_input_w,
+ g_use_bsn => true, -- use bsn to identify the inputs
+ g_use_ctrl => true, -- sop & eop
+ g_fifo_size => c_in_fifo_size,
+ g_fifo_af_margin => c_fifo_af_ready,
+ g_fifo_af_xon => c_fifo_af_xon,
+ g_fifo_rl => c_ready_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ wr_ful => in_fifo_wr_ful_arr(I),
+ usedw => in_fifo_usedw_arr(I),
+ rd_emp => in_fifo_rd_emp_arr(I),
+ -- ST sink
+ snk_out => fifo_in_siso_arr(I), -- flush control via out_siso.xon
+ snk_in => fifo_in_sosi_arr(I),
+ -- ST source
+ src_in => mux_in_siso_arr(I),
+ src_out => mux_in_sosi_arr(I)
);
- end generate;
+end generate;
- -- Enable input after reset and disable it before tb_end, to read FIFOs empty
- in_en <= '0', '1' after c_clk_period * 17,
- '0' after 4 * c_tb_nof_clk_cycles * c_clk_period;
+-- Enable input after reset and disable it before tb_end, to read FIFOs empty
+in_en <= '0', '1' after c_clk_period * 17,
+'0' after 4 * c_tb_nof_clk_cycles * c_clk_period;
- -- Also verify toggling external siso.xon flow control
- out_siso.xon <= '1',
+-- Also verify toggling external siso.xon flow control
+out_siso.xon <= '1',
'0' after 2 * c_tb_nof_clk_cycles * c_clk_period,
- '1' after 3 * c_tb_nof_clk_cycles * c_clk_period;
+'1' after 3 * c_tb_nof_clk_cycles * c_clk_period;
- -- End test
- tb_end <= '0', '1' after 5 * c_tb_nof_clk_cycles * c_clk_period;
+-- End test
+tb_end <= '0', '1' after 5 * c_tb_nof_clk_cycles * c_clk_period;
- ------------------------------------------------------------------------------
- -- Multiplexer
- ------------------------------------------------------------------------------
- u_dp_mux : entity work.dp_mux
+------------------------------------------------------------------------------
+-- Multiplexer
+------------------------------------------------------------------------------
+u_dp_mux : entity work.dp_mux
generic map (
g_nof_input => g_nof_inputs,
g_fifo_size => array_init(1024, g_nof_inputs), -- must match g_nof_input, even when g_use_fifo=FALSE
@@ -262,12 +263,12 @@ begin
src_out => mux_out_sosi
);
- ------------------------------------------------------------------------------
- -- Output
- ------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- Output
+------------------------------------------------------------------------------
- gen_dp_xonoff : if g_use_out_xonoff generate
- u_dp_xonoff : entity work.dp_xonoff
+gen_dp_xonoff : if g_use_out_xonoff generate
+ u_dp_xonoff : entity work.dp_xonoff
port map (
rst => rst,
clk => clk,
@@ -279,15 +280,15 @@ begin
out_sosi => fifo_fill_in_sosi,
out_en => dp_out_en
);
- end generate;
+end generate;
- no_dp_xonoff : if not g_use_out_xonoff generate
- fifo_fill_in_sosi <= mux_out_sosi;
- mux_out_siso <= fifo_fill_in_siso;
- dp_out_en <= '1';
- end generate;
+no_dp_xonoff : if not g_use_out_xonoff generate
+ fifo_fill_in_sosi <= mux_out_sosi;
+ mux_out_siso <= fifo_fill_in_siso;
+ dp_out_en <= '1';
+end generate;
- u_out_fifo : entity work.dp_fifo_fill_sc
+u_out_fifo : entity work.dp_fifo_fill_sc
--u_out_fifo : ENTITY work.dp_fifo_fill_eop_sc
generic map (
g_data_w => c_data_w,
@@ -304,13 +305,13 @@ begin
clk => clk,
-- Monitor FIFO filling
wr_ful => out_fifo_wr_ful,
- usedw => out_fifo_usedw,
- rd_emp => out_fifo_rd_emp,
- -- ST sink
- snk_out => fifo_fill_in_siso,
- snk_in => fifo_fill_in_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
+ usedw => out_fifo_usedw,
+ rd_emp => out_fifo_rd_emp,
+ -- ST sink
+ snk_out => fifo_fill_in_siso,
+ snk_in => fifo_fill_in_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index bb5e1dce668631c35da92367a168cdf38465c06b..3ffbd39fc37cfa98ead23f4e0121caca617aa861 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -29,13 +29,13 @@
-- . Observe m.flush_en and m.snk_in and m.src_out signals in Wave Window
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_flush is
generic (
@@ -121,11 +121,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
out_siso.ready <= out_ready when g_rl /= 0 else out_ready and out_sosi.valid; -- request for RL > 0, acknowledge for RL = 0
@@ -189,18 +189,18 @@ begin
-- These flush_en mode signals suit both g_rl=0 and g_rl>0
-- Use registered signals to avoid issues with different delta-cycle delays between both actors in_sosi.sop and flush_en_dly
reg_mode_flush_en_streaming <= '1' when rising_edge(clk) and flush_en_dly(0) = '1' else
- '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0'; -- equivalent to: reg_mode_flush_en_streaming <= vector_or(flush_en_dly);
+ '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0'; -- equivalent to: reg_mode_flush_en_streaming <= vector_or(flush_en_dly);
reg_mode_flush_en_framed <= '1' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(0) = '1' else
- '0' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(g_rl) = '0';
+ '0' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(g_rl) = '0';
reg_mode_flush_en_framed_xon <= '1' when rising_edge(clk) and flush_en_dly(0) = '1' else
- '0' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(g_rl) = '0';
+ '0' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(g_rl) = '0';
reg_mode_flush_en_framed_xoff <= '1' when rising_edge(clk) and in_sosi.sop = '1' and flush_en_dly(0) = '1' else
- '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0';
+ '0' when rising_edge(clk) and flush_en_dly(g_rl) = '0';
reg_mode_flush_en <= reg_mode_flush_en_streaming when g_framed_xon = false and g_framed_xoff = false else
reg_mode_flush_en_framed when g_framed_xon = true and g_framed_xoff = true else
reg_mode_flush_en_framed_xon when g_framed_xon = true and g_framed_xoff = false else
- reg_mode_flush_en_framed_xoff; -- g_framed_xon=FALSE AND g_framed_xoff=TRUE
+ reg_mode_flush_en_framed_xoff; -- g_framed_xon=FALSE AND g_framed_xoff=TRUE
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -256,23 +256,23 @@ begin
------------------------------------------------------------------------------
u_dut: entity work.dp_flush
- generic map (
- g_ready_latency => g_rl,
- g_framed_xon => g_framed_xon,
- g_framed_xoff => g_framed_xoff
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_in => in_sosi,
- snk_out => in_siso,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi,
- -- Enable flush
- flush_en => flush_en
- );
+ generic map (
+ g_ready_latency => g_rl,
+ g_framed_xon => g_framed_xon,
+ g_framed_xoff => g_framed_xoff
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_in => in_sosi,
+ snk_out => in_siso,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi,
+ -- Enable flush
+ flush_en => flush_en
+ );
-- Map record field to signals for easier monitoring in wave window
m.snk_out_ready <= in_siso.ready;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
index 1a752aaa71ad8deac703a7c386a827a560fae434..02221ea6c9cbacaf5fb6061173c352bee1eba30a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
@@ -26,13 +26,13 @@
-- . Verify stream through dp_unfolder->dp_folder stages
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_folder is
end tb_dp_folder;
@@ -94,30 +94,30 @@ begin
dp_unfolder_snk_in_arr(0) <= proc_dp_gen_block_data_src_out;
u_dp_unfolder : entity work.dp_unfolder
- generic map (
- g_nof_inputs => c_nof_inputs,
- g_nof_unfolds => c_nof_unfolds,
- g_output_align => false -- We're going to fold these outputs again, so don't align them!
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_arr => dp_unfolder_snk_in_arr,
- src_out_arr => dp_folder_snk_in_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_inputs,
+ g_nof_unfolds => c_nof_unfolds,
+ g_output_align => false -- We're going to fold these outputs again, so don't align them!
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_arr => dp_unfolder_snk_in_arr,
+ src_out_arr => dp_folder_snk_in_arr
+ );
u_dp_folder : entity work.dp_folder
- generic map (
- g_nof_inputs => c_nof_unfolded_streams,
- g_nof_folds => -1 -- Fold until 1 output remains,
--- g_output_block_size => c_packet_len
- )
- port map (
- clk => clk,
- rst => rst,
-
- snk_in_arr => dp_folder_snk_in_arr,
- src_out_arr => dp_folder_src_out_arr
- );
+ generic map (
+ g_nof_inputs => c_nof_unfolded_streams,
+ g_nof_folds => -1 -- Fold until 1 output remains,
+ -- g_output_block_size => c_packet_len
+ )
+ port map (
+ clk => clk,
+ rst => rst,
+
+ snk_in_arr => dp_folder_snk_in_arr,
+ src_out_arr => dp_folder_src_out_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index 8b0d02b22bb7ea8f243399277cd8e93dda14e2a5..ccfb59499230f707963850f71d94c3995be5e549 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_frame_rd is
end tb_dp_frame_rd;
@@ -53,7 +53,7 @@ architecture tb of tb_dp_frame_rd is
--CONSTANT c_throttle_eof : BOOLEAN := TRUE; -- when false immediately continue request next frame after eof
constant c_throttle_eof : boolean := false;
constant c_frame_request : std_logic := '1'; -- when '1' then always request, else only in state s_request when not frm_ack
- -- use '1' to verify c_throttle_eof=FALSE
+ -- use '1' to verify c_throttle_eof=FALSE
type t_state_enum is (s_request, s_eof, s_err);
@@ -97,14 +97,15 @@ architecture tb of tb_dp_frame_rd is
signal exp_data : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(100, c_data_w);
- procedure proc_frame(constant in_sof : in std_logic;
- constant in_data : in std_logic_vector(c_data_w - 1 downto 0);
- constant empty_length : in natural;
- signal clk : in std_logic;
- signal frm_data : out std_logic_vector(c_data_w - 1 downto 0);
- signal frm_val : out std_logic;
- signal frm_sof : out std_logic;
- signal frm_eof : out std_logic) is
+ procedure proc_frame(
+ constant in_sof : in std_logic;
+ constant in_data : in std_logic_vector(c_data_w - 1 downto 0);
+ constant empty_length : in natural;
+ signal clk : in std_logic;
+ signal frm_data : out std_logic_vector(c_data_w - 1 downto 0);
+ signal frm_val : out std_logic;
+ signal frm_sof : out std_logic;
+ signal frm_eof : out std_logic) is
variable v_frm_data : std_logic_vector(frm_data'range);
begin
frm_val <= '1';
@@ -199,29 +200,29 @@ begin
fifo_rd_eof <= rd_sosi.eop;
u_fifo : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_data_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => true,
- g_fifo_size => c_fifo_nof_words,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- usedw => fifo_usedw,
- src_in => rd_siso, -- IN = request from downstream ST sink
- src_out => rd_sosi
+ generic map (
+ g_data_w => c_data_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => true,
+ g_fifo_size => c_fifo_nof_words,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ usedw => fifo_usedw,
+ src_in => rd_siso, -- IN = request from downstream ST sink
+ src_out => rd_sosi
);
- u_dut : entity work.dp_frame_rd
+u_dut : entity work.dp_frame_rd
generic map (
g_dat_w => c_data_w,
g_frm_cnt_max => 1,
@@ -253,53 +254,53 @@ begin
out_eof => out_eof
);
- p_output_stimuli : process
- begin
- frm_req <= '0';
+p_output_stimuli : process
+begin
+ frm_req <= '0';
+ frm_flush <= '0';
+ state <= s_request;
+
+ for I in 1 to c_init_length loop wait until rising_edge(clk); end loop;
+ for I in 1 to c_wait_length * 10 loop wait until rising_edge(clk); end loop;
+
+ while true loop
+ frm_req <= c_frame_request;
frm_flush <= '0';
- state <= s_request;
-
- for I in 1 to c_init_length loop wait until rising_edge(clk); end loop;
- for I in 1 to c_wait_length * 10 loop wait until rising_edge(clk); end loop;
-
- while true loop
- frm_req <= c_frame_request;
- frm_flush <= '0';
- case state is
- when s_request =>
- if frm_ack = '0' then
- frm_req <= '1';
- elsif frm_err = '1' then
- state <= s_err; -- frame with valid data but no sof
- elsif frm_busy = '1' then
- state <= s_eof; -- frame with sof, read rest of frame
- else
- state <= s_request; -- no frame, request again
- end if;
- when s_eof =>
- if frm_done = '1' then
- state <= s_request;
- end if;
- when others => -- s_err
- report "Frame with valid data but no sof" severity WARNING;
+ case state is
+ when s_request =>
+ if frm_ack = '0' then
+ frm_req <= '1';
+ elsif frm_err = '1' then
+ state <= s_err; -- frame with valid data but no sof
+ elsif frm_busy = '1' then
+ state <= s_eof; -- frame with sof, read rest of frame
+ else
+ state <= s_request; -- no frame, request again
+ end if;
+ when s_eof =>
+ if frm_done = '1' then
state <= s_request;
- end case;
- wait until rising_edge(clk);
- end loop;
- end process;
-
- p_verify : process(clk)
- begin
- if rising_edge(clk) then
- if out_val = '1' then
- prev_out_data <= out_data;
- if verify_en = '1' and unsigned(out_data) /= unsigned(prev_out_data) + 1 then
- report "Wrong out_data count" severity ERROR;
end if;
+ when others => -- s_err
+ report "Frame with valid data but no sof" severity WARNING;
+ state <= s_request;
+ end case;
+ wait until rising_edge(clk);
+ end loop;
+end process;
+
+p_verify : process(clk)
+begin
+ if rising_edge(clk) then
+ if out_val = '1' then
+ prev_out_data <= out_data;
+ if verify_en = '1' and unsigned(out_data) /= unsigned(prev_out_data) + 1 then
+ report "Wrong out_data count" severity ERROR;
end if;
end if;
- end process;
+ end if;
+end process;
- -- Check that the test has ran at all
- proc_dp_verify_value(e_at_least, clk, verify_done, exp_data, out_data);
+-- Check that the test has ran at all
+proc_dp_verify_value(e_at_least, clk, verify_done, exp_data, out_data);
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index 3030dbaa28114bd9073add030febfc9be0e991fc..7add28de4b867c6539d5b3cf4a62da2b18879bbf 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packetizing_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packetizing_pkg.all;
entity tb_dp_frame_scheduler is
generic (
@@ -136,15 +136,16 @@ architecture tb of tb_dp_frame_scheduler is
signal expected_fsn_x : natural;
signal expected_fsn_b : natural;
- procedure proc_tx_packet(constant c_packet_size : in natural;
- constant c_sfd : in std_logic_vector;
- constant c_fsn_word : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal out_sof : out std_logic;
- signal out_eof : out std_logic;
- signal out_val : out std_logic;
- signal out_dat : inout std_logic_vector(c_lane_dat_w - 1 downto 0)) is
+ procedure proc_tx_packet(
+ constant c_packet_size : in natural;
+ constant c_sfd : in std_logic_vector;
+ constant c_fsn_word : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal out_sof : out std_logic;
+ signal out_eof : out std_logic;
+ signal out_val : out std_logic;
+ signal out_dat : inout std_logic_vector(c_lane_dat_w - 1 downto 0)) is
begin
out_sof <= '0';
out_eof <= '0';
@@ -177,9 +178,10 @@ architecture tb of tb_dp_frame_scheduler is
end if;
end proc_tx_packet;
- procedure proc_idle(constant c_idle_size : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic) is
+ procedure proc_idle(
+ constant c_idle_size : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic) is
begin
if rst = '1' then
wait until rising_edge(clk);
@@ -190,9 +192,10 @@ architecture tb of tb_dp_frame_scheduler is
end if;
end proc_idle;
- procedure proc_cnt(constant c_max : in natural;
- signal rst : in std_logic;
- signal cnt : inout natural) is
+ procedure proc_cnt(
+ constant c_max : in natural;
+ signal rst : in std_logic;
+ signal cnt : inout natural) is
begin
if rst = '0' then
cnt <= cnt + 1; -- increment packet counter
@@ -244,36 +247,36 @@ begin
begin
-- Send a crosslet packets
proc_tx_packet(c_packet_size_x,
- c_sfd_x,
- fsn_x,
- rst,
- clk,
- lane_tx_xsof,
- lane_tx_xeof,
- lane_tx_xval,
- lane_tx_xdat);
+ c_sfd_x,
+ fsn_x,
+ rst,
+ clk,
+ lane_tx_xsof,
+ lane_tx_xeof,
+ lane_tx_xval,
+ lane_tx_xdat);
proc_cnt(c_fsn_max, rst, fsn_x);
proc_idle(c_idle_size_x - 1, -- min 1 to tx one cycle earlier in every slice
- rst,
- clk);
+ rst,
+ clk);
end process;
p_tx_beamlets : process
begin
-- Send a beamlet packet at start of every slice
proc_tx_packet(c_packet_size_b,
- c_sfd_b,
- fsn_b,
- rst,
- clk,
- lane_tx_bsof,
- lane_tx_beof,
- lane_tx_bval,
- lane_tx_bdat);
+ c_sfd_b,
+ fsn_b,
+ rst,
+ clk,
+ lane_tx_bsof,
+ lane_tx_beof,
+ lane_tx_bval,
+ lane_tx_bdat);
proc_cnt(c_fsn_max, rst, fsn_b);
proc_idle(c_idle_size_b, -- tx at start of every slice
- rst,
- clk);
+ rst,
+ clk);
end process;
------------------------------------------------------------------------------
@@ -287,28 +290,29 @@ begin
gen_scheduler : if g_dut_verify_mux = false generate
dut : entity work.dp_frame_scheduler
- generic map (
- g_dat_w => c_lane_dat_w,
- g_nof_input => c_nof_input,
- g_fifo_rl => c_dut_fifo_rl,
- g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size), -- 1 DOWNTO 0
- g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill) -- 1 DOWNTO 0
- )
- port map (
- rst => rst_dut,
- clk => clk,
- in_dat => scheduler_dat,
- in_val => scheduler_val,
- in_sof => scheduler_sof,
- in_eof => scheduler_eof,
- out_dat => lane_tx_dat,
- out_val => lane_tx_val,
- out_sof => lane_tx_sof,
- out_eof => lane_tx_eof
- );
+ generic map (
+ g_dat_w => c_lane_dat_w,
+ g_nof_input => c_nof_input,
+ g_fifo_rl => c_dut_fifo_rl,
+ g_fifo_size => (c_x_scheduler_size, c_b_scheduler_size), -- 1 DOWNTO 0
+ g_fifo_fill => (c_x_scheduler_fill, c_b_scheduler_fill) -- 1 DOWNTO 0
+ )
+ port map (
+ rst => rst_dut,
+ clk => clk,
+ in_dat => scheduler_dat,
+ in_val => scheduler_val,
+ in_sof => scheduler_sof,
+ in_eof => scheduler_eof,
+ out_dat => lane_tx_dat,
+ out_val => lane_tx_val,
+ out_sof => lane_tx_sof,
+ out_eof => lane_tx_eof
+ );
end generate;
gen_mux : if g_dut_verify_mux = true generate
+
p_scheduler_sosi : process(scheduler_dat, scheduler_val, scheduler_sof, scheduler_eof)
begin
for I in 0 to c_nof_input - 1 loop
@@ -326,29 +330,29 @@ begin
lane_tx_channel <= lane_tx_sosi.channel(c_nof_input_w - 1 downto 0);
dut : entity work.dp_mux
- generic map (
- g_data_w => c_lane_dat_w,
- g_empty_w => 1, -- not used
- g_in_channel_w => 1, -- not used
- g_error_w => 1, -- not used
- g_use_empty => false,
- g_use_in_channel => false,
- g_use_error => false,
- g_nof_input => c_nof_input,
- g_use_fifo => true,
- g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size), -- 0 TO 1
- g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill) -- 0 TO 1
- )
- port map (
- rst => rst_dut,
- clk => clk,
- -- ST sinks
- snk_out_arr => OPEN, -- OUT = request to upstream ST source
- snk_in_arr => scheduler_sosi,
- -- ST source
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
- src_out => lane_tx_sosi
- );
+ generic map (
+ g_data_w => c_lane_dat_w,
+ g_empty_w => 1, -- not used
+ g_in_channel_w => 1, -- not used
+ g_error_w => 1, -- not used
+ g_use_empty => false,
+ g_use_in_channel => false,
+ g_use_error => false,
+ g_nof_input => c_nof_input,
+ g_use_fifo => true,
+ g_fifo_size => (c_b_scheduler_size, c_x_scheduler_size), -- 0 TO 1
+ g_fifo_fill => (c_b_scheduler_fill, c_x_scheduler_fill) -- 0 TO 1
+ )
+ port map (
+ rst => rst_dut,
+ clk => clk,
+ -- ST sinks
+ snk_out_arr => OPEN, -- OUT = request to upstream ST source
+ snk_in_arr => scheduler_sosi,
+ -- ST source
+ src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ src_out => lane_tx_sosi
+ );
end generate;
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
index 45705b5ea188f3ebf05af2bfc14cf766d55a2fb4..3ad5968fef8645ef40c8ffd8803a8d7188632cf9 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
@@ -20,12 +20,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_gap is
end tb_dp_gap;
@@ -118,7 +118,7 @@ begin
wait;
end process;
- -- Generate tx_sosi for DUT using counter data generator
+ -- Generate tx_sosi for DUT using counter data generator
proc_dp_gen_data(c_rl, c_dat_w, c_tx_init, rst, clk, tx_enable, tx_siso, tx_sosi);
-- Enable verification when valid output data is expected, i.e. when prev_data should be /= 'X'
@@ -133,19 +133,19 @@ begin
proc_dp_verify_data("gap_sosi.data", c_rl, clk, verify_en, gap_siso.ready, gap_sosi.valid, gap_sosi.data(c_dat_w - 1 downto 0), prev_data2);
dut : entity work.dp_gap
- generic map (
- g_dat_len => 100,
- g_gap_len => 5,
- g_gap_extend => true
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => tx_siso,
- snk_in => tx_sosi,
-
- src_in => gap_siso,
- src_out => gap_sosi
- );
+ generic map (
+ g_dat_len => 100,
+ g_gap_len => 5,
+ g_gap_extend => true
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => tx_siso,
+ snk_in => tx_sosi,
+
+ src_in => gap_siso,
+ src_out => gap_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
index 901fe867b80e92fcc4a8244fcc5a8b6d714009ea..fd77458e39482647c5e8d97c845558894d25f7cb 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -21,16 +21,16 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
-use common_lib.common_str_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
+ use common_lib.common_str_pkg.all;
entity tb_dp_hdr_insert_remove is
generic (
@@ -52,7 +52,7 @@ architecture tb of tb_dp_hdr_insert_remove is
constant c_nof_repeat : natural := 100;
constant c_bsn_w : natural := 16;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2 ** g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
constant c_channel_init : integer := 0;
constant c_err_init : natural := 0;
constant c_sync_period : natural := 7;
@@ -85,9 +85,9 @@ architecture tb of tb_dp_hdr_insert_remove is
signal prev_out_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := (others => '1'); -- = -1
signal prev_out_channel : std_logic_vector(c_dp_stream_channel_w - 1 downto 0) := TO_SVEC(c_channel_init - 1, c_dp_stream_channel_w);
signal prev_out_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0) := TO_SVEC(c_err_init - 1, c_dp_stream_error_w);
--- SIGNAL expected_out_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
--- SIGNAL expected_out_channel : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);
--- SIGNAL expected_out_err : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_channel : STD_LOGIC_VECTOR(c_dp_stream_channel_w-1 DOWNTO 0);
+ -- SIGNAL expected_out_err : STD_LOGIC_VECTOR(c_dp_stream_error_w-1 DOWNTO 0);
-- tb dut
signal in_siso : t_dp_siso;
@@ -157,11 +157,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -209,9 +209,9 @@ begin
end loop;
-- End of stimuli
--- expected_out_bsn <= INCR_UVEC(v_bsn, -1);
--- expected_out_channel <= TO_UVEC(v_channel-1, c_dp_stream_channel_w);
--- expected_out_err <= TO_UVEC(v_err-1, c_dp_stream_error_w);
+ -- expected_out_bsn <= INCR_UVEC(v_bsn, -1);
+ -- expected_out_channel <= TO_UVEC(v_channel-1, c_dp_stream_channel_w);
+ -- expected_out_err <= TO_UVEC(v_err-1, c_dp_stream_error_w);
proc_common_wait_some_cycles(st_clk, 50); -- depends on stream control
verify_done <= '1';
@@ -249,50 +249,50 @@ begin
-- DUT
------------------------------------------------------------------------------
u_hdr_insert : entity work.dp_hdr_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => c_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- ram_mosi => ram_hdr_mosi,
- reg_mosi => reg_hdr_mosi,
-
- snk_out => in_siso,
- snk_in => in_sosi,
-
- src_in => hdr_siso,
- src_out => hdr_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => c_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ ram_mosi => ram_hdr_mosi,
+ reg_mosi => reg_hdr_mosi,
+
+ snk_out => in_siso,
+ snk_in => in_sosi,
+
+ src_in => hdr_siso,
+ src_out => hdr_sosi
+ );
u_hdr_remove : entity work.dp_hdr_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_nof_words => c_hdr_nof_words
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- st_rst => st_rst,
- st_clk => st_clk,
-
- snk_out => hdr_siso,
- snk_in => hdr_sosi,
-
- sla_in => ram_hdr_mosi,
- sla_out => hdr_data_miso,
-
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_nof_words => c_hdr_nof_words
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => st_rst,
+ st_clk => st_clk,
+
+ snk_out => hdr_siso,
+ snk_in => hdr_sosi,
+
+ sla_in => ram_hdr_mosi,
+ sla_out => hdr_data_miso,
+
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
index cb7c1b30aed2a2c3b3e7c93429b7e97b91369b95..23c7b71027dd29857137944275d9a69e7cb6bfaa 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_latency_adapter is
end tb_dp_latency_adapter;
@@ -211,20 +211,20 @@ begin
gen_chain : for I in 0 to c_nof_dut - 1 generate
dut : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_dut_latency(I - 1),
- g_out_latency => c_dut_latency(I)
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => dut_siso(I - 1),
- snk_in => dut_sosi(I - 1),
- -- ST source
- src_in => dut_siso(I),
- src_out => dut_sosi(I)
- );
+ generic map (
+ g_in_latency => c_dut_latency(I - 1),
+ g_out_latency => c_dut_latency(I)
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => dut_siso(I - 1),
+ snk_in => dut_sosi(I - 1),
+ -- ST source
+ src_in => dut_siso(I),
+ src_out => dut_sosi(I)
+ );
end generate;
-- map record to sl, slv
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
index a0a272ebb63ad809adc286fd1c76455cac57acf7..16212c450e17ed8b855ef16adbc1f1ccecd107c1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: Verify dp_latency_fifo
-- Description:
@@ -65,7 +65,7 @@ architecture tb of tb_dp_latency_fifo is
constant c_symbol_w : natural := 8;
constant c_data_w : natural := g_nof_symbols_per_data * c_symbol_w;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**c_symbol_w; -- used to avoid TO_UVEC warning for smaller c_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2 ** c_symbol_w; -- used to avoid TO_UVEC warning for smaller c_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
-- tb default
signal tb_end : std_logic := '0';
@@ -127,11 +127,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -193,37 +193,37 @@ begin
------------------------------------------------------------------------------
dut : entity work.dp_latency_fifo
- generic map (
- g_bypass => g_bypass,
- g_input_rl => g_input_rl, -- input ready latency
- g_output_rl => g_output_rl, -- output ready latency
- g_fifo_size => g_fifo_size
- )
- port map (
- rst => rst,
- clk => clk,
- -- Monitor FIFO filling
- usedw => fifo_usedw,
- wr_ful => fifo_ful,
- rd_emp => fifo_emp,
- -- ST sink
- snk_in => in_sosi,
- snk_out => in_siso,
- -- ST source
- src_out => out_sosi,
- src_in => out_siso
+ generic map (
+ g_bypass => g_bypass,
+ g_input_rl => g_input_rl, -- input ready latency
+ g_output_rl => g_output_rl, -- output ready latency
+ g_fifo_size => g_fifo_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Monitor FIFO filling
+ usedw => fifo_usedw,
+ wr_ful => fifo_ful,
+ rd_emp => fifo_emp,
+ -- ST sink
+ snk_in => in_sosi,
+ snk_out => in_siso,
+ -- ST source
+ src_out => out_sosi,
+ src_in => out_siso
);
- -- Map to slv to ease monitoring in wave window
- in_data <= in_sosi.data(c_data_w - 1 downto 0);
- in_val <= in_sosi.valid;
- in_sop <= in_sosi.sop;
- in_eop <= in_sosi.eop;
- in_sync <= in_sosi.sync;
-
- out_data <= out_sosi.data(c_data_w - 1 downto 0);
- out_val <= out_sosi.valid;
- out_sop <= out_sosi.sop;
- out_eop <= out_sosi.eop;
- out_sync <= out_sosi.sync;
+-- Map to slv to ease monitoring in wave window
+in_data <= in_sosi.data(c_data_w - 1 downto 0);
+in_val <= in_sosi.valid;
+in_sop <= in_sosi.sop;
+in_eop <= in_sosi.eop;
+in_sync <= in_sosi.sync;
+
+out_data <= out_sosi.data(c_data_w - 1 downto 0);
+out_val <= out_sosi.valid;
+out_sop <= out_sosi.sop;
+out_eop <= out_sosi.eop;
+out_sync <= out_sosi.sync;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
index bc34fa7cc535d23e5712b149b74f831293305c4d..eaf14059dfa64d1fbe17b6a874ca41ea41acfbd0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_mux is
generic (
@@ -184,13 +184,13 @@ begin
out_data(I) <= mux_data;
out_empty(I) <= mux_empty;
out_val(I) <= mux_val when c_dut_nof_input_w = 0 else -- avoid Warning: NUMERIC_STD.TO_INTEGER: null detected, returning 0
- mux_val when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
+ mux_val when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
out_sync(I) <= mux_sync when c_dut_nof_input_w = 0 else
- mux_sync when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
+ mux_sync when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
out_sop(I) <= mux_sop when c_dut_nof_input_w = 0 else
- mux_sop when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
+ mux_sop when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
out_eop(I) <= mux_eop when c_dut_nof_input_w = 0 else
- mux_eop when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
+ mux_eop when TO_UINT(mux_channel(c_dut_nof_input_w - 1 downto 0)) = I else '0';
-- Output verify
proc_dp_verify_en(c_verify_en_wait, rst, clk, sync, verify_en);
@@ -258,31 +258,31 @@ begin
end process;
dut : entity work.dp_mux
- generic map (
- g_data_w => c_dp_data_w,
- g_empty_w => c_dp_empty_w,
- g_in_channel_w => c_dut_in_channel_w,
- g_error_w => 1,
- g_use_empty => g_dut_use_empty,
- g_use_in_channel => g_dut_use_in_channel,
- g_use_error => false,
- g_use_sync => g_dut_use_sync,
- g_mode => g_mode,
- g_nof_input => g_dut_nof_input,
- g_use_fifo => g_dut_use_fifo,
- g_fifo_size => g_dut_fifo_size,
- g_fifo_fill => g_dut_fifo_fill
- )
- port map (
- rst => rst,
- clk => clk,
- -- Control
- sel_ctrl => sel_ctrl,
- -- ST sinks
- snk_out_arr => in_siso, -- OUT = request to upstream ST source
- snk_in_arr => in_sosi,
- -- ST source
- src_in => mux_siso, -- IN = request from downstream ST sink
- src_out => mux_sosi
- );
+ generic map (
+ g_data_w => c_dp_data_w,
+ g_empty_w => c_dp_empty_w,
+ g_in_channel_w => c_dut_in_channel_w,
+ g_error_w => 1,
+ g_use_empty => g_dut_use_empty,
+ g_use_in_channel => g_dut_use_in_channel,
+ g_use_error => false,
+ g_use_sync => g_dut_use_sync,
+ g_mode => g_mode,
+ g_nof_input => g_dut_nof_input,
+ g_use_fifo => g_dut_use_fifo,
+ g_fifo_size => g_dut_fifo_size,
+ g_fifo_fill => g_dut_fifo_fill
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Control
+ sel_ctrl => sel_ctrl,
+ -- ST sinks
+ snk_out_arr => in_siso, -- OUT = request to upstream ST source
+ snk_in_arr => in_sosi,
+ -- ST source
+ src_in => mux_siso, -- IN = request from downstream ST sink
+ src_out => mux_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 4cca345bbd35100172c94b8936b40d15d0071eff..3bd7570c4aa31e32534da6e9b2c6d0589a703d82 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -36,16 +36,16 @@
-- . signal tb_end will stop the simulation by stopping the clk
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_offload_rx_filter is
end tb_dp_offload_rx_filter;
@@ -67,35 +67,36 @@ architecture tb of tb_dp_offload_rx_filter is
constant c_nof_packets : natural := 5;
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1;
- constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
- ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
- ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
- ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
- ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
- ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
- ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
- ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
- ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
- ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
+ constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := (
+ ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
+ ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
----------------------------------------------------------------------------
-- Clocks and resets
@@ -167,45 +168,45 @@ begin
p_special_stimuli : process(in_sosi.sop)
begin
- if in_sosi.sop = '1' then
- counter <= counter + 1;
- if toggle then
- hdr_fields_out_arr <= hdr_fields_in_arr;
- else
- hdr_fields_out_arr <= hdr_fields_wrong_arr;
- end if;
- toggle <= not toggle;
+ if in_sosi.sop = '1' then
+ counter <= counter + 1;
+ if toggle then
+ hdr_fields_out_arr <= hdr_fields_in_arr;
+ else
+ hdr_fields_out_arr <= hdr_fields_wrong_arr;
+ end if;
+ toggle <= not toggle;
else
- hdr_fields_out_arr <= hdr_fields_rst;
+ hdr_fields_out_arr <= hdr_fields_rst;
end if;
- if c_nof_packets + 1 <= counter then
- tb_end <= '1';
+ if c_nof_packets + 1 <= counter then
+ tb_end <= '1';
end if;
end process;
dut : entity work.dp_offload_rx_filter
- generic map(
- g_nof_streams => c_nof_streams, -- : POSITIVE;
- g_data_w => c_data_w, -- : NATURAL;
- g_hdr_field_arr => c_hdr_field_arr, -- : t_common_field_arr;
- g_eth_dst_mac_ena => true, -- : BOOLEAN;
- g_ip_dst_addr_ena => true, -- : BOOLEAN;
- g_ip_total_length_ena => true, -- : BOOLEAN;
- g_udp_dst_port_ena => true -- : BOOLEAN
- )
- port map(
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_in_arr => snk_in_arr,
- snk_out_arr => snk_out_arr,
-
- src_out_arr => src_out_arr,
- src_in_arr => src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr,
- hdr_fields_in_arr => hdr_fields_in_arr
- );
+ generic map(
+ g_nof_streams => c_nof_streams, -- : POSITIVE;
+ g_data_w => c_data_w, -- : NATURAL;
+ g_hdr_field_arr => c_hdr_field_arr, -- : t_common_field_arr;
+ g_eth_dst_mac_ena => true, -- : BOOLEAN;
+ g_ip_dst_addr_ena => true, -- : BOOLEAN;
+ g_ip_total_length_ena => true, -- : BOOLEAN;
+ g_udp_dst_port_ena => true -- : BOOLEAN
+ )
+ port map(
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_in_arr => snk_in_arr,
+ snk_out_arr => snk_out_arr,
+
+ src_out_arr => src_out_arr,
+ src_in_arr => src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr,
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index 41811773fe9a84b049f0d11b505e6d614e1f287b..a63bf44549bf48852fb6dee413f60bf3aba8d7bd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -53,17 +53,17 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_field_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_field_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_offload_tx_v3 is
generic (
@@ -92,8 +92,8 @@ architecture tb of tb_dp_offload_tx_v3 is
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w;
constant c_nof_symbols_per_bsn : natural := c_dp_stream_bsn_w / g_symbol_w; -- = 64 / g_symbol_w
constant c_bsn_w : natural := sel_a_b(c_nof_symbols_per_data = 1,
- g_symbol_w * c_nof_symbols_per_bsn,
- g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
+ g_symbol_w * c_nof_symbols_per_bsn,
+ g_symbol_w * (c_nof_symbols_per_bsn - g_empty));
constant c_use_shortened_header : boolean := c_bsn_w <= c_word_w;
-- dp_stream_stimuli
@@ -135,141 +135,141 @@ architecture tb of tb_dp_offload_tx_v3 is
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . udp_total_length = 176 beamlets * 64b / 8b = 1408B + 14 DP bytes + 8 UDP bytes = 1430B
constant c_udp_offload_hdr_field_arr : t_common_field_arr(c_udp_offload_nof_hdr_fields - 1 downto 0) := ( -- index
- ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
- ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
+ ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B214368AC") ), -- 21
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(x"0123456789AB") ), -- 20
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), -- 19
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- 18
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), -- 17
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), -- 16
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1450) ), -- 15
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), -- 14
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), -- 13
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), -- 12
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), -- 11
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), -- 10
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(29928) ), -- 9
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(x"C0A80009") ), -- 8
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- 7
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), -- 6
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), -- 5
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1430) ), -- 4
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), -- 3
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(x"010203040506") ), -- 2
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ), -- 1
+ ( field_name_pad("dp_bsn" ), "RW", c_bsn_w, field_default(0) ) ); -- 0
-- TX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
-- . Note: It appears that the tx_hdr_word read values are the MM write values, so read of value from logic fields (with MM override '0', e.g. dp_bsn, eth_src_mac) is not supported.
constant c_expected_tx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000000", -- 2 = dp_sync
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
+ X"00000000", -- 0 = dp_bsn[31:0] -- readback is MM value, not the logic value
+ X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000000", -- 2 = dp_sync
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port -- readback is MM value, not the logic value
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"456789AB", -- 22 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"00000123", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
constant c_expected_tx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
- X"00000000", -- 1 = dp_sync
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
- X"00000123", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ X"00000000", -- 0 = dp_bsn[c_bsn_w-1:0] -- readback is MM value, not the logic value
+ X"00000000", -- 1 = dp_sync
+ X"03040506", -- 2 = dp_reserved[31:0]
+ X"00000102", -- 3 = dp_reserved[47:32]
+ X"00000000", -- 4 = udp_checksum
+ X"00000596", -- 5 = udp_total_length
+ X"00000000", -- 6 = udp_dst_port
+ X"00000000", -- 7 = udp_src_port -- readback is MM value, not the logic value
+ X"C0A80001", -- 8 = ip_dst_addr
+ X"C0A80009", -- 9 = ip_src_addr
+ X"000074E8", -- 10 = ip_header_checksum
+ X"00000011", -- 11 = ip_protocol
+ X"0000007F", -- 12 = ip_time_to_live
+ X"00000000", -- 13 = ip_fragment_offset
+ X"00000002", -- 14 = ip_flags
+ X"00000000", -- 15 = ip_identification
+ X"000005AA", -- 16 = ip_total_length
+ X"00000000", -- 17 = ip_services
+ X"00000005", -- 18 = ip_header_length
+ X"00000004", -- 19 = ip_version
+ X"00000800", -- 20 = eth_type[15:0]
+ X"456789AB", -- 21 = eth_src_mac[31:0] -- readback is MM value, not the logic value
+ X"00000123", -- 22 = eth_src_mac[47:32]
+ X"214368AC", -- 23 = eth_dst_mac[31:0]
+ X"0000001B"); -- 24 = eth_dst_mac[47:32]
-- RX: Corresponding storage of c_udp_offload_hdr_field_arr in MM register words
constant c_expected_rx_hdr_word_arr_default : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_default - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
- X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
- X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 3 = dp_reserved[31:0]
- X"00000102", -- 4 = dp_reserved[47:32]
- X"00000000", -- 5 = udp_checksum
- X"00000596", -- 6 = udp_total_length
- X"00000000", -- 7 = udp_dst_port
- X"00000000", -- 8 = udp_src_port
- X"C0A80001", -- 9 = ip_dst_addr
- X"C0A80009", -- 10 = ip_src_addr
- X"000074E8", -- 11 = ip_header_checksum
- X"00000011", -- 12 = ip_protocol
- X"0000007F", -- 13 = ip_time_to_live
- X"00000000", -- 14 = ip_fragment_offset
- X"00000002", -- 15 = ip_flags
- X"00000000", -- 16 = ip_identification
- X"000005AA", -- 17 = ip_total_length
- X"00000000", -- 18 = ip_services
- X"00000005", -- 19 = ip_header_length
- X"00000004", -- 20 = ip_version
- X"00000800", -- 21 = eth_type[15:0]
- X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 23 = eth_src_mac[47:32]
- X"214368AC", -- 24 = eth_dst_mac[31:0]
- X"0000001B"); -- 25 = eth_dst_mac[47:32]
+ X"00000002", -- 0 = dp_bsn[31:0] -- dynamic value obtained from simulation
+ X"00000000", -- 1 = dp_bsn[c_bsn_w-1:32]
+ X"00000001", -- 2 = dp_sync -- dynamic value obtained from simulation
+ X"03040506", -- 3 = dp_reserved[31:0]
+ X"00000102", -- 4 = dp_reserved[47:32]
+ X"00000000", -- 5 = udp_checksum
+ X"00000596", -- 6 = udp_total_length
+ X"00000000", -- 7 = udp_dst_port
+ X"00000000", -- 8 = udp_src_port
+ X"C0A80001", -- 9 = ip_dst_addr
+ X"C0A80009", -- 10 = ip_src_addr
+ X"000074E8", -- 11 = ip_header_checksum
+ X"00000011", -- 12 = ip_protocol
+ X"0000007F", -- 13 = ip_time_to_live
+ X"00000000", -- 14 = ip_fragment_offset
+ X"00000002", -- 15 = ip_flags
+ X"00000000", -- 16 = ip_identification
+ X"000005AA", -- 17 = ip_total_length
+ X"00000000", -- 18 = ip_services
+ X"00000005", -- 19 = ip_header_length
+ X"00000004", -- 20 = ip_version
+ X"00000800", -- 21 = eth_type[15:0]
+ X"86080000", -- 22 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"00000022", -- 23 = eth_src_mac[47:32]
+ X"214368AC", -- 24 = eth_dst_mac[31:0]
+ X"0000001B"); -- 25 = eth_dst_mac[47:32]
constant c_expected_rx_hdr_word_arr_shortened : t_slv_32_arr(0 to c_udp_offload_nof_hdr_words_shortened - 1) := ( -- word address
- X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
- X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
- X"03040506", -- 2 = dp_reserved[31:0]
- X"00000102", -- 3 = dp_reserved[47:32]
- X"00000000", -- 4 = udp_checksum
- X"00000596", -- 5 = udp_total_length
- X"00000000", -- 6 = udp_dst_port
- X"00000000", -- 7 = udp_src_port
- X"C0A80001", -- 8 = ip_dst_addr
- X"C0A80009", -- 9 = ip_src_addr
- X"000074E8", -- 10 = ip_header_checksum
- X"00000011", -- 11 = ip_protocol
- X"0000007F", -- 12 = ip_time_to_live
- X"00000000", -- 13 = ip_fragment_offset
- X"00000002", -- 14 = ip_flags
- X"00000000", -- 15 = ip_identification
- X"000005AA", -- 16 = ip_total_length
- X"00000000", -- 17 = ip_services
- X"00000005", -- 18 = ip_header_length
- X"00000004", -- 19 = ip_version
- X"00000800", -- 20 = eth_type[15:0]
- X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
- X"00000022", -- 22 = eth_src_mac[47:32]
- X"214368AC", -- 23 = eth_dst_mac[31:0]
- X"0000001B"); -- 24 = eth_dst_mac[47:32]
+ X"00000002", -- 0 = dp_bsn[c_bsn_w-1:0] -- dynamic value obtained from simulation
+ X"00000001", -- 1 = dp_sync -- dynamic value obtained from simulation
+ X"03040506", -- 2 = dp_reserved[31:0]
+ X"00000102", -- 3 = dp_reserved[47:32]
+ X"00000000", -- 4 = udp_checksum
+ X"00000596", -- 5 = udp_total_length
+ X"00000000", -- 6 = udp_dst_port
+ X"00000000", -- 7 = udp_src_port
+ X"C0A80001", -- 8 = ip_dst_addr
+ X"C0A80009", -- 9 = ip_src_addr
+ X"000074E8", -- 10 = ip_header_checksum
+ X"00000011", -- 11 = ip_protocol
+ X"0000007F", -- 12 = ip_time_to_live
+ X"00000000", -- 13 = ip_fragment_offset
+ X"00000002", -- 14 = ip_flags
+ X"00000000", -- 15 = ip_identification
+ X"000005AA", -- 16 = ip_total_length
+ X"00000000", -- 17 = ip_services
+ X"00000005", -- 18 = ip_header_length
+ X"00000004", -- 19 = ip_version
+ X"00000800", -- 20 = eth_type[15:0]
+ X"86080000", -- 21 = eth_src_mac[31:0] -- readback is the logic value x"00228608" & id_backplane = 0 & id_chip = 0 (c_NODE_ID = 0)
+ X"00000022", -- 22 = eth_src_mac[47:32]
+ X"214368AC", -- 23 = eth_dst_mac[31:0]
+ X"0000001B"); -- 24 = eth_dst_mac[47:32]
-- From apertif_unb1_fn_beamformer_udp_offload.vhd: 221 111111111000 0000 000
-- Override ('1') only the Ethernet fields so we can use MM defaults there. 109 876543210987 6543 210
@@ -353,38 +353,38 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- -- specific
- g_in_dat_w => g_data_w,
- g_nof_repeat => c_nof_packets,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_wait_last_evt
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_nof_repeat => c_nof_packets,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_wait_last_evt
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -418,37 +418,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_data_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_data_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT offload Tx
@@ -458,23 +458,23 @@ begin
-- Use FIFO to mimic apertif_unb1_fn_beamformer_udp_offload.vhd, without FIFO dp_stream_stimuli
-- would handle the back pressure
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_data_w,
- g_bsn_w => 64,
- g_use_sync => true,
- g_use_bsn => true,
- g_fifo_size => 1024
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => OPEN, -- stimuli_src_in
- snk_in => stimuli_src_out,
-
- src_in => dp_fifo_sc_src_in,
- src_out => dp_fifo_sc_src_out
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_bsn_w => 64,
+ g_use_sync => true,
+ g_use_bsn => true,
+ g_fifo_size => 1024
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => OPEN, -- stimuli_src_in
+ snk_in => stimuli_src_out,
+
+ src_in => dp_fifo_sc_src_in,
+ src_out => dp_fifo_sc_src_out
+ );
dp_offload_tx_snk_in_arr(0) <= dp_fifo_sc_src_out;
dp_fifo_sc_src_in <= dp_offload_tx_snk_out_arr(0);
@@ -493,32 +493,32 @@ begin
tx_hdr_fields_in_arr(0)(field_hi(c_udp_offload_hdr_field_arr, "dp_bsn" ) downto field_lo(c_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(0).bsn(c_bsn_w - 1 downto 0);
u_tx : entity work.dp_offload_tx_v3
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_ovr_init
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_tx_snk_in_arr,
- snk_out_arr => dp_offload_tx_snk_out_arr,
-
- src_out_arr => tx_offload_sosi_arr,
- src_in_arr => tx_offload_siso_arr,
-
- hdr_fields_in_arr => tx_hdr_fields_in_arr,
- hdr_fields_out_arr => tx_hdr_fields_out_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => tx_offload_sosi_arr,
+ src_in_arr => tx_offload_siso_arr,
+
+ hdr_fields_in_arr => tx_hdr_fields_in_arr,
+ hdr_fields_out_arr => tx_hdr_fields_out_arr
+ );
p_rd_tx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
@@ -575,33 +575,33 @@ begin
------------------------------------------------------------------------------
u_rx : entity work.dp_offload_rx
- generic map (
- g_nof_streams => 1,
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_hdr_field_arr => c_udp_offload_hdr_field_arr,
- g_remove_crc => false,
- g_crc_nof_words => 0
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => link_offload_sosi_arr,
- snk_out_arr => link_offload_siso_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => rx_hdr_fields_out_arr,
- hdr_fields_raw_arr => rx_hdr_fields_raw_arr
- );
+ generic map (
+ g_nof_streams => 1,
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_hdr_field_arr => c_udp_offload_hdr_field_arr,
+ g_remove_crc => false,
+ g_crc_nof_words => 0
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => link_offload_sosi_arr,
+ snk_out_arr => link_offload_siso_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => rx_hdr_fields_out_arr,
+ hdr_fields_raw_arr => rx_hdr_fields_raw_arr
+ );
p_restore_sync_bsn : process(dp_offload_rx_src_out_arr, rx_hdr_fields_out_arr)
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index f0d5e7bde9cc567b2d583ebaf038e3f8adf32b95..1d4c99b807527a2e3b9a2baff4369b87aff20d7c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -27,13 +27,13 @@
-- > run -all -- signal tb_end will stop the simulation by stopping the clk
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packet is
generic (
@@ -48,26 +48,26 @@ architecture tb of tb_dp_packet is
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_data_mod : integer := 2**c_data_w; -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_data_mod : integer := 2 ** c_data_w; -- used to avoid TO_UVEC warning for smaller g_data_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0877665544332211";
constant c_err_init : natural := 247;
constant c_err_w : integer := sel_a_b(c_dp_stream_error_w < 30, c_dp_stream_error_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_err_mod : integer := 2**c_err_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_error_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_err_mod : integer := 2 ** c_err_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_error_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
constant c_channel_init : integer := 0; -- fixed
constant c_channel_w : integer := sel_a_b(c_dp_stream_channel_w < 30, c_dp_stream_channel_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
- constant c_channel_mod : integer := 2**c_channel_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_channel_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_channel_mod : integer := 2 ** c_channel_w; -- used to avoid TO_UVEC warning for smaller c_dp_stream_channel_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
constant c_sync_period_w : natural := 3;
- constant c_sync_period : natural := 2**c_sync_period_w;
+ constant c_sync_period : natural := 2 ** c_sync_period_w;
constant c_sync_offset : natural := 4;
-- Default use these:
constant c_nof_ch : natural := 10;
constant c_len_arr : t_natural_arr(0 to c_nof_ch - 1) := (1, 1, 1, 2, 3, 5, 10, 17, 32, 100);
-- Use these to verify the entire channel field width.
--- CONSTANT c_nof_ch : NATURAL := c_channel_mod + 10;
--- CONSTANT c_len_arr : t_natural_arr(0 TO c_nof_ch-1) := array_init(1, c_nof_ch, 0);
+ -- CONSTANT c_nof_ch : NATURAL := c_channel_mod + 10;
+ -- CONSTANT c_len_arr : t_natural_arr(0 TO c_nof_ch-1) := array_init(1, c_nof_ch, 0);
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
@@ -143,11 +143,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
rx_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -241,22 +241,23 @@ begin
-- Encode the data block to a DP packet
u_dp_packet_enc : entity work.dp_packet_enc
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => enc_siso,
- src_out => enc_sosi
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => enc_siso,
+ src_out => enc_sosi
+ );
-- Restrict to link g_data_w
enc_siso <= pkt_siso;
+
p_link : process(enc_sosi)
begin
pkt_sosi <= enc_sosi;
@@ -276,19 +277,19 @@ begin
-- Decode the DP packet into a data block
u_dp_packet_dec : entity work.dp_packet_dec
- generic map (
- g_data_w => g_data_w
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sinks
- snk_out => pkt_siso,
- snk_in => pkt_sosi,
- -- ST source
- src_in => rx_siso,
- src_out => rx_sosi
- );
+ generic map (
+ g_data_w => g_data_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sinks
+ snk_out => pkt_siso,
+ snk_in => pkt_sosi,
+ -- ST source
+ src_in => rx_siso,
+ src_out => rx_sosi
+ );
-- Map to slv to ease monitoring in wave window
rx_data <= rx_sosi.data(rx_data'range);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 42624ba3ea0b2b1778240d19a80e9e19e62df7b4..ec33a8410990105afa0f86cbe2bba2d56083f718 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -47,13 +47,13 @@
-- . Add tb_tb_dp_packet_merge to the DP lib regression testbench tb_tb_tb_backpressure.vhd
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packet_merge is
generic (
@@ -157,11 +157,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -259,12 +259,14 @@ begin
proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap,32), clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
end generate;
end generate;
+
proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap,32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
-- Verify that the output bsn error bit is set if an input block was missed in a merge
merged_pkt_err <= verify_snk_in.err(c_bsn_err_bi);
gen_verify_bsn_err : if g_verify_bsn_err = true generate
+
p_verify_bsn_err : process(clk)
begin
if rising_edge(clk) then
@@ -299,24 +301,24 @@ begin
-- Merge every g_nof_pkt incomming packets into output packets
u_dp_packet_merge : entity work.dp_packet_merge
- generic map (
- g_use_ready => c_use_ready,
- g_pipeline_ready => g_pipeline_ready,
- g_nof_pkt => g_nof_pkt,
- g_align_at_sync => g_align_at_sync,
- g_bsn_increment => g_bsn_increment,
- g_bsn_err_bi => c_bsn_err_bi
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => dp_packet_merge_snk_out,
- snk_in => dp_packet_merge_snk_in,
-
- src_in => dp_packet_merge_src_in,
- src_out => dp_packet_merge_src_out
- );
+ generic map (
+ g_use_ready => c_use_ready,
+ g_pipeline_ready => g_pipeline_ready,
+ g_nof_pkt => g_nof_pkt,
+ g_align_at_sync => g_align_at_sync,
+ g_bsn_increment => g_bsn_increment,
+ g_bsn_err_bi => c_bsn_err_bi
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => dp_packet_merge_snk_out,
+ snk_in => dp_packet_merge_snk_in,
+
+ src_in => dp_packet_merge_src_in,
+ src_out => dp_packet_merge_src_out
+ );
------------------------------------------------------------------------------
-- Optional reverse DUT dp_packet_unmerge
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
index 275d85700bd6a50eeeca057f5a52634eff691b37..38d3a25ff398d5924298b7a893a5d7ec20695982 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
@@ -54,13 +54,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packet_merge_unmerge is
generic (
@@ -97,13 +97,13 @@ architecture tb of tb_dp_packet_merge_unmerge is
constant c_data_init : integer := -1;
constant c_bsn_init : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := X"0000000000000000";
- -- X"0877665544332211"
+ -- X"0877665544332211"
constant c_bsn_increment_max : natural := (g_bsn_increment + 1) * g_nof_pkt_merge; -- +1 to ensure max > 0
constant c_bsn_increment_w : natural := ceil_log2(c_bsn_increment_max + 1);
constant c_unsigned_bsn_increment : unsigned(c_bsn_increment_w - 1 downto 0) :=
- to_unsigned(g_bsn_increment, c_bsn_increment_w);
+ to_unsigned(g_bsn_increment, c_bsn_increment_w);
constant c_unsigned_bsn_pkt_merge : unsigned(c_bsn_increment_w - 1 downto 0) :=
- to_unsigned(g_nof_pkt_merge, c_bsn_increment_w);
+ to_unsigned(g_nof_pkt_merge, c_bsn_increment_w);
constant c_nof_pkt_not_zero : natural := sel_a_b(g_nof_pkt_merge = 0, 1, g_nof_pkt_merge);
constant c_nof_merged_sop : natural := sel_a_b(g_nof_pkt_merge = 0, 0, ceil_div(g_nof_repeat, c_nof_pkt_not_zero));
@@ -169,11 +169,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -205,8 +205,8 @@ begin
-- Send packet
proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), g_pkt_len_merge,
- c_channel, c_err, v_sosi.sync, v_sosi.bsn,
- clk, stimuli_en, stimuli_src_in, stimuli_src_out);
+ c_channel, c_err, v_sosi.sync, v_sosi.bsn,
+ clk, stimuli_en, stimuli_src_in, stimuli_src_out);
-- Insert optional gap between the packets
proc_common_wait_some_cycles(clk, g_pkt_gap);
@@ -253,18 +253,19 @@ begin
-- Verify that the output is incrementing data, like the input stimuli
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1,
- clk, verify_en_valid, verify_snk_out.ready,
- verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
+ clk, verify_en_valid, verify_snk_out.ready,
+ verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
-- Verify that the output is incrementing BSN, like the input stimuli
gen_verify_bsn_increment : if g_nof_pkt_merge = c_nof_pkt_unmerge generate
-- If number of packets stays the same, then unmerge bsn will increment
-- as stimuli bsn by c_unsigned_bsn_increment = g_bsn_increment
proc_dp_verify_data("verify_snk_in.bsn increment", c_rl,
- c_unsigned_0, c_unsigned_bsn_increment,
- clk, verify_en_sop, verify_snk_out.ready,
- verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
+ c_unsigned_0, c_unsigned_bsn_increment,
+ clk, verify_en_sop, verify_snk_out.ready,
+ verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
end generate;
+
gen_verify_bsn_pkt_unmerge : if g_nof_pkt_merge /= c_nof_pkt_unmerge generate
-- If number of packets differs after unmerge, then use
-- c_bsn_increment_unmerge = 0 to not increment bsn during ummerge of
@@ -272,9 +273,9 @@ begin
-- packets is passed on into each of the unmerged packets, this is
-- covered by c_unsigned_bsn_pkt_merge.
proc_dp_verify_data("verify_snk_in.bsn pkt_unmerge", c_rl,
- c_unsigned_0, c_unsigned_0, c_unsigned_bsn_pkt_merge,
- clk, verify_en_sop, verify_snk_out.ready,
- verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
+ c_unsigned_0, c_unsigned_0, c_unsigned_bsn_pkt_merge,
+ clk, verify_en_sop, verify_snk_out.ready,
+ verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
end generate;
-- Verify output packet ctrl
@@ -294,17 +295,17 @@ begin
-- Verify that output channel yields index of unmerged packet, in range(c_nof_pkt_unmerge)
assert unsigned(verify_snk_in.channel) = exp_channel
report "Wrong unmerged verify_snk_in.channel"
- severity ERROR;
+ severity ERROR;
-- Verify that output error is same per c_nof_pkt_unmerge unmerged packets
assert unsigned(verify_snk_in.err) = exp_error
report "Wrong unmerged verify_snk_in.err"
- severity ERROR;
+ severity ERROR;
-- Verify that output empty is same per c_nof_pkt_unmerge unmerged packets
assert unsigned(verify_snk_in.empty) = exp_empty
report "Wrong unmerged verify_snk_in.empty"
- severity ERROR;
+ severity ERROR;
end if;
end if;
end process;
@@ -315,22 +316,22 @@ begin
-- Merge every g_nof_pkt_merge incomming packets into output packets
u_dp_packet_merge : entity work.dp_packet_merge
- generic map (
- g_nof_pkt => g_nof_pkt_merge,
- g_align_at_sync => false, -- not used in this tb
- g_bsn_increment => g_bsn_increment,
- g_bsn_err_bi => 0 -- not used in this tb
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
-
- src_in => dp_packet_merge_snk_in,
- src_out => dp_packet_merge_src_out
- );
+ generic map (
+ g_nof_pkt => g_nof_pkt_merge,
+ g_align_at_sync => false, -- not used in this tb
+ g_bsn_increment => g_bsn_increment,
+ g_bsn_err_bi => 0 -- not used in this tb
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+
+ src_in => dp_packet_merge_snk_in,
+ src_out => dp_packet_merge_src_out
+ );
dp_packet_merge_snk_in <= dp_packet_merge_siso;
@@ -370,23 +371,23 @@ begin
-- Optional reverse DUT dp_packet_unmerge
------------------------------------------------------------------------------
u_dp_packet_unmerge : entity work.dp_packet_unmerge
- generic map (
- g_use_ready => c_use_ready,
- g_pipeline_ready => g_pipeline_ready,
- g_nof_pkt => c_nof_pkt_unmerge,
- g_pkt_len => g_pkt_len_unmerge,
- g_bsn_increment => c_bsn_increment_unmerge
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => dp_packet_merge_siso,
- snk_in => dp_packet_merge_sosi,
-
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_use_ready => c_use_ready,
+ g_pipeline_ready => g_pipeline_ready,
+ g_nof_pkt => c_nof_pkt_unmerge,
+ g_pkt_len => g_pkt_len_unmerge,
+ g_bsn_increment => c_bsn_increment_unmerge
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => dp_packet_merge_siso,
+ snk_in => dp_packet_merge_sosi,
+
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
-- Map to slv to ease monitoring in wave window
stimuli_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
index 7046fe0e483ecbc27af54c2431eedc0d8feb2e42..9f1174b3f9c1e544f23061b83f53b2a74d198f66 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_packetizing_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_packetizing_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_packetizing is
generic (
@@ -56,7 +56,7 @@ architecture tb of tb_dp_packetizing is
constant c_usr_block_size : natural := 60; -- = 2*2*3*5, so suitable for g_usr_nof_words = 1, 2, 3, 4, 5, 6 and with c_dp_gap_min=4 yields minimal c_interval_size
--CONSTANT c_usr_block_size : NATURAL := 20 * g_usr_nof_words; -- dp_repack does not support padding, so the g_usr_nof_words must fit the block size
constant c_usr_block_size_w : natural := ceil_log2(c_usr_block_size + c_dp_gap_min);
- constant c_interval_size : natural := 2**c_usr_block_size_w;
+ constant c_interval_size : natural := 2 ** c_usr_block_size_w;
constant c_gap_size : natural := c_interval_size - c_usr_block_size;
constant c_phy_block_size : natural := c_usr_block_size * g_phy_nof_words / g_usr_nof_words;
@@ -67,8 +67,8 @@ architecture tb of tb_dp_packetizing is
constant c_fifo_size : natural := c_usr_block_size;
constant c_fifo_fill : integer := sel_a_b(g_usr_nof_words <= g_phy_nof_words,
- 0, -- no_xmt_pacer (dummy value)
- c_usr_block_size - c_phy_block_size); -- gen_xmt_pacer
+ 0, -- no_xmt_pacer (dummy value)
+ c_usr_block_size - c_phy_block_size); -- gen_xmt_pacer
constant c_rcv_fifo_nof_words : natural := c_phy_block_size;
@@ -160,27 +160,27 @@ begin
-- Generate data path input data
proc_dp_gen_block_data(c_nof_block_per_sync,
- c_usr_block_size,
- c_gap_size,
- g_usr_nof_words, -- apply throttle at generator
- g_phy_nof_words,
- rst,
- clk,
- sync_nr,
- block_nr,
- in_sync,
- in_val,
- in_dat);
+ c_usr_block_size,
+ c_gap_size,
+ g_usr_nof_words, -- apply throttle at generator
+ g_phy_nof_words,
+ rst,
+ clk,
+ sync_nr,
+ block_nr,
+ in_sync,
+ in_val,
+ in_dat);
-- Verify the data path output data
proc_dp_verify_data("rcv_dat",
- 1, -- c_ready_latency, any value > 0 suits here
- clk,
- sl1, -- verify_en
- sl1, -- out_ready
- rcv_val,
- rcv_dat,
- prev_rcv_dat);
+ 1, -- c_ready_latency, any value > 0 suits here
+ clk,
+ sl1, -- verify_en
+ sl1, -- out_ready
+ rcv_val,
+ rcv_dat,
+ prev_rcv_dat);
-- Verify the data path output CRC (avoid error message at initialisation)
assert NOW = 0 ps or rcv_err = '0' report "rcv_err = '1' indicating CRC error" severity ERROR;
@@ -191,95 +191,95 @@ begin
-- Determine the data block control signals: sof, eof, err and fsn
u_frame_fsn : entity work.dp_frame_fsn
- generic map (
- g_fsn_w => c_fsn_w,
- g_dat_w => g_usr_dat_w,
- g_use_sync => true,
- g_block_size => c_usr_block_size
- )
- port map (
- rst => rst,
- clk => clk,
- in_sync => in_sync,
- in_val => in_val,
- in_dat => in_dat,
- out_fsn => xmt_fsn,
- out_dat => xmt_dat,
- out_val => xmt_val,
- out_sof => xmt_sof,
- out_eof => xmt_eof,
- out_err => xmt_err
- );
+ generic map (
+ g_fsn_w => c_fsn_w,
+ g_dat_w => g_usr_dat_w,
+ g_use_sync => true,
+ g_block_size => c_usr_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ in_sync => in_sync,
+ in_val => in_val,
+ in_dat => in_dat,
+ out_fsn => xmt_fsn,
+ out_dat => xmt_dat,
+ out_val => xmt_val,
+ out_sof => xmt_sof,
+ out_eof => xmt_eof,
+ out_err => xmt_err
+ );
-- Insert the fsn and err into the internal data path frame format
u_frame : entity work.dp_frame
- generic map (
- g_fsn_w => c_fsn_w,
- g_dat_w => g_usr_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_fsn => xmt_fsn,
- in_dat => xmt_dat,
- in_val => xmt_val,
- in_sof => xmt_sof,
- in_eof => xmt_eof,
- in_err => xmt_err,
-
- out_dat => xmt_frm_dat,
- out_val => xmt_frm_val,
- out_sof => xmt_frm_sof,
- out_eof => xmt_frm_eof
- );
+ generic map (
+ g_fsn_w => c_fsn_w,
+ g_dat_w => g_usr_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_fsn => xmt_fsn,
+ in_dat => xmt_dat,
+ in_val => xmt_val,
+ in_sof => xmt_sof,
+ in_eof => xmt_eof,
+ in_err => xmt_err,
+
+ out_dat => xmt_frm_dat,
+ out_val => xmt_frm_val,
+ out_sof => xmt_frm_sof,
+ out_eof => xmt_frm_eof
+ );
-- Pack the user data width frame data into the PHY data width frame data
-- Note:
-- . The proc_dp_gen_block_data appies throttling if g_usr_nof_words <
-- g_phy_nof_words, so xmt_frm_val has a sufficiently slow pace.
u_frame_pack : entity work.dp_frame_repack
- generic map (
- g_in_dat_w => g_usr_dat_w,
- g_in_nof_words => g_usr_nof_words,
- g_out_dat_w => g_phy_dat_w,
- g_out_nof_words => g_phy_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => xmt_frm_dat,
- in_val => xmt_frm_val,
- in_sof => xmt_frm_sof,
- in_eof => xmt_frm_eof,
-
- out_dat => xmt_pack_dat,
- out_val => xmt_pack_val,
- out_sof => xmt_pack_sof,
- out_eof => xmt_pack_eof
- );
+ generic map (
+ g_in_dat_w => g_usr_dat_w,
+ g_in_nof_words => g_usr_nof_words,
+ g_out_dat_w => g_phy_dat_w,
+ g_out_nof_words => g_phy_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => xmt_frm_dat,
+ in_val => xmt_frm_val,
+ in_sof => xmt_frm_sof,
+ in_eof => xmt_frm_eof,
+
+ out_dat => xmt_pack_dat,
+ out_val => xmt_pack_val,
+ out_sof => xmt_pack_sof,
+ out_eof => xmt_pack_eof
+ );
-- Transmit the internal data path frame as a dp PHY frame with SFD and a true CRC
u_frame_tx : entity work.dp_frame_tx
- generic map (
- g_sfd => c_dp_sfd,
- g_dat_w => g_phy_dat_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => xmt_pack_dat,
- in_val => xmt_pack_val,
- in_sof => xmt_pack_sof,
- in_eof => xmt_pack_eof,
-
- out_dat => xmt_pace_dat,
- out_val => xmt_pace_val(0),
- out_sof => xmt_pace_sof(0),
- out_eof => xmt_pace_eof(0)
- );
+ generic map (
+ g_sfd => c_dp_sfd,
+ g_dat_w => g_phy_dat_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => xmt_pack_dat,
+ in_val => xmt_pack_val,
+ in_sof => xmt_pack_sof,
+ in_eof => xmt_pack_eof,
+
+ out_dat => xmt_pace_dat,
+ out_val => xmt_pace_val(0),
+ out_sof => xmt_pace_sof(0),
+ out_eof => xmt_pace_eof(0)
+ );
------------------------------------------------------------------------------
-- PHY LINK INTERFACE
@@ -287,37 +287,37 @@ begin
-- Model the transceiver link
u_transceiver_link : entity work.dp_phy_link
- generic map (
- g_latency => c_phy_link_latency,
- g_valid_support => c_phy_link_valid_support
- )
- port map (
- in_dat => phy_tx_dat,
- in_val => phy_tx_val,
-
- out_dat => phy_rx_dat,
- out_val => phy_rx_val
- );
+ generic map (
+ g_latency => c_phy_link_latency,
+ g_valid_support => c_phy_link_valid_support
+ )
+ port map (
+ in_dat => phy_tx_dat,
+ in_val => phy_tx_val,
+
+ out_dat => phy_rx_dat,
+ out_val => phy_rx_val
+ );
-- Receive the dp PHY frame with SFD and a true CRC and extract the internal data path frame
u_frame_rx : entity work.dp_frame_rx
- generic map (
- g_sfd => c_dp_sfd,
- g_dat_w => g_phy_dat_w,
- g_block_size => c_phy_block_size
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => phy_rx_dat,
- in_val => phy_rx_val,
-
- out_dat => rcv_pack_dat,
- out_val => rcv_pack_val,
- out_sof => rcv_pack_sof,
- out_eof => rcv_pack_eof
- );
+ generic map (
+ g_sfd => c_dp_sfd,
+ g_dat_w => g_phy_dat_w,
+ g_block_size => c_phy_block_size
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => phy_rx_dat,
+ in_val => phy_rx_val,
+
+ out_dat => rcv_pack_dat,
+ out_val => rcv_pack_val,
+ out_sof => rcv_pack_sof,
+ out_eof => rcv_pack_eof
+ );
-- Transceiver link interface control
gen_valid_support : if c_phy_link_valid_support = true generate
@@ -372,26 +372,26 @@ begin
phy_tx_val <= phy_tx_sosi.valid;
u_fifo_fill : entity work.dp_fifo_fill
- generic map (
- g_data_w => g_phy_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_fifo_fill => c_fifo_fill,
- g_fifo_size => c_fifo_size,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => xmt_pace_sosi,
- src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
- src_out => phy_tx_sosi
- );
+ generic map (
+ g_data_w => g_phy_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_fifo_fill => c_fifo_fill,
+ g_fifo_size => c_fifo_size,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => xmt_pace_sosi,
+ src_in => c_dp_siso_rdy, -- IN = request from downstream ST sink
+ src_out => phy_tx_sosi
+ );
end generate;
-- ==> 2) Use FIFO and dp_frame_rd to throttle the output frame for unpack if necessary
@@ -416,67 +416,67 @@ begin
rcv_fifo_rd_eof <= rcv_fifo_rd_sosi.eop;
dut : entity work.dp_fifo_sc
- generic map (
- g_data_w => g_phy_dat_w,
- g_empty_w => 1,
- g_channel_w => 1,
- g_error_w => 1,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_ctrl => true,
- g_fifo_size => c_rcv_fifo_nof_words,
- g_fifo_rl => 1
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => OPEN, -- OUT = request to upstream ST source
- snk_in => rcv_pack_sosi,
- usedw => OPEN,
- src_in => rcv_fifo_rd_siso, -- IN = request from downstream ST sink
- src_out => rcv_fifo_rd_sosi
+ generic map (
+ g_data_w => g_phy_dat_w,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_ctrl => true,
+ g_fifo_size => c_rcv_fifo_nof_words,
+ g_fifo_rl => 1
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => OPEN, -- OUT = request to upstream ST source
+ snk_in => rcv_pack_sosi,
+ usedw => OPEN,
+ src_in => rcv_fifo_rd_siso, -- IN = request from downstream ST sink
+ src_out => rcv_fifo_rd_sosi
);
- u_rcv_throttle : entity work.dp_frame_rd
- generic map (
- g_dat_w => g_phy_dat_w,
- g_throttle_num => g_phy_nof_words,
- g_throttle_den => g_usr_nof_words,
- g_throttle_sof => false,
- g_throttle_eof => false
- )
- port map (
- rst => rst,
- clk => clk,
-
- frm_req => '1',
- frm_flush => '0',
- frm_ack => OPEN,
- frm_busy => OPEN,
- frm_err => OPEN,
- frm_done => OPEN,
-
- rd_req => rcv_fifo_rd_req,
- rd_dat => rcv_fifo_rd_dat,
- rd_val => rcv_fifo_rd_val,
- rd_sof => rcv_fifo_rd_sof,
- rd_eof => rcv_fifo_rd_eof,
-
- out_dat => rcv_throttle_dat,
- out_val => rcv_throttle_val,
- out_sof => rcv_throttle_sof,
- out_eof => rcv_throttle_eof
- );
- end generate; -- gen_rcv_throttle
- end generate; -- no_valid_support
+u_rcv_throttle : entity work.dp_frame_rd
+ generic map (
+ g_dat_w => g_phy_dat_w,
+ g_throttle_num => g_phy_nof_words,
+ g_throttle_den => g_usr_nof_words,
+ g_throttle_sof => false,
+ g_throttle_eof => false
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ frm_req => '1',
+ frm_flush => '0',
+ frm_ack => OPEN,
+ frm_busy => OPEN,
+ frm_err => OPEN,
+ frm_done => OPEN,
+
+ rd_req => rcv_fifo_rd_req,
+ rd_dat => rcv_fifo_rd_dat,
+ rd_val => rcv_fifo_rd_val,
+ rd_sof => rcv_fifo_rd_sof,
+ rd_eof => rcv_fifo_rd_eof,
+
+ out_dat => rcv_throttle_dat,
+ out_val => rcv_throttle_val,
+ out_sof => rcv_throttle_sof,
+ out_eof => rcv_throttle_eof
+ );
+end generate; -- gen_rcv_throttle
+end generate; -- no_valid_support
- ------------------------------------------------------------------------------
- -- RECEIVER
- ------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- RECEIVER
+------------------------------------------------------------------------------
- -- Unpack the PHY data width frame data into the user data width frame data
- u_frame_unpack : entity work.dp_frame_repack
+-- Unpack the PHY data width frame data into the user data width frame data
+u_frame_unpack : entity work.dp_frame_repack
generic map (
g_in_dat_w => g_phy_dat_w,
g_in_nof_words => g_phy_nof_words,
@@ -498,8 +498,8 @@ begin
out_eof => rcv_frm_eof
);
- -- Extract the dat, fsn and err from the internal data path frame format
- u_unframe : entity work.dp_unframe
+-- Extract the dat, fsn and err from the internal data path frame format
+u_unframe : entity work.dp_unframe
generic map (
g_fsn_w => c_fsn_w,
g_dat_w => g_usr_dat_w
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
index f5bfc3ebe3ed4aac611671101f78a9e9cebe7082..2695b6d5914422190c8d8be905e16a735bcfe3e2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: Verify dp_pad_insert and dp_pad_remove
-- Description:
@@ -57,7 +57,7 @@ architecture tb of tb_dp_pad_insert_remove is
constant c_nof_repeat : natural := 100;
constant c_bsn_w : natural := 16;
constant c_symbol_init : natural := 0;
- constant c_symbol_mod : integer := 2**g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
+ constant c_symbol_mod : integer := 2 ** g_symbol_w; -- used to avoid TO_UVEC warning for smaller g_symbol_w : "NUMERIC_STD.TO_UNSIGNED: vector truncated"
constant c_channel_init : integer := 0;
constant c_err_init : natural := 0;
constant c_sync_period : natural := 7;
@@ -143,11 +143,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -221,34 +221,34 @@ begin
-- DUT
------------------------------------------------------------------------------
u_pad_insert : entity work.dp_pad_insert
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_padding => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso,
- snk_in => in_sosi,
- src_in => pad_siso,
- src_out => pad_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_padding => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ src_in => pad_siso,
+ src_out => pad_sosi
+ );
u_pad_remove : entity work.dp_pad_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_padding => g_nof_padding
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => pad_siso,
- snk_in => pad_sosi,
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_padding => g_nof_padding
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => pad_siso,
+ snk_in => pad_sosi,
+ src_in => out_siso,
+ src_out => out_sosi
+ );
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(g_data_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
index aec011b91bd00c5ee57c1657d886a3fb050e7e97..8d82b3f74c7990d25a4a68832b2c9daa67f22c24 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_pipeline is
generic (
@@ -145,15 +145,15 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_pipeline
- generic map (
- g_pipeline => g_pipeline
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_pipeline => g_pipeline
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
index 87366a33880b4f7b5a43161f5a3e0912711d917b..9ec2a2e1b697d0692bd87a58a8acaa2ff7861d95 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
@@ -28,13 +28,13 @@
-- . The verify procedures check the correct output
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_pipeline_ready is
generic (
@@ -108,11 +108,11 @@ begin
in_en <= '1' when g_in_en = e_active else
random_0(random_0'high) when g_in_en = e_random else
- pulse_0 when g_in_en = e_pulse;
+ pulse_0 when g_in_en = e_pulse;
out_siso.ready <= '1' when g_out_ready = e_active else
random_1(random_1'high) when g_out_ready = e_random else
- pulse_1 when g_out_ready = e_pulse;
+ pulse_1 when g_out_ready = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -150,20 +150,20 @@ begin
-- proc_dp_gen_block_data() only supports RL=0 or 1, so use a latency adpater to support any g_in_latency
u_input_adapt : entity work.dp_latency_adapter
- generic map (
- g_in_latency => c_rl,
- g_out_latency => g_in_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => in_siso,
- snk_in => in_sosi,
- -- ST source
- src_in => adapt_siso,
- src_out => adapt_sosi
- );
+ generic map (
+ g_in_latency => c_rl,
+ g_out_latency => g_in_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => in_siso,
+ snk_in => in_sosi,
+ -- ST source
+ src_in => adapt_siso,
+ src_out => adapt_sosi
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -172,7 +172,7 @@ begin
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1' and((g_out_latency > 0) or
- (g_out_latency = 0 and out_siso.ready = '1')); -- count number of output eop
+ (g_out_latency = 0 and out_siso.ready = '1')); -- count number of output eop
verify_done <= '1' when rising_edge(clk) and count_eop = g_nof_repeat; -- signal verify done after g_nof_repeat frames
-- Actual verification of the output streams
@@ -195,18 +195,18 @@ begin
------------------------------------------------------------------------------
pipeline : entity work.dp_pipeline_ready
- generic map (
- g_in_latency => g_in_latency,
- g_out_latency => g_out_latency
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => adapt_siso,
- snk_in => adapt_sosi,
- -- ST source
- src_in => out_siso,
- src_out => out_sosi
- );
+ generic map (
+ g_in_latency => g_in_latency,
+ g_out_latency => g_out_latency
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => adapt_siso,
+ snk_in => adapt_sosi,
+ -- ST source
+ src_in => out_siso,
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index 6353df4b0888251a65c083f94af093b3eae414c2..c0aaac52c5feea9711f860cc9fcc4af7b2d11ae5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -21,13 +21,13 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
package tb_dp_pkg is
------------------------------------------------------------------------------
@@ -112,77 +112,82 @@ package tb_dp_pkg is
-- Block data generator with feedforward throttle control
-- !!! old style: sync before sop
-- !!! used by tb_dp_packetizing, do not use for new DP components
- procedure proc_dp_gen_block_data(constant c_nof_block_per_sync : in natural;
- constant c_block_size : in natural;
- constant c_gap_size : in natural;
- constant c_throttle_num : in natural;
- constant c_throttle_den : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync_nr : inout natural;
- signal block_nr : inout natural;
- signal cnt_sync : out std_logic;
- signal cnt_val : out std_logic;
- signal cnt_dat : inout std_logic_vector);
+ procedure proc_dp_gen_block_data(
+ constant c_nof_block_per_sync : in natural;
+ constant c_block_size : in natural;
+ constant c_gap_size : in natural;
+ constant c_throttle_num : in natural;
+ constant c_throttle_den : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync_nr : inout natural;
+ signal block_nr : inout natural;
+ signal cnt_sync : out std_logic;
+ signal cnt_val : out std_logic;
+ signal cnt_dat : inout std_logic_vector);
-- Block data generator with ready flow control and symbols counter
- procedure proc_dp_gen_block_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
- constant c_data_w : in natural; -- data width for the data, re and im fields
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural; -- init counter for symbols in data field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_block_data( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
+ constant c_data_w : in natural; -- data width for the data, re and im fields
+ constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_init : in natural; -- init counter for symbols in data field
+ constant c_symbol_re_init : in natural; -- init counter for symbols in re field
+ constant c_symbol_im_init : in natural; -- init counter for symbols in im field
+ constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- Increment only sosi.data, keep complex re,im = 0
- procedure proc_dp_gen_block_data(constant c_data_w : in natural; -- data width for the data field
- constant c_symbol_init : in natural; -- init counter for the data in the data field
- constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_block_data( -- data width for the data field
+ constant c_data_w : in natural;
+ constant c_symbol_init : in natural; -- init counter for the data in the data field
+ constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- Increment only sosi.re, im, keep data = 0
- procedure proc_dp_gen_block_complex(constant c_data_w : in natural; -- data width for the re, im field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_block_complex( -- data width for the re, im field
+ constant c_data_w : in natural;
+ constant c_symbol_re_init : in natural; -- init counter for symbols in re field
+ constant c_symbol_im_init : in natural; -- init counter for symbols in im field
+ constant c_nof_symbols : in natural; -- nof symbols = nof data per frame for the data fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- Handle stream ready signal, only support RL=0 or 1.
- procedure proc_dp_stream_ready_latency(constant c_latency : in natural;
- signal clk : in std_logic;
- signal ready : in std_logic;
- signal in_en : in std_logic; -- when '1' then active output when ready
- constant c_sync : in std_logic;
- constant c_valid : in std_logic;
- constant c_sop : in std_logic;
- constant c_eop : in std_logic;
- signal out_sync : out std_logic;
- signal out_valid : out std_logic;
- signal out_sop : out std_logic;
- signal out_eop : out std_logic);
+ procedure proc_dp_stream_ready_latency(
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal ready : in std_logic;
+ signal in_en : in std_logic; -- when '1' then active output when ready
+ constant c_sync : in std_logic;
+ constant c_valid : in std_logic;
+ constant c_sop : in std_logic;
+ constant c_eop : in std_logic;
+ signal out_sync : out std_logic;
+ signal out_valid : out std_logic;
+ signal out_sop : out std_logic;
+ signal out_eop : out std_logic);
-- Initialize the data per symbol
function func_dp_data_init(c_data_w, c_symbol_w, init : natural) return std_logic_vector;
@@ -191,150 +196,167 @@ package tb_dp_pkg is
function func_dp_data_incr(c_data_w, c_symbol_w : natural; data : std_logic_vector) return std_logic_vector;
-- Generate a counter data with valid
- procedure proc_dp_gen_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_data_w : in natural;
- constant c_data_init : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_data( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_data_init : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- As above but with counter max
- procedure proc_dp_gen_data(constant c_ready_latency : in natural;
- constant c_data_w : in natural;
- constant c_data_init : in natural;
- constant c_data_max : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic;
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_data(
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_data_init : in natural;
+ constant c_data_max : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic;
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- Generate a frame with symbols counter
- procedure proc_dp_gen_frame(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_data_w : in natural;
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural;
- constant c_nof_symbols : in natural;
- constant c_bsn : in natural;
- constant c_sync : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi);
+ procedure proc_dp_gen_frame( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_init : in natural;
+ constant c_nof_symbols : in natural;
+ constant c_bsn : in natural;
+ constant c_sync : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi);
-- Input data counter
- procedure proc_dp_cnt_dat(signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic;
- signal cnt_dat : inout std_logic_vector);
-
- procedure proc_dp_cnt_dat(signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic;
- signal cnt_val : inout std_logic;
- signal cnt_dat : inout std_logic_vector);
+ procedure proc_dp_cnt_dat(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic;
+ signal cnt_dat : inout std_logic_vector);
+
+ procedure proc_dp_cnt_dat(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic;
+ signal cnt_val : inout std_logic;
+ signal cnt_dat : inout std_logic_vector);
-- Transmit data
- procedure proc_dp_tx_data(constant c_ready_latency : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal cnt_val : in std_logic;
- signal cnt_dat : in std_logic_vector;
- signal tx_data : inout t_dp_data_arr;
- signal tx_val : inout std_logic_vector;
- signal out_data : out std_logic_vector;
- signal out_val : out std_logic);
+ procedure proc_dp_tx_data(
+ constant c_ready_latency : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal cnt_val : in std_logic;
+ signal cnt_dat : in std_logic_vector;
+ signal tx_data : inout t_dp_data_arr;
+ signal tx_val : inout std_logic_vector;
+ signal out_data : out std_logic_vector;
+ signal out_val : out std_logic);
-- Transmit data control (use for sop, eop)
- procedure proc_dp_tx_ctrl(constant c_offset : in natural;
- constant c_period : in natural;
- signal data : in std_logic_vector;
- signal valid : in std_logic;
- signal ctrl : out std_logic);
+ procedure proc_dp_tx_ctrl(
+ constant c_offset : in natural;
+ constant c_period : in natural;
+ signal data : in std_logic_vector;
+ signal valid : in std_logic;
+ signal ctrl : out std_logic);
-- Define sync interval
- procedure proc_dp_sync_interval(signal clk : in std_logic;
- signal sync : out std_logic);
+ procedure proc_dp_sync_interval(
+ signal clk : in std_logic;
+ signal sync : out std_logic);
-- Stimuli for cnt_en
- procedure proc_dp_count_en(signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal lfsr : inout std_logic_vector;
- signal state : out t_dp_state_enum;
- signal done : out std_logic;
- signal tb_end : out std_logic;
- signal cnt_en : out std_logic);
+ procedure proc_dp_count_en(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal lfsr : inout std_logic_vector;
+ signal state : out t_dp_state_enum;
+ signal done : out std_logic;
+ signal tb_end : out std_logic;
+ signal cnt_en : out std_logic);
------------------------------------------------------------------------------
-- Stream sink functions
------------------------------------------------------------------------------
-- Stimuli for out_ready
- procedure proc_dp_out_ready(signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal lfsr : inout std_logic_vector;
- signal out_ready : out std_logic);
+ procedure proc_dp_out_ready(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal lfsr : inout std_logic_vector;
+ signal out_ready : out std_logic);
-- DUT output verify enable
- procedure proc_dp_verify_en(constant c_delay : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal verify_en : out std_logic);
-
- procedure proc_dp_verify_en(constant c_continuous : in boolean;
- signal clk : in std_logic;
- signal valid : in std_logic;
- signal sop : in std_logic;
- signal eop : in std_logic;
- signal verify_en : out std_logic);
+ procedure proc_dp_verify_en(
+ constant c_delay : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal verify_en : out std_logic);
+
+ procedure proc_dp_verify_en(
+ constant c_continuous : in boolean;
+ signal clk : in std_logic;
+ signal valid : in std_logic;
+ signal sop : in std_logic;
+ signal eop : in std_logic;
+ signal verify_en : out std_logic);
-- Run and verify for some cycles
- procedure proc_dp_verify_run_some_cycles(constant nof_pre_clk : in natural;
- constant nof_verify_clk : in natural;
- constant nof_post_clk : in natural;
- signal clk : in std_logic;
- signal verify_en : out std_logic);
+ procedure proc_dp_verify_run_some_cycles(
+ constant nof_pre_clk : in natural;
+ constant nof_verify_clk : in natural;
+ constant nof_post_clk : in natural;
+ signal clk : in std_logic;
+ signal verify_en : out std_logic);
-- Verify the expected value
- procedure proc_dp_verify_value(constant c_str : in string;
- constant mode : in t_dp_value_enum;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector);
-
- procedure proc_dp_verify_value(constant mode : in t_dp_value_enum;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector);
-
- procedure proc_dp_verify_value(constant c_str : in string;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic;
- signal res : in std_logic);
+ procedure proc_dp_verify_value(
+ constant c_str : in string;
+ constant mode : in t_dp_value_enum;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector);
+
+ procedure proc_dp_verify_value(
+ constant mode : in t_dp_value_enum;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector);
+
+ procedure proc_dp_verify_value(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic;
+ signal res : in std_logic);
-- Verify output global and local BSN
-- . incrementing or replicated global BSN
-- . incrementing local BSN that starts at 1
- procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean; -- use local BSN or only use global BSN
- constant c_global_bsn_increment : in positive; -- increment per global BSN
- constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
- constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
- signal clk : in std_logic;
- signal out_sync : in std_logic;
- signal out_sop : in std_logic;
- signal out_bsn : in std_logic_vector;
- signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
- signal cnt_replicated_global_bsn : inout natural;
- signal prev_out_bsn_global : inout std_logic_vector;
- signal prev_out_bsn_local : inout std_logic_vector);
+ procedure proc_dp_verify_bsn( -- use local BSN or only use global BSN
+ constant c_use_local_bsn : in boolean;
+ constant c_global_bsn_increment : in positive; -- increment per global BSN
+ constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
+ constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
+ signal clk : in std_logic;
+ signal out_sync : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_bsn : in std_logic_vector;
+ signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
+ signal cnt_replicated_global_bsn : inout natural;
+ signal prev_out_bsn_global : inout std_logic_vector;
+ signal prev_out_bsn_local : inout std_logic_vector);
-- Verify incrementing data
-- . wrap at c_out_data_max when >0, else no wrap when c_out_data_max=0
@@ -342,323 +364,358 @@ package tb_dp_pkg is
-- or +c_out_data_gap2.
-- . by using sop or eop for out_val input, the proc_dp_verify_data() can
-- also be used to verify other SOSI fields like bsn, error, channel, empty
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- constant c_out_data_gap2 : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
-
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ constant c_out_data_gap2 : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
+
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT incrementing output data that wraps in range 0 ... c_out_data_max
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT incrementing output data, fixed increment +1
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify incrementing data with RL > 0 or no flow control, support wrap at maximum and increment gap
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- constant c_out_data_gap2 : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
-
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
-
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- constant c_out_data_gap : in natural;
- constant c_out_data_gap2 : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
-
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- constant c_out_data_gap : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
-
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ constant c_out_data_gap2 : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
+
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
+
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ constant c_out_data_gap : in natural;
+ constant c_out_data_gap2 : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
+
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ constant c_out_data_gap : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
+
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify incrementing data with RL > 0 or no flow control, fixed increment +1
- procedure proc_dp_verify_data(constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT output symbols
- procedure proc_dp_verify_symbols(constant c_ready_latency : in natural;
- constant c_data_w : in natural;
- constant c_symbol_w : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_eop : in std_logic;
- signal out_data : in std_logic_vector;
- signal out_empty : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector);
+ procedure proc_dp_verify_symbols(
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_symbol_w : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_eop : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal out_empty : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector);
-- Verify the DUT output data with empty
- procedure proc_dp_verify_data_empty(constant c_ready_latency : in natural;
- constant c_last_word : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_eop : in std_logic;
- signal out_eop_1 : inout std_logic;
- signal out_eop_2 : inout std_logic;
- signal out_data : in std_logic_vector;
- signal out_data_1 : inout std_logic_vector;
- signal out_data_2 : inout std_logic_vector;
- signal out_data_3 : inout std_logic_vector;
- signal out_empty : in std_logic_vector;
- signal out_empty_1 : inout std_logic_vector);
-
- procedure proc_dp_verify_other_sosi(constant c_str : in string;
- constant c_exp_data : in std_logic_vector;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal res_data : in std_logic_vector);
-
- procedure proc_dp_verify_sosi_equal(constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
- signal exp_sosi : in t_dp_sosi_integer); -- use func_dp_stream_slv_to_integer for conversion
-
- procedure proc_dp_verify_sosi_equal(constant c_use_complex : in boolean;
- signal dut_sosi : in t_dp_sosi;
- signal exp_sosi : in t_dp_sosi);
-
- procedure proc_dp_verify_valid(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal prev_out_ready : inout std_logic_vector;
- signal out_val : in std_logic);
-
- procedure proc_dp_verify_valid(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal prev_out_ready : inout std_logic;
- signal out_val : in std_logic);
+ procedure proc_dp_verify_data_empty(
+ constant c_ready_latency : in natural;
+ constant c_last_word : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_eop : in std_logic;
+ signal out_eop_1 : inout std_logic;
+ signal out_eop_2 : inout std_logic;
+ signal out_data : in std_logic_vector;
+ signal out_data_1 : inout std_logic_vector;
+ signal out_data_2 : inout std_logic_vector;
+ signal out_data_3 : inout std_logic_vector;
+ signal out_empty : in std_logic_vector;
+ signal out_empty_1 : inout std_logic_vector);
+
+ procedure proc_dp_verify_other_sosi(
+ constant c_str : in string;
+ constant c_exp_data : in std_logic_vector;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal res_data : in std_logic_vector);
+
+ procedure proc_dp_verify_sosi_equal(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
+ signal exp_sosi : in t_dp_sosi_integer); -- use func_dp_stream_slv_to_integer for conversion
+
+ procedure proc_dp_verify_sosi_equal(
+ constant c_use_complex : in boolean;
+ signal dut_sosi : in t_dp_sosi;
+ signal exp_sosi : in t_dp_sosi);
+
+ procedure proc_dp_verify_valid(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal prev_out_ready : inout std_logic_vector;
+ signal out_val : in std_logic);
+
+ procedure proc_dp_verify_valid(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal prev_out_ready : inout std_logic;
+ signal out_val : in std_logic);
-- Verify the DUT output sync
- procedure proc_dp_verify_sync(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- expected_sync : in std_logic);
-
- procedure proc_dp_verify_sync(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- bsn : in natural; -- for reporting
- expected_bsn : in natural; -- for reporting
- expected_sync : in std_logic);
- -- Note: A SIGNAL IN can only connect a SIGNAL. Therefore define IN as
- -- default (= CONSTANT) instead of SIGNAL to be able to connect
- -- VARIABLE or SIGNAL.
-
- procedure proc_dp_verify_sync(constant c_sync_period : in natural;
- constant c_sync_offset : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector);
-
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural;
- constant c_sync_period : in natural;
- constant c_block_size : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector;
- -- for debug purposes
- signal dbg_nof_blk : out natural;
- signal dbg_accumulate : out natural;
- signal dbg_expected_bsn : out natural);
-
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural;
- constant c_sync_period : in natural;
- constant c_block_size : in natural;
- constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector;
- -- for debug purposes
- signal dbg_nof_blk : out natural;
- signal dbg_accumulate : out natural;
- signal dbg_expected_bsn : out natural);
+ procedure proc_dp_verify_sync(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ expected_sync : in std_logic);
+
+ procedure proc_dp_verify_sync(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ bsn : in natural; -- for reporting
+ expected_bsn : in natural; -- for reporting
+ expected_sync : in std_logic);
+ -- Note: A SIGNAL IN can only connect a SIGNAL. Therefore define IN as
+ -- default (= CONSTANT) instead of SIGNAL to be able to connect
+ -- VARIABLE or SIGNAL.
+
+ procedure proc_dp_verify_sync(
+ constant c_sync_period : in natural;
+ constant c_sync_offset : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector);
+
+ procedure proc_dp_verify_sync(
+ constant c_start_bsn : in natural;
+ constant c_sync_period : in natural;
+ constant c_block_size : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector;
+ -- for debug purposes
+ signal dbg_nof_blk : out natural;
+ signal dbg_accumulate : out natural;
+ signal dbg_expected_bsn : out natural);
+
+ procedure proc_dp_verify_sync(
+ constant c_start_bsn : in natural;
+ constant c_sync_period : in natural;
+ constant c_block_size : in natural;
+ constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector;
+ -- for debug purposes
+ signal dbg_nof_blk : out natural;
+ signal dbg_accumulate : out natural;
+ signal dbg_expected_bsn : out natural);
-- Verify the DUT output sop and eop
- procedure proc_dp_verify_sop_and_eop(constant c_ready_latency : in natural;
- constant c_verify_valid : in boolean;
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic);
-
- procedure proc_dp_verify_sop_and_eop(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic);
-
- procedure proc_dp_verify_sop_and_eop(signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic);
-
- procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal alt_size : in natural; -- alternative size (eg. use exp_size'last_value)
- signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural);
-
- procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural);
-
- procedure proc_dp_verify_block_size(signal alt_size : in natural; -- alternative size (eg. use exp_size'last_value)
- signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural);
-
- procedure proc_dp_verify_block_size(signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural);
+ procedure proc_dp_verify_sop_and_eop(
+ constant c_ready_latency : in natural;
+ constant c_verify_valid : in boolean;
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic);
+
+ procedure proc_dp_verify_sop_and_eop(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic);
+
+ procedure proc_dp_verify_sop_and_eop(
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic);
+
+ procedure proc_dp_verify_block_size(
+ constant c_ready_latency : in natural;
+ signal alt_size : in natural; -- alternative size (eg. use exp_size'last_value)
+ signal exp_size : in natural; -- expected size
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural);
+
+ procedure proc_dp_verify_block_size(
+ constant c_ready_latency : in natural;
+ signal exp_size : in natural; -- expected size
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural);
+
+ procedure proc_dp_verify_block_size( -- alternative size (eg. use exp_size'last_value)
+ signal alt_size : in natural;
+ signal exp_size : in natural; -- expected size
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural);
+
+ procedure proc_dp_verify_block_size( -- expected size
+ signal exp_size : in natural;
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural);
-- Verify the DUT output invalid between frames
- procedure proc_dp_verify_gap_invalid(signal clk : in std_logic;
- signal in_val : in std_logic;
- signal in_sop : in std_logic;
- signal in_eop : in std_logic;
- signal out_gap : inout std_logic); -- declare initial gap signal = '1'
+ procedure proc_dp_verify_gap_invalid(
+ signal clk : in std_logic;
+ signal in_val : in std_logic;
+ signal in_sop : in std_logic;
+ signal in_eop : in std_logic;
+ signal out_gap : inout std_logic); -- declare initial gap signal = '1'
-- Verify the DUT output control (use for sop, eop)
- procedure proc_dp_verify_ctrl(constant c_offset : in natural;
- constant c_period : in natural;
- constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal data : in std_logic_vector;
- signal valid : in std_logic;
- signal ctrl : in std_logic);
+ procedure proc_dp_verify_ctrl(
+ constant c_offset : in natural;
+ constant c_period : in natural;
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal data : in std_logic_vector;
+ signal valid : in std_logic;
+ signal ctrl : in std_logic);
-- Wait for stream valid
- procedure proc_dp_stream_valid(signal clk : in std_logic;
- signal in_valid : in std_logic);
+ procedure proc_dp_stream_valid(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic);
-- Wait for stream valid AND sop
- procedure proc_dp_stream_valid_sop(signal clk : in std_logic;
- signal in_valid : in std_logic;
- signal in_sop : in std_logic);
+ procedure proc_dp_stream_valid_sop(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic;
+ signal in_sop : in std_logic);
-- Wait for stream valid AND eop
- procedure proc_dp_stream_valid_eop(signal clk : in std_logic;
- signal in_valid : in std_logic;
- signal in_eop : in std_logic);
+ procedure proc_dp_stream_valid_eop(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic;
+ signal in_eop : in std_logic);
end tb_dp_pkg;
package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Block data generator with feedforward throttle control
------------------------------------------------------------------------------
- procedure proc_dp_gen_block_data(constant c_nof_block_per_sync : in natural;
- constant c_block_size : in natural;
- constant c_gap_size : in natural;
- constant c_throttle_num : in natural;
- constant c_throttle_den : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync_nr : inout natural;
- signal block_nr : inout natural;
- signal cnt_sync : out std_logic;
- signal cnt_val : out std_logic;
- signal cnt_dat : inout std_logic_vector) is
+ procedure proc_dp_gen_block_data(
+ constant c_nof_block_per_sync : in natural;
+ constant c_block_size : in natural;
+ constant c_gap_size : in natural;
+ constant c_throttle_num : in natural;
+ constant c_throttle_den : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync_nr : inout natural;
+ signal block_nr : inout natural;
+ signal cnt_sync : out std_logic;
+ signal cnt_val : out std_logic;
+ signal cnt_dat : inout std_logic_vector) is
constant c_start_delay : natural := 10;
variable v_throttle : natural;
begin
@@ -723,22 +780,23 @@ package body tb_dp_pkg is
-- . dependent on in_en and src_in.ready
-- . optional sync pulse at end of frame
------------------------------------------------------------------------------
- procedure proc_dp_gen_block_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
- constant c_data_w : in natural; -- data width for the data, re and im fields
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural; -- init counter for symbols in data field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_block_data( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_use_data : in boolean; -- when TRUE use data field, else use re, im fields, and keep unused fields at 'X'
+ constant c_data_w : in natural; -- data width for the data, re and im fields
+ constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_init : in natural; -- init counter for symbols in data field
+ constant c_symbol_re_init : in natural; -- init counter for symbols in re field
+ constant c_symbol_im_init : in natural; -- init counter for symbols in im field
+ constant c_nof_symbols : in natural; -- nof symbols per frame for the data, re and im fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w;
constant c_div : natural := c_nof_symbols / c_nof_symbols_per_data;
constant c_mod : natural := c_nof_symbols mod c_nof_symbols_per_data;
@@ -791,34 +849,36 @@ package body tb_dp_pkg is
end proc_dp_gen_block_data;
-- Increment only sosi.data, keep complex re,im = 0
- procedure proc_dp_gen_block_data(constant c_data_w : in natural; -- data width for the data field
- constant c_symbol_init : in natural; -- init counter for the data in the data field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_block_data( -- data width for the data field
+ constant c_data_w : in natural;
+ constant c_symbol_init : in natural; -- init counter for the data in the data field
+ constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
begin
proc_dp_gen_block_data(1, true, c_data_w, c_data_w, c_symbol_init, 0, 0, c_nof_symbols, c_channel, c_error, c_sync, c_bsn, clk, in_en, src_in, src_out);
end proc_dp_gen_block_data;
-- Increment only sosi.re, im, keep data = 0
- procedure proc_dp_gen_block_complex(constant c_data_w : in natural; -- data width for the re, im field
- constant c_symbol_re_init : in natural; -- init counter for symbols in re field
- constant c_symbol_im_init : in natural; -- init counter for symbols in im field
- constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
- constant c_channel : in natural; -- channel field
- constant c_error : in natural; -- error field
- constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
- constant c_bsn : in std_logic_vector; -- bsn field
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_block_complex( -- data width for the re, im field
+ constant c_data_w : in natural;
+ constant c_symbol_re_init : in natural; -- init counter for symbols in re field
+ constant c_symbol_im_init : in natural; -- init counter for symbols in im field
+ constant c_nof_symbols : in natural; -- nof symbols per frame for the data fields
+ constant c_channel : in natural; -- channel field
+ constant c_error : in natural; -- error field
+ constant c_sync : in std_logic; -- when '1' issue sync pulse during this block
+ constant c_bsn : in std_logic_vector; -- bsn field
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
begin
proc_dp_gen_block_data(1, false, c_data_w, c_data_w, 0, c_symbol_re_init, c_symbol_im_init, c_nof_symbols, c_channel, c_error, c_sync, c_bsn, clk, in_en, src_in, src_out);
end proc_dp_gen_block_complex;
@@ -828,18 +888,19 @@ package body tb_dp_pkg is
-- . output active when src_in is ready and in_en='1'
-- . only support RL=0 or 1, support for RL>1 requires keeping previous ready information in a STD_LOGIC_VECTOR(RL-1 DOWNTO 0).
------------------------------------------------------------------------------
- procedure proc_dp_stream_ready_latency(constant c_latency : in natural;
- signal clk : in std_logic;
- signal ready : in std_logic;
- signal in_en : in std_logic;
- constant c_sync : in std_logic;
- constant c_valid : in std_logic;
- constant c_sop : in std_logic;
- constant c_eop : in std_logic;
- signal out_sync : out std_logic;
- signal out_valid : out std_logic;
- signal out_sop : out std_logic;
- signal out_eop : out std_logic) is
+ procedure proc_dp_stream_ready_latency(
+ constant c_latency : in natural;
+ signal clk : in std_logic;
+ signal ready : in std_logic;
+ signal in_en : in std_logic;
+ constant c_sync : in std_logic;
+ constant c_valid : in std_logic;
+ constant c_sop : in std_logic;
+ constant c_eop : in std_logic;
+ signal out_sync : out std_logic;
+ signal out_valid : out std_logic;
+ signal out_sop : out std_logic;
+ signal out_eop : out std_logic) is
begin
-- Default no output
out_sync <= '0';
@@ -932,14 +993,15 @@ package body tb_dp_pkg is
-- PROCEDURE: Generate counter data with valid
-- . Output counter data dependent on in_en and src_in.ready
------------------------------------------------------------------------------
- procedure proc_dp_gen_data(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_data_w : in natural;
- constant c_data_init : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_data( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_data_init : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
variable v_data : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(c_data_init, c_data_w);
begin
src_out <= c_dp_sosi_rst;
@@ -959,15 +1021,16 @@ package body tb_dp_pkg is
-- . Output counter data dependent on in_en and src_in.ready
-- . with maximum count value
------------------------------------------------------------------------------
- procedure proc_dp_gen_data(constant c_ready_latency : in natural;
- constant c_data_w : in natural;
- constant c_data_init : in natural;
- constant c_data_max : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_data(
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_data_init : in natural;
+ constant c_data_max : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
variable v_cnt : std_logic_vector(c_data_w - 1 downto 0) := TO_UVEC(c_data_init, c_data_w);
begin
src_out <= c_dp_sosi_rst;
@@ -990,17 +1053,18 @@ package body tb_dp_pkg is
-- PROCEDURE: Generate a frame with symbols counter
-- . dependent on in_en and src_in.ready
------------------------------------------------------------------------------
- procedure proc_dp_gen_frame(constant c_ready_latency : in natural; -- 0, 1 are supported by proc_dp_stream_ready_latency()
- constant c_data_w : in natural;
- constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
- constant c_symbol_init : in natural;
- constant c_nof_symbols : in natural;
- constant c_bsn : in natural;
- constant c_sync : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
- signal src_in : in t_dp_siso;
- signal src_out : out t_dp_sosi) is
+ procedure proc_dp_gen_frame( -- 0, 1 are supported by proc_dp_stream_ready_latency()
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_symbol_w : in natural; -- c_data_w/c_symbol_w must be an integer
+ constant c_symbol_init : in natural;
+ constant c_nof_symbols : in natural;
+ constant c_bsn : in natural;
+ constant c_sync : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic; -- when '0' then no valid output even when src_in is ready
+ signal src_in : in t_dp_siso;
+ signal src_out : out t_dp_sosi) is
constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w;
constant c_div : natural := c_nof_symbols / c_nof_symbols_per_data;
constant c_mod : natural := c_nof_symbols mod c_nof_symbols_per_data;
@@ -1038,10 +1102,11 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Input data counter
------------------------------------------------------------------------------
- procedure proc_dp_cnt_dat(signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic;
- signal cnt_dat : inout std_logic_vector) is
+ procedure proc_dp_cnt_dat(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic;
+ signal cnt_dat : inout std_logic_vector) is
begin
if rst = '1' then
cnt_dat <= (cnt_dat'range => '0');
@@ -1052,11 +1117,12 @@ package body tb_dp_pkg is
end if;
end proc_dp_cnt_dat;
- procedure proc_dp_cnt_dat(signal rst : in std_logic;
- signal clk : in std_logic;
- signal in_en : in std_logic;
- signal cnt_val : inout std_logic;
- signal cnt_dat : inout std_logic_vector) is
+ procedure proc_dp_cnt_dat(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal in_en : in std_logic;
+ signal cnt_val : inout std_logic;
+ signal cnt_dat : inout std_logic_vector) is
begin
if rst = '1' then
cnt_val <= '0';
@@ -1073,15 +1139,16 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Transmit data
------------------------------------------------------------------------------
- procedure proc_dp_tx_data(constant c_ready_latency : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal cnt_val : in std_logic;
- signal cnt_dat : in std_logic_vector;
- signal tx_data : inout t_dp_data_arr;
- signal tx_val : inout std_logic_vector;
- signal out_data : out std_logic_vector;
- signal out_val : out std_logic) is
+ procedure proc_dp_tx_data(
+ constant c_ready_latency : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal cnt_val : in std_logic;
+ signal cnt_dat : in std_logic_vector;
+ signal tx_data : inout t_dp_data_arr;
+ signal tx_val : inout std_logic_vector;
+ signal out_data : out std_logic_vector;
+ signal out_val : out std_logic) is
constant c_void : natural := sel_a_b(c_ready_latency, 1, 0); -- used to avoid empty range VHDL warnings when c_ready_latency=0
begin
-- TX data array for output ready latency [c_ready_latency], index [0] for zero latency combinatorial
@@ -1103,11 +1170,12 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Transmit data control (use for sop, eop)
------------------------------------------------------------------------------
- procedure proc_dp_tx_ctrl(constant c_offset : in natural;
- constant c_period : in natural;
- signal data : in std_logic_vector;
- signal valid : in std_logic;
- signal ctrl : out std_logic) is
+ procedure proc_dp_tx_ctrl(
+ constant c_offset : in natural;
+ constant c_period : in natural;
+ signal data : in std_logic_vector;
+ signal valid : in std_logic;
+ signal ctrl : out std_logic) is
variable v_data : integer;
begin
v_data := TO_UINT(data);
@@ -1120,8 +1188,9 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Define test sync interval
------------------------------------------------------------------------------
- procedure proc_dp_sync_interval(signal clk : in std_logic;
- signal sync : out std_logic) is
+ procedure proc_dp_sync_interval(
+ signal clk : in std_logic;
+ signal sync : out std_logic) is
begin
sync <= '0';
for I in 1 to c_dp_sync_interval - 1 loop wait until rising_edge(clk); end loop;
@@ -1132,14 +1201,15 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Stimuli for cnt_en
------------------------------------------------------------------------------
- procedure proc_dp_count_en(signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal lfsr : inout std_logic_vector;
- signal state : out t_dp_state_enum;
- signal done : out std_logic;
- signal tb_end : out std_logic;
- signal cnt_en : out std_logic) is
+ procedure proc_dp_count_en(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal lfsr : inout std_logic_vector;
+ signal state : out t_dp_state_enum;
+ signal done : out std_logic;
+ signal tb_end : out std_logic;
+ signal cnt_en : out std_logic) is
begin
-- The counter operates at zero latency
state <= s_idle;
@@ -1439,11 +1509,12 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Stimuli for out_ready
------------------------------------------------------------------------------
- procedure proc_dp_out_ready(signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal lfsr : inout std_logic_vector;
- signal out_ready : out std_logic) is
+ procedure proc_dp_out_ready(
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal lfsr : inout std_logic_vector;
+ signal out_ready : out std_logic) is
begin
out_ready <= '0';
wait until rst = '0';
@@ -1712,11 +1783,12 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- Fixed delay until verify_en active
- procedure proc_dp_verify_en(constant c_delay : in natural;
- signal rst : in std_logic;
- signal clk : in std_logic;
- signal sync : in std_logic;
- signal verify_en : out std_logic) is
+ procedure proc_dp_verify_en(
+ constant c_delay : in natural;
+ signal rst : in std_logic;
+ signal clk : in std_logic;
+ signal sync : in std_logic;
+ signal verify_en : out std_logic) is
begin
verify_en <= '0';
wait until rst = '0';
@@ -1731,12 +1803,13 @@ package body tb_dp_pkg is
end proc_dp_verify_en;
-- Dynamicly depend on first valid data to make verify_en active
- procedure proc_dp_verify_en(constant c_continuous : in boolean;
- signal clk : in std_logic;
- signal valid : in std_logic;
- signal sop : in std_logic;
- signal eop : in std_logic;
- signal verify_en : out std_logic) is
+ procedure proc_dp_verify_en(
+ constant c_continuous : in boolean;
+ signal clk : in std_logic;
+ signal valid : in std_logic;
+ signal sop : in std_logic;
+ signal eop : in std_logic;
+ signal verify_en : out std_logic) is
begin
if rising_edge(clk) then
if c_continuous = true then
@@ -1756,11 +1829,12 @@ package body tb_dp_pkg is
end proc_dp_verify_en;
-- Run and verify for some cycles
- procedure proc_dp_verify_run_some_cycles(constant nof_pre_clk : in natural;
- constant nof_verify_clk : in natural;
- constant nof_post_clk : in natural;
- signal clk : in std_logic;
- signal verify_en : out std_logic) is
+ procedure proc_dp_verify_run_some_cycles(
+ constant nof_pre_clk : in natural;
+ constant nof_verify_clk : in natural;
+ constant nof_post_clk : in natural;
+ signal clk : in std_logic;
+ signal verify_en : out std_logic) is
begin
proc_common_wait_some_cycles(clk, nof_pre_clk);
verify_en <= '1';
@@ -1773,12 +1847,13 @@ package body tb_dp_pkg is
-- PROCEDURE: Verify the expected value
------------------------------------------------------------------------------
-- e.g. to check that a test has ran at all
- procedure proc_dp_verify_value(constant c_str : in string;
- constant mode : in t_dp_value_enum;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector) is
+ procedure proc_dp_verify_value(
+ constant c_str : in string;
+ constant mode : in t_dp_value_enum;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector) is
begin
if rising_edge(clk) then
if en = '1' then
@@ -1792,20 +1867,22 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_value;
- procedure proc_dp_verify_value(constant mode : in t_dp_value_enum;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic_vector;
- signal res : in std_logic_vector) is
+ procedure proc_dp_verify_value(
+ constant mode : in t_dp_value_enum;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic_vector;
+ signal res : in std_logic_vector) is
begin
proc_dp_verify_value("", mode, clk, en, exp, res);
end proc_dp_verify_value;
- procedure proc_dp_verify_value(constant c_str : in string;
- signal clk : in std_logic;
- signal en : in std_logic;
- signal exp : in std_logic;
- signal res : in std_logic) is
+ procedure proc_dp_verify_value(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal en : in std_logic;
+ signal exp : in std_logic;
+ signal res : in std_logic) is
begin
if rising_edge(clk) then
if en = '1' then
@@ -1843,18 +1920,19 @@ package body tb_dp_pkg is
-- The verify_en should initially be set to '0' and gets enabled when
-- sufficient BSN history is available to do the verification.
--
- procedure proc_dp_verify_bsn(constant c_use_local_bsn : in boolean; -- use local BSN or only use global BSN
- constant c_global_bsn_increment : in positive; -- increment per global BSN
- constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
- constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
- signal clk : in std_logic;
- signal out_sync : in std_logic;
- signal out_sop : in std_logic;
- signal out_bsn : in std_logic_vector;
- signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
- signal cnt_replicated_global_bsn : inout natural;
- signal prev_out_bsn_global : inout std_logic_vector;
- signal prev_out_bsn_local : inout std_logic_vector) is
+ procedure proc_dp_verify_bsn( -- use local BSN or only use global BSN
+ constant c_use_local_bsn : in boolean;
+ constant c_global_bsn_increment : in positive; -- increment per global BSN
+ constant c_nof_replicated_global_bsn : in positive; -- number of replicated global BSN
+ constant c_block_per_sync : in positive; -- of sop/eop blocks per sync interval
+ signal clk : in std_logic;
+ signal out_sync : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_bsn : in std_logic_vector;
+ signal verify_en : inout std_logic; -- initialize '0', becomes '1' when bsn verification starts
+ signal cnt_replicated_global_bsn : inout natural;
+ signal prev_out_bsn_global : inout std_logic_vector;
+ signal prev_out_bsn_local : inout std_logic_vector) is
begin
if rising_edge(clk) then
-- out_sop must be active, because only then out_bsn will differ from the previous out_bsn
@@ -1914,17 +1992,18 @@ package body tb_dp_pkg is
-- . wrap at c_out_data_max when >0, else no wrap when c_out_data_max=0
-- . default increment by 1, but also allow an increment by c_out_data_gap
-- . or c_out_data_gap2.
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- constant c_out_data_gap2 : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic; -- only needed when c_ready_latency = 0
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ constant c_out_data_gap2 : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic; -- only needed when c_ready_latency = 0
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
if rising_edge(clk) then
-- out_val must be active, because only the out_data will it differ from the previous out_data
@@ -1944,13 +2023,13 @@ package body tb_dp_pkg is
-- also allow increment +c_out_data_gap or +c_out_data_gap2.
-- also allow increment +c_out_data_gap wrapped by c_out_data_max.
if unsigned(out_data) /= unsigned(prev_out_data) + 1 and
- unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap and
- unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap2 and
- unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap - c_out_data_max then
+ unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap and
+ unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap2 and
+ unsigned(out_data) /= unsigned(prev_out_data) + c_out_data_gap - c_out_data_max then
report "DP : Wrong out_data " & c_str & " count (" &
- natural'image(to_uint(out_data)) & ", " &
- natural'image(to_uint(prev_out_data)) & ")"
- severity ERROR;
+ natural'image(to_uint(out_data)) & ", " &
+ natural'image(to_uint(prev_out_data)) & ")"
+ severity ERROR;
end if;
end if;
end if;
@@ -1958,158 +2037,168 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic; -- only needed when c_ready_latency = 0
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic; -- only needed when c_ready_latency = 0
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
proc_dp_verify_data(c_str, c_ready_latency,
- c_out_data_max, c_out_data_gap, c_unsigned_1,
- clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ c_out_data_max, c_out_data_gap, c_unsigned_1,
+ clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
-- Verify incrementing data that wraps in range 0 ... c_out_data_max
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- constant c_out_data_max : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ constant c_out_data_max : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
proc_dp_verify_data(c_str, c_ready_latency,
- c_out_data_max, c_unsigned_1, c_unsigned_1,
- clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ c_out_data_max, c_unsigned_1, c_unsigned_1,
+ clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
-- Verify incrementing data
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
proc_dp_verify_data(c_str, c_ready_latency,
- c_unsigned_0, c_unsigned_1, c_unsigned_1,
- clk, verify_en, out_ready, out_val, out_data, prev_out_data);
+ c_unsigned_0, c_unsigned_1, c_unsigned_1,
+ clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
-- Verify incrementing data with RL > 0 or no flow control
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- constant c_out_data_gap2 : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ constant c_out_data_gap2 : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
-- Use out_val as void signal to pass on to unused out_ready, because a
-- signal input can not connect a constant or variable.
proc_dp_verify_data(c_str, 1,
- c_out_data_max, c_out_data_gap, c_out_data_gap2,
- clk, verify_en, out_val, out_val, out_data, prev_out_data);
+ c_out_data_max, c_out_data_gap, c_out_data_gap2,
+ clk, verify_en, out_val, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in unsigned;
- constant c_out_data_gap : in unsigned;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in unsigned;
+ constant c_out_data_gap : in unsigned;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
proc_dp_verify_data(c_str,
- c_out_data_max, c_out_data_gap, c_unsigned_1,
- clk, verify_en, out_val, out_data, prev_out_data);
+ c_out_data_max, c_out_data_gap, c_unsigned_1,
+ clk, verify_en, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- constant c_out_data_gap : in natural;
- constant c_out_data_gap2 : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ constant c_out_data_gap : in natural;
+ constant c_out_data_gap2 : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
constant c_data_w : natural := out_data'length;
begin
proc_dp_verify_data(c_str,
- to_unsigned(c_out_data_max, c_data_w),
- to_unsigned(c_out_data_gap, c_data_w),
- to_unsigned(c_out_data_gap2, c_data_w),
- clk, verify_en, out_val, out_data, prev_out_data);
+ to_unsigned(c_out_data_max, c_data_w),
+ to_unsigned(c_out_data_gap, c_data_w),
+ to_unsigned(c_out_data_gap2, c_data_w),
+ clk, verify_en, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- constant c_out_data_gap : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ constant c_out_data_gap : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
constant c_data_w : natural := out_data'length;
begin
proc_dp_verify_data(c_str,
- c_out_data_max, c_out_data_gap, 1,
- clk, verify_en, out_val, out_data, prev_out_data);
+ c_out_data_max, c_out_data_gap, 1,
+ clk, verify_en, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- constant c_out_data_max : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ constant c_out_data_max : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
constant c_data_w : natural := out_data'length;
begin
proc_dp_verify_data(c_str,
- c_out_data_max, 1,
- clk, verify_en, out_val, out_data, prev_out_data);
+ c_out_data_max, 1,
+ clk, verify_en, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
- procedure proc_dp_verify_data(constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_val : in std_logic;
- signal out_data : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_data(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_val : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
begin
proc_dp_verify_data(c_str, 0,
- clk, verify_en, out_val, out_data, prev_out_data);
+ clk, verify_en, out_val, out_data, prev_out_data);
end proc_dp_verify_data;
------------------------------------------------------------------------------
-- PROCEDURE: Verify incrementing symbols in data
-- . for c_data_w = c_symbol_w proc_dp_verify_symbols() = proc_dp_verify_data()
------------------------------------------------------------------------------
- procedure proc_dp_verify_symbols(constant c_ready_latency : in natural;
- constant c_data_w : in natural;
- constant c_symbol_w : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_eop : in std_logic;
- signal out_data : in std_logic_vector;
- signal out_empty : in std_logic_vector;
- signal prev_out_data : inout std_logic_vector) is
+ procedure proc_dp_verify_symbols(
+ constant c_ready_latency : in natural;
+ constant c_data_w : in natural;
+ constant c_symbol_w : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_eop : in std_logic;
+ signal out_data : in std_logic_vector;
+ signal out_empty : in std_logic_vector;
+ signal prev_out_data : inout std_logic_vector) is
constant c_nof_symbols_per_data : natural := c_data_w / c_symbol_w; -- must be an integer
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
variable v_data : std_logic_vector(c_data_w - 1 downto 0);
@@ -2159,21 +2248,22 @@ package body tb_dp_pkg is
-- . support last word replace (e.g. by a CRC instead of the count, or use
-- c_last_word=out_data for no replace)
------------------------------------------------------------------------------
- procedure proc_dp_verify_data_empty(constant c_ready_latency : in natural;
- constant c_last_word : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_eop : in std_logic;
- signal out_eop_1 : inout std_logic;
- signal out_eop_2 : inout std_logic;
- signal out_data : in std_logic_vector;
- signal out_data_1 : inout std_logic_vector;
- signal out_data_2 : inout std_logic_vector;
- signal out_data_3 : inout std_logic_vector;
- signal out_empty : in std_logic_vector;
- signal out_empty_1 : inout std_logic_vector) is
+ procedure proc_dp_verify_data_empty(
+ constant c_ready_latency : in natural;
+ constant c_last_word : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_eop : in std_logic;
+ signal out_eop_1 : inout std_logic;
+ signal out_eop_2 : inout std_logic;
+ signal out_data : in std_logic_vector;
+ signal out_data_1 : inout std_logic_vector;
+ signal out_data_2 : inout std_logic_vector;
+ signal out_data_3 : inout std_logic_vector;
+ signal out_empty : in std_logic_vector;
+ signal out_empty_1 : inout std_logic_vector) is
variable v_last_word : std_logic_vector(out_data'high downto 0);
variable v_ref_data : std_logic_vector(out_data'high downto 0);
variable v_empty_data : std_logic_vector(out_data'high downto 0);
@@ -2245,11 +2335,12 @@ package body tb_dp_pkg is
-- . Suited to verify the empty, error, channel fields assuming that these
-- are treated in the same way in parallel to the SOSI data.
------------------------------------------------------------------------------
- procedure proc_dp_verify_other_sosi(constant c_str : in string;
- constant c_exp_data : in std_logic_vector; -- use constant to support assignment via FUNCTION return value
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal res_data : in std_logic_vector) is
+ procedure proc_dp_verify_other_sosi(
+ constant c_str : in string;
+ constant c_exp_data : in std_logic_vector; -- use constant to support assignment via FUNCTION return value
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal res_data : in std_logic_vector) is
begin
if rising_edge(clk) then
if verify_en = '1' then
@@ -2279,11 +2370,12 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify per field whether DUT output SOSI is equal to expected SOSI
------------------------------------------------------------------------------
- procedure proc_dp_verify_sosi_equal(constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
- signal exp_sosi : in t_dp_sosi_integer) is -- use func_dp_stream_slv_to_integer for conversion
+ procedure proc_dp_verify_sosi_equal(
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal dut_sosi : in t_dp_sosi_integer; -- use func_dp_stream_slv_to_integer for conversion
+ signal exp_sosi : in t_dp_sosi_integer) is -- use func_dp_stream_slv_to_integer for conversion
begin
-- Use sosi integers, instead of sosi slv, for easier comparision. This
-- implies that only integer low part of sosi slv fields is checked, so
@@ -2309,7 +2401,7 @@ package body tb_dp_pkg is
report "DP : Wrong dut_sosi.valid (" & sl_to_str(dut_sosi.valid) & " /= " & sl_to_str(exp_sosi.valid) & ")" severity ERROR;
end if;
- -- sosi info fields
+ -- sosi info fields
elsif c_str = "bsn" then
if dut_sosi.bsn /= exp_sosi.bsn then
report "DP : Wrong dut_sosi.bsn (" & int_to_str(dut_sosi.bsn) & " /= " & int_to_str(exp_sosi.bsn) & ")" severity ERROR;
@@ -2327,7 +2419,7 @@ package body tb_dp_pkg is
report "DP : Wrong dut_sosi.err (" & int_to_str(dut_sosi.err) & " /= " & int_to_str(exp_sosi.err) & ")" severity ERROR;
end if;
- -- sosi data fields
+ -- sosi data fields
elsif c_str = "data" then
if dut_sosi.data /= exp_sosi.data then
report "DP : Wrong dut_sosi.data (" & int_to_str(dut_sosi.data) & " /= " & int_to_str(exp_sosi.data) & ")" severity ERROR;
@@ -2341,7 +2433,7 @@ package body tb_dp_pkg is
report "DP : Wrong dut_sosi.im (" & int_to_str(dut_sosi.im) & " /= " & int_to_str(exp_sosi.im) & ")" & ")" severity ERROR;
end if;
- -- unknown sosi field
+ -- unknown sosi field
else
report "proc_dp_verify_sosi_equal : Unknown sosi." & c_str & "field" severity FAILURE;
end if;
@@ -2349,9 +2441,10 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_sosi_equal;
- procedure proc_dp_verify_sosi_equal(constant c_use_complex : in boolean;
- signal dut_sosi : in t_dp_sosi;
- signal exp_sosi : in t_dp_sosi) is
+ procedure proc_dp_verify_sosi_equal(
+ constant c_use_complex : in boolean;
+ signal dut_sosi : in t_dp_sosi;
+ signal exp_sosi : in t_dp_sosi) is
begin
assert dut_sosi.sync = exp_sosi.sync report "Wrong dut_sosi.sync" severity ERROR;
assert dut_sosi.sop = exp_sosi.sop report "Wrong dut_sosi.sop" severity ERROR;
@@ -2378,12 +2471,13 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output valid
------------------------------------------------------------------------------
- procedure proc_dp_verify_valid(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal prev_out_ready : inout std_logic_vector;
- signal out_val : in std_logic) is
+ procedure proc_dp_verify_valid(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal prev_out_ready : inout std_logic_vector;
+ signal out_val : in std_logic) is
begin
if rising_edge(clk) then
-- for ready_latency > 0 out_val may only be asserted after out_ready
@@ -2404,11 +2498,12 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_valid;
- procedure proc_dp_verify_valid(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal out_ready : in std_logic;
- signal prev_out_ready : inout std_logic;
- signal out_val : in std_logic) is
+ procedure proc_dp_verify_valid(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal out_ready : in std_logic;
+ signal prev_out_ready : inout std_logic;
+ signal out_val : in std_logic) is
begin
-- Can not reuse:
-- proc_dp_verify_valid(1, clk, verify_en, out_ready, prev_out_ready, out_val);
@@ -2429,51 +2524,53 @@ package body tb_dp_pkg is
-- . sync is defined such that it can only be active at sop
-- . report expected_sync from input
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- expected_sync : in std_logic) is
+ procedure proc_dp_verify_sync(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ expected_sync : in std_logic) is
begin
if rising_edge(clk) then
if verify_en = '1' then
-- Check for unexpected sync
if sync = '1' then
assert expected_sync = '1'
- report "Error: Unexpected sync at BSN" severity ERROR;
+ report "Error: Unexpected sync at BSN" severity ERROR;
assert sop = '1'
- report "Error: Unexpected sync at inactive sop" severity ERROR;
+ report "Error: Unexpected sync at inactive sop" severity ERROR;
end if;
-- Check for missing sync
if sop = '1' and expected_sync = '1' then
assert sync = '1'
- report "Error: Missing sync" severity ERROR;
+ report "Error: Missing sync" severity ERROR;
end if;
end if;
end if;
end proc_dp_verify_sync;
- procedure proc_dp_verify_sync(signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- bsn : in natural; -- for reporting
- expected_bsn : in natural; -- for reporting
- expected_sync : in std_logic) is
+ procedure proc_dp_verify_sync(
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ bsn : in natural; -- for reporting
+ expected_bsn : in natural; -- for reporting
+ expected_sync : in std_logic) is
begin
if rising_edge(clk) then
if verify_en = '1' then
-- Check for unexpected sync
if sync = '1' then
assert expected_sync = '1'
- report "Error: Unexpected sync at BSN (" & int_to_str(bsn) & " /= " & int_to_str(expected_bsn) & ")" severity ERROR;
+ report "Error: Unexpected sync at BSN (" & int_to_str(bsn) & " /= " & int_to_str(expected_bsn) & ")" severity ERROR;
assert sop = '1'
- report "Error: Unexpected sync at inactive sop" severity ERROR;
+ report "Error: Unexpected sync at inactive sop" severity ERROR;
end if;
-- Check for missing sync
if sop = '1' and expected_sync = '1' then
assert sync = '1'
- report "Error: Missing sync" severity ERROR;
+ report "Error: Missing sync" severity ERROR;
end if;
end if;
end if;
@@ -2484,13 +2581,14 @@ package body tb_dp_pkg is
-- . sync is defined such that it can only be active at sop
-- . assume that the sync occures priodically at bsn MOD c_sync_period = c_sync_offset
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_sync_period : in natural; -- BSN sync period
- constant c_sync_offset : in natural; -- BSN sync offset
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector) is
+ procedure proc_dp_verify_sync( -- BSN sync period
+ constant c_sync_period : in natural;
+ constant c_sync_offset : in natural; -- BSN sync offset
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector) is
constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length); -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
variable v_bsn : natural := TO_UINT(bsn(c_bsn_w - 1 downto 0));
variable v_expected_sync : boolean;
@@ -2509,31 +2607,32 @@ package body tb_dp_pkg is
-- dp_bsn_source_v2, dp_bsn_sync_scheduler.
-- . Use block sequence number (BSN) in dbg_expected_bsn.
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural; -- BSN of first sync, start of fractional periods
- constant c_sync_period : in natural; -- number of sample per sync period
- constant c_block_size : in natural; -- number of sample per block
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector;
- -- for debug purposes
- signal dbg_nof_blk : out natural;
- signal dbg_accumulate : out natural;
- signal dbg_expected_bsn : out natural) is
+ procedure proc_dp_verify_sync( -- BSN of first sync, start of fractional periods
+ constant c_start_bsn : in natural;
+ constant c_sync_period : in natural; -- number of sample per sync period
+ constant c_block_size : in natural; -- number of sample per block
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector;
+ -- for debug purposes
+ signal dbg_nof_blk : out natural;
+ signal dbg_accumulate : out natural;
+ signal dbg_expected_bsn : out natural) is
begin
proc_dp_verify_sync(c_start_bsn,
- c_sync_period,
- c_block_size,
- false,
- clk,
- verify_en,
- sync,
- sop,
- bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ c_sync_period,
+ c_block_size,
+ false,
+ clk,
+ verify_en,
+ sync,
+ sop,
+ bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
end proc_dp_verify_sync;
------------------------------------------------------------------------------
@@ -2545,19 +2644,20 @@ package body tb_dp_pkg is
-- . support using block sequence number (BSN) in dbg_expected_bsn or using
-- raw samples sequence number (RSN) in dbg_expected_bsn
------------------------------------------------------------------------------
- procedure proc_dp_verify_sync(constant c_start_bsn : in natural; -- BSN of first sync, start of fractional periods
- constant c_sync_period : in natural; -- number of sample per sync period
- constant c_block_size : in natural; -- number of sample per block
- constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal sync : in std_logic;
- signal sop : in std_logic;
- signal bsn : in std_logic_vector;
- -- for debug purposes
- signal dbg_nof_blk : out natural;
- signal dbg_accumulate : out natural;
- signal dbg_expected_bsn : out natural) is
+ procedure proc_dp_verify_sync( -- BSN of first sync, start of fractional periods
+ constant c_start_bsn : in natural;
+ constant c_sync_period : in natural; -- number of sample per sync period
+ constant c_block_size : in natural; -- number of sample per block
+ constant c_bsn_is_rsn : in boolean; -- increment BSN by 1 or by c_block_size for RSN
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal sync : in std_logic;
+ signal sop : in std_logic;
+ signal bsn : in std_logic_vector;
+ -- for debug purposes
+ signal dbg_nof_blk : out natural;
+ signal dbg_accumulate : out natural;
+ signal dbg_expected_bsn : out natural) is
constant c_bsn_w : natural := sel_a_b(bsn'length > 31, 31, bsn'length); -- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
constant c_nof_blk_min : natural := c_sync_period / c_block_size; -- minimum number of blocks in sync period
constant c_extra : natural := c_sync_period mod c_block_size; -- number of extra samples in sync period
@@ -2612,14 +2712,15 @@ package body tb_dp_pkg is
-- PROCEDURE: Verify the DUT output sop and eop
------------------------------------------------------------------------------
-- sop and eop in pairs, valid during packet and invalid between packets
- procedure proc_dp_verify_sop_and_eop(constant c_ready_latency : in natural;
- constant c_verify_valid : in boolean;
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic) is
+ procedure proc_dp_verify_sop_and_eop(
+ constant c_ready_latency : in natural;
+ constant c_verify_valid : in boolean;
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic) is
begin
if rising_edge(clk) then
if out_val = '0' then
@@ -2650,36 +2751,39 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_sop_and_eop;
- procedure proc_dp_verify_sop_and_eop(constant c_ready_latency : in natural;
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic) is
+ procedure proc_dp_verify_sop_and_eop(
+ constant c_ready_latency : in natural;
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic) is
begin
proc_dp_verify_sop_and_eop(c_ready_latency, true, clk, out_ready, out_val, out_sop, out_eop, hold_sop);
end proc_dp_verify_sop_and_eop;
- procedure proc_dp_verify_sop_and_eop(signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal hold_sop : inout std_logic) is
+ procedure proc_dp_verify_sop_and_eop(
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal hold_sop : inout std_logic) is
begin
-- Use out_val as void signal to pass on to unused out_ready, because a signal input can not connect a constant or variable
proc_dp_verify_sop_and_eop(1, true, clk, out_val, out_val, out_sop, out_eop, hold_sop);
end proc_dp_verify_sop_and_eop;
- procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal alt_size : in natural; -- alternative size
- signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural) is
+ procedure proc_dp_verify_block_size(
+ constant c_ready_latency : in natural;
+ signal alt_size : in natural; -- alternative size
+ signal exp_size : in natural; -- expected size
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural) is
begin
if rising_edge(clk) then
if out_val = '1' then
@@ -2701,36 +2805,39 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_block_size;
- procedure proc_dp_verify_block_size(constant c_ready_latency : in natural;
- signal exp_size : in natural;
- signal clk : in std_logic;
- signal out_ready : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural) is
+ procedure proc_dp_verify_block_size(
+ constant c_ready_latency : in natural;
+ signal exp_size : in natural;
+ signal clk : in std_logic;
+ signal out_ready : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural) is
begin
proc_dp_verify_block_size(c_ready_latency, exp_size, exp_size, clk, out_ready, out_val, out_sop, out_eop, cnt_size);
end proc_dp_verify_block_size;
- procedure proc_dp_verify_block_size(signal alt_size : in natural; -- alternative size
- signal exp_size : in natural; -- expected size
- signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural) is
+ procedure proc_dp_verify_block_size( -- alternative size
+ signal alt_size : in natural;
+ signal exp_size : in natural; -- expected size
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural) is
begin
-- Use out_val as void signal to pass on to unused out_ready, because a signal input can not connect a constant or variable
proc_dp_verify_block_size(1, alt_size, exp_size, clk, out_val, out_val, out_sop, out_eop, cnt_size);
end proc_dp_verify_block_size;
- procedure proc_dp_verify_block_size(signal exp_size : in natural;
- signal clk : in std_logic;
- signal out_val : in std_logic;
- signal out_sop : in std_logic;
- signal out_eop : in std_logic;
- signal cnt_size : inout natural) is
+ procedure proc_dp_verify_block_size(
+ signal exp_size : in natural;
+ signal clk : in std_logic;
+ signal out_val : in std_logic;
+ signal out_sop : in std_logic;
+ signal out_eop : in std_logic;
+ signal cnt_size : inout natural) is
begin
-- Use out_val as void signal to pass on to unused out_ready, because a signal input can not connect a constant or variable
proc_dp_verify_block_size(1, exp_size, exp_size, clk, out_val, out_val, out_sop, out_eop, cnt_size);
@@ -2739,11 +2846,12 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output invalid between frames
------------------------------------------------------------------------------
- procedure proc_dp_verify_gap_invalid(signal clk : in std_logic;
- signal in_val : in std_logic;
- signal in_sop : in std_logic;
- signal in_eop : in std_logic;
- signal out_gap : inout std_logic) is
+ procedure proc_dp_verify_gap_invalid(
+ signal clk : in std_logic;
+ signal in_val : in std_logic;
+ signal in_sop : in std_logic;
+ signal in_eop : in std_logic;
+ signal out_gap : inout std_logic) is
begin
if rising_edge(clk) then
if in_eop = '1' then
@@ -2759,14 +2867,15 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output control (use for sop, eop)
------------------------------------------------------------------------------
- procedure proc_dp_verify_ctrl(constant c_offset : in natural;
- constant c_period : in natural;
- constant c_str : in string;
- signal clk : in std_logic;
- signal verify_en : in std_logic;
- signal data : in std_logic_vector;
- signal valid : in std_logic;
- signal ctrl : in std_logic) is
+ procedure proc_dp_verify_ctrl(
+ constant c_offset : in natural;
+ constant c_period : in natural;
+ constant c_str : in string;
+ signal clk : in std_logic;
+ signal verify_en : in std_logic;
+ signal data : in std_logic_vector;
+ signal valid : in std_logic;
+ signal ctrl : in std_logic) is
variable v_data : integer;
begin
if rising_edge(clk) then
@@ -2788,8 +2897,9 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid
------------------------------------------------------------------------------
- procedure proc_dp_stream_valid(signal clk : in std_logic;
- signal in_valid : in std_logic) is
+ procedure proc_dp_stream_valid(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic) is
begin
wait until rising_edge(clk);
while in_valid /= '1' loop
@@ -2800,9 +2910,10 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid AND sop
------------------------------------------------------------------------------
- procedure proc_dp_stream_valid_sop(signal clk : in std_logic;
- signal in_valid : in std_logic;
- signal in_sop : in std_logic) is
+ procedure proc_dp_stream_valid_sop(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic;
+ signal in_sop : in std_logic) is
begin
wait until rising_edge(clk);
while in_valid /= '1' and in_sop /= '1' loop
@@ -2813,9 +2924,10 @@ package body tb_dp_pkg is
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid AND eop
------------------------------------------------------------------------------
- procedure proc_dp_stream_valid_eop(signal clk : in std_logic;
- signal in_valid : in std_logic;
- signal in_eop : in std_logic) is
+ procedure proc_dp_stream_valid_eop(
+ signal clk : in std_logic;
+ signal in_valid : in std_logic;
+ signal in_eop : in std_logic) is
begin
wait until rising_edge(clk);
while in_valid /= '1' and in_eop /= '1' loop
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
index da2ad8b364e2d8096b719a92456d7eb26b19e944..99fc33626c79a53fed4618580a629994ac761d4f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
@@ -20,11 +20,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use work.dp_stream_pkg.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use work.dp_stream_pkg.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.tb_dp_pkg.all;
-- Purpose: Test bench to check reinterleave function on DP level
-- Usage:
@@ -44,7 +44,7 @@ entity tb_dp_reinterleave is
g_inter_block_size : natural := 2;
g_use_complex : boolean := true;
g_align_out : boolean := true
- );
+ );
end;
architecture rtl of tb_dp_reinterleave is
@@ -85,6 +85,7 @@ begin
cnt_ena <= '0', '1' after 20 * c_clk_period;
gen_cnt_dat : for i in 0 to g_nof_in - 1 generate
+
p_stimuli : process
variable v_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
begin
@@ -94,7 +95,7 @@ begin
proc_common_wait_some_cycles(clk, c_input_inval);
v_bsn := INCR_UVEC(v_bsn, 1);
end loop;
- end process;
+ end process;
-----------------------------------------------------------------------------
-- The I/O of common_reinterleave and its lower level components operate
@@ -109,27 +110,26 @@ begin
snk_out_arr(i).ready <= '1';
wait for c_clk_period;
end process;
-
end generate;
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_reinterleave : entity work.dp_reinterleave
- generic map (
- g_nof_in => g_nof_in,
- g_deint_block_size => g_deint_block_size,
- g_nof_out => g_nof_out,
- g_inter_block_size => g_inter_block_size,
- g_dat_w => g_dat_w,
- g_use_complex => g_use_complex,
- g_align_out => g_align_out
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in_arr => snk_in_arr,
- src_out_arr => src_out_arr
- );
+ generic map (
+ g_nof_in => g_nof_in,
+ g_deint_block_size => g_deint_block_size,
+ g_nof_out => g_nof_out,
+ g_inter_block_size => g_inter_block_size,
+ g_dat_w => g_dat_w,
+ g_use_complex => g_use_complex,
+ g_align_out => g_align_out
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in_arr => snk_in_arr,
+ src_out_arr => src_out_arr
+ );
end rtl;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
index f8137c37ce8e2eac48b0f108c61f2b6651f51a2f..5d11b38f399f32b6bf518b8b10560745c7830661 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack is
generic (
@@ -123,11 +123,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -222,28 +222,28 @@ begin
stimuli_src_in <= pack_src_in;
u_pack : entity work.dp_repack
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
- in_val => stimuli_src_out.valid,
- in_sof => stimuli_src_out.sop,
- in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
-
- out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- out_val => pack_src_out.valid,
- out_sof => pack_src_out.sop,
- out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
+ in_val => stimuli_src_out.valid,
+ in_sof => stimuli_src_out.sop,
+ in_eof => stimuli_src_out.eop,
+ in_sync => stimuli_src_out.sync, -- DP style sync at sof
+
+ out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ out_val => pack_src_out.valid,
+ out_sof => pack_src_out.sop,
+ out_eof => pack_src_out.eop,
+ sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
------------------------------------------------------------------------------
-- Unpack
@@ -252,28 +252,28 @@ begin
pack_src_in <= unpack_src_in;
u_unpack : entity work.dp_repack
- generic map (
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- in_val => pack_src_out.valid,
- in_sof => pack_src_out.sop,
- in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
-
- out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
- out_val => unpack_src_out.valid,
- out_sof => unpack_src_out.sop,
- out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ in_val => pack_src_out.valid,
+ in_sof => pack_src_out.sop,
+ in_eof => pack_src_out.eop,
+ in_sync => pack_src_out.sync, -- DP style sync at sof
+
+ out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
+ out_val => unpack_src_out.valid,
+ out_sof => unpack_src_out.sop,
+ out_eof => unpack_src_out.eop,
+ sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
index 1fbc042d83c68b5f5e55817d62faab380e2ca0c7..f63544f833a064c91ab9f6e1a616c226640be38d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
@@ -40,13 +40,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack_data is
generic (
@@ -132,39 +132,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -198,65 +198,65 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_pkt_len => c_expected_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_pkt_len => c_expected_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT Pack
------------------------------------------------------------------------------
u_pack : entity work.dp_repack_data
- generic map (
- g_enable_repack_in => c_enable_repack_in,
- g_enable_repack_out => c_enable_repack_out,
- g_in_bypass => g_in_bypass,
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_in_symbol_w => g_in_symbol_w,
- g_out_bypass => g_pack_bypass,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words,
- g_out_symbol_w => g_pack_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
-
- src_in => pack_src_in,
- src_out => pack_src_out
- );
+ generic map (
+ g_enable_repack_in => c_enable_repack_in,
+ g_enable_repack_out => c_enable_repack_out,
+ g_in_bypass => g_in_bypass,
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_bypass => g_pack_bypass,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words,
+ g_out_symbol_w => g_pack_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+
+ src_in => pack_src_in,
+ src_out => pack_src_out
+ );
pack_src_out_data <= pack_src_out.data(g_pack_dat_w - 1 downto 0);
@@ -271,28 +271,28 @@ begin
gen_unpack : if c_no_unpack = false generate
u_unpack : entity work.dp_repack_data
- generic map (
- g_enable_repack_in => c_enable_repack_out,
- g_enable_repack_out => c_enable_repack_in,
- g_in_bypass => g_pack_bypass,
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_in_symbol_w => g_pack_symbol_w,
- g_out_bypass => g_in_bypass,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words,
- g_out_symbol_w => g_in_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => pack_src_in,
- snk_in => pack_src_out,
-
- src_in => unpack_src_in,
- src_out => unpack_src_out
- );
+ generic map (
+ g_enable_repack_in => c_enable_repack_out,
+ g_enable_repack_out => c_enable_repack_in,
+ g_in_bypass => g_pack_bypass,
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_in_symbol_w => g_pack_symbol_w,
+ g_out_bypass => g_in_bypass,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words,
+ g_out_symbol_w => g_in_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => pack_src_in,
+ snk_in => pack_src_out,
+
+ src_in => unpack_src_in,
+ src_out => unpack_src_out
+ );
end generate;
unpack_src_out_data <= unpack_src_out.data(g_in_dat_w - 1 downto 0);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
index 062f9d2deeca01986cb62ec00d32c670005a83fe..f37260a3ea9c0d1da39eff2b60ba146bcf5ca5c1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_repack_legacy is
generic (
@@ -46,13 +46,13 @@ entity tb_dp_repack_legacy is
g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- specific
--- g_in_dat_w : NATURAL := 8;
--- g_in_nof_words : NATURAL := 9;
--- g_pack_dat_w : NATURAL := 24;
--- g_pack_nof_words : NATURAL := 3;
--- g_nof_repeat : NATURAL := 24;
--- g_pkt_len : NATURAL := 36; -- must be a multiple of g_in_nof_words
--- g_pkt_gap : NATURAL := 4 -- must be >= g_pack_nof_words
+ -- g_in_dat_w : NATURAL := 8;
+ -- g_in_nof_words : NATURAL := 9;
+ -- g_pack_dat_w : NATURAL := 24;
+ -- g_pack_nof_words : NATURAL := 3;
+ -- g_nof_repeat : NATURAL := 24;
+ -- g_pkt_len : NATURAL := 36; -- must be a multiple of g_in_nof_words
+ -- g_pkt_gap : NATURAL := 4 -- must be >= g_pack_nof_words
g_in_dat_w : natural := 8;
g_in_nof_words : natural := 4;
g_pack_dat_w : natural := 16;
@@ -120,39 +120,39 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_data_init => c_data_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => g_pkt_len,
- g_pkt_gap => g_pkt_gap
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_data_init => c_data_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => g_pkt_len,
+ g_pkt_gap => g_pkt_gap
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -186,37 +186,37 @@ begin
verify_last_snk_in_evt.err <= '0';
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => g_in_dat_w,
- g_pkt_len => g_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => g_in_dat_w,
+ g_pkt_len => g_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT Pack
@@ -225,28 +225,28 @@ begin
stimuli_src_in <= pack_src_in;
u_pack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_in_dat_w,
- g_in_nof_words => g_in_nof_words,
- g_out_dat_w => g_pack_dat_w,
- g_out_nof_words => g_pack_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
- in_val => stimuli_src_out.valid,
- in_sof => stimuli_src_out.sop,
- in_eof => stimuli_src_out.eop,
- in_sync => stimuli_src_out.sync, -- DP style sync at sof
-
- out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- out_val => pack_src_out.valid,
- out_sof => pack_src_out.sop,
- out_eof => pack_src_out.eop,
- sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_in_dat_w,
+ g_in_nof_words => g_in_nof_words,
+ g_out_dat_w => g_pack_dat_w,
+ g_out_nof_words => g_pack_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => stimuli_src_out.data(g_in_dat_w - 1 downto 0),
+ in_val => stimuli_src_out.valid,
+ in_sof => stimuli_src_out.sop,
+ in_eof => stimuli_src_out.eop,
+ in_sync => stimuli_src_out.sync, -- DP style sync at sof
+
+ out_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ out_val => pack_src_out.valid,
+ out_sof => pack_src_out.sop,
+ out_eof => pack_src_out.eop,
+ sof_sync => pack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
------------------------------------------------------------------------------
-- DUT Unpack
@@ -255,28 +255,28 @@ begin
pack_src_in <= unpack_src_in;
u_unpack : entity work.dp_repack_legacy
- generic map (
- g_in_dat_w => g_pack_dat_w,
- g_in_nof_words => g_pack_nof_words,
- g_out_dat_w => g_in_dat_w,
- g_out_nof_words => g_in_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
-
- in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
- in_val => pack_src_out.valid,
- in_sof => pack_src_out.sop,
- in_eof => pack_src_out.eop,
- in_sync => pack_src_out.sync, -- DP style sync at sof
-
- out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
- out_val => unpack_src_out.valid,
- out_sof => unpack_src_out.sop,
- out_eof => unpack_src_out.eop,
- sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
- );
+ generic map (
+ g_in_dat_w => g_pack_dat_w,
+ g_in_nof_words => g_pack_nof_words,
+ g_out_dat_w => g_in_dat_w,
+ g_out_nof_words => g_in_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ in_dat => pack_src_out.data(g_pack_dat_w - 1 downto 0),
+ in_val => pack_src_out.valid,
+ in_sof => pack_src_out.sop,
+ in_eof => pack_src_out.eop,
+ in_sync => pack_src_out.sync, -- DP style sync at sof
+
+ out_dat => unpack_src_out.data(g_in_dat_w - 1 downto 0),
+ out_val => unpack_src_out.valid,
+ out_sof => unpack_src_out.sop,
+ out_eof => unpack_src_out.eop,
+ sof_sync => unpack_src_out.sync -- DP style sync at sof, passes on in_sync
+ );
unpack_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
index 163c4635bf689c8634b5b045fe0a48a7e33d287b..b3808c75adb7186d159a226339c9a9f3918e3bda 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
@@ -40,14 +40,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data is
generic (
@@ -120,40 +120,40 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_flow_control => e_active, -- always active, no flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => false,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => c_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => c_dp_siso_rdy,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_flow_control => e_active, -- always active, no flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => false,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => c_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => c_dp_siso_rdy,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -183,34 +183,34 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_flow_control => e_active, -- always active, no flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => OPEN,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_flow_control => e_active, -- always active, no flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => OPEN,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: Using dp_reverse_n_data
@@ -222,37 +222,37 @@ begin
-- Reverse
u_reverse : entity work.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => g_pipeline,
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0,
- g_pipeline_mux_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out => reverse_src_out
- );
+ generic map (
+ g_pipeline_demux_in => g_pipeline,
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0,
+ g_pipeline_mux_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => stimuli_src_out,
+ src_out => reverse_src_out
+ );
-- Reverse again to unreverse
u_unreverse : entity work.dp_reverse_n_data
- generic map (
- g_pipeline_demux_in => g_pipeline,
- g_pipeline_demux_out => 0,
- g_pipeline_mux_in => 0,
- g_pipeline_mux_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => reverse_src_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline_demux_in => g_pipeline,
+ g_pipeline_demux_out => 0,
+ g_pipeline_mux_in => 0,
+ g_pipeline_mux_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => reverse_src_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- DUT: Using dp_reverse_n_data_fc, but with c_dp_siso_rdy so no flow control
@@ -260,33 +260,33 @@ begin
-- Reverse
u_reverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => stimuli_src_out,
- src_out => reverse_fc_src_out
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => stimuli_src_out,
+ src_out => reverse_fc_src_out
+ );
-- Reverse again to unreverse
u_unreverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_in => reverse_fc_src_out,
- src_out => verify_fc_snk_in
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_in => reverse_fc_src_out,
+ src_out => verify_fc_snk_in
+ );
-- Verify that dp_reverse_n_data_fc is equivalent to dp_reverse_n_data, when
-- no flow control is used.
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
index 5d89c3ab55ca9cb41d1e52e3d28925e3bf6393c4..56ee8de81bce9b78965203b09d1ff7b71f008308 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
@@ -36,14 +36,14 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_reverse_n_data_fc is
generic (
@@ -80,8 +80,8 @@ architecture tb of tb_dp_reverse_n_data_fc is
constant c_flow_control_latency_pls : natural := g_nof_repeat * c_pkt_len * (c_verify_pulse_period * c_stimuli_pulse_period) / (c_stimuli_pulse_active * c_verify_pulse_active);
constant c_flow_control_latency_rnd : natural := g_nof_repeat * c_pkt_len;
constant c_flow_control_latency : natural := sel_a_b(g_flow_control_stimuli = e_pulse or g_flow_control_verify = e_pulse,
- c_flow_control_latency_pls,
- c_flow_control_latency_rnd); -- worst case value
+ c_flow_control_latency_pls,
+ c_flow_control_latency_rnd); -- worst case value
constant c_data_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
constant c_dsp_max : unsigned(c_data_w - 1 downto 0) := (others => '1');
@@ -123,43 +123,43 @@ begin
------------------------------------------------------------------------------
u_dp_stream_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_stimuli_pulse_active,
- g_pulse_period => c_stimuli_pulse_period,
- g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_use_complex => false,
- g_data_init => c_data_init,
- g_re_init => c_re_init,
- g_im_init => c_im_init,
- g_bsn_init => c_bsn_init,
- g_err_init => c_err_init,
- g_channel_init => c_channel_init,
- -- specific
- g_in_dat_w => c_data_w,
- g_nof_repeat => g_nof_repeat,
- g_pkt_len => c_pkt_len,
- g_pkt_gap => g_pkt_gap,
- g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Generate stimuli
- src_in => stimuli_src_in,
- src_out => stimuli_src_out,
-
- -- End of stimuli
- last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
- tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_stimuli_pulse_active,
+ g_pulse_period => c_stimuli_pulse_period,
+ g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_use_complex => false,
+ g_data_init => c_data_init,
+ g_re_init => c_re_init,
+ g_im_init => c_im_init,
+ g_bsn_init => c_bsn_init,
+ g_err_init => c_err_init,
+ g_channel_init => c_channel_init,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_nof_repeat => g_nof_repeat,
+ g_pkt_len => c_pkt_len,
+ g_pkt_gap => g_pkt_gap,
+ g_wait_last_evt => c_flow_control_latency -- number of clk cycles to wait with last_snk_in_evt after finishing the stimuli
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Generate stimuli
+ src_in => stimuli_src_in,
+ src_out => stimuli_src_out,
+
+ -- End of stimuli
+ last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
+ tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
+ );
------------------------------------------------------------------------------
-- DATA VERIFICATION
@@ -189,37 +189,37 @@ begin
verify_last_snk_in_evt.err <= last_snk_in_evt;
u_dp_stream_verify : entity work.dp_stream_verify
- generic map (
- g_instance_nr => 0, -- only one stream so choose index 0
- -- flow control
- g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
- g_pulse_active => c_verify_pulse_active,
- g_pulse_period => c_verify_pulse_period,
- g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
- -- initializations
- g_sync_period => c_sync_period,
- g_sync_offset => c_sync_offset,
- g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
- g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
- -- specific
- g_in_dat_w => c_data_w,
- g_pkt_len => c_pkt_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Verify data
- snk_out => verify_snk_out,
- snk_in => verify_snk_in,
-
- -- During stimuli
- verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
-
- -- End of stimuli
- expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
- verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
- );
+ generic map (
+ g_instance_nr => 0, -- only one stream so choose index 0
+ -- flow control
+ g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
+ g_pulse_active => c_verify_pulse_active,
+ g_pulse_period => c_verify_pulse_period,
+ g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
+ -- initializations
+ g_sync_period => c_sync_period,
+ g_sync_offset => c_sync_offset,
+ g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
+ g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
+ -- specific
+ g_in_dat_w => c_data_w,
+ g_pkt_len => c_pkt_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Verify data
+ snk_out => verify_snk_out,
+ snk_in => verify_snk_in,
+
+ -- During stimuli
+ verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
+
+ -- End of stimuli
+ expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
+ verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
+ );
------------------------------------------------------------------------------
-- DUT
@@ -227,37 +227,37 @@ begin
-- Reverse
u_reverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- src_in => reverse_src_in,
- src_out => reverse_src_out
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ src_in => reverse_src_in,
+ src_out => reverse_src_out
+ );
-- Reverse again to unreverse
u_unreverse_fc : entity work.dp_reverse_n_data_fc
- generic map (
- g_pipeline_in => g_pipeline,
- g_pipeline_out => g_pipeline,
- g_reverse_len => g_reverse_len
- )
- port map (
- rst => rst,
- clk => clk,
-
- snk_out => reverse_src_in,
- snk_in => reverse_src_out,
- src_in => verify_snk_out,
- src_out => verify_snk_in
- );
+ generic map (
+ g_pipeline_in => g_pipeline,
+ g_pipeline_out => g_pipeline,
+ g_reverse_len => g_reverse_len
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ snk_out => reverse_src_in,
+ snk_in => reverse_src_out,
+ src_in => verify_snk_out,
+ src_out => verify_snk_in
+ );
------------------------------------------------------------------------------
-- Auxiliary
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index 2079df76274b23a4f88114270dd0461d2037edb4..d2ea7a2e4425344df03ee3f3e5c08cde76690495 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -30,12 +30,12 @@
-- needed
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_rsn_source is
generic (
@@ -324,17 +324,17 @@ begin
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync(exp_rs_start_bsn,
- g_pps_interval,
- g_rs_block_size,
- true, -- use BSN as RSN
- clk,
- verify_en,
- rs_sosi.sync,
- rs_sosi.sop,
- rs_sosi.bsn,
- dbg_nof_blk,
- dbg_accumulate,
- dbg_expected_bsn);
+ g_pps_interval,
+ g_rs_block_size,
+ true, -- use BSN as RSN
+ clk,
+ verify_en,
+ rs_sosi.sync,
+ rs_sosi.sop,
+ rs_sosi.bsn,
+ dbg_nof_blk,
+ dbg_accumulate,
+ dbg_expected_bsn);
-- Verify rs_sosi by comparing with exp_grid_rs, this again verifies rs_sosi.sync, sop and bsn
p_verify_rs_sosi_grid : process(clk)
@@ -390,48 +390,48 @@ begin
-----------------------------------------------------------------------------
u_bsn : entity work.dp_bsn_source_v2
- generic map (
- g_block_size => g_bs_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w,
- g_bsn_time_offset_w => c_bsn_time_offset_w
- )
- port map (
- rst => rst,
- clk => clk,
- pps => ref_grid_bs.pps,
- -- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
-
- dp_on_status => dp_on_status, -- = src_out.valid
- bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
- bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
-
- bsn_init => bsn_init,
- bsn_time_offset => bsn_time_offset,
-
- -- Streaming
- src_out => bs_sosi
- );
+ generic map (
+ g_block_size => g_bs_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w,
+ g_bsn_time_offset_w => c_bsn_time_offset_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ pps => ref_grid_bs.pps,
+ -- MM control
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+
+ dp_on_status => dp_on_status, -- = src_out.valid
+ bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
+ bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
+
+ bsn_init => bsn_init,
+ bsn_time_offset => bsn_time_offset,
+
+ -- Streaming
+ src_out => bs_sosi
+ );
u_rsn : entity work.dp_rsn_source
- generic map (
- g_bs_block_size => g_bs_block_size,
- g_rs_block_size => g_rs_block_size,
- g_nof_clk_per_sync => g_pps_interval,
- g_bsn_w => c_bsn_w
- )
- port map (
- rst => rst,
- clk => clk,
-
- -- Input stream sosi control using BSN
- bs_sosi => bs_sosi, -- input reference stream using BSN
-
- -- Output stream sosi control using RSN
- rs_sosi => rs_sosi, -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
- rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
- rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
- );
+ generic map (
+ g_bs_block_size => g_bs_block_size,
+ g_rs_block_size => g_rs_block_size,
+ g_nof_clk_per_sync => g_pps_interval,
+ g_bsn_w => c_bsn_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+
+ -- Input stream sosi control using BSN
+ bs_sosi => bs_sosi, -- input reference stream using BSN
+
+ -- Output stream sosi control using RSN
+ rs_sosi => rs_sosi, -- output stream using RSN and g_rs_block_size, g_nof_clk_per_sync
+ rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
+ rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index 2801b29fc2bebb169ad5c1663573eecf1a7410e4..c31a2dd744fb3e18122f0f64712fb11f92c08393 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -37,15 +37,15 @@
-- Remarks:
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_selector_arr is
generic (
@@ -181,59 +181,59 @@ begin
-- DUT that selects pipe_sosi_arr
u_dut_pipe : entity work.dp_selector_arr
- generic map(
- g_nof_arr => c_nof_streams,
- g_pipeline => 1
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- reg_selector_mosi => mm_mosi_pipe,
- reg_selector_miso => OPEN,
-
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
-
- -- ST sinks
- pipe_sosi_arr => pipe_sosi_arr,
- ref_sosi_arr => ref_sosi_arr,
- -- ST source
- out_sosi_arr => out_pipe_sosi_arr
- );
+ generic map(
+ g_nof_arr => c_nof_streams,
+ g_pipeline => 1
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_selector_mosi => mm_mosi_pipe,
+ reg_selector_miso => OPEN,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ pipe_sosi_arr => pipe_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
+ -- ST source
+ out_sosi_arr => out_pipe_sosi_arr
+ );
-- DUT that selects ref_sosi_arr
u_dut_ref : entity work.dp_selector_arr
- generic map(
- g_nof_arr => c_nof_streams,
- g_pipeline => 1
- )
- port map(
- -- Memory-mapped clock domain
- mm_rst => rst,
- mm_clk => clk,
-
- reg_selector_mosi => mm_mosi_ref,
- reg_selector_miso => OPEN,
-
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
-
- -- ST sinks
- pipe_sosi_arr => pipe_sosi_arr,
- ref_sosi_arr => ref_sosi_arr,
- -- ST source
- out_sosi_arr => out_ref_sosi_arr
- );
+ generic map(
+ g_nof_arr => c_nof_streams,
+ g_pipeline => 1
+ )
+ port map(
+ -- Memory-mapped clock domain
+ mm_rst => rst,
+ mm_clk => clk,
+
+ reg_selector_mosi => mm_mosi_ref,
+ reg_selector_miso => OPEN,
+
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+
+ -- ST sinks
+ pipe_sosi_arr => pipe_sosi_arr,
+ ref_sosi_arr => ref_sosi_arr,
+ -- ST source
+ out_sosi_arr => out_ref_sosi_arr
+ );
p_stim: process
begin
- wait until rst = '0';
- proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
- proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
- wait;
- end process;
+ wait until rst = '0';
+ proc_mem_mm_bus_wr(0, x"0", clk, mm_mosi_ref); -- select ref_sosi_arr on dut_ref
+ proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
+ wait;
+ end process;
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
index dfa71d0f185870e7a6eaf8b443d30ca53e0aae2e..dcf428854621b23cb69c63ebae1880e6e6f1e4c1 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
@@ -32,15 +32,15 @@
--
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_shiftram is
generic (
@@ -150,7 +150,7 @@ begin
begin
state <= 0;
reg_mosi <= c_mem_mosi_rst;
- proc_common_wait_some_cycles(mm_clk, 10);
+ proc_common_wait_some_cycles(mm_clk, 10);
proc_mem_mm_bus_wr( 0, c_half_nof_words, mm_clk, reg_mosi);
proc_common_wait_some_cycles(mm_clk, 12);
state <= 1;
@@ -184,28 +184,28 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_shiftram
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_words => g_nof_words,
- g_data_w => g_data_w,
- g_use_sync_in => g_use_sync_in
-
- )
- port map (
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sync_in => sync_in,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming sink
- snk_in_arr => ref_sosi_arr,
- -- Streaming source
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_words => g_nof_words,
+ g_data_w => g_data_w,
+ g_use_sync_in => g_use_sync_in
+
+ )
+ port map (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ sync_in => sync_in,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming sink
+ snk_in_arr => ref_sosi_arr,
+ -- Streaming source
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
index 1d249b0aa1e22a96485c7659d14849f8fa0e2bfb..76902eb8756d2e85263f748a8596de50f1851b47 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
@@ -21,11 +21,11 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_shiftreg is
end tb_dp_shiftreg;
@@ -145,23 +145,23 @@ begin
out_eop <= out_sosi.eop;
dut : entity work.dp_shiftreg
- generic map (
- g_output_reg => c_dut_output_reg,
- g_flush_eop => c_dut_flush_eop,
- g_modify_support => c_modify_support,
- g_nof_words => c_dut_nof_words
- )
- port map (
- rst => rst,
- clk => clk,
- -- ST sink
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- -- Control shift register contents
- cur_shiftreg_inputs => cur_shiftreg_inputs,
- new_shiftreg_inputs => new_shiftreg_inputs,
- -- ST source
- src_in => out_siso, -- IN = request from downstream ST sink
- src_out => out_sosi
- );
+ generic map (
+ g_output_reg => c_dut_output_reg,
+ g_flush_eop => c_dut_flush_eop,
+ g_modify_support => c_modify_support,
+ g_nof_words => c_dut_nof_words
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- ST sink
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ -- Control shift register contents
+ cur_shiftreg_inputs => cur_shiftreg_inputs,
+ new_shiftreg_inputs => new_shiftreg_inputs,
+ -- ST source
+ src_in => out_siso, -- IN = request from downstream ST sink
+ src_out => out_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
index 47278fc5b0eb9e6d7962c55ac16503b9f6f01434..eb17ac23c0ff74e683d84a9d39f334c598eca734 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
-- run 300 us
@@ -34,7 +34,7 @@ entity tb_dp_split is
generic (
g_data_w : natural := 64; -- g_data_w/g_symbol_w must be an integer
g_symbol_w : natural := 16; -- use sufficient width to avoid wrap in proc_dp_gen_frame()
- -- use symbols width that contains whole nibbles (4-bit) to easy debugging in HEX
+ -- use symbols width that contains whole nibbles (4-bit) to easy debugging in HEX
g_nof_symbols_max : natural := 50; -- maximum supported frame size
g_random_control : boolean := false -- use TRUE for random snk_in.valid and src_in.ready control
);
@@ -108,8 +108,8 @@ begin
-- frames
vINIT := 0;
--- FOR vLEN IN 3 TO 3 LOOP
--- FOR vNOF IN 1 TO 1 LOOP --vLEN+c_nof_symbols_per_data LOOP
+ -- FOR vLEN IN 3 TO 3 LOOP
+ -- FOR vNOF IN 1 TO 1 LOOP --vLEN+c_nof_symbols_per_data LOOP
for vLEN in 1 to g_nof_symbols_max loop
for vNOF in 0 to vLEN + c_nof_symbols_per_data loop
nof_symbols <= TO_UVEC(vNOF, c_nof_symbols_w);
@@ -118,7 +118,7 @@ begin
v_sync := sel_a_b(v_bsn mod c_sync_period = c_sync_offset, '1', '0');
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, vINIT, vLEN, v_bsn, v_sync, clk, in_en, in_siso, in_sosi);
v_bsn := v_bsn + 1;
- vINIT := (vINIT + vLEN) mod 2**g_symbol_w;
+ vINIT := (vINIT + vLEN) mod 2 ** g_symbol_w;
end loop;
end loop;
@@ -137,20 +137,20 @@ begin
end process;
dut : entity work.dp_split
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => g_nof_symbols_max
- )
- port map (
- rst => rst,
- clk => clk,
- nof_symbols => nof_symbols,
- snk_out => in_siso, -- OUT = request to upstream ST source
- snk_in => in_sosi,
- src_in_arr => out_siso, -- IN = request from downstream ST sink
- src_out_arr => out_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => g_nof_symbols_max
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ nof_symbols => nof_symbols,
+ snk_out => in_siso, -- OUT = request to upstream ST source
+ snk_in => in_sosi,
+ src_in_arr => out_siso, -- IN = request from downstream ST sink
+ src_out_arr => out_sosi
+ );
-- Output verify
-- Note that verify per frame can only verify frames that are longer than 1 data word
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
index 55c713be62ff85fb0e9a99f15cd70a6eea1e437f..69a713929430c05a18b2c98690117e43ad4946ae 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
@@ -32,15 +32,15 @@
-- . run -all
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.dp_components_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.dp_components_pkg.all;
entity tb_dp_strobe_total_count is
generic (
@@ -67,7 +67,7 @@ architecture tb of tb_dp_strobe_total_count is
-- dut
constant c_nof_counts_max : natural := c_dp_strobe_total_count_reg_nof_counts_max; -- fixed by REGMAP
constant c_nof_counts : natural := 3; -- count stimuli.sync, sop, valid
- constant c_count_max : natural := 2**g_count_w - 1;
+ constant c_count_max : natural := 2 ** g_count_w - 1;
constant c_mm_addr_clear : natural := c_dp_strobe_total_count_reg_clear_adr;
-- c_tb_nof_sync - c_skip_nof_sync because first sync intervals are skipped
@@ -110,22 +110,22 @@ begin
-- Generate snk_in with data frames
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => g_nof_blocks_per_sync,
- g_nof_repeat => g_nof_blocks_per_sync * c_tb_nof_sync,
- g_pkt_len => g_nof_valid_per_blk,
- g_pkt_gap => g_gap_size
- )
- port map (
- rst => stimuli_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => g_nof_blocks_per_sync,
+ g_nof_repeat => g_nof_blocks_per_sync * c_tb_nof_sync,
+ g_pkt_len => g_nof_valid_per_blk,
+ g_pkt_gap => g_gap_size
+ )
+ port map (
+ rst => stimuli_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
stimuli_strobe_arr(0) <= stimuli_sosi.sync;
stimuli_strobe_arr(1) <= stimuli_sosi.sop;
@@ -135,25 +135,25 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut : entity work.dp_strobe_total_count
- generic map (
- g_mm_w => g_mm_w,
- g_nof_counts => c_nof_counts,
- g_count_w => g_count_w,
- g_clip => c_clip
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- ref_sync => stimuli_sosi.sync,
- in_strobe_arr => stimuli_strobe_arr,
-
- mm_rst => rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso
- );
+ generic map (
+ g_mm_w => g_mm_w,
+ g_nof_counts => c_nof_counts,
+ g_count_w => g_count_w,
+ g_clip => c_clip
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ ref_sync => stimuli_sosi.sync,
+ in_strobe_arr => stimuli_strobe_arr,
+
+ mm_rst => rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso
+ );
------------------------------------------------------------------------------
-- Verification
@@ -185,7 +185,7 @@ begin
proc_mem_mm_bus_rd(I * 2 + 1, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
v_rd_data := reg_miso.rddata(g_mm_w - 1 downto 0);
- v_rd_count := v_rd_count + TO_UINT(v_rd_data) * 2**g_mm_w;
+ v_rd_count := v_rd_count + TO_UINT(v_rd_data) * 2 ** g_mm_w;
rd_count_arr(I) <= v_rd_count;
assert exp_count_arr(I) = v_rd_count report "Wrong total block count(" & natural'image(I) & ")" severity ERROR;
end loop;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index 83b91d51143c56abb68679ec11e9689d0dff9d6f..a12898bec768820f8ca620c1754ae5f4bba9b9ee 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -26,15 +26,15 @@
-- . Generate input streams for dp_switch, verify by eye in wave window.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_str_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_switch is
end tb_dp_switch;
@@ -87,6 +87,7 @@ begin
dp_gen_block_data_src_in_arr <= dp_switch_snk_out_arr;
gen_generate_packets : for i in 0 to c_nof_inputs - 1 generate
+
p_generate_packets : process
begin
dp_gen_block_data_src_out_arr(i) <= c_dp_sosi_rst;
@@ -120,16 +121,16 @@ begin
-- check if channel number in src_out is the same as requested (J)
assert J = TO_UINT(dp_switch_src_out.channel)
report "Wrong src_out channel" &
- ", expected=" & int_to_str(J) &
- ", readback=" & int_to_str(integer(TO_UINT(dp_switch_src_out.channel)))
- severity ERROR;
+ ", expected=" & int_to_str(J) &
+ ", readback=" & int_to_str(integer(TO_UINT(dp_switch_src_out.channel)))
+ severity ERROR;
-- check if data value in src_out is in the expected value window (J*1000 <= data < (J+1)*1000))
assert TO_UINT(dp_switch_src_out.data) >= J * 1000 and TO_UINT(dp_switch_src_out.data) < (J + 1) * 1000
report "Wrong src_out data" &
- ", expected between=" & int_to_str(J * 1000) & " and " & int_to_str((J + 1) * 1000) &
- ", readback=" & int_to_str(integer(TO_UINT(dp_switch_src_out.data)))
- severity ERROR;
+ ", expected between=" & int_to_str(J * 1000) & " and " & int_to_str((J + 1) * 1000) &
+ ", readback=" & int_to_str(integer(TO_UINT(dp_switch_src_out.data)))
+ severity ERROR;
end loop;
end loop;
@@ -137,13 +138,13 @@ begin
dp_switch_src_in <= c_dp_siso_hold;
proc_common_wait_some_cycles(mm_clk, 50);
assert dp_switch_src_out.valid = '0'
- report "Still data on output after setting hold command" severity ERROR;
+ report "Still data on output after setting hold command" severity ERROR;
-- check if output data flows again if output send flush signal
dp_switch_src_in <= c_dp_siso_rdy;
proc_common_wait_some_cycles(mm_clk, 50);
assert dp_switch_src_out.valid = '1'
- report "No data on output after setting flush command" severity ERROR;
+ report "No data on output after setting flush command" severity ERROR;
tb_end <= '1';
wait;
@@ -158,24 +159,24 @@ begin
end generate;
u_dp_switch : entity work.dp_switch
- generic map (
- g_nof_inputs => c_nof_inputs,
- g_default_enabled => 0
- )
- port map (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- snk_in_arr => dp_switch_snk_in_arr,
- snk_out_arr => dp_switch_snk_out_arr,
-
- src_out => dp_switch_src_out,
- src_in => dp_switch_src_in,
-
- reg_mosi => reg_dp_switch_mosi,
- reg_miso => reg_dp_switch_miso
- );
+ generic map (
+ g_nof_inputs => c_nof_inputs,
+ g_default_enabled => 0
+ )
+ port map (
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ snk_in_arr => dp_switch_snk_in_arr,
+ snk_out_arr => dp_switch_snk_out_arr,
+
+ src_out => dp_switch_src_out,
+ src_in => dp_switch_src_in,
+
+ reg_mosi => reg_dp_switch_mosi,
+ reg_miso => reg_dp_switch_miso
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 22cf16f4c6aa666ad36bd28409e444d227eb641d..1b44444be5c547cb1d3dcc92ea8b6784c7ac894d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -35,13 +35,13 @@
-- . the tb is self checking
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_sync_checker is
generic (
@@ -133,11 +133,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -251,19 +251,19 @@ begin
-- DUT function
dut : entity work.dp_sync_checker
- generic map (
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- dp_rst => rst,
- dp_clk => clk,
- snk_out => dut_snk_out,
- snk_in => dut_snk_in,
- src_in => dut_src_in,
- src_out => dut_src_out,
- nof_early_syncs => dut_nof_early_syncs,
- nof_late_syncs => dut_nof_late_syncs
- );
+ generic map (
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => clk,
+ snk_out => dut_snk_out,
+ snk_in => dut_snk_in,
+ src_in => dut_src_in,
+ src_out => dut_src_out,
+ nof_early_syncs => dut_nof_early_syncs,
+ nof_late_syncs => dut_nof_late_syncs
+ );
-- Connect DUT source output stream to verification
dut_src_in <= verify_snk_out;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
index d11d579d64b5a951d678ab0d02581c33bc4bc741..39c45725cd8e38abd2dadeb9d8f503f1e512c732 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
@@ -32,13 +32,13 @@
-- proc_dp_verify_bsn().
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_insert is
generic (
@@ -148,18 +148,18 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_insert
- generic map (
- g_nof_data_per_blk => g_nof_data_per_block,
- g_nof_blk_per_sync => g_nof_blk_per_sync
- )
- port map (
- rst => rst,
- clk => clk,
- -- Streaming sink
- snk_in => ref_sosi,
- -- Streaming source
- src_out => out_sosi
- );
+ generic map (
+ g_nof_data_per_blk => g_nof_data_per_block,
+ g_nof_blk_per_sync => g_nof_blk_per_sync
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Streaming sink
+ snk_in => ref_sosi,
+ -- Streaming source
+ src_out => out_sosi
+ );
------------------------------------------------------------------------------
-- Verification
@@ -185,8 +185,8 @@ begin
-- Verify output global and local bsn
proc_dp_verify_bsn(true, 1, c_nof_replicated_sync, g_nof_blk_per_sync,
- clk, out_sosi.sync, out_sosi.sop, out_sosi.bsn,
- verify_bsn_en, cnt_replicated_global_bsn, prev_out_sosi_global.bsn, prev_out_sosi_local.bsn);
+ clk, out_sosi.sync, out_sosi.sop, out_sosi.bsn,
+ verify_bsn_en, cnt_replicated_global_bsn, prev_out_sosi_global.bsn, prev_out_sosi_local.bsn);
-- Verify output packet ctrl
proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index 481331ffe8aed6340372dc1eac8501f63bfa0beb..f64181be1027bce79357d832a66bf1e33822cf98 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -35,14 +35,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_insert_v2 is
generic (
@@ -165,25 +165,25 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_insert_v2
- generic map (
- g_nof_streams => g_nof_streams,
- g_nof_blk_per_sync => g_nof_blk_per_sync,
- g_nof_blk_per_sync_min => g_nof_blk_per_sync_min
- )
- port map (
- mm_rst => rst,
- mm_clk => mm_clk,
- dp_rst => rst,
- dp_clk => dp_clk,
-
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming sink
- in_sosi_arr => ref_sosi_arr,
- -- Streaming source
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => g_nof_streams,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_nof_blk_per_sync_min => g_nof_blk_per_sync_min
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => mm_clk,
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming sink
+ in_sosi_arr => ref_sosi_arr,
+ -- Streaming source
+ out_sosi_arr => out_sosi_arr
+ );
------------------------------------------------------------------------------
-- Verification
@@ -228,5 +228,4 @@ begin
-- Verify output packet block size
proc_dp_verify_block_size(exp_size, dp_clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, cnt_size_arr(I));
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index 3ec876e8a30820ff6a74d97518b3faa357b26fd7..3059e674ddfe6ba52f2570f886fc85c02b5a4f04 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -35,14 +35,14 @@
-------------------------------------------------------------------------------
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_dp_sync_recover is
generic (
@@ -85,7 +85,7 @@ begin
------------------------------------------------------------------------------
p_stimuli : process
- variable v_bsn : natural;
+ variable v_bsn : natural;
begin
proc_common_wait_until_low(dp_clk, rst);
proc_common_wait_some_cycles(dp_clk, 5);
@@ -170,20 +170,20 @@ begin
-- DUT
------------------------------------------------------------------------------
u_dut: entity work.dp_sync_recover
- generic map (
- g_nof_data_per_block => g_nof_data_per_block
- )
- port map (
- dp_rst => rst,
- dp_clk => dp_clk,
-
- -- Streaming sink
- in_sosi => ref_sosi,
- recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
- restart => restart,
- -- Streaming source
- out_sosi => out_sosi
- );
+ generic map (
+ g_nof_data_per_block => g_nof_data_per_block
+ )
+ port map (
+ dp_rst => rst,
+ dp_clk => dp_clk,
+
+ -- Streaming sink
+ in_sosi => ref_sosi,
+ recover_val => dly_ref_sosi_arr(g_dut_latency).valid,
+ restart => restart,
+ -- Streaming source
+ out_sosi => out_sosi
+ );
------------------------------------------------------------------------------
-- Verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
index 7f85cf3f48ff9551ecf656e57c3ab0b35401c8d7..3fe4916d86f6487ea04beb2d4f59b9c21014a927 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
@@ -21,12 +21,12 @@
-------------------------------------------------------------------------------
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_tail_remove is
generic (
@@ -71,11 +71,11 @@ begin
wait for 10 * c_clk_period;
wait until rising_edge(clk);
- for i in 0 to c_nof_frames loop
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_frame, v_bsn, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
- v_symbol_init := v_symbol_init + c_nof_symbols_per_frame;
- v_bsn := v_bsn + 1;
- end loop;
+ for i in 0 to c_nof_frames loop
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_frame, v_bsn, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ v_symbol_init := v_symbol_init + c_nof_symbols_per_frame;
+ v_bsn := v_bsn + 1;
+ end loop;
wait;
end process;
@@ -87,11 +87,11 @@ begin
wait for 15 * c_clk_period;
wait until rising_edge(clk);
- for i in 0 to c_nof_frames loop
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_tail, v_bsn, '0', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
- v_symbol_init := v_symbol_init + c_nof_symbols_per_tail;
- v_bsn := v_bsn + 1;
- end loop;
+ for i in 0 to c_nof_frames loop
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, v_symbol_init, c_nof_symbols_per_tail, v_bsn, '0', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
+ v_symbol_init := v_symbol_init + c_nof_symbols_per_tail;
+ v_bsn := v_bsn + 1;
+ end loop;
-- As the tail frame will allways be last we can end the TB here:
tb_end <= '1';
@@ -101,34 +101,34 @@ begin
-- Concatenate the two streams so we can remove stream 1 (='tail')
u_dp_concat : entity work.dp_concat
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- src_in => concat_siso,
- src_out => concat_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ src_in => concat_siso,
+ src_out => concat_sosi
+ );
-- Now feed the concatenated streams into dp_tail_remove to remove the tail
u_dp_tail_remove : entity work.dp_tail_remove
- generic map (
- g_data_w => g_data_w,
- g_symbol_w => g_symbol_w,
- g_nof_symbols => c_nof_symbols_per_tail
- )
- port map (
- st_rst => rst,
- st_clk => clk,
-
- snk_out => concat_siso,
- snk_in => concat_sosi,
-
- src_in => detailed_siso,
- src_out => detailed_sosi
- );
+ generic map (
+ g_data_w => g_data_w,
+ g_symbol_w => g_symbol_w,
+ g_nof_symbols => c_nof_symbols_per_tail
+ )
+ port map (
+ st_rst => rst,
+ st_clk => clk,
+
+ snk_out => concat_siso,
+ snk_in => concat_sosi,
+
+ src_in => detailed_siso,
+ src_out => detailed_sosi
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
index 13cc297acc85ee5f1f8d966e6109650cee2e5021..06505b1ced4533552bc1d7e271681f4621a43ac2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
@@ -29,11 +29,11 @@
-- without throttling as the minimum of c_period is met.
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_throttle_sop is
end tb_dp_throttle_sop;
@@ -91,36 +91,36 @@ begin
-- FIFO acts as sink that dp_throttle_sop provides a constant flow for
-----------------------------------------------------------------------------
u_dp_fifo_sc : entity work.dp_fifo_sc
- generic map (
- g_data_w => c_gen_data_w,
- g_use_bsn => false,
- g_use_empty => false,
- g_use_channel => false,
- g_use_error => false,
- g_use_sync => false,
- g_use_ctrl => true,
- g_fifo_size => 100
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => gen_src_in,
- snk_in => gen_src_out,
- src_in => fifo_src_in,
- src_out => fifo_src_out
- );
+ generic map (
+ g_data_w => c_gen_data_w,
+ g_use_bsn => false,
+ g_use_empty => false,
+ g_use_channel => false,
+ g_use_error => false,
+ g_use_sync => false,
+ g_use_ctrl => true,
+ g_fifo_size => 100
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => gen_src_in,
+ snk_in => gen_src_out,
+ src_in => fifo_src_in,
+ src_out => fifo_src_out
+ );
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
u_dp_throttle_sop : entity work.dp_throttle_sop
- generic map (
- g_period => c_period
- )
- port map (
- rst => rst,
- clk => clk,
- snk_out => fifo_src_in,
- snk_in => fifo_src_out
- );
+ generic map (
+ g_period => c_period
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ snk_out => fifo_src_in,
+ snk_in => fifo_src_out
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
index f9587df95d1a3e24b149e625b605eda6842bcfea..6d81047af192d4f69876ad05e303c7ca22916a4d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
@@ -32,13 +32,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_throttle_xon is
generic (
@@ -168,8 +168,8 @@ begin
-- Verify incrementing global BSN
proc_dp_verify_bsn(false, 1, 1, g_nof_block_per_sync,
- clk, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn,
- verify_en_bsn, cnt_replicated_global_bsn, prev_out_bsn_global, prev_out_bsn_local);
+ clk, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn,
+ verify_en_bsn, cnt_replicated_global_bsn, prev_out_bsn_global, prev_out_bsn_local);
p_verify_xonxoff : process(clk)
begin
@@ -211,20 +211,20 @@ begin
------------------------------------------------------------------------------
u_dut : entity work.dp_throttle_xon
- generic map (
- g_restart_at_sync => g_restart_at_sync,
- g_block_size => g_block_size,
- g_nof_block_on => g_nof_block_on,
- g_nof_clk_off => c_nof_clk_off
- )
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- snk_out => stimuli_src_in,
- snk_in => stimuli_src_out,
- -- Frame out
- src_in => verify_snk_out, -- flush control via out_siso.xon
- src_out => verify_snk_in
- );
+ generic map (
+ g_restart_at_sync => g_restart_at_sync,
+ g_block_size => g_block_size,
+ g_nof_block_on => g_nof_block_on,
+ g_nof_clk_off => c_nof_clk_off
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ snk_out => stimuli_src_in,
+ snk_in => stimuli_src_out,
+ -- Frame out
+ src_in => verify_snk_out, -- flush control via out_siso.xon
+ src_out => verify_snk_in
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
index bd86e59c732776f7803aa5721b3e7e1687b344d7..0061b4c93b86165151e03fc3dbbbabbffe74d73a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
@@ -52,13 +52,13 @@
--
library IEEE, common_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_dp_xonoff is
generic (
@@ -147,11 +147,11 @@ begin
stimuli_en <= '1' when g_flow_control_stimuli = e_active else
random_0(random_0'high) when g_flow_control_stimuli = e_random else
- pulse_0 when g_flow_control_stimuli = e_pulse;
+ pulse_0 when g_flow_control_stimuli = e_pulse;
verify_snk_out.ready <= '1' when g_flow_control_verify = e_active else
random_1(random_1'high) when g_flow_control_verify = e_random else
- pulse_1 when g_flow_control_verify = e_pulse;
+ pulse_1 when g_flow_control_verify = e_pulse;
------------------------------------------------------------------------------
-- DATA GENERATION
@@ -277,16 +277,16 @@ begin
-- DUT function
gen_dut : for I in 0 to g_nof_dut - 1 generate
u_dut : entity work.dp_xonoff
- port map (
- rst => rst,
- clk => clk,
- -- Frame in
- in_siso => dut_siso_arr(I - 1),
- in_sosi => dut_sosi_arr(I - 1),
- -- Frame out
- out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
- out_sosi => dut_sosi_arr(I)
- );
+ port map (
+ rst => rst,
+ clk => clk,
+ -- Frame in
+ in_siso => dut_siso_arr(I - 1),
+ in_sosi => dut_sosi_arr(I - 1),
+ -- Frame out
+ out_siso => dut_siso_arr(I), -- flush control via out_siso.xon
+ out_sosi => dut_sosi_arr(I)
+ );
end generate;
-- Connect DUT source output stream to verification
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
index 46d08b2d87f8d1669af908f897a87551fe2e6365..0a3e8076450820f6febd85d8721c603726a0fa1a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
@@ -26,11 +26,11 @@
-- > run -all
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
entity tb_dp_xonoff_reg_timeout is
end tb_dp_xonoff_reg_timeout;
@@ -94,19 +94,19 @@ begin
end process;
u_dut : entity work.dp_xonoff_reg_timeout
- generic map (
- g_mm_timeout => 1,
- g_sim => true
- )
- port map (
- mm_rst => rst,
- mm_clk => clk,
- st_rst => rst,
- st_clk => st_clk,
+ generic map (
+ g_mm_timeout => 1,
+ g_sim => true
+ )
+ port map (
+ mm_rst => rst,
+ mm_clk => clk,
+ st_rst => rst,
+ st_clk => st_clk,
- sla_in => sla_in_mosi,
- sla_out => sla_out_miso,
+ sla_in => sla_in_mosi,
+ sla_out => sla_out_miso,
- xonoff_reg => xonoff_reg
- );
+ xonoff_reg => xonoff_reg
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index 78ff1107922be99fcc03ddd829a454cf448692a1..d5e725bfc156e3e5741503dca67600f069361a9e 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -34,15 +34,15 @@
-- > run -all
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mmp_dp_bsn_align_v2 is
generic (
@@ -81,7 +81,7 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
constant c_mon_sync_latency : natural := 1; -- due to sync_reg2 in dp_bsn_monitor_v2
constant c_reg_bsn_monitor_adr_w : natural := ceil_log2(7);
- constant c_reg_bsn_monitor_span : natural := 2**c_reg_bsn_monitor_adr_w;
+ constant c_reg_bsn_monitor_span : natural := 2 ** c_reg_bsn_monitor_adr_w;
-- maximum nof clk delay between any inputs, <= c_align_latency_nof_clk
-- . the -1 is due to some acceptable pipeline detail related to dp_block_from_mm
@@ -214,7 +214,7 @@ begin
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
assert reg_bsn_align_cipo.rddata(0) = '1' report
- "Wrong stream disable for output " & int_to_str(I) severity ERROR;
+ "Wrong stream disable for output " & int_to_str(I) severity ERROR;
end loop;
-- Write stream enable bits for stream_en_arr
@@ -229,7 +229,7 @@ begin
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
assert reg_bsn_align_cipo.rddata(0) = '0' report
- "Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
+ "Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
end loop;
-- Write stream enable bits for stream_en_arr
@@ -244,7 +244,7 @@ begin
proc_mem_mm_bus_rd(2 * I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
assert reg_bsn_align_cipo.rddata(0) = '1' report
- "Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
+ "Wrong BSN align stream enable for output " & int_to_str(I) severity ERROR;
end loop;
-- End of MM test
@@ -266,17 +266,17 @@ begin
if g_lost_input = true and I = c_nof_streams - 1 then
v_exp_latency := -1; -- -1 for BSN monitor timeout due to lost input
assert mon_latency_input_arr(I) = v_exp_latency report
- "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
- " (" & int_to_str(mon_latency_input_arr(I)) &
- " /= " & int_to_str(v_exp_latency) &
- ")" severity ERROR;
+ "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
+ " (" & int_to_str(mon_latency_input_arr(I)) &
+ " /= " & int_to_str(v_exp_latency) &
+ ")" severity ERROR;
else
v_exp_latency := c_mon_sync_latency + func_input_delay(I);
assert mon_latency_input_arr(I) = v_exp_latency report
- "Wrong input BSN monitor latency for input " & int_to_str(I) &
- " (" & int_to_str(mon_latency_input_arr(I)) &
- " /= " & int_to_str(v_exp_latency) &
- ")" severity ERROR;
+ "Wrong input BSN monitor latency for input " & int_to_str(I) &
+ " (" & int_to_str(mon_latency_input_arr(I)) &
+ " /= " & int_to_str(v_exp_latency) &
+ ")" severity ERROR;
end if;
end loop;
@@ -288,9 +288,9 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
v_exp_latency := c_mon_sync_latency + c_total_latency;
assert mon_latency_output = v_exp_latency report
- "Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
- " /= " & int_to_str(v_exp_latency) &
- ")" severity ERROR;
+ "Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
+ " /= " & int_to_str(v_exp_latency) &
+ ")" severity ERROR;
-- End of MM test
mm_end <= '1';
@@ -303,6 +303,7 @@ begin
-- Generate data path input data (similar as in tb_mmp_dp_bsn_align_v2.vhd)
gen_input : for I in c_nof_streams - 1 downto 0 generate
+
p_stimuli : process
variable v_sync : std_logic := '0';
variable v_bsn : natural;
@@ -364,6 +365,7 @@ begin
-- Model misalignment latency between the input streams to have different
-- input BSN monitor latencies
no_lost_input : if g_lost_input = false generate
+
gen_in_sosi_arr : for I in c_nof_streams - 1 downto 0 generate
in_sosi_arr(I) <= transport ref_sosi_arr(I) after func_input_delay(I) * c_dp_clk_period;
end generate;
@@ -424,46 +426,46 @@ begin
------------------------------------------------------------------------------
u_mmp_dp_bsn_align : entity work.mmp_dp_bsn_align_v2
- generic map (
- g_nof_streams => c_nof_streams,
- g_bsn_latency_max => c_bsn_latency_max,
- g_nof_aligners_max => c_nof_aligners_max,
- g_block_size => c_block_size,
- g_bsn_w => c_bsn_w,
- g_data_w => c_data_w,
- g_data_replacement_value => c_data_replacement_value,
- g_use_mm_output => c_use_mm_output,
- g_pipeline_input => c_pipeline_input,
- g_pipeline_output => c_pipeline_output,
- g_rd_latency => c_rd_latency,
- g_nof_clk_per_sync => c_nof_clk_per_sync,
- g_nof_input_bsn_monitors => c_nof_input_bsn_monitors,
- g_use_bsn_output_monitor => c_use_bsn_output_monitor
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
-
- reg_input_monitor_copi => reg_input_monitor_copi,
- reg_input_monitor_cipo => reg_input_monitor_cipo,
-
- reg_output_monitor_copi => reg_output_monitor_copi,
- reg_output_monitor_cipo => reg_output_monitor_cipo,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- node_index => node_index,
- -- Streaming input
- in_sosi_arr => in_sosi_arr,
- -- Output via local MM in dp_clk domain
- --mm_sosi => mm_sosi,
- --mm_copi => mm_copi,
- --mm_cipo_arr => mm_cipo_arr,
- -- Output via streaming DP interface, when g_use_mm_output = TRUE.
- out_sosi_arr => out_sosi_arr
- );
+ generic map (
+ g_nof_streams => c_nof_streams,
+ g_bsn_latency_max => c_bsn_latency_max,
+ g_nof_aligners_max => c_nof_aligners_max,
+ g_block_size => c_block_size,
+ g_bsn_w => c_bsn_w,
+ g_data_w => c_data_w,
+ g_data_replacement_value => c_data_replacement_value,
+ g_use_mm_output => c_use_mm_output,
+ g_pipeline_input => c_pipeline_input,
+ g_pipeline_output => c_pipeline_output,
+ g_rd_latency => c_rd_latency,
+ g_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_nof_input_bsn_monitors => c_nof_input_bsn_monitors,
+ g_use_bsn_output_monitor => c_use_bsn_output_monitor
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_input_monitor_copi => reg_input_monitor_copi,
+ reg_input_monitor_cipo => reg_input_monitor_cipo,
+
+ reg_output_monitor_copi => reg_output_monitor_copi,
+ reg_output_monitor_cipo => reg_output_monitor_cipo,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ node_index => node_index,
+ -- Streaming input
+ in_sosi_arr => in_sosi_arr,
+ -- Output via local MM in dp_clk domain
+ --mm_sosi => mm_sosi,
+ --mm_copi => mm_copi,
+ --mm_cipo_arr => mm_cipo_arr,
+ -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+ out_sosi_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index 20d75a9e96538e0a879d3c595d753f01ea649bbf..ccceba7f7c37b609a50476dd3a3c4844c05bec75 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -26,15 +26,15 @@
-- . View *_64 BSN values as radix hex in Wave window to recognize BSN hi word.
library IEEE, common_lib, technology_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use common_lib.common_str_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use common_lib.common_str_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mmp_dp_bsn_sync_scheduler is
end tb_mmp_dp_bsn_sync_scheduler;
@@ -365,52 +365,52 @@ begin
-- Generate data blocks with input sync
u_stimuli : entity work.dp_stream_stimuli
- generic map (
- g_sync_period => c_nof_block_per_input_sync,
- g_err_init => 0,
- g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_channel_init => 0,
- g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
- g_nof_repeat => c_sim_nof_blocks,
- g_pkt_len => c_block_size,
- g_pkt_gap => c_input_gap_size
- )
- port map (
- rst => dp_rst,
- clk => dp_clk,
-
- -- Generate stimuli
- src_out => stimuli_sosi,
-
- -- End of stimuli
- tb_end => stimuli_end
- );
+ generic map (
+ g_sync_period => c_nof_block_per_input_sync,
+ g_err_init => 0,
+ g_err_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_channel_init => 0,
+ g_channel_incr => 0, -- do not increment, to not distract from viewing of BSN in Wave window
+ g_nof_repeat => c_sim_nof_blocks,
+ g_pkt_len => c_block_size,
+ g_pkt_gap => c_input_gap_size
+ )
+ port map (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ -- Generate stimuli
+ src_out => stimuli_sosi,
+
+ -- End of stimuli
+ tb_end => stimuli_end
+ );
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
- generic map (
- g_bsn_w => c_bsn_w,
- g_block_size => c_block_size,
- g_ctrl_interval_size_min => c_ctrl_interval_size_min
- )
- port map (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- -- MM control
- reg_mosi => reg_mosi,
- reg_miso => reg_miso,
-
- -- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_enable => out_enable
- );
+ generic map (
+ g_bsn_w => c_bsn_w,
+ g_block_size => c_block_size,
+ g_ctrl_interval_size_min => c_ctrl_interval_size_min
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- MM control
+ reg_mosi => reg_mosi,
+ reg_miso => reg_miso,
+
+ -- Streaming
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_enable => out_enable
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
index ad32c921763e7e4f7ca031c48eca53bc3964ff31..e9d86883f622d5833b80f5473da7ddb4ed26c73b 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
@@ -33,15 +33,15 @@
-- automatically.
library IEEE, common_lib, dp_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.common_lfsr_sequences_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use dp_lib.dp_stream_pkg.all;
-use dp_lib.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.common_lfsr_sequences_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use dp_lib.dp_stream_pkg.all;
+ use dp_lib.tb_dp_pkg.all;
entity tb_mms_dp_bsn_align is
generic (
@@ -166,7 +166,7 @@ begin
out_siso.xon <= '1';
out_siso.ready <= '1' when g_out_ready = e_active else
random(random'high) when g_out_ready = e_random else
- pulse when g_out_ready = e_pulse;
+ pulse when g_out_ready = e_pulse;
out_siso_arr <= (others => out_siso);
@@ -176,6 +176,7 @@ begin
-- Generate data path input data
gen_input : for I in g_nof_input - 1 downto 0 generate
+
p_stimuli : process
variable v_sync : std_logic := '0';
variable v_bsn : std_logic_vector(c_bsn_w - 1 downto 0) := c_bsn_init;
@@ -295,7 +296,7 @@ begin
verify_dis_arr <= (others => '0');
proc_common_wait_some_cycles(clk, 1000);
--- verify_dis_arr <= (OTHERS=>'1');
+ -- verify_dis_arr <= (OTHERS=>'1');
-- . enforce large BSN misalignment
tb_state <= s_large_bsn_diff;
@@ -304,8 +305,8 @@ begin
proc_common_wait_until_high(clk, bsn_event_ack);
bsn_event <= '0';
-- expect no output, because difference remains too large, so do not restart verify_en here and leave it commented:
--- proc_common_wait_some_cycles(clk, 100);
--- verify_dis_arr <= (OTHERS=>'0');
+ -- proc_common_wait_some_cycles(clk, 100);
+ -- verify_dis_arr <= (OTHERS=>'0');
proc_common_wait_some_cycles(clk, 1000);
verify_dis_arr <= (others => '1');
@@ -326,10 +327,10 @@ begin
tb_state <= s_disable_one_input;
verify_dis_arr <= (others => '1');
--- in_en_event <= '1';
+ -- in_en_event <= '1';
in_en_arr(c_event_input) <= '0'; -- switch an input off
--- proc_common_wait_some_cycles(clk, 1);
--- in_en_event <= '0';
+ -- proc_common_wait_some_cycles(clk, 1);
+ -- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
proc_mem_mm_bus_wr(c_event_input, x"0", mm_clk, mm_mosi);
@@ -340,10 +341,10 @@ begin
tb_state <= s_enable_inputs;
verify_dis_arr <= (others => '1');
--- in_en_event <= '1';
+ -- in_en_event <= '1';
in_en_arr(c_event_input) <= '1'; -- switch this input on
--- proc_common_wait_some_cycles(clk, 1);
--- in_en_event <= '0';
+ -- proc_common_wait_some_cycles(clk, 1);
+ -- in_en_event <= '0';
proc_common_wait_some_cycles(mm_clk, 1);
proc_mem_mm_bus_wr(c_event_input, x"1", mm_clk, mm_mosi);
@@ -377,7 +378,7 @@ begin
gen_verify : for I in g_nof_input - 1 downto 0 generate
-- Verification logistics
verify_en_arr(I) <= '1' when rising_edge(clk) and verify_dis_arr(I) = '0' and in_en_arr(I) = '1' and out_sosi_arr(I).sop = '1' else
- '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
+ '0' when rising_edge(clk) and verify_dis_arr(I) = '1'; -- verify enable after first output sop
-- Ease in_siso_arr monitoring
in_ready(I) <= in_siso_arr(I).ready;
@@ -422,29 +423,29 @@ begin
-- DUT
------------------------------------------------------------------------------
u_mms_bsn_align : entity work.mms_dp_bsn_align
- generic map (
- g_block_size => g_block_size,
- g_nof_input => g_nof_input,
- g_xoff_timeout => c_xoff_timeout,
- g_sop_timeout => c_sop_timeout,
- g_bsn_latency => g_bsn_latency,
- g_bsn_request_pipeline => g_bsn_request_pipeline,
- g_cross_clock_domain => true
- )
- port map (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => mm_mosi,
- reg_miso => mm_miso,
- -- Streaming clock domain
- dp_rst => rst,
- dp_clk => clk,
- -- ST sinks
- snk_out_arr => in_siso_arr,
- snk_in_arr => in_sosi_arr,
- -- ST source
- src_in_arr => out_siso_arr,
- src_out_arr => out_sosi_arr
- );
+ generic map (
+ g_block_size => g_block_size,
+ g_nof_input => g_nof_input,
+ g_xoff_timeout => c_xoff_timeout,
+ g_sop_timeout => c_sop_timeout,
+ g_bsn_latency => g_bsn_latency,
+ g_bsn_request_pipeline => g_bsn_request_pipeline,
+ g_cross_clock_domain => true
+ )
+ port map (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => mm_mosi,
+ reg_miso => mm_miso,
+ -- Streaming clock domain
+ dp_rst => rst,
+ dp_clk => clk,
+ -- ST sinks
+ snk_out_arr => in_siso_arr,
+ snk_in_arr => in_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr
+ );
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index 13cb45b509ea464702b6c627a0a84b91ed24fb89..55f6185d99839405403eb2b45110161a844d72ce 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -30,14 +30,14 @@
-- > view expanded bs_sosi in Wave window
library IEEE, common_lib, mm_lib;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use common_lib.common_pkg.all;
-use common_lib.tb_common_pkg.all;
-use common_lib.common_mem_pkg.all;
-use common_lib.tb_common_mem_pkg.all;
-use work.dp_stream_pkg.all;
-use work.tb_dp_pkg.all;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+ use common_lib.common_pkg.all;
+ use common_lib.tb_common_pkg.all;
+ use common_lib.common_mem_pkg.all;
+ use common_lib.tb_common_mem_pkg.all;
+ use work.dp_stream_pkg.all;
+ use work.tb_dp_pkg.all;
entity tb_mms_dp_bsn_source is
end tb_mms_dp_bsn_source;
@@ -83,97 +83,97 @@ begin
p_mm_stimuli : process
begin
- wait until rst = '0';
- proc_common_wait_some_cycles(clk, 10);
-
- -- Write initial BSN and number of block per sync interval
- proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
- proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- --------------------------------------------------------------------------
- -- DP on immediate
- --------------------------------------------------------------------------
-
- -- Wait until after PPS
- proc_common_wait_until_hi_lo(clk, pps);
-
- -- Write DP on immediate
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
-
- -- Read BSN twice in same PPS interval
- proc_common_wait_some_cycles(clk, 3 * c_block_size);
-
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
-
- proc_common_wait_some_cycles(clk, c_block_size);
-
- mm_bsn_prev <= mm_bsn;
- proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
- proc_common_wait_some_cycles(clk, 1);
-
- -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
- --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
- assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
-
- -- Run few sync intervals
- proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
-
- -- Write DP off
- proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
- proc_common_wait_some_cycles(clk, c_block_size);
-
- -- Read dp on status
- proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
- proc_mem_mm_bus_rd_latency(1, clk);
- mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
- proc_common_wait_some_cycles(clk, 1);
- assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
-
- proc_common_wait_some_cycles(clk, c_sync_interval);
- tb_end <= '1';
- wait;
+ wait until rst = '0';
+ proc_common_wait_some_cycles(clk, 10);
+
+ -- Write initial BSN and number of block per sync interval
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_lo, c_init_bsn, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_hi, 0, clk, mm_miso, mm_mosi); -- must also write hi part to trigger transfer accross clock domain
+ proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ --------------------------------------------------------------------------
+ -- DP on immediate
+ --------------------------------------------------------------------------
+
+ -- Wait until after PPS
+ proc_common_wait_until_hi_lo(clk, pps);
+
+ -- Write DP on immediate
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_on_immediate, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_on_immediate report "Wrong DP on status, expected DP on immediate." severity ERROR;
+
+ -- Read BSN twice in same PPS interval
+ proc_common_wait_some_cycles(clk, 3 * c_block_size);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ mm_bsn_prev <= mm_bsn;
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+ proc_common_wait_some_cycles(clk, 1);
+
+ -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
+ --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
+ assert mm_bsn_prev = mm_bsn report "Wrong BSN, expected constant BSN during PPS or sync interval." severity ERROR;
+
+ -- Run few sync intervals
+ proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
+
+ -- Write DP off
+ proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, c_block_size);
+
+ -- Read dp on status
+ proc_mem_mm_bus_rd(c_mm_addr_dp_on, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_dp_on_status <= TO_UINT(mm_miso.rddata(1 downto 0));
+ proc_common_wait_some_cycles(clk, 1);
+ assert mm_dp_on_status = c_mm_dp_off report "Wrong DP on status, expected DP off." severity ERROR;
+
+ proc_common_wait_some_cycles(clk, c_sync_interval);
+ tb_end <= '1';
+ wait;
end process;
u_dut : entity work.mms_dp_bsn_source
- generic map (
- g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_block_size => c_block_size,
- g_nof_block_per_sync => 1, -- overrule via MM write
- g_bsn_w => c_dp_stream_bsn_w
- )
- port map (
- -- Clocks and reset
- mm_rst => rst,
- mm_clk => clk,
- dp_rst => rst,
- dp_clk => clk,
- dp_pps => pps,
-
- -- Memory-mapped clock domain
- reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
- reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
+ generic map (
+ g_cross_clock_domain => true, -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+ g_block_size => c_block_size,
+ g_nof_block_per_sync => 1, -- overrule via MM write
+ g_bsn_w => c_dp_stream_bsn_w
+ )
+ port map (
+ -- Clocks and reset
+ mm_rst => rst,
+ mm_clk => clk,
+ dp_rst => rst,
+ dp_clk => clk,
+ dp_pps => pps,
+
+ -- Memory-mapped clock domain
+ reg_mosi => mm_mosi, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+ reg_miso => mm_miso, -- actual ranges defined by c_mm_reg in dp_bsn_source_reg
+
+ -- Streaming clock domain
+ bs_sosi =>