diff --git a/applications/lofar2/designs/.gitignore b/applications/lofar2/designs/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..00bdd025b727d6ba26b2d269775fbf79095fc9bc
--- /dev/null
+++ b/applications/lofar2/designs/.gitignore
@@ -0,0 +1,5 @@
+*/*.aoco
+*/*.aocr
+*/*.aocx
+*/*.sof
+*/*.rbf
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
index 373f67c336f362db51b0f2c07bb4ad4119d930d5..931256ec79ceeb609fb5b78dc9e34fe1ede25322 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/lofar2_unb2b_adc.fpga.yaml
@@ -18,7 +18,7 @@ peripherals:
- peripheral_name: unb2b_board/wdi
mm_port_names:
- - PIO_WDI
+ - REG_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 96e3c42900bd80357dc8c4f7ef22ca834fa67a6e..77501b43b2fd78bdc0690189682e352ae11ff8c6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -86,9 +86,9 @@ ENTITY node_adc_input_and_timing IS
reg_bsn_monitor_input_miso : OUT t_mem_miso;
-- Data buffer for raw samples
- ram_diag_data_buf_jesd_mosi : IN t_mem_mosi;
+ ram_diag_data_buf_jesd_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_jesd_miso : OUT t_mem_miso;
- reg_diag_data_buf_jesd_mosi : IN t_mem_mosi;
+ reg_diag_data_buf_jesd_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_jesd_miso : OUT t_mem_miso;
-- Data buffer for framed samples (variable depth)
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
index 674f5ceb675cef28356a62c13099580c279a810f..14218e8d3d3e96e1716b2418c849465390c4b3ff 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.fpga.yaml
@@ -45,7 +45,7 @@ peripherals:
- peripheral_name: unb2b_board/wdi
mm_port_names:
- - PIO_WDI
+ - REG_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
mm_port_names:
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
index b9b96a2c4acb2059c6cce74b2e31e4453fbb1031..c7da0c5726d09d2034d4d111993bccdf20b3de50 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -18,7 +18,7 @@ peripherals:
- peripheral_name: unb2b_board/wdi
mm_port_names:
- - PIO_WDI
+ - REG_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
mm_port_names:
@@ -105,14 +105,14 @@ peripherals:
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
mm_port_names:
- - REG_DIAG_WG
- - RAM_DIAG_WG
+ - REG_WG
+ - RAM_WG
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: 12 } # = S_pn
mm_port_names:
- - REG_ADUH_MON
+ - REG_ADUH_MONITOR
# Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
#- peripheral_name: aduh/aduh_mon_data_buffer
@@ -172,4 +172,4 @@ peripherals:
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
mm_port_names:
- - REG_STAT_HDR_INFO
+ - REG_STAT_HDR_DAT
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
index 366e44d371e5ae91aa9d1e4e26418a2c3cdfb328..1fcb0f917bb41c2a552759bd999c72a91a137e7e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
@@ -1018,7 +1018,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>18</spirit:right>
+ <spirit:right>19</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -2153,7 +2153,7 @@
<spirit:parameter>
<spirit:name>dataAddrWidth</spirit:name>
<spirit:displayName>dataAddrWidth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataAddrWidth">19</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="dataAddrWidth">20</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0AddrWidth</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_wg.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x80000' end='0x82000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2368,7 +2368,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">19</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">20</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</spirit:name>
@@ -2668,7 +2668,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>19</width>
+ <width>20</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -3489,11 +3489,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_wg.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x80000' end='0x82000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>19</value>
+ <value>20</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
index 397f28f6c14859580d6cf52f7f213bc5fad2d497..ba53d7b3f51c4e23f261590aafddab4effb19d57 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>9</spirit:right>
+ <spirit:right>12</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>9</spirit:right>
+ <spirit:right>12</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -854,7 +854,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -918,7 +918,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -987,7 +987,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1382,11 +1382,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>12</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
index 5789d953891f37af312dfa2809a09eb454675365..983451d8bc8cdcf186ea15e608f98671863f455f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/qsys_lofar2_unb2b_filterbank.qsys
@@ -22,7 +22,7 @@
{
datum baseAddress
{
- value = "499712";
+ value = "8192";
type = "String";
}
}
@@ -38,7 +38,7 @@
{
datum baseAddress
{
- value = "8192";
+ value = "4096";
type = "String";
}
}
@@ -223,7 +223,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "98304";
type = "String";
}
}
@@ -239,7 +239,7 @@
{
datum baseAddress
{
- value = "262144";
+ value = "327680";
type = "String";
}
}
@@ -255,7 +255,7 @@
{
datum baseAddress
{
- value = "491520";
+ value = "524288";
type = "String";
}
}
@@ -287,7 +287,7 @@
{
datum baseAddress
{
- value = "327680";
+ value = "393216";
type = "String";
}
}
@@ -319,7 +319,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "458752";
type = "String";
}
}
@@ -335,7 +335,7 @@
{
datum baseAddress
{
- value = "65536";
+ value = "262144";
type = "String";
}
}
@@ -802,7 +802,7 @@
}
datum sopceditor_expanded
{
- value = "0";
+ value = "1";
type = "boolean";
}
}
@@ -815,7 +815,7 @@
}
datum baseAddress
{
- value = "4096";
+ value = "65536";
type = "String";
}
}
@@ -4083,7 +4083,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>19</width>
+ <width>20</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -5172,11 +5172,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_wg.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x70000' end='0x78000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x78000' end='0x7A000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x7A000' end='0x7B000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_wg.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x300' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buf_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3300' end='0x3340' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3340' end='0x3380' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3380' end='0x33A0' datawidth='32' /><slave name='reg_epcs.mem' start='0x33A0' end='0x33C0' datawidth='32' /><slave name='reg_remu.mem' start='0x33C0' end='0x33E0' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x33E0' end='0x33F0' datawidth='32' /><slave name='reg_diag_data_buf_jesd.mem' start='0x33F0' end='0x3400' datawidth='32' /><slave name='reg_stat_enable.mem' start='0x3400' end='0x3408' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3408' end='0x3410' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3410' end='0x3418' datawidth='32' /><slave name='reg_si.mem' start='0x3418' end='0x3420' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3420' end='0x3428' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3428' end='0x3430' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3430' end='0x3438' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3438' end='0x3440' datawidth='32' /><slave name='pio_pps.mem' start='0x3440' end='0x3448' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3448' end='0x3450' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='jesd204b.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_aduh_monitor.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_wg.mem' start='0x40000' end='0x50000' datawidth='32' /><slave name='ram_diag_data_buf_bsn.mem' start='0x50000' end='0x60000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buf_jesd.mem' start='0x80000' end='0x82000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>19</value>
+ <value>20</value>
</entry>
</consumedSystemInfos>
</value>
@@ -5296,7 +5296,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
- <value>19</value>
+ <value>20</value>
</entry>
<entry>
<key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
@@ -29387,7 +29387,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29451,7 +29451,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29520,7 +29520,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29926,11 +29926,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>12</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30736,7 +30736,7 @@
version="18.0"
start="cpu_0.data_master"
end="rom_system_info.mem">
- <parameter name="baseAddress" value="0x1000" />
+ <parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="avalon"
@@ -30827,7 +30827,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00070000" />
</connection>
<connection
kind="avalon"
@@ -30841,7 +30841,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00050000" />
+ <parameter name="baseAddress" value="0x00060000" />
</connection>
<connection
kind="avalon"
@@ -30855,7 +30855,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_diag_data_buf_jesd.mem">
- <parameter name="baseAddress" value="0x00078000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
@@ -30869,7 +30869,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
@@ -30883,7 +30883,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_diag_data_buf_bsn.mem">
- <parameter name="baseAddress" value="0x00040000" />
+ <parameter name="baseAddress" value="0x00050000" />
</connection>
<connection
kind="avalon"
@@ -30897,7 +30897,7 @@
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x00010000" />
+ <parameter name="baseAddress" value="0x00040000" />
</connection>
<connection
kind="avalon"
@@ -30988,7 +30988,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
- <parameter name="baseAddress" value="0x0007a000" />
+ <parameter name="baseAddress" value="0x2000" />
</connection>
<connection
kind="avalon"
@@ -31002,7 +31002,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_tse">
- <parameter name="baseAddress" value="0x2000" />
+ <parameter name="baseAddress" value="0x1000" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index eb53db17a7e9dfefd618e24c09ea64c3f99e9f0e..cc013d2f75c46079af825d5facdd4a7f7eab65d5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -109,7 +109,7 @@ ARCHITECTURE str OF lofar2_unb2b_filterbank IS
CONSTANT c_dp_clk_freq : NATURAL := c_revision_select.dp_clk_freq;
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (2, 0);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index a0280460a0f7dd5971d4d375b75c8582134d8df8..35e8ae29785f10bb64345f6dcf882b3274a86fc4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -286,7 +286,7 @@ BEGIN
u_mm_file_reg_stat_enable : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
PORT MAP(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
- u_mm_file_reg_stat_hdr_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_INFO")
+ u_mm_file_reg_stat_hdr_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
----------------------------------------------------------------------------
@@ -365,9 +365,7 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
--- ToDo: This has changed in the peripherals package
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index e15bdce19d10082f87dd9c41060afeb367a6f36d..efb2b9af91f7e9ff7972b6b943ccff9b42a52513 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -298,7 +298,7 @@ PACKAGE qsys_lofar2_unb2b_filterbank_pkg IS
reg_wg_write_export : out std_logic; -- export
reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
rom_system_info_clk_export : out std_logic; -- export
rom_system_info_read_export : out std_logic; -- export
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..fca2daaed30f712ecca86478cd0c8fbf984958fa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
@@ -0,0 +1,121 @@
+######################
+### SETUP ###
+######################
+ifeq ($(VERBOSE),1)
+ECHO :=
+else
+ECHO := @
+endif
+
+# Where is the Intel(R) FPGA SDK for OpenCL(TM) software?
+ifeq ($(wildcard $(INTELFPGAOCLSDKROOT)),)
+$(error Set INTELFPGAOCLSDKROOT to the root directory of the Intel(R) FPGA SDK for OpenCL(TM) software installation)
+endif
+ifeq ($(wildcard $(INTELFPGAOCLSDKROOT)/host/include/CL/opencl.h),)
+$(error Set INTELFPGAOCLSDKROOT to the root directory of the Intel(R) FPGA SDK for OpenCL(TM) software installation.)
+endif
+
+###########################
+### Basic configuration ###
+###########################
+
+# Name of unb2b BSP
+UNB2B_BSP=lofar2_unb2b_ring_bsp
+
+# Compile directory
+BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+
+
+##############################
+### Advanced Configuration ###
+##############################
+
+CXX= g++ #-mcmodel=medium
+CXXFLAGS= -std=c++11 -mavx2 -g -O3 -fopenmp #-DCL_ALTERA
+AOC= aoc
+AOCFLAGS= -v -g
+#AOCRFLAGS+= -fp-relaxed
+AOCRFLAGS+= -report
+AOCOFLAGS+= -Wno-error=analyze-channels-usage
+AOCRFLAGS+= -opt-arg=-allow-io-channel-autorun-kernel
+#AOCRFLAGS+= -board=p385a_min_ax115_1710240
+AOCOFLAGS+= -board=$(UNB2B_BSP)
+
+AOCOFLAGS+= -I$(INTELOCLSDKROOT)/include/kernel_headers
+AOCXFLAGS+= -bsp-flow=flat
+ifneq ("$(SEED)", "")
+AOCXFLAGS+= -seed=$(SEED)
+endif
+INCLUDES= $(shell aocl compile-config) #-I..
+LDFLAGS= $(shell aocl link-config) #-ldl -lacl_emulator_kernel_rt #-lbfd
+CXXFLAGS+= $(INCLUDES)
+
+### Emulator configuration
+# Emulation Compilation flags
+ifeq ($(DEBUG),1)
+EMUCXXFLAGS += -g
+else
+EMUCXXFLAGS += -O2
+endif
+
+# Target
+TARGET := host
+TARGET_DIR := $(BUILDDIR)/bin
+
+# Directories
+INC_DIRS := host/lib/common/inc
+LIB_DIRS :=
+
+# Files
+INCS := $(wildcard )
+SRCS := $(wildcard host/src/*.cpp host/lib/common/src/*.cpp host/lib/common/src/AOCLUtils/*.cpp)
+LIBS := rt pthread
+
+### Emulator compilation
+# Make it all!
+%: %.cl $(TARGET_DIR)/$(TARGET)
+ (unset DISPLAY; mkdir -p $(BUILDDIR)/$* && $(AOC) -march=emulator -DEMULATOR $< -o $(TARGET_DIR)/$@.aocx -legacy-emulator $(AOCOFLAGS) $(AOCRFLAGS))
+
+# Host executable target.
+$(TARGET_DIR)/$(TARGET) : Makefile $(SRCS) $(INCS) $(TARGET_DIR)
+ $(ECHO)$(CXX) $(CPPFLAGS) $(CXXFLAGS) -fPIC $(foreach D,$(INC_DIRS),-I$D) \
+ $(INCLUDES) $(SRCS) $(LDFLAGS) \
+ $(foreach D,$(LIB_DIRS),-L$D) \
+ $(foreach L,$(LIBS),-l$L) \
+ -o $(TARGET_DIR)/$(TARGET)
+
+$(TARGET_DIR) :
+ $(ECHO)mkdir -p $(TARGET_DIR)
+
+# Standard make targets
+clean :
+ $(ECHO)rm -rf $(TARGET_DIR)/*
+
+
+### Device compilation
+%.d: %.cc
+ -$(CXX) $(CXXFLAGS) -MM -MT $@ -MT ${@:%.d=%.o} $< -o $@
+
+%.o: %.cc
+ $(CXX) -c $(CXXFLAGS) -o $@ $<
+
+%.aoco: %.cl
+ (unset DISPLAY; mkdir -p $(BUILDDIR)/$* && cp -a $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) -c $(AOCOFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.aocr: %.aoco
+ (unset DISPLAY; cp -a $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) -rtl $(AOCRFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.aocx: %.aocr
+ (unset DISPLAY; cp -a $< $(BUILDDIR)/$* && cd $(BUILDDIR)/$* && $(AOC) $(AOCXFLAGS) $< && cd - && cp -a $(BUILDDIR)/$*/$@ .)
+
+%.sof: %.aocx
+ (unset DISPLAY; cp -a $(BUILDDIR)/$*/flat.sof ./$@)
+
+%.rbf: %.sof
+ (unset DISPLAY; cp -a $(BUILDDIR)/$*/flat.rbf ./$@)
+
+
+%.build:
+ test -f $@ || test -f /tmp/stop || (echo `hostname` && cp `basename $* _$(lastword $(subst _, ,$*))`.cl $*.cl && SEED=$(lastword $(subst _, ,$*)) time make -j1 $*.aocx && fgrep MHz $(BUILDDIR)/$*/$*/quartus_sh_compile.log|tail -n 1) >$@ 2>&1
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h
new file mode 100644
index 0000000000000000000000000000000000000000..d16ade9618880b8bba4bfcbd42b218f6efb69773
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/inc/common.h
@@ -0,0 +1,48 @@
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <iomanip>
+
+#define CL_HPP_ENABLE_EXCEPTIONS
+#define CL_HPP_MINIMUM_OPENCL_VERSION 120
+#define CL_HPP_TARGET_OPENCL_VERSION 120
+#define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY
+#include <CL/cl2.hpp>
+
+void init(
+ cl::Context &context,
+ std::vector<cl::Device> &devices);
+
+void print_platform(
+ cl::Platform &platform);
+
+void print_device(
+ cl::Device &device,
+ bool marker = false);
+
+std::string get_source(
+ std::string& filename);
+
+std::string get_flags();
+
+cl::Program compile_program(
+ cl::Context& context,
+ cl::Device& device,
+ std::string& source);
+
+void write_source(
+ std::string& source,
+ std::string& filename);
+
+cl::Program get_program(
+ cl::Context& context,
+ cl::Device& device,
+ std::string& filename);
+
+cl::Kernel get_kernel(
+ cl::Program& program,
+ std::string& name);
+
+double compute_runtime(
+ cl::Event& start,
+ cl::Event& end);
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css
new file mode 100644
index 0000000000000000000000000000000000000000..ce1c649289c93957c5eeefe2dec8a7b9d8b7d36a
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/readme.css
@@ -0,0 +1,261 @@
+/*
+Copyright (C) 2013-2018 Altera Corporation, San Jose, California, USA. All rights reserved.
+Permission is hereby granted, free of charge, to any person obtaining a copy of this
+software and associated documentation files (the "Software"), to deal in the Software
+without restriction, including without limitation the rights to use, copy, modify, merge,
+publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to
+whom the Software is furnished to do so, subject to the following conditions:
+The above copyright notice and this permission notice shall be included in all copies or
+substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+This agreement shall be governed in all respects by the laws of the State of California and
+by the laws of the United States of America.
+*/
+
+body {
+ margin: 0 1em 1em 1em;
+ font-family: sans-serif;
+}
+ul {
+ list-style-type: square;
+}
+pre, code, kbd, samp, tt {
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+}
+
+h1 {
+ font-size: 200%;
+ color: #fff;
+ background-color: #0067a6;
+ margin: 0 -0.5em;
+ padding: 0.25em 0.5em;
+}
+h1 .preheading {
+ font-size: 40%;
+ font-weight: normal;
+}
+h2 {
+ font-size: 125%;
+ background-color: #bae5ff;
+ margin: 1.5em -0.8em 0 -0.8em;
+ padding: 0.2em 0.8em;
+}
+h3 {
+ margin-top: 1.5em;
+ font-size: 100%;
+ border-bottom: 1px dotted #000;
+}
+
+table {
+ border: 2px solid #0067a6;
+ border-collapse: collapse;
+}
+th {
+ border-bottom: 1px solid #0067a6;
+ border-left: 1px dotted #0067a6;
+ border-right: 1px dotted #0067a6;
+ background-color: #bae5ff;
+ padding: 0.3em;
+ font-size: 90%;
+}
+td {
+ padding: 0.3em;
+ border: 1px dotted #0067a6;
+}
+
+table.reqs {
+ margin: 0 auto;
+}
+table.reqs td {
+ white-space: nowrap;
+ text-align: center;
+}
+table.reqs td:first-child,
+table.reqs tr:first-child th:first-child {
+ text-align: left;
+}
+table.reqs td.req {
+ background-color: #b3ef71;
+ font-size: 150%;
+ padding: 0 0.3em;
+}
+table.reqs td.req .either {
+ font-size: 50%;
+}
+table.reqs td.unsupported {
+ white-space: normal;
+ background-color: #ccc;
+ max-width: 20em;
+}
+table.reqs a.note {
+ text-decoration: none;
+}
+ol.req-notes > li {
+ margin-bottom: 0.75em;
+}
+
+table.history {
+ margin: 0 auto;
+}
+table.history td {
+ text-align: center;
+ vertical-align: top;
+}
+table.history .changes {
+ text-align: left;
+}
+table.history tbody tr:first-child td {
+ background-color: #b3ef71;
+}
+table.history ul {
+ margin: 0;
+ padding-left: 1em;
+}
+
+table.pkg-contents {
+ margin: 0 auto;
+}
+table.pkg-contents th,
+table.pkg-contents td {
+ text-align: left;
+ vertical-align: top;
+}
+table.pkg-contents td.path {
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+}
+table.pkg-contents tr.highlight td {
+ background-color: #ffc;
+ font-weight: bold;
+ color: #000;
+}
+table.pkg-contents td p:first-child {
+ margin-top: 0;
+}
+table.pkg-contents td p:last-child {
+ margin-bottom: 0;
+}
+
+table.parameters {
+ margin-left: 3em;
+ margin-right: 3em;
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+}
+table.parameters th,
+table.parameters td {
+ font-family: sans-serif;
+ text-align: center;
+ vertical-align: top;
+}
+table.parameters .name,
+table.parameters .desc {
+ text-align: left;
+}
+table.parameters .name {
+ white-space: nowrap;
+}
+table.parameters td.name,
+table.parameters td.default {
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+}
+table.parameters ul {
+ margin-top: 0;
+}
+table.parameters td ul:last-child {
+ margin-bottom: 0;
+}
+
+table.indent {
+ margin-left: 3em;
+}
+
+.doc .title {
+ background-color: #eee;
+ padding: 0.35em;
+ margin-bottom: 0.5em;
+}
+.doc .title a {
+ font-weight: bold;
+}
+.doc .desc {
+ margin-left: 2em;
+ margin-right: 2em;
+}
+
+.left {
+ text-align: left;
+}
+.center {
+ text-align: center;
+}
+.right {
+ text-align: right;
+}
+
+.mono {
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+}
+.highlight {
+ font-weight: bold;
+ color: #0067a6;
+}
+.nowrap {
+ white-space: nowrap;
+}
+
+.command {
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+ margin: 0 3em;
+ background-color: #ffc;
+ border: 1px solid #aaa;
+ padding: 0.5em 1em;
+}
+.console-output,
+.code-block {
+ display: block;
+ font-family: monospace, sans-serif;
+ font-size: 1em;
+ margin: 0 3em;
+ background-color: #fff;
+ border: 1px solid #aaa !important;
+ padding: 1.8em 1em 0.5em 1em !important;
+ position: relative;
+}
+.console-output .heading,
+.code-block .heading {
+ position: absolute;
+ left: 0;
+ top: 0;
+ width: 100%;
+ font-size: 80%;
+ text-transform: uppercase;
+ background-color: #e8e8e8;
+ padding: 0.3125em 0;
+ border-bottom: 1px dotted #888;
+}
+.console-output .heading span,
+.code-block .heading span {
+ padding: 0 1.25em;
+}
+.not-released {
+ font-weight: bold;
+ color: red;
+}
+.license,
+.trademark {
+ font-size: 80%;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..928b8534b95239c6fa0a29f27640984e5605de17
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/lib/common/src/common.cpp
@@ -0,0 +1,189 @@
+#include "common.h"
+
+using namespace std;
+
+ostream &os = clog;
+
+void init(
+ cl::Context &context,
+ vector<cl::Device> &devices)
+{
+ vector<cl::Platform> platforms;
+ cl::Platform::get(&platforms);
+
+ // The selected device
+ int i = 0;
+ const char *platform_name = getenv("PLATFORM");
+
+ if (platform_name == 0)
+ platform_name = getenv("CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA") ? "Intel(R) FPGA Emulation Platform for OpenCL(TM)" : "Intel(R) FPGA SDK for OpenCL(TM)";
+
+ os << ">>> OpenCL environment: " << endl;
+
+ // Iterate all platforms
+ for (cl::Platform &platform : platforms) {
+ print_platform(platform);
+ bool selected = platform.getInfo<CL_PLATFORM_NAME>() == platform_name;
+
+ // Get devices for the current platform
+ vector<cl::Device> devices_;
+ platform.getDevices(CL_DEVICE_TYPE_ALL, &devices_);
+
+ // Iterate all devices
+ for (cl::Device &device : devices_) {
+ if (true)//(selected)
+ devices.push_back(device);
+
+ print_device(device, selected);
+ i++;
+ }
+ }
+ os << endl;
+
+ if (devices.size() == 0) {
+ cerr << "Could not find any device in platform " << platform_name << endl;
+ exit(EXIT_FAILURE);
+ }
+
+ context = cl::Context(devices);
+}
+
+void print_platform(
+ cl::Platform &platform)
+{
+ os << ">>> Platform: " << endl;
+ os << "Name : " << platform.getInfo<CL_PLATFORM_NAME>() << endl;
+ os << "Version : " << platform.getInfo<CL_PLATFORM_VERSION>() << endl;
+ os << "Extensions : " << platform.getInfo<CL_PLATFORM_EXTENSIONS>() << endl;
+ os << endl;
+}
+
+void print_device(
+ cl::Device &device,
+ bool marker)
+{
+ os << ">>> Device: ";
+ if (marker) os << " (selected)";
+ os << endl;
+ os << "Name : " << device.getInfo<CL_DEVICE_NAME>() << endl;
+ os << "Driver version : " << device.getInfo<CL_DRIVER_VERSION>() << endl;
+ os << "Device version : " << device.getInfo<CL_DEVICE_VERSION>() << endl;
+ os << "Compute units : " << device.getInfo<CL_DEVICE_MAX_COMPUTE_UNITS>() << endl;
+ os << "Clock frequency : " << device.getInfo<CL_DEVICE_MAX_CLOCK_FREQUENCY>() << " MHz" << endl;
+ os << "Global memory : " << device.getInfo<CL_DEVICE_GLOBAL_MEM_SIZE>() * 1e-9 << " Gb" << endl;
+ os << "Local memory : " << device.getInfo<CL_DEVICE_LOCAL_MEM_SIZE>() * 1e-6 << " Mb" << endl;
+ os << endl;
+}
+
+string get_source(
+ string& filename)
+{
+ // Source directory
+ string srcdir = "./cl";
+
+ // All helper files to include in build
+ vector<string> helper_files;
+ helper_files.push_back("types.cl");
+ helper_files.push_back("math.cl");
+
+ // Store helper files in string
+ stringstream source_helper_;
+
+ for (int i = 0; i < helper_files.size(); i++) {
+ // Get source filename
+ stringstream source_file_name_;
+ source_file_name_ << srcdir << "/" << helper_files[i];
+ string source_file_name = source_file_name_.str();
+
+ // Read source from file
+ ifstream source_file(source_file_name.c_str());
+ string source(istreambuf_iterator<char>(source_file),
+ (istreambuf_iterator<char>()));
+ source_file.close();
+
+ // Update source helper stream
+ source_helper_ << source;
+ }
+
+ string source_helper = source_helper_.str();
+
+ // Get source filename
+ stringstream source_file_name_;
+ source_file_name_ << srcdir << "/" << filename;
+ string source_file_name = source_file_name_.str();
+
+ // Read kernel source from file
+ ifstream source_file(source_file_name.c_str());
+ string source_kernel(
+ istreambuf_iterator<char>(source_file),
+ (istreambuf_iterator<char>()));
+ source_file.close();
+
+ // Construct full source file
+ stringstream full_source;
+ full_source << source_helper;
+ full_source << source_kernel;
+
+ return full_source.str();
+}
+
+string get_flags()
+{
+ return string("-cl-fast-relaxed-math");
+}
+
+void write_source(
+ string& source,
+ string& filename)
+{
+ cout << ">>> Writing source to: " << filename << endl
+ << endl;
+ ofstream source_output;
+ source_output.open(filename, ofstream::out);
+ source_output << source;
+ source_output.close();
+}
+
+cl::Program get_program(
+ cl::Context& context,
+ cl::Device& device,
+ string& filename)
+{
+ os << ">>> Loading program from binary: " << filename << endl;
+ try {
+ ifstream ifs(filename, ios::in | ios::binary);
+ string str((istreambuf_iterator<char>(ifs)), istreambuf_iterator<char>());
+ cl::Program::Binaries binaries(1, std::make_pair(str.c_str(), str.length()));
+ vector<cl::Device> devices;
+ devices.push_back(device);
+ os << endl;
+ return cl::Program(context, devices, binaries);
+ } catch (cl::Error& error) {
+ cerr << "Loading binary failed: " << error.what() << endl;
+ exit(EXIT_FAILURE);
+ }
+}
+
+cl::Kernel get_kernel(
+ cl::Program& program,
+ string& name)
+{
+ os << ">>> Loading kernel: " << name << endl;
+ try {
+ os << endl;
+ return cl::Kernel(program, name.c_str());
+ } catch (cl::Error& error) {
+ cerr << "Loading kernel failed: " << error.what() << endl;
+ exit(EXIT_FAILURE);
+ }
+}
+
+double compute_runtime(
+ cl::Event& start,
+ cl::Event& end)
+{
+ double runtime = 0;
+ runtime -= start.getProfilingInfo<CL_PROFILING_COMMAND_START>();
+ runtime += end.getProfilingInfo<CL_PROFILING_COMMAND_START>();
+ return runtime * 1e-9;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..a26be673bb31499f785593cb7defdacb6c700d78
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
@@ -0,0 +1,152 @@
+/* *************************************************************************
+* Copyright 2021
+* ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+* P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* *********************************************************************** */
+
+/* *************************************************************************
+* Author:
+* . Reinier vd Walle
+* Purpose:
+* . Test the lofar2_unb2b_ring OpenCL application in emulator
+* Description:
+* . Run: -> make lofar2_unb2b_ring
+* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
+* . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
+* *********************************************************************** */
+#include <CL/cl_ext_intelfpga.h>
+#include <iostream>
+#include <fstream>
+#include <vector>
+#include "common.h"
+#include <unistd.h>
+
+using namespace std;
+int main(int argc, char **argv)
+{
+ if (argc > 2) {
+ cerr << "usage: " << argv[0] << " [lofar2_unb2b_ring.aocx]" << endl;
+ exit(1);
+ }
+
+ // Initialize OpenCL
+ cl::Context context;
+ vector<cl::Device> devices;
+ init(context, devices);
+ cl::Device &device = devices[0];
+
+ // Get program
+ string filename_bin = string(argc == 2 ? argv[1] : "lofar2_unb2b_ring.aocx");
+ cl::Program program = get_program(context, device, filename_bin);
+
+
+ // Setup command queues
+ vector<cl::CommandQueue> queues(8);
+
+ for (cl::CommandQueue &queue : queues) {
+ queue = cl::CommandQueue(context, device, CL_QUEUE_PROFILING_ENABLE);
+ }
+
+ cl::Event computeDone[8];
+
+ // Setup FPGA kernels
+ cl::Kernel mmInController(program, "mm_in_controller");
+ cl::Kernel mmOutController(program, "mm_out_controller");
+ cl::Kernel interfaceSelect(program, "interface_select");
+ cl::Kernel blockValidateDecode(program, "block_validate_decode");
+ cl::Kernel rxSplit(program, "rx_split");
+ cl::Kernel validateBsnAtSync(program, "validate_bsn_at_sync");
+// cl::Kernel noValidateBsnAtSync(program, "no_validate_bsn_at_sync");
+ cl::Kernel validateChannel(program, "validate_channel");
+// cl::Kernel noValidateChannel(program, "no_validate_channel");
+ cl::Kernel txEncode(program, "tx_encode");
+
+ // Run FPGA kernels
+ clog << ">>> Run fpga" << endl;
+ try {
+ queues[0].enqueueTask(txEncode, nullptr, &computeDone[0]);
+ queues[1].enqueueTask(validateChannel, nullptr, &computeDone[1]);
+ queues[2].enqueueTask(validateBsnAtSync, nullptr, &computeDone[2]);
+ queues[3].enqueueTask(rxSplit, nullptr, &computeDone[3]);
+ queues[4].enqueueTask(blockValidateDecode, nullptr, &computeDone[4]);
+ queues[5].enqueueTask(interfaceSelect, nullptr, &computeDone[5]);
+ queues[6].enqueueTask(mmOutController, nullptr, &computeDone[6]);
+ queues[7].enqueueTask(mmInController, nullptr, &computeDone[7]);
+
+ } catch (cl::Error &error) {
+ cerr << "Error launching kernel: " << error.what() << endl;
+ exit(EXIT_FAILURE);
+ }
+
+ // Write IO channel file
+ // Input packet channel = 1
+ vector<unsigned char> inputVecs[] = {{0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0xAA, 0xBB, 0x01, 0x00, 0x00, 0x00, 0x00}, //First
+ {0xCC, 0xDD, 0xEE, 0xFF, 0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x02, 0x00, 0x00, 0x00, 0x00}}; // Last
+
+ // dp lane input, channel = 0
+ vector<unsigned char> dpVecs[] = {{'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},//First
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}; // Last
+
+
+ ofstream output_fileA("kernel_input_10GbE_ring_0");
+ ostream_iterator<char> output_iteratorA(output_fileA, "");
+ for (int i = 0; i < 11; i++)
+ copy(inputVecs[i].begin(), inputVecs[i].end(), output_iteratorA);
+
+ output_fileA.close();
+
+ ofstream output_fileX("kernel_input_lane_0");
+ ostream_iterator<char> output_iteratorX(output_fileX, "");
+ for (int i = 0; i < 8; i++)
+ copy(dpVecs[i].begin(), dpVecs[i].end(), output_iteratorX);
+
+ output_fileX.close();
+
+
+ clog << ">>> Written IO files" << endl;
+
+ // wait for validate_bsn_at_sync to be finished
+ computeDone[2].wait();
+
+ // print output IO channel file
+ const string inputFileB = "kernel_output_lane_0";
+ ifstream fileB(inputFileB);
+ clog << fileB.rdbuf() << endl;
+
+ // wait for interface_select to be finished
+ computeDone[5].wait();
+
+ // print output IO channel file
+ const string inputFileY = "kernel_output_10GbE_ring_0";
+ ifstream fileY(inputFileY);
+ clog << fileY.rdbuf() << endl;
+
+ return EXIT_SUCCESS;
+}
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl
new file mode 100644
index 0000000000000000000000000000000000000000..b2f0baeee6bf008a08e10f6989b151cebfce7c16
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/lofar2_unb2b_ring.cl
@@ -0,0 +1,889 @@
+/* *************************************************************************
+* Copyright 2021
+* ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+* P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* *********************************************************************** */
+
+/* *************************************************************************
+* Author:
+* . Reinier vd Walle
+* Purpose:
+* . Implements ring network functionality for UniBoard2b as part of Lofar2
+* *********************************************************************** */
+
+#pragma OPENCL EXTENSION cl_intel_channels : enable
+
+#include <ihc_apint.h>
+
+// Directives
+#define DIVIDE_AND_ROUND_UP(A,B) (((A)+(B)-1)/(B))
+#define FLAG_FIRST 0x01
+#define FLAG_LAST 0x02
+#define FLAG_SYNC 0x04
+#define MASK_BSN 0x7FFFFFFFFFFFFFFF
+#define MASK_SYNC 0x8000000000000000
+#define LANE_DIRECTION 1
+// Nof lanes = 1 - 8
+#define NOF_LANES 8
+#define USE_DP_LAYER
+#define ETH_HEADER_SIZE 2
+#define DP_HEADER_SIZE 3
+#ifdef EMULATOR
+#define PAYLOAD_SIZE 8
+#else
+#define PAYLOAD_SIZE 750 // = 750*8 bytes = 6000 bytes
+#endif
+#ifdef USE_DP_LAYER
+#define BLOCK_LENGTH (PAYLOAD_SIZE+DP_HEADER_SIZE)
+#else
+#define BLOCK_LENGTH (PAYLOAD_SIZE+ETH_HEADER_SIZE)
+#endif
+
+#define ERR_BI 6
+#define NOF_ERR_COUNTS 7
+#define REMOVE_CHANNEL 16 //default
+
+// Mac checks for packet size if type < 0x600, other values the MAC uses
+// are 0x8100 (VLAN) and 0x8808 (Control frames).
+#define ETHER_TYPE 0x0600
+
+// mm_channel order enum
+enum mm_channel {
+ CH_INTERFACE_SELECT,
+ CH_BLOCK_VALIDATE_DECODE_0,
+ CH_BLOCK_VALIDATE_DECODE_1,
+ CH_BLOCK_VALIDATE_DECODE_2,
+ CH_BLOCK_VALIDATE_DECODE_3,
+ CH_BLOCK_VALIDATE_DECODE_4,
+ CH_BLOCK_VALIDATE_DECODE_5,
+ CH_BLOCK_VALIDATE_DECODE_6,
+ CH_BLOCK_VALIDATE_DECODE_7,
+ CH_VALIDATE_CHANNEL,
+ CH_LANE_DIRECTION,
+ LAST_MM_CHANNEL_ENTRY
+};
+
+// M&C parameters definitions
+struct param_rx_validate_struct {
+ uint block_cnt;
+ uint err_cnt[NOF_ERR_COUNTS];
+};
+union param_rx_validate {
+ struct param_rx_validate_struct parameters;
+ uint arr[DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))];
+};
+
+struct param_interface_select_struct {
+ uint input_select;
+ uint output_select;
+};
+union param_interface_select {
+ struct param_interface_select_struct parameters;
+ uint arr[DIVIDE_AND_ROUND_UP(sizeof(struct param_interface_select_struct),sizeof(uint))];
+};
+
+struct param_validate_channel_struct {
+ uint transport_nof_hops;
+};
+union param_validate_channel {
+ struct param_validate_channel_struct parameters[NOF_LANES];
+ uint arr[DIVIDE_AND_ROUND_UP(NOF_LANES*sizeof(struct param_validate_channel_struct),sizeof(uint))];
+};
+
+// register struct
+struct reg {
+ uint offset;
+ uint size;
+} __attribute__((packed));
+
+// Channel element structs
+struct mm_in {
+ uint wrdata;
+ uint address;
+ bool wr;
+} __attribute__((packed));
+
+struct mm_out {
+ uint rddata;
+} __attribute__((packed));
+
+struct line_10GbE {
+ uint64_t data;
+ uchar flags;
+ uint err;
+} __attribute__((packed));
+
+struct line_dp {
+ uint64_t data;
+ uchar flags;
+ uint64_t dp_bsn;
+ uint dp_channel;
+} __attribute__((packed));
+
+struct line_bs_sosi {
+ uint data;
+ uchar flags;
+ uint64_t dp_bsn;
+} __attribute__((packed));
+
+
+// Ethernet packet definition
+struct ethernet_header_struct {
+ uchar destination_mac[6], source_mac[6];
+ ushort ether_type;
+}__attribute__((packed));
+
+struct ethernet_packet_struct {
+ struct ethernet_header_struct ethernet_header;
+ ushort padding;
+ uint64_t payload[PAYLOAD_SIZE];
+}__attribute__((packed));
+
+union eth_packet {
+ struct ethernet_packet_struct packet;
+ uint64_t raw[PAYLOAD_SIZE+ETH_HEADER_SIZE];
+} __attribute__((packed));
+
+// DP packet definition
+struct dp_header_struct {
+ ushort dp_channel;
+ uint64_t dp_sync_and_bsn; // 62:0 = bsn, 63=sync
+} __attribute__((packed));
+
+struct dp_packet_struct{
+ struct ethernet_header_struct ethernet_header;
+ struct dp_header_struct dp_header;
+ uint64_t payload[PAYLOAD_SIZE];
+} __attribute__((packed));
+
+union dp_packet {
+ struct dp_packet_struct packet;
+ uint64_t raw[PAYLOAD_SIZE+DP_HEADER_SIZE];
+} __attribute__((packed));
+
+
+// IO channels
+channel struct mm_in ch_in_mm __attribute__((depth(0))) __attribute__((io("kernel_input_mm")));
+channel struct mm_out ch_out_mm __attribute__((depth(0))) __attribute__((io("kernel_output_mm")));
+
+channel struct line_10GbE ch_in_ring_0 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_0")));
+channel struct line_10GbE ch_out_ring_0 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_0")));
+
+channel struct line_10GbE ch_in_ring_1 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_1")));
+channel struct line_10GbE ch_out_ring_1 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_1")));
+
+channel struct line_10GbE ch_in_ring_2 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_2")));
+channel struct line_10GbE ch_out_ring_2 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_2")));
+
+channel struct line_10GbE ch_in_ring_3 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_3")));
+channel struct line_10GbE ch_out_ring_3 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_3")));
+
+channel struct line_10GbE ch_in_ring_4 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_4")));
+channel struct line_10GbE ch_out_ring_4 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_4")));
+
+channel struct line_10GbE ch_in_ring_5 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_5")));
+channel struct line_10GbE ch_out_ring_5 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_5")));
+
+channel struct line_10GbE ch_in_ring_6 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_6")));
+channel struct line_10GbE ch_out_ring_6 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_6")));
+
+channel struct line_10GbE ch_in_ring_7 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_ring_7")));
+channel struct line_10GbE ch_out_ring_7 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_ring_7")));
+
+channel struct line_10GbE ch_in_qsfp_0 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_0")));
+channel struct line_10GbE ch_out_qsfp_0 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_0")));
+
+channel struct line_10GbE ch_in_qsfp_1 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_1")));
+channel struct line_10GbE ch_out_qsfp_1 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_1")));
+
+channel struct line_10GbE ch_in_qsfp_2 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_2")));
+channel struct line_10GbE ch_out_qsfp_2 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_2")));
+
+channel struct line_10GbE ch_in_qsfp_3 __attribute__((depth(0))) __attribute__((io("kernel_input_10GbE_qsfp_3")));
+channel struct line_10GbE ch_out_qsfp_3 __attribute__((depth(0))) __attribute__((io("kernel_output_10GbE_qsfp_3")));
+
+channel struct line_dp ch_out_lane_0 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_0")));
+channel struct line_dp ch_out_lane_1 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_1")));
+channel struct line_dp ch_out_lane_2 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_2")));
+channel struct line_dp ch_out_lane_3 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_3")));
+channel struct line_dp ch_out_lane_4 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_4")));
+channel struct line_dp ch_out_lane_5 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_5")));
+channel struct line_dp ch_out_lane_6 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_6")));
+channel struct line_dp ch_out_lane_7 __attribute__((depth(0))) __attribute__((io("kernel_output_lane_7")));
+
+channel struct line_dp ch_in_lane_0 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_0")));
+channel struct line_dp ch_in_lane_1 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_1")));
+channel struct line_dp ch_in_lane_2 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_2")));
+channel struct line_dp ch_in_lane_3 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_3")));
+channel struct line_dp ch_in_lane_4 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_4")));
+channel struct line_dp ch_in_lane_5 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_5")));
+channel struct line_dp ch_in_lane_6 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_6")));
+channel struct line_dp ch_in_lane_7 __attribute__((depth(0))) __attribute__((io("kernel_input_lane_7")));
+
+channel struct line_dp ch_out_rx_monitor_0 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_0")));
+channel struct line_dp ch_out_rx_monitor_1 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_1")));
+channel struct line_dp ch_out_rx_monitor_2 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_2")));
+channel struct line_dp ch_out_rx_monitor_3 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_3")));
+channel struct line_dp ch_out_rx_monitor_4 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_4")));
+channel struct line_dp ch_out_rx_monitor_5 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_5")));
+channel struct line_dp ch_out_rx_monitor_6 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_6")));
+channel struct line_dp ch_out_rx_monitor_7 __attribute__((depth(0))) __attribute__((io("kernel_output_rx_monitor_7")));
+
+channel struct line_dp ch_out_tx_monitor_0 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_0")));
+channel struct line_dp ch_out_tx_monitor_1 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_1")));
+channel struct line_dp ch_out_tx_monitor_2 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_2")));
+channel struct line_dp ch_out_tx_monitor_3 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_3")));
+channel struct line_dp ch_out_tx_monitor_4 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_4")));
+channel struct line_dp ch_out_tx_monitor_5 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_5")));
+channel struct line_dp ch_out_tx_monitor_6 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_6")));
+channel struct line_dp ch_out_tx_monitor_7 __attribute__((depth(0))) __attribute__((io("kernel_output_tx_monitor_7")));
+
+channel struct line_bs_sosi ch_in_bs_sosi __attribute__((depth(0))) __attribute__((io("kernel_input_bs_sosi")));
+
+// Internal channels
+channel struct line_10GbE rx_10GbE_channels[NOF_LANES] __attribute__((depth(0)));
+channel struct line_dp rx_decoded_channels[NOF_LANES] __attribute__((depth(0)));
+channel struct line_dp rx_sosi_channels[NOF_LANES] __attribute__((depth(0)));
+
+channel struct line_dp tx_validated_channels[NOF_LANES] __attribute__((depth(DP_HEADER_SIZE)));
+channel struct line_10GbE tx_sosi_channels[NOF_LANES] __attribute__((depth(0)));
+
+channel struct mm_in mm_channel_in[LAST_MM_CHANNEL_ENTRY] __attribute__((depth(0)));
+channel struct mm_out mm_channel_out[LAST_MM_CHANNEL_ENTRY+1] __attribute__((depth(0))); // 1 extra channel for undefined addresses
+
+// Constants
+__constant uchar destination_mac[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+__constant uchar source_mac[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+__constant uint64_t c_header_out[ETH_HEADER_SIZE] = {(__constant uint64_t) 0xFFFFFFFFFFFF0000, (__constant uint64_t) 0x0000000006000000};
+
+// Regmap table with offset, size. Offsets are chosen to fit the largest sizes when NOF_LANES=8
+__constant struct reg regmap[LAST_MM_CHANNEL_ENTRY] = {
+ {0 , DIVIDE_AND_ROUND_UP(sizeof(struct param_interface_select_struct),sizeof(uint))}, //CH_INTERFACE_SELECT, size = 2
+ {2 , DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_0 size = 8
+ {10, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_1 size = 8
+ {18, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_2 size = 8
+ {26, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_3 size = 8
+ {34, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_4 size = 8
+ {42, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_5 size = 8
+ {50, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_6 size = 8
+ {58, DIVIDE_AND_ROUND_UP(sizeof(struct param_rx_validate_struct),sizeof(uint))}, //CH_BLOCK_VALIDATE_DECODE_7 size = 8
+ {66, DIVIDE_AND_ROUND_UP(NOF_LANES*sizeof(struct param_validate_channel_struct),sizeof(uint))},//CH_VALIDATE_CHANNEL size = NOF_LANES*1
+ {74, 8} //CH_LANE_DIRECTION size = 8
+};
+
+// helper functions
+void handle_mm_request(const int ch_id, uint *reg_arr, bool ro)
+{
+ bool mm_valid;
+ struct mm_in mm_request = read_channel_nb_intel(mm_channel_in[ch_id], &mm_valid); //non-blocking read
+ struct mm_out mm_response;
+ if (mm_valid) {
+ if(mm_request.wr) //write request
+ {
+ if(!ro)
+ reg_arr[mm_request.address] = mm_request.wrdata;
+ } else { //read request
+ mm_response.rddata = reg_arr[mm_request.address];
+ write_channel_intel(mm_channel_out[ch_id], mm_response);
+ }
+ }
+}
+
+void handle_rw_mm_request(const int ch_id, uint *reg_arr)
+{
+ handle_mm_request(ch_id, reg_arr, false);
+}
+
+void handle_ro_mm_request(const int ch_id, uint *reg_arr)
+{
+ handle_mm_request(ch_id, reg_arr, true);
+}
+
+
+/* ----- MM Controller ----- */
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void mm_in_controller()
+{
+ while(1)
+ {
+ bool undefined = true;
+ struct mm_in mm_request = read_channel_intel(ch_in_mm);
+ #pragma unroll
+ for (int i = 0; i < LAST_MM_CHANNEL_ENTRY; i++)
+ {
+ if (mm_request.address >= regmap[i].offset && mm_request.address < (regmap[i].offset + regmap[i].size))
+ {
+ undefined = false;
+ struct mm_in local_mm_request;
+ local_mm_request.wr = mm_request.wr;
+ local_mm_request.wrdata = mm_request.wrdata;
+ local_mm_request.address = mm_request.address - regmap[i].offset;
+ write_channel_intel(mm_channel_in[i], local_mm_request);
+ }
+ }
+
+ if (undefined && mm_request.wr == 0) { // undefined address
+ struct mm_out zero_response;
+ zero_response.rddata = 0;
+ write_channel_intel(mm_channel_out[LAST_MM_CHANNEL_ENTRY], zero_response);
+ }
+ }
+}
+
+
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void mm_out_controller()
+{
+ while(1)
+ {
+ struct mm_out mm_response;
+ for (int i = 0; i < LAST_MM_CHANNEL_ENTRY+1; i++)
+ {
+ bool valid;
+ mm_response = read_channel_nb_intel(mm_channel_out[i], &valid);
+ if (valid)
+ {
+ write_channel_intel(ch_out_mm, mm_response);
+ }
+ }
+ }
+}
+/* ----- End of MM Controller ----- */
+
+
+/* ----- Constant MM Read only parameters ----- */
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void lane_direction()
+{
+ uint lane_directions[8] = {1,0,1,0,1,0,1,0};
+ for (int i = NOF_LANES; i < 8; i++){
+ lane_directions[i] = -1; //force to -1 if lane is unused.
+ }
+ while(1){
+ // handle MM read/write requests
+ handle_ro_mm_request(CH_LANE_DIRECTION, lane_directions);
+ }
+}
+
+
+/* ----- In/Output select -----*/
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void interface_select()
+{
+ union param_interface_select reg;
+ reg.parameters.input_select = 0; // default input is board input = 0
+ reg.parameters.output_select = 0; // default input is board input = 0
+#ifdef EMULATOR
+ int emu_i = 0;
+#endif
+ while(1){
+ // handle MM read/write requests
+ handle_rw_mm_request(CH_INTERFACE_SELECT, reg.arr);
+ // Do someting with parameters
+
+ struct line_10GbE line_out_ring[8];
+ struct line_10GbE line_out_qsfp[4];
+ struct line_10GbE line_in_ring[8];
+ struct line_10GbE line_in_qsfp[4];
+ bool valid_ring_input[8];
+ bool valid_qsfp_input[4];
+ bool valid_qsfp_output[4] = {};
+ bool valid_ring_output[8] = {};
+
+ line_in_qsfp[0] = read_channel_nb_intel(ch_in_qsfp_0, &valid_qsfp_input[0]);
+ line_in_qsfp[1] = read_channel_nb_intel(ch_in_qsfp_1, &valid_qsfp_input[1]);
+ line_in_qsfp[2] = read_channel_nb_intel(ch_in_qsfp_2, &valid_qsfp_input[2]);
+ line_in_qsfp[3] = read_channel_nb_intel(ch_in_qsfp_3, &valid_qsfp_input[3]);
+
+ line_in_ring[0] = read_channel_nb_intel(ch_in_ring_0, &valid_ring_input[0]);
+ line_in_ring[1] = read_channel_nb_intel(ch_in_ring_1, &valid_ring_input[1]);
+ line_in_ring[2] = read_channel_nb_intel(ch_in_ring_2, &valid_ring_input[2]);
+ line_in_ring[3] = read_channel_nb_intel(ch_in_ring_3, &valid_ring_input[3]);
+ line_in_ring[4] = read_channel_nb_intel(ch_in_ring_4, &valid_ring_input[4]);
+ line_in_ring[5] = read_channel_nb_intel(ch_in_ring_5, &valid_ring_input[5]);
+ line_in_ring[6] = read_channel_nb_intel(ch_in_ring_6, &valid_ring_input[6]);
+ line_in_ring[7] = read_channel_nb_intel(ch_in_ring_7, &valid_ring_input[7]);
+
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++)
+ {
+ struct line_10GbE input_10GbE;
+ struct line_10GbE output_10GbE;
+ bool valid_input;
+ bool valid_output;
+ //read tx channels
+ output_10GbE = read_channel_nb_intel(tx_sosi_channels[i], &valid_output);
+ // all even lanes are received from qsfp instead of board (odd lanes received from ring).
+ // even lanes are therefore transmitted over ring and odd lanes are transmitted over qsfp.
+ if (reg.parameters.input_select == 1 && reg.parameters.output_select == 0) // RX_input select
+ {
+ if (i % 2) { // odd
+ input_10GbE = line_in_ring[i];
+ valid_input = valid_ring_input[i];
+ if(valid_output){
+ valid_qsfp_output[i/2] = true;
+ line_out_qsfp[i/2] = output_10GbE;
+ }
+ } else { // even
+ input_10GbE = line_in_qsfp[i/2];
+ valid_input = valid_qsfp_input[i/2];
+ if(valid_output){
+ valid_ring_output[i] = true;
+ line_out_ring[i] = output_10GbE;
+ }
+ }
+ }
+
+ // all even lanes are transmitted to qsfp instead of board (odd lanes transmitted to ring).
+ // even lanes are therefore received from ring and odd lanes are received over qsfp.
+ else if (reg.parameters.input_select == 0 && reg.parameters.output_select == 1) // TX_output select
+ {
+ if (i % 2) { // odd
+ input_10GbE = line_in_qsfp[i/2];
+ valid_input = valid_qsfp_input[i/2];
+ if(valid_output){
+ valid_ring_output[i] = true;
+ line_out_ring[i] = output_10GbE;
+ }
+ } else { // even
+ input_10GbE = line_in_ring[i];
+ valid_input = valid_ring_input[i];
+ if(valid_output){
+ valid_qsfp_output[i/2] = true;
+ line_out_qsfp[i/2] = output_10GbE;
+ }
+ }
+
+ }
+ // All lanes are received from and transmitted to ring
+ else { // board input
+ input_10GbE = line_in_ring[i];
+ valid_input = valid_ring_input[i];
+ if(valid_output){
+ valid_ring_output[i] = true;
+ line_out_ring[i] = output_10GbE;
+ }
+ }
+ // Write rx channels
+ if(valid_input)
+ write_channel_intel(rx_10GbE_channels[i], input_10GbE);
+ }
+
+ // Write channels to output
+ if (valid_qsfp_output[0]){write_channel_intel(ch_out_qsfp_0, line_out_qsfp[0]);}
+ if (valid_qsfp_output[1]){write_channel_intel(ch_out_qsfp_1, line_out_qsfp[1]);}
+ if (valid_qsfp_output[2]){write_channel_intel(ch_out_qsfp_2, line_out_qsfp[2]);}
+ if (valid_qsfp_output[3]){write_channel_intel(ch_out_qsfp_3, line_out_qsfp[3]);}
+
+ if (valid_ring_output[0]){write_channel_intel(ch_out_ring_0, line_out_ring[0]);
+#ifdef EMULATOR
+ emu_i++;
+ if(emu_i >= BLOCK_LENGTH)
+ break;
+#endif
+ }
+ if (valid_ring_output[1]){write_channel_intel(ch_out_ring_1, line_out_ring[1]);}
+ if (valid_ring_output[2]){write_channel_intel(ch_out_ring_2, line_out_ring[2]);}
+ if (valid_ring_output[3]){write_channel_intel(ch_out_ring_3, line_out_ring[3]);}
+ if (valid_ring_output[4]){write_channel_intel(ch_out_ring_4, line_out_ring[4]);}
+ if (valid_ring_output[5]){write_channel_intel(ch_out_ring_5, line_out_ring[5]);}
+ if (valid_ring_output[6]){write_channel_intel(ch_out_ring_6, line_out_ring[6]);}
+ if (valid_ring_output[7]){write_channel_intel(ch_out_ring_7, line_out_ring[7]);}
+ }
+}
+/* ----- End of In/Output select -----*/
+
+
+/* ----- ring_rx ----- */
+__attribute__((num_compute_units(NOF_LANES), max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void block_validate_decode()
+{
+ const int laneIndex = get_compute_id(0);
+ union param_rx_validate reg;
+ reg.parameters.block_cnt = 0;
+ for (int x = 0; x < NOF_ERR_COUNTS; x++)
+ reg.parameters.err_cnt[x] = 0;
+
+#ifdef USE_DP_LAYER
+ union dp_packet packets[2]; //one to read and one to write
+#else
+ union eth_packet packets[2]; //one to read and one to write
+#endif
+ bool valid = false;
+ bool canWrite = false;
+ uint i = 0; // read iterator
+ uint j = 0; // write iterator
+ uint1_t readIndex = 0;
+ uint1_t writeIndex = 0;
+ while(1){
+ struct line_10GbE input_10GbE;
+ struct line_dp line_out;
+ bool ch_valid;
+
+ handle_ro_mm_request((laneIndex+CH_BLOCK_VALIDATE_DECODE_0), reg.arr); // handle MM read/write requests
+
+ input_10GbE = read_channel_nb_intel(rx_10GbE_channels[laneIndex], &ch_valid);
+ if(ch_valid){
+ // validation
+ if((input_10GbE.flags & FLAG_LAST) == FLAG_LAST){
+ if (i == BLOCK_LENGTH -1 && input_10GbE.err == 0) {
+ valid = true;
+ reg.parameters.block_cnt += 1;
+ }
+ else {
+ if (i != BLOCK_LENGTH-1)
+ reg.parameters.err_cnt[ERR_BI] += 1;
+#pragma unroll
+ for (int err = 0; err < NOF_ERR_COUNTS; err++){
+ if (err != ERR_BI)
+ reg.parameters.err_cnt[err] += ((input_10GbE.err & (1 << err)) >> err);
+ }
+ }
+ }
+ //Packet capturing
+ packets[readIndex].raw[i] = input_10GbE.data;
+ if (i == BLOCK_LENGTH-1 || (input_10GbE.flags & FLAG_LAST) == FLAG_LAST){
+ i = 0; // reset read iterator
+ }
+ else {
+ i++; //only iterate if ch_valid = true
+ }
+ }
+
+ // Packet decoding
+ if (valid) {
+ writeIndex = readIndex; // Write the stored packet
+ readIndex = !readIndex; // set read index to the packet which can be overwritten
+ valid = false;
+ canWrite = true; // assumes canWrite will be false again before valid is true as outgoing packet is shorter than incoming packet
+ }
+
+ if (canWrite){
+ line_out.data = packets[writeIndex].packet.payload[j];
+ line_out.flags = 0;
+ line_out.dp_bsn = 0;
+ line_out.dp_channel = 0;
+ if (j == 0) {
+ line_out.flags |= FLAG_FIRST;
+#ifdef USE_DP_LAYER
+ line_out.dp_bsn = (packets[writeIndex].packet.dp_header.dp_sync_and_bsn & MASK_BSN); //62:0 = bsn
+ line_out.dp_channel = packets[writeIndex].packet.dp_header.dp_channel;
+
+ if( 0 != (packets[writeIndex].packet.dp_header.dp_sync_and_bsn & MASK_SYNC))
+ line_out.flags |= FLAG_SYNC;
+#endif
+ }
+ if (j == BLOCK_LENGTH-1){
+ line_out.flags |= FLAG_LAST;
+ j = 0;
+ canWrite = false;
+ }
+ else {
+ j++;
+ }
+
+ write_channel_intel(rx_decoded_channels[laneIndex], line_out);
+ }
+ }
+}
+
+
+
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void rx_split()
+{
+ while(1){
+ struct line_dp line[NOF_LANES];
+ bool valid[NOF_LANES];
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++){
+ line[i] = read_channel_nb_intel(rx_decoded_channels[i], &valid[i]);
+ if (valid[i])
+ write_channel_intel(rx_sosi_channels[i], line[i]);
+ }
+
+ if (valid[0]){ write_channel_intel(ch_out_rx_monitor_0, line[0]);}
+ if (valid[1]){ write_channel_intel(ch_out_rx_monitor_1, line[1]);}
+ if (valid[2]){ write_channel_intel(ch_out_rx_monitor_2, line[2]);}
+ if (valid[3]){ write_channel_intel(ch_out_rx_monitor_3, line[3]);}
+ if (valid[4]){ write_channel_intel(ch_out_rx_monitor_4, line[4]);}
+ if (valid[5]){ write_channel_intel(ch_out_rx_monitor_5, line[5]);}
+ if (valid[6]){ write_channel_intel(ch_out_rx_monitor_6, line[6]);}
+ if (valid[7]){ write_channel_intel(ch_out_rx_monitor_7, line[7]);}
+
+ }
+}
+
+#ifdef USE_DP_LAYER
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void validate_bsn_at_sync()
+{
+ bool discard[NOF_LANES] = {};
+ uint64_t localBsn = 0;
+#ifdef EMULATOR
+ int emu_i = 0;
+#endif
+ while(1){
+ struct line_bs_sosi bs_sosi;
+ struct line_dp line[NOF_LANES];
+ bool valid[NOF_LANES];
+ bool bs_sosi_valid;
+
+ bs_sosi = read_channel_nb_intel(ch_in_bs_sosi, &bs_sosi_valid);
+ if (bs_sosi_valid && ((bs_sosi.flags & FLAG_SYNC) == FLAG_SYNC))
+ localBsn = bs_sosi.dp_bsn;
+
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++){
+ line[i] = read_channel_nb_intel(rx_sosi_channels[i], &valid[i]);
+ if (valid[i] && ((line[i].flags & FLAG_SYNC) == FLAG_SYNC))
+ discard[i] = (localBsn != line[i].dp_bsn);
+ }
+
+ if ((!discard[0]) && valid[0]){ write_channel_intel(ch_out_lane_0, line[0]);
+#ifdef EMULATOR
+ emu_i++;
+ if (emu_i >= PAYLOAD_SIZE)
+ break;
+#endif
+ }
+ if ((!discard[1]) && valid[1]){ write_channel_intel(ch_out_lane_1, line[1]);}
+ if ((!discard[2]) && valid[2]){ write_channel_intel(ch_out_lane_2, line[2]);}
+ if ((!discard[3]) && valid[3]){ write_channel_intel(ch_out_lane_3, line[3]);}
+ if ((!discard[4]) && valid[4]){ write_channel_intel(ch_out_lane_4, line[4]);}
+ if ((!discard[5]) && valid[5]){ write_channel_intel(ch_out_lane_5, line[5]);}
+ if ((!discard[6]) && valid[6]){ write_channel_intel(ch_out_lane_6, line[6]);}
+ if ((!discard[7]) && valid[7]){ write_channel_intel(ch_out_lane_7, line[7]);}
+
+ }
+}
+
+#else
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void no_validate_bsn_at_sync()
+{
+ while(1){
+ struct line_dp line[NOF_LANES];
+ bool valid[NOF_LANES];
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++)
+ line[i] = read_channel_nb_intel(rx_sosi_channels[i], &valid[i]);
+
+ if(valid[0]){ write_channel_intel(ch_out_lane_0, line[0]);}
+ if(valid[1]){ write_channel_intel(ch_out_lane_1, line[1]);}
+ if(valid[2]){ write_channel_intel(ch_out_lane_2, line[2]);}
+ if(valid[3]){ write_channel_intel(ch_out_lane_3, line[3]);}
+ if(valid[4]){ write_channel_intel(ch_out_lane_4, line[4]);}
+ if(valid[5]){ write_channel_intel(ch_out_lane_5, line[5]);}
+ if(valid[6]){ write_channel_intel(ch_out_lane_6, line[6]);}
+ if(valid[7]){ write_channel_intel(ch_out_lane_7, line[7]);}
+ }
+}
+#endif
+
+/* ----- End of ring_rx ----- */
+
+/* ----- ring_tx ----- */
+#ifdef USE_DP_LAYER
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void validate_channel()
+{
+ union param_validate_channel reg;
+ for (int i = 0; i < NOF_LANES; i++){
+ reg.parameters[i].transport_nof_hops = REMOVE_CHANNEL;
+ }
+
+ bool discard[NOF_LANES] = {0};
+ while(1){
+ // handle MM read/write requests
+ handle_rw_mm_request(CH_VALIDATE_CHANNEL, reg.arr);
+ // Do someting with parameters
+ bool valid[NOF_LANES];
+ struct line_dp line[NOF_LANES];
+ line[0] = read_channel_nb_intel(ch_in_lane_0, &valid[0]);
+ line[1] = read_channel_nb_intel(ch_in_lane_1, &valid[1]);
+ line[2] = read_channel_nb_intel(ch_in_lane_2, &valid[2]);
+ line[3] = read_channel_nb_intel(ch_in_lane_3, &valid[3]);
+ line[4] = read_channel_nb_intel(ch_in_lane_4, &valid[4]);
+ line[5] = read_channel_nb_intel(ch_in_lane_5, &valid[5]);
+ line[6] = read_channel_nb_intel(ch_in_lane_6, &valid[6]);
+ line[7] = read_channel_nb_intel(ch_in_lane_7, &valid[7]);
+
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++){
+ if (valid[i]){
+ if((line[i].flags & FLAG_FIRST) == FLAG_FIRST)
+ discard[i] = (line[i].dp_channel == reg.parameters[i].transport_nof_hops);
+ if (!discard[i])
+ write_channel_intel(tx_validated_channels[i], line[i]);
+ }
+ }
+
+ if(valid[0] && !discard[0]){ write_channel_intel(ch_out_tx_monitor_0, line[0]);}
+ if(valid[1] && !discard[1]){ write_channel_intel(ch_out_tx_monitor_1, line[1]);}
+ if(valid[2] && !discard[2]){ write_channel_intel(ch_out_tx_monitor_2, line[2]);}
+ if(valid[3] && !discard[3]){ write_channel_intel(ch_out_tx_monitor_3, line[3]);}
+ if(valid[4] && !discard[4]){ write_channel_intel(ch_out_tx_monitor_4, line[4]);}
+ if(valid[5] && !discard[5]){ write_channel_intel(ch_out_tx_monitor_5, line[5]);}
+ if(valid[6] && !discard[6]){ write_channel_intel(ch_out_tx_monitor_6, line[6]);}
+ if(valid[7] && !discard[7]){ write_channel_intel(ch_out_tx_monitor_7, line[7]);}
+
+ }
+}
+#else
+__attribute__((max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void no_validate_channel()
+{
+ uint no_param_arr[8] = [~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0];
+ while(1){
+ // handle MM read/write requests
+ handle_ro_mm_request(CH_VALIDATE_CHANNEL, no_param_arr);
+
+ bool valid[NOF_LANES];
+ struct line_dp line[NOF_LANES];
+ line[0] = read_channel_nb_intel(ch_in_lane_0, &valid[0]);
+ line[1] = read_channel_nb_intel(ch_in_lane_1, &valid[1]);
+ line[2] = read_channel_nb_intel(ch_in_lane_2, &valid[2]);
+ line[3] = read_channel_nb_intel(ch_in_lane_3, &valid[3]);
+ line[4] = read_channel_nb_intel(ch_in_lane_4, &valid[4]);
+ line[5] = read_channel_nb_intel(ch_in_lane_5, &valid[5]);
+ line[6] = read_channel_nb_intel(ch_in_lane_6, &valid[6]);
+ line[7] = read_channel_nb_intel(ch_in_lane_7, &valid[7]);
+
+ #pragma unroll
+ for (int i = 0; i < NOF_LANES; i++){
+ if (valid[i])
+ write_channel_intel(tx_validated_channels[i], line[i]);
+ }
+
+ if(valid[0]){ write_channel_intel(ch_out_tx_monitor_0, line[0]);}
+ if(valid[1]){ write_channel_intel(ch_out_tx_monitor_1, line[1]);}
+ if(valid[2]){ write_channel_intel(ch_out_tx_monitor_2, line[2]);}
+ if(valid[3]){ write_channel_intel(ch_out_tx_monitor_3, line[3]);}
+ if(valid[4]){ write_channel_intel(ch_out_tx_monitor_4, line[4]);}
+ if(valid[5]){ write_channel_intel(ch_out_tx_monitor_5, line[5]);}
+ if(valid[6]){ write_channel_intel(ch_out_tx_monitor_6, line[6]);}
+ if(valid[7]){ write_channel_intel(ch_out_tx_monitor_7, line[7]);}
+
+ }
+}
+#endif
+
+// TODO: make sure the latency is low.
+__attribute__((num_compute_units(NOF_LANES), max_global_work_dim(0)))
+#ifndef EMULATOR
+__attribute__((autorun))
+#endif
+__kernel void tx_encode()
+{
+ const int laneIndex = get_compute_id(0);
+ while(1){
+ struct line_10GbE output_10GbE;
+ struct line_dp input_dp;
+ uint64_t dp_sync_and_bsn = 0;
+ ushort dp_channel = 0;
+ for (int j = 0; j < BLOCK_LENGTH; j++){
+
+#ifdef USE_DP_LAYER
+ if(j == 0 || (j > DP_HEADER_SIZE)){
+#else
+ if(j == 0 || (j > ETH_HEADER_SIZE)){
+#endif
+ input_dp = read_channel_intel(tx_validated_channels[laneIndex]);
+ }
+ output_10GbE.flags = 0;
+ output_10GbE.err = 0;
+
+ switch(j)
+ {
+ case 0:
+#ifdef USE_DP_LAYER
+ dp_channel = input_dp.dp_channel + 1; //Add 1 hop.
+ if ((input_dp.flags & FLAG_SYNC)==FLAG_SYNC){
+ dp_sync_and_bsn = (input_dp.dp_bsn | MASK_SYNC); // set bsn and sync
+ }
+ else{
+ dp_sync_and_bsn = (input_dp.dp_bsn & MASK_BSN); // set bsn and clear sync (if set)
+ }
+#endif
+ output_10GbE.flags = FLAG_FIRST;
+ output_10GbE.data = c_header_out[0];
+ break;
+
+ case 1:
+#ifdef USE_DP_LAYER
+ output_10GbE.data = (c_header_out[1] | ((uint64_t) dp_channel));
+#else
+ output_10GbE.data = c_header_out[1];
+#endif
+ break;
+
+#ifdef USE_DP_LAYER
+ case 2:
+ output_10GbE.data = dp_sync_and_bsn;
+ break;
+#endif
+
+ case (BLOCK_LENGTH-1):
+ output_10GbE.flags = FLAG_LAST;
+ // no break, we also want to execute the default case.
+
+ default:
+ output_10GbE.data = input_dp.data;
+ }
+
+ write_channel_intel(tx_sosi_channels[laneIndex], output_10GbE);
+ }
+ }
+}
+
+
+
+__attribute__((max_global_work_dim(0)))
+__kernel void dummy()
+{
+}
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index 663aefa26a6996293774b50364c5429a2efc5a7d..81ed7b897acde801e0f918df397a0c1b13e115be 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -19,6 +19,7 @@ synth_files =
src/vhdl/lofar2_unb2b_sdp_station.vhd
test_bench_files =
+ tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
regression_test_vhdl =
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index aa7cf53417e5b347abe994b5f08a323ae2d61e78..5bb941d05775856b5417be5bc07050ff9ee45607 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -45,7 +45,7 @@ peripherals:
- peripheral_name: unb2b_board/wdi
mm_port_names:
- - PIO_WDI
+ - REG_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
mm_port_names:
@@ -104,20 +104,13 @@ peripherals:
mm_port_names:
- REG_DP_SHIFTRAM
- - peripheral_name: dp/dp_bsn_source
+ - peripheral_name: dp/dp_bsn_source_v2
parameter_overrides:
- - { name: g_nof_block_per_sync, value: c_nof_block_per_sync }
+ - { name: g_nof_clk_per_sync, value: c_nof_clk_per_pps }
+ - { name: g_block_size, value: c_N_fft }
+ - { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
mm_port_names:
- - REG_BSN_SOURCE
-
- # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
- #peripheral_name: dp/dp_bsn_source_v2
- #parameter_overrides:
- # - { name: g_nof_clk_per_sync, value: c_nof_clk_per_pps }
- # - { name: g_block_size, value: c_N_fft }
- # - { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
- #mm_port_names:
- # - REG_BSN_SOURCE_V2
+ - REG_BSN_SOURCE_V2
- peripheral_name: dp/dp_bsn_scheduler
mm_port_names:
@@ -132,14 +125,14 @@ peripherals:
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- - REG_DIAG_WG
- - RAM_DIAG_WG
+ - REG_WG
+ - RAM_WG
- peripheral_name: aduh/aduh_mon_dc_power
parameter_overrides:
- { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- - REG_ADUH_MON
+ - REG_ADUH_MONITOR
# Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
#- peripheral_name: aduh/aduh_mon_data_buffer
@@ -159,8 +152,8 @@ peripherals:
- { name: g_data_w, value: c_W_adc_jesd }
- { name: g_nof_data, value: c_V_si_db }
mm_port_names:
- - REG_DIAG_DATA_BUF_BSN
- - RAM_DIAG_DATA_BUF_BSN
+ - REG_DIAG_DATA_BUFFER_BSN
+ - RAM_DIAG_DATA_BUFFER_BSN
#############################################################################
# Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
@@ -193,12 +186,12 @@ peripherals:
- peripheral_name: common/common_variable_delay
peripheral_group: sst
mm_port_names:
- - REG_STAT_ENABLE
+ - REG_STAT_ENABLE_SST
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
peripheral_group: sst
mm_port_names:
- - REG_STAT_HDR_INFO
+ - REG_STAT_HDR_DAT_SST
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
@@ -249,16 +242,26 @@ peripherals:
- peripheral_name: st/st_bst_for_sdp
mm_port_names:
- RAM_ST_BST
+
+ - peripheral_name: common/common_variable_delay
+ peripheral_group: bst
+ mm_port_names:
+ - REG_STAT_ENABLE_BST_0
+ - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
+ peripheral_group: bst
+ mm_port_names:
+ - REG_STAT_HDR_DAT_BST_0
+
- peripheral_name: common/common_variable_delay
peripheral_group: bst
mm_port_names:
- - REG_STAT_ENABLE_BST
+ - REG_STAT_ENABLE_BST_1
- peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
peripheral_group: bst
mm_port_names:
- - REG_STAT_HDR_INFO_BST
+ - REG_STAT_HDR_DAT_BST_1
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy
peripheral_group: beamlet_output
@@ -275,3 +278,4 @@ peripherals:
- REG_NW_10GBE_ETH10G
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index 408325eb93077f19c539b3f1b8c8cce005240198..2f2d234af3b3a8f02f91aaa5284df16304c44af1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
index 99094d9434cb93ed9894873ebe4acabd6632283b..ee64493169ca082c585ed7e2ae77b265a53745e5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
@@ -824,9 +824,6 @@
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
- element qsys_lofar2_unb2b_filterbank_reg_bsn_source
- {
- }
}
</spirit:value>
</spirit:parameter>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
new file mode 100644
index 0000000000000000000000000000000000000000..abb238885cd706c366bbca1919d260f0faba6816
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e4500ca3d683d29adeabee6a1c298cbe7dc02383
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
new file mode 100644
index 0000000000000000000000000000000000000000..6de7600bcf10b7c5035e2532a52448c0de69cf4d
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
@@ -0,0 +1,1439 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
new file mode 100644
index 0000000000000000000000000000000000000000..3c0b3d0ae7ad54913a0b8a1316b603eb0226ed9a
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
new file mode 100644
index 0000000000000000000000000000000000000000..1ae732e8c725b6782daeb2b0a1acfcde59de303e
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
new file mode 100644
index 0000000000000000000000000000000000000000..b831745f3d57d9d28adc1d60d26678ef61375296
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>5</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
index 715647a287be9554aba3edc43a5a22b7ab53400b..35188afbf7099cd7a51a4f983120320e82633be3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32768</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>9</spirit:right>
+ <spirit:right>12</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>9</spirit:right>
+ <spirit:right>12</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">13</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -854,7 +854,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -918,7 +918,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -987,7 +987,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1382,11 +1382,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>12</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index b66b1b6e96d92f0f3619d4f10e0d1bc49df3f665..81ce21efced6447469d0a125380059080ca9d8d3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -22,7 +22,7 @@
{
datum baseAddress
{
- value = "638976";
+ value = "8192";
type = "String";
}
}
@@ -38,7 +38,7 @@
{
datum baseAddress
{
- value = "8192";
+ value = "4096";
type = "String";
}
}
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "622592";
+ value = "655360";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "13672";
+ value = "671872";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "12296";
+ value = "671792";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "13664";
+ value = "671864";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "589824";
+ value = "98304";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "458752";
+ value = "524288";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "65536";
+ value = "393216";
type = "String";
}
}
@@ -330,7 +330,7 @@
{
datum baseAddress
{
- value = "524288";
+ value = "589824";
type = "String";
}
}
@@ -346,7 +346,7 @@
{
datum baseAddress
{
- value = "393216";
+ value = "458752";
type = "String";
}
}
@@ -362,7 +362,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "13312";
type = "String";
}
}
@@ -378,7 +378,7 @@
{
datum baseAddress
{
- value = "13584";
+ value = "671760";
type = "String";
}
}
@@ -410,7 +410,7 @@
{
datum baseAddress
{
- value = "13616";
+ value = "671816";
type = "String";
}
}
@@ -426,7 +426,7 @@
{
datum baseAddress
{
- value = "13440";
+ value = "14208";
type = "String";
}
}
@@ -458,7 +458,7 @@
{
datum baseAddress
{
- value = "13608";
+ value = "671808";
type = "String";
}
}
@@ -490,7 +490,7 @@
{
datum baseAddress
{
- value = "13568";
+ value = "671744";
type = "String";
}
}
@@ -511,7 +511,7 @@
{
datum baseAddress
{
- value = "13656";
+ value = "671856";
type = "String";
}
}
@@ -532,7 +532,7 @@
{
datum baseAddress
{
- value = "13648";
+ value = "671848";
type = "String";
}
}
@@ -553,7 +553,7 @@
{
datum baseAddress
{
- value = "13504";
+ value = "14272";
type = "String";
}
}
@@ -569,7 +569,7 @@
{
datum baseAddress
{
- value = "13472";
+ value = "14240";
type = "String";
}
}
@@ -590,7 +590,7 @@
{
datum baseAddress
{
- value = "13376";
+ value = "14144";
type = "String";
}
}
@@ -627,7 +627,7 @@
{
datum baseAddress
{
- value = "13640";
+ value = "671840";
type = "String";
}
}
@@ -648,7 +648,7 @@
{
datum baseAddress
{
- value = "13632";
+ value = "671832";
type = "String";
}
}
@@ -664,7 +664,7 @@
{
datum baseAddress
{
- value = "13600";
+ value = "671800";
type = "String";
}
}
@@ -701,7 +701,7 @@
{
datum baseAddress
{
- value = "13536";
+ value = "14304";
type = "String";
}
}
@@ -717,7 +717,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "14080";
type = "String";
}
}
@@ -733,7 +733,103 @@
{
datum baseAddress
{
- value = "13624";
+ value = "671824";
+ type = "String";
+ }
+ }
+ element reg_stat_enable_bst_0
+ {
+ datum _sortIndex
+ {
+ value = "49";
+ type = "int";
+ }
+ }
+ element reg_stat_enable_bst_0.mem
+ {
+ datum baseAddress
+ {
+ value = "671776";
+ type = "String";
+ }
+ }
+ element reg_stat_enable_bst_1
+ {
+ datum _sortIndex
+ {
+ value = "51";
+ type = "int";
+ }
+ }
+ element reg_stat_enable_bst_1.mem
+ {
+ datum baseAddress
+ {
+ value = "12296";
+ type = "String";
+ }
+ }
+ element reg_stat_enable_sst
+ {
+ datum _sortIndex
+ {
+ value = "47";
+ type = "int";
+ }
+ }
+ element reg_stat_enable_sst.mem
+ {
+ datum baseAddress
+ {
+ value = "671784";
+ type = "String";
+ }
+ }
+ element reg_stat_hdr_dat_bst_0
+ {
+ datum _sortIndex
+ {
+ value = "50";
+ type = "int";
+ }
+ }
+ element reg_stat_hdr_dat_bst_0.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "String";
+ }
+ }
+ element reg_stat_hdr_dat_bst_1
+ {
+ datum _sortIndex
+ {
+ value = "52";
+ type = "int";
+ }
+ }
+ element reg_stat_hdr_dat_bst_1.mem
+ {
+ datum baseAddress
+ {
+ value = "12544";
+ type = "String";
+ }
+ }
+ element reg_stat_hdr_dat_sst
+ {
+ datum _sortIndex
+ {
+ value = "48";
+ type = "int";
+ }
+ }
+ element reg_stat_hdr_dat_sst.mem
+ {
+ datum baseAddress
+ {
+ value = "12800";
type = "String";
}
}
@@ -749,7 +845,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "13568";
type = "String";
}
}
@@ -765,7 +861,7 @@
{
datum baseAddress
{
- value = "13056";
+ value = "13824";
type = "String";
}
}
@@ -807,7 +903,7 @@
{
datum baseAddress
{
- value = "256";
+ value = "13056";
type = "String";
}
}
@@ -833,7 +929,7 @@
}
datum baseAddress
{
- value = "4096";
+ value = "65536";
type = "String";
}
}
@@ -2176,6 +2272,216 @@
internal="reg_si.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_address"
+ internal="reg_stat_enable_bst_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_clk"
+ internal="reg_stat_enable_bst_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_read"
+ internal="reg_stat_enable_bst_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_readdata"
+ internal="reg_stat_enable_bst_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_reset"
+ internal="reg_stat_enable_bst_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_write"
+ internal="reg_stat_enable_bst_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_0_writedata"
+ internal="reg_stat_enable_bst_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_address"
+ internal="reg_stat_enable_bst_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_clk"
+ internal="reg_stat_enable_bst_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_read"
+ internal="reg_stat_enable_bst_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_readdata"
+ internal="reg_stat_enable_bst_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_reset"
+ internal="reg_stat_enable_bst_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_write"
+ internal="reg_stat_enable_bst_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_bst_1_writedata"
+ internal="reg_stat_enable_bst_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_address"
+ internal="reg_stat_enable_sst.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_clk"
+ internal="reg_stat_enable_sst.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_read"
+ internal="reg_stat_enable_sst.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_readdata"
+ internal="reg_stat_enable_sst.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_reset"
+ internal="reg_stat_enable_sst.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_write"
+ internal="reg_stat_enable_sst.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_enable_sst_writedata"
+ internal="reg_stat_enable_sst.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_address"
+ internal="reg_stat_hdr_dat_bst_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_clk"
+ internal="reg_stat_hdr_dat_bst_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_read"
+ internal="reg_stat_hdr_dat_bst_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_readdata"
+ internal="reg_stat_hdr_dat_bst_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_reset"
+ internal="reg_stat_hdr_dat_bst_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_write"
+ internal="reg_stat_hdr_dat_bst_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_0_writedata"
+ internal="reg_stat_hdr_dat_bst_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_address"
+ internal="reg_stat_hdr_dat_bst_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_clk"
+ internal="reg_stat_hdr_dat_bst_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_read"
+ internal="reg_stat_hdr_dat_bst_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_readdata"
+ internal="reg_stat_hdr_dat_bst_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_reset"
+ internal="reg_stat_hdr_dat_bst_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_write"
+ internal="reg_stat_hdr_dat_bst_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_bst_1_writedata"
+ internal="reg_stat_hdr_dat_bst_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_address"
+ internal="reg_stat_hdr_dat_sst.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_clk"
+ internal="reg_stat_hdr_dat_sst.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_read"
+ internal="reg_stat_hdr_dat_sst.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_readdata"
+ internal="reg_stat_hdr_dat_sst.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_reset"
+ internal="reg_stat_hdr_dat_sst.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_write"
+ internal="reg_stat_hdr_dat_sst.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_stat_hdr_dat_sst_writedata"
+ internal="reg_stat_hdr_dat_sst.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_unb_pmbus_address"
internal="reg_unb_pmbus.address"
@@ -4203,20 +4509,12 @@
<isStart>true</isStart>
<ports>
<port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <role>debugaccess</role>
+ <name>d_address</name>
+ <role>address</role>
<direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>d_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
- <width>1</width>
+ <width>24</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
<name>d_byteenable</name>
@@ -4227,17 +4525,25 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_address</name>
- <role>address</role>
+ <name>d_read</name>
+ <role>read</role>
<direction>Output</direction>
- <width>24</width>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>d_readdata</name>
+ <role>readdata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_read</name>
- <role>read</role>
- <direction>Output</direction>
+ <name>d_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -4259,12 +4565,12 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>d_readdata</name>
- <role>readdata</role>
- <direction>Input</direction>
- <width>32</width>
+ <name>debug_mem_slave_debugaccess_to_roms</name>
+ <role>debugaccess</role>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -4428,14 +4734,6 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
- <port>
- <name>debug_mem_slave_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
<port>
<name>debug_mem_slave_byteenable</name>
<role>byteenable</role>
@@ -4445,16 +4743,16 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_waitrequest</name>
- <role>waitrequest</role>
- <direction>Output</direction>
+ <name>debug_mem_slave_debugaccess</name>
+ <role>debugaccess</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>debug_mem_slave_write</name>
- <role>write</role>
+ <name>debug_mem_slave_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4469,8 +4767,16 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>debug_mem_slave_debugaccess</name>
- <role>debugaccess</role>
+ <name>debug_mem_slave_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>debug_mem_slave_write</name>
+ <role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -4723,14 +5029,6 @@
<type>avalon</type>
<isStart>true</isStart>
<ports>
- <port>
- <name>i_read</name>
- <role>read</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
<port>
<name>i_address</name>
<role>address</role>
@@ -4740,9 +5038,9 @@
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>i_waitrequest</name>
- <role>waitrequest</role>
- <direction>Input</direction>
+ <name>i_read</name>
+ <role>read</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -4755,6 +5053,14 @@
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
+ <port>
+ <name>i_waitrequest</name>
+ <role>waitrequest</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
</ports>
<assignments>
<assignmentValueMap/>
@@ -4946,16 +5252,16 @@
<isStart>false</isStart>
<ports>
<port>
- <name>reset_req</name>
- <role>reset_req</role>
+ <name>reset_n</name>
+ <role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>reset_n</name>
- <role>reset_n</role>
+ <name>reset_req</name>
+ <role>reset_req</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -5295,7 +5601,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_0.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_bst_1.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_bst_1.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_wg.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3700' end='0x3740' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3740' end='0x3780' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3780' end='0x37A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x37A0' end='0x37C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x37C0' end='0x37E0' datawidth='32' /><slave name='reg_remu.mem' start='0x37E0' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_wg.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='jesd204b.mem' start='0xA0000' end='0xA4000' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xA4000' end='0xA4010' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xA4010' end='0xA4020' datawidth='32' /><slave name='reg_stat_enable_bst_0.mem' start='0xA4020' end='0xA4028' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xA4028' end='0xA4030' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xA4030' end='0xA4038' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xA4038' end='0xA4040' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xA4040' end='0xA4048' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xA4048' end='0xA4050' datawidth='32' /><slave name='reg_si.mem' start='0xA4050' end='0xA4058' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xA4058' end='0xA4060' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xA4060' end='0xA4068' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xA4068' end='0xA4070' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xA4070' end='0xA4078' datawidth='32' /><slave name='pio_pps.mem' start='0xA4078' end='0xA4080' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xA4080' end='0xA4088' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -11600,37 +11906,3733 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_fil_coefs"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_scrap"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_ss_ss_wide"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_st_bst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>12</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16384</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>14</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_st_sst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="ram_wg"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>14</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>65536</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_fil_coefs"
+ name="reg_aduh_monitor"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11646,7 +15648,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11710,7 +15712,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11779,7 +15781,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12185,11 +16187,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12216,37 +16218,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_scrap"
+ name="reg_bf_scale"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12262,7 +16264,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>9</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12326,7 +16328,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>9</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12395,7 +16397,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>2048</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12801,11 +16803,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>11</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12832,37 +16834,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_ss_ss_wide"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12878,7 +16880,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12942,7 +16944,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13011,7 +17013,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -13417,11 +17419,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13448,37 +17450,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_bst"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13494,7 +17496,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13558,7 +17560,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>12</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -13627,7 +17629,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16384</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14033,11 +18035,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x4000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>14</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14064,37 +18066,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_st_sst"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14110,7 +18112,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14174,7 +18176,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14243,7 +18245,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -14649,11 +18651,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14680,37 +18682,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="ram_wg"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -14726,7 +18728,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>14</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14790,7 +18792,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>14</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -14859,7 +18861,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>65536</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15265,11 +19267,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>16</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15296,37 +19298,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_aduh_monitor"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15342,7 +19344,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15406,7 +19408,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15475,7 +19477,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -15881,11 +19883,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15912,37 +19914,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bf_scale"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -15958,7 +19960,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16022,7 +20024,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16091,7 +20093,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16497,11 +20499,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16528,37 +20530,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -16574,7 +20576,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16638,7 +20640,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16707,7 +20709,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -17113,11 +21115,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17144,37 +21146,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17760,37 +21762,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -17806,7 +21808,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17870,7 +21872,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -17939,7 +21941,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18345,11 +22347,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18376,37 +22378,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18422,7 +22424,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18486,7 +22488,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18555,7 +22557,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18961,11 +22963,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18992,37 +22994,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19038,7 +23040,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19102,7 +23104,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19171,7 +23173,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19577,11 +23579,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19608,37 +23610,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19654,7 +23656,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19718,7 +23720,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19787,7 +23789,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20193,11 +24195,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20224,37 +24226,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20270,7 +24272,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20334,7 +24336,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20403,7 +24405,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20809,11 +24811,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20840,37 +24842,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21456,37 +25458,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22072,37 +26074,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22118,7 +26120,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22182,7 +26184,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22251,7 +26253,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22657,11 +26659,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22688,37 +26690,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22734,7 +26736,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22798,7 +26800,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22867,7 +26869,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23273,11 +27275,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23304,37 +27306,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23350,7 +27352,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23414,7 +27416,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23483,7 +27485,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23889,11 +27891,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23920,37 +27922,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23966,7 +27968,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24030,7 +28032,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24099,7 +28101,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24505,11 +28507,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24536,37 +28538,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25152,37 +29154,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_stat_enable_bst_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25768,37 +29770,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_stat_enable_bst_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26384,37 +30386,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26430,7 +30432,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26494,7 +30496,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26563,7 +30565,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26969,11 +30971,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27000,37 +31002,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_stat_hdr_dat_bst_0"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27046,7 +31048,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27110,7 +31112,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27179,7 +31181,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27585,11 +31587,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27616,37 +31618,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_stat_hdr_dat_bst_1"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27662,7 +31664,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27726,7 +31728,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27795,7 +31797,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28201,11 +32203,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28232,37 +32234,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_stat_hdr_dat_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28278,7 +32280,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28342,7 +32344,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28411,7 +32413,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28817,11 +32819,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28848,30 +32850,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -31358,7 +35360,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31422,7 +35424,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31491,7 +35493,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31897,11 +35899,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>12</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32686,7 +36688,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x3568" />
+ <parameter name="baseAddress" value="0x000a4080" />
</connection>
<connection
kind="avalon"
@@ -32700,14 +36702,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x3300" />
+ <parameter name="baseAddress" value="0x3600" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="rom_system_info.mem">
- <parameter name="baseAddress" value="0x1000" />
+ <parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="avalon"
@@ -32721,7 +36723,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x3560" />
+ <parameter name="baseAddress" value="0x000a4078" />
</connection>
<connection
kind="avalon"
@@ -32735,84 +36737,84 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x34e0" />
+ <parameter name="baseAddress" value="0x37e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x34c0" />
+ <parameter name="baseAddress" value="0x37c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x3558" />
+ <parameter name="baseAddress" value="0x000a4070" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x3550" />
+ <parameter name="baseAddress" value="0x000a4068" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x3548" />
+ <parameter name="baseAddress" value="0x000a4060" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x3540" />
+ <parameter name="baseAddress" value="0x000a4058" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x34a0" />
+ <parameter name="baseAddress" value="0x37a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x3500" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x3440" />
+ <parameter name="baseAddress" value="0x3740" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_st_sst.mem">
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x00090000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x3538" />
+ <parameter name="baseAddress" value="0x000a4050" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
- <parameter name="baseAddress" value="0x00070000" />
+ <parameter name="baseAddress" value="0x00080000" />
</connection>
<connection
kind="avalon"
@@ -32826,14 +36828,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x3400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_wg.mem">
- <parameter name="baseAddress" value="0x00060000" />
+ <parameter name="baseAddress" value="0x00070000" />
</connection>
<connection
kind="avalon"
@@ -32847,21 +36849,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x3530" />
+ <parameter name="baseAddress" value="0x000a4048" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x3480" />
+ <parameter name="baseAddress" value="0x3780" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x3300" />
</connection>
<connection
kind="avalon"
@@ -32875,28 +36877,28 @@
version="18.0"
start="cpu_0.data_master"
end="jesd204b.mem">
- <parameter name="baseAddress" value="0x00098000" />
+ <parameter name="baseAddress" value="0x000a0000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x3528" />
+ <parameter name="baseAddress" value="0x000a4040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_equalizer_gains.mem">
- <parameter name="baseAddress" value="0x00090000" />
+ <parameter name="baseAddress" value="0x00018000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="ram_ss_ss_wide.mem">
- <parameter name="baseAddress" value="0x00010000" />
+ <parameter name="baseAddress" value="0x00060000" />
</connection>
<connection
kind="avalon"
@@ -32910,7 +36912,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x3510" />
+ <parameter name="baseAddress" value="0x000a4010" />
</connection>
<connection
kind="avalon"
@@ -32924,7 +36926,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x3500" />
+ <parameter name="baseAddress" value="0x000a4000" />
</connection>
<connection
kind="avalon"
@@ -32938,14 +36940,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x3700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x3520" />
+ <parameter name="baseAddress" value="0x000a4038" />
</connection>
<connection
kind="avalon"
@@ -32973,14 +36975,56 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
+ <parameter name="baseAddress" value="0x000a4030" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_enable_sst.mem">
+ <parameter name="baseAddress" value="0x000a4028" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_hdr_dat_sst.mem">
+ <parameter name="baseAddress" value="0x3200" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_enable_bst_0.mem">
+ <parameter name="baseAddress" value="0x000a4020" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_enable_bst_1.mem">
<parameter name="baseAddress" value="0x3008" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_hdr_dat_bst_1.mem">
+ <parameter name="baseAddress" value="0x3100" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_stat_hdr_dat_bst_0.mem">
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
- <parameter name="baseAddress" value="0x0009c000" />
+ <parameter name="baseAddress" value="0x2000" />
</connection>
<connection
kind="avalon"
@@ -32994,7 +37038,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_tse">
- <parameter name="baseAddress" value="0x2000" />
+ <parameter name="baseAddress" value="0x1000" />
</connection>
<connection
kind="avalon"
@@ -33197,6 +37241,36 @@
version="18.0"
start="clk_0.clk"
end="pio_jesd_ctrl.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_hdr_dat_sst.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_enable_sst.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_enable_bst_0.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_enable_bst_1.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_hdr_dat_bst_1.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_stat_hdr_dat_bst_0.system" />
<connection
kind="interrupt"
version="18.0"
@@ -33438,6 +37512,36 @@
version="18.0"
start="clk_0.clk_reset"
end="pio_jesd_ctrl.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_enable_sst.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_hdr_dat_sst.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_enable_bst_0.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_enable_bst_1.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_hdr_dat_bst_1.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_stat_hdr_dat_bst_0.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 70df4b5df7277eb49c1f646442805263adc76b0b..44b7d53cf3daa2937c82387c8ccba3579e6fa3c0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -83,6 +83,12 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 9d999569781b9844f2a354f238a0930e40ea98b1..492a2f066bd4feb838d465a7b0d3125cd56c3124 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = lofar2_unb2b_sdp_station_bf
hdl_library_clause_name = lofar2_unb2b_sdp_station_bf_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = eth
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -9,9 +9,11 @@ hdl_lib_technology = ip_arria10_e1sg
test_bench_files =
tb_lofar2_unb2b_sdp_station_bf.vhd
+ tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
regression_test_vhdl =
tb_lofar2_unb2b_sdp_station_bf.vhd
+ tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
[modelsim_project_file]
modelsim_copy_files =
@@ -89,6 +91,12 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..429a7d3eab609b1160a8bbbba877c8945ea193c0
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -0,0 +1,249 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_bf capturing BST UDP offload packets.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable BSN source and enable BST offload
+--
+-- 2) Verify ethernet statistics using eth_statistics, it checks the number of
+-- received packets and the total number of valid data. The content of the packets is not verified.
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_bf_bst_offload IS
+END tb_lofar2_unb2b_sdp_station_bf_bst_offload;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf_bst_offload IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16; -- long enough to stream out udp data
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable_bst_0 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_BST_0";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL eth_done : STD_LOGIC := '0';
+
+ -- . 1GbE output
+ CONSTANT c_eth_check_nof_packets : NATURAL := 1; -- received packets in 1 sync period
+ CONSTANT c_eth_header_size : NATURAL := 19; -- words
+ CONSTANT c_eth_crc_size : NATURAL := 1; -- word
+ CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_eth_crc_size + (c_sdp_W_statistic / c_word_w) * c_sdp_S_sub_bf * c_sdp_N_pol; -- 20 + 2 * 488 * 2 = 1972
+ CONSTANT c_eth_check_nof_valid : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;
+ CONSTANT c_eth_runtime_timeout : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done at the second sync interval
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_bf : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+
+ ----------------------------------------------------------------------------
+ -- Offload enable
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable_bst_0, 0, 1, tb_clk);
+
+ -- wait for udp offload is done
+ proc_common_wait_until_high(ext_clk, eth_done);
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -------------------------------------------------------------------------
+ -- Verify proper DUT 1GbE offload output using Ethernet packet statistics
+ -------------------------------------------------------------------------
+ u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_valid
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index bbdd8b6c5416dc4d088a12432b3ef9486c385931..79c5c8a6cac59b00baafa79ba5fa55e52d5c7754 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = lofar2_unb2b_sdp_station_fsub
hdl_library_clause_name = lofar2_unb2b_sdp_station_fsub_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = eth
hdl_lib_technology = ip_arria10_e1sg
synth_files =
@@ -9,9 +9,11 @@ hdl_lib_technology = ip_arria10_e1sg
test_bench_files =
tb_lofar2_unb2b_sdp_station_fsub.vhd
+ tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
regression_test_vhdl =
tb_lofar2_unb2b_sdp_station_fsub.vhd
+ tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
[modelsim_project_file]
@@ -88,6 +90,12 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 1a467b6b499c9fa611d9feab9baf1cfdf113c68d..44f22b5dbe0e4c6e6190adda0914f29621adfb2d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -107,7 +107,6 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
TyPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub);
-- MM
- CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
@@ -117,7 +116,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL tb_clk : STD_LOGIC := '0';
- SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
-- WG
SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
@@ -142,8 +141,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
- SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
- SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
@@ -164,7 +163,6 @@ BEGIN
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
- eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
@@ -178,7 +176,7 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
ext_pps <= pps;
@@ -246,16 +244,17 @@ BEGIN
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
-
+
+ -- wait for pps
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
+
----------------------------------------------------------------------------
- -- Enable BS
+ -- Enable BSN
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
----------------------------------------------------------------------------
-- Enable WG
@@ -278,13 +277,13 @@ BEGIN
-- Write scheduler BSN to trigger start of WG at next block
v_bsn := TO_UINT(current_bsn_wg) + 2;
ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
- v_bsn := c_bsn_start_wg;
- mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- Wait for enough WG data and start of sync interval
+
mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ "UNSIGNED", rd_data, ">=", c_nof_block_per_sync * 3, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
@@ -351,7 +350,7 @@ BEGIN
---------------------------------------------------------------------------
-- End Simulation
- ---------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
sim_done <= '1';
proc_common_wait_some_cycles(ext_clk, 100);
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ac3bffbe3e31ee2d4815f4d42c2d7bb2279103ec
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -0,0 +1,249 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_sdp_station_fsub capturing SST UDP offload packets.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable BSN source and enable UDP offload
+--
+-- 2) Verify ethernet statistics using eth_statistics, it checks the number of
+-- received packets and the total number of valid data. The content of the packets is not verified.
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station_fsub_sst_offload IS
+END tb_lofar2_unb2b_sdp_station_fsub_sst_offload;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub_sst_offload IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 80; -- long enough to stream out udp data
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL eth_done : STD_LOGIC := '0';
+
+ -- . 1GbE output
+ CONSTANT c_eth_check_nof_packets : NATURAL := c_sdp_S_pn; -- received packets in 1 sync period
+ CONSTANT c_eth_header_size : NATURAL := 19; -- words
+ CONSTANT c_eth_crc_size : NATURAL := 1; -- word
+ CONSTANT c_eth_packet_size : NATURAL := c_eth_header_size + c_eth_crc_size + c_sdp_N_sub * (c_sdp_W_statistic / c_word_w); -- 20 + 512 * 2 = 1044
+ CONSTANT c_eth_check_nof_valid : NATURAL := c_eth_check_nof_packets * c_eth_packet_size;
+ CONSTANT c_eth_runtime_timeout : TIME := 2 * c_nof_clk_per_sync * c_ext_clk_period; -- eth statistics should be done at the second sync interval
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0) := (OTHERS => '0');
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_sdp_station_fsub : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_fsub",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BSN
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000001#, tb_clk); -- Enable BSN immediately
+
+ ----------------------------------------------------------------------------
+ -- Offload enable
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+
+ -- wait for udp offload is done
+ proc_common_wait_until_high(ext_clk, eth_done);
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -------------------------------------------------------------------------
+ -- Verify proper DUT 1GbE offload output using Ethernet packet statistics
+ -------------------------------------------------------------------------
+ u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_valid
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 0e2c058d57ea520fe9bf7991b49e1bb95df5e83a..1793c7e65cbf4ca8dd410329816b608b2f1e520f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -26,7 +26,7 @@
-- Unb2b version for lab testing
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -41,6 +41,8 @@ USE dp_lib.dp_stream_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
USE lofar2_sdp_lib.sdp_pkg.ALL;
USE work.lofar2_unb2b_sdp_station_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
ENTITY lofar2_unb2b_sdp_station IS
GENERIC (
@@ -55,7 +57,7 @@ ENTITY lofar2_unb2b_sdp_station IS
g_revision_id : STRING := ""; -- revision ID -- set by QSF
g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range : BOOLEAN := FALSE;
- g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_bsn_nof_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
g_scope_selected_subband : NATURAL := 0
);
@@ -111,12 +113,12 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
CONSTANT c_revision_select : t_lofar2_unb2b_sdp_station_config := func_sel_revision_rec(g_design_name);
-- Firmware version x.y
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (2, 0);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
CONSTANT c_lofar2_sample_clk_freq : NATURAL := c_sdp_f_adc_MHz * 10**6; -- fixed 200 MHz for LOFAR2.0 stage 1
-- 10 GbE Interface
- CONSTANT c_nof_streams_qsfp : NATURAL := 4;
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.nof_bus * c_quad;
CONSTANT c_nof_qsfp_bus : NATURAL := 1;
CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
CONSTANT c_nof_blocks_per_packet : NATURAL := 4;
@@ -132,11 +134,14 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+
+ --
+ CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
-
+
SIGNAL gn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
SIGNAL gn_index : NATURAL := 0;
@@ -328,6 +333,33 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ ----------------------------------------------
+ -- SST
+ ----------------------------------------------
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_sst_mosi : t_mem_mosi;
+ SIGNAL reg_stat_enable_sst_miso : t_mem_miso;
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
+ SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+ ----------------------------------------------
+ -- BST
+ ----------------------------------------------
+ -- Statistics Enable
+ SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ -- Statistics header info
+ SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ ----------------------------------------------
+ -- UDP Offload
+ ----------------------------------------------
+ SIGNAL udp_tx_sosi_arr : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL udp_tx_siso_arr : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
----------------------------------------------
-- 10 GbE
----------------------------------------------
@@ -352,8 +384,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL tr_ref_clk_156 : STD_LOGIC;
SIGNAL tr_ref_rst_156 : STD_LOGIC;
- SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
- SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+ SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => '0');
@@ -383,9 +415,9 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL unb2_board_qsfp_leds_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2_board_qsfp_leds_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2_board_qsfp_leds_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2b_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2b_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL unb2b_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
BEGIN
@@ -394,21 +426,23 @@ BEGIN
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range,
- g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
- g_dp_clk_use_pll => FALSE
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range,
+ g_dp_clk_freq => c_unb2b_board_ext_clk_freq_200M,
+ g_dp_clk_use_pll => FALSE,
+ g_udp_offload => TRUE,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
)
PORT MAP (
-- Clock an reset signals
@@ -490,6 +524,10 @@ BEGIN
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
+ -- eth1g UDP streaming
+ udp_tx_sosi_arr => udp_tx_sosi_arr,
+ udp_tx_siso_arr => udp_tx_siso_arr,
+
ram_scrap_mosi => ram_scrap_mosi,
ram_scrap_miso => ram_scrap_miso,
@@ -535,42 +573,42 @@ BEGIN
pout_wdi => pout_wdi,
-- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
-- mm buses for signal flow blocks
-- Jesd ip status/control
@@ -625,7 +663,19 @@ BEGIN
reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso
+ ram_scrap_miso => ram_scrap_miso,
+ reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
+ reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
+ reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_bst_0_mosi => reg_stat_enable_bst_mosi_arr(0),
+ reg_stat_enable_bst_0_miso => reg_stat_enable_bst_miso_arr(0),
+ reg_stat_hdr_dat_bst_0_mosi => reg_stat_hdr_dat_bst_mosi_arr(0),
+ reg_stat_hdr_dat_bst_0_miso => reg_stat_hdr_dat_bst_miso_arr(0),
+ reg_stat_enable_bst_1_mosi => reg_stat_enable_bst_mosi_arr(1),
+ reg_stat_enable_bst_1_miso => reg_stat_enable_bst_miso_arr(1),
+ reg_stat_hdr_dat_bst_1_mosi => reg_stat_hdr_dat_bst_mosi_arr(1),
+ reg_stat_hdr_dat_bst_1_miso => reg_stat_hdr_dat_bst_miso_arr(1)
);
-----------------------------------------------------------------------------
@@ -637,6 +687,7 @@ BEGIN
cep_eth_src_mac <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
cep_ip_src_addr <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+
stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
@@ -732,6 +783,9 @@ BEGIN
in_sosi_arr => ait_sosi_arr,
pfb_sosi_arr => pfb_sosi_arr,
fsub_sosi_arr => fsub_sosi_arr,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -746,6 +800,11 @@ BEGIN
ram_gains_miso => ram_equalizer_gains_miso,
reg_selector_mosi => reg_dp_selector_mosi,
reg_selector_miso => reg_dp_selector_miso,
+
+ reg_enable_mosi => reg_stat_enable_sst_mosi,
+ reg_enable_miso => reg_stat_enable_sst_miso,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
sdp_info => sdp_info,
gn_id => gn_id,
@@ -774,24 +833,28 @@ BEGIN
in_sosi_arr => fsub_sosi_arr,
bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
bf_udp_siso => bf_udp_siso_arr(beamset_id),
- bst_udp_sosi => OPEN,
+ bst_udp_sosi => udp_tx_sosi_arr(1+ beamset_id),
+ bst_udp_siso => udp_tx_siso_arr(1+ beamset_id),
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_sst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_sst_miso => ram_st_bst_miso_arr(beamset_id),
-
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
sdp_info => sdp_info,
gn_id => gn_id,
@@ -799,6 +862,10 @@ BEGIN
ip_src_addr => cep_ip_src_addr,
udp_src_port => cep_udp_src_port,
+ stat_eth_src_mac => stat_eth_src_mac,
+ stat_ip_src_addr => stat_ip_src_addr,
+ stat_udp_src_port => bst_udp_src_port,
+
hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
);
@@ -902,49 +969,7 @@ BEGIN
src_out => nw_10gbe_snk_in_arr(0),
src_in => nw_10gbe_snk_out_arr(0)
);
-
- -----------------------------------------------------------------------------
- -- Interface : 10GbE
- -----------------------------------------------------------------------------
- -- put the QSFP_TX/RX ports into arrays
- i_QSFP_RX(0) <= QSFP_1_RX;
- QSFP_1_TX <= i_QSFP_TX(0);
- ------------
- -- Front IO
- ------------
- u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
- GENERIC MAP (
- g_nof_qsfp_bus => c_nof_qsfp_bus
- )
- PORT MAP (
- serial_tx_arr => unb2_board_front_io_serial_tx_arr,
- serial_rx_arr => unb2_board_front_io_serial_rx_arr,
-
- green_led_arr => qsfp_green_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
- red_led_arr => qsfp_red_led_arr(c_nof_qsfp_bus-1 DOWNTO 0),
-
- QSFP_RX => i_QSFP_RX,
- QSFP_TX => i_QSFP_TX,
-
- QSFP_LED => QSFP_LED
- );
-
- ---------
- -- PLL
- ---------
- u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- refclk_644 => SA_CLK,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => OPEN
- );
-
+
---------------
-- nw_10GbE
---------------
@@ -995,4 +1020,74 @@ BEGIN
hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
);
END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Interface : 10GbE
+ -----------------------------------------------------------------------------
+ -- put the QSFP_TX/RX ports into arrays
+ i_QSFP_RX(0) <= QSFP_1_RX;
+ QSFP_1_TX <= i_QSFP_TX(0);
+ ------------
+ -- Front IO
+ ------------
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ PORT MAP (
+ serial_tx_arr => unb2_board_front_io_serial_tx_arr,
+ serial_rx_arr => unb2_board_front_io_serial_rx_arr,
+
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ QSFP_RX => i_QSFP_RX,
+ QSFP_TX => i_QSFP_TX,
+
+ QSFP_LED => QSFP_LED
+ );
+
+ ---------
+ -- PLL
+ ---------
+ u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ ------------
+ -- LEDs
+ ------------
+ unb2b_board_qsfp_leds_tx_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_out_arr;
+ unb2b_board_qsfp_leds_tx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_snk_in_arr;
+ unb2b_board_qsfp_leds_rx_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0) <= nw_10gbe_src_out_arr;
+
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+
+ tx_siso_arr => unb2b_board_qsfp_leds_tx_siso_arr,
+ tx_sosi_arr => unb2b_board_qsfp_leds_tx_sosi_arr,
+ rx_sosi_arr => unb2b_board_qsfp_leds_rx_sosi_arr
+ );
+
+
+
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 41c51dd2529fdc9432f5d82e6a22de87d5acf6a7..1021899a027b7b34c3f577bc7a70f2c46a1db693 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -182,6 +182,30 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
ram_st_bst_mosi : OUT t_mem_mosi;
ram_st_bst_miso : IN t_mem_miso;
+ -- Subband Statistics offload
+ reg_stat_enable_sst_mosi : OUT t_mem_mosi;
+ reg_stat_enable_sst_miso : IN t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+
+ -- Beamlet Statistics offload BS 0
+ reg_stat_enable_bst_0_mosi : OUT t_mem_mosi;
+ reg_stat_enable_bst_0_miso : IN t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_bst_0_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_bst_0_miso : IN t_mem_miso;
+
+ -- Beamlet Statistics offload BS 1
+ reg_stat_enable_bst_1_mosi : OUT t_mem_mosi;
+ reg_stat_enable_bst_1_miso : IN t_mem_miso;
+
+ -- Statistics header info
+ reg_stat_hdr_dat_bst_1_mosi : OUT t_mem_mosi;
+ reg_stat_hdr_dat_bst_1_miso : IN t_mem_miso;
+
-- 10 GbE mac
reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
reg_nw_10GbE_mac_miso : IN t_mem_miso;
@@ -215,105 +239,123 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
- u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
- u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
- u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
- u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
- u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
- u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
- u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
- u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
- u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
- u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
- u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
+ PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
- u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
- u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
- u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
- u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
- u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
+ PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
+ PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
- u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
- u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
- u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
+ PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
- u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
+ PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
- u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
+ PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
- u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
+ PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
- u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
- u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
+ PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
- u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
- u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
- u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
+ PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
- u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
+ PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
- u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
- u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
- u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
+ PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+
+ u_mm_file_reg_stat_enable_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_mosi, reg_stat_enable_sst_miso );
- u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
- u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ u_mm_file_reg_stat_enable_bst_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST_0")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_0_mosi, reg_stat_enable_bst_0_miso );
- u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ u_mm_file_reg_stat_hdr_info_bst_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST_0")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_0_mosi, reg_stat_hdr_dat_bst_0_miso);
+
+ u_mm_file_reg_stat_enable_bst_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST_1")
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_1_mosi, reg_stat_enable_bst_1_miso );
+
+ u_mm_file_reg_stat_hdr_info_bst_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST_1")
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_1_mosi, reg_stat_hdr_dat_bst_1_miso);
+
+ u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+
+ u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+
+ u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
@@ -392,8 +434,8 @@ BEGIN
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+-- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
@@ -659,6 +701,54 @@ BEGIN
ram_st_bst_read_export => ram_st_bst_mosi.rd,
ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_clk_export => OPEN,
+ reg_stat_enable_sst_reset_export => OPEN,
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_mosi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_mosi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_sst_clk_export => OPEN,
+ reg_stat_hdr_dat_sst_reset_export => OPEN,
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_mosi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_enable_bst_0_clk_export => OPEN,
+ reg_stat_enable_bst_0_reset_export => OPEN,
+ reg_stat_enable_bst_0_address_export => reg_stat_enable_bst_0_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_0_write_export => reg_stat_enable_bst_0_mosi.wr,
+ reg_stat_enable_bst_0_writedata_export => reg_stat_enable_bst_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_0_read_export => reg_stat_enable_bst_0_mosi.rd,
+ reg_stat_enable_bst_0_readdata_export => reg_stat_enable_bst_0_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_bst_0_clk_export => OPEN,
+ reg_stat_hdr_dat_bst_0_reset_export => OPEN,
+ reg_stat_hdr_dat_bst_0_address_export => reg_stat_hdr_dat_bst_0_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_0_write_export => reg_stat_hdr_dat_bst_0_mosi.wr,
+ reg_stat_hdr_dat_bst_0_writedata_export => reg_stat_hdr_dat_bst_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_0_read_export => reg_stat_hdr_dat_bst_0_mosi.rd,
+ reg_stat_hdr_dat_bst_0_readdata_export => reg_stat_hdr_dat_bst_0_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_enable_bst_1_clk_export => OPEN,
+ reg_stat_enable_bst_1_reset_export => OPEN,
+ reg_stat_enable_bst_1_address_export => reg_stat_enable_bst_1_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_1_write_export => reg_stat_enable_bst_1_mosi.wr,
+ reg_stat_enable_bst_1_writedata_export => reg_stat_enable_bst_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_1_read_export => reg_stat_enable_bst_1_mosi.rd,
+ reg_stat_enable_bst_1_readdata_export => reg_stat_enable_bst_1_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_stat_hdr_dat_bst_1_clk_export => OPEN,
+ reg_stat_hdr_dat_bst_1_reset_export => OPEN,
+ reg_stat_hdr_dat_bst_1_address_export => reg_stat_hdr_dat_bst_1_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_1_write_export => reg_stat_hdr_dat_bst_1_mosi.wr,
+ reg_stat_hdr_dat_bst_1_writedata_export => reg_stat_hdr_dat_bst_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_1_read_export => reg_stat_hdr_dat_bst_1_mosi.rd,
+ reg_stat_hdr_dat_bst_1_readdata_export => reg_stat_hdr_dat_bst_1_miso.rddata(c_word_w-1 DOWNTO 0),
+
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 1f8d495b0b7dea61db86c6642e138995248ca9c7..f4f915592f2f5676e97b63d237e533e52fab2c98 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -287,6 +287,48 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_sdp_info_reset_export : out std_logic; -- export
reg_sdp_info_write_export : out std_logic; -- export
reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_0_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_bst_0_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_0_read_export : out std_logic; -- export
+ reg_stat_enable_bst_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_0_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_0_write_export : out std_logic; -- export
+ reg_stat_enable_bst_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_0_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_bst_0_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_0_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_0_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_0_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_0_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_0_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_1_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_bst_1_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_1_read_export : out std_logic; -- export
+ reg_stat_enable_bst_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_1_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_1_write_export : out std_logic; -- export
+ reg_stat_enable_bst_1_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_1_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_bst_1_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_1_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_1_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_1_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_1_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_1_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_si_address_export : out std_logic_vector(0 downto 0); -- export
reg_si_clk_export : out std_logic; -- export
reg_si_read_export : out std_logic; -- export
@@ -323,7 +365,7 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_wg_write_export : out std_logic; -- export
reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
rom_system_info_clk_export : out std_logic; -- export
rom_system_info_read_export : out std_logic; -- export
rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d3198bf0d2b4db7888cd4efed534c3cdc08ca31d
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -0,0 +1,260 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Test statistics offload with "ethernet packet statistics" in wave window only
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station IS
+END tb_lofar2_unb2b_sdp_station;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+
+ -- WG
+ CONSTANT c_full_scale_ampl : REAL := REAL(2**(18-1) - 1); -- = full scale of WG
+ CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit / REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+ CONSTANT c_wg_freq_offset : REAL := 0.0 / 11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
+
+-- . 1GbE output
+ CONSTANT c_eth_check_nof_packets : NATURAL := 4512; -- received packets in 2 sync periods
+ CONSTANT c_eth_runtime_timeout : TIME := 100 ms; -- factor 2 margin
+
+ -- MM
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL eth_done : STD_LOGIC := '0';
+ SIGNAL verify_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+ -- System setup
+ ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ -- External PPS
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ -- >> DUT <<
+ u_lofar_unb2b_sdp_station : ENTITY work.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_sdp_station_bf",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_wpfb => c_wpfb_sim,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+
+ ---------------------------------------------------------------------------------------------------------------------
+ -- Stimuli
+ -- MM slave accesses via file IO
+ tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ CONSTANT c_mm_file_reg_stat_enable : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+ CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
+ VARIABLE v_bsn : NATURAL;
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ -- Enable BS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 1, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ -- Enable WG
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024 * 2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk); -- ampl
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ v_bsn := c_bsn_start_wg;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ -- Wait for ADUH monitor to have filled with WG data
+ WAIT FOR c_sdp_T_sub * c_sdp_N_taps;
+ WAIT FOR c_sdp_T_sub * 2;
+
+ -- Offload enable
+ mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+
+ -- End Simulation
+ proc_common_wait_until_high(ext_clk, eth_done);
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -- >> Verify proper DUT output using Ethernet packet statistics <<
+ u_eth_statistics : ENTITY eth_lib.eth_statistics
+ GENERIC MAP (
+ g_runtime_nof_packets => c_eth_check_nof_packets,
+ g_runtime_timeout => c_eth_runtime_timeout,
+ g_check_nof_valid => TRUE,
+ g_check_nof_valid_ref => c_eth_check_nof_packets
+ )
+ PORT MAP (
+ eth_serial_in => eth_txp(0),
+ tb_end => eth_done
+ );
+
+END tb;
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
index 6dc4dd599952403683f07df927ef8fe576e5a4fc..86d425c6093b5ff9422589b1dcfc389045216be6 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt
@@ -329,7 +329,16 @@ Design options:
==> Design decision:
Do not make or use a dp_sync_aligner, because loosing an entire sync interval is not acceptable.
-
+. Assume circular buffer:
+ - advantage:
+ . direct access to each word in block
+ . no need to flush blocks, status bit per block tells whether it is filled
+ - buffer is filled and read after certain latency, because then all remote packets should have arrived
+ . provide CP for active input streams, is this needed ?
+ - use MM interface to read from head column (with block for all parallel streams)
+ - provide mm to dp component with bsn aligner (= dp_block_from_mm ?)
+ - provide MP for nof lost = nof filler blocks / stream ?
+ . err at eop indicates lost = filler data, sosi_info could have eop at sop like with crosslets_info
. Initial alignment:
- Assume the received packets on the inputs contain one block per packet.
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 843a49247a740b06c32a726543192f50f3590cc8..7068a9f4104a54a404540a09e830491c0ded6074 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -18,6 +18,7 @@ synth_files =
src/vhdl/node_sdp_adc_input_and_timing.vhd
src/vhdl/node_sdp_filterbank.vhd
src/vhdl/node_sdp_beamformer.vhd
+ src/vhdl/node_sdp_correlator.vhd
test_bench_files =
tb/vhdl/tb_sdp_info.vhd
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 166db254179b429d95f53754422cea9b4f937c21..2542eff1d91997df3074d65cd3546b415a56bfc5 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -175,50 +175,48 @@ peripherals:
"
fields:
# eth field group
- - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0xA0 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x98 }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x94 }
# ip field group
- - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x90 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x88 }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x80 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x7C }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x78 }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x68 }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x64 }
# udp field group
- - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x58 }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x54 }
# application field group
- - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- - "source_info":
- - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: beamlet_width, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, mm_width: 32, user_width: 40, radix: uint64, access_mode: RW, address_offset: 0x1C }
- - - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x18 }
- - - { field_name: beamlet_index, mm_width: 16, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_blocks_per_packet, mm_width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_beamlets_per_block, mm_width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: sdp_marker, mm_width: 8, access_mode: RO, address_offset: 0x50 }
+ - - { field_name: sdp_version_id, mm_width: 8, access_mode: RO, address_offset: 0x4C }
+ - - { field_name: sdp_observation_id, mm_width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: sdp_station_id, mm_width: 16, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: sdp_source_info_antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: sdp_source_info_nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: sdp_source_info_f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x30 }
+ - - { field_name: sdp_source_info_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_beamlet_width, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+
+ - - { field_name: sdp_reserved, mm_width: 32, user_width: 40, radix: uint64, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: sdp_beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x18 }
+ - - { field_name: sdp_beamlet_index, mm_width: 16, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: sdp_nof_blocks_per_packet, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: sdp_nof_beamlets_per_block, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: sdp_block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -239,57 +237,54 @@ peripherals:
"
fields:
# eth field group
- - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0xAC }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0xA4 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x9C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x98 }
# ip field group
- - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x94 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x90 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x88 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x80 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x7C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x78 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x68 }
# udp field group
- - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x58 }
# application field group
- - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- - "source_info":
- - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- - "data_id_sst":
- - { field_name: reserved, mm_width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
-
- - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: sdp_marker, mm_width: 8, access_mode: RO, address_offset: 0x54 }
+ - - { field_name: sdp_version_id, mm_width: 8, access_mode: RO, address_offset: 0x50 }
+ - - { field_name: sdp_observation_id, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: sdp_station_id, mm_width: 16, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: sdp_source_info_antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: sdp_source_info_nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: sdp_source_info_f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
+ - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: sdp_integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: sdp_data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
+ - "sdp_data_id_sst":
+ - { field_name: reserved, mm_width: 24, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: sdp_nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: sdp_nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: sdp_nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: sdp_block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -310,57 +305,54 @@ peripherals:
"
fields:
# eth field group
- - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0xAC }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0xA4 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x9C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x98 }
# ip field group
- - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x94 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x90 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x88 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x80 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x7C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x78 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x68 }
# udp field group
- - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x58 }
# application field group
- - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- - "source_info":
- - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- - "data_id_bst":
- - { field_name: reserved, mm_width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: beamlet_index, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
-
- - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
+ - - { field_name: sdp_marker, mm_width: 8, access_mode: RO, address_offset: 0x54 }
+ - - { field_name: sdp_version_id, mm_width: 8, access_mode: RO, address_offset: 0x50 }
+ - - { field_name: sdp_observation_id, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: sdp_station_id, mm_width: 16, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: sdp_source_info_antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: sdp_source_info_nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: sdp_source_info_f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
+ - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: sdp_integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: sdp_data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
+ - "sdp_data_id_bst":
+ - { field_name: reserved, mm_width: 16, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: beamlet_index, mm_width: 16, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -382,57 +374,53 @@ peripherals:
"
fields:
# eth field group
- - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0x8C }
- - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0x84 }
- - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x7C }
- - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x78 }
+ - - { field_name: word_align, mm_width: 16, access_mode: RW, address_offset: 0xAC }
+ - - { field_name: eth_destination_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RW, address_offset: 0xA4 }
+ - - { field_name: eth_source_mac, mm_width: 32, user_width: 48, radix: uint64, access_mode: RO, address_offset: 0x9C }
+ - - { field_name: eth_type, mm_width: 16, access_mode: RO, address_offset: 0x98 }
# ip field group
- - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x74 }
- - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x70 }
- - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x6C }
- - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x68 }
- - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x64 }
- - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x60 }
- - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x5C }
- - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x58 }
- - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x54 }
- - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x50 }
- - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x4C }
- - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: ip_version, mm_width: 4, access_mode: RW, address_offset: 0x94 }
+ - - { field_name: ip_header_length, mm_width: 4, access_mode: RW, address_offset: 0x90 }
+ - - { field_name: ip_services, mm_width: 8, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: ip_total_length, mm_width: 16, access_mode: RW, address_offset: 0x88 }
+ - - { field_name: ip_identification, mm_width: 16, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: ip_flags, mm_width: 3, access_mode: RW, address_offset: 0x80 }
+ - - { field_name: ip_fragment_offset, mm_width: 13, access_mode: RW, address_offset: 0x7C }
+ - - { field_name: ip_time_to_live, mm_width: 8, access_mode: RW, address_offset: 0x78 }
+ - - { field_name: ip_protocol, mm_width: 8, access_mode: RW, address_offset: 0x74 }
+ - - { field_name: ip_header_checksum, mm_width: 16, access_mode: RW, address_offset: 0x70 }
+ - - { field_name: ip_source_address, mm_width: 32, access_mode: RW, address_offset: 0x6C }
+ - - { field_name: ip_destination_address, mm_width: 32, access_mode: RW, address_offset: 0x68 }
# udp field group
- - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x44 }
- - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x40 }
- - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x3C }
- - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: udp_source_port, mm_width: 16, access_mode: RW, address_offset: 0x64 }
+ - - { field_name: udp_destination_port, mm_width: 16, access_mode: RW, address_offset: 0x60 }
+ - - { field_name: udp_length, mm_width: 16, access_mode: RW, address_offset: 0x5C }
+ - - { field_name: udp_checksum, mm_width: 16, access_mode: RW, address_offset: 0x58 }
# application field group
- - - { field_name: marker, mm_width: 8, access_mode: RO, address_offset: 0x34 }
- - - { field_name: version_id, mm_width: 8, access_mode: RO, address_offset: 0x30 }
- - - { field_name: observation_id, mm_width: 32, access_mode: RW, address_offset: 0x2C }
- - - { field_name: station_id, mm_width: 16, access_mode: RW, address_offset: 0x28 }
- - - { field_name: source_info, mm_width: 16, access_mode: RW, address_offset: 0x24 }
- - "source_info":
- - { field_name: antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x24 }
- - { field_name: nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x24 }
- - { field_name: f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x24 }
- - { field_name: fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x24 }
- - { field_name: payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x24 }
- - { field_name: beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x24 }
- - { field_name: subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x24 }
- - { field_name: reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- - { field_name: gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
-
- - - { field_name: reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
- - - { field_name: integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
- - - { field_name: data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
- - "data_id_xst":
- - { field_name: reserved, mm_width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
- - { field_name: subband_index, mm_width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_A_index, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
- - { field_name: signal_input_B_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
-
- - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
- - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
- - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
- - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
-
+ - - { field_name: sdp_marker, mm_width: 8, access_mode: RO, address_offset: 0x54 }
+ - - { field_name: sdp_version_id, mm_width: 8, access_mode: RO, address_offset: 0x50 }
+ - - { field_name: sdp_observation_id, mm_width: 32, access_mode: RW, address_offset: 0x4C }
+ - - { field_name: sdp_station_id, mm_width: 16, access_mode: RW, address_offset: 0x48 }
+ - - { field_name: sdp_source_info_antenna_band_index, mm_width: 1, bit_offset: 15, access_mode: RW, address_offset: 0x44 }
+ - - { field_name: sdp_source_info_nyquist_zone_index, mm_width: 2, bit_offset: 13, access_mode: RW, address_offset: 0x40 }
+ - - { field_name: sdp_source_info_f_adc, mm_width: 1, bit_offset: 12, access_mode: RW, address_offset: 0x3C }
+ - - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
+ - - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
+ - - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
+ - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
+ - - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
+ - - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
+ - - { field_name: sdp_integration_interval, mm_width: 24, access_mode: RW, address_offset: 0x1C }
+ - - { field_name: sdp_data_id, mm_width: 32, access_mode: RW, address_offset: 0x18 }
+ - "sdp_data_id_xst":
+ - { field_name: reserved, mm_width: 7, bit_offset: 25, access_mode: RW, address_offset: 0x18 }
+ - { field_name: subband_index, mm_width: 9, bit_offset: 16, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_A_index, mm_width: 8, bit_offset: 8, access_mode: RW, address_offset: 0x18 }
+ - { field_name: signal_input_B_index, mm_width: 8, bit_offset: 0, access_mode: RW, address_offset: 0x18 }
+
+ - - { field_name: nof_signal_inputs, mm_width: 8, access_mode: RW, address_offset: 0x14 }
+ - - { field_name: nof_bytes_per_statistic, mm_width: 8, access_mode: RW, address_offset: 0x10 }
+ - - { field_name: nof_statistics_per_packet, mm_width: 16, access_mode: RW, address_offset: 0xC }
+ - - { field_name: block_period, mm_width: 16, access_mode: RW, address_offset: 0x8 }
+ - - { field_name: BSN, mm_width: 32, user_width: 64, radix: uint64, access_mode: RW, address_offset: 0x0 }
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index f453ee5fe4155b5da629f372409a96ef7614029d..bf0dda7f3cb4bc0c62564fd2a38d4de81bbf9b30 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -29,7 +29,7 @@
-- .
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib;
+LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
@@ -39,9 +39,10 @@ USE work.sdp_pkg.ALL;
ENTITY node_sdp_beamformer IS
GENERIC (
- g_sim : BOOLEAN := FALSE;
- g_beamset_id : NATURAL := 0;
- g_scope_selected_beamlet : NATURAL := 0
+ g_sim : BOOLEAN := FALSE;
+ g_beamset_id : NATURAL := 0;
+ g_scope_selected_beamlet : NATURAL := 0;
+ g_offload_time : NATURAL := c_sdp_offload_time
);
PORT (
dp_clk : IN STD_LOGIC;
@@ -51,22 +52,27 @@ ENTITY node_sdp_beamformer IS
bf_udp_sosi : OUT t_dp_sosi;
bf_udp_siso : IN t_dp_siso;
bst_udp_sosi : OUT t_dp_sosi;
+ bst_udp_siso : IN t_dp_siso;
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
- ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_ss_ss_wide_miso : OUT t_mem_miso;
- ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_bf_weights_miso : OUT t_mem_miso;
- reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bf_scale_miso : OUT t_mem_miso;
- reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_hdr_dat_miso : OUT t_mem_miso;
- reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_xonoff_miso : OUT t_mem_miso;
- ram_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_sst_miso : OUT t_mem_miso;
+ ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_ss_ss_wide_miso : OUT t_mem_miso;
+ ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_bf_weights_miso : OUT t_mem_miso;
+ reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bf_scale_miso : OUT t_mem_miso;
+ reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_hdr_dat_miso : OUT t_mem_miso;
+ reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_xonoff_miso : OUT t_mem_miso;
+ ram_st_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_bst_miso : OUT t_mem_miso;
+ reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_enable_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_stat_hdr_dat_miso : OUT t_mem_miso;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -75,22 +81,38 @@ ENTITY node_sdp_beamformer IS
ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
- hdr_fields_out : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0) -- Needed by nw_10GbE for PING/ARP
+ hdr_fields_out : OUT STD_LOGIC_VECTOR(1023 DOWNTO 0); -- Needed by nw_10GbE for PING/ARP
+
+ stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
+
);
END node_sdp_beamformer;
ARCHITECTURE str OF node_sdp_beamformer IS
CONSTANT c_bf_select_file_prefix : STRING := "data/bf_unit_ss_wide";
- CONSTANT c_bf_weights_file_name : STRING := "data/bf_unit_weights";
-
- SIGNAL bsel_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL local_bf_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL bf_out_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL scope_local_bf_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
- SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
- SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
+ CONSTANT c_bf_weights_file_name : STRING := "data/bf_unit_weights";
+
+ CONSTANT c_nof_masters : POSITIVE := 2;
+
+ -- beamlet statistics
+ SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+ SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+
+ SIGNAL bsel_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL local_bf_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL bf_out_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL scope_local_bf_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
+ SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
+ SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol-1 DOWNTO 0);
BEGIN
---------------------------------------------------------------
-- Beamlet Subband Select
@@ -222,19 +244,69 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
in_complex => bf_sum_sosi,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso
+ ram_st_sst_mosi => master_mem_mux_mosi,
+ ram_st_sst_miso => master_mem_mux_miso
);
---------------------------------------------------------------
-- MM master multiplexer
---------------------------------------------------------------
- -- Not yet implemented
+ -- Connect 2 mm_masters to the common_mem_mux output
+ master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
+ ram_st_bst_miso <= master_miso_arr(0);
+ master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+ ram_st_offload_miso <= master_miso_arr(1);
+
+ u_mem_master_mux : ENTITY mm_lib.mm_master_mux
+ GENERIC MAP (
+ g_nof_masters => c_nof_masters,
+ g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+
+ master_mosi_arr => master_mosi_arr,
+ master_miso_arr => master_miso_arr,
+ mux_mosi => master_mem_mux_mosi,
+ mux_miso => master_mem_mux_miso
+ );
---------------------------------------------------------------
-- BST UDP offload
---------------------------------------------------------------
- -- Not yet implemented
+ u_sdp_bst_udp_offload: ENTITY work.sdp_statistics_offload
+ GENERIC MAP (
+ g_statistics_type => "BST",
+ g_offload_time => g_offload_time,
+ g_beamset_id => g_beamset_id
+ )
+ PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ master_mosi => ram_st_offload_mosi,
+ master_miso => ram_st_offload_miso,
+
+ reg_enable_mosi => reg_stat_enable_mosi,
+ reg_enable_miso => reg_stat_enable_miso,
+
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+
+ sdp_info => sdp_info,
+ gn_index => TO_UINT(gn_id),
+
+ in_sosi => bf_sum_sosi,
+ out_sosi => bst_udp_sosi,
+ out_siso => bst_udp_siso,
+
+ eth_src_mac => stat_eth_src_mac,
+ udp_src_port => stat_udp_src_port,
+ ip_src_addr => stat_ip_src_addr
+ );
---------------------------------------------------------------
-- SIGNAL SCOPES
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1a28839eecb89d4fec64d3176b3d0bed61bb06d9
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -0,0 +1,299 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- . Implements the functionality of the Subband Correlator in the
+-- LOFAR2 SDPFW design.
+-- Description:
+-- Remark:
+-- .
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.sdp_pkg.ALL;
+
+ENTITY node_sdp_correlator IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_P_sq : NATURAL := c_sdp_P_sq
+ --g_offload_time : NATURAL := c_sdp_offload_time
+ );
+ PORT (
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ --xst_udp_sosi : OUT t_dp_sosi;
+ --xst_udp_siso : IN t_dp_siso;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_sync_insert_v2_miso : OUT t_mem_miso;
+ reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_crosslets_info_miso : OUT t_mem_miso;
+ reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso;
+
+ --sdp_info : IN t_sdp_info;
+ --gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ --stat_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
+ --stat_ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
+ --stat_udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0)
+
+ out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
+
+ );
+END node_sdp_correlator;
+
+ARCHITECTURE str OF node_sdp_correlator IS
+
+-- CONSTANT c_nof_masters : POSITIVE := 2;
+
+ -- crosslet statistics offload
+-- SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
+-- SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
+
+-- SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+-- SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+-- SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
+-- SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
+
+ SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+BEGIN
+ ---------------------------------------------------------------
+ -- Requantize 18b to 16b
+ ---------------------------------------------------------------
+ gen_requantize : FOR I IN 0 TO c_sdp_P_pfb-1 GENERATE
+ u_dp_requantize : ENTITY dp_lib.dp_requantize
+ GENERIC MAP (
+ g_complex => TRUE,
+ g_representation => "SIGNED",
+ g_lsb_w => 0,
+ g_lsb_round => TRUE,
+ g_lsb_round_clip => FALSE,
+ g_msb_clip => TRUE,
+ g_msb_clip_symmetric => FALSE,
+ g_in_dat_w => c_sdp_W_subband,
+ g_out_dat_w => c_sdp_W_crosslet
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => in_sosi_arr(I),
+ src_out => quant_sosi_arr(I)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------
+ -- dp_sync_insert_v2
+ ---------------------------------------------------------------
+ u_dp_sync_insert_v2 : ENTITY dp_lib.dp_sync_insert_v2
+ GENERIC MAP (
+ g_nof_streams => c_sdp_P_pfb,
+ g_nof_blk_per_sync => 200000,
+ g_nof_blk_per_sync_min => 19530
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_sync_insert_v2_mosi,
+ reg_miso => reg_dp_sync_insert_v2_miso,
+
+ in_sosi_arr => quant_sosi_arr,
+ out_sosi_arr => xin_sosi_arr
+ );
+
+ ---------------------------------------------------------------
+ -- Crosslet Subband Select
+ ---------------------------------------------------------------
+ u_crosslets_subband_select : ENTITY work.sdp_crosslets_subband_select
+ GENERIC MAP (
+ g_N_crosslets => c_sdp_N_crosslets
+ )
+ PORT MAP(
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => xin_sosi_arr,
+ out_sosi => xsel_sosi,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_crosslets_info_mosi => reg_crosslets_info_mosi,
+ reg_crosslets_info_miso => reg_crosslets_info_miso,
+
+ reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
+ reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
+
+ out_crosslets_info => out_crosslets_info
+ );
+
+ ---------------------------------------------------------------
+ -- Repack 32b to 64b
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- ring_mux
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- Repack 64b to 32b
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- dp_demux
+ ---------------------------------------------------------------
+ -- Not implemented yet
+
+ ---------------------------------------------------------------
+ -- dp_bsn_aligner_v2 Not implemented yet, using st_xsq_dp_to_mm as a tempory replacement
+ ---------------------------------------------------------------
+ gen_dp_to_mm : FOR I IN 0 TO g_P_sq-1 GENERATE
+ u_st_xsq_dp_to_mm : ENTITY st_lib.st_xsq_dp_to_mm
+ GENERIC MAP(
+ g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_dsp_data_w => c_sdp_W_crosslet
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ in_sosi => xsel_sosi,
+ out_sosi_info => crosslets_sosi_arr(I),
+
+ mm_mosi => crosslets_mosi_arr(I),
+ mm_miso => crosslets_miso_arr(I)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------
+ -- Crosslets Statistics (XST)
+ ---------------------------------------------------------------
+ u_crosslets_stats : ENTITY st_lib.st_xst
+ GENERIC MAP(
+ g_nof_streams => g_P_sq,
+ g_nof_crosslets => c_sdp_N_crosslets,
+ g_nof_signal_inputs => c_sdp_S_pn,
+ g_in_data_w => c_sdp_W_crosslet,
+ g_stat_data_w => c_longword_w,
+ g_stat_data_sz => c_longword_sz/c_word_sz
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_sosi => crosslets_sosi_arr(0),
+ mm_mosi_arr => crosslets_mosi_arr,
+ mm_miso_arr => crosslets_miso_arr,
+
+ ram_st_xsq_mosi => ram_st_xsq_mosi, --master_mem_mux_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso --master_mem_mux_miso
+ );
+
+-- ---------------------------------------------------------------
+-- -- MM master multiplexer
+-- ---------------------------------------------------------------
+-- -- Connect 2 mm_masters to the common_mem_mux output
+-- master_mosi_arr(0) <= ram_st_bst_mosi; -- MM access via QSYS MM bus
+-- ram_st_bst_miso <= master_miso_arr(0);
+-- master_mosi_arr(1) <= ram_st_offload_mosi; -- MM access by SST offload
+-- ram_st_offload_miso <= master_miso_arr(1);
+--
+-- u_mem_master_mux : ENTITY mm_lib.mm_master_mux
+-- GENERIC MAP (
+-- g_nof_masters => c_nof_masters,
+-- g_rd_latency_min => 1 -- read latency of statistics RAM is 1
+-- )
+-- PORT MAP (
+-- mm_clk => mm_clk,
+--
+-- master_mosi_arr => master_mosi_arr,
+-- master_miso_arr => master_miso_arr,
+-- mux_mosi => master_mem_mux_mosi,
+-- mux_miso => master_mem_mux_miso
+-- );
+--
+-- ---------------------------------------------------------------
+-- -- XST UDP offload
+-- ---------------------------------------------------------------
+-- u_sdp_bst_udp_offload: ENTITY work.sdp_statistics_offload
+-- GENERIC MAP (
+-- g_statistics_type => "XST",
+-- g_offload_time => g_offload_time,
+-- g_beamset_id => g_beamset_id
+-- )
+-- PORT MAP (
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+--
+-- dp_clk => dp_clk,
+-- dp_rst => dp_rst,
+--
+-- master_mosi => ram_st_offload_mosi,
+-- master_miso => ram_st_offload_miso,
+--
+-- reg_enable_mosi => reg_stat_enable_mosi,
+-- reg_enable_miso => reg_stat_enable_miso,
+--
+-- reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
+-- reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+--
+-- sdp_info => sdp_info,
+-- gn_index => TO_UINT(gn_id),
+--
+-- in_sosi => bf_sum_sosi,
+-- out_sosi => bst_udp_sosi,
+-- out_siso => bst_udp_siso,
+--
+-- eth_src_mac => stat_eth_src_mac,
+-- udp_src_port => stat_udp_src_port,
+-- ip_src_addr => stat_ip_src_addr
+-- );
+
+
+END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index a33fdb59910caf81e2b261cb293cb73906a3e8e6..cea8db61daf21b5f74863ceeddee8085124c7e26 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -51,7 +51,7 @@ ENTITY node_sdp_filterbank IS
g_sim : BOOLEAN := FALSE;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_scope_selected_subband : NATURAL := 0;
- g_offload_time : NATURAL := 0
+ g_offload_time : NATURAL := c_sdp_offload_time
);
PORT (
dp_clk : IN STD_LOGIC;
@@ -106,8 +106,8 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL ram_st_offload_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_offload_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL master_mem_mux_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL master_mem_mux_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL master_mosi_arr : t_mem_mosi_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_mosi_rst);
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index c8eefd48bd2723d3051e9ba45e48ce576924b872..00b4b5ed89099bea08523565cf334bf162088f70 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -77,6 +77,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_pol : NATURAL := 2;
CONSTANT c_sdp_N_sub : NATURAL := 512;
CONSTANT c_sdp_N_taps : NATURAL := 16;
+ CONSTANT c_sdp_P_sq : NATURAL := 9;
CONSTANT c_sdp_Q_fft : NATURAL := 2;
CONSTANT c_sdp_S_pn : NATURAL := 12;
CONSTANT c_sdp_S_rcu : NATURAL := 3;
@@ -91,8 +92,10 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
CONSTANT c_sdp_W_bf_magnitude : NATURAL := 1;
CONSTANT c_sdp_W_bf_weight : NATURAL := 16;
+ CONSTANT c_sdp_W_crosslet : NATURAL := 16;
CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
CONSTANT c_sdp_W_gn_id : NATURAL := 5;
+ CONSTANT c_sdp_W_statistic : NATURAL := 64;
CONSTANT c_sdp_W_sub_magnitude : NATURAL := 2;
CONSTANT c_sdp_W_sub_weight : NATURAL := 16;
CONSTANT c_sdp_W_subband : NATURAL := 18;
@@ -110,6 +113,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_marker_bst : NATURAL := 66; -- = 0x42 = 'B'
CONSTANT c_sdp_marker_xst : NATURAL := 88; -- = 0x58 = 'X'
+ CONSTANT c_sdp_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
+
+
-- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1,
-- therefore these parameters are not explicitly used in calculation of derived constants
-- LTS 2020_11_23:
@@ -189,12 +195,14 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_cep_nof_blocks_per_packet : NATURAL := 4;
CONSTANT c_sdp_cep_nof_beamlets_per_block : NATURAL := c_sdp_N_pol * c_sdp_S_sub_bf;
CONSTANT c_sdp_cep_nof_hdr_fields : NATURAL := 3+12+4+18+1; -- 592b; 9.25 64b words
- CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"110000000010000110"&"0";
+ CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111001"&"0111"&"1100"&"00000010"&"000110"&"0"; -- 0=data path, 1=MM controlled TODO
+--CONSTANT c_sdp_cep_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := "100"&"000000010001"&"0100"&"0100"&"00000000"&"101000"&"0"; -- 0=data path, 1=MM controlled TODO
CONSTANT c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"00074306C700") ), -- 00074306C700=DOP36-eth0
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
@@ -207,14 +215,17 @@ PACKAGE sdp_pkg is
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"C0A80001") ), -- C0A80001=DOP36-eth0 '192.168.0.1'
+
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), "RW", 16, field_default(5000) ),
( field_name_pad("udp_total_length" ), "RW", 16, field_default(7848) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
( field_name_pad("sdp_marker" ), "RW", 8, field_default(x"62") ),
( field_name_pad("sdp_version_id" ), "RW", 8, field_default(5) ),
( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
( field_name_pad("sdp_station_id" ), "RW", 16, field_default(0) ),
+
( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
@@ -223,12 +234,14 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_source_info_repositioning_flag" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
+
( field_name_pad("sdp_reserved" ), "RW", 40, field_default(0) ),
( field_name_pad("sdp_beamlet_scale" ), "RW", 16, field_default(2**15) ),
( field_name_pad("sdp_beamlet_id" ), "RW", 16, field_default(0) ),
( field_name_pad("sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
( field_name_pad("sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
( field_name_pad("sdp_block_period" ), "RW", 16, field_default(5120) ),
+
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
@@ -252,13 +265,15 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_xst_udp_src_port_15_8 : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"D2"; -- TBC
CONSTANT c_sdp_stat_nof_hdr_fields : NATURAL := 1+3+12+4+20+1; -- 592b; 18.5 32b words
- CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111111111101"&"0111"&"01000000000000000100"&"0"; -- 0=data path, 1=MM controlled TODO
+ CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "1"&"101"&"111111111001"&"0111"&"0100"&"000000000"&"0000100"&"0"; -- 0=data path, 1=MM controlled TODO
+--CONSTANT c_sdp_stat_hdr_field_sel : STD_LOGIC_VECTOR(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := "0"&"100"&"000000010001"&"0100"&"0100"&"000000010"&"1000000"&"0"; -- 0=data path, 1=MM controlled TODO
CONSTANT c_sdp_stat_hdr_field_arr : t_common_field_arr(c_sdp_stat_nof_hdr_fields-1 DOWNTO 0) := (
( field_name_pad("word_align" ), "RW", 16, field_default(0) ),
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"001B217176B9") ), -- 001B217176B9 = DOP36-enp2s0
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
@@ -271,14 +286,17 @@ PACKAGE sdp_pkg is
( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ),
( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A6300FE") ), -- 0A6300FE = DOP36-enp2s0 '10.99.0.254'
+
( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
( field_name_pad("udp_dst_port" ), "RW", 16, field_default(5001) ),
( field_name_pad("udp_total_length" ), "RW", 16, field_default(4136) ),
( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+
( field_name_pad("sdp_marker" ), "RW", 8, field_default(0) ),
( field_name_pad("sdp_version_id" ), "RW", 8, field_default(5) ),
( field_name_pad("sdp_observation_id" ), "RW", 32, field_default(0) ),
( field_name_pad("sdp_station_id" ), "RW", 16, field_default(0) ),
+
( field_name_pad("sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
( field_name_pad("sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
@@ -288,6 +306,7 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
+
( field_name_pad("sdp_reserved" ), "RW", 8, field_default(0) ),
( field_name_pad("sdp_integration_interval" ), "RW", 24, field_default(0) ),
( field_name_pad("sdp_data_id" ), "RW", 32, field_default(0) ),
@@ -295,6 +314,7 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_nof_bytes_per_statistics" ), "RW", 8, field_default(8) ),
( field_name_pad("sdp_nof_statistics_per_packet" ), "RW", 16, field_default(0) ),
( field_name_pad("sdp_block_period" ), "RW", 16, field_default(0) ),
+
( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) )
);
CONSTANT c_sdp_reg_stat_hdr_dat_addr_w : NATURAL := ceil_log2(field_nof_words(c_sdp_stat_hdr_field_arr, c_word_w));
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 82c7be74fc12eae88d8e61b88c1843ead9bf6b09..8a5953606a796ee0ac203c5265b200167b5ace99 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -44,7 +44,7 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_statistics_offload IS
GENERIC (
g_statistics_type : STRING := "SST";
- g_offload_time : NATURAL := 13000; -- from wave window 62855nS / 5nS = 12571 cycles.
+ g_offload_time : NATURAL := c_sdp_offload_time;
g_beamset_id : NATURAL := 0
);
PORT (
@@ -86,14 +86,20 @@ END sdp_statistics_offload;
ARCHITECTURE str OF sdp_statistics_offload IS
- CONSTANT c_step_size : NATURAL := 4;
- CONSTANT c_nof_data : NATURAL := 512;
- CONSTANT c_block_size : NATURAL := c_nof_data * c_step_size;
-
CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_data_size : NATURAL := 2;
CONSTANT c_nof_data_per_step : NATURAL := 2;
+
+ CONSTANT c_step_size : NATURAL := sel_a_b(g_statistics_type="BST", c_data_size,
+ sel_a_b(g_statistics_type="XST", c_data_size,
+ c_data_size * c_nof_data_per_step)); -- SST
+
+ CONSTANT c_nof_data : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
+ sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn * c_nof_complex),
+ c_sdp_N_sub)); -- SST
+ CONSTANT c_block_size : NATURAL := c_nof_data * c_step_size;
+
CONSTANT c_nof_packets : NATURAL := sel_a_b(g_statistics_type="BST", 1,
sel_a_b(g_statistics_type="XST", c_sdp_S_pn,
c_sdp_S_pn)); -- SST
@@ -106,7 +112,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
sel_a_b(g_statistics_type="XST", c_sdp_S_pn,
1)); -- SST
- CONSTANT c_nof_statistics_per_packet : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_S_sub_bf,
+ CONSTANT c_nof_statistics_per_packet : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_N_pol * c_sdp_S_sub_bf,
sel_a_b(g_statistics_type="XST", (c_sdp_S_pn * c_sdp_S_pn * c_nof_complex),
c_sdp_N_sub)); -- SST
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
index fef79242898ecf145b7b6af8543ec4736bfb309e..3277c6bf3d69fddb637e0113f8a95ee6e90d44a7 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "128";
+ value = "192";
type = "String";
}
}
@@ -62,7 +62,7 @@
{
datum baseAddress
{
- value = "40960";
+ value = "53248";
type = "String";
}
}
@@ -78,7 +78,7 @@
{
datum baseAddress
{
- value = "12512";
+ value = "12384";
type = "String";
}
}
@@ -118,7 +118,7 @@
{
datum baseAddress
{
- value = "36864";
+ value = "49152";
type = "String";
}
}
@@ -176,7 +176,7 @@
{
datum baseAddress
{
- value = "12504";
+ value = "12376";
type = "String";
}
}
@@ -229,7 +229,7 @@
{
datum baseAddress
{
- value = "512";
+ value = "45056";
type = "String";
}
}
@@ -249,6 +249,38 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_rx
+ {
+ datum _sortIndex
+ {
+ value = "31";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx.mem
+ {
+ datum baseAddress
+ {
+ value = "40960";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_tx
+ {
+ datum _sortIndex
+ {
+ value = "32";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "36864";
+ type = "String";
+ }
+ }
element reg_diag_bg_ring
{
datum _sortIndex
@@ -261,7 +293,39 @@
{
datum baseAddress
{
- value = "12320";
+ value = "928";
+ type = "String";
+ }
+ }
+ element reg_dp_xonoff_bg
+ {
+ datum _sortIndex
+ {
+ value = "29";
+ type = "int";
+ }
+ }
+ element reg_dp_xonoff_bg.mem
+ {
+ datum baseAddress
+ {
+ value = "896";
+ type = "String";
+ }
+ }
+ element reg_dp_xonoff_from_lane
+ {
+ datum _sortIndex
+ {
+ value = "30";
+ type = "int";
+ }
+ }
+ element reg_dp_xonoff_from_lane.mem
+ {
+ datum baseAddress
+ {
+ value = "864";
type = "String";
}
}
@@ -282,7 +346,7 @@
{
datum baseAddress
{
- value = "12496";
+ value = "12368";
type = "String";
}
}
@@ -303,7 +367,7 @@
{
datum baseAddress
{
- value = "12488";
+ value = "12360";
type = "String";
}
}
@@ -324,7 +388,7 @@
{
datum baseAddress
{
- value = "12416";
+ value = "992";
type = "String";
}
}
@@ -340,7 +404,7 @@
{
datum baseAddress
{
- value = "12384";
+ value = "960";
type = "String";
}
}
@@ -361,7 +425,7 @@
{
datum baseAddress
{
- value = "192";
+ value = "768";
type = "String";
}
}
@@ -382,7 +446,7 @@
{
datum baseAddress
{
- value = "12480";
+ value = "12352";
type = "String";
}
}
@@ -424,7 +488,23 @@
{
datum baseAddress
{
- value = "12448";
+ value = "12320";
+ type = "String";
+ }
+ }
+ element reg_sdp_info
+ {
+ datum _sortIndex
+ {
+ value = "33";
+ type = "int";
+ }
+ }
+ element reg_sdp_info.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
type = "String";
}
}
@@ -472,7 +552,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "512";
type = "String";
}
}
@@ -540,7 +620,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "832";
type = "String";
}
}
@@ -868,6 +948,76 @@
internal="ram_scrap.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_address"
+ internal="reg_bsn_monitor_v2_rx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_clk"
+ internal="reg_bsn_monitor_v2_rx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_read"
+ internal="reg_bsn_monitor_v2_rx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_readdata"
+ internal="reg_bsn_monitor_v2_rx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_reset"
+ internal="reg_bsn_monitor_v2_rx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_write"
+ internal="reg_bsn_monitor_v2_rx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_writedata"
+ internal="reg_bsn_monitor_v2_rx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_address"
+ internal="reg_bsn_monitor_v2_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_clk"
+ internal="reg_bsn_monitor_v2_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_read"
+ internal="reg_bsn_monitor_v2_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_readdata"
+ internal="reg_bsn_monitor_v2_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_reset"
+ internal="reg_bsn_monitor_v2_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_write"
+ internal="reg_bsn_monitor_v2_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_tx_writedata"
+ internal="reg_bsn_monitor_v2_tx.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_diag_bg_ring_address"
internal="reg_diag_bg_ring.address"
@@ -903,6 +1053,76 @@
internal="reg_diag_bg_ring.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_address"
+ internal="reg_dp_xonoff_bg.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_clk"
+ internal="reg_dp_xonoff_bg.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_read"
+ internal="reg_dp_xonoff_bg.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_readdata"
+ internal="reg_dp_xonoff_bg.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_reset"
+ internal="reg_dp_xonoff_bg.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_write"
+ internal="reg_dp_xonoff_bg.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_bg_writedata"
+ internal="reg_dp_xonoff_bg.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_address"
+ internal="reg_dp_xonoff_from_lane.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_clk"
+ internal="reg_dp_xonoff_from_lane.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_read"
+ internal="reg_dp_xonoff_from_lane.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_readdata"
+ internal="reg_dp_xonoff_from_lane.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_reset"
+ internal="reg_dp_xonoff_from_lane.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_write"
+ internal="reg_dp_xonoff_from_lane.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_xonoff_from_lane_writedata"
+ internal="reg_dp_xonoff_from_lane.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dpmm_ctrl_address"
internal="reg_dpmm_ctrl.address"
@@ -1175,6 +1395,41 @@
internal="reg_remu.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_sdp_info_address"
+ internal="reg_sdp_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_clk"
+ internal="reg_sdp_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_read"
+ internal="reg_sdp_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_readdata"
+ internal="reg_sdp_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_reset"
+ internal="reg_sdp_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_write"
+ internal="reg_sdp_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_sdp_info_writedata"
+ internal="reg_sdp_info.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_ta2_unb2b_mm_io_address"
internal="reg_ta2_unb2b_mm_io.address"
@@ -5899,7 +6154,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg_ring.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /><slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /><slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /><slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /><slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /><slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /><slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /><slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -5937,7 +6192,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -6867,7 +7122,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x0000a020</value>
+ <value>0x0000d020</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -15902,7 +16157,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -15971,7 +16226,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16200,7 +16455,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16378,11 +16633,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16482,7 +16737,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -16521,17 +16776,21 @@
</ports>
<assignments>
<assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>false</value>
+ <value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
- <value>false</value>
+ <value>0</value>
</entry>
</assignmentValueMap>
</assignments>
@@ -16547,7 +16806,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -16571,6 +16830,7 @@
</entry>
<entry>
<key>bridgedAddressOffset</key>
+ <value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
@@ -16775,7 +17035,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18100,7 +18360,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_bg_ring"
+ name="reg_bsn_monitor_v2_rx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18179,7 +18439,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18248,7 +18508,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -18477,7 +18737,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18655,11 +18915,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18759,7 +19019,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -18828,7 +19088,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19057,7 +19317,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19211,37 +19471,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_diag_bg_ring</hdlLibraryName>
+ <hdlLibraryName>board_reg_bsn_monitor_v2_rx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_diag_bg_ring</fileSetName>
- <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_diag_bg_ring</fileSetName>
- <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_diag_bg_ring</fileSetName>
- <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_rx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_rx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_diag_bg_ring.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_bsn_monitor_v2_rx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_bsn_monitor_v2_tx"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19249,17 +19509,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -19268,27 +19528,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -19301,13 +19562,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -19321,7 +19580,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19390,7 +19649,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19547,12 +19806,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -19579,17 +19838,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -19611,17 +19870,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -19643,14 +19902,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -19662,31 +19921,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -19696,22 +19954,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -19738,14 +19998,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -19796,11 +20056,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19829,17 +20089,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -19848,27 +20108,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -19881,13 +20142,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -19901,7 +20160,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19970,7 +20229,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20126,70 +20385,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -20223,75 +20418,12 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -20318,15 +20450,143 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>32</width>
+ <width>10</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20352,37 +20612,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>board_reg_bsn_monitor_v2_tx</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_bsn_monitor_v2_tx</fileSetName>
+ <fileSetFixedName>board_reg_bsn_monitor_v2_tx</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_bsn_monitor_v2_tx.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_diag_bg_ring"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20390,17 +20650,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -20409,27 +20669,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -20442,13 +20703,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -20462,7 +20721,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20531,7 +20790,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20688,12 +20947,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -20720,17 +20979,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -20752,17 +21011,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -20784,14 +21043,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -20803,31 +21062,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -20837,22 +21095,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -20879,14 +21139,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -20937,11 +21197,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20970,17 +21230,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -20989,27 +21249,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -21022,13 +21283,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -21042,7 +21301,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21111,7 +21370,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21268,12 +21527,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -21300,17 +21559,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -21332,17 +21591,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -21364,14 +21623,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -21383,31 +21642,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -21417,22 +21675,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -21459,14 +21719,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -21493,37 +21753,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>board_reg_diag_bg_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_dpmm_data</fileSetName>
- <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>board_reg_diag_bg_ring</fileSetName>
+ <fileSetFixedName>board_reg_diag_bg_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_diag_bg_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dp_xonoff_bg"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21531,17 +21791,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -21550,27 +21810,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -21583,13 +21844,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -21829,12 +22088,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -21861,17 +22120,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -21893,17 +22152,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -21924,69 +22183,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -22051,6 +22247,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -22111,17 +22371,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -22130,27 +22390,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -22163,13 +22424,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -22409,12 +22668,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -22441,17 +22700,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -22473,17 +22732,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -22505,14 +22764,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -22524,31 +22783,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -22558,22 +22816,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -22600,14 +22860,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -22634,37 +22894,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>board_reg_dp_xonoff_bg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_epcs</fileSetName>
- <fileSetFixedName>board_reg_epcs</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_bg</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_bg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dp_xonoff_bg.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dp_xonoff_from_lane"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22672,17 +22932,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -22691,27 +22951,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -22724,13 +22985,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -22970,12 +23229,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -23002,44 +23261,12 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -23066,17 +23293,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -23085,28 +23312,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -23119,22 +23345,56 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -23161,14 +23421,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -23252,17 +23512,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -23271,27 +23531,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -23304,13 +23565,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -23550,12 +23809,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -23582,17 +23841,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -23614,17 +23873,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -23646,14 +23905,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -23665,31 +23924,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -23699,22 +23957,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -23741,14 +24001,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -23775,37 +24035,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>board_reg_dp_xonoff_from_lane</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>board_reg_dp_xonoff_from_lane</fileSetName>
+ <fileSetFixedName>board_reg_dp_xonoff_from_lane</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dp_xonoff_from_lane.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23821,7 +24081,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23885,7 +24145,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23954,7 +24214,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24360,11 +24620,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24401,7 +24661,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24465,7 +24725,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24534,7 +24794,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24916,37 +25176,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>board_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26057,37 +26317,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>board_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>board_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>board_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26103,7 +26363,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26167,7 +26427,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26236,7 +26496,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26642,11 +26902,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26683,7 +26943,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26747,7 +27007,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26816,7 +27076,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27198,37 +27458,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>board_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_mmdp_data</fileSetName>
- <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>board_reg_epcs</fileSetName>
+ <fileSetFixedName>board_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28178,12 +28438,5684 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_reg_fpga_temp_sens</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_fpga_voltage_sens"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_reg_fpga_voltage_sens</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>board_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_mmdp_ctrl"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_reg_mmdp_ctrl</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_mmdp_data"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_reg_mmdp_data</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>board_reg_mmdp_data</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_reg_mmdp_data.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_remu"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>board_reg_remu</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>board_reg_remu</fileSetName>
+ <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_sdp_info"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -28210,17 +34142,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -28229,28 +34161,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -28263,22 +34194,56 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -28305,14 +34270,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -28339,30 +34304,30 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>board_reg_remu</hdlLibraryName>
+ <hdlLibraryName>board_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_sdp_info</fileSetName>
+ <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_sdp_info</fileSetName>
+ <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>board_reg_remu</fileSetName>
- <fileSetFixedName>board_reg_remu</fileSetFixedName>
+ <fileSetName>board_reg_sdp_info</fileSetName>
+ <fileSetFixedName>board_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/board/board_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/board/board_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -35463,7 +41428,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30e0" />
+ <parameter name="baseAddress" value="0x3060" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35483,7 +41448,7 @@
start="cpu_0.data_master"
end="kernel_clk_gen.ctrl">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x9000" />
+ <parameter name="baseAddress" value="0xc000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35523,7 +41488,7 @@
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xa000" />
+ <parameter name="baseAddress" value="0xd000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35543,7 +41508,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35603,7 +41568,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30d8" />
+ <parameter name="baseAddress" value="0x3058" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35643,7 +41608,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30a0" />
+ <parameter name="baseAddress" value="0x3020" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35663,7 +41628,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x03e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35683,7 +41648,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30d0" />
+ <parameter name="baseAddress" value="0x3050" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35703,7 +41668,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30c8" />
+ <parameter name="baseAddress" value="0x3048" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35723,7 +41688,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30c0" />
+ <parameter name="baseAddress" value="0x3040" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35763,7 +41728,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3060" />
+ <parameter name="baseAddress" value="0x03c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35803,7 +41768,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00c0" />
+ <parameter name="baseAddress" value="0x0300" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35843,7 +41808,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_ring.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x03a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35863,7 +41828,7 @@
start="cpu_0.data_master"
end="ram_diag_bg_ring.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0xb000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -35897,6 +41862,106 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.2"
+ start="cpu_0.data_master"
+ end="reg_dp_xonoff_bg.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0380" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.2"
+ start="cpu_0.data_master"
+ end="reg_dp_xonoff_from_lane.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0360" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.2"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_rx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0xa000" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.2"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x9000" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.2"
+ start="cpu_0.data_master"
+ end="reg_sdp_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.2"
@@ -35923,7 +41988,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x00c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36003,7 +42068,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0340" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36023,7 +42088,7 @@
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0xa000" />
+ <parameter name="baseAddress" value="0xd000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -36152,6 +42217,31 @@
start="clk_0.clk"
end="ram_diag_bg_ring.system" />
<connection kind="clock" version="19.2" start="clk_0.clk" end="ram_scrap.system" />
+ <connection
+ kind="clock"
+ version="19.2"
+ start="clk_0.clk"
+ end="reg_dp_xonoff_bg.system" />
+ <connection
+ kind="clock"
+ version="19.2"
+ start="clk_0.clk"
+ end="reg_dp_xonoff_from_lane.system" />
+ <connection
+ kind="clock"
+ version="19.2"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_rx.system" />
+ <connection
+ kind="clock"
+ version="19.2"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_tx.system" />
+ <connection
+ kind="clock"
+ version="19.2"
+ start="clk_0.clk"
+ end="reg_sdp_info.system" />
<connection
kind="clock"
version="19.2"
@@ -36310,6 +42400,31 @@
version="19.2"
start="clk_0.clk_reset"
end="ram_scrap.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="clk_0.clk_reset"
+ end="reg_dp_xonoff_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="clk_0.clk_reset"
+ end="reg_dp_xonoff_from_lane.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="clk_0.clk_reset"
+ end="reg_sdp_info.system_reset" />
<connection
kind="reset"
version="19.2"
@@ -36440,6 +42555,31 @@
version="19.2"
start="cpu_0.debug_reset_request"
end="ram_scrap.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_xonoff_bg.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="cpu_0.debug_reset_request"
+ end="reg_dp_xonoff_from_lane.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="cpu_0.debug_reset_request"
+ end="reg_bsn_monitor_v2_rx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="cpu_0.debug_reset_request"
+ end="reg_bsn_monitor_v2_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="19.2"
+ start="cpu_0.debug_reset_request"
+ end="reg_sdp_info.system_reset" />
<connection
kind="reset"
version="19.2"
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
index 5a50c89b67d768da824afce31a787ecbf9153907..51696a11d56185b4dae53e666fa3bb4ca7fdfe4c 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/board_spec.xml
@@ -27,36 +27,69 @@
<channels>
<!-- qsfp interfaces for connecting multiple UniBoards -->
- <interface name="board" port="kernel_stream_src_10GbE_qsfp_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_0"/>
- <interface name="board" port="kernel_stream_snk_10GbE_qsfp_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_0"/>
- <interface name="board" port="kernel_stream_src_10GbE_qsfp_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_1"/>
- <interface name="board" port="kernel_stream_snk_10GbE_qsfp_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_1"/>
- <interface name="board" port="kernel_stream_src_10GbE_qsfp_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_2"/>
- <interface name="board" port="kernel_stream_snk_10GbE_qsfp_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_2"/>
- <interface name="board" port="kernel_stream_src_10GbE_qsfp_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_qsfp_3"/>
- <interface name="board" port="kernel_stream_snk_10GbE_qsfp_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_qsfp_3"/>
+ <interface name="board" port="kernel_stream_src_10GbE_qsfp_0" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_0"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_qsfp_0" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_0"/>
+ <interface name="board" port="kernel_stream_src_10GbE_qsfp_1" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_1"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_qsfp_1" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_1"/>
+ <interface name="board" port="kernel_stream_src_10GbE_qsfp_2" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_2"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_qsfp_2" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_2"/>
+ <interface name="board" port="kernel_stream_src_10GbE_qsfp_3" type="streamsource" width="104" chan_id="kernel_input_10GbE_qsfp_3"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_qsfp_3" type="streamsink" width="104" chan_id="kernel_output_10GbE_qsfp_3"/>
<!-- Ring interface, ring_0, 2, 4, 6 transport in positive direction (receive from left transmit to right). ring_1, 3, 5, 7 transport in negative direction -->
- <interface name="board" port="kernel_stream_src_10GbE_ring_0" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_0"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_0" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_0"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_1" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_1"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_1" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_1"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_2" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_2"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_2" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_2"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_3" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_3"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_3" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_3"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_4" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_4"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_4" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_4"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_5" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_5"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_5" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_5"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_6" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_6"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_6" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_6"/>
- <interface name="board" port="kernel_stream_src_10GbE_ring_7" type="streamsource" width="72" chan_id="kernel_input_10GbE_ring_7"/>
- <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="72" chan_id="kernel_output_10GbE_ring_7"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_0" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_0" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_0"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_1" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_1"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_1" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_1"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_2" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_2"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_2" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_2"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_3" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_3"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_3" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_3"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_4" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_4"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_4" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_4"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_5" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_5"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_5" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_5"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_6" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_6"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_6" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_6"/>
+ <interface name="board" port="kernel_stream_src_10GbE_ring_7" type="streamsource" width="104" chan_id="kernel_input_10GbE_ring_7"/>
+ <interface name="board" port="kernel_stream_snk_10GbE_ring_7" type="streamsink" width="104" chan_id="kernel_output_10GbE_ring_7"/>
<!-- IO channel from/to design -->
- <interface name="board" port="kernel_stream_src_lane" type="streamsource" width="72" chan_id="kernel_input_lane"/>
- <interface name="board" port="kernel_stream_snk_lane" type="streamsink" width="72" chan_id="kernel_output_lane"/>
+ <interface name="board" port="kernel_stream_src_lane_0" type="streamsource" width="168" chan_id="kernel_input_lane_0"/>
+ <interface name="board" port="kernel_stream_snk_lane_0" type="streamsink" width="168" chan_id="kernel_output_lane_0"/>
+ <interface name="board" port="kernel_stream_src_lane_1" type="streamsource" width="168" chan_id="kernel_input_lane_1"/>
+ <interface name="board" port="kernel_stream_snk_lane_1" type="streamsink" width="168" chan_id="kernel_output_lane_1"/>
+ <interface name="board" port="kernel_stream_src_lane_2" type="streamsource" width="168" chan_id="kernel_input_lane_2"/>
+ <interface name="board" port="kernel_stream_snk_lane_2" type="streamsink" width="168" chan_id="kernel_output_lane_2"/>
+ <interface name="board" port="kernel_stream_src_lane_3" type="streamsource" width="168" chan_id="kernel_input_lane_3"/>
+ <interface name="board" port="kernel_stream_snk_lane_3" type="streamsink" width="168" chan_id="kernel_output_lane_3"/>
+ <interface name="board" port="kernel_stream_src_lane_4" type="streamsource" width="168" chan_id="kernel_input_lane_4"/>
+ <interface name="board" port="kernel_stream_snk_lane_4" type="streamsink" width="168" chan_id="kernel_output_lane_4"/>
+ <interface name="board" port="kernel_stream_src_lane_5" type="streamsource" width="168" chan_id="kernel_input_lane_5"/>
+ <interface name="board" port="kernel_stream_snk_lane_5" type="streamsink" width="168" chan_id="kernel_output_lane_5"/>
+ <interface name="board" port="kernel_stream_src_lane_6" type="streamsource" width="168" chan_id="kernel_input_lane_6"/>
+ <interface name="board" port="kernel_stream_snk_lane_6" type="streamsink" width="168" chan_id="kernel_output_lane_6"/>
+ <interface name="board" port="kernel_stream_src_lane_7" type="streamsource" width="168" chan_id="kernel_input_lane_7"/>
+ <interface name="board" port="kernel_stream_snk_lane_7" type="streamsink" width="168" chan_id="kernel_output_lane_7"/>
+
+ <interface name="board" port="kernel_stream_snk_rx_monitor_0" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_0"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_0" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_0"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_1" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_1"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_1" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_1"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_2" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_2"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_2" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_2"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_3" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_3"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_3" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_3"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_4" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_4"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_4" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_4"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_5" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_5"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_5" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_5"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_6" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_6"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_6" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_6"/>
+ <interface name="board" port="kernel_stream_snk_rx_monitor_7" type="streamsink" width="168" chan_id="kernel_output_rx_monitor_7"/>
+ <interface name="board" port="kernel_stream_snk_tx_monitor_7" type="streamsink" width="168" chan_id="kernel_output_tx_monitor_7"/>
+
+ <interface name="board" port="kernel_stream_src_bs" type="streamsource" width="104" chan_id="kernel_input_bs_sosi"/>
<interface name="board" port="kernel_stream_src_mm_io" type="streamsource" width="72" chan_id="kernel_input_mm"/>
<interface name="board" port="kernel_stream_snk_mm_io" type="streamsink" width="32" chan_id="kernel_output_mm"/>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
index cc0d5c1e26ce10fe2169e6a44d742783219d3365..85ec060c674073c56e4acdbb16ff787e0e575e35 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/flat.qsf
@@ -357,208 +357,208 @@ set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0
set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
-#### LANE 2, 3
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
-#
-#
-#### LANE 4, 5
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
-#
-#
-#### LANE 6,7
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+### LANE 2, 3
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+
+### LANE 4, 5
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+
+### LANE 6,7
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
@@ -594,4 +594,3 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
-
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
index 603eece27e12f88980dbe46d2d7991b693d7c911..7affbbc077a8e51ea5819184ea9ea1862d6b1ea1 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
@@ -1,17 +1,21 @@
hdl_lib_name = lofar2_unb2b_ring_bsp
hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
-hdl_lib_uses_synth = common technology dp unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io
+hdl_lib_uses_synth = common technology tech_pll dp mm unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io lofar2_sdp
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip =
+ ip_arria10_e1sg_phy_10gbase_r_12
+ ip_arria10_e1sg_transceiver_reset_controller_12
synth_files =
+ ring_pkg.vhd
top_components_pkg.vhd
ip/pr_region.v
ip/freeze_wrapper.v
top.vhd
test_bench_files =
+ tb_lofar2_unb2b_ring_bsp.vhd
regression_test_vhdl =
@@ -24,10 +28,10 @@ quartus_copy_files =
./ .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
index 0fc5b4c5627003328302555a95239e7217c4e60e..077cedc99a7b53c03888a67784cb59e3cf81d80a 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_cpu_0.ip
@@ -2157,7 +2157,7 @@
<ipxact:parameter parameterId="breakAbsoluteAddr" type="int">
<ipxact:name>breakAbsoluteAddr</ipxact:name>
<ipxact:displayName>Break vector</ipxact:displayName>
- <ipxact:value>40992</ipxact:value>
+ <ipxact:value>53280</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="mmu_TLBMissExcAbsAddr" type="int">
<ipxact:name>mmu_TLBMissExcAbsAddr</ipxact:name>
@@ -2292,7 +2292,7 @@
<ipxact:parameter parameterId="instSlaveMapParam" type="string">
<ipxact:name>instSlaveMapParam</ipxact:name>
<ipxact:displayName>instSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="faSlaveMapParam" type="string">
<ipxact:name>faSlaveMapParam</ipxact:name>
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_bg_data.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_bg_ctrl.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /><slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /><slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /><slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /><slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /><slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /><slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /><slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /><slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /><slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /><slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /><slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -2428,7 +2428,7 @@
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.BREAK_ADDR" type="string">
<ipxact:name>embeddedsw.CMacro.BREAK_ADDR</ipxact:name>
- <ipxact:value>0x0000a020</ipxact:value>
+ <ipxact:value>0x0000d020</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1" type="string">
<ipxact:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='ram_bg_data.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_bg_ctrl.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3040' end='0x3060' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x30C0' end='0x30C8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x30C8' end='0x30D0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x30D0' end='0x30D8' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x30D8' end='0x30E0' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x30E0' end='0x30E8' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x300' end='0x340' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x340' end='0x360' datawidth='16' /&gt;&lt;slave name='reg_dp_xonoff_from_lane.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff_bg.mem' start='0x380' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_diag_bg_ring.mem' start='0x3A0' end='0x3C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x3C0' end='0x3E0' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x3E0' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_ta2_unb2b_mm_io.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x3040' end='0x3048' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3048' end='0x3050' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3050' end='0x3058' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3058' end='0x3060' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3060' end='0x3068' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='kernel_interface.ctrl' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x8000' end='0x9000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_tx.mem' start='0x9000' end='0xA000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx.mem' start='0xA000' end='0xB000' datawidth='32' /&gt;&lt;slave name='ram_diag_bg_ring.mem' start='0xB000' end='0xC000' datawidth='32' /&gt;&lt;slave name='kernel_clk_gen.ctrl' start='0xC000' end='0xD000' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -3627,7 +3627,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xA000' end='0xA800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0xD000' end='0xD800' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
index 4574de872512e8035dc3ba1d97b12b77a781b852..5375e1c55e56bbd3ada5f8cbcc3127699a50fbbd 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_ram_diag_bg_ring.ip
@@ -139,7 +139,7 @@
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>512</ipxact:value>
+ <ipxact:value>4096</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
@@ -667,7 +667,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>6</ipxact:right>
+ <ipxact:right>9</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -773,7 +773,7 @@
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
- <ipxact:right>6</ipxact:right>
+ <ipxact:right>9</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
@@ -860,7 +860,7 @@
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>7</ipxact:value>
+ <ipxact:value>10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element board_ram_bg_data
+ element board_ram_diag_bg_ring
{
}
}
@@ -997,7 +997,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1066,7 +1066,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1295,7 +1295,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1462,11 +1462,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x200' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..95e381ec3170272af67376dcc7461b52eb9758f0
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_rx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:name>board_reg_bsn_monitor_v2_rx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>4096</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>9</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>9</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_bsn_monitor_v2_rx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element board_reg_bsn_monitor_v2_rx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>10</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>4096</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>10</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_bsn_monitor_v2_rx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_bsn_monitor_v2_rx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_bsn_monitor_v2_rx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_bsn_monitor_v2_rx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_bsn_monitor_v2_rx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_bsn_monitor_v2_rx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_bsn_monitor_v2_rx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_bsn_monitor_v2_rx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_bsn_monitor_v2_rx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_bsn_monitor_v2_rx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip
new file mode 100644
index 0000000000000000000000000000000000000000..c7454a1f327d3305f07ff65652751c90bc1e0f07
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_bsn_monitor_v2_tx.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:name>board_reg_bsn_monitor_v2_tx</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>4096</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>9</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>9</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_bsn_monitor_v2_tx</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element board_reg_bsn_monitor_v2_tx
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>10</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>4096</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>10</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_bsn_monitor_v2_tx.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_bsn_monitor_v2_tx.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_bsn_monitor_v2_tx.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_bsn_monitor_v2_tx.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_bsn_monitor_v2_tx.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_bsn_monitor_v2_tx.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_bsn_monitor_v2_tx.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_bsn_monitor_v2_tx.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_bsn_monitor_v2_tx.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_bsn_monitor_v2_tx.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
index 0abc1ad4a0529da24ba60b3460b884fddbedd5c5..213d7b23fbd8748ce74479bf3ac3cde7a9f32495 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_diag_bg_ring.ip
@@ -909,7 +909,7 @@
type = "String";
}
}
- element board_reg_bg_ctrl
+ element board_reg_diag_bg_ring
{
}
}
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip
new file mode 100644
index 0000000000000000000000000000000000000000..48759814a65e053b2e25dc0950de781a18e7613d
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_bg.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_dp_xonoff_bg</ipxact:library>
+ <ipxact:name>board_reg_dp_xonoff_bg</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_dp_xonoff_bg</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element board_reg_dp_xonoff_bg
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_dp_xonoff_bg.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_dp_xonoff_bg.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_dp_xonoff_bg.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_dp_xonoff_bg.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_dp_xonoff_bg.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_dp_xonoff_bg.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_dp_xonoff_bg.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_dp_xonoff_bg.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_dp_xonoff_bg.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_dp_xonoff_bg.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip
new file mode 100644
index 0000000000000000000000000000000000000000..a5f9d1a915e8668fba8e54498ba792b9d85689af
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_dp_xonoff_from_lane.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_dp_xonoff_from_lane</ipxact:library>
+ <ipxact:name>board_reg_dp_xonoff_from_lane</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_dp_xonoff_from_lane</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element board_reg_dp_xonoff_from_lane
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_dp_xonoff_from_lane.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_dp_xonoff_from_lane.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_dp_xonoff_from_lane.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_dp_xonoff_from_lane.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_dp_xonoff_from_lane.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_dp_xonoff_from_lane.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_dp_xonoff_from_lane.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_dp_xonoff_from_lane.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_dp_xonoff_from_lane.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_dp_xonoff_from_lane.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e2bdfbfb0e74820e19f90801a0816cb4eaa7f346
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/board/board_reg_sdp_info.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_sdp_info</ipxact:library>
+ <ipxact:name>board_reg_sdp_info</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>board_reg_sdp_info</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element board_reg_sdp_info
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="board_reg_sdp_info.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="board_reg_sdp_info.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="board_reg_sdp_info.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="board_reg_sdp_info.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="board_reg_sdp_info.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="board_reg_sdp_info.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="board_reg_sdp_info.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="board_reg_sdp_info.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="board_reg_sdp_info.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="board_reg_sdp_info.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
index 3eb75ddc144edaf2173e074718473495d0d72e63..df19828e981a30ef0dfd0c97ed0a5ceac0a40c23 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/freeze_wrapper.v
@@ -47,104 +47,213 @@ module freeze_wrapper(
input wire board_kernel_stream_snk_mm_io_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_0_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_0_data,
input wire board_kernel_stream_src_10GbE_ring_0_valid,
output wire board_kernel_stream_src_10GbE_ring_0_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_0_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_0_data,
output wire board_kernel_stream_snk_10GbE_ring_0_valid,
input wire board_kernel_stream_snk_10GbE_ring_0_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_1_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_1_data,
input wire board_kernel_stream_src_10GbE_ring_1_valid,
output wire board_kernel_stream_src_10GbE_ring_1_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_1_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_1_data,
output wire board_kernel_stream_snk_10GbE_ring_1_valid,
input wire board_kernel_stream_snk_10GbE_ring_1_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_2_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_2_data,
input wire board_kernel_stream_src_10GbE_ring_2_valid,
output wire board_kernel_stream_src_10GbE_ring_2_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_2_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_2_data,
output wire board_kernel_stream_snk_10GbE_ring_2_valid,
input wire board_kernel_stream_snk_10GbE_ring_2_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_3_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_3_data,
input wire board_kernel_stream_src_10GbE_ring_3_valid,
output wire board_kernel_stream_src_10GbE_ring_3_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_3_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_3_data,
output wire board_kernel_stream_snk_10GbE_ring_3_valid,
input wire board_kernel_stream_snk_10GbE_ring_3_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_4_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_4_data,
input wire board_kernel_stream_src_10GbE_ring_4_valid,
output wire board_kernel_stream_src_10GbE_ring_4_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_4_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_4_data,
output wire board_kernel_stream_snk_10GbE_ring_4_valid,
input wire board_kernel_stream_snk_10GbE_ring_4_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_5_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_5_data,
input wire board_kernel_stream_src_10GbE_ring_5_valid,
output wire board_kernel_stream_src_10GbE_ring_5_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_5_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_5_data,
output wire board_kernel_stream_snk_10GbE_ring_5_valid,
input wire board_kernel_stream_snk_10GbE_ring_5_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_6_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_6_data,
input wire board_kernel_stream_src_10GbE_ring_6_valid,
output wire board_kernel_stream_src_10GbE_ring_6_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_6_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_6_data,
output wire board_kernel_stream_snk_10GbE_ring_6_valid,
input wire board_kernel_stream_snk_10GbE_ring_6_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_ring_7_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_ring_7_data,
input wire board_kernel_stream_src_10GbE_ring_7_valid,
output wire board_kernel_stream_src_10GbE_ring_7_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_ring_7_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_ring_7_data,
output wire board_kernel_stream_snk_10GbE_ring_7_valid,
input wire board_kernel_stream_snk_10GbE_ring_7_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_qsfp_0_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_qsfp_0_data,
input wire board_kernel_stream_src_10GbE_qsfp_0_valid,
output wire board_kernel_stream_src_10GbE_qsfp_0_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_qsfp_0_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_0_data,
output wire board_kernel_stream_snk_10GbE_qsfp_0_valid,
input wire board_kernel_stream_snk_10GbE_qsfp_0_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_qsfp_1_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_qsfp_1_data,
input wire board_kernel_stream_src_10GbE_qsfp_1_valid,
output wire board_kernel_stream_src_10GbE_qsfp_1_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_qsfp_1_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_1_data,
output wire board_kernel_stream_snk_10GbE_qsfp_1_valid,
input wire board_kernel_stream_snk_10GbE_qsfp_1_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_qsfp_2_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_qsfp_2_data,
input wire board_kernel_stream_src_10GbE_qsfp_2_valid,
output wire board_kernel_stream_src_10GbE_qsfp_2_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_qsfp_2_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_2_data,
output wire board_kernel_stream_snk_10GbE_qsfp_2_valid,
input wire board_kernel_stream_snk_10GbE_qsfp_2_ready,
- input wire [71:0] board_kernel_stream_src_10GbE_qsfp_3_data,
+ input wire [103:0] board_kernel_stream_src_10GbE_qsfp_3_data,
input wire board_kernel_stream_src_10GbE_qsfp_3_valid,
output wire board_kernel_stream_src_10GbE_qsfp_3_ready,
- output wire [71:0] board_kernel_stream_snk_10GbE_qsfp_3_data,
+ output wire [103:0] board_kernel_stream_snk_10GbE_qsfp_3_data,
output wire board_kernel_stream_snk_10GbE_qsfp_3_valid,
input wire board_kernel_stream_snk_10GbE_qsfp_3_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_0_data,
+ input wire board_kernel_stream_src_lane_0_valid,
+ output wire board_kernel_stream_src_lane_0_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_0_data,
+ output wire board_kernel_stream_snk_lane_0_valid,
+ input wire board_kernel_stream_snk_lane_0_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_1_data,
+ input wire board_kernel_stream_src_lane_1_valid,
+ output wire board_kernel_stream_src_lane_1_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_1_data,
+ output wire board_kernel_stream_snk_lane_1_valid,
+ input wire board_kernel_stream_snk_lane_1_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_2_data,
+ input wire board_kernel_stream_src_lane_2_valid,
+ output wire board_kernel_stream_src_lane_2_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_2_data,
+ output wire board_kernel_stream_snk_lane_2_valid,
+ input wire board_kernel_stream_snk_lane_2_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_3_data,
+ input wire board_kernel_stream_src_lane_3_valid,
+ output wire board_kernel_stream_src_lane_3_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_3_data,
+ output wire board_kernel_stream_snk_lane_3_valid,
+ input wire board_kernel_stream_snk_lane_3_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_4_data,
+ input wire board_kernel_stream_src_lane_4_valid,
+ output wire board_kernel_stream_src_lane_4_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_4_data,
+ output wire board_kernel_stream_snk_lane_4_valid,
+ input wire board_kernel_stream_snk_lane_4_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_5_data,
+ input wire board_kernel_stream_src_lane_5_valid,
+ output wire board_kernel_stream_src_lane_5_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_5_data,
+ output wire board_kernel_stream_snk_lane_5_valid,
+ input wire board_kernel_stream_snk_lane_5_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_6_data,
+ input wire board_kernel_stream_src_lane_6_valid,
+ output wire board_kernel_stream_src_lane_6_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_6_data,
+ output wire board_kernel_stream_snk_lane_6_valid,
+ input wire board_kernel_stream_snk_lane_6_ready,
+
+ input wire [167:0] board_kernel_stream_src_lane_7_data,
+ input wire board_kernel_stream_src_lane_7_valid,
+ output wire board_kernel_stream_src_lane_7_ready,
+ output wire [167:0] board_kernel_stream_snk_lane_7_data,
+ output wire board_kernel_stream_snk_lane_7_valid,
+ input wire board_kernel_stream_snk_lane_7_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_0_data,
+ output wire board_kernel_stream_snk_rx_monitor_0_valid,
+ input wire board_kernel_stream_snk_rx_monitor_0_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_0_data,
+ output wire board_kernel_stream_snk_tx_monitor_0_valid,
+ input wire board_kernel_stream_snk_tx_monitor_0_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_1_data,
+ output wire board_kernel_stream_snk_rx_monitor_1_valid,
+ input wire board_kernel_stream_snk_rx_monitor_1_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_1_data,
+ output wire board_kernel_stream_snk_tx_monitor_1_valid,
+ input wire board_kernel_stream_snk_tx_monitor_1_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_2_data,
+ output wire board_kernel_stream_snk_rx_monitor_2_valid,
+ input wire board_kernel_stream_snk_rx_monitor_2_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_2_data,
+ output wire board_kernel_stream_snk_tx_monitor_2_valid,
+ input wire board_kernel_stream_snk_tx_monitor_2_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_3_data,
+ output wire board_kernel_stream_snk_rx_monitor_3_valid,
+ input wire board_kernel_stream_snk_rx_monitor_3_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_3_data,
+ output wire board_kernel_stream_snk_tx_monitor_3_valid,
+ input wire board_kernel_stream_snk_tx_monitor_3_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_4_data,
+ output wire board_kernel_stream_snk_rx_monitor_4_valid,
+ input wire board_kernel_stream_snk_rx_monitor_4_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_4_data,
+ output wire board_kernel_stream_snk_tx_monitor_4_valid,
+ input wire board_kernel_stream_snk_tx_monitor_4_ready,
- input wire [71:0] board_kernel_stream_src_lane_data,
- input wire board_kernel_stream_src_lane_valid,
- output wire board_kernel_stream_src_lane_ready,
- output wire [71:0] board_kernel_stream_snk_lane_data,
- output wire board_kernel_stream_snk_lane_valid,
- input wire board_kernel_stream_snk_lane_ready,
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_5_data,
+ output wire board_kernel_stream_snk_rx_monitor_5_valid,
+ input wire board_kernel_stream_snk_rx_monitor_5_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_5_data,
+ output wire board_kernel_stream_snk_tx_monitor_5_valid,
+ input wire board_kernel_stream_snk_tx_monitor_5_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_6_data,
+ output wire board_kernel_stream_snk_rx_monitor_6_valid,
+ input wire board_kernel_stream_snk_rx_monitor_6_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_6_data,
+ output wire board_kernel_stream_snk_tx_monitor_6_valid,
+ input wire board_kernel_stream_snk_tx_monitor_6_ready,
+
+ output wire [167:0] board_kernel_stream_snk_rx_monitor_7_data,
+ output wire board_kernel_stream_snk_rx_monitor_7_valid,
+ input wire board_kernel_stream_snk_rx_monitor_7_ready,
+ output wire [167:0] board_kernel_stream_snk_tx_monitor_7_data,
+ output wire board_kernel_stream_snk_tx_monitor_7_valid,
+ input wire board_kernel_stream_snk_tx_monitor_7_ready,
+
+ input wire [103:0] board_kernel_stream_src_bs_data,
+ input wire board_kernel_stream_src_bs_valid,
+ output wire board_kernel_stream_src_bs_ready,
output [6:0] board_kernel_register_mem_address,
output board_kernel_register_mem_clken,
output board_kernel_register_mem_chipselect,
output board_kernel_register_mem_write,
- input [255:0] board_kernel_register_mem_readdata,
- output [255:0] board_kernel_register_mem_writedata,
- output [31:0] board_kernel_register_mem_byteenable
+ input [255:0] board_kernel_register_mem_readdata,
+ output [255:0] board_kernel_register_mem_writedata,
+ output [31:0] board_kernel_register_mem_byteenable
);
//=======================================================
// pr_region instantiation
@@ -259,13 +368,123 @@ pr_region pr_region_inst
.kernel_stream_snk_10GbE_qsfp_3_ready(board_kernel_stream_snk_10GbE_qsfp_3_ready),
.kernel_stream_snk_10GbE_qsfp_3_valid(board_kernel_stream_snk_10GbE_qsfp_3_valid),
- .kernel_stream_src_lane_data( board_kernel_stream_src_lane_data),
- .kernel_stream_src_lane_ready(board_kernel_stream_src_lane_ready),
- .kernel_stream_src_lane_valid(board_kernel_stream_src_lane_valid),
- .kernel_stream_snk_lane_data( board_kernel_stream_snk_lane_data),
- .kernel_stream_snk_lane_ready(board_kernel_stream_snk_lane_ready),
- .kernel_stream_snk_lane_valid(board_kernel_stream_snk_lane_valid),
+ .kernel_stream_src_lane_0_data( board_kernel_stream_src_lane_0_data),
+ .kernel_stream_src_lane_0_ready(board_kernel_stream_src_lane_0_ready),
+ .kernel_stream_src_lane_0_valid(board_kernel_stream_src_lane_0_valid),
+ .kernel_stream_snk_lane_0_data( board_kernel_stream_snk_lane_0_data),
+ .kernel_stream_snk_lane_0_ready(board_kernel_stream_snk_lane_0_ready),
+ .kernel_stream_snk_lane_0_valid(board_kernel_stream_snk_lane_0_valid),
+
+ .kernel_stream_src_lane_1_data( board_kernel_stream_src_lane_1_data),
+ .kernel_stream_src_lane_1_ready(board_kernel_stream_src_lane_1_ready),
+ .kernel_stream_src_lane_1_valid(board_kernel_stream_src_lane_1_valid),
+ .kernel_stream_snk_lane_1_data( board_kernel_stream_snk_lane_1_data),
+ .kernel_stream_snk_lane_1_ready(board_kernel_stream_snk_lane_1_ready),
+ .kernel_stream_snk_lane_1_valid(board_kernel_stream_snk_lane_1_valid),
+
+ .kernel_stream_src_lane_2_data( board_kernel_stream_src_lane_2_data),
+ .kernel_stream_src_lane_2_ready(board_kernel_stream_src_lane_2_ready),
+ .kernel_stream_src_lane_2_valid(board_kernel_stream_src_lane_2_valid),
+ .kernel_stream_snk_lane_2_data( board_kernel_stream_snk_lane_2_data),
+ .kernel_stream_snk_lane_2_ready(board_kernel_stream_snk_lane_2_ready),
+ .kernel_stream_snk_lane_2_valid(board_kernel_stream_snk_lane_2_valid),
+
+ .kernel_stream_src_lane_3_data( board_kernel_stream_src_lane_3_data),
+ .kernel_stream_src_lane_3_ready(board_kernel_stream_src_lane_3_ready),
+ .kernel_stream_src_lane_3_valid(board_kernel_stream_src_lane_3_valid),
+ .kernel_stream_snk_lane_3_data( board_kernel_stream_snk_lane_3_data),
+ .kernel_stream_snk_lane_3_ready(board_kernel_stream_snk_lane_3_ready),
+ .kernel_stream_snk_lane_3_valid(board_kernel_stream_snk_lane_3_valid),
+
+ .kernel_stream_src_lane_4_data( board_kernel_stream_src_lane_4_data),
+ .kernel_stream_src_lane_4_ready(board_kernel_stream_src_lane_4_ready),
+ .kernel_stream_src_lane_4_valid(board_kernel_stream_src_lane_4_valid),
+ .kernel_stream_snk_lane_4_data( board_kernel_stream_snk_lane_4_data),
+ .kernel_stream_snk_lane_4_ready(board_kernel_stream_snk_lane_4_ready),
+ .kernel_stream_snk_lane_4_valid(board_kernel_stream_snk_lane_4_valid),
+
+ .kernel_stream_src_lane_5_data( board_kernel_stream_src_lane_5_data),
+ .kernel_stream_src_lane_5_ready(board_kernel_stream_src_lane_5_ready),
+ .kernel_stream_src_lane_5_valid(board_kernel_stream_src_lane_5_valid),
+ .kernel_stream_snk_lane_5_data( board_kernel_stream_snk_lane_5_data),
+ .kernel_stream_snk_lane_5_ready(board_kernel_stream_snk_lane_5_ready),
+ .kernel_stream_snk_lane_5_valid(board_kernel_stream_snk_lane_5_valid),
+
+ .kernel_stream_src_lane_6_data( board_kernel_stream_src_lane_6_data),
+ .kernel_stream_src_lane_6_ready(board_kernel_stream_src_lane_6_ready),
+ .kernel_stream_src_lane_6_valid(board_kernel_stream_src_lane_6_valid),
+ .kernel_stream_snk_lane_6_data( board_kernel_stream_snk_lane_6_data),
+ .kernel_stream_snk_lane_6_ready(board_kernel_stream_snk_lane_6_ready),
+ .kernel_stream_snk_lane_6_valid(board_kernel_stream_snk_lane_6_valid),
+
+ .kernel_stream_src_lane_7_data( board_kernel_stream_src_lane_7_data),
+ .kernel_stream_src_lane_7_ready(board_kernel_stream_src_lane_7_ready),
+ .kernel_stream_src_lane_7_valid(board_kernel_stream_src_lane_7_valid),
+ .kernel_stream_snk_lane_7_data( board_kernel_stream_snk_lane_7_data),
+ .kernel_stream_snk_lane_7_ready(board_kernel_stream_snk_lane_7_ready),
+ .kernel_stream_snk_lane_7_valid(board_kernel_stream_snk_lane_7_valid),
+
+ .kernel_stream_snk_rx_monitor_0_data( board_kernel_stream_snk_rx_monitor_0_data),
+ .kernel_stream_snk_rx_monitor_0_ready(board_kernel_stream_snk_rx_monitor_0_ready),
+ .kernel_stream_snk_rx_monitor_0_valid(board_kernel_stream_snk_rx_monitor_0_valid),
+ .kernel_stream_snk_tx_monitor_0_data( board_kernel_stream_snk_tx_monitor_0_data),
+ .kernel_stream_snk_tx_monitor_0_ready(board_kernel_stream_snk_tx_monitor_0_ready),
+ .kernel_stream_snk_tx_monitor_0_valid(board_kernel_stream_snk_tx_monitor_0_valid),
+
+ .kernel_stream_snk_rx_monitor_1_data( board_kernel_stream_snk_rx_monitor_1_data),
+ .kernel_stream_snk_rx_monitor_1_ready(board_kernel_stream_snk_rx_monitor_1_ready),
+ .kernel_stream_snk_rx_monitor_1_valid(board_kernel_stream_snk_rx_monitor_1_valid),
+ .kernel_stream_snk_tx_monitor_1_data( board_kernel_stream_snk_tx_monitor_1_data),
+ .kernel_stream_snk_tx_monitor_1_ready(board_kernel_stream_snk_tx_monitor_1_ready),
+ .kernel_stream_snk_tx_monitor_1_valid(board_kernel_stream_snk_tx_monitor_1_valid),
+
+ .kernel_stream_snk_rx_monitor_2_data( board_kernel_stream_snk_rx_monitor_2_data),
+ .kernel_stream_snk_rx_monitor_2_ready(board_kernel_stream_snk_rx_monitor_2_ready),
+ .kernel_stream_snk_rx_monitor_2_valid(board_kernel_stream_snk_rx_monitor_2_valid),
+ .kernel_stream_snk_tx_monitor_2_data( board_kernel_stream_snk_tx_monitor_2_data),
+ .kernel_stream_snk_tx_monitor_2_ready(board_kernel_stream_snk_tx_monitor_2_ready),
+ .kernel_stream_snk_tx_monitor_2_valid(board_kernel_stream_snk_tx_monitor_2_valid),
+
+ .kernel_stream_snk_rx_monitor_3_data( board_kernel_stream_snk_rx_monitor_3_data),
+ .kernel_stream_snk_rx_monitor_3_ready(board_kernel_stream_snk_rx_monitor_3_ready),
+ .kernel_stream_snk_rx_monitor_3_valid(board_kernel_stream_snk_rx_monitor_3_valid),
+ .kernel_stream_snk_tx_monitor_3_data( board_kernel_stream_snk_tx_monitor_3_data),
+ .kernel_stream_snk_tx_monitor_3_ready(board_kernel_stream_snk_tx_monitor_3_ready),
+ .kernel_stream_snk_tx_monitor_3_valid(board_kernel_stream_snk_tx_monitor_3_valid),
+
+ .kernel_stream_snk_rx_monitor_4_data( board_kernel_stream_snk_rx_monitor_4_data),
+ .kernel_stream_snk_rx_monitor_4_ready(board_kernel_stream_snk_rx_monitor_4_ready),
+ .kernel_stream_snk_rx_monitor_4_valid(board_kernel_stream_snk_rx_monitor_4_valid),
+ .kernel_stream_snk_tx_monitor_4_data( board_kernel_stream_snk_tx_monitor_4_data),
+ .kernel_stream_snk_tx_monitor_4_ready(board_kernel_stream_snk_tx_monitor_4_ready),
+ .kernel_stream_snk_tx_monitor_4_valid(board_kernel_stream_snk_tx_monitor_4_valid),
+
+ .kernel_stream_snk_rx_monitor_5_data( board_kernel_stream_snk_rx_monitor_5_data),
+ .kernel_stream_snk_rx_monitor_5_ready(board_kernel_stream_snk_rx_monitor_5_ready),
+ .kernel_stream_snk_rx_monitor_5_valid(board_kernel_stream_snk_rx_monitor_5_valid),
+ .kernel_stream_snk_tx_monitor_5_data( board_kernel_stream_snk_tx_monitor_5_data),
+ .kernel_stream_snk_tx_monitor_5_ready(board_kernel_stream_snk_tx_monitor_5_ready),
+ .kernel_stream_snk_tx_monitor_5_valid(board_kernel_stream_snk_tx_monitor_5_valid),
+
+ .kernel_stream_snk_rx_monitor_6_data( board_kernel_stream_snk_rx_monitor_6_data),
+ .kernel_stream_snk_rx_monitor_6_ready(board_kernel_stream_snk_rx_monitor_6_ready),
+ .kernel_stream_snk_rx_monitor_6_valid(board_kernel_stream_snk_rx_monitor_6_valid),
+ .kernel_stream_snk_tx_monitor_6_data( board_kernel_stream_snk_tx_monitor_6_data),
+ .kernel_stream_snk_tx_monitor_6_ready(board_kernel_stream_snk_tx_monitor_6_ready),
+ .kernel_stream_snk_tx_monitor_6_valid(board_kernel_stream_snk_tx_monitor_6_valid),
+
+ .kernel_stream_snk_rx_monitor_7_data( board_kernel_stream_snk_rx_monitor_7_data),
+ .kernel_stream_snk_rx_monitor_7_ready(board_kernel_stream_snk_rx_monitor_7_ready),
+ .kernel_stream_snk_rx_monitor_7_valid(board_kernel_stream_snk_rx_monitor_7_valid),
+ .kernel_stream_snk_tx_monitor_7_data( board_kernel_stream_snk_tx_monitor_7_data),
+ .kernel_stream_snk_tx_monitor_7_ready(board_kernel_stream_snk_tx_monitor_7_ready),
+ .kernel_stream_snk_tx_monitor_7_valid(board_kernel_stream_snk_tx_monitor_7_valid),
+
+
+ .kernel_stream_src_bs_data( board_kernel_stream_src_bs_data),
+ .kernel_stream_src_bs_ready(board_kernel_stream_src_bs_ready),
+ .kernel_stream_src_bs_valid(board_kernel_stream_src_bs_valid),
.kernel_stream_snk_mm_io_data(board_kernel_stream_snk_mm_io_data),
.kernel_stream_snk_mm_io_ready(board_kernel_stream_snk_mm_io_ready),
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
index 84122659265f2bbdf6c3535044b142b632570788..b00e18a8f17971d40ea9f25d95cc2065ec6c2142 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ip/pr_region.v
@@ -40,9 +40,9 @@ module pr_region (
output wire kernel_register_mem_clken,
output wire kernel_register_mem_chipselect,
output wire kernel_register_mem_write,
- input wire [255:0] kernel_register_mem_readdata,
- output wire [255:0] kernel_register_mem_writedata,
- output wire [31:0] kernel_register_mem_byteenable,
+ input wire [255:0] kernel_register_mem_readdata,
+ output wire [255:0] kernel_register_mem_writedata,
+ output wire [31:0] kernel_register_mem_byteenable,
input wire [71:0] kernel_stream_src_mm_io_data,
input wire kernel_stream_src_mm_io_valid,
@@ -51,96 +51,208 @@ module pr_region (
output wire kernel_stream_snk_mm_io_valid,
input wire kernel_stream_snk_mm_io_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_0_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_0_data,
input wire kernel_stream_src_10GbE_ring_0_valid,
output wire kernel_stream_src_10GbE_ring_0_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_0_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_0_data,
output wire kernel_stream_snk_10GbE_ring_0_valid,
input wire kernel_stream_snk_10GbE_ring_0_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_1_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_1_data,
input wire kernel_stream_src_10GbE_ring_1_valid,
output wire kernel_stream_src_10GbE_ring_1_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_1_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_1_data,
output wire kernel_stream_snk_10GbE_ring_1_valid,
input wire kernel_stream_snk_10GbE_ring_1_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_2_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_2_data,
input wire kernel_stream_src_10GbE_ring_2_valid,
output wire kernel_stream_src_10GbE_ring_2_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_2_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_2_data,
output wire kernel_stream_snk_10GbE_ring_2_valid,
input wire kernel_stream_snk_10GbE_ring_2_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_3_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_3_data,
input wire kernel_stream_src_10GbE_ring_3_valid,
output wire kernel_stream_src_10GbE_ring_3_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_3_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_3_data,
output wire kernel_stream_snk_10GbE_ring_3_valid,
input wire kernel_stream_snk_10GbE_ring_3_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_4_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_4_data,
input wire kernel_stream_src_10GbE_ring_4_valid,
output wire kernel_stream_src_10GbE_ring_4_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_4_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_4_data,
output wire kernel_stream_snk_10GbE_ring_4_valid,
input wire kernel_stream_snk_10GbE_ring_4_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_5_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_5_data,
input wire kernel_stream_src_10GbE_ring_5_valid,
output wire kernel_stream_src_10GbE_ring_5_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_5_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_5_data,
output wire kernel_stream_snk_10GbE_ring_5_valid,
input wire kernel_stream_snk_10GbE_ring_5_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_6_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_6_data,
input wire kernel_stream_src_10GbE_ring_6_valid,
output wire kernel_stream_src_10GbE_ring_6_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_6_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_6_data,
output wire kernel_stream_snk_10GbE_ring_6_valid,
input wire kernel_stream_snk_10GbE_ring_6_ready,
- input wire [71:0] kernel_stream_src_10GbE_ring_7_data,
+ input wire [103:0] kernel_stream_src_10GbE_ring_7_data,
input wire kernel_stream_src_10GbE_ring_7_valid,
output wire kernel_stream_src_10GbE_ring_7_ready,
- output wire [71:0] kernel_stream_snk_10GbE_ring_7_data,
+ output wire [103:0] kernel_stream_snk_10GbE_ring_7_data,
output wire kernel_stream_snk_10GbE_ring_7_valid,
input wire kernel_stream_snk_10GbE_ring_7_ready,
- input wire [71:0] kernel_stream_src_10GbE_qsfp_0_data,
+ input wire [103:0] kernel_stream_src_10GbE_qsfp_0_data,
input wire kernel_stream_src_10GbE_qsfp_0_valid,
output wire kernel_stream_src_10GbE_qsfp_0_ready,
- output wire [71:0] kernel_stream_snk_10GbE_qsfp_0_data,
+ output wire [103:0] kernel_stream_snk_10GbE_qsfp_0_data,
output wire kernel_stream_snk_10GbE_qsfp_0_valid,
input wire kernel_stream_snk_10GbE_qsfp_0_ready,
- input wire [71:0] kernel_stream_src_10GbE_qsfp_1_data,
+ input wire [103:0] kernel_stream_src_10GbE_qsfp_1_data,
input wire kernel_stream_src_10GbE_qsfp_1_valid,
output wire kernel_stream_src_10GbE_qsfp_1_ready,
- output wire [71:0] kernel_stream_snk_10GbE_qsfp_1_data,
+ output wire [103:0] kernel_stream_snk_10GbE_qsfp_1_data,
output wire kernel_stream_snk_10GbE_qsfp_1_valid,
input wire kernel_stream_snk_10GbE_qsfp_1_ready,
- input wire [71:0] kernel_stream_src_10GbE_qsfp_2_data,
+ input wire [103:0] kernel_stream_src_10GbE_qsfp_2_data,
input wire kernel_stream_src_10GbE_qsfp_2_valid,
output wire kernel_stream_src_10GbE_qsfp_2_ready,
- output wire [71:0] kernel_stream_snk_10GbE_qsfp_2_data,
+ output wire [103:0] kernel_stream_snk_10GbE_qsfp_2_data,
output wire kernel_stream_snk_10GbE_qsfp_2_valid,
input wire kernel_stream_snk_10GbE_qsfp_2_ready,
- input wire [71:0] kernel_stream_src_10GbE_qsfp_3_data,
+ input wire [103:0] kernel_stream_src_10GbE_qsfp_3_data,
input wire kernel_stream_src_10GbE_qsfp_3_valid,
output wire kernel_stream_src_10GbE_qsfp_3_ready,
- output wire [71:0] kernel_stream_snk_10GbE_qsfp_3_data,
+ output wire [103:0] kernel_stream_snk_10GbE_qsfp_3_data,
output wire kernel_stream_snk_10GbE_qsfp_3_valid,
input wire kernel_stream_snk_10GbE_qsfp_3_ready,
- input wire [71:0] kernel_stream_src_lane_data,
- input wire kernel_stream_src_lane_valid,
- output wire kernel_stream_src_lane_ready,
- output wire [71:0] kernel_stream_snk_lane_data,
- output wire kernel_stream_snk_lane_valid,
- input wire kernel_stream_snk_lane_ready
+ input wire [167:0] kernel_stream_src_lane_0_data,
+ input wire kernel_stream_src_lane_0_valid,
+ output wire kernel_stream_src_lane_0_ready,
+ output wire [167:0] kernel_stream_snk_lane_0_data,
+ output wire kernel_stream_snk_lane_0_valid,
+ input wire kernel_stream_snk_lane_0_ready,
+
+ input wire [167:0] kernel_stream_src_lane_1_data,
+ input wire kernel_stream_src_lane_1_valid,
+ output wire kernel_stream_src_lane_1_ready,
+ output wire [167:0] kernel_stream_snk_lane_1_data,
+ output wire kernel_stream_snk_lane_1_valid,
+ input wire kernel_stream_snk_lane_1_ready,
+
+ input wire [167:0] kernel_stream_src_lane_2_data,
+ input wire kernel_stream_src_lane_2_valid,
+ output wire kernel_stream_src_lane_2_ready,
+ output wire [167:0] kernel_stream_snk_lane_2_data,
+ output wire kernel_stream_snk_lane_2_valid,
+ input wire kernel_stream_snk_lane_2_ready,
+
+ input wire [167:0] kernel_stream_src_lane_3_data,
+ input wire kernel_stream_src_lane_3_valid,
+ output wire kernel_stream_src_lane_3_ready,
+ output wire [167:0] kernel_stream_snk_lane_3_data,
+ output wire kernel_stream_snk_lane_3_valid,
+ input wire kernel_stream_snk_lane_3_ready,
+
+ input wire [167:0] kernel_stream_src_lane_4_data,
+ input wire kernel_stream_src_lane_4_valid,
+ output wire kernel_stream_src_lane_4_ready,
+ output wire [167:0] kernel_stream_snk_lane_4_data,
+ output wire kernel_stream_snk_lane_4_valid,
+ input wire kernel_stream_snk_lane_4_ready,
+
+ input wire [167:0] kernel_stream_src_lane_5_data,
+ input wire kernel_stream_src_lane_5_valid,
+ output wire kernel_stream_src_lane_5_ready,
+ output wire [167:0] kernel_stream_snk_lane_5_data,
+ output wire kernel_stream_snk_lane_5_valid,
+ input wire kernel_stream_snk_lane_5_ready,
+
+ input wire [167:0] kernel_stream_src_lane_6_data,
+ input wire kernel_stream_src_lane_6_valid,
+ output wire kernel_stream_src_lane_6_ready,
+ output wire [167:0] kernel_stream_snk_lane_6_data,
+ output wire kernel_stream_snk_lane_6_valid,
+ input wire kernel_stream_snk_lane_6_ready,
+
+ input wire [167:0] kernel_stream_src_lane_7_data,
+ input wire kernel_stream_src_lane_7_valid,
+ output wire kernel_stream_src_lane_7_ready,
+ output wire [167:0] kernel_stream_snk_lane_7_data,
+ output wire kernel_stream_snk_lane_7_valid,
+ input wire kernel_stream_snk_lane_7_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_0_data,
+ output wire kernel_stream_snk_rx_monitor_0_valid,
+ input wire kernel_stream_snk_rx_monitor_0_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_0_data,
+ output wire kernel_stream_snk_tx_monitor_0_valid,
+ input wire kernel_stream_snk_tx_monitor_0_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_1_data,
+ output wire kernel_stream_snk_rx_monitor_1_valid,
+ input wire kernel_stream_snk_rx_monitor_1_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_1_data,
+ output wire kernel_stream_snk_tx_monitor_1_valid,
+ input wire kernel_stream_snk_tx_monitor_1_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_2_data,
+ output wire kernel_stream_snk_rx_monitor_2_valid,
+ input wire kernel_stream_snk_rx_monitor_2_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_2_data,
+ output wire kernel_stream_snk_tx_monitor_2_valid,
+ input wire kernel_stream_snk_tx_monitor_2_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_3_data,
+ output wire kernel_stream_snk_rx_monitor_3_valid,
+ input wire kernel_stream_snk_rx_monitor_3_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_3_data,
+ output wire kernel_stream_snk_tx_monitor_3_valid,
+ input wire kernel_stream_snk_tx_monitor_3_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_4_data,
+ output wire kernel_stream_snk_rx_monitor_4_valid,
+ input wire kernel_stream_snk_rx_monitor_4_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_4_data,
+ output wire kernel_stream_snk_tx_monitor_4_valid,
+ input wire kernel_stream_snk_tx_monitor_4_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_5_data,
+ output wire kernel_stream_snk_rx_monitor_5_valid,
+ input wire kernel_stream_snk_rx_monitor_5_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_5_data,
+ output wire kernel_stream_snk_tx_monitor_5_valid,
+ input wire kernel_stream_snk_tx_monitor_5_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_6_data,
+ output wire kernel_stream_snk_rx_monitor_6_valid,
+ input wire kernel_stream_snk_rx_monitor_6_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_6_data,
+ output wire kernel_stream_snk_tx_monitor_6_valid,
+ input wire kernel_stream_snk_tx_monitor_6_ready,
+
+ output wire [167:0] kernel_stream_snk_rx_monitor_7_data,
+ output wire kernel_stream_snk_rx_monitor_7_valid,
+ input wire kernel_stream_snk_rx_monitor_7_ready,
+ output wire [167:0] kernel_stream_snk_tx_monitor_7_data,
+ output wire kernel_stream_snk_tx_monitor_7_valid,
+ input wire kernel_stream_snk_tx_monitor_7_ready,
+
+
+ input wire [103:0] kernel_stream_src_bs_data,
+ input wire kernel_stream_src_bs_valid,
+ output wire kernel_stream_src_bs_ready
+
+
);
wire [11:0] kernel_system_register_mem_address;
wire kernel_system_register_mem_write;
@@ -244,11 +356,6 @@ kernel_system kernel_system_inst
.kernel_input_10GbE_qsfp_3_ready(kernel_stream_src_10GbE_qsfp_3_ready),
.kernel_input_10GbE_qsfp_3_valid(kernel_stream_src_10GbE_qsfp_3_valid),
- .kernel_input_lane_data( kernel_stream_src_lane_data),
- .kernel_input_lane_ready(kernel_stream_src_lane_ready),
- .kernel_input_lane_valid(kernel_stream_src_lane_valid),
-
-
.kernel_output_10GbE_ring_0_data( kernel_stream_snk_10GbE_ring_0_data),
.kernel_output_10GbE_ring_0_ready(kernel_stream_snk_10GbE_ring_0_ready),
.kernel_output_10GbE_ring_0_valid(kernel_stream_snk_10GbE_ring_0_valid),
@@ -297,10 +404,122 @@ kernel_system kernel_system_inst
.kernel_output_10GbE_qsfp_3_ready(kernel_stream_snk_10GbE_qsfp_3_ready),
.kernel_output_10GbE_qsfp_3_valid(kernel_stream_snk_10GbE_qsfp_3_valid),
- .kernel_output_lane_data( kernel_stream_snk_lane_data),
- .kernel_output_lane_ready(kernel_stream_snk_lane_ready),
- .kernel_output_lane_valid(kernel_stream_snk_lane_valid),
-
+ .kernel_input_lane_0_data( kernel_stream_src_lane_0_data),
+ .kernel_input_lane_0_ready(kernel_stream_src_lane_0_ready),
+ .kernel_input_lane_0_valid(kernel_stream_src_lane_0_valid),
+ .kernel_output_lane_0_data( kernel_stream_snk_lane_0_data),
+ .kernel_output_lane_0_ready(kernel_stream_snk_lane_0_ready),
+ .kernel_output_lane_0_valid(kernel_stream_snk_lane_0_valid),
+
+ .kernel_input_lane_1_data( kernel_stream_src_lane_1_data),
+ .kernel_input_lane_1_ready(kernel_stream_src_lane_1_ready),
+ .kernel_input_lane_1_valid(kernel_stream_src_lane_1_valid),
+ .kernel_output_lane_1_data( kernel_stream_snk_lane_1_data),
+ .kernel_output_lane_1_ready(kernel_stream_snk_lane_1_ready),
+ .kernel_output_lane_1_valid(kernel_stream_snk_lane_1_valid),
+
+ .kernel_input_lane_2_data( kernel_stream_src_lane_2_data),
+ .kernel_input_lane_2_ready(kernel_stream_src_lane_2_ready),
+ .kernel_input_lane_2_valid(kernel_stream_src_lane_2_valid),
+ .kernel_output_lane_2_data( kernel_stream_snk_lane_2_data),
+ .kernel_output_lane_2_ready(kernel_stream_snk_lane_2_ready),
+ .kernel_output_lane_2_valid(kernel_stream_snk_lane_2_valid),
+
+ .kernel_input_lane_3_data( kernel_stream_src_lane_3_data),
+ .kernel_input_lane_3_ready(kernel_stream_src_lane_3_ready),
+ .kernel_input_lane_3_valid(kernel_stream_src_lane_3_valid),
+ .kernel_output_lane_3_data( kernel_stream_snk_lane_3_data),
+ .kernel_output_lane_3_ready(kernel_stream_snk_lane_3_ready),
+ .kernel_output_lane_3_valid(kernel_stream_snk_lane_3_valid),
+
+ .kernel_input_lane_4_data( kernel_stream_src_lane_4_data),
+ .kernel_input_lane_4_ready(kernel_stream_src_lane_4_ready),
+ .kernel_input_lane_4_valid(kernel_stream_src_lane_4_valid),
+ .kernel_output_lane_4_data( kernel_stream_snk_lane_4_data),
+ .kernel_output_lane_4_ready(kernel_stream_snk_lane_4_ready),
+ .kernel_output_lane_4_valid(kernel_stream_snk_lane_4_valid),
+
+ .kernel_input_lane_5_data( kernel_stream_src_lane_5_data),
+ .kernel_input_lane_5_ready(kernel_stream_src_lane_5_ready),
+ .kernel_input_lane_5_valid(kernel_stream_src_lane_5_valid),
+ .kernel_output_lane_5_data( kernel_stream_snk_lane_5_data),
+ .kernel_output_lane_5_ready(kernel_stream_snk_lane_5_ready),
+ .kernel_output_lane_5_valid(kernel_stream_snk_lane_5_valid),
+
+ .kernel_input_lane_6_data( kernel_stream_src_lane_6_data),
+ .kernel_input_lane_6_ready(kernel_stream_src_lane_6_ready),
+ .kernel_input_lane_6_valid(kernel_stream_src_lane_6_valid),
+ .kernel_output_lane_6_data( kernel_stream_snk_lane_6_data),
+ .kernel_output_lane_6_ready(kernel_stream_snk_lane_6_ready),
+ .kernel_output_lane_6_valid(kernel_stream_snk_lane_6_valid),
+
+ .kernel_input_lane_7_data( kernel_stream_src_lane_7_data),
+ .kernel_input_lane_7_ready(kernel_stream_src_lane_7_ready),
+ .kernel_input_lane_7_valid(kernel_stream_src_lane_7_valid),
+ .kernel_output_lane_7_data( kernel_stream_snk_lane_7_data),
+ .kernel_output_lane_7_ready(kernel_stream_snk_lane_7_ready),
+ .kernel_output_lane_7_valid(kernel_stream_snk_lane_7_valid),
+
+ .kernel_output_rx_monitor_0_data( kernel_stream_snk_rx_monitor_0_data),
+ .kernel_output_rx_monitor_0_ready(kernel_stream_snk_rx_monitor_0_ready),
+ .kernel_output_rx_monitor_0_valid(kernel_stream_snk_rx_monitor_0_valid),
+ .kernel_output_tx_monitor_0_data( kernel_stream_snk_tx_monitor_0_data),
+ .kernel_output_tx_monitor_0_ready(kernel_stream_snk_tx_monitor_0_ready),
+ .kernel_output_tx_monitor_0_valid(kernel_stream_snk_tx_monitor_0_valid),
+
+ .kernel_output_rx_monitor_1_data( kernel_stream_snk_rx_monitor_1_data),
+ .kernel_output_rx_monitor_1_ready(kernel_stream_snk_rx_monitor_1_ready),
+ .kernel_output_rx_monitor_1_valid(kernel_stream_snk_rx_monitor_1_valid),
+ .kernel_output_tx_monitor_1_data( kernel_stream_snk_tx_monitor_1_data),
+ .kernel_output_tx_monitor_1_ready(kernel_stream_snk_tx_monitor_1_ready),
+ .kernel_output_tx_monitor_1_valid(kernel_stream_snk_tx_monitor_1_valid),
+
+ .kernel_output_rx_monitor_2_data( kernel_stream_snk_rx_monitor_2_data),
+ .kernel_output_rx_monitor_2_ready(kernel_stream_snk_rx_monitor_2_ready),
+ .kernel_output_rx_monitor_2_valid(kernel_stream_snk_rx_monitor_2_valid),
+ .kernel_output_tx_monitor_2_data( kernel_stream_snk_tx_monitor_2_data),
+ .kernel_output_tx_monitor_2_ready(kernel_stream_snk_tx_monitor_2_ready),
+ .kernel_output_tx_monitor_2_valid(kernel_stream_snk_tx_monitor_2_valid),
+
+ .kernel_output_rx_monitor_3_data( kernel_stream_snk_rx_monitor_3_data),
+ .kernel_output_rx_monitor_3_ready(kernel_stream_snk_rx_monitor_3_ready),
+ .kernel_output_rx_monitor_3_valid(kernel_stream_snk_rx_monitor_3_valid),
+ .kernel_output_tx_monitor_3_data( kernel_stream_snk_tx_monitor_3_data),
+ .kernel_output_tx_monitor_3_ready(kernel_stream_snk_tx_monitor_3_ready),
+ .kernel_output_tx_monitor_3_valid(kernel_stream_snk_tx_monitor_3_valid),
+
+ .kernel_output_rx_monitor_4_data( kernel_stream_snk_rx_monitor_4_data),
+ .kernel_output_rx_monitor_4_ready(kernel_stream_snk_rx_monitor_4_ready),
+ .kernel_output_rx_monitor_4_valid(kernel_stream_snk_rx_monitor_4_valid),
+ .kernel_output_tx_monitor_4_data( kernel_stream_snk_tx_monitor_4_data),
+ .kernel_output_tx_monitor_4_ready(kernel_stream_snk_tx_monitor_4_ready),
+ .kernel_output_tx_monitor_4_valid(kernel_stream_snk_tx_monitor_4_valid),
+
+ .kernel_output_rx_monitor_5_data( kernel_stream_snk_rx_monitor_5_data),
+ .kernel_output_rx_monitor_5_ready(kernel_stream_snk_rx_monitor_5_ready),
+ .kernel_output_rx_monitor_5_valid(kernel_stream_snk_rx_monitor_5_valid),
+ .kernel_output_tx_monitor_5_data( kernel_stream_snk_tx_monitor_5_data),
+ .kernel_output_tx_monitor_5_ready(kernel_stream_snk_tx_monitor_5_ready),
+ .kernel_output_tx_monitor_5_valid(kernel_stream_snk_tx_monitor_5_valid),
+
+ .kernel_output_rx_monitor_6_data( kernel_stream_snk_rx_monitor_6_data),
+ .kernel_output_rx_monitor_6_ready(kernel_stream_snk_rx_monitor_6_ready),
+ .kernel_output_rx_monitor_6_valid(kernel_stream_snk_rx_monitor_6_valid),
+ .kernel_output_tx_monitor_6_data( kernel_stream_snk_tx_monitor_6_data),
+ .kernel_output_tx_monitor_6_ready(kernel_stream_snk_tx_monitor_6_ready),
+ .kernel_output_tx_monitor_6_valid(kernel_stream_snk_tx_monitor_6_valid),
+
+ .kernel_output_rx_monitor_7_data( kernel_stream_snk_rx_monitor_7_data),
+ .kernel_output_rx_monitor_7_ready(kernel_stream_snk_rx_monitor_7_ready),
+ .kernel_output_rx_monitor_7_valid(kernel_stream_snk_rx_monitor_7_valid),
+ .kernel_output_tx_monitor_7_data( kernel_stream_snk_tx_monitor_7_data),
+ .kernel_output_tx_monitor_7_ready(kernel_stream_snk_tx_monitor_7_ready),
+ .kernel_output_tx_monitor_7_valid(kernel_stream_snk_tx_monitor_7_valid),
+
+
+ .kernel_input_bs_sosi_data( kernel_stream_src_bs_data),
+ .kernel_input_bs_sosi_ready(kernel_stream_src_bs_ready),
+ .kernel_input_bs_sosi_valid(kernel_stream_src_bs_valid),
.kernel_input_mm_data(kernel_stream_src_mm_io_data),
.kernel_input_mm_ready(kernel_stream_src_mm_io_ready),
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
index dd4da688b7142a5fdab7b917d3c933505163710c..23618a94e60404ce95c5578e78ed8557c516c290 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/opencl_bsp_ip.qsf
@@ -70,3 +70,8 @@ set_global_assignment -name IP_FILE ip/board/board_ram_scrap.ip
set_global_assignment -name IP_FILE ip/board/board_kclk_global.ip
set_global_assignment -name IP_FILE ip/board/board_ram_diag_bg_ring.ip
set_global_assignment -name IP_FILE ip/board/board_reg_diag_bg_ring.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dp_xonoff_bg.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_dp_xonoff_from_lane.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_bsn_monitor_v2_rx.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_bsn_monitor_v2_tx.ip
+set_global_assignment -name IP_FILE ip/board/board_reg_sdp_info.ip
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de72d6aa588a68e97970c3bc12f9c13455ba3eb4
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -0,0 +1,64 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Reinier vd Walle
+-- Purpose:
+-- . Collection of functions for the ring design
+-- --------------------------------------------------------------------------
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE ring_pkg IS
+
+ FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : NATURAL) RETURN INTEGER;
+ FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR; -- return vector length is same as hops vector length
+
+END ring_pkg;
+
+PACKAGE BODY ring_pkg IS
+
+ FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : NATURAL) RETURN INTEGER IS
+ VARIABLE v_source_rn : INTEGER;
+ BEGIN
+ IF lane_dir > 0 THEN
+ v_source_rn := this_rn - hops;
+ IF v_source_rn < 0 THEN -- Cannot use MOD as N_rn is not a constant.
+ v_source_rn := v_source_rn+N_rn;
+ END IF;
+ ELSE
+ v_source_rn := this_rn + hops;
+ IF v_source_rn > N_rn THEN
+ v_source_rn := v_source_rn-N_rn;
+ END IF;
+ END IF;
+
+ IF (v_source_rn < 0) OR (v_source_rn > N_rn) THEN
+ v_source_rn := -1; -- return -1 for invalid values. This can happen if nof hops > N_rn.
+ END IF;
+ RETURN v_source_rn;
+ END;
+
+ FUNCTION nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN TO_SVEC(nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
+ END;
+
+END ring_pkg;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..46c7e12f44e5c629900412bd1323cc9ee54bd259
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -0,0 +1,317 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_ring_bsp using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read subband statistics (SST)
+--
+-- 4) Read beamlet statistics (BST) via ram_st_bst and verify with
+-- c_exp_beamlet_power_sp_0 at c_sdp_N_sub-1 - c_subband_sp_0.
+-- View sp_beamlet_power_0 in Wave window
+-- 5) Compare SST with BST.
+-- 6) Verify 10GbE output.
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_ring_bsp IS
+END tb_lofar2_unb2b_ring_bsp;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_ring_bsp IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+
+
+ -- MM
+ CONSTANT c_mm_file_reg_sdp_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
+ CONSTANT c_mm_file_reg_dp_xonoff_bg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_BG";
+ CONSTANT c_mm_file_reg_dp_xonoff_from_lane : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_FROM_LANE";
+ CONSTANT c_mm_file_reg_bsn_monitor_rx : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RX";
+ CONSTANT c_mm_file_reg_bsn_monitor_tx : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_TX";
+ CONSTANT c_mm_file_reg_bg_ctrl : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DIAG_BG_RING";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+
+ -- 10GbE
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '1';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ SIGNAL SA_CLK : STD_LOGIC := '1';
+ SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_1 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_2 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_ring_bsp : ENTITY work.top
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_ring_bsp",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_0_TX => si_lpbk_0,
+ -- ring transceivers
+ RING_0_RX => si_lpbk_2,
+ RING_0_TX => si_lpbk_1,
+ RING_1_RX => si_lpbk_1,
+ RING_1_TX => si_lpbk_2,
+
+ -- LEDs
+ QSFP_LED => open
+
+ );
+
+ u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => pps_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => pps_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out
+
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_power_sum_0 : REAL;
+ VARIABLE v_sp_beamlet_power : REAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+
+ ----------------------------------------------------------------------------
+ -- Enable UDP offload (dp_xonoff) of beamset 0
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_bg,0 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_from_lane,0 , 0, tb_clk);
+
+ ----------------------------------------------------------------------------
+ -- Enable BG
+ ----------------------------------------------------------------------------
+ -- 0: enable[1:0] --> off=0, enable=1, enable_pps=3
+ -- 1: samples_per_packet[15:0]
+ -- 2: Blocks_per_sync[15:0]
+ -- 3: Gapsize[15:0]
+ -- 4: Mem_low_adrs[7:0]
+ -- 5: Mem_high_adrs[7:0]
+ -- 6: BSN_init[31:0]
+ -- 7: BSN_init[63:32]
+
+
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 2, c_nof_block_per_sync, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 3, 250 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 4, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 5, 127 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0 , tb_clk);
+
+
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3 , tb_clk);
+ proc_common_wait_some_cycles(ext_clk, 2* c_nof_block_per_sync * 1000);
+
+ ---------------------------------------------------------------------------
+ -- Read TX monitor
+ ---------------------------------------------------------------------------
+ FOR I IN 0 TO 8*128 LOOP
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_tx, I, rd_data, tb_clk);
+ END LOOP;
+
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index 4c13366d12dbbfdd436018bd97afae331bef3aea..6e32616d56255d5d8d7b7fa5760a601f065a93ec 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -1,5 +1,5 @@
-- --------------------------------------------------------------------------
--- Copyright 2020
+-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -30,15 +30,19 @@
-- . M&C
-- --------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, diag_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, tech_pll_lib, dp_lib, diag_lib, mm_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib, lofar2_sdp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE work.ring_pkg.ALL;
USE work.top_components_pkg.ALL;
ENTITY top IS
@@ -54,7 +58,9 @@ ENTITY top IS
g_revision_id : STRING := ""; -- revision_id, commit hash (first 9 chars) or number
g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range : BOOLEAN := FALSE;
- g_nof_lanes : POSITIVE := 1 -- must be in range 1 - 8
+ g_nof_lanes : POSITIVE := 8; -- must be in range 1 - 8
+ g_nof_rx_monitors : NATURAL := 16; -- max = 16
+ g_nof_tx_monitors : NATURAL := 16 -- max = 16
);
PORT (
-- GENERAL
@@ -90,10 +96,10 @@ ENTITY top IS
QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- ring transceivers
- RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS => '0');
- RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
- RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_ring.bus_w-1 DOWNTO 0);
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
@@ -105,23 +111,42 @@ ARCHITECTURE str OF top IS
---------------
-- Constants
---------------
+ CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
+
-- QSFP
CONSTANT c_nof_qsfp_bus : NATURAL := 1;
- CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus;
+ CONSTANT c_nof_streams_qsfp : NATURAL := c_unb2b_board_tr_qsfp.bus_w*c_nof_qsfp_bus; --4
-- RING
CONSTANT c_nof_ring_bus : NATURAL := 2;
- CONSTANT c_ring_bus_w : NATURAL := c_unb2b_board_tr_ring.bus_w;
- CONSTANT c_nof_streams_ring : NATURAL := c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus;
+ CONSTANT c_ring_bus_w : NATURAL := 4; --Using 4 phisically, there are 12
+ CONSTANT c_nof_streams_ring : NATURAL := c_ring_bus_w*c_nof_ring_bus; --c_unb2b_board_tr_ring.bus_w*c_nof_ring_bus; -- 8
-- 10GbE
- CONSTANT c_nof_10GbE_ring_IP : NATURAL := 2*ceil_div(g_nof_lanes, 2);
- CONSTANT c_nof_10GbE_qsfp_IP : NATURAL := ceil_div(g_nof_lanes, 2);
+ CONSTANT c_max_nof_mac : NATURAL := c_nof_streams_qsfp+c_nof_streams_ring; -- Use the 12 channel 10GbE IP
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+ -- OpenCL kernel channel widths as defined in the OpenCL kernel
+ CONSTANT c_kernel_10gbe_channel_w : NATURAL := 104;
+ CONSTANT c_kernel_bs_sosi_channel_w : NATURAL := 104;
+ CONSTANT c_kernel_lane_sosi_channel_w : NATURAL := 168;
+ CONSTANT c_kernel_mm_io_mosi_channel_w : NATURAL := 72;
+ CONSTANT c_kernel_mm_io_miso_channel_w : NATURAL := 32;
+
+ -- OpenCL kernel regmap address width as defined in qsys
+ CONSTANT c_kernel_regmap_addr_w : NATURAL := 8;
+
+ ------------
+ -- Types
+ ------------
+ TYPE t_dp_siso_rx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_siso_arr(g_nof_rx_monitors-1 DOWNTO 0);
+ TYPE t_dp_sosi_rx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0);
+ TYPE t_dp_siso_tx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_siso_arr(g_nof_tx_monitors-1 DOWNTO 0);
+ TYPE t_dp_sosi_tx_monitor_2arr IS ARRAY (INTEGER RANGE <>) OF t_dp_sosi_arr(g_nof_tx_monitors-1 DOWNTO 0);
+
------------
-- Signals
------------
@@ -208,10 +233,34 @@ ARCHITECTURE str OF top IS
SIGNAL ram_bg_data_mosi : t_mem_mosi;
SIGNAL ram_bg_data_miso : t_mem_miso;
+ -- DP XonOff
+ SIGNAL reg_dp_xonoff_bg_mosi : t_mem_mosi;
+ SIGNAL reg_dp_xonoff_bg_miso : t_mem_miso;
+ SIGNAL reg_dp_xonoff_from_lane_mosi : t_mem_mosi;
+ SIGNAL reg_dp_xonoff_from_lane_miso : t_mem_miso;
+
+ -- tx/rx monitors
+ SIGNAL reg_bsn_monitor_v2_tx_mosi_arr : t_mem_mosi_arr(g_nof_lanes-1 DOWNTO 0);
+ SIGNAL reg_bsn_monitor_v2_tx_miso_arr : t_mem_miso_arr(g_nof_lanes-1 DOWNTO 0);
+ SIGNAL reg_bsn_monitor_v2_rx_mosi_arr : t_mem_mosi_arr(g_nof_lanes-1 DOWNTO 0);
+ SIGNAL reg_bsn_monitor_v2_rx_miso_arr : t_mem_miso_arr(g_nof_lanes-1 DOWNTO 0);
+ SIGNAL reg_bsn_monitor_v2_tx_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_v2_tx_miso : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_rx_mosi : t_mem_mosi;
+ SIGNAL reg_bsn_monitor_v2_rx_miso : t_mem_miso;
+
-- MM IO
SIGNAL reg_ta2_unb2b_mm_io_mosi : t_mem_mosi;
SIGNAL reg_ta2_unb2b_mm_io_miso : t_mem_miso;
-
+
+ -- SDP Info
+ SIGNAL reg_sdp_info_mosi : t_mem_mosi;
+ SIGNAL reg_sdp_info_miso : t_mem_miso;
+
+ -- PLL
+ SIGNAL clk_156 : STD_LOGIC := '0';
+ SIGNAL clk_312 : STD_LOGIC := '0';
+ SIGNAL rst_156 : STD_LOGIC := '0';
-- QSFP
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
@@ -221,8 +270,8 @@ ARCHITECTURE str OF top IS
SIGNAL unb2b_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
-- RING
- SIGNAL i_RING_TX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
- SIGNAL i_RING_RX : t_unb2b_board_ring_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
+ SIGNAL i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0); --TODO make ring bus array with 4 elements
+ SIGNAL i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus-1 DOWNTO 0);
SIGNAL unb2b_board_ring_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL unb2b_board_ring_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_ring-1 DOWNTO 0);
@@ -237,64 +286,106 @@ ARCHITECTURE str OF top IS
SIGNAL i_kernel_rst : STD_LOGIC;
-- OpenCL kernel
- SIGNAL board_kernel_clk_clk : std_logic;
- SIGNAL board_kernel_clk2x_clk : std_logic;
- SIGNAL board_kernel_reset_reset_n : std_logic;
- SIGNAL board_kernel_reset_reset_n_in : std_logic;
+ SIGNAL board_kernel_clk_clk : std_logic;
+ SIGNAL board_kernel_clk2x_clk : std_logic;
+ SIGNAL board_kernel_reset_reset_n : std_logic;
+ SIGNAL board_kernel_reset_reset_n_in : std_logic;
- SIGNAL board_kernel_cra_waitrequest : std_logic;
- SIGNAL board_kernel_cra_readdata : std_logic_vector(63 downto 0);
- SIGNAL board_kernel_cra_readdatavalid : std_logic;
- SIGNAL board_kernel_cra_burstcount : std_logic_vector(0 downto 0);
- SIGNAL board_kernel_cra_writedata : std_logic_vector(63 downto 0);
- SIGNAL board_kernel_cra_address : std_logic_vector(29 downto 0);
- SIGNAL board_kernel_cra_write : std_logic;
- SIGNAL board_kernel_cra_read : std_logic;
- SIGNAL board_kernel_cra_byteenable : std_logic_vector(7 downto 0);
- SIGNAL board_kernel_cra_debugaccess : std_logic;
-
- SIGNAL board_kernel_irq_irq : std_logic_vector(0 downto 0);
-
- SIGNAL board_kernel_register_mem_address : std_logic_vector(6 downto 0) := (others => '0'); -- address
- SIGNAL board_kernel_register_mem_clken : std_logic := '0'; -- clken
- SIGNAL board_kernel_register_mem_chipselect : std_logic := '0'; -- chipselect
- SIGNAL board_kernel_register_mem_write : std_logic := '0'; -- write
- SIGNAL board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata
- SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata
- SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable
-
- SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_tx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
- SIGNAL ta2_unb2b_10GbE_ring_rx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
-
- SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
- SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi;
- SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso;
- SIGNAL ta2_unb2b_mm_io_src_out : t_dp_sosi;
- SIGNAL ta2_unb2b_mm_io_src_in : t_dp_siso;
-
- SIGNAL from_lane_sosi : t_dp_sosi;
- SIGNAL from_lane_siso : t_dp_siso;
- SIGNAL to_lane_sosi : t_dp_sosi;
- SIGNAL to_lane_siso : t_dp_siso;
-
- SIGNAL kernel_from_lane_sosi : t_dp_sosi;
- SIGNAL kernel_from_lane_siso : t_dp_siso;
- SIGNAL kernel_to_lane_sosi : t_dp_sosi;
- SIGNAL kernel_to_lane_siso : t_dp_siso;
-
-
+ SIGNAL board_kernel_cra_waitrequest : std_logic;
+ SIGNAL board_kernel_cra_readdata : std_logic_vector(63 downto 0);
+ SIGNAL board_kernel_cra_readdatavalid : std_logic;
+ SIGNAL board_kernel_cra_burstcount : std_logic_vector(0 downto 0);
+ SIGNAL board_kernel_cra_writedata : std_logic_vector(63 downto 0);
+ SIGNAL board_kernel_cra_address : std_logic_vector(29 downto 0);
+ SIGNAL board_kernel_cra_write : std_logic;
+ SIGNAL board_kernel_cra_read : std_logic;
+ SIGNAL board_kernel_cra_byteenable : std_logic_vector(7 downto 0);
+ SIGNAL board_kernel_cra_debugaccess : std_logic;
+
+ SIGNAL board_kernel_irq_irq : std_logic_vector(0 downto 0);
+
+ SIGNAL board_kernel_register_mem_address : std_logic_vector(6 downto 0) := (others => '0'); -- address
+ SIGNAL board_kernel_register_mem_clken : std_logic := '0'; -- clken
+ SIGNAL board_kernel_register_mem_chipselect : std_logic := '0'; -- chipselect
+ SIGNAL board_kernel_register_mem_write : std_logic := '0'; -- write
+ SIGNAL board_kernel_register_mem_readdata : std_logic_vector(255 downto 0); -- readdata
+ SIGNAL board_kernel_register_mem_writedata : std_logic_vector(255 downto 0) := (others => '0'); -- writedata
+ SIGNAL board_kernel_register_mem_byteenable : std_logic_vector(31 downto 0) := (others => '0'); -- byteenable
+
+ SIGNAL ta2_unb2b_10GbE_src_out_arr : t_dp_sosi_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_src_in_arr : t_dp_siso_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_snk_out_arr : t_dp_siso_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_snk_in_arr : t_dp_sosi_arr(c_max_nof_mac-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_tx_serial_r : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
+ SIGNAL ta2_unb2b_10GbE_rx_serial_r : STD_LOGIC_VECTOR(c_max_nof_mac -1 DOWNTO 0);
+
+ SIGNAL ta2_unb2b_10GbE_ring_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+
+ SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_qsfp_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL ta2_unb2b_mm_io_snk_in : t_dp_sosi;
+ SIGNAL ta2_unb2b_mm_io_snk_out : t_dp_siso;
+ SIGNAL ta2_unb2b_mm_io_src_out : t_dp_sosi;
+ SIGNAL ta2_unb2b_mm_io_src_in : t_dp_siso;
+
+ SIGNAL from_lane_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL from_lane_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL to_lane_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL to_lane_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL kernel_from_lane_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL kernel_from_lane_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL kernel_to_lane_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL kernel_to_lane_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL kernel_rx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL kernel_rx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL kernel_tx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL kernel_tx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL rx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL rx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL tx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL tx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL dp_demux_rx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_demux_rx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL dp_demux_tx_monitor_sosi_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_demux_tx_monitor_siso_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL rx_monitor_sosi_2arr : t_dp_sosi_rx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_sosi_rst));
+ SIGNAL rx_monitor_siso_2arr : t_dp_siso_rx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_siso_rdy));
+ SIGNAL tx_monitor_sosi_2arr : t_dp_sosi_tx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_sosi_rst));
+ SIGNAL tx_monitor_siso_2arr : t_dp_siso_tx_monitor_2arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => (OTHERS => c_dp_siso_rdy));
+
+ SIGNAL local_sosi_arr : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL local_siso_arr : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL dp_xonoff_bg_sosi_arr : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_xonoff_bg_siso_arr : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL dp_xonoff_from_lane_sosi_arr : t_dp_sosi_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_xonoff_from_lane_siso_arr : t_dp_siso_arr(g_nof_lanes-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+
+ SIGNAL mux_snk_out_2arr_2 : t_dp_siso_2arr_2(g_nof_lanes-1 DOWNTO 0);
+ SIGNAL mux_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_lanes-1 DOWNTO 0);
+
+ SIGNAL bs_sosi : t_dp_sosi;
+ SIGNAL kernel_bs_sosi : t_dp_sosi;
+
+ SIGNAL gn_index : NATURAL := 0;
+ SIGNAL this_rn_id : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ SIGNAL sdp_info : t_sdp_info := c_sdp_info_rst;
BEGIN
@@ -360,85 +451,93 @@ BEGIN
RING_0_TX <= i_RING_TX(0);
RING_1_TX <= i_RING_TX(1);
- u_ring_io : ENTITY unb2b_board_lib.unb2b_board_ring_io
+ gen_wire_bus : FOR i IN 0 TO c_nof_ring_bus-1 GENERATE
+ gen_wire_signals : FOR j IN 0 TO c_ring_bus_w-1 GENERATE
+
+ i_RING_TX(i)(j) <= unb2b_board_ring_io_serial_tx_arr(i*c_ring_bus_w + j);
+ unb2b_board_ring_io_serial_rx_arr(i*c_ring_bus_w + j) <= i_RING_RX(i)(j);
+
+ END GENERATE;
+ END GENERATE;
+
+ --------
+ -- PLL
+ --------
+ u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP (
- g_nof_ring_bus => c_nof_ring_bus
+ g_technology => c_tech_arria10_e1sg
)
PORT MAP (
- serial_tx_arr => unb2b_board_ring_io_serial_tx_arr,
- serial_rx_arr => unb2b_board_ring_io_serial_rx_arr,
- RING_RX => i_RING_RX,
- RING_TX => i_RING_TX
+ refclk_644 => SA_CLK,
+ rst_in => mm_rst,
+ clk_156 => clk_156,
+ clk_312 => clk_312,
+ rst_156 => rst_156,
+ rst_312 => OPEN
);
----------
-- 10GbE
----------
- -- Map [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] -> [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3]
- gen_ring_lanes : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
- unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
- unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
+ -- For the indexing of the lanes we would like to have all even indices (0, 2, 4, 6) to receive from the left (RING_RX_0) and transmit to the right (RING_TX_1).
+ -- For the odd indices it should be the other way around, from RING_RX_1 to RING_TX_0. Therefore we need to rewire those signals as follows:
+ -- For receiving, instead of the array [0,0; 0,1; 0,2; 0,3; 1,0; 1,1; 1,2; 1,3] we need the array [0,0; 1,0; 0,1; 1,1; 0,2; 1,2; 0,3; 1,3] where each element is (RING bus index, stream index of that bus).
+ -- Because all of all the RING busses are concatenated into one array we can do the following:
+ -- Rewire [0, 1, 2, 3, 4, 5, 6, 7] to [0, 4, 1, 5, 2, 6, 3, 7]. So now we have the even indices containing the interfaces from RING_0 (receive from the left)
+ -- and the odd indices containing RING_1 (receive from the right).
+ -- For transmitting we need to have the even indices containing RING_1 (transmit to the right) and the odd having RING_0 (transmit to the left)
+ gen_ring_lanes : FOR I IN 0 TO c_ring_bus_w -1 GENERATE
+ -- RX side
+ ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I) <= ta2_unb2b_10GbE_ring_src_out_arr(I);
+ ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_src_out_arr(I+c_ring_bus_w);
+ ta2_unb2b_10GbE_ring_src_in_arr(I) <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I);
+ ta2_unb2b_10GbE_ring_src_in_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I+1);
+ -- TX side
+ ta2_unb2b_10GbE_ring_snk_in_arr(I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
+ ta2_unb2b_10GbE_ring_snk_in_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
+ ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_out_arr(I);
+ ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_out_arr(I+c_ring_bus_w);
END GENERATE;
+ -- Wire 8 ring and 4 qsfp to one array of 12 10GbE
+ ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
+ ta2_unb2b_10GbE_snk_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_snk_in_arr;
+ ta2_unb2b_10GbE_qsfp_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+
+ ta2_unb2b_10GbE_qsfp_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_src_in_arr;
+ ta2_unb2b_10GbE_src_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_src_in_arr;
+
+ ta2_unb2b_10GbE_rx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr;
+ ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= unb2b_board_ring_io_serial_rx_arr;
+ unb2b_board_front_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0);
+ unb2b_board_ring_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
- -- tr_10GbE for RING
- u_ta2_unb2b_10GbE_ring : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
+ -- tr_10GbE
+ u_ta2_unb2b_10GbE : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
GENERIC MAP (
- g_nof_mac => c_nof_10GbE_ring_IP
+ g_nof_mac => c_max_nof_mac,
+ g_use_err => TRUE,
+ g_use_pll => TRUE
)
PORT MAP (
mm_clk => '0', --mm_clk,
mm_rst => mm_rst,
clk_ref_r => SA_CLK,
-
- tx_serial_r => ta2_unb2b_10GbE_ring_tx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0),
- rx_serial_r => ta2_unb2b_10GbE_ring_rx_serial_r(c_nof_10GbE_ring_IP-1 DOWNTO 0),
-
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_10GbE_ring_src_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
- src_in_arr => ta2_unb2b_10GbE_ring_src_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
- snk_out_arr => ta2_unb2b_10GbE_ring_snk_out_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0),
- snk_in_arr => ta2_unb2b_10GbE_ring_snk_in_arr(c_nof_10GbE_ring_IP-1 DOWNTO 0)
- );
-
- -- Map to kernel channel, swapping every two elements of the sink.
- ta2_unb2b_10GbE_ring_ch_src_out_arr <= ta2_unb2b_10GbE_ring_src_out_arr;
- ta2_unb2b_10GbE_ring_src_in_arr <= ta2_unb2b_10GbE_ring_ch_src_in_arr;
- gen_ring_ch : FOR I IN 0 TO c_nof_streams_ring/2 -1 GENERATE
- ta2_unb2b_10GbE_ring_snk_in_arr(2*I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
- ta2_unb2b_10GbE_ring_snk_in_arr(2*I+1) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
- ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I);
- ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_out_arr(2*I+1);
- END GENERATE;
-
- -- Front QSFP 0 RX/TX 10GbE Interface
-
- -- tr_10GbE for QSFP
- u_ta2_unb2b_10GbE_qsfp : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
- GENERIC MAP (
- g_nof_mac => c_nof_10GbE_qsfp_IP
- )
- PORT MAP (
- mm_clk => '0', --mm_clk,
- mm_rst => mm_rst,
-
- clk_ref_r => SA_CLK,
-
- tx_serial_r => unb2b_board_front_io_serial_tx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
- rx_serial_r => unb2b_board_front_io_serial_rx_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
+ tx_serial_r => ta2_unb2b_10GbE_tx_serial_r,
+ rx_serial_r => ta2_unb2b_10GbE_rx_serial_r,
kernel_clk => board_kernel_clk_clk,
kernel_reset => i_kernel_rst,
- src_out_arr => ta2_unb2b_10GbE_qsfp_src_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
- src_in_arr => ta2_unb2b_10GbE_qsfp_src_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
- snk_out_arr => ta2_unb2b_10GbE_qsfp_snk_out_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0),
- snk_in_arr => ta2_unb2b_10GbE_qsfp_snk_in_arr(c_nof_10GbE_qsfp_IP-1 DOWNTO 0)
+ src_out_arr => ta2_unb2b_10GbE_src_out_arr,
+ src_in_arr => ta2_unb2b_10GbE_src_in_arr,
+ snk_out_arr => ta2_unb2b_10GbE_snk_out_arr,
+ snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
);
--------------------------------------
@@ -462,34 +561,233 @@ BEGIN
snk_out => ta2_unb2b_mm_io_snk_out,
src_out => ta2_unb2b_mm_io_src_out,
src_in => ta2_unb2b_mm_io_src_in
-
);
-----------------------------------------------------------------------------
-- kernel clock crossing for from/to lane sosi
-----------------------------------------------------------------------------
- u_ta2_channel_cross : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+ u_ta2_channel_cross_lanes : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+ GENERIC MAP(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => TRUE,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_use_channel => TRUE
+ )
+ PORT MAP(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+ dp_src_out_arr => from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+ dp_src_in_arr => from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ dp_snk_out_arr => to_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ dp_snk_in_arr => to_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_src_out_arr => kernel_to_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+ kernel_src_in_arr => kernel_to_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ kernel_snk_out_arr => kernel_from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0)
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- kernel clock crossing for bs sosi
+ -----------------------------------------------------------------------------
+ u_ta2_channel_cross_bs_sosi : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => 1,
- g_nof_bytes => 8,
- g_reverse_bytes => TRUE
+ g_nof_bytes => c_word_sz,
+ g_reverse_bytes => TRUE,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE
)
PORT MAP(
- dp_clk => st_clk,
- dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ dp_snk_in_arr(0) => bs_sosi,
+ kernel_src_out_arr(0) => kernel_bs_sosi
+ );
- dp_src_out_arr(0) => from_lane_sosi,
- dp_src_in_arr(0) => from_lane_siso,
- dp_snk_out_arr(0) => to_lane_siso,
- dp_snk_in_arr(0) => to_lane_sosi,
+ -----------------------------------------------------------------------------
+ -- kernel clock crossing for rx_monitors
+ -----------------------------------------------------------------------------
+ u_ta2_channel_cross_rx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+ GENERIC MAP(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => TRUE,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_use_channel => TRUE
+ )
+ PORT MAP(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => rx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+ dp_src_in_arr => rx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0),
- kernel_clk => board_kernel_clk_clk,
- kernel_reset => i_kernel_rst,
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
- kernel_src_out_arr(0) => kernel_to_lane_sosi,
- kernel_src_in_arr(0) => kernel_to_lane_siso,
- kernel_snk_out_arr(0) => kernel_from_lane_siso,
- kernel_snk_in_arr(0) => kernel_from_lane_sosi
+ kernel_snk_out_arr => kernel_rx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ kernel_snk_in_arr => kernel_rx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0)
+ );
+
+ -----------------------------------------------------------------------------
+ -- kernel clock crossing for tx_monitors
+ -----------------------------------------------------------------------------
+ gen_tx_mon_sim_wires: IF g_sim = TRUE GENERATE -- bypass OpenCL kernel in simulation
+ kernel_tx_monitor_sosi_arr <= kernel_to_lane_sosi_arr;
+ kernel_to_lane_siso_arr <= kernel_tx_monitor_siso_arr;
+ END GENERATE;
+
+ u_ta2_channel_cross_tx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
+ GENERIC MAP(
+ g_nof_streams => g_nof_lanes,
+ g_nof_bytes => c_longword_sz,
+ g_reverse_bytes => TRUE,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_use_channel => TRUE
+ )
+ PORT MAP(
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ dp_src_out_arr => tx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+ dp_src_in_arr => tx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0),
+
+ kernel_clk => board_kernel_clk_clk,
+ kernel_reset => i_kernel_rst,
+
+ kernel_snk_out_arr => kernel_tx_monitor_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ kernel_snk_in_arr => kernel_tx_monitor_sosi_arr(g_nof_lanes-1 DOWNTO 0)
+ );
+
+ rx_monitor_siso_arr <= dp_demux_rx_monitor_siso_arr;
+ tx_monitor_siso_arr <= dp_demux_tx_monitor_siso_arr;
+ p_calc_source_rn : PROCESS(tx_monitor_sosi_arr, rx_monitor_sosi_arr)
+ BEGIN
+ dp_demux_rx_monitor_sosi_arr <= rx_monitor_sosi_arr;
+ dp_demux_tx_monitor_sosi_arr <= tx_monitor_sosi_arr;
+
+ FOR I IN 0 TO g_nof_lanes-1 LOOP
+ dp_demux_rx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(rx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2)); -- Use (I+1) MOD 2 to get 1 if I is even and 0 if I is odd
+ dp_demux_tx_monitor_sosi_arr(I).channel <= nof_hops_to_source_rn(tx_monitor_sosi_arr(I).channel, this_rn_id, sdp_info.N_rn, ((I+1) MOD 2));
+ END LOOP;
+ END PROCESS;
+
+ gen_monitors : FOR I IN 0 TO g_nof_lanes-1 GENERATE
+ -----------------------------------------------------------------------------
+ -- demux rx_monitor inputs
+ -----------------------------------------------------------------------------
+ u_dp_demux_rx_monitor : ENTITY dp_lib.dp_demux
+ GENERIC MAP(
+ g_nof_output => g_nof_rx_monitors,
+ g_sel_ctrl_invert => TRUE
+ )
+ PORT MAP(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_demux_rx_monitor_siso_arr(I),
+ snk_in => dp_demux_rx_monitor_sosi_arr(I),
+
+ src_in_arr => rx_monitor_siso_2arr(I),
+ src_out_arr => rx_monitor_sosi_2arr(I)
+ );
+ -----------------------------------------------------------------------------
+ -- rx_monitors
+ -----------------------------------------------------------------------------
+ u_mms_dp_bsn_monitor_v2_rx : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+ GENERIC MAP(
+ g_nof_streams => g_nof_rx_monitors
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_rx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_rx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => rx_monitor_siso_2arr(I),
+ in_sosi_arr => rx_monitor_sosi_2arr(I)
+ );
+
+ -----------------------------------------------------------------------------
+ -- demux tx_monitor inputs
+ -----------------------------------------------------------------------------
+ u_dp_demux_tx_monitor : ENTITY dp_lib.dp_demux
+ GENERIC MAP(
+ g_nof_output => g_nof_tx_monitors,
+ g_sel_ctrl_invert => TRUE
+ )
+ PORT MAP(
+ rst => st_rst,
+ clk => st_clk,
+
+ snk_out => dp_demux_tx_monitor_siso_arr(I),
+ snk_in => dp_demux_tx_monitor_sosi_arr(I),
+
+ src_in_arr => tx_monitor_siso_2arr(I),
+ src_out_arr => tx_monitor_sosi_2arr(I)
+ );
+
+ -----------------------------------------------------------------------------
+ -- tx_monitors
+ -----------------------------------------------------------------------------
+ u_mms_dp_bsn_monitor_v2_tx : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+ GENERIC MAP(
+ g_nof_streams => g_nof_tx_monitors
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_tx_mosi_arr(I),
+ reg_miso => reg_bsn_monitor_v2_tx_miso_arr(I),
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ ref_sync => bs_sosi.sync,
+
+ in_siso_arr => tx_monitor_siso_2arr(I),
+ in_sosi_arr => tx_monitor_sosi_2arr(I)
+ );
+ END GENERATE;
+
+ u_common_mem_mux_rx_monitors : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_rx_monitors)+3
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_rx_mosi,
+ miso => reg_bsn_monitor_v2_rx_miso,
+ mosi_arr => reg_bsn_monitor_v2_rx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_miso_arr
+ );
+
+ u_common_mem_mux_tx_monitors : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_lanes,
+ g_mult_addr_w => ceil_log2(g_nof_tx_monitors)+3
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_tx_mosi,
+ miso => reg_bsn_monitor_v2_tx_miso,
+ mosi_arr => reg_bsn_monitor_v2_tx_mosi_arr,
+ miso_arr => reg_bsn_monitor_v2_tx_miso_arr
);
-----------------------------------------------------------------------------
@@ -497,9 +795,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
- g_use_usr_input => TRUE,
- g_use_bg => TRUE,
- g_nof_streams => 1,
+ g_nof_streams => g_nof_lanes,
g_use_bg_buffer_ram => TRUE,
g_buf_dat_w => 32, --BG is limited to 32 bits data
g_buf_addr_w => 7,
@@ -520,15 +816,129 @@ BEGIN
ram_bg_data_miso => ram_bg_data_miso,
-- ST interface
- usr_siso_arr(0) => from_lane_siso,
- usr_sosi_arr(0) => from_lane_sosi,
- out_siso_arr(0) => to_lane_siso,
- out_sosi_arr(0) => to_lane_sosi
+ out_siso_arr => local_siso_arr,
+ out_sosi_arr => local_sosi_arr
+ );
+
+ bs_sosi <= local_sosi_arr(0);
+
+ u_mms_dp_xonoff_bg : ENTITY dp_lib.mms_dp_xonoff
+ GENERIC MAP(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => FALSE,
+ g_default_value => '0'
+ )
+ PORT MAP(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_bg_mosi,
+ reg_miso => reg_dp_xonoff_bg_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => local_siso_arr,
+ snk_in_arr => local_sosi_arr,
+ -- ST source
+ src_in_arr => dp_xonoff_bg_siso_arr,
+ src_out_arr => dp_xonoff_bg_sosi_arr
+ );
+
+ u_mms_dp_xonoff_from_lane : ENTITY dp_lib.mms_dp_xonoff
+ GENERIC MAP(
+ g_nof_streams => g_nof_lanes,
+ g_combine_streams => FALSE,
+ g_default_value => '1'
+ )
+ PORT MAP(
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_xonoff_from_lane_mosi,
+ reg_miso => reg_dp_xonoff_from_lane_miso,
+
+ -- Streaming clock domain
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+
+ -- ST sinks
+ snk_out_arr => from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ snk_in_arr => from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0),
+ -- ST source
+ src_in_arr => dp_xonoff_from_lane_siso_arr(g_nof_lanes-1 DOWNTO 0),
+ src_out_arr => dp_xonoff_from_lane_sosi_arr(g_nof_lanes-1 DOWNTO 0)
+ );
+
+ gen_streams : FOR I IN 0 TO g_nof_lanes-1 GENERATE
+ -- Multiplex the inputs:
+ -- . [0] = from lane sosi
+ -- . [1] = BG
+ dp_xonoff_from_lane_siso_arr(I) <= mux_snk_out_2arr_2(I)(0);
+ dp_xonoff_bg_siso_arr(I) <= mux_snk_out_2arr_2(I)(1);
+
+ mux_snk_in_2arr_2(I)(0) <= dp_xonoff_from_lane_sosi_arr(I);
+ mux_snk_in_2arr_2(I)(1) <= dp_xonoff_bg_sosi_arr(I);
+
+ u_dp_mux : ENTITY dp_lib.dp_mux
+ GENERIC MAP (
+ g_technology => g_technology,
+ -- MUX
+ g_mode => 0,
+ g_nof_input => 2,
+ g_append_channel_lo => FALSE,
+ g_sel_ctrl_invert => TRUE, -- Use default FALSE when stream array IO are indexed (0 TO g_nof_input-1), else use TRUE when indexed (g_nof_input-1 DOWNTO 0)
+ -- Input FIFO
+ g_use_fifo => FALSE,
+ g_fifo_size => array_init(1024, 2), -- must match g_nof_input, even when g_use_fifo=FALSE
+ g_fifo_fill => array_init( 0, 2) -- must match g_nof_input, even when g_use_fifo=FALSE
+ )
+ PORT MAP (
+ rst => st_rst,
+ clk => st_clk,
+ -- ST sinks
+ snk_out_arr => mux_snk_out_2arr_2(I), -- [c_mux_nof_input-1:0]
+ snk_in_arr => mux_snk_in_2arr_2(I), -- [c_mux_nof_input-1:0]
+ -- ST source
+ src_in => to_lane_siso_arr(I),
+ src_out => to_lane_sosi_arr(I)
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- SDP Info register
+ -----------------------------------------------------------------------------
+ gn_index <= TO_UINT(ID(c_sdp_W_gn_id-1 DOWNTO 0));
+ this_rn_id <= TO_UVEC(gn_index - TO_UINT(sdp_info.O_rn), c_sdp_W_gn_id);
+ u_sdp_info : ENTITY lofar2_sdp_lib.sdp_info
+ PORT MAP(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+
+ dp_clk => st_clk,
+ dp_rst => st_rst,
+
+ reg_mosi => reg_sdp_info_mosi,
+ reg_miso => reg_sdp_info_miso,
+
+ -- inputs from other blocks
+ gn_index => gn_index,
+ f_adc => '1',
+ fsub_type => '0',
+
+ -- sdp info
+ sdp_info => sdp_info
);
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
+ gen_opencl: IF g_sim = FALSE GENERATE
freeze_wrapper_inst : freeze_wrapper
PORT MAP(
board_kernel_clk_clk => board_kernel_clk_clk,
@@ -554,110 +964,239 @@ BEGIN
board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
- board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
board_kernel_stream_src_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(0).valid,
board_kernel_stream_snk_10GbE_qsfp_0_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(0).ready,
- board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(1).valid,
board_kernel_stream_src_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_1_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_1_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(1).valid,
board_kernel_stream_snk_10GbE_qsfp_1_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(1).ready,
- board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(2).valid,
board_kernel_stream_src_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_2_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_2_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(2).valid,
board_kernel_stream_snk_10GbE_qsfp_2_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(2).ready,
- board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(71 DOWNTO 0),
+ board_kernel_stream_src_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(3).valid,
board_kernel_stream_src_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(71 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_qsfp_3_data => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_10GbE_qsfp_3_valid => ta2_unb2b_10GbE_qsfp_snk_in_arr(3).valid,
board_kernel_stream_snk_10GbE_qsfp_3_ready => ta2_unb2b_10GbE_qsfp_snk_out_arr(3).ready,
- board_kernel_stream_src_lane_data => kernel_to_lane_sosi.data(71 DOWNTO 0),
- board_kernel_stream_src_lane_valid => kernel_to_lane_sosi.valid,
- board_kernel_stream_src_lane_ready => kernel_to_lane_siso.ready,
- board_kernel_stream_snk_lane_data => kernel_from_lane_sosi.data(71 DOWNTO 0),
- board_kernel_stream_snk_lane_valid => kernel_from_lane_sosi.valid,
- board_kernel_stream_snk_lane_ready => kernel_from_lane_siso.ready,
-
- board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(71 DOWNTO 0),
+ board_kernel_stream_src_lane_0_data => kernel_to_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_0_valid => kernel_to_lane_sosi_arr(0).valid,
+ board_kernel_stream_src_lane_0_ready => kernel_to_lane_siso_arr(0).ready,
+ board_kernel_stream_snk_lane_0_data => kernel_from_lane_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_0_valid => kernel_from_lane_sosi_arr(0).valid,
+ board_kernel_stream_snk_lane_0_ready => kernel_from_lane_siso_arr(0).ready,
+
+ board_kernel_stream_src_lane_1_data => kernel_to_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_1_valid => kernel_to_lane_sosi_arr(1).valid,
+ board_kernel_stream_src_lane_1_ready => kernel_to_lane_siso_arr(1).ready,
+ board_kernel_stream_snk_lane_1_data => kernel_from_lane_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_1_valid => kernel_from_lane_sosi_arr(1).valid,
+ board_kernel_stream_snk_lane_1_ready => kernel_from_lane_siso_arr(1).ready,
+
+ board_kernel_stream_src_lane_2_data => kernel_to_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_2_valid => kernel_to_lane_sosi_arr(2).valid,
+ board_kernel_stream_src_lane_2_ready => kernel_to_lane_siso_arr(2).ready,
+ board_kernel_stream_snk_lane_2_data => kernel_from_lane_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_2_valid => kernel_from_lane_sosi_arr(2).valid,
+ board_kernel_stream_snk_lane_2_ready => kernel_from_lane_siso_arr(2).ready,
+
+ board_kernel_stream_src_lane_3_data => kernel_to_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_3_valid => kernel_to_lane_sosi_arr(3).valid,
+ board_kernel_stream_src_lane_3_ready => kernel_to_lane_siso_arr(3).ready,
+ board_kernel_stream_snk_lane_3_data => kernel_from_lane_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_3_valid => kernel_from_lane_sosi_arr(3).valid,
+ board_kernel_stream_snk_lane_3_ready => kernel_from_lane_siso_arr(3).ready,
+
+ board_kernel_stream_src_lane_4_data => kernel_to_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_4_valid => kernel_to_lane_sosi_arr(4).valid,
+ board_kernel_stream_src_lane_4_ready => kernel_to_lane_siso_arr(4).ready,
+ board_kernel_stream_snk_lane_4_data => kernel_from_lane_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_4_valid => kernel_from_lane_sosi_arr(4).valid,
+ board_kernel_stream_snk_lane_4_ready => kernel_from_lane_siso_arr(4).ready,
+
+ board_kernel_stream_src_lane_5_data => kernel_to_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_5_valid => kernel_to_lane_sosi_arr(5).valid,
+ board_kernel_stream_src_lane_5_ready => kernel_to_lane_siso_arr(5).ready,
+ board_kernel_stream_snk_lane_5_data => kernel_from_lane_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_5_valid => kernel_from_lane_sosi_arr(5).valid,
+ board_kernel_stream_snk_lane_5_ready => kernel_from_lane_siso_arr(5).ready,
+
+ board_kernel_stream_src_lane_6_data => kernel_to_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_6_valid => kernel_to_lane_sosi_arr(6).valid,
+ board_kernel_stream_src_lane_6_ready => kernel_to_lane_siso_arr(6).ready,
+ board_kernel_stream_snk_lane_6_data => kernel_from_lane_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_6_valid => kernel_from_lane_sosi_arr(6).valid,
+ board_kernel_stream_snk_lane_6_ready => kernel_from_lane_siso_arr(6).ready,
+
+ board_kernel_stream_src_lane_7_data => kernel_to_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_lane_7_valid => kernel_to_lane_sosi_arr(7).valid,
+ board_kernel_stream_src_lane_7_ready => kernel_to_lane_siso_arr(7).ready,
+ board_kernel_stream_snk_lane_7_data => kernel_from_lane_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_lane_7_valid => kernel_from_lane_sosi_arr(7).valid,
+ board_kernel_stream_snk_lane_7_ready => kernel_from_lane_siso_arr(7).ready,
+
+ board_kernel_stream_snk_rx_monitor_0_data => kernel_rx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_0_valid => kernel_rx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_rx_monitor_0_ready => kernel_rx_monitor_siso_arr(0).ready,
+ board_kernel_stream_snk_tx_monitor_0_data => kernel_tx_monitor_sosi_arr(0).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_0_valid => kernel_tx_monitor_sosi_arr(0).valid,
+ board_kernel_stream_snk_tx_monitor_0_ready => kernel_tx_monitor_siso_arr(0).ready,
+
+ board_kernel_stream_snk_rx_monitor_1_data => kernel_rx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_1_valid => kernel_rx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_rx_monitor_1_ready => kernel_rx_monitor_siso_arr(1).ready,
+ board_kernel_stream_snk_tx_monitor_1_data => kernel_tx_monitor_sosi_arr(1).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_1_valid => kernel_tx_monitor_sosi_arr(1).valid,
+ board_kernel_stream_snk_tx_monitor_1_ready => kernel_tx_monitor_siso_arr(1).ready,
+
+ board_kernel_stream_snk_rx_monitor_2_data => kernel_rx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_2_valid => kernel_rx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_rx_monitor_2_ready => kernel_rx_monitor_siso_arr(2).ready,
+ board_kernel_stream_snk_tx_monitor_2_data => kernel_tx_monitor_sosi_arr(2).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_2_valid => kernel_tx_monitor_sosi_arr(2).valid,
+ board_kernel_stream_snk_tx_monitor_2_ready => kernel_tx_monitor_siso_arr(2).ready,
+
+ board_kernel_stream_snk_rx_monitor_3_data => kernel_rx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_3_valid => kernel_rx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_rx_monitor_3_ready => kernel_rx_monitor_siso_arr(3).ready,
+ board_kernel_stream_snk_tx_monitor_3_data => kernel_tx_monitor_sosi_arr(3).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_3_valid => kernel_tx_monitor_sosi_arr(3).valid,
+ board_kernel_stream_snk_tx_monitor_3_ready => kernel_tx_monitor_siso_arr(3).ready,
+
+ board_kernel_stream_snk_rx_monitor_4_data => kernel_rx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_4_valid => kernel_rx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_rx_monitor_4_ready => kernel_rx_monitor_siso_arr(4).ready,
+ board_kernel_stream_snk_tx_monitor_4_data => kernel_tx_monitor_sosi_arr(4).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_4_valid => kernel_tx_monitor_sosi_arr(4).valid,
+ board_kernel_stream_snk_tx_monitor_4_ready => kernel_tx_monitor_siso_arr(4).ready,
+
+ board_kernel_stream_snk_rx_monitor_5_data => kernel_rx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_5_valid => kernel_rx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_rx_monitor_5_ready => kernel_rx_monitor_siso_arr(5).ready,
+ board_kernel_stream_snk_tx_monitor_5_data => kernel_tx_monitor_sosi_arr(5).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_5_valid => kernel_tx_monitor_sosi_arr(5).valid,
+ board_kernel_stream_snk_tx_monitor_5_ready => kernel_tx_monitor_siso_arr(5).ready,
+
+ board_kernel_stream_snk_rx_monitor_6_data => kernel_rx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_6_valid => kernel_rx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_rx_monitor_6_ready => kernel_rx_monitor_siso_arr(6).ready,
+ board_kernel_stream_snk_tx_monitor_6_data => kernel_tx_monitor_sosi_arr(6).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_6_valid => kernel_tx_monitor_sosi_arr(6).valid,
+ board_kernel_stream_snk_tx_monitor_6_ready => kernel_tx_monitor_siso_arr(6).ready,
+
+ board_kernel_stream_snk_rx_monitor_7_data => kernel_rx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_rx_monitor_7_valid => kernel_rx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_rx_monitor_7_ready => kernel_rx_monitor_siso_arr(7).ready,
+ board_kernel_stream_snk_tx_monitor_7_data => kernel_tx_monitor_sosi_arr(7).data(c_kernel_lane_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_tx_monitor_7_valid => kernel_tx_monitor_sosi_arr(7).valid,
+ board_kernel_stream_snk_tx_monitor_7_ready => kernel_tx_monitor_siso_arr(7).ready,
+
+ board_kernel_stream_src_bs_data => kernel_bs_sosi.data(c_kernel_bs_sosi_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_bs_valid => kernel_bs_sosi.valid,
+ board_kernel_stream_src_bs_ready => OPEN,
+
+ board_kernel_stream_src_mm_io_data => ta2_unb2b_mm_io_src_out.data(c_kernel_mm_io_mosi_channel_w-1 DOWNTO 0),
board_kernel_stream_src_mm_io_valid => ta2_unb2b_mm_io_src_out.valid,
board_kernel_stream_src_mm_io_ready => ta2_unb2b_mm_io_src_in.ready,
- board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(31 DOWNTO 0),
+ board_kernel_stream_snk_mm_io_data => ta2_unb2b_mm_io_snk_in.data(c_kernel_mm_io_miso_channel_w-1 DOWNTO 0),
board_kernel_stream_snk_mm_io_valid => ta2_unb2b_mm_io_snk_in.valid,
board_kernel_stream_snk_mm_io_ready => ta2_unb2b_mm_io_snk_out.ready
);
- i_reset_n <= NOT mm_rst;
- i_kernel_rst <= NOT board_kernel_reset_reset_n;
+ i_kernel_rst <= NOT board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
+ END GENERATE;
+
+ gen_sim: IF g_sim = TRUE GENERATE
+ i_kernel_rst <= NOT i_reset_n;
+ board_kernel_clk_clk <= st_clk;
+
+ u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_dp_xonoff_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+ u_mm_file_reg_dp_xonoff_from_lane: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+ u_mm_file_reg_bsn_monitor_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+ u_mm_file_reg_bsn_monitor_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+ u_mm_file_reg_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, g_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
+ PORT MAP(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+ END GENERATE;
- -- Kernel should start later than BSP
+ i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
+ -- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
+ -- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : ENTITY common_lib.common_areset
GENERIC MAP (
g_rst_level => '0',
@@ -668,8 +1207,7 @@ BEGIN
clk => board_kernel_clk_clk,
out_rst => board_kernel_reset_reset_n_in
);
-
- -----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : ENTITY unb2b_board_lib.ctrl_unb2b_board
@@ -797,6 +1335,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
+ gen_board: IF g_sim = FALSE GENERATE
board_inst : board
PORT MAP (
clk_clk => mm_clk,
@@ -920,7 +1459,19 @@ BEGIN
ram_scrap_write_export => ram_scrap_mosi.wr,
ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_bg_ring_address_export => ram_bg_data_mosi.address(6 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_address_export => reg_bsn_monitor_v2_rx_mosi.address(9 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_read_export => reg_bsn_monitor_v2_rx_mosi.rd,
+ reg_bsn_monitor_v2_rx_readdata_export => reg_bsn_monitor_v2_rx_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_write_export => reg_bsn_monitor_v2_rx_mosi.wr,
+ reg_bsn_monitor_v2_rx_writedata_export => reg_bsn_monitor_v2_rx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_tx_address_export => reg_bsn_monitor_v2_tx_mosi.address(9 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_read_export => reg_bsn_monitor_v2_tx_mosi.rd,
+ reg_bsn_monitor_v2_tx_readdata_export => reg_bsn_monitor_v2_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_tx_write_export => reg_bsn_monitor_v2_tx_mosi.wr,
+ reg_bsn_monitor_v2_tx_writedata_export => reg_bsn_monitor_v2_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ ram_diag_bg_ring_address_export => ram_bg_data_mosi.address(9 DOWNTO 0),
ram_diag_bg_ring_read_export => ram_bg_data_mosi.rd,
ram_diag_bg_ring_readdata_export => ram_bg_data_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_bg_ring_write_export => ram_bg_data_mosi.wr,
@@ -932,6 +1483,24 @@ BEGIN
reg_diag_bg_ring_write_export => reg_bg_ctrl_mosi.wr,
reg_diag_bg_ring_writedata_export => reg_bg_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_bg_address_export => reg_dp_xonoff_bg_mosi.address(2 DOWNTO 0),
+ reg_dp_xonoff_bg_read_export => reg_dp_xonoff_bg_mosi.rd,
+ reg_dp_xonoff_bg_readdata_export => reg_dp_xonoff_bg_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_bg_write_export => reg_dp_xonoff_bg_mosi.wr,
+ reg_dp_xonoff_bg_writedata_export => reg_dp_xonoff_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_xonoff_from_lane_address_export => reg_dp_xonoff_from_lane_mosi.address(2 DOWNTO 0),
+ reg_dp_xonoff_from_lane_read_export => reg_dp_xonoff_from_lane_mosi.rd,
+ reg_dp_xonoff_from_lane_readdata_export => reg_dp_xonoff_from_lane_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_from_lane_write_export => reg_dp_xonoff_from_lane_mosi.wr,
+ reg_dp_xonoff_from_lane_writedata_export => reg_dp_xonoff_from_lane_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+
kernel_cra_waitrequest => board_kernel_cra_waitrequest,
kernel_cra_readdata => board_kernel_cra_readdata,
kernel_cra_readdatavalid => board_kernel_cra_readdatavalid,
@@ -945,13 +1514,13 @@ BEGIN
kernel_irq_irq => board_kernel_irq_irq,
- reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(7 DOWNTO 0),
+ reg_ta2_unb2b_mm_io_address_export => reg_ta2_unb2b_mm_io_mosi.address(c_kernel_regmap_addr_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_read_export => reg_ta2_unb2b_mm_io_mosi.rd,
reg_ta2_unb2b_mm_io_readdata_export => reg_ta2_unb2b_mm_io_miso.rddata(c_word_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_write_export => reg_ta2_unb2b_mm_io_mosi.wr,
reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
);
-
+ END GENERATE;
END str;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index b278ee0e6d25094d175ae0de17993c1a7114999e..4072e277124bc06055f61d9ddca8953b09372594 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -29,173 +29,207 @@ USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE top_components_pkg IS
-
component board is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- kernel_clk_clk : out std_logic; -- clk
- kernel_reset_reset_n : out std_logic; -- reset_n
- kernel_clk2x_clk : out std_logic; -- clk
- kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
- kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
- kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
- kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
- kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
- kernel_cra_address : out std_logic_vector(29 downto 0); -- address
- kernel_cra_write : out std_logic; -- write
- kernel_cra_read : out std_logic; -- read
- kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
- kernel_cra_debugaccess : out std_logic; -- debugaccess
- kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
- kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_diag_bg_ring_reset_export : out std_logic; -- export
- ram_diag_bg_ring_clk_export : out std_logic; -- export
- ram_diag_bg_ring_address_export : out std_logic_vector(6 downto 0); -- export
- ram_diag_bg_ring_write_export : out std_logic; -- export
- ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_bg_ring_read_export : out std_logic; -- export
- ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_bg_ring_reset_export : out std_logic; -- export
- reg_diag_bg_ring_clk_export : out std_logic; -- export
- reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
- reg_diag_bg_ring_write_export : out std_logic; -- export
- reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_bg_ring_read_export : out std_logic; -- export
- reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
- reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
- reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ kernel_clk_clk : out std_logic; -- clk
+ kernel_reset_reset_n : out std_logic; -- reset_n
+ kernel_clk2x_clk : out std_logic; -- clk
+ kernel_cra_waitrequest : in std_logic := 'X'; -- waitrequest
+ kernel_cra_readdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- readdata
+ kernel_cra_readdatavalid : in std_logic := 'X'; -- readdatavalid
+ kernel_cra_burstcount : out std_logic_vector(0 downto 0); -- burstcount
+ kernel_cra_writedata : out std_logic_vector(63 downto 0); -- writedata
+ kernel_cra_address : out std_logic_vector(29 downto 0); -- address
+ kernel_cra_write : out std_logic; -- write
+ kernel_cra_read : out std_logic; -- read
+ kernel_cra_byteenable : out std_logic_vector(7 downto 0); -- byteenable
+ kernel_cra_debugaccess : out std_logic; -- debugaccess
+ kernel_irq_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
+ kernel_interface_sw_reset_in_reset : in std_logic := 'X'; -- reset
+ pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_rx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_tx_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_address_export : out std_logic_vector(9 downto 0); -- export
+ reg_bsn_monitor_v2_tx_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_tx_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_bg_ring_reset_export : out std_logic; -- export
+ ram_diag_bg_ring_clk_export : out std_logic; -- export
+ ram_diag_bg_ring_address_export : out std_logic_vector(9 downto 0); -- export
+ ram_diag_bg_ring_write_export : out std_logic; -- export
+ ram_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_bg_ring_read_export : out std_logic; -- export
+ ram_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_bg_ring_reset_export : out std_logic; -- export
+ reg_diag_bg_ring_clk_export : out std_logic; -- export
+ reg_diag_bg_ring_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_diag_bg_ring_write_export : out std_logic; -- export
+ reg_diag_bg_ring_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_bg_ring_read_export : out std_logic; -- export
+ reg_diag_bg_ring_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_bg_reset_export : out std_logic; -- export
+ reg_dp_xonoff_bg_clk_export : out std_logic; -- export
+ reg_dp_xonoff_bg_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_bg_write_export : out std_logic; -- export
+ reg_dp_xonoff_bg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_bg_read_export : out std_logic; -- export
+ reg_dp_xonoff_bg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_from_lane_reset_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_clk_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_xonoff_from_lane_write_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_from_lane_read_export : out std_logic; -- export
+ reg_dp_xonoff_from_lane_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_reset_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_clk_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_ta2_unb2b_mm_io_write_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ta2_unb2b_mm_io_read_export : out std_logic; -- export
+ reg_ta2_unb2b_mm_io_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ta2_unb2b_mm_io_waitrequest_export : in std_logic := 'X'; -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component board;
@@ -224,96 +258,206 @@ PACKAGE top_components_pkg IS
board_kernel_register_mem_writedata : out std_logic_vector(255 downto 0); -- := (others => 'X'); -- writedata
board_kernel_register_mem_byteenable : out std_logic_vector(31 downto 0); -- := (others => 'X'); -- byteenable
- board_kernel_stream_src_10GbE_ring_0_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_0_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_0_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_0_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_0_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_0_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_0_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_0_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_1_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_1_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_1_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_1_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_1_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_1_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_1_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_1_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_2_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_2_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_2_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_2_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_2_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_2_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_2_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_2_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_3_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_3_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_3_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_3_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_3_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_3_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_3_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_3_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_4_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_4_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_4_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_4_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_4_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_4_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_4_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_4_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_5_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_5_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_5_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_5_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_5_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_5_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_5_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_5_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_6_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_6_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_6_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_6_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_6_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_6_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_6_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_6_ready : in std_logic;
- board_kernel_stream_src_10GbE_ring_7_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_ring_7_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_ring_7_valid : in std_logic;
board_kernel_stream_src_10GbE_ring_7_ready : out std_logic;
- board_kernel_stream_snk_10GbE_ring_7_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_ring_7_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_ring_7_valid : out std_logic;
board_kernel_stream_snk_10GbE_ring_7_ready : in std_logic;
- board_kernel_stream_src_10GbE_qsfp_0_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_qsfp_0_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_qsfp_0_valid : in std_logic;
board_kernel_stream_src_10GbE_qsfp_0_ready : out std_logic;
- board_kernel_stream_snk_10GbE_qsfp_0_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_qsfp_0_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_qsfp_0_valid : out std_logic;
board_kernel_stream_snk_10GbE_qsfp_0_ready : in std_logic;
- board_kernel_stream_src_10GbE_qsfp_1_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_qsfp_1_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_qsfp_1_valid : in std_logic;
board_kernel_stream_src_10GbE_qsfp_1_ready : out std_logic;
- board_kernel_stream_snk_10GbE_qsfp_1_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_qsfp_1_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_qsfp_1_valid : out std_logic;
board_kernel_stream_snk_10GbE_qsfp_1_ready : in std_logic;
- board_kernel_stream_src_10GbE_qsfp_2_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_qsfp_2_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_qsfp_2_valid : in std_logic;
board_kernel_stream_src_10GbE_qsfp_2_ready : out std_logic;
- board_kernel_stream_snk_10GbE_qsfp_2_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_qsfp_2_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_qsfp_2_valid : out std_logic;
board_kernel_stream_snk_10GbE_qsfp_2_ready : in std_logic;
- board_kernel_stream_src_10GbE_qsfp_3_data : in std_logic_vector(71 downto 0);
+ board_kernel_stream_src_10GbE_qsfp_3_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_10GbE_qsfp_3_valid : in std_logic;
board_kernel_stream_src_10GbE_qsfp_3_ready : out std_logic;
- board_kernel_stream_snk_10GbE_qsfp_3_data : out std_logic_vector(71 downto 0);
+ board_kernel_stream_snk_10GbE_qsfp_3_data : out std_logic_vector(103 downto 0);
board_kernel_stream_snk_10GbE_qsfp_3_valid : out std_logic;
board_kernel_stream_snk_10GbE_qsfp_3_ready : in std_logic;
-
- board_kernel_stream_src_lane_data : in std_logic_vector(71 downto 0);
- board_kernel_stream_src_lane_valid : in std_logic;
- board_kernel_stream_src_lane_ready : out std_logic;
- board_kernel_stream_snk_lane_data : out std_logic_vector(71 downto 0);
- board_kernel_stream_snk_lane_valid : out std_logic;
- board_kernel_stream_snk_lane_ready : in std_logic;
+
+ board_kernel_stream_src_lane_0_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_0_valid : in std_logic;
+ board_kernel_stream_src_lane_0_ready : out std_logic;
+ board_kernel_stream_snk_lane_0_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_0_valid : out std_logic;
+ board_kernel_stream_snk_lane_0_ready : in std_logic;
+
+ board_kernel_stream_src_lane_1_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_1_valid : in std_logic;
+ board_kernel_stream_src_lane_1_ready : out std_logic;
+ board_kernel_stream_snk_lane_1_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_1_valid : out std_logic;
+ board_kernel_stream_snk_lane_1_ready : in std_logic;
+
+ board_kernel_stream_src_lane_2_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_2_valid : in std_logic;
+ board_kernel_stream_src_lane_2_ready : out std_logic;
+ board_kernel_stream_snk_lane_2_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_2_valid : out std_logic;
+ board_kernel_stream_snk_lane_2_ready : in std_logic;
+
+ board_kernel_stream_src_lane_3_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_3_valid : in std_logic;
+ board_kernel_stream_src_lane_3_ready : out std_logic;
+ board_kernel_stream_snk_lane_3_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_3_valid : out std_logic;
+ board_kernel_stream_snk_lane_3_ready : in std_logic;
+
+ board_kernel_stream_src_lane_4_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_4_valid : in std_logic;
+ board_kernel_stream_src_lane_4_ready : out std_logic;
+ board_kernel_stream_snk_lane_4_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_4_valid : out std_logic;
+ board_kernel_stream_snk_lane_4_ready : in std_logic;
+
+ board_kernel_stream_src_lane_5_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_5_valid : in std_logic;
+ board_kernel_stream_src_lane_5_ready : out std_logic;
+ board_kernel_stream_snk_lane_5_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_5_valid : out std_logic;
+ board_kernel_stream_snk_lane_5_ready : in std_logic;
+
+ board_kernel_stream_src_lane_6_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_6_valid : in std_logic;
+ board_kernel_stream_src_lane_6_ready : out std_logic;
+ board_kernel_stream_snk_lane_6_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_6_valid : out std_logic;
+ board_kernel_stream_snk_lane_6_ready : in std_logic;
+
+ board_kernel_stream_src_lane_7_data : in std_logic_vector(167 downto 0);
+ board_kernel_stream_src_lane_7_valid : in std_logic;
+ board_kernel_stream_src_lane_7_ready : out std_logic;
+ board_kernel_stream_snk_lane_7_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_lane_7_valid : out std_logic;
+ board_kernel_stream_snk_lane_7_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_0_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_0_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_0_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_0_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_0_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_0_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_1_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_1_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_1_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_1_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_1_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_1_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_2_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_2_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_2_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_2_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_2_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_2_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_3_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_3_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_3_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_3_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_3_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_3_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_4_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_4_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_4_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_4_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_4_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_4_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_5_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_5_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_5_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_5_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_5_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_5_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_6_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_6_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_6_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_6_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_6_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_6_ready : in std_logic;
+
+ board_kernel_stream_snk_rx_monitor_7_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_rx_monitor_7_valid : out std_logic;
+ board_kernel_stream_snk_rx_monitor_7_ready : in std_logic;
+ board_kernel_stream_snk_tx_monitor_7_data : out std_logic_vector(167 downto 0);
+ board_kernel_stream_snk_tx_monitor_7_valid : out std_logic;
+ board_kernel_stream_snk_tx_monitor_7_ready : in std_logic;
+
+
+ board_kernel_stream_src_bs_data : in std_logic_vector(103 downto 0);
+ board_kernel_stream_src_bs_valid : in std_logic;
+ board_kernel_stream_src_bs_ready : out std_logic;
board_kernel_stream_src_mm_io_data : in std_logic_vector(71 downto 0);
board_kernel_stream_src_mm_io_valid : in std_logic;
@@ -321,8 +465,6 @@ PACKAGE top_components_pkg IS
board_kernel_stream_snk_mm_io_data : out std_logic_vector(31 downto 0);
board_kernel_stream_snk_mm_io_valid : out std_logic;
board_kernel_stream_snk_mm_io_ready : out std_logic
-
-
);
end component freeze_wrapper;
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
index a78a5c77389ed7fc19c552470e057bc0db344ffb..d7a2b9f42b341c6577197ff099a9271af9b026e3 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
./ .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
diff --git a/applications/ta2/ip/ta2_channel_cross/hdllib.cfg b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
index 5aacfba5f22333d1396d02444ceb5a1dec930ea7..db608b4b29a54c77d516fc60bbceaa9c5b9c8331 100644
--- a/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
+++ b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
@@ -3,7 +3,6 @@ hdl_library_clause_name = ta2_channel_cross_lib
hdl_lib_uses_synth = common technology dp
hdl_lib_uses_sim =
hdl_lib_technology =
-hdl_lib_include_ip =
synth_files =
ta2_channel_cross.vhd
@@ -14,17 +13,3 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
-
-quartus_qsf_files =
-
-quartus_sdc_files =
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index 68a19952f64cfd9e7ed752674a5734c12bfac39d..1f4acf20126f5ee624b227056cd039f92514f9d3 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -39,10 +39,27 @@
-- +-----------+---------+--------------------------------------------------------+
-- | 65 | eop | End of packet signal |
-- +-----------+---------+--------------------------------------------------------+
--- | 66:68 | - | reserved bits |
+-- | 66 | sync | sync bit, always zero if g_use_sync = FALSE |
+-- +-----------+---------+--------------------------------------------------------+
+-- | 67:68 | - | reserved bits |
-- +-----------+---------+--------------------------------------------------------+
-- | 69:71 | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
+-- | 72:~ | error | Error field, availability and size are dependent on |
+-- | | | generics |
+-- +-----------+---------+--------------------------------------------------------+
+-- | ~:~ | bsn | BSN field, availability and size are dependent on |
+-- | | | generics |
+-- +-----------+---------+--------------------------------------------------------+
+-- | ~:~ | channel | channel field, availability and size are dependent on |
+-- | | | generics |
+-- +-----------+---------+--------------------------------------------------------+
+-- Remark:
+-- . This IP should be configured according to the corresponding IO channel in the OpenCL code.
+-- . It may be nice to be able to configure a larger empty field to support g_nof_bytes > 32
+-- but that would mean that the data structure in the OpenCL code must be adapted. Keep
+-- in mind that IO channels must be a multiple of 8 bits (bytes).
+
LIBRARY IEEE, common_lib, dp_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
@@ -52,26 +69,33 @@ USE technology_lib.technology_pkg.ALL;
ENTITY ta2_channel_cross IS
GENERIC (
g_nof_streams : NATURAL;
- g_nof_bytes : POSITIVE; -- Max = 64
+ g_nof_bytes : POSITIVE; -- nof bytes in payload field, Max = 32
g_reverse_bytes : BOOLEAN := TRUE;
- g_fifo_size : NATURAL := 8
+ g_fifo_size : NATURAL := 8;
+ g_use_err : BOOLEAN := FALSE;
+ g_use_bsn : BOOLEAN := FALSE;
+ g_use_channel : BOOLEAN := FALSE;
+ g_use_sync : BOOLEAN := FALSE;
+ g_err_w : POSITIVE := 32;
+ g_bsn_w : POSITIVE := 64;
+ g_channel_w : POSITIVE := 32
);
PORT (
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- dp_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ dp_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
dp_snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
- dp_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ dp_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
kernel_clk : IN STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
kernel_reset : IN STD_LOGIC;
kernel_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- kernel_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ kernel_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
kernel_snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
- kernel_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+ kernel_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst)
);
END ta2_channel_cross;
@@ -79,48 +103,35 @@ END ta2_channel_cross;
ARCHITECTURE str OF ta2_channel_cross IS
- CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
- CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
+ CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
+ CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
+ CONSTANT c_err_w : NATURAL := sel_a_b(g_use_err, g_err_w, 0);
+ CONSTANT c_bsn_w : NATURAL := sel_a_b(g_use_bsn, g_bsn_w, 0);
+ CONSTANT c_channel_w : NATURAL := sel_a_b(g_use_channel, g_channel_w, 0);
+
+ CONSTANT c_sop_offset : NATURAL := g_nof_bytes*c_byte_w;
+ CONSTANT c_eop_offset : NATURAL := g_nof_bytes*c_byte_w+1;
+ CONSTANT c_sync_offset : NATURAL := g_nof_bytes*c_byte_w+2;
+ CONSTANT c_empty_high : NATURAL := c_byte_w*(g_nof_bytes+1);
+ CONSTANT c_err_offset : NATURAL := c_byte_w*(g_nof_bytes+1);
+ CONSTANT c_bsn_offset : NATURAL := c_err_offset+c_err_w;
+ CONSTANT c_channel_offset : NATURAL := c_bsn_offset+c_bsn_w;
SIGNAL dp_latency_adapter_tx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_fifo_dc_tx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_dc_tx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
-
+ SIGNAL dp_latency_adapter_rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL dp_latency_adapter_rx_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
BEGIN
- ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_channel_cross is configured higher than 64" SEVERITY ERROR;
+ ASSERT g_nof_bytes <= 32 REPORT "g_nof_bytes of ta2_channel_cross is configured higher than 32" SEVERITY ERROR;
gen_streams: FOR stream IN 0 TO g_nof_streams-1 GENERATE
-- dp_snk_in -> kernel_src_out
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order to correct for endianess
- gen_reverse_tx_bytes : IF g_reverse_bytes GENERATE
- gen_tx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
- dp_fifo_dc_tx_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_snk_in_arr(stream).data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
- END GENERATE;
- END GENERATE;
- gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE
- dp_fifo_dc_tx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0);
- END GENERATE;
-
- -- Assign correct data fields to control signals.
- dp_fifo_dc_tx_snk_in_arr(stream).sop <= dp_snk_in_arr(stream).data(c_byte_w*g_nof_bytes+0);
- dp_fifo_dc_tx_snk_in_arr(stream).eop <= dp_snk_in_arr(stream).data(c_byte_w*g_nof_bytes+1);
- dp_fifo_dc_tx_snk_in_arr(stream).empty(c_empty_w-1 DOWNTO 0) <= dp_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w);
- dp_fifo_dc_tx_snk_in_arr(stream).valid <= dp_snk_in_arr(stream).valid;
- dp_snk_out_arr(stream).ready <= dp_fifo_dc_tx_snk_out_arr(stream).ready; -- Flow control towards source
- dp_snk_out_arr(stream).xon <= dp_fifo_dc_tx_snk_out_arr(stream).xon;
---------------------------------------------------------------------------------------
-- TX FIFO: dp_clk -> kernel_clk
@@ -128,8 +139,15 @@ BEGIN
u_dp_fifo_dc_tx : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
g_use_empty => TRUE,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
g_fifo_size => g_fifo_size
)
PORT MAP (
@@ -138,8 +156,8 @@ BEGIN
rd_rst => kernel_reset,
rd_clk => kernel_clk,
- snk_out => dp_fifo_dc_tx_snk_out_arr(stream),
- snk_in => dp_fifo_dc_tx_snk_in_arr(stream),
+ snk_out => dp_snk_out_arr(stream),
+ snk_in => dp_snk_in_arr(stream),
src_in => dp_latency_adapter_tx_snk_out_arr(stream),
src_out => dp_latency_adapter_tx_snk_in_arr(stream)
@@ -160,12 +178,80 @@ BEGIN
snk_in => dp_latency_adapter_tx_snk_in_arr(stream),
snk_out => dp_latency_adapter_tx_snk_out_arr(stream),
- src_out => kernel_src_out_arr(stream),
- src_in => kernel_src_in_arr(stream)
+ src_out => dp_latency_adapter_tx_src_out_arr(stream),
+ src_in => dp_latency_adapter_tx_src_in_arr(stream)
);
-
- -- kernel_snk_in -> dp_src_out
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order
+ gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE
+ gen_rx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
+ kernel_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I);
+ END GENERATE;
+ END GENERATE;
+ gen_no_reverse_rx_bytes : IF NOT g_reverse_bytes GENERATE
+ kernel_src_out_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w-1 DOWNTO 0);
+ END GENERATE;
+
+ -- Assign control signals to correct data fields.
+ kernel_src_out_arr(stream).data(c_sop_offset) <= dp_latency_adapter_tx_src_out_arr(stream).sop;
+ kernel_src_out_arr(stream).data(c_eop_offset) <= dp_latency_adapter_tx_src_out_arr(stream).eop;
+ kernel_src_out_arr(stream).data(c_sync_offset) <= dp_latency_adapter_tx_src_out_arr(stream).sync WHEN g_use_sync ELSE '0';
+ kernel_src_out_arr(stream).data(c_empty_high-1 DOWNTO c_empty_high-c_empty_w) <= dp_latency_adapter_tx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
+ kernel_src_out_arr(stream).valid <= dp_latency_adapter_tx_src_out_arr(stream).valid;
+ dp_latency_adapter_tx_src_in_arr(stream).ready <= kernel_src_in_arr(stream).ready;
+ dp_latency_adapter_tx_src_in_arr(stream).xon <= '1';
+
+ -- Assign optional meta data signals to correct data fields.
+ gen_err_out : IF g_use_err GENERATE
+ kernel_src_out_arr(stream).data(c_err_offset+c_err_w-1 DOWNTO c_err_offset) <= dp_latency_adapter_tx_src_out_arr(stream).err(c_err_w-1 DOWNTO 0);
+ END GENERATE;
+
+ gen_bsn_out : IF g_use_bsn GENERATE
+ kernel_src_out_arr(stream).data(c_bsn_offset+c_bsn_w-1 DOWNTO c_bsn_offset) <= dp_latency_adapter_tx_src_out_arr(stream).bsn(c_bsn_w-1 DOWNTO 0);
+ END GENERATE;
+
+ gen_channel_out : IF g_use_channel GENERATE
+ kernel_src_out_arr(stream).data(c_channel_offset+c_channel_w-1 DOWNTO c_channel_offset) <= dp_latency_adapter_tx_src_out_arr(stream).channel(c_channel_w-1 DOWNTO 0);
+ END GENERATE;
+
+ -- kernel_snk_in -> dp_src_out
+ ----------------------------------------------------------------------------
+ -- Data mapping
+ ----------------------------------------------------------------------------
+ -- Reverse byte order to correct for endianess
+ gen_reverse_tx_bytes : IF g_reverse_bytes GENERATE
+ gen_tx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
+ dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= kernel_snk_in_arr(stream).data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+ END GENERATE;
+ END GENERATE;
+ gen_no_reverse_tx_bytes : IF NOT g_reverse_bytes GENERATE
+ dp_latency_adapter_rx_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_data_w-1 DOWNTO 0);
+ END GENERATE;
+
+ gen_err_in : IF g_use_err GENERATE
+ dp_latency_adapter_rx_snk_in_arr(stream).err(c_err_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_err_offset+c_err_w-1 DOWNTO c_err_offset);
+ END GENERATE;
+
+ gen_bsn_in : IF g_use_bsn GENERATE
+ dp_latency_adapter_rx_snk_in_arr(stream).bsn(c_bsn_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_bsn_offset+c_bsn_w-1 DOWNTO c_bsn_offset);
+ END GENERATE;
+
+ gen_channel_in : IF g_use_channel GENERATE
+ dp_latency_adapter_rx_snk_in_arr(stream).channel(c_channel_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_channel_offset+c_channel_w-1 DOWNTO c_channel_offset);
+ END GENERATE;
+
+ -- Assign correct data fields to control signals.
+ dp_latency_adapter_rx_snk_in_arr(stream).sop <= kernel_snk_in_arr(stream).data(c_sop_offset);
+ dp_latency_adapter_rx_snk_in_arr(stream).eop <= kernel_snk_in_arr(stream).data(c_eop_offset);
+ dp_latency_adapter_rx_snk_in_arr(stream).sync <= kernel_snk_in_arr(stream).data(c_sync_offset) WHEN g_use_sync ELSE '0';
+ dp_latency_adapter_rx_snk_in_arr(stream).empty(c_empty_w-1 DOWNTO 0) <= kernel_snk_in_arr(stream).data(c_empty_high-1 DOWNTO c_empty_high-c_empty_w);
+ dp_latency_adapter_rx_snk_in_arr(stream).valid <= kernel_snk_in_arr(stream).valid;
+ kernel_snk_out_arr(stream).ready <= dp_latency_adapter_rx_snk_out_arr(stream).ready; -- Flow control towards source
+ kernel_snk_out_arr(stream).xon <= dp_latency_adapter_rx_snk_out_arr(stream).xon;
+
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=0 (OpenCL kernel) to RL=1 (Downstream).
----------------------------------------------------------------------------
@@ -178,8 +264,8 @@ BEGIN
clk => kernel_clk,
rst => kernel_reset,
- snk_in => kernel_snk_in_arr(stream),
- snk_out => kernel_snk_out_arr(stream),
+ snk_in => dp_latency_adapter_rx_snk_in_arr(stream),
+ snk_out => dp_latency_adapter_rx_snk_out_arr(stream),
src_out => dp_latency_adapter_rx_src_out_arr(stream),
src_in => dp_latency_adapter_rx_src_in_arr(stream)
@@ -191,8 +277,15 @@ BEGIN
u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
g_data_w => c_data_w,
+ g_bsn_w => c_bsn_w,
g_empty_w => c_empty_w,
+ g_channel_w => c_channel_w,
+ g_error_w => c_err_w,
+ g_use_bsn => g_use_bsn,
g_use_empty => TRUE,
+ g_use_channel => g_use_channel,
+ g_use_error => g_use_err,
+ g_use_sync => g_use_sync,
g_fifo_size => g_fifo_size
)
PORT MAP (
@@ -204,31 +297,10 @@ BEGIN
snk_out => dp_latency_adapter_rx_src_in_arr(stream),
snk_in => dp_latency_adapter_rx_src_out_arr(stream),
- src_in => dp_fifo_dc_rx_src_in_arr(stream),
- src_out => dp_fifo_dc_rx_src_out_arr(stream)
+ src_in => dp_src_in_arr(stream),
+ src_out => dp_src_out_arr(stream)
);
-
-
- ----------------------------------------------------------------------------
- -- Data mapping
- ----------------------------------------------------------------------------
- -- Reverse byte order
- gen_reverse_rx_bytes : IF g_reverse_bytes GENERATE
- gen_rx_bytes: FOR I IN 0 TO g_nof_bytes-1 GENERATE
- dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes-I) -1 DOWNTO c_byte_w*(g_nof_bytes-1-I)) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_byte_w*(I+1)-1 DOWNTO c_byte_w*I);
- END GENERATE;
- END GENERATE;
- gen_no_reverse_rx_bytes : IF NOT g_reverse_bytes GENERATE
- dp_src_out_arr(stream).data(c_data_w-1 DOWNTO 0) <= dp_fifo_dc_rx_src_out_arr(stream).data(c_data_w-1 DOWNTO 0);
- END GENERATE;
-
- -- Assign control signals to correct data fields.
- dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+0) <= dp_fifo_dc_rx_src_out_arr(stream).sop;
- dp_src_out_arr(stream).data(g_nof_bytes*c_byte_w+1) <= dp_fifo_dc_rx_src_out_arr(stream).eop;
- dp_src_out_arr(stream).data(c_byte_w*(g_nof_bytes+1)-1 DOWNTO c_byte_w*(g_nof_bytes+1)-c_empty_w) <= dp_fifo_dc_rx_src_out_arr(stream).empty(c_empty_w-1 DOWNTO 0);
- dp_src_out_arr(stream).valid <= dp_fifo_dc_rx_src_out_arr(stream).valid;
- dp_fifo_dc_rx_src_in_arr(stream).ready <= dp_src_in_arr(stream).ready;
- dp_fifo_dc_rx_src_in_arr(stream).xon <= '1';
+
END GENERATE;
END str;
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
index aab4d4bca08d4666073e50956523f37c68a37f7a..af7197e767a76a90e1c1dab71233b1a78d66aa1b 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/hdllib.cfg
@@ -31,19 +31,4 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-quartus_copy_files =
-
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 27f608901b8de958f53e27f6ce7dc069aa211ba0..171537fdf7e4d800fe6ad57ba692071f6bc25599 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -49,6 +49,10 @@
-- +-----------+---------+--------------------------------------------------------+
-- | 69:71 | empty | On EOP, this field indicates how many bytes are unused |
-- +-----------+---------+--------------------------------------------------------+
+-- | 72:103 | err | On EOP, this field indicates errors (only used if |
+-- | | | g_use_err = TRUE) |
+-- +-----------+---------+--------------------------------------------------------+
+
LIBRARY IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_eth_10g_lib, tech_mac_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
@@ -59,13 +63,19 @@ USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
ENTITY ta2_unb2b_10GbE IS
GENERIC (
- g_nof_mac : NATURAL
+ g_nof_mac : NATURAL; -- Valid inputs are 1, 3, 4, 12, 24, 48
+ g_use_err : BOOLEAN := FALSE;
+ g_err_w : POSITIVE := 32;
+ g_use_pll : BOOLEAN := TRUE
);
PORT (
mm_clk : IN STD_LOGIC; -- 100MHz clk for reconfig block and status interface
mm_rst : IN STD_LOGIC;
clk_ref_r : IN STD_LOGIC; -- 644.53125MHz 10G MAC reference clock
+ clk_156 : IN STD_LOGIC := '0';
+ clk_312 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
tx_serial_r : OUT STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial TX lanes towards QSFP cage
rx_serial_r : IN STD_LOGIC_VECTOR(g_nof_mac-1 DOWNTO 0); -- Serial RX lanes from QSFP cage
@@ -129,18 +139,26 @@ BEGIN
--------
-- PLL
--------
- u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg
- )
- PORT MAP (
- refclk_644 => clk_ref_r,
- rst_in => mm_rst,
- clk_156 => tr_ref_clk_156,
- clk_312 => tr_ref_clk_312,
- rst_156 => tr_ref_rst_156,
- rst_312 => OPEN
- );
+ g_pll : IF g_use_pll GENERATE
+ u_tech_pll_xgmii_mac_clocks : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg
+ )
+ PORT MAP (
+ refclk_644 => clk_ref_r,
+ rst_in => mm_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+ END GENERATE;
+
+ gen_no_pll : IF NOT g_use_pll GENERATE
+ tr_ref_clk_156 <= clk_156;
+ tr_ref_clk_312 <= clk_312;
+ tr_ref_rst_156 <= rst_156;
+ END GENERATE;
---------------------------------------------------------------------------------------
-- Clocks and reset
@@ -185,6 +203,9 @@ BEGIN
END GENERATE;
-- Assign correct data fields to control signals.
+ gen_err_in: IF g_use_err GENERATE
+ dp_latency_adapter_tx_snk_in_arr(mac).err(g_err_w-1 DOWNTO 0) <= snk_in_arr(mac).data(71+g_err_w DOWNTO 72);
+ END GENERATE;
dp_latency_adapter_tx_snk_in_arr(mac).sop <= snk_in_arr(mac).data(64);
dp_latency_adapter_tx_snk_in_arr(mac).eop <= snk_in_arr(mac).data(65);
dp_latency_adapter_tx_snk_in_arr(mac).empty(2 DOWNTO 0) <= snk_in_arr(mac).data(71 DOWNTO 69);
@@ -253,43 +274,6 @@ BEGIN
src_out => dp_fifo_fill_tx_src_out_arr(mac)
);
-
- ---------------------------------------------------------------------------------------
- -- ETH MAC + PHY, use g_nof_mac duplicates of eth_10g with g_nof_channels = 1 to be most flexible
- ---------------------------------------------------------------------------------------
- u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
- GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
- g_sim => c_sim,
- g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
- g_nof_channels => 1,
- g_direction => "TX_RX",
- g_pre_header_padding => FALSE
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
- tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
- tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
- tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
-
- -- MM
- mm_clk => '0',
- mm_rst => '0',
-
- -- ST
- tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr(mac DOWNTO mac), -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr(mac DOWNTO mac),
-
- rx_src_out_arr => mac_10g_src_out_arr(mac DOWNTO mac), -- 64 bit data @ 156 MHz
- rx_src_in_arr => mac_10g_src_in_arr(mac DOWNTO mac),
-
- -- PHY serial IO
- -- . 10GBASE-R (single lane)
- serial_tx_arr => tx_serial_r(mac DOWNTO mac),
- serial_rx_arr => rx_serial_r(mac DOWNTO mac)
- );
-
---------------------------------------------------------------------------------------
-- RX FIFO: rx_clk -> dp_clk
---------------------------------------------------------------------------------------
@@ -342,6 +326,9 @@ BEGIN
END GENERATE;
-- Assign control signals to correct data fields.
+ gen_err_out: IF g_use_err GENERATE
+ src_out_arr(mac).data(71+g_err_w DOWNTO 72) <= dp_latency_adapter_rx_src_out_arr(mac).err(g_err_w-1 DOWNTO 0);
+ END GENERATE;
src_out_arr(mac).data(64) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
src_out_arr(mac).data(65) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
src_out_arr(mac).data(71 DOWNTO 69) <= dp_latency_adapter_rx_src_out_arr(mac).empty(2 DOWNTO 0);
@@ -350,5 +337,42 @@ BEGIN
dp_latency_adapter_rx_src_in_arr(mac).xon <= '1';
END GENERATE;
+ ---------------------------------------------------------------------------------------
+ -- ETH MAC + PHY
+ ---------------------------------------------------------------------------------------
+ u_tech_eth_10g : ENTITY tech_eth_10g_lib.tech_eth_10g
+ GENERIC MAP (
+ g_technology => c_tech_arria10_e1sg,
+ g_sim => c_sim,
+ g_sim_level => 1, -- 0 = use IP; 1 = use fast serdes model
+ g_nof_channels => g_nof_mac,
+ g_direction => "TX_RX",
+ g_pre_header_padding => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => eth_ref_clk_644, -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_312 => eth_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => eth_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => eth_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM
+ mm_clk => '0',
+ mm_rst => '0',
+
+ -- ST
+ tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
+
+ rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
+ rx_src_in_arr => mac_10g_src_in_arr,
+
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => tx_serial_r,
+ serial_rx_arr => rx_serial_r
+ );
+
+
END str;
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
index ec8ec20de75740c8d6d56a46fa747d844e40546d..75b9ecc8cc6cc90918cc577f764a492179834c67 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg
@@ -13,19 +13,4 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-quartus_copy_files =
-
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
index a128fd70244f389cf29ae5d6c8305829026fe2c0..5b31bc919ca1bfcd4977d52fe874cf745ad22b2d 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -14,25 +14,11 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
quartus_copy_files =
arria10_40g_mac.ip .
arria10_40g_atx_pll.ip .
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
-
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
index d716f7b25ae02d704636d16eeeacd345061bfa3f..5efa9d2a69434efac43fb1050bf7f74b2ab86570 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_ddr/hdllib.cfg
@@ -18,19 +18,4 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-quartus_copy_files =
-
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
index dc2c4c56c53bf428282cc757d22f6f24d6b0468e..4d5bf3ae7a6e0d9f0914aee29dcdbfe86f8b6550 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/hdllib.cfg
@@ -14,19 +14,4 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-quartus_copy_files =
-
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
index 274d179d5969d1c22bf79a8d99afe87e1f738503..74ad7164e9b793958af22a5340abb3ebe97336bb 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/hdllib.cfg
@@ -14,19 +14,3 @@ regression_test_vhdl =
[modelsim_project_file]
[quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
-
-quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
-
-quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
-
-quartus_tcl_files =
-
-
-quartus_vhdl_files =
-
-quartus_qip_files =
diff --git a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
index 40f9191902718876c4770eddae1437b8cc66f0fe..930c532f171f7c58d85b39ad34039a10abc5c3ef 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
+++ b/boards/uniboard2b/designs/unb2b_minimal/unb2b_minimal.fpga.yaml
@@ -18,7 +18,7 @@ peripherals:
- peripheral_name: unb2b_board/wdi
mm_port_names:
- - PIO_WDI
+ - REG_WDI
- peripheral_name: unb2b_board/unb2_fpga_sens
mm_port_names:
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index 0856f4403c2e0b7ec01f825f9aa30ea6698d5f8a..ab23adb03f4bcb6c38f44f5a5d06e9f0e4e75275 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -43,7 +43,7 @@ ENTITY ctrl_unb2b_board IS
----------------------------------------------------------------------------
g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE;
- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model;
g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
g_design_name : STRING := "UNUSED";
g_fw_version : t_unb2b_board_fw_version := (0, 0); -- firmware version x.y
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 12cf2dacce1a83c871c0eb1679d3e35268145169..58bd7d22dccf0090f87864f2266bd4a486847293 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -3,6 +3,7 @@
* RadioHDL issues
* ARGS
* GIT workflow
+* SVN
* Confluence
* Polarion
* Latex
@@ -15,6 +16,8 @@
* Linux
* ICT diensten
* Python
+* Zenodo DOI
+
@@ -37,16 +40,16 @@
> cd ~/git/hdl
-> . ./init_hdl.sh
+> . ./init_hdl.sh
* init_hdl.sh defines:
- RADIOHDL_WORK directory for where the source code resides
- RADIOHDL_BUILD_DIR directory for where the targets will be build
- HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
-
+
* init_hdl.sh copies git user_components.ipx into Altera dir's
- cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
-
+
* init_hdl.sh automatically also sources ../radiohdl/init_radiohdl.sh if necessary
@@ -57,31 +60,31 @@ source also radiohdl tools
- RADIOHDL_GEAR directory of where the init_radiohdl.sh is located
- RADIOHDL_BUILD_DIR = ${RADIOHDL_BUILD_DIR}/build if not already defined
- RADIOHDL_CONFIG = ${RADIOHDL_GEAR}/config if not already defined
-
+
* init_radiohdl.sh extends:
- PATH with ${RADIOHDL_GEAR}/core
${RADIOHDL_GEAR}/quartus
${RADIOHDL_GEAR}/modelsim
- PYTHONPATH with ${RADIOHDL_GEAR}/core
${RADIOHDL_GEAR}/components
-
-
+
+
> compile_altera_simlibs unb1 # creates build/unb1/hdl_libraries_ip_stratixiv.txt
# creates build/quartus/<tool version> simulation models that need to be moved
# manually to $MODELSIM_ALTERA_LIBS_DIR/<tool version>
-
+
> generate_ip_libs unb1 # creates build/unb1/qmegawiz/
# creates build/unb1/quartus_sh --> empty dir, why is it there?
-
+
> quartus_config unb1 # creates build/unb1/quartus/<hdllib libraries> for synthesis
# creates build/unb1/quartus/technology_select_pkg.vhd
-
+
> modelsim_config unb1 # creates build/unb1/modelsim/<hdllib libraries> for simulation
# creates build/unb1/modelsim/modelsim_project_files.txt for Modelsim commands.do
# creates build/unb1/modelsim/technology_select_pkg.vhd
-
+
> run_qsys unb1 unb1_minimal_qsys # creates QSYS block in build/unb1/quartus/unb1_minimal_qsys
-> run_qcomp unb1 unb1_minimal_qsys # creates
+> run_qcomp unb1 unb1_minimal_qsys # creates
> run_modelsim unb1 &
@@ -277,15 +280,15 @@ We identify two persons in this process:
* Work on branch using git add, commit and push
* Manually run regression test to test the changes (for Casacore SW the merge
request makes github automatically issue a regression test in the cloud, for
- FW we need to run the relevant testbenches manually. It is not necessary to
+ FW we need to run the relevant testbenches manually. It is not necessary to
rerun the entire FW regression test, it is sufficient to only run the
- regression test for the HDL libraries that were modified and the HDL
+ regression test for the HDL libraries that were modified and the HDL
libraries that could be impacted by the modification)
-* Push the branch to the central repository at gitlab
+* Push the branch to the central repository at gitlab
git push -u origin L2SDP-26 # first time to declare the branch at the remote
-
-
+
+
* Coder does merge request to reviewer using the central Gitlab GUI
* gitlab will warn if the branch will lead to a merge conflict, the coder then
first has to fix the merge conflict by merging the master to the branch:
@@ -300,7 +303,7 @@ We identify two persons in this process:
git add file
git commit
git push
-
+
* In gitlab do merge request to reviewer
* Reviewer reviews the code per line or in general comments in gitlab GUI,
so reviewer does not need to pull the branch locally and also does not need
@@ -313,19 +316,19 @@ We identify two persons in this process:
* When review is done then the reviewer does the merge.
* The merge automatically deletes the branch (if selected to do so in gitlab)
locally the coder manually needs to delete the branch:
-
+
git branch
git checkout master
git status
git branch -d L2SDP-26
git status
-
+
* Use Jira tag in commit message to have link between GIT and Jira. The link
was made via Settings/Intergations/Jira
Note:
* In github a merge request is called a pull request
-* Default a pull pulls the master. Typically it is not necessary to pull a
+* Default a pull pulls the master. Typically it is not necessary to pull a
branch because the reviewer does not need to compile and run the code and
because typically only one coder works on a branch.
@@ -333,8 +336,14 @@ We hebben nog geen regel over sub-branches wel of niet. Als er geen duidelijk vo
ik alleen vanaf de master branchen, omdat je de branches dan onafhankelijk houdt van elkaar en
alle branches dan dezelfde referentie hebben. Voordat je een merge request van je branch naar een
bovenliggende branch doet, moet je eerst die bovenliggende branch mergen naar je branch.
-
-
+
+
+*******************************************************************************
+* SVN:
+*******************************************************************************
+svn -diff --diff-cmd='meld' [filepath] -r [revision]
+
+
*******************************************************************************
* Confluence:
*******************************************************************************
@@ -375,7 +384,7 @@ for me it is an ok workaround,
* Markdown
*******************************************************************************
-See https://git.astron.nl/desp/args/Markdown/readme_markdown.txt
+See https://git.astron.nl/desp/args/Markdown/readme_markdown.txt
*******************************************************************************
@@ -403,20 +412,20 @@ bcksp |
|
j
-
+
*******************************************************************************
* Remote access
*******************************************************************************
* RDP:
Instead of Remote Desktop (RDP) use Remmina. It may be necessary to use:
-
+
> ssh -t -L 5900:localhost:5900 -C dop466 'x11vnc -localhost -display :0'
en daarna:
-
+
> remmina &
-
+
Note: Windows NTSERVER65 has IP: 10.87.3.165
* Login using ssh keys:
@@ -456,11 +465,11 @@ Host dop421
ProxyCommand ssh -q -A astron netcat 10.87.0.221
*******************************************************************************
-* License server
+* License server
*******************************************************************************
export LM_LICENSE_FILE=1800@license4.astron.nl:1717@license5.astron.nl
-
+
ping 10.87.3.179 # = ping license4.astron.nl
ping 10.87.3.114 # = ping license5.astron.nl
@@ -473,7 +482,7 @@ https://linuxize.com/post/how-to-use-linux-screen/
screen --version
-Basic Linux Screen Usage
+Basic Linux Screen Usage
On the command prompt, type screen.
Run the desired program.
@@ -486,7 +495,7 @@ To start a screen session, simply type screen in your console:
screen
screen -S session_name
-This will open a screen session, create a new window, and start a shell in
+This will open a screen session, create a new window, and start a shell in
that window. Now that you have opened a screen session, you can get a list of
commands by typing:
@@ -518,7 +527,7 @@ from the session. To resume your screen session use the following command:
screen -r
-In case you have multiple screen sessions running on your machine, you will
+In case you have multiple screen sessions running on your machine, you will
need to append the screen session ID after the r switch.
To find the session ID list the current running screen sessions with:
@@ -565,10 +574,10 @@ Copy
1) Designs without QSYS: unb2b_arp_ping
Met meld blijkt dat de ip dir van unb2b_arp_ping en unb2b_minimal gelijk zijn
-in de STAT-266 branch. Dat komt omdat je ze gecopieerd hebt en omdat
+in de STAT-266 branch. Dat komt omdat je ze gecopieerd hebt en omdat
unb2b_arp_ping geen QSYS heeft zijn ze dus ongewijzigd.
-Aangezien unb2b_arp_ping geen QSYS heeft, en ook niet zou krijgen, is het
+Aangezien unb2b_arp_ping geen QSYS heeft, en ook niet zou krijgen, is het
beter om de unb2b_arp_ping/quartus/ip dir van unb2_arp_ping te deleten.
2) Designs with QSYS
@@ -589,7 +598,7 @@ mag gebruiken, dus zonder naamswijziging.
ll $RADIOHDL_WORK/boards/uniboard2b/designs/unb2b_jesd/quartus/
ip/
qsys_unb2b_jesd.qsys
-
+
ll $RADIOHDL_WORK/boards/uniboard2b/designs/unb2b_jesd/quartus/ip/qsys_unb2b_minimal
total 2492
-rw-r--r-- 1 kooistra users 234095 Sep 23 13:01 altjesd_ss_RX_corepll.ip
@@ -662,6 +671,11 @@ https://linuxize.com/
> apt-get dist-upgrade
> apt autoremove
+# Henk Vosmeier
+sudo apt-get upgrade
+sudo apt-get dist-upgrade
+sudo apt remove
+
# Login on dop386 and then power off:
> sudo shutdown
@@ -673,6 +687,9 @@ dop466_0 = HDD
> gzip filename # zip file
> unzip filename.gz # unzip file
+> zip -r apertif_matlab-v1.0.zip apertif_matlab
+> zipinfo apertif_matlab-v1.0.zip
+
> grep -rl 'search text in files' . # -r for recursive, -l for only list filename
> find . -name *_thisfile.txt
@@ -685,6 +702,7 @@ Start --> Administration --> Synaptic package manager
> sudo pip3 install numpy # to run Python3 library installer as root
> sudo apt-get install pip # to install Python2 library installer
+> sudo apt-get install python-matplotlib
# ARGS doc gen
> sudo pip3 install --upgrade setuptools
@@ -710,11 +728,6 @@ Start --> Administration --> Synaptic package manager
# Ethernet
> ifconfig
-# Henk Vosmeier
-sudo apt-get upgrade
-sudo apt-get dist-upgrade
-sudo apt remove
-
# primary group
# supplementary groups
@@ -728,8 +741,8 @@ sudo usermod -a -G software kooistra # add user 'kooistra' to a Linux group 's
ls -l filename # shows current user,group owners of the 'filename'
sudo chgrp software filename # change group of 'filename' to 'software'
sudo chgrp -R software dirname # recursively change group of 'dirname' to 'software'
-#chown # change user,group
+sudo chown user_name file_name # change user,group
*******************************************************************************
* ICT diensten
@@ -771,3 +784,18 @@ https://pypi.org/project/black/ # Python code formatter
numpy tutorial:
https://lwn.net/SubscriberLink/847039/3016fa7278000b77/
+
+
+*******************************************************************************
+* Zenodo DOI
+*******************************************************************************
+
+- login at https://zenodo.org/
+- choose Upload in main menu --> my zenodo DOIs area
+- choose New Upload button
+- fill in all fields, reserve a DOI and do save
+- check the README.md, NOTICE.md (with the DOI) and the LICENSE.md
+- create the zip file
+- upload the zip file and publish the DOI.
+
+
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 75b70901a1163728a9d1d7f6d3f551db58b6384d..e95d804fc699c49196b5e95764f559a01854ca91 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -8,9 +8,9 @@ synth_files =
$RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
src/vhdl/common_str_pkg.vhd
src/vhdl/common_mem_pkg.vhd
- src/vhdl/common_math_pkg.vhd
src/vhdl/common_field_pkg.vhd
src/vhdl/common_lfsr_sequences_pkg.vhd
+ src/vhdl/common_math_pkg.vhd
src/vhdl/common_interface_layers_pkg.vhd
src/vhdl/common_network_layers_pkg.vhd
src/vhdl/common_network_total_header_pkg.vhd
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 0cbb134183563d9fc256e750614fca2a017625a0..1fd31bbd370afc179e24e0247d8a8f091e12df39 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -36,7 +36,7 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE work.common_pkg.ALL;
-
+USE work.common_lfsr_sequences_pkg.ALL;
PACKAGE common_math_pkg IS
@@ -79,7 +79,10 @@ PACKAGE common_math_pkg IS
-- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
FUNCTION common_math_create_look_up_table_phasor(N, W : POSITIVE; AMPL, FREQ, PHI : REAL) RETURN t_nat_integer_arr;
FUNCTION common_math_create_look_up_table_phasor(N, W : POSITIVE; AMPL, FREQ, PHI : REAL) RETURN t_slv_32_arr; -- range 0 TO N-1
-
+
+ FUNCTION common_math_create_random_arr(N, W : POSITIVE; seed : NATURAL) RETURN t_integer_arr;
+
+
END common_math_pkg;
@@ -178,6 +181,18 @@ PACKAGE BODY common_math_pkg IS
END LOOP;
RETURN v_exp_arr;
END;
-
+
+ FUNCTION common_math_create_random_arr(N, W : POSITIVE; seed : NATURAL) RETURN t_integer_arr IS
+ VARIABLE v_rand_arr : t_integer_arr(0 TO N-1);
+ VARIABLE v_random : STD_LOGIC_VECTOR(W-1 DOWNTO 0) := TO_UVEC(seed, W);
+ BEGIN
+ FOR I IN 0 TO N-1 LOOP
+ v_random := func_common_random(v_random);
+ v_rand_arr(I) := TO_SINT(v_random);
+ END LOOP;
+ RETURN v_rand_arr;
+ END;
+
+
END common_math_pkg;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index 078e54f9405b2e9ba2f7ac50af5d25ad8ded3d9d..3467ca37d93d603183c7c01cf208818fe696f15b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -63,7 +63,7 @@ architecture tb of tb_fft_reorder_sepa_pipe is
constant c_bst_skip_nof_sync : natural := 3;
constant c_nof_accum_per_sync : natural := 10;
constant c_bsn_init : natural := 32;
- constant c_bg_prefix : string := "../../../tb/data/to_separate";
+ constant c_bg_prefix : string := "data/to_separate";
signal tb_end : std_logic := '0';
signal rst : std_logic;
diff --git a/libraries/dsp/st/hdllib.cfg b/libraries/dsp/st/hdllib.cfg
index 3617a5976a7da4b76d245c3cbcd1c1cfdcfb6d71..02987cf05a878d6d473ef63930b6d49de9696b75 100644
--- a/libraries/dsp/st/hdllib.cfg
+++ b/libraries/dsp/st/hdllib.cfg
@@ -9,22 +9,35 @@ synth_files =
src/vhdl/st_ctrl.vhd
src/vhdl/st_calc.vhd
src/vhdl/st_sst.vhd
+ src/vhdl/st_xsq.vhd
+ src/vhdl/st_xsq_arr.vhd
+ src/vhdl/st_xsq_mm_to_dp.vhd
+ src/vhdl/st_xsq_dp_to_mm.vhd
+ src/vhdl/st_xst.vhd
# src/vhdl/st_top.vhd
src/vhdl/st_histogram.vhd
src/vhdl/st_histogram_reg.vhd
src/vhdl/mms_st_histogram.vhd
src/vhdl/st_histogram_8_april.vhd
+
+ tb/vhdl/tb_st_pkg.vhd
test_bench_files =
tb/vhdl/tb_st_acc.vhd
tb/vhdl/tb_st_calc.vhd
tb/vhdl/tb_mmf_st_sst.vhd
+ tb/vhdl/tb_st_xsq.vhd
+ tb/vhdl/tb_tb_st_xsq.vhd
+ tb/vhdl/tb_st_xst.vhd
+ tb/vhdl/tb_tb_st_xst.vhd
tb/vhdl/tb_st_histogram.vhd
tb/vhdl/tb_mms_st_histogram.vhd
tb/vhdl/tb_tb_st_histogram.vhd
regression_test_vhdl =
tb/vhdl/tb_st_acc.vhd
+ tb/vhdl/tb_tb_st_xsq.vhd
+ tb/vhdl/tb_tb_st_xst.vhd
#tb/vhdl/tb_st_calc.vhd -- tb is not self checking yet
diff --git a/libraries/dsp/st/src/vhdl/st_xsq.vhd b/libraries/dsp/st/src/vhdl/st_xsq.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..997e13c1b253434c103dca1bc505447b0bfa37ab
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xsq.vhd
@@ -0,0 +1,255 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- Store the statistics of the complex input streams in_a and in_b with
+-- blocks of g_nof_crosslets * g_nof_signal_inputs**2 multiplexed subbands into a MM register.
+-- Description:
+--
+-- After each sync the MM register gets updated with the statistics
+-- of the previous sync interval. The length of the sync interval determines
+-- the nof accumlations per statistic, hence the integration time. See st_calc
+-- for more details.
+-- Remarks:
+-- . The in_sync is assumed to be a pulse an interpreted directly.
+-- . The MM register is single page RAM to save memory resources. Therefore
+-- just after the sync its contents is undefined when it gets written, but
+-- after that its contents remains stable for the rest of the sync interval.
+-- Therefore it is not necessary to use a dual page register that swaps at
+-- the sync.
+-- . The minimum c_nof_statistics = 8. Lower values lead to simulation errors. This is
+-- due to the read latency of 2 of the accumulation memory in the st_calc entity.
+-- . More detail can be found in:
+-- https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+Correlator
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+ENTITY st_xsq IS
+ GENERIC (
+ g_nof_signal_inputs : NATURAL := 2;
+ g_nof_crosslets : NATURAL := 1;
+ g_in_data_w : NATURAL := 18; -- width of the data to be accumulated
+ g_stat_data_w : NATURAL := 54; -- statistics accumulator width
+ g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- Streaming
+ in_a : IN t_dp_sosi; -- Complex input data
+ in_b : IN t_dp_sosi; -- Complex input data
+
+ -- Memory Mapped
+ ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst
+ );
+END st_xsq;
+
+ARCHITECTURE str OF st_xsq IS
+
+ CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+ CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+ CONSTANT c_nof_stat_w : NATURAL := ceil_log2(c_nof_statistics);
+ CONSTANT c_nof_word : NATURAL := g_stat_data_sz*c_nof_statistics;
+ CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
+ CONSTANT c_stat_word_w : NATURAL := g_stat_data_sz*c_word_w;
+ CONSTANT c_total_ram_addr_w : NATURAL := ceil_log2(c_nof_complex) + c_nof_word_w;
+
+ -- Statistics register
+ CONSTANT c_mm_ram : t_c_mem := (latency => 1,
+ adr_w => c_nof_word_w,
+ dat_w => c_word_w,
+ nof_dat => c_nof_word,
+ init_sl => '0'); -- MM side : sla_in, sla_out
+ CONSTANT c_stat_ram : t_c_mem := (latency => 1,
+ adr_w => c_nof_stat_w,
+ dat_w => c_stat_word_w,
+ nof_dat => c_nof_statistics,
+ init_sl => '0'); -- ST side : stat_mosi
+ SIGNAL pipe_in_a : t_dp_sosi;
+ SIGNAL pipe_in_b : t_dp_sosi;
+
+ SIGNAL stat_data_re : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
+ SIGNAL stat_data_im : STD_LOGIC_VECTOR(g_stat_data_w-1 DOWNTO 0);
+
+ SIGNAL wrdata_re : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
+ SIGNAL wrdata_im : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);
+
+ SIGNAL stat_mosi : t_mem_mosi := c_mem_mosi_rst;
+
+ SIGNAL ram_st_xsq_mosi_arr : t_mem_mosi_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_st_xsq_miso_arr : t_mem_miso_arr(c_nof_complex-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL remapped_ram_st_xsq_mosi : t_mem_mosi;
+
+BEGIN
+ ---------------------------------------------------------------
+ -- pipeline inputs to increase latency with 1 in comparison to sync for st_calc
+ ---------------------------------------------------------------
+ u_dp_pipeline_a : ENTITY dp_lib.dp_pipeline
+ GENERIC MAP (
+ g_pipeline => 1
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => in_a,
+ -- ST source
+ src_out => pipe_in_a
+ );
+
+ u_dp_pipeline_b : ENTITY dp_lib.dp_pipeline
+ GENERIC MAP (
+ g_pipeline => 1
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => in_b,
+ -- ST source
+ src_out => pipe_in_b
+ );
+
+ ---------------------------------------------------------------
+ -- st_calc
+ ---------------------------------------------------------------
+ st_calc : ENTITY work.st_calc
+ GENERIC MAP (
+ g_nof_mux => 1,
+ g_nof_stat => c_nof_statistics,
+ g_in_dat_w => g_in_data_w,
+ g_out_dat_w => g_stat_data_w,
+ g_out_adr_w => c_nof_stat_w,
+ g_complex => TRUE
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ in_ar => pipe_in_a.re(g_in_data_w-1 DOWNTO 0),
+ in_ai => pipe_in_a.im(g_in_data_w-1 DOWNTO 0),
+ in_br => pipe_in_b.re(g_in_data_w-1 DOWNTO 0),
+ in_bi => pipe_in_b.im(g_in_data_w-1 DOWNTO 0),
+ in_val => pipe_in_a.valid,
+ in_sync => in_a.sync,
+ out_adr => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
+ out_re => stat_data_re,
+ out_im => stat_data_im,
+ out_val => stat_mosi.wr,
+ out_val_m => OPEN
+ );
+
+ wrdata_re <= RESIZE_MEM_UDATA(stat_data_re);
+ wrdata_im <= RESIZE_MEM_UDATA(stat_data_im);
+
+ ---------------------------------------------------------------
+ -- COMBINE MEMORY MAPPED INTERFACES
+ ---------------------------------------------------------------
+ -- Translate incoming MM interface [crosslets][in A][in B][complex][word] to
+ -- [complex][crosslets][in A][in B][word]
+ p_remap : PROCESS(ram_st_xsq_mosi)
+ BEGIN
+ remapped_ram_st_xsq_mosi <= ram_st_xsq_mosi;
+ remapped_ram_st_xsq_mosi.address(c_total_ram_addr_w -1 DOWNTO c_nof_word_w) <= ram_st_xsq_mosi.address(ceil_log2(c_nof_complex)+ceil_log2(g_stat_data_sz)-1 DOWNTO ceil_log2(g_stat_data_sz));
+ remapped_ram_st_xsq_mosi.address(c_nof_word_w -1 DOWNTO 0) <= ram_st_xsq_mosi.address(c_total_ram_addr_w -1 DOWNTO ceil_log2(c_nof_complex)+ceil_log2(g_stat_data_sz)) & ram_st_xsq_mosi.address(ceil_log2(g_stat_data_sz)-1 DOWNTO 0);
+ END PROCESS;
+
+ -- Combine the internal array of mm interfaces for both real
+ -- and imaginary part.
+ u_mem_mux_select : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => c_nof_complex,
+ g_mult_addr_w => c_nof_word_w
+ )
+ port map (
+ mosi => remapped_ram_st_xsq_mosi,
+ miso => ram_st_xsq_miso,
+ mosi_arr => ram_st_xsq_mosi_arr,
+ miso_arr => ram_st_xsq_miso_arr
+ );
+
+ -- ram for real values
+ stat_reg_re : ENTITY common_lib.common_ram_crw_crw_ratio
+ GENERIC MAP (
+ g_ram_a => c_mm_ram,
+ g_ram_b => c_stat_ram,
+ g_init_file => "UNUSED"
+ )
+ PORT MAP (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+
+ wr_en_a => ram_st_xsq_mosi_arr(0).wr, -- only for diagnostic purposes, typically statistics are read only
+ wr_dat_a => ram_st_xsq_mosi_arr(0).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
+ adr_a => ram_st_xsq_mosi_arr(0).address(c_mm_ram.adr_w-1 DOWNTO 0),
+ rd_en_a => ram_st_xsq_mosi_arr(0).rd,
+ rd_dat_a => ram_st_xsq_miso_arr(0).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
+ rd_val_a => ram_st_xsq_miso_arr(0).rdval,
+
+ wr_en_b => stat_mosi.wr,
+ wr_dat_b => wrdata_re(c_stat_ram.dat_w-1 DOWNTO 0),
+ adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => OPEN
+ );
+
+ -- ram for imaginary values
+ stat_reg_im : ENTITY common_lib.common_ram_crw_crw_ratio
+ GENERIC MAP (
+ g_ram_a => c_mm_ram,
+ g_ram_b => c_stat_ram,
+ g_init_file => "UNUSED"
+ )
+ PORT MAP (
+ rst_a => mm_rst,
+ clk_a => mm_clk,
+
+ rst_b => dp_rst,
+ clk_b => dp_clk,
+
+ wr_en_a => ram_st_xsq_mosi_arr(1).wr, -- only for diagnostic purposes, typically statistics are read only
+ wr_dat_a => ram_st_xsq_mosi_arr(1).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
+ adr_a => ram_st_xsq_mosi_arr(1).address(c_mm_ram.adr_w-1 DOWNTO 0),
+ rd_en_a => ram_st_xsq_mosi_arr(1).rd,
+ rd_dat_a => ram_st_xsq_miso_arr(1).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
+ rd_val_a => ram_st_xsq_miso_arr(1).rdval,
+
+ wr_en_b => stat_mosi.wr,
+ wr_dat_b => wrdata_im(c_stat_ram.dat_w-1 DOWNTO 0),
+ adr_b => stat_mosi.address(c_stat_ram.adr_w-1 DOWNTO 0),
+ rd_en_b => '0',
+ rd_dat_b => OPEN,
+ rd_val_b => OPEN
+ );
+
+END str;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b4445b2022a4ef884e3c5eeb16bf8d465ff683ac
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
@@ -0,0 +1,114 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- Multiple instances of st_xsq.vhd
+-- Description:
+-- . See st_xsq.vhd
+-- Remarks:
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+ENTITY st_xsq_arr IS
+ GENERIC (
+ g_nof_streams : NATURAL := 1;
+ g_nof_crosslets : NATURAL := 1;
+ g_nof_signal_inputs : NATURAL := 2;
+ g_in_data_w : NATURAL := 18; -- width of the data to be accumulated
+ g_stat_data_w : NATURAL := 54; -- statistics accumulator width
+ g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- Streaming
+ in_a_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Complex input data
+ in_b_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Complex input data
+
+ -- Memory Mapped
+ ram_st_xsq_mosi : IN t_mem_mosi;
+ ram_st_xsq_miso : OUT t_mem_miso
+ );
+END st_xsq_arr;
+
+ARCHITECTURE str OF st_xsq_arr IS
+
+ CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+ CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+ CONSTANT c_nof_word : NATURAL := g_stat_data_sz*c_nof_statistics*c_nof_complex;
+ CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
+
+ SIGNAL ram_st_xsq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL ram_st_xsq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+BEGIN
+ -- st_xsq instances
+ gen_xsq : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ st_xsq : ENTITY work.st_xsq
+ GENERIC MAP (
+ g_nof_signal_inputs => g_nof_signal_inputs,
+ g_nof_crosslets => g_nof_crosslets,
+ g_in_data_w => g_in_data_w,
+ g_stat_data_w => g_stat_data_w,
+ g_stat_data_sz => g_stat_data_sz
+ )
+ PORT MAP (
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Streaming
+ in_a => in_a_arr(I),
+ in_b => in_b_arr(I),
+
+ -- Memory Mapped
+ ram_st_xsq_mosi => ram_st_xsq_mosi_arr(I),
+ ram_st_xsq_miso => ram_st_xsq_miso_arr(I)
+ );
+ END GENERATE;
+
+ ---------------------------------------------------------------
+ -- COMBINE MEMORY MAPPED INTERFACES
+ ---------------------------------------------------------------
+ -- Combine the internal array of mm interfaces.
+ u_mem_mux_select : entity common_lib.common_mem_mux
+ generic map (
+ g_nof_mosi => g_nof_streams,
+ g_mult_addr_w => c_nof_word_w
+ )
+ port map (
+ mosi => ram_st_xsq_mosi,
+ miso => ram_st_xsq_miso,
+ mosi_arr => ram_st_xsq_mosi_arr,
+ miso_arr => ram_st_xsq_miso_arr
+ );
+
+
+END str;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c12b28090198fd721d9e5f2610f28b6db06b378e
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- . Write a block of xsq data with size (g_nof_crosslets * g_nof_signal_inputs)
+-- to RAM.
+-- Description:
+-- After every in_sosi.sop the st_xsq_dp_to_mm.vhd writes the block of data
+-- to RAM and can be read by MM.
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE,common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY st_xsq_dp_to_mm IS
+ GENERIC (
+ g_nof_crosslets : NATURAL;
+ g_nof_signal_inputs : NATURAL;
+ g_dsp_data_w : NATURAL := 16
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi;
+ mm_mosi : IN t_mem_mosi;
+ mm_miso : OUT t_mem_miso;
+ out_sosi_info : OUT t_dp_sosi
+ );
+END st_xsq_dp_to_mm;
+
+
+ARCHITECTURE rtl OF st_xsq_dp_to_mm IS
+
+ CONSTANT c_nof_data : NATURAL := g_nof_crosslets * g_nof_signal_inputs;
+ CONSTANT c_mm_ram_adr_w : NATURAL := ceil_log2(c_nof_data);
+ CONSTANT c_mm_ram_dat_w : NATURAL := c_nof_complex * g_dsp_data_w;
+
+ SIGNAL ram_wr_mosi : t_mem_mosi := c_mem_mosi_rst;
+
+ SIGNAL reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_sosi_rewired : t_dp_sosi := c_dp_sosi_rst;
+
+BEGIN
+
+ p_in_sosi : PROCESS(in_sosi)
+ BEGIN
+ in_sosi_rewired <= in_sosi;
+ in_sosi_rewired.data( g_dsp_data_w -1 DOWNTO 0) <= in_sosi.re(g_dsp_data_w-1 DOWNTO 0);
+ in_sosi_rewired.data(c_nof_complex * g_dsp_data_w -1 DOWNTO 0) <= in_sosi.im(g_dsp_data_w-1 DOWNTO 0);
+ END PROCESS;
+
+ u_dp_block_to_mm : ENTITY dp_lib.dp_block_to_mm
+ GENERIC MAP(
+ g_data_size => 1,
+ g_step_size => 1,
+ g_nof_data => c_nof_data
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ start_address => 0,
+ mm_mosi => ram_wr_mosi,
+ in_sosi => in_sosi_rewired
+ );
+
+ u_common_paged_ram_r_w : ENTITY common_lib.common_paged_ram_r_w
+ GENERIC MAP(
+ g_data_w => c_mm_ram_dat_w,
+ g_page_sz => c_nof_data,
+ g_wr_start_page => 0,
+ g_rd_start_page => 1
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ wr_next_page => in_sosi.eop,
+ wr_adr => ram_wr_mosi.address(c_mm_ram_adr_w-1 DOWNTO 0),
+ wr_en => ram_wr_mosi.wr,
+ wr_dat => ram_wr_mosi.wrdata(c_mm_ram_dat_w-1 DOWNTO 0),
+ rd_next_page => in_sosi.eop,
+ rd_adr => mm_mosi.address(c_mm_ram_adr_w-1 DOWNTO 0),
+ rd_en => mm_mosi.rd,
+ rd_dat => mm_miso.rddata(c_mm_ram_dat_w-1 DOWNTO 0),
+ rd_val => mm_miso.rdval
+ );
+
+
+ p_control : PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ out_sosi_info <= c_dp_sosi_rst;
+ reg_sosi_info <= c_dp_sosi_rst;
+ ELSIF rising_edge(clk) THEN
+ IF in_sosi.sop = '1' THEN
+ reg_sosi_info <= in_sosi;
+ END IF;
+ IF in_sosi.eop = '1' THEN
+ out_sosi_info <= reg_sosi_info;
+ out_sosi_info.eop <= '1';
+ out_sosi_info.err <= in_sosi.err;
+ ELSE
+ out_sosi_info <= c_dp_sosi_rst;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+END rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0327d6162cd04d63f778800b4d4b2b04422743c3
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -0,0 +1,146 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- . Read a block of xsq data with size (g_nof_crosslets * g_nof_signal_inputs)
+-- from memory mapped (MM) location and stream it as a block of data of
+-- size g_nof_crosslets * g_nof_signal_inputs **2.
+-- Description:
+-- After every in_sosi.sop the st_xsq_mm_to_dp.vhd reads blocks of data
+-- via g_nof_streams mm and outputs it as g_nof_streams parallel streams via
+-- out_sosi_arr. In_sosi.sync is passed on to out_sosi.
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE,common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY st_xsq_mm_to_dp IS
+ GENERIC (
+ g_nof_streams : NATURAL;
+ g_nof_crosslets : NATURAL;
+ g_nof_signal_inputs : NATURAL;
+ g_dsp_data_w : NATURAL := 16
+ );
+ PORT (
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ in_sosi : IN t_dp_sosi; -- sop used as start signal
+ mm_mosi_arr : OUT t_mem_mosi_arr(g_nof_streams -1 DOWNTO 0);
+ mm_miso_arr : IN t_mem_miso_arr(g_nof_streams -1 DOWNTO 0);
+ out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams -1 DOWNTO 0)
+ );
+END st_xsq_mm_to_dp;
+
+
+ARCHITECTURE rtl OF st_xsq_mm_to_dp IS
+
+ TYPE t_reg IS RECORD
+ in_sosi_strobe : t_dp_sosi;
+ out_sosi_ctrl : t_dp_sosi;
+ busy : STD_LOGIC;
+ crosslets_index : NATURAL;
+ in_a_index : NATURAL;
+ in_b_index : NATURAL;
+ END RECORD;
+
+ CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0);
+
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
+ SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
+
+BEGIN
+
+ mm_mosi_arr <= (OTHERS => mm_mosi); -- all mosi are identical.
+
+ u_sosi : PROCESS(r, mm_miso_arr)
+ BEGIN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ out_sosi_arr(I) <= r.out_sosi_ctrl;
+ out_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(mm_miso_arr(I).rddata(g_dsp_data_w-1 DOWNTO 0));
+ out_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(mm_miso_arr(I).rddata(c_nof_complex * g_dsp_data_w -1 DOWNTO g_dsp_data_w));
+ out_sosi_arr(I).valid <= mm_miso_arr(I).rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
+ END LOOP;
+ END PROCESS;
+
+ p_reg : PROCESS(rst, clk)
+ BEGIN
+ IF rst='1' THEN
+ r <= c_reg_rst;
+ ELSIF rising_edge(clk) THEN
+ r <= nxt_r;
+ END IF;
+ END PROCESS;
+
+ p_comb : PROCESS(r, in_sosi)
+ VARIABLE v : t_reg;
+ BEGIN
+ v := r;
+ v.out_sosi_ctrl := c_dp_sosi_rst;
+ mm_mosi.rd <= '0';
+
+ -- initiate next block and capture in_sosi strobe
+ IF r.busy = '0' AND in_sosi.sop = '1' THEN
+ v.busy := '1';
+ v.in_sosi_strobe := in_sosi;
+ ELSIF r.busy = '1' THEN
+ -- continue with block
+ mm_mosi.rd <= '1';
+ mm_mosi.address <= TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
+
+ -- Indices counters to select data order
+ IF r.in_b_index < g_nof_signal_inputs - 1 THEN
+ v.in_b_index := r.in_b_index + 1;
+ ELSE
+ v.in_b_index := 0;
+ IF r.in_a_index < g_nof_signal_inputs - 1 THEN
+ v.in_a_index := r.in_a_index + 1;
+ ELSE
+ v.in_a_index := 0;
+ IF r.crosslets_index < g_nof_crosslets - 1 THEN
+ v.crosslets_index := r.crosslets_index + 1;
+ ELSE
+ v.crosslets_index := 0;
+ END IF;
+ END IF;
+ END IF;
+
+ -- check start of block
+ IF r.crosslets_index = 0 AND r.in_a_index = 0 AND r.in_b_index = 0 THEN
+ v.out_sosi_ctrl.sop := '1';
+ v.out_sosi_ctrl.sync := r.in_sosi_strobe.sync;
+ v.out_sosi_ctrl.bsn := r.in_sosi_strobe.bsn;
+ END IF;
+
+ -- check end of block
+ IF r.crosslets_index >= (g_nof_crosslets - 1) AND r.in_a_index >= (g_nof_signal_inputs - 1) AND r.in_b_index >= (g_nof_signal_inputs - 1) THEN
+ v.out_sosi_ctrl.eop := '1';
+ v.out_sosi_ctrl.err := r.in_sosi_strobe.err;
+ v.busy := '0';
+ END IF;
+ END IF;
+ nxt_r <= v;
+ END PROCESS;
+
+END rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ba841158b07c5399cc8468ae5a96089e98ef9742
--- /dev/null
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -0,0 +1,194 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author : R. vd Walle
+-- Purpose:
+-- Calculate Crosslets Statistics
+-- Description:
+-- Consists of st_xsq_mm_to_dp connected to st_xsq_arr. in_b_arr comes directly
+-- from st_xsq_mm_to_dp but all streams in in_a_arr are x_sosi_arr(0) with corrected
+-- indices done by a process.
+-- Remarks:
+-- . More detail, see:
+-- https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+Correlator
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+ENTITY st_xst IS
+ GENERIC (
+ g_nof_streams : NATURAL := 1;
+ g_nof_crosslets : NATURAL := 1;
+ g_nof_signal_inputs : NATURAL := 2;
+ g_in_data_w : NATURAL := 18; -- width of the data to be accumulated
+ g_stat_data_w : NATURAL := 54; -- statistics accumulator width
+ g_stat_data_sz : NATURAL := 2 -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ -- Streaming
+ in_sosi : IN t_dp_sosi;
+
+ -- DP Memory Mapped
+ mm_mosi_arr : OUT t_mem_mosi_arr(g_nof_streams -1 DOWNTO 0);
+ mm_miso_arr : IN t_mem_miso_arr(g_nof_streams -1 DOWNTO 0);
+
+ -- MM Memory Mapped
+ ram_st_xsq_mosi : IN t_mem_mosi;
+ ram_st_xsq_miso : OUT t_mem_miso
+ );
+END st_xst;
+
+ARCHITECTURE str OF st_xst IS
+
+ CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+ CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+ CONSTANT c_nof_word : NATURAL := g_stat_data_sz*c_nof_statistics*c_nof_complex;
+ CONSTANT c_nof_word_w : NATURAL := ceil_log2(c_nof_word);
+
+ TYPE t_reg IS RECORD
+ busy : STD_LOGIC;
+ in_a_index : NATURAL;
+ in_b_index : NATURAL;
+ END RECORD;
+
+ CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
+
+ SIGNAL r : t_reg;
+ SIGNAL nxt_r : t_reg;
+
+ SIGNAL in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL x_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+
+ SIGNAL reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ SIGNAL reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+BEGIN
+
+ -- MM -> DP
+ st_xsq_mm_to_dp : ENTITY work.st_xsq_mm_to_dp
+ GENERIC MAP(
+ g_nof_streams => g_nof_streams,
+ g_nof_crosslets => g_nof_crosslets,
+ g_nof_signal_inputs => g_nof_signal_inputs,
+ g_dsp_data_w => g_in_data_w
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+ in_sosi => in_sosi,
+ mm_mosi_arr => mm_mosi_arr,
+ mm_miso_arr => mm_miso_arr,
+ out_sosi_arr => x_sosi_arr
+ );
+
+ -- in_b_sosi_arr = x_sosi_arr
+ in_b_sosi_arr <= x_sosi_arr;
+
+ -- Capture x_sosi_arr(0) data
+ reg_x_sosi_0_re(nxt_r.in_b_index) <= x_sosi_arr(0).re;
+ reg_x_sosi_0_im(nxt_r.in_b_index) <= x_sosi_arr(0).im;
+
+ -- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
+ p_in_a : PROCESS(x_sosi_arr, reg_x_sosi_0_re, reg_x_sosi_0_im, nxt_r.in_a_index)
+ BEGIN
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_a_sosi_arr(I) <= x_sosi_arr(0);
+ in_a_sosi_arr(I).re <= reg_x_sosi_0_re(nxt_r.in_a_index);
+ in_a_sosi_arr(I).im <= reg_x_sosi_0_im(nxt_r.in_a_index);
+ END LOOP;
+ END PROCESS;
+
+ -- Register process
+ p_reg : PROCESS(dp_rst, dp_clk)
+ BEGIN
+ IF dp_rst='1' THEN
+ r <= c_reg_rst;
+ ELSIF rising_edge(dp_clk) THEN
+ r <= nxt_r;
+ END IF;
+ END PROCESS;
+
+ -- Combinatorial process to create in_a_index and in_b_index for reoredering x_sosi_arr(0) data.
+ p_comb : PROCESS(r, x_sosi_arr)
+ VARIABLE v : t_reg;
+ BEGIN
+ v := r;
+ -- initiate next block
+ IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN
+ v.busy := '1';
+ -- Continue block
+ ELSIF r.busy = '1' THEN
+ -- Indices counters to select data order
+ IF r.in_b_index < g_nof_signal_inputs - 1 THEN
+ v.in_b_index := r.in_b_index + 1;
+ ELSE
+ v.in_b_index := 0;
+ IF r.in_a_index < g_nof_signal_inputs - 1 THEN
+ v.in_a_index := r.in_a_index + 1;
+ ELSE
+ v.in_a_index := 0;
+ END IF;
+ END IF;
+ END IF;
+ -- End of block
+ IF x_sosi_arr(0).eop = '1' THEN
+ v.busy := '0';
+ v.in_a_index := 0;
+ v.in_b_index := 0;
+ END IF;
+ nxt_r <= v;
+ END PROCESS;
+
+ -- st_xsq instances
+ st_xsq_arr : ENTITY work.st_xsq_arr
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_nof_crosslets => g_nof_crosslets,
+ g_nof_signal_inputs => g_nof_signal_inputs,
+ g_in_data_w => g_in_data_w,
+ g_stat_data_w => g_stat_data_w,
+ g_stat_data_sz => g_stat_data_sz
+ )
+ PORT MAP (
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Streaming
+ in_a_arr => in_a_sosi_arr,
+ in_b_arr => in_b_sosi_arr,
+
+ -- Memory Mapped
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso
+ );
+
+
+END str;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd b/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7d6c17284ffb148c7eafc8f037b1f71e5d585752
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd
@@ -0,0 +1,54 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. vd Walle
+-- Purpose:
+-- Functions used in st_lib
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE tb_st_pkg IS
+
+ FUNCTION func_st_calculate_expected_xsq(a_re, a_im, b_re, b_im : t_integer_arr; N_crosslets, N_int : NATURAL) RETURN t_integer_arr;
+
+END tb_st_pkg;
+
+PACKAGE BODY tb_st_pkg IS
+
+ FUNCTION func_st_calculate_expected_xsq(a_re, a_im, b_re, b_im : t_integer_arr; N_crosslets, N_int : NATURAL) RETURN t_integer_arr IS
+ CONSTANT c_N_s : NATURAL := a_re'LENGTH/N_crosslets;
+ CONSTANT c_xsq : NATURAL := c_N_s * c_N_s;
+ CONSTANT c_N_stat : NATURAL := N_crosslets * c_xsq;
+ VARIABLE v_exp_xsq : t_integer_arr(0 TO c_nof_complex * c_N_stat-1);
+ BEGIN
+
+ FOR N IN 0 TO N_crosslets-1 LOOP
+ FOR I IN 0 TO c_N_s-1 LOOP
+ FOR J IN 0 TO c_N_s-1 LOOP
+ v_exp_xsq(c_nof_complex * (N * c_xsq + I * c_N_s + J) ) := N_int * COMPLEX_MULT_REAL(a_re(N * c_N_s + I), a_im(N * c_N_s + I), b_re(N * c_N_s + J), -1 * b_im(N * c_N_s + J));
+ v_exp_xsq(c_nof_complex * (N * c_xsq + I * c_N_s + J) + 1) := N_int * COMPLEX_MULT_IMAG(a_re(N * c_N_s + I), a_im(N * c_N_s + I), b_re(N * c_N_s + J), -1 * b_im(N * c_N_s + J));
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ RETURN v_exp_xsq;
+ END;
+
+END tb_st_pkg;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8bb8ecc75340026968bfc873f4583172de7391a9
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
@@ -0,0 +1,232 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Testbench for the st_xsq unit.
+--
+-- Usage in non-auto-mode (c_modelsim_start = 0 in python):
+-- > as 5
+-- > run -all
+-- Description:
+-- The tb generates random data to feed into st_xsq. The output is compared to
+-- a pre-calculated expected array of xsq values.
+-- Remark:
+-- . More detail can be found in:
+-- https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+Correlator
+
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_math_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+USE work.tb_st_pkg.ALL;
+
+ENTITY tb_st_xsq IS
+ GENERIC(
+ g_nof_crosslets : NATURAL := 2;
+ g_nof_signal_inputs : NATURAL := 12;
+ g_in_data_w : NATURAL := 16;
+ g_nof_sync : NATURAL := 3;
+ g_stat_data_w : NATURAL := 64; -- statistics accumulator width
+ g_stat_data_sz : NATURAL := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_nof_block_per_sync : NATURAL := 5;
+ g_nof_clk_per_blk : NATURAL := 1024
+ );
+END tb_st_xsq;
+
+ARCHITECTURE tb OF tb_st_xsq IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_rl : NATURAL := 1;
+ CONSTANT c_block_size : NATURAL := g_nof_crosslets * g_nof_signal_inputs;
+ CONSTANT c_random_data_w : NATURAL := 8;
+ CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+ CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+ CONSTANT c_gap_size : NATURAL := g_nof_clk_per_blk - c_nof_statistics;
+
+ CONSTANT c_random_in_a_re : t_integer_arr(0 TO c_block_size-1) := common_math_create_random_arr(c_block_size, c_random_data_w, 100);
+ CONSTANT c_random_in_a_im : t_integer_arr(0 TO c_block_size-1) := common_math_create_random_arr(c_block_size, c_random_data_w, 101);
+ CONSTANT c_random_in_b_re : t_integer_arr(0 TO c_block_size-1) := common_math_create_random_arr(c_block_size, c_random_data_w, 102);
+ CONSTANT c_random_in_b_im : t_integer_arr(0 TO c_block_size-1) := common_math_create_random_arr(c_block_size, c_random_data_w, 103);
+
+ CONSTANT c_expected_xsq : t_integer_arr(0 TO c_nof_statistics * c_nof_complex-1) := func_st_calculate_expected_xsq(c_random_in_a_re, c_random_in_a_im, c_random_in_b_re, c_random_in_b_im, g_nof_crosslets, g_nof_block_per_sync);
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+ CONSTANT c_dp_pps_period : NATURAL := 64;
+
+ SIGNAL tb_end : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '1';
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '1';
+
+ SIGNAL st_en : STD_LOGIC := '1';
+ SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_sosi_a : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL in_sosi_b : t_dp_sosi := c_dp_sosi_rst;
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL st_xsq_out_arr : t_slv_32_arr(0 TO c_nof_statistics * c_nof_complex * g_stat_data_sz-1) := (OTHERS => (OTHERS => '0'));
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Clock and reset generation
+ ----------------------------------------------------------------------------
+ mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
+
+ dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
+
+ ------------------------------------------------------------------------------
+ -- MM Stimuli
+ ------------------------------------------------------------------------------
+ p_mm_stimuli : PROCESS
+ BEGIN
+ FOR I IN 0 TO g_nof_sync -1 LOOP
+ proc_common_wait_until_lo_hi(dp_clk, st_sosi.sync);
+ END LOOP;
+ proc_common_wait_some_cycles(dp_clk, g_nof_clk_per_blk);
+ proc_common_wait_some_cycles(dp_clk, 20);
+ -- read ram
+ proc_mem_read_ram(0, c_nof_statistics * c_nof_complex * g_stat_data_sz, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso, st_xsq_out_arr);
+ WAIT;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Data blocks
+ ------------------------------------------------------------------------------
+ p_st_stimuli : PROCESS
+ VARIABLE v_re : NATURAL := 0;
+ VARIABLE v_im : NATURAL := 0;
+ BEGIN
+ tb_end <= '0';
+ st_sosi <= c_dp_sosi_rst;
+ proc_common_wait_until_low(dp_clk, dp_rst);
+
+ -- Run some sync intervals with DSP counter data for the real and imag fields
+ WAIT UNTIL rising_edge(dp_clk);
+ proc_common_wait_some_cycles(dp_clk, 7);
+ FOR I IN 0 TO g_nof_sync-1 LOOP
+ proc_dp_gen_block_data(c_rl, FALSE, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '1', "0", dp_clk, st_en, st_siso, st_sosi); -- next sync
+ st_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, c_gap_size);
+ FOR J IN 0 TO g_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
+ proc_dp_gen_block_data(c_rl, FALSE, g_in_data_w, g_in_data_w, 0, v_re, v_im, c_nof_statistics, 0, 0, '0', "0", dp_clk, st_en, st_siso, st_sosi); -- no sync
+ st_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, c_gap_size);
+ END LOOP;
+ END LOOP;
+ st_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ in_sosi_a.sync <= st_sosi.sync;
+ in_sosi_b.sync <= st_sosi.sync;
+ in_sosi_a.sop <= st_sosi.sop;
+ in_sosi_b.sop <= st_sosi.sop;
+ in_sosi_a.eop <= st_sosi.eop;
+ in_sosi_b.eop <= st_sosi.eop;
+ in_sosi_a.valid <= st_sosi.valid;
+ in_sosi_b.valid <= st_sosi.valid;
+
+ p_random_stimuli : PROCESS
+ BEGIN
+ FOR S IN 0 TO g_nof_sync * g_nof_block_per_sync -1 LOOP
+ WAIT UNTIL rising_edge(st_sosi.sop);
+ FOR N IN 0 TO g_nof_crosslets -1 LOOP
+ FOR I IN 0 TO g_nof_signal_inputs -1 LOOP
+ FOR J IN 0 TO g_nof_signal_inputs -1 LOOP
+ in_sosi_a.re <= TO_DP_DSP_DATA(c_random_in_a_re(N * g_nof_signal_inputs + I));
+ in_sosi_a.im <= TO_DP_DSP_DATA(c_random_in_a_im(N * g_nof_signal_inputs + I));
+ in_sosi_b.re <= TO_DP_DSP_DATA(c_random_in_b_re(N * g_nof_signal_inputs + J));
+ in_sosi_b.im <= TO_DP_DSP_DATA(c_random_in_b_im(N * g_nof_signal_inputs + J));
+ proc_common_wait_some_cycles(dp_clk, 1);
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Verification
+ ------------------------------------------------------------------------------
+ p_verify : PROCESS
+ BEGIN
+ proc_common_wait_until_high(mm_clk, ram_st_xsq_miso.rdval);
+ proc_common_wait_some_cycles(mm_clk, 2* c_nof_statistics * c_nof_complex * g_stat_data_sz + 10);
+ FOR I IN 0 TO c_nof_statistics * c_nof_complex -1 LOOP
+ ASSERT TO_SINT(st_xsq_out_arr(I*2)) = c_expected_xsq(I) REPORT "WRONG XSQ DATA" SEVERITY ERROR; -- Only read low part of statistic
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ ----------------------------------------------------------------------------
+ -- DUT: Device Under Test
+ ----------------------------------------------------------------------------
+ u_dut : ENTITY work.st_xsq
+ GENERIC MAP(
+ g_nof_signal_inputs => g_nof_signal_inputs,
+ g_nof_crosslets => g_nof_crosslets,
+ g_in_data_w => g_in_data_w,
+ g_stat_data_w => g_stat_data_w,
+ g_stat_data_sz => g_stat_data_sz
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Streaming
+ in_a => in_sosi_a,
+ in_b => in_sosi_b,
+
+ -- Memory Mapped
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso
+ );
+
+END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..53d63fe0aa937b6241052077a3594b7e99193d8c
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
@@ -0,0 +1,280 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Testbench for the st_xst unit.
+--
+-- Usage in non-auto-mode (c_modelsim_start = 0 in python):
+-- > as 5
+-- > run -all
+-- Description:
+-- The tb generates random data to feed into st_xst. The output is compared to
+-- a pre-calculated expected array of xsq values.
+-- Remark:
+-- . More detail can be found in:
+-- https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+Correlator
+
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_math_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+USE work.tb_st_pkg.ALL;
+
+ENTITY tb_st_xst IS
+ GENERIC(
+ g_nof_streams : NATURAL := 9;
+ g_nof_crosslets : NATURAL := 2;
+ g_nof_signal_inputs : NATURAL := 12;
+ g_in_data_w : NATURAL := 16;
+ g_nof_sync : NATURAL := 3;
+ g_stat_data_w : NATURAL := 64; -- statistics accumulator width
+ g_stat_data_sz : NATURAL := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+ g_nof_block_per_sync : NATURAL := 5;
+ g_nof_clk_per_blk : NATURAL := 1024
+ );
+END tb_st_xst;
+
+ARCHITECTURE tb OF tb_st_xst IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_rl : NATURAL := 1;
+ CONSTANT c_block_size : NATURAL := g_nof_crosslets * g_nof_signal_inputs;
+ CONSTANT c_random_data_w : NATURAL := 8;
+ CONSTANT c_xsq : NATURAL := g_nof_signal_inputs * g_nof_signal_inputs;
+ CONSTANT c_nof_statistics : NATURAL := g_nof_crosslets * c_xsq;
+ CONSTANT c_nof_statistics_w : NATURAL := ceil_log2(c_nof_statistics);
+ CONSTANT c_nof_statistics_mem_size : NATURAL := c_nof_complex * 2**c_nof_statistics_w;
+ CONSTANT c_single_stream_mem_size : NATURAL := c_nof_complex * c_nof_statistics * g_stat_data_sz;
+ CONSTANT c_total_mem_size : NATURAL := g_nof_streams * c_nof_statistics_mem_size * g_stat_data_sz;
+ CONSTANT c_random_seed : NATURAL := 100;
+
+ CONSTANT c_mm_ram : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(c_block_size),
+ dat_w => c_nof_complex * g_in_data_w,
+ nof_dat => c_block_size,
+ init_sl => '0'); -- MM side : sla_in, sla_out
+
+ TYPE t_random_in_2arr IS ARRAY (INTEGER RANGE <>) OF t_integer_arr(0 TO c_block_size-1);
+ TYPE t_xsq_2arr IS ARRAY (INTEGER RANGE <>) OF t_integer_arr(0 TO c_nof_statistics * c_nof_complex-1);
+ TYPE t_xsq_out_2arr IS ARRAY (INTEGER RANGE <>) OF t_slv_32_arr(0 TO c_single_stream_mem_size-1);
+
+ SIGNAL random_in_re_2arr : t_random_in_2arr(0 TO g_nof_streams-1);
+ SIGNAL random_in_im_2arr : t_random_in_2arr(0 TO g_nof_streams-1);
+ SIGNAL expected_xsq_2arr : t_xsq_2arr(0 TO g_nof_streams-1);
+
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+
+ SIGNAL tb_end : STD_LOGIC;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '1';
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '1';
+
+ SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL st_xst_mm_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL st_xst_mm_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+
+ SIGNAL in_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+
+ ----------------------------------------------------------------------------
+ -- Output array
+ ----------------------------------------------------------------------------
+ SIGNAL st_xsq_out_2arr : t_xsq_out_2arr(0 TO g_nof_streams-1) := (OTHERS => (OTHERS => (OTHERS => '0')));
+
+BEGIN
+ -- random input and expected xsq
+ gen_in_exp : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ random_in_re_2arr(I) <= common_math_create_random_arr(c_block_size, c_random_data_w, c_random_seed+2*I);
+ random_in_im_2arr(I) <= common_math_create_random_arr(c_block_size, c_random_data_w, c_random_seed+2*I+1);
+ expected_xsq_2arr(I) <= func_st_calculate_expected_xsq(random_in_re_2arr(0), random_in_im_2arr(0), random_in_re_2arr(I), random_in_im_2arr(I), g_nof_crosslets, g_nof_block_per_sync);
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- Clock and reset generation
+ ----------------------------------------------------------------------------
+ mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
+
+ dp_clk <= NOT dp_clk OR tb_end AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
+
+ ------------------------------------------------------------------------------
+ -- in mosi Stimuli
+ ------------------------------------------------------------------------------
+ gen_p_in_mosi : FOR M IN 0 TO g_nof_streams-1 GENERATE
+ p_in_mosi : PROCESS
+ VARIABLE v_ram_arr : t_slv_32_arr(c_block_size-1 DOWNTO 0);
+ BEGIN
+ -- write random data to ram
+ proc_common_wait_until_low(mm_clk, mm_rst);
+ FOR J IN 0 TO c_block_size-1 LOOP
+ v_ram_arr(J) := TO_SVEC(random_in_im_2arr(M)(J), g_in_data_w) & TO_SVEC(random_in_re_2arr(M)(J), g_in_data_w);
+ END LOOP;
+ proc_mem_write_ram(v_ram_arr, mm_clk, in_mosi_arr(M));
+ WAIT;
+ END PROCESS;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- MM Stimuli
+ ------------------------------------------------------------------------------
+ gen_mm_stimuli : FOR M IN 0 TO g_nof_streams-1 GENERATE
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- read statistics
+ FOR I IN 0 TO g_nof_sync -1 LOOP
+ proc_common_wait_until_lo_hi(dp_clk, in_sosi.sync);
+ END LOOP;
+ proc_common_wait_some_cycles(dp_clk, g_nof_clk_per_blk);
+ proc_common_wait_some_cycles(dp_clk, 20);
+ proc_common_wait_some_cycles(mm_clk, 2 * M * c_single_stream_mem_size);
+ proc_mem_read_ram(M*c_nof_statistics_mem_size, c_single_stream_mem_size, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso, st_xsq_out_2arr(M));
+ WAIT;
+ END PROCESS;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Data blocks
+ ------------------------------------------------------------------------------
+ p_in_sosi : PROCESS
+ BEGIN
+ tb_end <= '0';
+ in_sosi <= c_dp_sosi_rst;
+ proc_common_wait_until_low(dp_clk, dp_rst);
+
+ -- Run some sync intervals with DSP counter data for the real and imag fields
+ WAIT UNTIL rising_edge(dp_clk);
+ proc_common_wait_some_cycles(dp_clk, 7);
+ FOR I IN 0 TO g_nof_sync-1 LOOP
+ in_sosi.sop <= '1';
+ in_sosi.eop <= '1';
+ in_sosi.sync <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ in_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, g_nof_clk_per_blk-1);
+ FOR J IN 0 TO g_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
+ in_sosi.sop <= '1';
+ in_sosi.eop <= '1';
+ proc_common_wait_some_cycles(dp_clk, 1);
+ in_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, g_nof_clk_per_blk-1);
+ END LOOP;
+ END LOOP;
+ in_sosi <= c_dp_sosi_rst;
+ proc_common_wait_some_cycles(dp_clk, 100);
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Verification
+ ------------------------------------------------------------------------------
+ p_verify : PROCESS
+ BEGIN
+ proc_common_wait_until_high(mm_clk, ram_st_xsq_miso.rdval);
+ proc_common_wait_some_cycles(mm_clk, 2* c_total_mem_size + 10);
+ FOR M IN 0 TO g_nof_streams -1 LOOP
+ FOR I IN 0 TO c_nof_statistics * c_nof_complex -1 LOOP
+ ASSERT TO_SINT(st_xsq_out_2arr(M)(g_stat_data_sz * I)) = expected_xsq_2arr(M)(I) REPORT "WRONG XSQ DATA" SEVERITY ERROR; -- Only read low part of statistic
+ END LOOP;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+
+ ----------------------------------------------------------------------------
+ -- RAMs that contain a block of crosslets for each stream
+ ----------------------------------------------------------------------------
+ gen_ram : FOR I IN 0 TO g_nof_streams-1 GENERATE
+ u_ram : ENTITY common_lib.common_ram_cr_cw
+ GENERIC MAP(
+ g_ram => c_mm_ram
+ )
+ PORT MAP(
+ wr_rst => mm_rst,
+ wr_clk => mm_clk,
+ wr_en => in_mosi_arr(I).wr,
+ wr_adr => in_mosi_arr(I).address(c_mm_ram.adr_w-1 DOWNTO 0),
+ wr_dat => in_mosi_arr(I).wrdata(c_mm_ram.dat_w-1 DOWNTO 0),
+
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ rd_en => st_xst_mm_mosi_arr(I).rd,
+ rd_adr => st_xst_mm_mosi_arr(I).address(c_mm_ram.adr_w-1 DOWNTO 0),
+ rd_dat => st_xst_mm_miso_arr(I).rddata(c_mm_ram.dat_w-1 DOWNTO 0),
+ rd_val => st_xst_mm_miso_arr(I).rdval
+ );
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- DUT: Device Under Test
+ ----------------------------------------------------------------------------
+ u_dut : ENTITY work.st_xst
+ GENERIC MAP(
+ g_nof_streams => g_nof_streams,
+ g_nof_signal_inputs => g_nof_signal_inputs,
+ g_nof_crosslets => g_nof_crosslets,
+ g_in_data_w => g_in_data_w,
+ g_stat_data_w => g_stat_data_w,
+ g_stat_data_sz => g_stat_data_sz
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ -- Streaming
+ in_sosi => in_sosi,
+
+ -- DP Memory Mapped
+ mm_mosi_arr => st_xst_mm_mosi_arr,
+ mm_miso_arr => st_xst_mm_miso_arr,
+
+ -- Memory Mapped
+ ram_st_xsq_mosi => ram_st_xsq_mosi,
+ ram_st_xsq_miso => ram_st_xsq_miso
+ );
+
+END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ab1b84dfa8f35bea402a0d2be7c582845ebb8731
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
@@ -0,0 +1,56 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Test multiple instances of tb_st_xsq
+-- Usage:
+-- > as 10
+-- > run -all
+--
+-- Description: See tb_st_xsq
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_st_xsq IS
+END tb_tb_st_xsq;
+
+ARCHITECTURE tb OF tb_tb_st_xsq IS
+
+ CONSTANT c_nof_sync : NATURAL := 3;
+ CONSTANT c_dsp_data_w : NATURAL := 16;
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+-- GENERICS:
+-- g_nof_crosslets : NATURAL := 2;
+-- g_nof_signal_inputs : NATURAL := 12;
+-- g_in_data_w : NATURAL := 16;
+-- g_nof_sync : NATURAL := 3;
+-- g_stat_data_w : NATURAL := 64; -- statistics accumulator width
+-- g_stat_data_sz : NATURAL := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+-- g_nof_block_per_sync : NATURAL := 5;
+-- g_nof_clk_per_blk : NATURAL := 1024
+
+ u_sdp : ENTITY work.tb_st_xsq GENERIC MAP (1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
+ u_max : ENTITY work.tb_st_xsq GENERIC MAP (16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+
+END tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e62c61e10c32fe8cfa0d2a604f2c8cf3bbd4a9ee
--- /dev/null
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
@@ -0,0 +1,60 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Test multiple instances of tb_st_xst
+-- Usage:
+-- > as 10
+-- > run -all
+--
+-- Description: See tb_st_xst
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_st_xst IS
+END tb_tb_st_xst;
+
+ARCHITECTURE tb OF tb_tb_st_xst IS
+
+ CONSTANT c_nof_sync : NATURAL := 3;
+ CONSTANT c_dsp_data_w : NATURAL := 16;
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+-- GENERICS:
+-- g_nof_streams : NATURAL := 9;
+-- g_nof_crosslets : NATURAL := 2;
+-- g_nof_signal_inputs : NATURAL := 12;
+-- g_in_data_w : NATURAL := 16;
+-- g_nof_sync : NATURAL := 3;
+-- g_stat_data_w : NATURAL := 64; -- statistics accumulator width
+-- g_stat_data_sz : NATURAL := 2; -- statistics word width >= statistics accumulator width and fit in a power of 2 multiple 32b MM words
+-- g_nof_block_per_sync : NATURAL := 5;
+-- g_nof_clk_per_blk : NATURAL := 1024
+
+ u_sdp : ENTITY work.tb_st_xst GENERIC MAP (9, 1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
+ u_sdp_one : ENTITY work.tb_st_xst GENERIC MAP (1, 1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
+ u_sdp_mult_crosslets : ENTITY work.tb_st_xst GENERIC MAP (9, 7, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
+ -- Note: u_max shows that the dut will skip sync periods if nof_statistics is not < g_nof_clk_per_blk
+ u_max : ENTITY work.tb_st_xst GENERIC MAP (2, 16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
+
+END tb;