diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8a5ce16825a7393c3b9704fd7b9ca3e21f6c1edd
--- /dev/null
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -0,0 +1,318 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_ring_bsp using WG data.
+--
+-- Description:
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG via reg_diag_wg with:
+-- freq = 19.921875MHz
+-- ampl = 0.5 * 2**13
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
+-- to trigger start of WG at BSN.
+--
+-- 3) Read subband statistics (SST)
+--
+-- 4) Read beamlet statistics (BST) via ram_st_bst and verify with
+-- c_exp_beamlet_power_sp_0 at c_sdp_N_sub-1 - c_subband_sp_0.
+-- View sp_beamlet_power_0 in Wave window
+-- 5) Compare SST with BST.
+-- 6) Verify 10GbE output.
+--
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, tech_pll_lib, tr_10GbE_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_ring_bsp IS
+END tb_lofar2_unb2b_ring_bsp;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_ring_bsp IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+
+
+ -- MM
+ CONSTANT c_mm_file_reg_sdp_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
+ CONSTANT c_mm_file_reg_dp_xonoff_bg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_BG";
+ CONSTANT c_mm_file_reg_dp_xonoff_from_lane : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_FROM_LANE";
+ CONSTANT c_mm_file_reg_bsn_monitor_rx : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RX";
+ CONSTANT c_mm_file_reg_bsn_monitor_tx : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_TX";
+ CONSTANT c_mm_file_reg_bg_ctrl : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DIAG_BG_RING";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+
+ -- 10GbE
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '1';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ SIGNAL SA_CLK : STD_LOGIC := '1';
+ SIGNAL si_lpbk_0 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_1 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ SIGNAL si_lpbk_2 : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ jesd204b_sysref <= pps;
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_ring_bsp : ENTITY work.top
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_ring_bsp",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => si_lpbk_0,
+ QSFP_0_TX => si_lpbk_0,
+ -- ring transceivers
+ RING_0_RX => si_lpbk_2,
+ RING_0_TX => si_lpbk_1,
+ RING_1_RX => si_lpbk_1,
+ RING_1_TX => si_lpbk_2,
+
+ -- LEDs
+ QSFP_LED => open
+
+ );
+
+ u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => pps_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => pps_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => pps_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => si_lpbk_0(0),
+
+ src_out_arr(0) => tr_10GbE_src_out
+
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_power_sum_0 : REAL;
+ VARIABLE v_sp_beamlet_power : REAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+
+ ----------------------------------------------------------------------------
+ -- Enable UDP offload (dp_xonoff) of beamset 0
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_bg,0 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_from_lane,0 , 0, tb_clk);
+
+ ----------------------------------------------------------------------------
+ -- Enable BG
+ ----------------------------------------------------------------------------
+ -- 0: enable[1:0] --> off=0, enable=1, enable_pps=3
+ -- 1: samples_per_packet[15:0]
+ -- 2: Blocks_per_sync[15:0]
+ -- 3: Gapsize[15:0]
+ -- 4: Mem_low_adrs[7:0]
+ -- 5: Mem_high_adrs[7:0]
+ -- 6: BSN_init[31:0]
+ -- 7: BSN_init[63:32]
+
+
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 2, c_nof_block_per_sync, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 3, 250 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 4, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 5, 127 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0 , tb_clk);
+
+
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3 , tb_clk);
+ proc_common_wait_some_cycles(ext_clk, 5* c_nof_block_per_sync * 1000);
+
+ ---------------------------------------------------------------------------
+ -- Read TX monitor
+ ---------------------------------------------------------------------------
+ FOR I IN 0 TO 8*128 LOOP
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_tx, I, rd_data, tb_clk);
+ END LOOP;
+
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index 33507f51bf32ace02a46dd204711306190958f92..212c386342d030d75eb45cba1bde779e88044f79 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -319,8 +319,12 @@ ARCHITECTURE str OF top IS
SIGNAL ta2_unb2b_10GbE_ring_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
SIGNAL ta2_unb2b_10GbE_ring_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL ta2_unb2b_10GbE_ring_tx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
- SIGNAL ta2_unb2b_10GbE_ring_rx_serial_r : STD_LOGIC_VECTOR(c_nof_streams_ring -1 DOWNTO 0);
+
+ SIGNAL ta2_unb2b_10GbE_ring_ch_src_out_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_src_in_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+ SIGNAL ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
SIGNAL ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
@@ -479,27 +483,33 @@ BEGIN
-- and the odd indices containing RING_1 (receive from the right).
-- For transmitting we need to have the even indices containing RING_1 (transmit to the right) and the odd having RING_0 (transmit to the left)
gen_ring_lanes : FOR I IN 0 TO c_ring_bus_w -1 GENERATE
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2) <= unb2b_board_ring_io_serial_rx_arr(I);
- ta2_unb2b_10GbE_ring_rx_serial_r(I*2 +1) <= unb2b_board_ring_io_serial_rx_arr(I+c_ring_bus_w);
- unb2b_board_ring_io_serial_tx_arr(I) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2 +1);
- unb2b_board_ring_io_serial_tx_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_tx_serial_r(I*2);
+ -- RX side
+ ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I) <= ta2_unb2b_10GbE_ring_src_out_arr(I);
+ ta2_unb2b_10GbE_ring_ch_src_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_src_out_arr(I+c_ring_bus_w);
+ ta2_unb2b_10GbE_ring_src_in_arr(I) <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I);
+ ta2_unb2b_10GbE_ring_src_in_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_ch_src_in_arr(2*I+1);
+ -- TX side
+ ta2_unb2b_10GbE_ring_snk_in_arr(I) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I+1);
+ ta2_unb2b_10GbE_ring_snk_in_arr(I+c_ring_bus_w) <= ta2_unb2b_10GbE_ring_ch_snk_in_arr(2*I);
+ ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I+1) <= ta2_unb2b_10GbE_ring_snk_out_arr(I);
+ ta2_unb2b_10GbE_ring_ch_snk_out_arr(2*I) <= ta2_unb2b_10GbE_ring_snk_out_arr(I+c_ring_bus_w);
END GENERATE;
- -- Wire ring and qsfp to one array
- ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
- ta2_unb2b_10GbE_snk_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_snk_in_arr;
- ta2_unb2b_10GbE_qsfp_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ -- Wire 8 ring and 4 qsfp to one array of 12 10GbE
+ ta2_unb2b_10GbE_snk_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_snk_in_arr;
+ ta2_unb2b_10GbE_snk_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_snk_in_arr;
+ ta2_unb2b_10GbE_qsfp_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_snk_out_arr <= ta2_unb2b_10GbE_snk_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
- ta2_unb2b_10GbE_qsfp_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
- ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_src_in_arr;
- ta2_unb2b_10GbE_src_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_src_in_arr;
+ ta2_unb2b_10GbE_qsfp_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_nof_streams_qsfp-1 DOWNTO 0);
+ ta2_unb2b_10GbE_ring_src_out_arr <= ta2_unb2b_10GbE_src_out_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ ta2_unb2b_10GbE_src_in_arr(c_nof_streams_qsfp-1 DOWNTO 0) <= ta2_unb2b_10GbE_qsfp_src_in_arr;
+ ta2_unb2b_10GbE_src_in_arr(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_src_in_arr;
ta2_unb2b_10GbE_rx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0) <= unb2b_board_front_io_serial_rx_arr;
- ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= ta2_unb2b_10GbE_ring_rx_serial_r;
+ ta2_unb2b_10GbE_rx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp) <= unb2b_board_ring_io_serial_rx_arr;
unb2b_board_front_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_nof_streams_qsfp-1 DOWNTO 0);
- ta2_unb2b_10GbE_ring_tx_serial_r <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
+ unb2b_board_ring_io_serial_tx_arr <= ta2_unb2b_10GbE_tx_serial_r(c_max_nof_mac-1 DOWNTO c_nof_streams_qsfp);
-- tr_10GbE
u_ta2_unb2b_10GbE : ENTITY ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
@@ -526,7 +536,6 @@ BEGIN
snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
);
-
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
@@ -631,6 +640,11 @@ BEGIN
-----------------------------------------------------------------------------
-- kernel clock crossing for tx_monitors
-----------------------------------------------------------------------------
+ gen_tx_mon_sim_wires: IF g_sim = TRUE GENERATE -- bypass OpenCL kernel in simulation
+ kernel_tx_monitor_sosi_arr <= kernel_to_lane_sosi_arr;
+ kernel_to_lane_siso_arr <= kernel_tx_monitor_siso_arr;
+ END GENERATE;
+
u_ta2_channel_cross_tx_monitor : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => g_nof_lanes,
@@ -918,6 +932,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Freeze wrapper instantiation
-----------------------------------------------------------------------------
+ gen_opencl: IF g_sim = FLASE GENERATE
freeze_wrapper_inst : freeze_wrapper
PORT MAP(
board_kernel_clk_clk => board_kernel_clk_clk,
@@ -943,61 +958,61 @@ BEGIN
board_kernel_register_mem_writedata => board_kernel_register_mem_writedata,
board_kernel_register_mem_byteenable => board_kernel_register_mem_byteenable,
- board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_src_out_arr(0).valid,
- board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_src_in_arr(0).ready,
- board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_snk_in_arr(0).valid,
- board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_snk_out_arr(0).ready,
-
- board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_src_out_arr(1).valid,
- board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_src_in_arr(1).ready,
- board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_snk_in_arr(1).valid,
- board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_snk_out_arr(1).ready,
-
- board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_src_out_arr(2).valid,
- board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_src_in_arr(2).ready,
- board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_snk_in_arr(2).valid,
- board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_snk_out_arr(2).ready,
-
- board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_src_out_arr(3).valid,
- board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_src_in_arr(3).ready,
- board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_snk_in_arr(3).valid,
- board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_snk_out_arr(3).ready,
-
- board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_src_out_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_src_out_arr(4).valid,
- board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_src_in_arr(4).ready,
- board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_snk_in_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_snk_in_arr(4).valid,
- board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_snk_out_arr(4).ready,
-
- board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_src_out_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_src_out_arr(5).valid,
- board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_src_in_arr(5).ready,
- board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_snk_in_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_snk_in_arr(5).valid,
- board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_snk_out_arr(5).ready,
-
- board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_src_out_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_src_out_arr(6).valid,
- board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_src_in_arr(6).ready,
- board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_snk_in_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_snk_in_arr(6).valid,
- board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_snk_out_arr(6).ready,
-
- board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_src_out_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_src_out_arr(7).valid,
- board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_src_in_arr(7).ready,
- board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_snk_in_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
- board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_snk_in_arr(7).valid,
- board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_snk_out_arr(7).ready,
+ board_kernel_stream_src_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(0).valid,
+ board_kernel_stream_src_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(0).ready,
+ board_kernel_stream_snk_10GbE_ring_0_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_0_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(0).valid,
+ board_kernel_stream_snk_10GbE_ring_0_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(0).ready,
+
+ board_kernel_stream_src_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(1).valid,
+ board_kernel_stream_src_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(1).ready,
+ board_kernel_stream_snk_10GbE_ring_1_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_1_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(1).valid,
+ board_kernel_stream_snk_10GbE_ring_1_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(1).ready,
+
+ board_kernel_stream_src_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(2).valid,
+ board_kernel_stream_src_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(2).ready,
+ board_kernel_stream_snk_10GbE_ring_2_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_2_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(2).valid,
+ board_kernel_stream_snk_10GbE_ring_2_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(2).ready,
+
+ board_kernel_stream_src_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(3).valid,
+ board_kernel_stream_src_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(3).ready,
+ board_kernel_stream_snk_10GbE_ring_3_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_3_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(3).valid,
+ board_kernel_stream_snk_10GbE_ring_3_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(3).ready,
+
+ board_kernel_stream_src_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(4).valid,
+ board_kernel_stream_src_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(4).ready,
+ board_kernel_stream_snk_10GbE_ring_4_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_4_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(4).valid,
+ board_kernel_stream_snk_10GbE_ring_4_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(4).ready,
+
+ board_kernel_stream_src_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(5).valid,
+ board_kernel_stream_src_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(5).ready,
+ board_kernel_stream_snk_10GbE_ring_5_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_5_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(5).valid,
+ board_kernel_stream_snk_10GbE_ring_5_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(5).ready,
+
+ board_kernel_stream_src_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(6).valid,
+ board_kernel_stream_src_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(6).ready,
+ board_kernel_stream_snk_10GbE_ring_6_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_6_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(6).valid,
+ board_kernel_stream_snk_10GbE_ring_6_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(6).ready,
+
+ board_kernel_stream_src_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_src_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_src_out_arr(7).valid,
+ board_kernel_stream_src_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_src_in_arr(7).ready,
+ board_kernel_stream_snk_10GbE_ring_7_data => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
+ board_kernel_stream_snk_10GbE_ring_7_valid => ta2_unb2b_10GbE_ring_ch_snk_in_arr(7).valid,
+ board_kernel_stream_snk_10GbE_ring_7_ready => ta2_unb2b_10GbE_ring_ch_snk_out_arr(7).ready,
board_kernel_stream_src_10GbE_qsfp_0_data => ta2_unb2b_10GbE_qsfp_src_out_arr(0).data(c_kernel_10gbe_channel_w-1 DOWNTO 0),
board_kernel_stream_src_10GbE_qsfp_0_valid => ta2_unb2b_10GbE_qsfp_src_out_arr(0).valid,
@@ -1152,9 +1167,27 @@ BEGIN
);
- i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
- i_kernel_rst <= NOT board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
+ i_kernel_rst <= NOT board_kernel_reset_reset_n; -- qsys output used to reset all OpenCL BSP components
+ END GENERATE;
+ gen_sim: IF g_sim = TRUE GENERATE
+ i_kernel_rst <= NOT i_reset_n;
+
+ u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ u_mm_file_reg_dp_xonoff_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_BG")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_bg_mosi, reg_dp_xonoff_bg_miso );
+ u_mm_file_reg_dp_xonoff_from_lane: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF_FROM_LANE")
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_from_lane_mosi, reg_dp_xonoff_from_lane_miso );
+ u_mm_file_reg_bsn_monitor_rx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_mosi, reg_bsn_monitor_v2_rx_miso );
+ u_mm_file_reg_bsn_monitor_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_TX")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_tx_mosi, reg_bsn_monitor_v2_tx_miso );
+ u_mm_file_reg_bg_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_RING")
+ PORT MAP(mm_rst, mm_clk, reg_bg_ctrl_mosi, reg_bg_ctrl_miso );
+ END GENERATE
+
+ i_reset_n <= NOT mm_rst; -- First reset OpenCL components in qsys (board)
-- Kernel should start later than BSP. Delaying the reset from the qsys output to form the reset of the OpenCL kernel.
-- This way it is ensured the OpenCL kernel does not start reading/writing data before the components in the OpenCL BSP are ready.
u_common_areset : ENTITY common_lib.common_areset
@@ -1167,8 +1200,7 @@ BEGIN
clk => board_kernel_clk_clk,
out_rst => board_kernel_reset_reset_n_in
);
-
- -----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl_unb2b_board : ENTITY unb2b_board_lib.ctrl_unb2b_board
@@ -1296,6 +1328,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
+ gen_board: IF g_sim = FALSE GENERATE
board_inst : board
PORT MAP (
clk_clk => mm_clk,
@@ -1481,6 +1514,6 @@ BEGIN
reg_ta2_unb2b_mm_io_writedata_export => reg_ta2_unb2b_mm_io_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_ta2_unb2b_mm_io_waitrequest_export => reg_ta2_unb2b_mm_io_miso.waitrequest
);
-
+ END GENERATE;
END str;