diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd index 019ef371cf1d43e5f7654c6340c7f5908f6aaf0a..f3cf793ce5b7dd0d3d4994794e26195c5a494494 100644 --- a/libraries/base/common/src/vhdl/common_pulser.vhd +++ b/libraries/base/common/src/vhdl/common_pulser.vhd @@ -30,9 +30,15 @@ USE common_lib.common_pkg.ALL; -- The pulse period can dynamically be set via the input pulse_period. -- Default pulse_period = g_pulse_period, to also support static setting of -- the pulse period. The pulse_clr can be used to synchronise the pulser. +-- The g_pulse_phase defines when the first pulse occurs after rst release: +-- . g_pulse_phase=0 : first pulse after g_pulse_period cycles +-- . g_pulse_phase=g_pulse_period : first pulse after g_pulse_period cycles +-- . g_pulse_phase=g_pulse_period-1 : first pulse after 1 cycles +-- . g_pulse_phase=g_pulse_period-N : first pulse after N cycles ENTITY common_pulser IS GENERIC ( - g_pulse_period : NATURAL := 25000 -- nof clk cycles to get pulse period + g_pulse_period : NATURAL := 25000; -- nof clk cycles to get pulse period + g_pulse_phase : INTEGER := 0 ); PORT ( rst : IN STD_LOGIC; @@ -76,6 +82,7 @@ BEGIN u_cnt : ENTITY common_lib.common_counter GENERIC MAP ( + g_init => g_pulse_phase, g_width => c_pulse_period_w ) PORT MAP ( diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd index 5a910d88f1d1ebd0a7663f9380835fc05c7822bd..6a479b914da0b33d32ba4047699fcba94888ca20 100644 --- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd +++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd @@ -28,9 +28,9 @@ USE common_lib.common_pkg.ALL; ENTITY common_pulser_us_ms_s IS GENERIC ( - g_pulse_us : NATURAL := 125/(10**6); -- nof clk cycles to get us period - g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period - g_pulse_s : NATURAL := 1000 -- nof pulse_ms pulses to get s period + g_pulse_us : NATURAL := 125; -- nof clk cycles to get us period + g_pulse_ms : NATURAL := 1000; -- nof pulse_us pulses to get ms period + g_pulse_s : NATURAL := 1000 -- nof pulse_ms pulses to get s period ); PORT ( rst : IN STD_LOGIC; @@ -78,7 +78,8 @@ BEGIN u_common_pulser_us : ENTITY common_lib.common_pulser GENERIC MAP ( - g_pulse_period => g_pulse_us + g_pulse_period => g_pulse_us, + g_pulse_phase => g_pulse_us-1 ) PORT MAP ( rst => rst, @@ -91,7 +92,8 @@ BEGIN u_common_pulser_ms : ENTITY common_lib.common_pulser GENERIC MAP ( - g_pulse_period => g_pulse_ms + g_pulse_period => g_pulse_ms, + g_pulse_phase => g_pulse_ms-1 ) PORT MAP ( rst => rst, @@ -104,7 +106,8 @@ BEGIN u_common_pulser_s : ENTITY common_lib.common_pulser GENERIC MAP ( - g_pulse_period => g_pulse_s + g_pulse_period => g_pulse_s, + g_pulse_phase => g_pulse_s-1 ) PORT MAP ( rst => rst, diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd index 0a4393896c8e3d19594fbd44e41ff3f1280eccf0..5b00cf780d0bd01e5d0d548fcff6f5cf441bdd66 100644 --- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd +++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd @@ -81,7 +81,8 @@ BEGIN u_pulse_us : ENTITY work.common_pulser GENERIC MAP ( - g_pulse_period => c_pulse_us + g_pulse_period => c_pulse_us, + g_pulse_phase => c_pulse_us-1 ) PORT MAP ( rst => rst,