diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd index 405a1dc5beaeb86d2a15106cb0edeece5306f52c..1a2f86719e6a2eae9f33616683ea02b236b62fd4 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd @@ -20,9 +20,7 @@ -- ------------------------------------------------------------------------------- - - -LIBRARY IEEE, unb1_test_lib; +LIBRARY IEEE, unb2_test_lib; USE IEEE.std_logic_1164.ALL; diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd index 1ee35bb0f1b72dcd47d6dd0ac897244e2bdf8dbd..1270f959aacf76afb26f56c8f0fdf74372f10e7e 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd @@ -22,7 +22,7 @@ -LIBRARY IEEE, unb1_test_lib; +LIBRARY IEEE, unb2_test_lib; USE IEEE.std_logic_1164.ALL; diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd index b55b50ffa3e178055c34206f7d6eaaac3a48ccaf..6871fcf69cef43f6c0fcfd4fbd62c82bed86cf4b 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd @@ -22,7 +22,7 @@ -LIBRARY IEEE, unb1_test_lib; +LIBRARY IEEE, unb2_test_lib; USE IEEE.std_logic_1164.ALL; diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd index 4a9a31317daeab439506e89c38cc54dce2047579..0c73f884a0f386067b0b8161a8318bbf09f752db 100644 --- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd +++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/tb_unb2_test_ddr.vhd @@ -22,7 +22,7 @@ -LIBRARY IEEE, unb1_test_lib; +LIBRARY IEEE, unb2_test_lib; USE IEEE.std_logic_1164.ALL;