From 8c6816aa11489da353ec44c4f3000c34f06a1dce Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Tue, 30 Jun 2015 05:21:50 +0000
Subject: [PATCH] Increase timeout to >> 1 hour, to avoid timeout in slow
simulation.
---
.../designs/unb2_test/tb/python/tc_unb2_test_ddr.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py
index 1130f7af49..518b51bcd1 100644
--- a/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py
+++ b/boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py
@@ -101,7 +101,7 @@ for rep in range(tc.repeat):
rx_seq_ddr[mb].write_disable(vLevel=5)
# Wait for the DDR memory to become available
- do_until_eq(io_ddr[mb].read_init_done, ms_retry=3000, val=1, s_timeout=3600)
+ do_until_eq(io_ddr[mb].read_init_done, ms_retry=3000, val=1, s_timeout=36000)
for mb in mb_list:
# Flush Tx FIFO
@@ -124,7 +124,7 @@ for rep in range(tc.repeat):
for mb in mb_list:
# Wait until controller write access is done
- do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=3600)
+ do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=36000)
# Rx sequence start
rx_seq_ddr[mb].write_enable_cntr(vLevel=5)
@@ -140,7 +140,7 @@ for rep in range(tc.repeat):
for mb in mb_list:
# Wait until controller read access is done
- do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=3600)
+ do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=36000)
rx_seq_ddr[mb].read_result(vLevel=5)
--
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