From 8bbea39cd1949c56463acdeaa70ca26bc59ce596 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 29 Aug 2023 11:57:02 +0200
Subject: [PATCH] Improved readability of proc_common_fifo_asserts().
---
libraries/base/common/src/vhdl/common_pkg.vhd | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 3820f51255..1814c90570 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -2946,9 +2946,21 @@ package body common_pkg is
-- Therefore only check on wr_full going high when wr_rst='0'.
--synthesis translate_off
- assert not(c_fail_rd_emp = true and rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1') report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
- assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0') report c_fifo_name & " : fifo is full now" severity NOTE;
- assert not( rising_edge(wr_clk) and wr_full = '1' and wr_en = '1') report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ if c_fail_rd_emp then
+ if rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1' then
+ report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
+ end if;
+ end if;
+
+ if c_note_is_ful then
+ if rising_edge(wr_full) and wr_rst = '0' then
+ report c_fifo_name & " : fifo is full now" severity NOTE;
+ end if;
+ end if;
+
+ if rising_edge(wr_clk) and wr_full = '1' and wr_en = '1' then
+ report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+ end if;
--synthesis translate_on
end procedure proc_common_fifo_asserts;
--
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