diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 3820f512559300a6e55401b844f04174ec04f88c..1814c905705c31c4381d1b2506587dbf325eb7dc 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -2946,9 +2946,21 @@ package body common_pkg is
     -- Therefore only check on wr_full going high when wr_rst='0'.
 
     --synthesis translate_off
-    assert not(c_fail_rd_emp = true and rising_edge(rd_clk)  and rd_empty = '1' and rd_en = '1')  report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
-    assert not(c_note_is_ful = true and rising_edge(wr_full) and wr_rst = '0')                  report c_fifo_name & " : fifo is full now"               severity NOTE;
-    assert not(                       rising_edge(wr_clk)  and wr_full = '1'  and wr_en = '1')  report c_fifo_name & " : fifo overflow occurred!"        severity FAILURE;
+    if c_fail_rd_emp then
+      if rising_edge(rd_clk) and rd_empty = '1' and rd_en = '1' then
+        report c_fifo_name & " : read from empty fifo occurred!" severity FAILURE;
+      end if;
+    end if;
+
+    if c_note_is_ful then
+      if rising_edge(wr_full) and wr_rst = '0' then
+        report c_fifo_name & " : fifo is full now" severity NOTE;
+      end if;
+    end if;
+
+    if rising_edge(wr_clk) and wr_full = '1' and wr_en = '1' then
+      report c_fifo_name & " : fifo overflow occurred!" severity FAILURE;
+    end if;
     --synthesis translate_on
   end procedure proc_common_fifo_asserts;