diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
deleted file mode 100644
index 314ee098b4b86022842b73363b83348f2da94e4f..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
+++ /dev/null
@@ -1,112 +0,0 @@
-hdl_lib_name = unb2c_test_minimal
-hdl_library_clause_name = unb2c_test_minimal_lib
-hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
-hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e2sg
-hdl_lib_include_ip =
-
-synth_files =
- unb2c_test_minimal.vhd
-
-test_bench_files =
- tb_unb2c_test_minimal.vhd
-
-regression_test_vhdl =
- tb_unb2c_test_minimal.vhd
-
-
-[modelsim_project_file]
-modelsim_copy_files =
- ../../src/hex hex
-
-
-[quartus_project_file]
-synth_top_level_entity =
-
-quartus_copy_files =
- quartus .
- ../../quartus .
- ../../src/hex hex
-
-quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
-
-quartus_sdc_pre_files =
- quartus/unb2c_test_minimal.sdc
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
-
-quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
-
-quartus_tcl_files =
- quartus/unb2c_test_minimal_pins.tcl
-
-quartus_vhdl_files =
-
-quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
-
-quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_1GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
-
-
-
-nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc
deleted file mode 100644
index fbcc86fb1bb44ec25f621483883c32ce0ba743e3..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal.sdc
+++ /dev/null
@@ -1 +0,0 @@
-#set_false_path -from [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
deleted file mode 100644
index ae417258f888c910d593c6ab6e5117615ebbd36f..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-###############################################################################
-#
-# Copyright (C) 2014
-# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-###############################################################################
-
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd
deleted file mode 100644
index fd8d3bd83e1ac09a154993de19b8add792cda7c5..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/tb_unb2c_test_minimal.vhd
+++ /dev/null
@@ -1,38 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, unb2c_test_lib;
-USE IEEE.std_logic_1164.ALL;
-
-
-ENTITY tb_unb2c_test_minimal IS
-END tb_unb2c_test_minimal;
-
-
-ARCHITECTURE tb OF tb_unb2c_test_minimal IS
-BEGIN
- u_tb_unb2c_test : ENTITY unb2c_test_lib.tb_unb2c_test
- GENERIC MAP (
- g_design_name => "unb2c_test_minimal"
- );
-END tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
deleted file mode 100644
index a13551d02f34e6ae41547d1257e81fb98f42151d..0000000000000000000000000000000000000000
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ /dev/null
@@ -1,101 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE unb2c_board_lib.unb2c_board_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-
-
-ENTITY unb2c_test_minimal IS
- GENERIC (
- g_design_name : STRING := "unb2c_test_minimal";
- g_design_note : STRING := "minimal: none";
- g_sim : BOOLEAN := FALSE; --Overridden by TB
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : STRING := "" -- revision ID -- set by QSF
- );
- PORT (
- -- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
- PPS : IN STD_LOGIC; -- System Sync
- WDI : OUT STD_LOGIC; -- Watchdog Clear
- INTA : INOUT STD_LOGIC; -- FPGA interconnect line
- INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
-
-
- -- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
- );
-END unb2c_test_minimal;
-
-
-ARCHITECTURE str OF unb2c_test_minimal IS
-
-BEGIN
- u_revision : ENTITY unb2c_test_lib.unb2c_test
- GENERIC MAP (
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id
- )
- PORT MAP (
- -- GENERAL
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
-
- -- 1GbE Control Interface
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- QSFP_LED => QSFP_LED
- );
-END str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index 9722d44faea0927d7a23450e2a7a9c7b5a0d4578..306af33cbd1abe7428f9fbc65f9b60cd9cab2756 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -77,7 +77,6 @@ PACKAGE unb2c_test_pkg IS
type_MB_II : t_c_tech_ddr;
END RECORD;
-- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
- CONSTANT c_test_minimal : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_10GbE : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_10GbE_qb : t_unb2c_test_config := (FALSE, TRUE, TRUE, TRUE,FALSE, TRUE,FALSE,FALSE,FALSE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
CONSTANT c_test_ddr : t_unb2c_test_config := (FALSE, TRUE, TRUE,FALSE,FALSE,FALSE,FALSE, TRUE, TRUE,FALSE,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
@@ -95,8 +94,7 @@ PACKAGE BODY unb2c_test_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_unb2c_test_config IS
BEGIN
- IF g_design_name = "unb2c_test_minimal" THEN RETURN c_test_minimal;
- ELSIF g_design_name = "unb2c_test_10GbE" THEN RETURN c_test_10GbE;
+ IF g_design_name = "unb2c_test_10GbE" THEN RETURN c_test_10GbE;
ELSIF g_design_name = "unb2c_test_ddr" THEN RETURN c_test_ddr;
ELSIF g_design_name = "unb2c_test_heater" THEN RETURN c_test_heater;
ELSIF g_design_name = "unb2c_test_jesd204b" THEN RETURN c_test_jesd204b;
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
index 4be13ed09c4bf68f00c1c506794378bc5d9c9b1d..d75b4a025b541fd4891dd046685a2394940ee194 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
@@ -4,7 +4,7 @@ set_location_assignment PIN_J15 -to "CLK(n)"
set_location_assignment PIN_N12 -to ETH_CLK[0]
set_location_assignment PIN_AK33 -to ETH_CLK[1]
-set_location_assignment PIN_H17 -to S10_ETH_CLK
+#set_location_assignment PIN_H17 -to S10_ETH_CLK
set_location_assignment PIN_K14 -to PPS
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
index 179df2ea458eee1bc1940f998155c02fa7c501fc..d97de2bec6e0e3371d5a2de28e3f5905e740844a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
@@ -70,8 +70,6 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk125]
set_clock_groups -asynchronous -group [get_clocks pll_clk200]
set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400]
-# Isolate the 200MHz dp_clk
-set_clock_groups -asynchronous -group [get_clocks {*|u_ctrl_unb2_board|\gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
# FPLL outputs
# Three of these have been removed because they cut paths between the PHY and MAC, and between the 156.25MHz
@@ -84,15 +82,6 @@ set_clock_groups -asynchronous -group [get_clocks {*|u_ctrl_unb2_board|\gen_pll:
#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
-# Cut paths used in signal taps (temporary 06-09-2019 - will be removed for production designs)
-set_false_path -from [get_clocks {*u_tech_10gbase_r|\gen_ip_arria10_e1sg:u0|\gen_phy_24:u_ip_arria10_e1sg_phy_10gbase_r_24|xcvr_native_a10_0|g_xcvr_native_insts*|avmmclk}] -to [get_clocks {u_tech_pll_xgmii_mac_clocks|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}];
-
-# False path from mm_clk to MAC clocks
-set_false_path -from [get_clocks {*|u_ctrl_unb2_board|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk1}] -to [get_clocks {*|u_tech_pll_xgmii_mac_clocks|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
-# Seems harmless to remove this
-#set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
-
-#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
#set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index e16a5d6ab2869fb929ea13cf46f155ba7340b8d8..c4182ba908d548a7c2556ad7093b7821bce00608 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -43,6 +43,8 @@ ENTITY ctrl_unb2c_board IS
----------------------------------------------------------------------------
g_technology : NATURAL := c_tech_arria10;
g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model;
+ g_sim_mm_clk_period : TIME := 10 ns; -- use e.g. c_mmf_mm_clk_period for MM bus file IO model, use e.g. 10 ns for MM access with TSE MAC IP
g_design_name : STRING := "UNUSED";
g_fw_version : t_unb2c_board_fw_version := (0, 0); -- firmware version x.y
g_stamp_date : NATURAL := 0;
@@ -257,7 +259,7 @@ ARCHITECTURE str OF ctrl_unb2c_board IS
SIGNAL i_mm_rst : STD_LOGIC;
SIGNAL i_mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_sim_clk : STD_LOGIC := '1';
+ SIGNAL sim_mm_clk : STD_LOGIC := '1';
SIGNAL epcs_clk : STD_LOGIC := '1';
SIGNAL clk125 : STD_LOGIC := '1';
SIGNAL clk100 : STD_LOGIC := '1';
@@ -413,11 +415,11 @@ BEGIN
-----------------------------------------------------------------------------
-- mm_clk
- -- . use mm_sim_clk in sim
+ -- . use sim_mm_clk in sim
-- . derived from ETH_CLK via PLL on hardware
-----------------------------------------------------------------------------
- i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
+ i_mm_clk <= sim_mm_clk WHEN g_sim = TRUE ELSE
clk125 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_125M ELSE
clk100 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_100M ELSE
clk50 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_50M ELSE
@@ -428,7 +430,7 @@ BEGIN
clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
clk100 <= NOT clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
clk125 <= NOT clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ sim_mm_clk <= NOT sim_mm_clk AFTER g_sim_mm_clk_period/2;
mm_locked <= '0', '1' AFTER 70 ns;
END GENERATE;
@@ -716,7 +718,9 @@ BEGIN
g_technology => g_technology,
g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => TRUE
+ g_frm_discard_en => TRUE,
+ g_sim => g_sim,
+ g_sim_level => g_sim_level -- 0 -- 0 = use IP; 1 = use fast serdes model;
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
index fcb493e25db6b6b1f9c54ae6db335e549d4214df..34e8546b799c343698618ecd71ae47e0e1577edf 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
@@ -50,6 +50,5 @@ vmap altera_xcvr_atx_pll_a10_191 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fbvyoua.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/ip_arria10_e2sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_191_fbvyoua.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_191/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_191
-
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
index 86eaf4a404e4a6701cd6df3f33aadb540b2a68cb..8bc95d11ae128bccb78c265a48f9719944ee7ef7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
@@ -8,7 +8,6 @@ synth_files =
test_bench_files =
-
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0864beac27c53a6e12511305e60e87de325c4274
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+
+vmap altmult_complex_1910 ./work/
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3880a880c2d0606923a8551ca6a4fb7c4407848e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_arria10_e2sg_altmult_complex_1910
+hdl_library_clause_name = altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e2sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/liborder.txt b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/liborder.txt
new file mode 100644
index 0000000000000000000000000000000000000000..03ec3b6a361368d60c6da26520d59235a6cb3ce1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/liborder.txt
@@ -0,0 +1,3 @@
+common: n_libs=9 lib_order=['technology', 'ip_arria10_e2sg_ram', 'tech_memory', 'ip_arria10_e2sg_fifo', 'tech_fifo', 'ip_arria10_e2sg_ddio', 'tech_iobuf', 'tst', 'common']
+
+New test order: []
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index caf20a24146e908c0142323457060a3eeb3faf82..24d21235f925d508c769aba950bffafd55444092 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -31,4 +31,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
vmap altmult_complex_1910 ./work/
- vlog "$IP_DIR/../altmult_complex_1910/synth/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.v" -work altmult_complex_1910
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
+ vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd" -work altmult_complex_1910
+
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index 2f0aca17109aeff235dd343b831a4c7b4fd4c8d8..a7582656cbbce3505ed6625bd38fdca6948fe08d 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -1,7 +1,7 @@
hdl_lib_name = ip_arria10_e2sg_complex_mult
hdl_library_clause_name = ip_arria10_e2sg_complex_mult_altmult_complex_1910
hdl_lib_uses_synth =
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = ip_arria10_e2sg_altmult_complex_1910
hdl_lib_technology = ip_arria10_e2sg
synth_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index 033a87880432c7f50eb7484d458df12e51518838..833ac0341320c43d29064b7ca3aac725d3c3bc49 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -115,7 +115,7 @@ BEGIN
ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
gen_ip : IF g_inferred=FALSE GENERATE
- -- Copied from ip_arria10_e2sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ -- Copied from ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
u_altera_syncram : altera_syncram
GENERIC MAP (
address_reg_b => "CLOCK1",
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.bsf b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.bsf
new file mode 100644
index 0000000000000000000000000000000000000000..4521bc11b8ebacf2619b02f996db44208571ed38
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.bsf
@@ -0,0 +1,148 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2019 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 304 384)
+ (text "ip_arria10_e2sg_ram_crw_crw" (rect 61 -1 186 11)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 368 20 380)(font "Arial" ))
+ (port
+ (pt 0 72)
+ (input)
+ (text "data_a[7..0]" (rect 0 0 47 12)(font "Arial" (font_size 8)))
+ (text "data_a[7..0]" (rect 4 61 76 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 96 72)(line_width 3))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "data_b[7..0]" (rect 0 0 47 12)(font "Arial" (font_size 8)))
+ (text "data_b[7..0]" (rect 4 101 76 112)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 96 112)(line_width 3))
+ )
+ (port
+ (pt 0 152)
+ (input)
+ (text "address_a[4..0]" (rect 0 0 63 12)(font "Arial" (font_size 8)))
+ (text "address_a[4..0]" (rect 4 141 94 152)(font "Arial" (font_size 8)))
+ (line (pt 0 152)(pt 96 152)(line_width 3))
+ )
+ (port
+ (pt 0 192)
+ (input)
+ (text "address_b[4..0]" (rect 0 0 63 12)(font "Arial" (font_size 8)))
+ (text "address_b[4..0]" (rect 4 181 94 192)(font "Arial" (font_size 8)))
+ (line (pt 0 192)(pt 96 192)(line_width 3))
+ )
+ (port
+ (pt 0 232)
+ (input)
+ (text "wren_a" (rect 0 0 29 12)(font "Arial" (font_size 8)))
+ (text "wren_a" (rect 4 221 40 232)(font "Arial" (font_size 8)))
+ (line (pt 0 232)(pt 96 232)(line_width 1))
+ )
+ (port
+ (pt 0 272)
+ (input)
+ (text "wren_b" (rect 0 0 29 12)(font "Arial" (font_size 8)))
+ (text "wren_b" (rect 4 261 40 272)(font "Arial" (font_size 8)))
+ (line (pt 0 272)(pt 96 272)(line_width 1))
+ )
+ (port
+ (pt 0 312)
+ (input)
+ (text "clock_a" (rect 0 0 30 12)(font "Arial" (font_size 8)))
+ (text "clock_a" (rect 4 301 46 312)(font "Arial" (font_size 8)))
+ (line (pt 0 312)(pt 96 312)(line_width 1))
+ )
+ (port
+ (pt 0 352)
+ (input)
+ (text "clock_b" (rect 0 0 30 12)(font "Arial" (font_size 8)))
+ (text "clock_b" (rect 4 341 46 352)(font "Arial" (font_size 8)))
+ (line (pt 0 352)(pt 96 352)(line_width 1))
+ )
+ (port
+ (pt 304 72)
+ (output)
+ (text "q_a[7..0]" (rect 0 0 35 12)(font "Arial" (font_size 8)))
+ (text "q_a[7..0]" (rect 259 61 313 72)(font "Arial" (font_size 8)))
+ (line (pt 304 72)(pt 208 72)(line_width 3))
+ )
+ (port
+ (pt 304 112)
+ (output)
+ (text "q_b[7..0]" (rect 0 0 35 12)(font "Arial" (font_size 8)))
+ (text "q_b[7..0]" (rect 259 101 313 112)(font "Arial" (font_size 8)))
+ (line (pt 304 112)(pt 208 112)(line_width 3))
+ )
+ (drawing
+ (text "data_a" (rect 57 43 150 99)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "datain_a" (rect 101 67 250 144)(font "Arial" (color 0 0 0)))
+ (text "q_a" (rect 209 43 436 99)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "dataout_a" (rect 163 67 380 144)(font "Arial" (color 0 0 0)))
+ (text "data_b" (rect 57 83 150 179)(font "Arial" (color 128 0 0)(font_size 9)))
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+ (text "wren_b" (rect 101 267 238 544)(font "Arial" (color 0 0 0)))
+ (text "clock_a" (rect 53 283 148 579)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 101 307 220 624)(font "Arial" (color 0 0 0)))
+ (text "clock_b" (rect 53 323 148 659)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 101 347 220 704)(font "Arial" (color 0 0 0)))
+ (text " ip_arria10_e2sg_ram_crw_crw " (rect 168 368 510 746)(font "Arial" ))
+ (line (pt 96 32)(pt 208 32)(line_width 1))
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diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.cmp b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.cmp
new file mode 100644
index 0000000000000000000000000000000000000000..090b3483515dc6158bcd0e8bb0637e82c8683ef4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.cmp
@@ -0,0 +1,15 @@
+ component ip_arria10_e2sg_ram_crw_crw is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
+ q_a : out std_logic_vector(7 downto 0); -- dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ q_b : out std_logic_vector(7 downto 0); -- dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clk
+ clock_b : in std_logic := 'X' -- clk
+ );
+ end component ip_arria10_e2sg_ram_crw_crw;
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.csv b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.csv
new file mode 100644
index 0000000000000000000000000000000000000000..10178c734cbbc58aaab1fd4d3614217548ece838
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.csv
@@ -0,0 +1,18 @@
+# system info ip_arria10_e2sg_ram_crw_crw on 2021.04.14.00:17:36
+system_info:
+name,value
+DEVICE,10AX115U3F45E2SG
+DEVICE_FAMILY,Arria 10
+GENERATION_ID,0
+#
+#
+# Files generated for ip_arria10_e2sg_ram_crw_crw on 2021.04.14.00:17:36
+files:
+filepath,kind,attributes,module,is_top
+sim/ip_arria10_e2sg_ram_crw_crw.vhd,VHDL,CONTAINS_INLINE_CONFIGURATION,ip_arria10_e2sg_ram_crw_crw,true
+ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd,VHDL,,ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey,false
+#
+# Map from instance-path to kind of module
+instances:
+instancePath,module
+ip_arria10_e2sg_ram_crw_crw.ram_2port_0,ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.html b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.html
new file mode 100644
index 0000000000000000000000000000000000000000..e06736eeb1d0b9926e234d56a691b194d894ddbe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.html
@@ -0,0 +1,329 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+ <title>datasheet for ip_arria10_e2sg_ram_crw_crw</title>
+ <style type="text/css">
+body { font-family:arial ;}
+a { text-decoration:underline ; color:#003000 ;}
+a:hover { text-decoration:underline ; color:0030f0 ;}
+td { padding : 5px ;}
+table.topTitle { width:100% ;}
+table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
+table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
+table.blueBar { width : 100% ; border-spacing : 0px ;}
+table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
+table.blueBar td.l { text-align : left ;}
+table.blueBar td.r { text-align : right ;}
+table.items { width:100% ; border-collapse:collapse ;}
+table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
+table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
+div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ; font-size:12px ;}
+body { font-family:arial ;}
+table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
+table.x td { border:1px solid #bbb ;}
+td.tableTitle { font-weight:bold ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ;}
+table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
+table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
+table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
+table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
+table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
+table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
+table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
+table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
+table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
+table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
+table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
+table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
+table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
+table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
+.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
+.flowbox { display:inline-block ;}
+.parametersbox table { font-size:10px ;}
+td.parametername { font-style:italic ;}
+td.parametervalue { font-weight:bold ;}
+div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
+ </head>
+ <body>
+ <table class="topTitle">
+ <tr>
+ <td class="l">ip_arria10_e2sg_ram_crw_crw</td>
+ <td class="r">
+ <br/>
+ <br/>
+ </td>
+ </tr>
+ </table>
+ <table class="blueBar">
+ <tr>
+ <td class="l">2021.04.14.00:17:38</td>
+ <td class="r">Datasheet</td>
+ </tr>
+ </table>
+ <div style="width:100% ; height:10px"> </div>
+ <div class="label">Overview</div>
+ <div class="greydiv">
+ <div style="display:inline-block ; text-align:left">
+ <table class="connectionboxes">
+ <tr style="height:6px">
+ <td></td>
+ </tr>
+ </table>
+ </div><span style="display:inline-block ; width:28px"> </span>
+ <div style="display:inline-block ; text-align:left"><span>
+ <br/></span>
+ </div>
+ </div>
+ <div style="width:100% ; height:10px"> </div>
+ <div class="label">Memory Map</div>
+ <table class="mmap">
+ <tr>
+ <td class="empty" rowspan="2"></td>
+ </tr>
+ </table>
+ <a name="module_ram_2port_0"> </a>
+ <div>
+ <hr/>
+ <h2>ram_2port_0</h2>ram_2port v20.0.0
+ <br/>
+ <br/>
+ <br/>
+ <table class="flowbox">
+ <tr>
+ <td class="parametersbox">
+ <h2>Parameters</h2>
+ <table>
+ <tr>
+ <td class="parametername">GUI_MODE</td>
+ <td class="parametervalue">1</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_MEM_IN_BITS</td>
+ <td class="parametervalue">0</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_MEMSIZE_WORDS</td>
+ <td class="parametervalue">32</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_QA_WIDTH</td>
+ <td class="parametervalue">8</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_QB_WIDTH</td>
+ <td class="parametervalue">8</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_DATAA_WIDTH</td>
+ <td class="parametervalue">8</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_MAX_DEPTH</td>
+ <td class="parametervalue">Auto</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_TDP_EMULATE</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_VAR_WIDTH</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_RAM_BLOCK_TYPE</td>
+ <td class="parametervalue">Auto</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_LC_IMPLEMENTION_OPTIONS</td>
+ <td class="parametervalue">0</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_OPTIMIZATION_OPTION</td>
+ <td class="parametervalue">0</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLOCK_TYPE</td>
+ <td class="parametervalue">4</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_RDEN_DOUBLE</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_BYTE_ENABLE_A</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_BYTE_ENABLE_B</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ECC_TRIPLE</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ECC_PIPELINE</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ECCENCBYPASS</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_COHERENT_READ</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_FORCE_TO_ZERO</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_PR</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_BYTE_ENABLE_WIDTH</td>
+ <td class="parametervalue">8</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_WRITE_INPUT_PORTS</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_READ_INPUT_RDADDRESS</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_READ_OUTPUT_QA</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_READ_OUTPUT_QB</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_DIFFERENT_CLKENS</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_INPUT_REG_A</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_INPUT_REG_B</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_OUTPUT_REG_A</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_OUTPUT_REG_B</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_ADDRESS_STALL_A</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CLKEN_ADDRESS_STALL_B</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ACLR_READ_INPUT_RDADDRESS</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ACLR_READ_OUTPUT_QA</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_ACLR_READ_OUTPUT_QB</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_SCLR_READ_OUTPUT_QA</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_SCLR_READ_OUTPUT_QB</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_Q_PORT_MODE</td>
+ <td class="parametervalue">2</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_CONSTRAINED_DONT_CARE</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_RDW_A_MODE</td>
+ <td class="parametervalue">New Data</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_RDW_B_MODE</td>
+ <td class="parametervalue">New Data</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_NBE_A</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_NBE_B</td>
+ <td class="parametervalue">true</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_BLANK_MEMORY</td>
+ <td class="parametervalue">1</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_INIT_FILE_LAYOUT</td>
+ <td class="parametervalue">PORT_B</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_INIT_SIM_TO_X</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ <tr>
+ <td class="parametername">GUI_MIF_FILENAME</td>
+ <td class="parametervalue">./ram_1024.hex</td>
+ </tr>
+ <tr>
+ <td class="parametername">deviceFamily</td>
+ <td class="parametervalue">UNKNOWN</td>
+ </tr>
+ <tr>
+ <td class="parametername">generateLegacySim</td>
+ <td class="parametervalue">false</td>
+ </tr>
+ </table>
+ </td>
+ </tr>
+ </table>  
+ <table class="flowbox">
+ <tr>
+ <td class="parametersbox">
+ <h2>Software Assignments</h2>(none)</td>
+ </tr>
+ </table>
+ </div>
+ <table class="blueBar">
+ <tr>
+ <td class="l">generation took 0.00 seconds</td>
+ <td class="r">rendering took 0.01 seconds</td>
+ </tr>
+ </table>
+ </body>
+</html>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsimc b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsimc
new file mode 100644
index 0000000000000000000000000000000000000000..29a09a60a4c9001842e987258f52597e6b40b8a5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsimc
@@ -0,0 +1,320 @@
+<?xml version="1.0" ?>
+<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
+ <instanceKey xsi:type="xs:string">ip_arria10_e2sg_ram_crw_crw</instanceKey>
+ <instanceData xsi:type="data">
+ <parameters></parameters>
+ <interconnectAssignments></interconnectAssignments>
+ <className>ip_arria10_e2sg_ram_crw_crw</className>
+ <version>1.0</version>
+ <name>ip_arria10_e2sg_ram_crw_crw</name>
+ <uniqueName>ip_arria10_e2sg_ram_crw_crw</uniqueName>
+ <nonce>0</nonce>
+ <incidentConnections></incidentConnections>
+ </instanceData>
+ <children>
+ <node>
+ <instanceKey xsi:type="xs:string">ram_2port_0</instanceKey>
+ <instanceData xsi:type="data">
+ <parameters>
+ <parameter>
+ <name>DEVICE_FAMILY</name>
+ <value>Arria 10</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_INPUT_RDADDRESS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_OUTPUT_QA</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_OUTPUT_QB</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BLANK_MEMORY</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_WIDTH_A</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_WIDTH_B</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_ADDRESS_STALL_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_ADDRESS_STALL_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_INPUT_REG_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_INPUT_REG_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_OUTPUT_REG_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_OUTPUT_REG_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_RDADDRESSSTALL</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_READ_INPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_READ_OUTPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_WRADDRESSSTALL</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_WRITE_INPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLOCK_TYPE</name>
+ <value>4</value>
+ </parameter>
+ <parameter>
+ <name>GUI_COHERENT_READ</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CONSTRAINED_DONT_CARE</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DATAA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DATA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DIFFERENT_CLKENS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECCENCBYPASS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_DOUBLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_PIPELINE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_TRIPLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_FILE_REFERENCE</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_FORCE_TO_ZERO</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_INIT_FILE_LAYOUT</name>
+ <value>PORT_B</value>
+ </parameter>
+ <parameter>
+ <name>GUI_INIT_SIM_TO_X</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_LC_IMPLEMENTION_OPTIONS</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MAX_DEPTH</name>
+ <value>Auto</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEMSIZE_BITS</name>
+ <value>256</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEMSIZE_WORDS</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEM_IN_BITS</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MIF_FILENAME</name>
+ <value>./ram_1024.hex</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MODE</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MODULE_NAME</name>
+ <value>altera_syncram</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NBE_A</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NBE_B</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NUMWORDS_A</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NUMWORDS_B</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_OPTIMIZATION_OPTION</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_PR</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_QA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_QB_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_Q_PORT_MODE</name>
+ <value>2</value>
+ </parameter>
+ <parameter>
+ <name>GUI_Q_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RAM_BLOCK_TYPE</name>
+ <value>Auto</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDADDRESS_WIDTH</name>
+ <value>5</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDEN_DOUBLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDEN_SINGLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDW_A_MODE</name>
+ <value>New Data</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDW_B_MODE</name>
+ <value>New Data</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_INPUT_RDADDRESS</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_OUTPUT_QA</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_OUTPUT_QB</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RESOURCE_USAGE</name>
+ <value>1 M20K</value>
+ </parameter>
+ <parameter>
+ <name>GUI_SCLR_READ_OUTPUT_QA</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_SCLR_READ_OUTPUT_QB</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_TBENCH</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_TDP_EMULATE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_VAR_WIDTH</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WIDTH_ECCENCPARITY</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WIDTH_ECCSTATUS</name>
+ <value>2</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WRADDRESS_WIDTH</name>
+ <value>5</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WRITE_INPUT_PORTS</name>
+ <value>true</value>
+ </parameter>
+ </parameters>
+ <interconnectAssignments></interconnectAssignments>
+ <className>ram_2port</className>
+ <version>20.0.0</version>
+ <name>ram_2port_0</name>
+ <uniqueName>ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey</uniqueName>
+ <nonce>0</nonce>
+ <incidentConnections></incidentConnections>
+ <path>ip_arria10_e2sg_ram_crw_crw.ram_2port_0</path>
+ </instanceData>
+ <children></children>
+ </node>
+ </children>
+</node>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsynthc b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsynthc
new file mode 100644
index 0000000000000000000000000000000000000000..29a09a60a4c9001842e987258f52597e6b40b8a5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qgsynthc
@@ -0,0 +1,320 @@
+<?xml version="1.0" ?>
+<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
+ <instanceKey xsi:type="xs:string">ip_arria10_e2sg_ram_crw_crw</instanceKey>
+ <instanceData xsi:type="data">
+ <parameters></parameters>
+ <interconnectAssignments></interconnectAssignments>
+ <className>ip_arria10_e2sg_ram_crw_crw</className>
+ <version>1.0</version>
+ <name>ip_arria10_e2sg_ram_crw_crw</name>
+ <uniqueName>ip_arria10_e2sg_ram_crw_crw</uniqueName>
+ <nonce>0</nonce>
+ <incidentConnections></incidentConnections>
+ </instanceData>
+ <children>
+ <node>
+ <instanceKey xsi:type="xs:string">ram_2port_0</instanceKey>
+ <instanceData xsi:type="data">
+ <parameters>
+ <parameter>
+ <name>DEVICE_FAMILY</name>
+ <value>Arria 10</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_INPUT_RDADDRESS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_OUTPUT_QA</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ACLR_READ_OUTPUT_QB</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BLANK_MEMORY</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_ENABLE_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_WIDTH_A</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_BYTE_WIDTH_B</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_ADDRESS_STALL_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_ADDRESS_STALL_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_INPUT_REG_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_INPUT_REG_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_OUTPUT_REG_A</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_OUTPUT_REG_B</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_RDADDRESSSTALL</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_READ_INPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_READ_OUTPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_WRADDRESSSTALL</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLKEN_WRITE_INPUT_REG</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CLOCK_TYPE</name>
+ <value>4</value>
+ </parameter>
+ <parameter>
+ <name>GUI_COHERENT_READ</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_CONSTRAINED_DONT_CARE</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DATAA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DATA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_DIFFERENT_CLKENS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECCENCBYPASS</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_DOUBLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_PIPELINE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_ECC_TRIPLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_FILE_REFERENCE</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_FORCE_TO_ZERO</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_INIT_FILE_LAYOUT</name>
+ <value>PORT_B</value>
+ </parameter>
+ <parameter>
+ <name>GUI_INIT_SIM_TO_X</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_LC_IMPLEMENTION_OPTIONS</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MAX_DEPTH</name>
+ <value>Auto</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEMSIZE_BITS</name>
+ <value>256</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEMSIZE_WORDS</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MEM_IN_BITS</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MIF_FILENAME</name>
+ <value>./ram_1024.hex</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MODE</name>
+ <value>1</value>
+ </parameter>
+ <parameter>
+ <name>GUI_MODULE_NAME</name>
+ <value>altera_syncram</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NBE_A</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NBE_B</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NUMWORDS_A</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_NUMWORDS_B</name>
+ <value>32</value>
+ </parameter>
+ <parameter>
+ <name>GUI_OPTIMIZATION_OPTION</name>
+ <value>0</value>
+ </parameter>
+ <parameter>
+ <name>GUI_PR</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_QA_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_QB_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_Q_PORT_MODE</name>
+ <value>2</value>
+ </parameter>
+ <parameter>
+ <name>GUI_Q_WIDTH</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RAM_BLOCK_TYPE</name>
+ <value>Auto</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDADDRESS_WIDTH</name>
+ <value>5</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDEN_DOUBLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDEN_SINGLE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDW_A_MODE</name>
+ <value>New Data</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RDW_B_MODE</name>
+ <value>New Data</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_INPUT_RDADDRESS</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_OUTPUT_QA</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_READ_OUTPUT_QB</name>
+ <value>true</value>
+ </parameter>
+ <parameter>
+ <name>GUI_RESOURCE_USAGE</name>
+ <value>1 M20K</value>
+ </parameter>
+ <parameter>
+ <name>GUI_SCLR_READ_OUTPUT_QA</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_SCLR_READ_OUTPUT_QB</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_TBENCH</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_TDP_EMULATE</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_VAR_WIDTH</name>
+ <value>false</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WIDTH_ECCENCPARITY</name>
+ <value>8</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WIDTH_ECCSTATUS</name>
+ <value>2</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WRADDRESS_WIDTH</name>
+ <value>5</value>
+ </parameter>
+ <parameter>
+ <name>GUI_WRITE_INPUT_PORTS</name>
+ <value>true</value>
+ </parameter>
+ </parameters>
+ <interconnectAssignments></interconnectAssignments>
+ <className>ram_2port</className>
+ <version>20.0.0</version>
+ <name>ram_2port_0</name>
+ <uniqueName>ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey</uniqueName>
+ <nonce>0</nonce>
+ <incidentConnections></incidentConnections>
+ <path>ip_arria10_e2sg_ram_crw_crw.ram_2port_0</path>
+ </instanceData>
+ <children></children>
+ </node>
+ </children>
+</node>
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qip b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qip
new file mode 100644
index 0000000000000000000000000000000000000000..d9da19dd85288ab52a1a4634c8f7b96a88e5026f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.qip
@@ -0,0 +1,113 @@
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TOOL_NAME "QsysPrimePro"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TOOL_VERSION "19.4"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TOOL_ENV "QsysPrimePro"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TOP_LEVEL_COMPONENT_NAME "ram_2port"
+set_global_assignment -library "ip_arria10_e2sg_ram_crw_crw" -name SOPCINFO_FILE [file join $::quartus(qip_path) "ip_arria10_e2sg_ram_crw_crw.sopcinfo"]
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name SLD_INFO "QSYS_NAME ip_arria10_e2sg_ram_crw_crw HAS_SOPCINFO 1 GENERATION_ID 0"
+set_global_assignment -library "ip_arria10_e2sg_ram_crw_crw" -name MISC_FILE [file join $::quartus(qip_path) "ip_arria10_e2sg_ram_crw_crw.cmp"]
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_QSYS_MODE "STANDALONE"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "ip_arria10_e2sg_ram_crw_crw" -name MISC_FILE [file join $::quartus(qip_path) "../ip_arria10_e2sg_ram_crw_crw.ip"]
+
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_NAME "aXBfYXJyaWExMF9lMnNnX3JhbV9jcndfY3J3X3JhbV8ycG9ydF8yMDAwX3p4bnY0ZXk="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DISPLAY_NAME "UkFNOiAyLVBPUlQgSW50ZWwgRlBHQSBJUA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_VERSION "MjAuMC4w"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::QXJyaWEgMTA=::RGV2aWNlIEZhbWlseQ=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01PREU=::MQ==::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01FTV9JTl9CSVRT::MA==::VHlwZQ=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01FTVNJWkVfQklUUw==::MjU2::SG93IG1hbnkgYml0cyBvZiBtZW1vcnk/"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01FTVNJWkVfV09SRFM=::MzI=::SG93IG1hbnkgd29yZHMgb2YgbWVtb3J5Pw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1FBX1dJRFRI::OA==::SG93IHdpZGUgc2hvdWxkIHRoZSAncV9hJyBvdXRwdXQgYnVzIGJlPw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1FCX1dJRFRI::OA==::SG93IHdpZGUgc2hvdWxkIHRoZSAncV9iJyBvdXRwdXQgYnVzIGJlPw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0RBVEFBX1dJRFRI::OA==::SG93IHdpZGUgc2hvdWxkIHRoZSAnZGF0YV9hJyBpbnB1dCBidXMgYmU/"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01BWF9ERVBUSA==::QXV0bw==::U2V0IHRoZSBtYXhpbXVtIGJsb2NrIGRlcHRoIHRv"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1dJRFRIX0VDQ0VOQ1BBUklUWQ==::OA==::U2V0IHRoZSBlY2MgZW5jIHBhcml0eSB3aWR0aA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1RCRU5DSA==::ZmFsc2U=::VEVTVElORw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1REUF9FTVVMQVRF::ZmFsc2U=::RW11bGF0ZSBURFAgZHVhbCBjbG9jayBtb2Rl"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1ZBUl9XSURUSA==::ZmFsc2U=::VXNlIGRpZmZlcmVudCBkYXRhIHdpZHRocyBvbiBkaWZmZXJlbnQgcG9ydHM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JBTV9CTE9DS19UWVBF::QXV0bw==::UmFtIEJsb2NrIFR5cGU="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0xDX0lNUExFTUVOVElPTl9PUFRJT05T::MA==::SG93IHNob3VsZCB0aGUgbWVtb3J5IGJlIGltcGxlbWVudGVkPw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0ZJTEVfUkVGRVJFTkNF::MA==::SW5pdGlhbGl6YXRpb24gRmlsZTo="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMT0NLX1RZUEU=::NA==::V2hpY2ggY2xvY2tpbmcgbWV0aG9kIGRvIHlvdSB3YW50IHRvIHVzZT8="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JERU5fU0lOR0xF::ZmFsc2U=::Q3JlYXRlIGEgJ3JkZW4nIHJlYWQgZW5hYmxlIHNpZ25hbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JERU5fRE9VQkxF::ZmFsc2U=::Q3JlYXRlICdyZGVuX2EnIGFuZCAncmRlbl9iJyByZWFkIGVuYWJsZSBzaWduYWxz"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0JZVEVfRU5BQkxFX0E=::ZmFsc2U=::Q3JlYXRlIGJ5dGUgZW5hYmxlIGZvciBwb3J0IEE="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0JZVEVfRU5BQkxFX0I=::ZmFsc2U=::Q3JlYXRlIGJ5dGUgZW5hYmxlIGZvciBwb3J0IEI="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0VDQ19ET1VCTEU=::ZmFsc2U=::RW5hYmxlIEVycm9yIENvcnJlY3Rpb24gQ2hlY2sgKEVDQyk="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0VDQ19UUklQTEU=::ZmFsc2U=::RW5hYmxlIEVycm9yIENvcnJlY3Rpb24gQ2hlY2sgKEVDQyk="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0VDQ19QSVBFTElORQ==::ZmFsc2U=::RW5hYmxlIEVDQyBQaXBlbGluZSBSZWdpc3RlcnM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0VDQ0VOQ0JZUEFTUw==::ZmFsc2U=::RW5hYmxlIEVDQyBFbmNvZGVyIEJ5cGFzcw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NPSEVSRU5UX1JFQUQ=::ZmFsc2U=::RW5hYmxlIENvaGVyZW50IFJlYWQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0ZPUkNFX1RPX1pFUk8=::ZmFsc2U=::RW5hYmxlIEZvcmNlIFRvIFplcm8="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1BS::ZmFsc2U=::SW1wbGVtZW50IGNsb2NrLWVuYWJsZSBjaXJjdWl0cnkgZm9yIHVzZSBpbiBhIHBhcnRpYWwgcmVjb25maWd1cmF0aW9uIHJlZ2lvbg=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1dSSVRFX0lOUFVUX1BPUlRT::dHJ1ZQ==::QWxsIHdyaXRlIGlucHV0IHBvcnRz"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JFQURfSU5QVVRfUkRBRERSRVNT::dHJ1ZQ==::cmRhZGRyZXNzIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JFQURfT1VUUFVUX1FB::dHJ1ZQ==::cV9hIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JFQURfT1VUUFVUX1FC::dHJ1ZQ==::cV9iIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0RJRkZFUkVOVF9DTEtFTlM=::ZmFsc2U=::VXNlIGRpZmZlcmVudCBjbG9jayBlbmFibGVzIGZvciByZWdpc3RlcnM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX1dSSVRFX0lOUFVUX1JFRw==::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3Igd3JpdGUgaW5wdXQgcmVnaXN0ZXJz"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX1JFQURfSU5QVVRfUkVH::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgcmVhZCBpbnB1dCByZWdpc3RlcnM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX1JFQURfT1VUUFVUX1JFRw==::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3Igb3V0cHV0IHJlZ2lzdGVycw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX0lOUFVUX1JFR19B::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgcG9ydCBBIGlucHV0IHJlZ2lzdGVycw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX0lOUFVUX1JFR19C::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgcG9ydCBCIGlucHV0IHJlZ2lzdGVycw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX09VVFBVVF9SRUdfQQ==::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgcG9ydCBBIG91dHB1dCByZWdpc3RlcnM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX09VVFBVVF9SRUdfQg==::ZmFsc2U=::VXNlIGNsb2NrIGVuYWJsZSBmb3IgcG9ydCBCIG91dHB1dCByZWdpc3RlcnM="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX0FERFJFU1NfU1RBTExfQQ==::ZmFsc2U=::Q3JlYXRlIGFuIGFkZHJlc3NzdGFsbF9hIGlucHV0IHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX0FERFJFU1NfU1RBTExfQg==::ZmFsc2U=::Q3JlYXRlIGFuIGFkZHJlc3NzdGFsbF9iIGlucHV0IHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX1dSQUREUkVTU1NUQUxM::ZmFsc2U=::Q3JlYXRlIGFuIHdyX2FkZHJlc3NzdGFsbCBpbnB1dCBwb3J0"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0NMS0VOX1JEQUREUkVTU1NUQUxM::ZmFsc2U=::Q3JlYXRlIGFuIHJkX2FkZHJlc3NzdGFsbCBpbnB1dCBwb3J0"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0FDTFJfUkVBRF9JTlBVVF9SREFERFJFU1M=::ZmFsc2U=::cmRhZGRyZXNzIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0FDTFJfUkVBRF9PVVRQVVRfUUE=::ZmFsc2U=::cV9hIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0FDTFJfUkVBRF9PVVRQVVRfUUI=::ZmFsc2U=::cV9iIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1NDTFJfUkVBRF9PVVRQVVRfUUE=::ZmFsc2U=::cV9hIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1NDTFJfUkVBRF9PVVRQVVRfUUI=::ZmFsc2U=::cV9iIHBvcnQ="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JEV19BX01PREU=::TmV3IERhdGE=::V2hhdCBzaG91bGQgdGhlIHFfYSBvdXRwdXQgYmUgd2hlbiByZWFkaW5nIGZyb20gYSBtZW1vcnkgbG9jYXRpb24gYmVpbmcgd3JpdHRlbiB0bz8="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JEV19CX01PREU=::TmV3IERhdGE=::V2hhdCBzaG91bGQgdGhlIHFfYiBvdXRwdXQgYmUgd2hlbiByZWFkaW5nIGZyb20gYSBtZW1vcnkgbG9jYXRpb24gYmVpbmcgd3JpdHRlbiB0bz8="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX05CRV9B::dHJ1ZQ==::R2V0IHgncyBmb3Igd3JpdGUgbWFza2VkIGJ5dGVzIGluc3RlYWQgb2Ygb2xkIGRhdGEgd2hlbiBieXRlIGVuYWJsZSBpcyB1c2Vk"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX05CRV9C::dHJ1ZQ==::R2V0IHgncyBmb3Igd3JpdGUgbWFza2VkIGJ5dGVzIGluc3RlYWQgb2Ygb2xkIGRhdGEgd2hlbiBieXRlIGVuYWJsZSBpcyB1c2Vk"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0JMQU5LX01FTU9SWQ==::MQ==::VHlwZQ=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0lOSVRfRklMRV9MQVlPVVQ=::UE9SVF9C::VGhlIGluaXRpYWwgY29udGVudCBmaWxlIHNob3VsZCBjb25mb3JtIHRvIHdoaWNoIHBvcnQncyBkaW1lbnNpb25zPw=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX0lOSVRfU0lNX1RPX1g=::ZmFsc2U=::SW5pdGlhbGl6ZSBtZW1vcnkgY29udGVudCBkYXRhIHRvIFhYLi5YIG9uIHBvd2VyLXVwIGluIHNpbXVsYXRpb24="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX01JRl9GSUxFTkFNRQ==::Li9yYW1fMTAyNC5oZXg=::RmlsZSBuYW1l"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_PARAMETER "R1VJX1JFU09VUkNFX1VTQUdF::MSBNMjBL::UmVzb3VyY2UgVXNhZ2U="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL09uIENoaXAgTWVtb3J5"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL211ZjE0ODg1MTE0Nzg4MjUuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL21jbjE0MTMxODIyOTI1NjguaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL21jbjE0NDEwOTI5NTgxOTguaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2ZubzE1NTA2MjYwMjcyNzQuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2VpczE0MTM0MjU3MTY5NjUuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3ZnbzE0Mzk0NTEwMDAzMDQuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2ZqbjE1NDg5MDM4MzI4ODkuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2txZDE1MTczNjI0NzQyNDEuaHRtbA=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_NAME "aXBfYXJyaWExMF9lMnNnX3JhbV9jcndfY3J3"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MA==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUzRjQ1RTJTRw==::QXV0byBERVZJQ0U="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Mg==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19BX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19BX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19BX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw" -library "ip_arria10_e2sg_ram_crw_crw" -name IP_COMPONENT_PARAMETER "QVVUT19DTE9DS19CX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
+
+
+set_global_assignment -library "ram_2port_2000" -name VERILOG_FILE [file join $::quartus(qip_path) "ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v"]
+set_global_assignment -library "ip_arria10_e2sg_ram_crw_crw" -name VHDL_FILE [file join $::quartus(qip_path) "synth/ip_arria10_e2sg_ram_crw_crw.vhd"]
+
+
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_TOOL_NAME "ram_2port"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_TOOL_VERSION "20.0.0"
+set_global_assignment -entity "ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey" -library "ram_2port_2000" -name IP_TOOL_ENV "QsysPrimePro"
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.sopcinfo b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.sopcinfo
new file mode 100644
index 0000000000000000000000000000000000000000..07f8a2bbc0dbefe44617e6e39f1d160da8e17e31
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.sopcinfo
@@ -0,0 +1,1316 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport
+ name="ip_arria10_e2sg_ram_crw_crw"
+ kind="ip_arria10_e2sg_ram_crw_crw"
+ version="1.0"
+ fabric="QSYS">
+ <!-- Format version 19.4 64 (Future versions may contain additional information.) -->
+ <!-- 2021.04.14.00:17:38 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+ <type>java.lang.Integer</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+ <type>java.lang.String</type>
+ <value>10AX115U3F45E2SG</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+ <type>java.lang.String</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_CLOCK_A_CLOCK_RATE">
+ <type>java.lang.Long</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_RATE</sysinfo_type>
+ <sysinfo_arg>clock_a</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_A_CLOCK_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clock_a</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_A_RESET_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clock_a</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_B_CLOCK_RATE">
+ <type>java.lang.Long</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_RATE</sysinfo_type>
+ <sysinfo_arg>clock_b</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_B_CLOCK_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clock_b</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLOCK_B_RESET_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clock_b</sysinfo_arg>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>Arria 10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="20.0.0"
+ entity="ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey"
+ library="ram_2port_2000"
+ path="ram_2port_0"
+ hpath="ram_2port_0">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <parameter name="DEVICE_FAMILY">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="GUI_MODE">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MEM_IN_BITS">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MEMSIZE_BITS">
+ <type>int</type>
+ <value>256</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MEMSIZE_WORDS">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_QA_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_QB_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_DATAA_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MAX_DEPTH">
+ <type>java.lang.String</type>
+ <value>Auto</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_WIDTH_ECCENCPARITY">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_TBENCH">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_TDP_EMULATE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_VAR_WIDTH">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RAM_BLOCK_TYPE">
+ <type>java.lang.String</type>
+ <value>Auto</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_FILE_REFERENCE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_OPTIMIZATION_OPTION">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLOCK_TYPE">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RDEN_SINGLE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RDEN_DOUBLE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BYTE_ENABLE_A">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BYTE_ENABLE_B">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ECC_DOUBLE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ECC_TRIPLE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ECC_PIPELINE">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ECCENCBYPASS">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_COHERENT_READ">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_FORCE_TO_ZERO">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_PR">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BYTE_ENABLE_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_WRITE_INPUT_PORTS">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_READ_INPUT_RDADDRESS">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_READ_OUTPUT_QA">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_READ_OUTPUT_QB">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_DIFFERENT_CLKENS">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_READ_INPUT_REG">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_INPUT_REG_A">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_INPUT_REG_B">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_Q_PORT_MODE">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_CONSTRAINED_DONT_CARE">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RDW_A_MODE">
+ <type>java.lang.String</type>
+ <value>New Data</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RDW_B_MODE">
+ <type>java.lang.String</type>
+ <value>New Data</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_NBE_A">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_NBE_B">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BLANK_MEMORY">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_INIT_FILE_LAYOUT">
+ <type>java.lang.String</type>
+ <value>PORT_B</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_INIT_SIM_TO_X">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MIF_FILENAME">
+ <type>java.lang.String</type>
+ <value>./ram_1024.hex</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BYTE_WIDTH_A">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_BYTE_WIDTH_B">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_MODULE_NAME">
+ <type>java.lang.String</type>
+ <value>altera_syncram</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_DATA_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_Q_WIDTH">
+ <type>int</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_WRADDRESS_WIDTH">
+ <type>int</type>
+ <value>5</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RDADDRESS_WIDTH">
+ <type>int</type>
+ <value>5</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_WIDTH_ECCSTATUS">
+ <type>int</type>
+ <value>2</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_NUMWORDS_A">
+ <type>int</type>
+ <value>32</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_NUMWORDS_B">
+ <type>int</type>
+ <value>32</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="GUI_RESOURCE_USAGE">
+ <type>java.lang.String</type>
+ <value>1 M20K</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="data_a" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>data_a</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>datain_a</role>
+ </port>
+ </interface>
+ <interface name="q_a" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>q_a</name>
+ <direction>Output</direction>
+ <width>8</width>
+ <role>dataout_a</role>
+ </port>
+ </interface>
+ <interface name="data_b" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>data_b</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>datain_b</role>
+ </port>
+ </interface>
+ <interface name="q_b" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>q_b</name>
+ <direction>Output</direction>
+ <width>8</width>
+ <role>dataout_b</role>
+ </port>
+ </interface>
+ <interface name="address_a" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address_a</name>
+ <direction>Input</direction>
+ <width>5</width>
+ <role>address_a</role>
+ </port>
+ </interface>
+ <interface name="address_b" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>address_b</name>
+ <direction>Input</direction>
+ <width>5</width>
+ <role>address_b</role>
+ </port>
+ </interface>
+ <interface name="wren_a" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>wren_a</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>wren_a</role>
+ </port>
+ </interface>
+ <interface name="wren_b" kind="conduit_end" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prSafe">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>wren_b</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>wren_b</role>
+ </port>
+ </interface>
+ <interface name="clock_a" kind="clock_sink" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clock_a</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="clock_b" kind="clock_sink" version="19.4">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clock_b</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ </module>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>ram_2port</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>RAM: 2-PORT Intel FPGA IP</displayName>
+ <version>20.0.0</version>
+ </plugin>
+ <plugin>
+ <instanceCount>8</instanceCount>
+ <name>conduit_end</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Conduit</displayName>
+ <version>19.4</version>
+ </plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>clock_sink</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Clock Input</displayName>
+ <version>19.4</version>
+ </plugin>
+ <reportVersion>19.4 64</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.spd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.spd
new file mode 100644
index 0000000000000000000000000000000000000000..b3efa6caa72f871969207047e29a96a2be34615b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.spd
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+ path="ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd"
+ type="VHDL"
+ library="ram_2port_2000" />
+ <file
+ path="sim/ip_arria10_e2sg_ram_crw_crw.vhd"
+ type="VHDL"
+ library="ip_arria10_e2sg_ram_crw_crw"
+ hasInlineConfiguration="true" />
+ <topLevel name="ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw" />
+ <deviceFamily name="arria10" />
+</simPackage>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.xml b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..5cbe0879e96c42d70803be7bb12de9af48feb407
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw.xml
@@ -0,0 +1,267 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2021.04.14.00:17:38"
+ outputDirectory="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/">
+ <perimeter>
+ <parameter
+ name="AUTO_GENERATION_ID"
+ type="Integer"
+ defaultValue="0"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_UNIQUE_ID"
+ type="String"
+ defaultValue=""
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_DEVICE_FAMILY"
+ type="String"
+ defaultValue="Arria 10"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_DEVICE"
+ type="String"
+ defaultValue="10AX115U3F45E2SG"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_DEVICE_SPEEDGRADE"
+ type="String"
+ defaultValue="2"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_A_CLOCK_RATE"
+ type="Long"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_A_CLOCK_DOMAIN"
+ type="Integer"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_A_RESET_DOMAIN"
+ type="Integer"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_B_CLOCK_RATE"
+ type="Long"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_B_CLOCK_DOMAIN"
+ type="Integer"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <parameter
+ name="AUTO_CLOCK_B_RESET_DOMAIN"
+ type="Integer"
+ defaultValue="-1"
+ onHdl="0"
+ affectsHdl="1" />
+ <interface name="data_a" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="data_a" direction="input" role="datain_a" width="8" />
+ </interface>
+ <interface name="q_a" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="q_a" direction="output" role="dataout_a" width="8" />
+ </interface>
+ <interface name="data_b" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="data_b" direction="input" role="datain_b" width="8" />
+ </interface>
+ <interface name="q_b" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="q_b" direction="output" role="dataout_b" width="8" />
+ </interface>
+ <interface name="address_a" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="address_a" direction="input" role="address_a" width="5" />
+ </interface>
+ <interface name="address_b" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="address_b" direction="input" role="address_b" width="5" />
+ </interface>
+ <interface name="wren_a" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="wren_a" direction="input" role="wren_a" width="1" />
+ </interface>
+ <interface name="wren_b" kind="conduit" start="0">
+ <property name="associatedClock" value="" />
+ <property name="associatedReset" value="" />
+ <property name="prSafe" value="false" />
+ <port name="wren_b" direction="input" role="wren_b" width="1" />
+ </interface>
+ <interface name="clock_a" kind="clock" start="0">
+ <property name="clockRate" value="0" />
+ <property name="externallyDriven" value="false" />
+ <property name="ptfSchematicName" value="" />
+ <port name="clock_a" direction="input" role="clk" width="1" />
+ </interface>
+ <interface name="clock_b" kind="clock" start="0">
+ <property name="clockRate" value="0" />
+ <property name="externallyDriven" value="false" />
+ <property name="ptfSchematicName" value="" />
+ <port name="clock_b" direction="input" role="clk" width="1" />
+ </interface>
+ </perimeter>
+ <entity
+ kind="ip_arria10_e2sg_ram_crw_crw"
+ version="1.0"
+ name="ip_arria10_e2sg_ram_crw_crw">
+ <parameter name="AUTO_GENERATION_ID" value="0" />
+ <parameter name="AUTO_DEVICE" value="10AX115U3F45E2SG" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="AUTO_CLOCK_B_CLOCK_DOMAIN" value="-1" />
+ <parameter name="AUTO_CLOCK_A_CLOCK_DOMAIN" value="-1" />
+ <parameter name="AUTO_UNIQUE_ID" value="" />
+ <parameter name="AUTO_CLOCK_A_RESET_DOMAIN" value="-1" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="AUTO_CLOCK_A_CLOCK_RATE" value="-1" />
+ <parameter name="AUTO_CLOCK_B_RESET_DOMAIN" value="-1" />
+ <parameter name="AUTO_CLOCK_B_CLOCK_RATE" value="-1" />
+ <generatedFiles>
+ <file
+ path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/synth/ip_arria10_e2sg_ram_crw_crw.vhd"
+ attributes="CONTAINS_INLINE_CONFIGURATION" />
+ </generatedFiles>
+ <childGeneratedFiles>
+ <file
+ path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/synth/ip_arria10_e2sg_ram_crw_crw.vhd"
+ attributes="CONTAINS_INLINE_CONFIGURATION" />
+ </childGeneratedFiles>
+ <sourceFiles>
+ <file
+ path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.ip" />
+ </sourceFiles>
+ <childSourceFiles>
+ <file
+ path="/home/software/Altera/19.4.0.64/ip/altera/megafunctions/ram_2port/ram_2_port_hw.tcl" />
+ </childSourceFiles>
+ <messages>
+ <message level="Info" culprit="ip_arria10_e2sg_ram_crw_crw">"Generating: ip_arria10_e2sg_ram_crw_crw"</message>
+ <message level="Info" culprit="ip_arria10_e2sg_ram_crw_crw">"Generating: ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey"</message>
+ </messages>
+ </entity>
+ <entity
+ kind="ram_2port"
+ version="20.0.0"
+ name="ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey">
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_NBE_A" value="true" />
+ <parameter name="GUI_NUMWORDS_B" value="32" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_NUMWORDS_A" value="32" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_MODE" value="1" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_RESOURCE_USAGE" value="1 M20K" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_NBE_B" value="true" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_BYTE_WIDTH_B" value="1" />
+ <parameter name="GUI_FORCE_TO_ZERO" value="false" />
+ <parameter name="GUI_BYTE_WIDTH_A" value="1" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_OPTIMIZATION_OPTION" value="0" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_RDADDRESS_WIDTH" value="5" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_DATA_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="4" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_Q_WIDTH" value="8" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_WIDTH_ECCSTATUS" value="2" />
+ <parameter name="GUI_TDP_EMULATE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_PR" value="false" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_WRADDRESS_WIDTH" value="5" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_MODULE_NAME" value="altera_syncram" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <generatedFiles>
+ <file
+ path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v"
+ attributes="" />
+ </generatedFiles>
+ <childGeneratedFiles>
+ <file
+ path="/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v"
+ attributes="" />
+ </childGeneratedFiles>
+ <sourceFiles>
+ <file
+ path="/home/software/Altera/19.4.0.64/ip/altera/megafunctions/ram_2port/ram_2_port_hw.tcl" />
+ </sourceFiles>
+ <childSourceFiles/>
+ <instantiator instantiator="ip_arria10_e2sg_ram_crw_crw" as="ram_2port_0" />
+ <messages>
+ <message level="Info" culprit="ip_arria10_e2sg_ram_crw_crw">"Generating: ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey"</message>
+ </messages>
+ </entity>
+</deploy>
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_bb.v b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_bb.v
new file mode 100644
index 0000000000000000000000000000000000000000..4e56c70b5eda178d0a5bd2db039af4248aa43585
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_bb.v
@@ -0,0 +1,14 @@
+module ip_arria10_e2sg_ram_crw_crw (
+ input wire [7:0] data_a, // data_a.datain_a
+ output wire [7:0] q_a, // q_a.dataout_a
+ input wire [7:0] data_b, // data_b.datain_b
+ output wire [7:0] q_b, // q_b.dataout_b
+ input wire [4:0] address_a, // address_a.address_a
+ input wire [4:0] address_b, // address_b.address_b
+ input wire wren_a, // wren_a.wren_a
+ input wire wren_b, // wren_b.wren_b
+ input wire clock_a, // clock_a.clk
+ input wire clock_b // clock_b.clk
+ );
+endmodule
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_generation.rpt b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_generation.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a9840028356335214d12cc451819d76534c3b2b1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_generation.rpt
@@ -0,0 +1,75 @@
+Info: Generated by version: 19.4 build 64
+Info: Starting: Create simulation model
+Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.ip --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw --family="Arria 10" --part=10AX115U3F45E2SG
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: Targeting device family: Arria 10.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: 'Output1' tab is unavailable while using 'Customize clocks for A and B ports' clocking method.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: In 'Performance Optimization' tab, Arria 10 does not support 'Timing/Power Optimization' feature.
+Info: ip_arria10_e2sg_ram_crw_crw: "Transforming system: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Naming system components in system: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Processing generation queue"
+Info: ip_arria10_e2sg_ram_crw_crw: "Generating: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Generating: ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey"
+Info: ip_arria10_e2sg_ram_crw_crw: Done "ip_arria10_e2sg_ram_crw_crw" with 2 modules, 2 files
+Info: Generating the following file(s) for MODELSIM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/modelsim_files.tcl
+Info: Generating the following file(s) for VCSMX simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/vcsmx_files.tcl
+Info: Generating the following file(s) for VCS simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/vcs_files.tcl
+Info: Generating the following file(s) for RIVIERA simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/riviera_files.tcl
+Info: Generating the following file(s) for NCSIM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/ncsim_files.tcl
+Info: Generating the following file(s) for XCELIUM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: common/xcelium_files.tcl
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: qsys-generate succeeded.
+Info: Finished: Create simulation model
+Info: Starting: Create Modelsim Project.
+Info: sim-script-gen --system-file=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.ip --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ --use-relative-paths=true
+Info: Generating the following file(s) for MODELSIM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: mentor/msim_setup.tcl
+Info: Generating the following file(s) for VCSMX simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: synopsys/vcsmx/synopsys_sim.setup
+Info: synopsys/vcsmx/vcsmx_setup.sh
+Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
+Info: Generating the following file(s) for RIVIERA simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: aldec/rivierapro_setup.tcl
+Info: Generating the following file(s) for NCSIM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: cadence/cds.lib
+Info: cadence/hdl.var
+Info: cadence/ncsim_setup.sh
+Info: 2 .cds.lib files in cadence/cds_libs/ directory
+Info: Generating the following file(s) for XCELIUM simulator in /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ directory:
+Info: xcelium/cds.lib
+Info: xcelium/hdl.var
+Info: xcelium/xcelium_setup.sh
+Info: 2 .cds.lib files in xcelium/cds_libs/ directory
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: Finished: Create Modelsim Project.
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.ip --block-symbol-file --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw --family="Arria 10" --part=10AX115U3F45E2SG
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: Targeting device family: Arria 10.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: 'Output1' tab is unavailable while using 'Customize clocks for A and B ports' clocking method.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: In 'Performance Optimization' tab, Arria 10 does not support 'Timing/Power Optimization' feature.
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info:
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.ip --synthesis=VHDL --output-directory=/home/hiemstra/git/hdl/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw --family="Arria 10" --part=10AX115U3F45E2SG
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: Targeting device family: Arria 10.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: 'Output1' tab is unavailable while using 'Customize clocks for A and B ports' clocking method.
+: ip_arria10_e2sg_ram_crw_crw.ram_2port_0: In 'Performance Optimization' tab, Arria 10 does not support 'Timing/Power Optimization' feature.
+Info: ip_arria10_e2sg_ram_crw_crw: "Transforming system: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Naming system components in system: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Processing generation queue"
+Info: ip_arria10_e2sg_ram_crw_crw: "Generating: ip_arria10_e2sg_ram_crw_crw"
+Info: ip_arria10_e2sg_ram_crw_crw: "Generating: ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey"
+Info: ip_arria10_e2sg_ram_crw_crw: Done "ip_arria10_e2sg_ram_crw_crw" with 2 modules, 2 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
+Info: Starting: Generate IP Core Documentation
+Info: No documentation filesets were found for components in ip_arria10_e2sg_ram_crw_crw. No files generated.
+Info: Finished: Generate IP Core Documentation
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.v b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.v
new file mode 100644
index 0000000000000000000000000000000000000000..788a2061b8df9148e5a307583300ad9517448892
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.v
@@ -0,0 +1,13 @@
+ ip_arria10_e2sg_ram_crw_crw u0 (
+ .data_a (_connected_to_data_a_), // input, width = 8, data_a.datain_a
+ .q_a (_connected_to_q_a_), // output, width = 8, q_a.dataout_a
+ .data_b (_connected_to_data_b_), // input, width = 8, data_b.datain_b
+ .q_b (_connected_to_q_b_), // output, width = 8, q_b.dataout_b
+ .address_a (_connected_to_address_a_), // input, width = 5, address_a.address_a
+ .address_b (_connected_to_address_b_), // input, width = 5, address_b.address_b
+ .wren_a (_connected_to_wren_a_), // input, width = 1, wren_a.wren_a
+ .wren_b (_connected_to_wren_b_), // input, width = 1, wren_b.wren_b
+ .clock_a (_connected_to_clock_a_), // input, width = 1, clock_a.clk
+ .clock_b (_connected_to_clock_b_) // input, width = 1, clock_b.clk
+ );
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3a9ae4ad18436342d23f23748225bbee98ec25ae
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
@@ -0,0 +1,29 @@
+ component ip_arria10_e2sg_ram_crw_crw is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
+ q_a : out std_logic_vector(7 downto 0); -- dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ q_b : out std_logic_vector(7 downto 0); -- dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clk
+ clock_b : in std_logic := 'X' -- clk
+ );
+ end component ip_arria10_e2sg_ram_crw_crw;
+
+ u0 : component ip_arria10_e2sg_ram_crw_crw
+ port map (
+ data_a => CONNECTED_TO_data_a, -- data_a.datain_a
+ q_a => CONNECTED_TO_q_a, -- q_a.dataout_a
+ data_b => CONNECTED_TO_data_b, -- data_b.datain_b
+ q_b => CONNECTED_TO_q_b, -- q_b.dataout_b
+ address_a => CONNECTED_TO_address_a, -- address_a.address_a
+ address_b => CONNECTED_TO_address_b, -- address_b.address_b
+ wren_a => CONNECTED_TO_wren_a, -- wren_a.wren_a
+ wren_b => CONNECTED_TO_wren_b, -- wren_b.wren_b
+ clock_a => CONNECTED_TO_clock_a, -- clock_a.clk
+ clock_b => CONNECTED_TO_clock_b -- clock_b.clk
+ );
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed696209ef8e9068e027768593d014a7b83c93c3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
@@ -0,0 +1,94 @@
+-- (C) 2001-2019 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files from any of the foregoing (including device programming or simulation
+-- files), and any associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License Subscription
+-- Agreement, Intel FPGA IP License Agreement, or other applicable
+-- license agreement, including, without limitation, that your use is for the
+-- sole purpose of programming logic devices manufactured by Intel and sold by
+-- Intel or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey IS
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+ clock_a : IN STD_LOGIC := '1';
+ clock_b : IN STD_LOGIC;
+ data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ );
+END ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+ q_a <= sub_wire0 (7 DOWNTO 0);
+ q_b <= sub_wire1 (7 DOWNTO 0);
+
+ altera_syncram_component : altera_syncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => "./ram_1024.hex",
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => 32,
+ numwords_b => 32,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_sclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_sclr_b => "NONE",
+ outdata_reg_a => "CLOCK0",
+ outdata_reg_b => "CLOCK1",
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => 5,
+ widthad_b => 5,
+ width_a => 8,
+ width_b => 8,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ PORT MAP (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clock_a,
+ clock1 => clock_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => sub_wire0,
+ q_b => sub_wire1
+ );
+
+
+
+END SYN;
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v
new file mode 100644
index 0000000000000000000000000000000000000000..6491044c085973c98a8f97f516d17aa671d51f5a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/synth/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.v
@@ -0,0 +1,130 @@
+// (C) 2001-2019 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey (
+ address_a,
+ address_b,
+ clock_a,
+ clock_b,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [4:0] address_a;
+ input [4:0] address_b;
+ input clock_a;
+ input clock_b;
+ input [7:0] data_a;
+ input [7:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [7:0] q_a;
+ output [7:0] q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock_a;
+ tri0 wren_a;
+ tri0 wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire [7:0] sub_wire1;
+ wire [7:0] q_a = sub_wire0[7:0];
+ wire [7:0] q_b = sub_wire1[7:0];
+
+ altera_syncram altera_syncram_component (
+ .address_a (address_a),
+ .address_b (address_b),
+ .clock0 (clock_a),
+ .clock1 (clock_b),
+ .data_a (data_a),
+ .data_b (data_b),
+ .wren_a (wren_a),
+ .wren_b (wren_b),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .address2_a (1'b1),
+ .address2_b (1'b1),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccencbypass (1'b0),
+ .eccencparity (8'b0),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1),
+ .sclr (1'b0));
+ defparam
+ altera_syncram_component.address_reg_b = "CLOCK1",
+ altera_syncram_component.clock_enable_input_a = "BYPASS",
+ altera_syncram_component.clock_enable_input_b = "BYPASS",
+ altera_syncram_component.clock_enable_output_a = "BYPASS",
+ altera_syncram_component.clock_enable_output_b = "BYPASS",
+ altera_syncram_component.indata_reg_b = "CLOCK1",
+`ifdef NO_PLI
+ altera_syncram_component.init_file = "./ram_1024.rif"
+`else
+ altera_syncram_component.init_file = "./ram_1024.hex"
+`endif
+,
+ altera_syncram_component.intended_device_family = "Arria 10",
+ altera_syncram_component.lpm_type = "altera_syncram",
+ altera_syncram_component.numwords_a = 32,
+ altera_syncram_component.numwords_b = 32,
+ altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altera_syncram_component.outdata_aclr_a = "NONE",
+ altera_syncram_component.outdata_sclr_a = "NONE",
+ altera_syncram_component.outdata_aclr_b = "NONE",
+ altera_syncram_component.outdata_sclr_b = "NONE",
+ altera_syncram_component.outdata_reg_a = "CLOCK0",
+ altera_syncram_component.outdata_reg_b = "CLOCK1",
+ altera_syncram_component.power_up_uninitialized = "FALSE",
+ altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+ altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
+ altera_syncram_component.widthad_a = 5,
+ altera_syncram_component.widthad_b = 5,
+ altera_syncram_component.width_a = 8,
+ altera_syncram_component.width_b = 8,
+ altera_syncram_component.width_byteena_a = 1,
+ altera_syncram_component.width_byteena_b = 1;
+
+
+
+
+
+
+
+
+
+
+
+endmodule
+
+
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/aldec/rivierapro_setup.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b1d88d574f5071313d47cba4275b478bb5afb0a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/aldec/rivierapro_setup.tcl
@@ -0,0 +1,353 @@
+
+# (C) 2001-2021 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Intel
+# Program License Subscription Agreement, Intel MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Intel and sold by Intel
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_arria10_e2sg_ram_crw_crw
+#
+# Intel recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Intel simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_arria10_e2sg_ram_crw_crw is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Intel IP
+# within the Quartus project, and generate a unified
+# script which supports all the Intel IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/home/software/Altera/19.4.0.64/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+if ![info exists SILENCE] {
+ set SILENCE "false"
+}
+
+
+# ----------------------------------------
+# Source Common Tcl File
+source $QSYS_SIMDIR/common/riviera_files.tcl
+
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+set LD_LIBRARY_PATH [dict create]
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+ set SIMULATOR_TOOL_BITNESS "bit_32"
+} else {
+ set SIMULATOR_TOOL_BITNESS "bit_64"
+}
+set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [ip_arria10_e2sg_ram_crw_crw::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
+if {[dict size $LD_LIBRARY_PATH] !=0 } {
+ set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
+ setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
+}
+append ELAB_OPTIONS [subst [ip_arria10_e2sg_ram_crw_crw::get_elab_options $SIMULATOR_TOOL_BITNESS]]
+append SIM_OPTIONS [subst [ip_arria10_e2sg_ram_crw_crw::get_sim_options $SIMULATOR_TOOL_BITNESS]]
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+ set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+ scripterconf -tcl
+ createdesign "$TOP_LEVEL_NAME" "."
+ opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] file_copy"
+ }
+ set memory_files [list]
+ set memory_files [concat $memory_files [ip_arria10_e2sg_ram_crw_crw::get_memory_files "$QSYS_SIMDIR"]]
+ foreach file $memory_files { file copy -force $file ./ }
+}
+
+# ----------------------------------------
+# Create compilation libraries
+
+set logical_libraries [list "work" "work_lib" "altera" "lpm" "sgate" "altera_mf" "altera_lnsim" "twentynm" "twentynm_hssi" "twentynm_hip"]
+
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work
+vmap work ./libraries/work
+ensure_lib ./libraries/altera
+vmap altera ./libraries/altera
+ensure_lib ./libraries/lpm
+vmap lpm ./libraries/lpm
+ensure_lib ./libraries/sgate
+vmap sgate ./libraries/sgate
+ensure_lib ./libraries/altera_mf
+vmap altera_mf ./libraries/altera_mf
+ensure_lib ./libraries/altera_lnsim
+vmap altera_lnsim ./libraries/altera_lnsim
+ensure_lib ./libraries/twentynm
+vmap twentynm ./libraries/twentynm
+ensure_lib ./libraries/twentynm_hssi
+vmap twentynm_hssi ./libraries/twentynm_hssi
+ensure_lib ./libraries/twentynm_hip
+vmap twentynm_hip ./libraries/twentynm_hip
+set design_libraries [dict create]
+set design_libraries [dict merge $design_libraries [ip_arria10_e2sg_ram_crw_crw::get_design_libraries]]
+set libraries [dict keys $design_libraries]
+foreach library $libraries {
+ ensure_lib ./libraries/$library/
+ vmap $library ./libraries/$library/
+ lappend logical_libraries $library
+}
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] dev_com"
+ }
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/twentynm_atoms_ncrypt.v" -work twentynm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_atoms.vhd" -work twentynm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_components.vhd" -work twentynm
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/twentynm_hssi_atoms_ncrypt.v" -work twentynm_hssi
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_components.vhd" -work twentynm_hssi
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_atoms.vhd" -work twentynm_hssi
+ eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/twentynm_hip_atoms_ncrypt.v" -work twentynm_hip
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_components.vhd" -work twentynm_hip
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_atoms.vhd" -work twentynm_hip
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] com"
+ }
+ set design_files [dict create]
+ set design_files [dict merge [ip_arria10_e2sg_ram_crw_crw::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+ set common_design_files [dict values $design_files]
+ foreach file $common_design_files {
+ eval $file
+ }
+ set design_files [list]
+ set design_files [concat $design_files [ip_arria10_e2sg_ram_crw_crw::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+ foreach file $design_files {
+ eval $file
+ }
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] elab"
+ }
+ set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
+ foreach library $logical_libraries { append elabcommand " -L $library" }
+ append elabcommand " $TOP_LEVEL_NAME"
+ eval vsim +access +r $elabcommand
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] elab_debug"
+ }
+ set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
+ foreach library $logical_libraries { append elabcommand " -L $library" }
+ append elabcommand " $TOP_LEVEL_NAME"
+ eval vsim -dbg -O2 +access +r $elabcommand
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Qsys base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
+}
+file_copy
+h
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..c4bbf4b617cde8c5eea291ace049725ea8c898fe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds.lib
@@ -0,0 +1,21 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./libraries/work/
+DEFINE ram_2port_2000 ./libraries/ram_2port_2000/
+DEFINE ip_arria10_e2sg_ram_crw_crw ./libraries/ip_arria10_e2sg_ram_crw_crw/
+DEFINE altera ./libraries/altera/
+DEFINE lpm ./libraries/lpm/
+DEFINE sgate ./libraries/sgate/
+DEFINE altera_mf ./libraries/altera_mf/
+DEFINE altera_lnsim ./libraries/altera_lnsim/
+DEFINE twentynm ./libraries/twentynm/
+DEFINE twentynm_hssi ./libraries/twentynm_hssi/
+DEFINE twentynm_hip ./libraries/twentynm_hip/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..b69bd46f323b6c56fe97c3a27864f4a0d9ac517a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib
@@ -0,0 +1,20 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./../libraries/work/
+DEFINE altera ./../libraries/altera/
+DEFINE lpm ./../libraries/lpm/
+DEFINE sgate ./../libraries/sgate/
+DEFINE altera_mf ./../libraries/altera_mf/
+DEFINE altera_lnsim ./../libraries/altera_lnsim/
+DEFINE twentynm ./../libraries/twentynm/
+DEFINE twentynm_hssi ./../libraries/twentynm_hssi/
+DEFINE twentynm_hip ./../libraries/twentynm_hip/
+DEFINE ip_arria10_e2sg_ram_crw_crw ./../libraries/ip_arria10_e2sg_ram_crw_crw/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ram_2port_2000.cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ram_2port_2000.cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..cf2afc78bfef3b8c8ca80de405fd5658af814414
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/cds_libs/ram_2port_2000.cds.lib
@@ -0,0 +1,20 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./../libraries/work/
+DEFINE altera ./../libraries/altera/
+DEFINE lpm ./../libraries/lpm/
+DEFINE sgate ./../libraries/sgate/
+DEFINE altera_mf ./../libraries/altera_mf/
+DEFINE altera_lnsim ./../libraries/altera_lnsim/
+DEFINE twentynm ./../libraries/twentynm/
+DEFINE twentynm_hssi ./../libraries/twentynm_hssi/
+DEFINE twentynm_hip ./../libraries/twentynm_hip/
+DEFINE ram_2port_2000 ./../libraries/ram_2port_2000/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/hdl.var b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/hdl.var
new file mode 100644
index 0000000000000000000000000000000000000000..c1b781426d042871372b372708619b1944b149db
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/hdl.var
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/ncsim_setup.sh b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/ncsim_setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..93b2abe1da941f4861db692a7a51ee7904384d16
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/cadence/ncsim_setup.sh
@@ -0,0 +1,327 @@
+
+# (C) 2001-2021 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Intel
+# Program License Subscription Agreement, Intel MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Intel and sold by Intel
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_arria10_e2sg_ram_crw_crw
+#
+# Intel recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Intel simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_arria10_e2sg_ram_crw_crw is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Intel IP
+# within the Quartus project, and generate a unified
+# script which supports all the Intel IP within the design.
+# ----------------------------------------
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/software/Altera/19.4.0.64/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+#-------------------------------------------
+# check tclsh version no earlier than 8.5
+version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
+if [ $version -eq -1 ]; then
+ echo "Error: Minimum required tcl package version is 8.5." >&2
+ exit 1
+fi
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+ SIMULATOR_TOOL_BITNESS="bit_32"
+else
+ SIMULATOR_TOOL_BITNESS="bit_64"
+fi
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
+source $QSYS_SIMDIR/common/ncsim_files.tcl
+set LD_LIBRARY_PATH [dict create]
+set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [ip_arria10_e2sg_ram_crw_crw::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
+if {[dict size $LD_LIBRARY_PATH] !=0 } {
+ set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
+ puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
+}
+
+set ELAB_OPTIONS ""
+append ELAB_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_elab_options $SIMULATOR_TOOL_BITNESS]
+puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
+set SIM_OPTIONS ""
+append SIM_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_sim_options $SIMULATOR_TOOL_BITNESS]
+puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+eval $cmd_output
+
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set libraries [dict create]
+source $QSYS_SIMDIR/common/ncsim_files.tcl
+set libraries [dict merge $libraries [ip_arria10_e2sg_ram_crw_crw::get_design_libraries]]
+set design_libraries [dict keys $libraries]
+foreach file $design_libraries { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_libraries=$cmd_output
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/twentynm/
+mkdir -p ./libraries/twentynm_hssi/
+mkdir -p ./libraries/twentynm_hip/
+for library in $design_libraries
+do
+ mkdir -p ./libraries/$library
+done
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set memory_files [list]
+source $QSYS_SIMDIR/common/ncsim_files.tcl
+set memory_files [concat $memory_files [ip_arria10_e2sg_ram_crw_crw::get_memory_files "$QSYS_SIMDIR"]]
+foreach file $memory_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+memory_files=$cmd_output
+if [ $SKIP_FILE_COPY -eq 0 ]; then
+ for file in $memory_files
+ do
+ cp -f $file ./
+ done
+fi
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_atoms_ncrypt.v" -work twentynm
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_atoms.vhd" -work twentynm
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_components.vhd" -work twentynm
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_hssi_atoms_ncrypt.v" -work twentynm_hssi
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_components.vhd" -work twentynm_hssi
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_atoms.vhd" -work twentynm_hssi
+ ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_hip_atoms_ncrypt.v" -work twentynm_hip
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_components.vhd" -work twentynm_hip
+ ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_atoms.vhd" -work twentynm_hip
+fi
+
+# ----------------------------------------
+# get common system verilog package design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set design_files [dict create]
+source $QSYS_SIMDIR/common/ncsim_files.tcl
+set design_files [dict merge $design_files [ip_arria10_e2sg_ram_crw_crw::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set common_design_files [dict values $design_files]
+foreach file $common_design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+common_design_files=$cmd_output
+
+# ----------------------------------------
+# get design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set files [list]
+source $QSYS_SIMDIR/common/ncsim_files.tcl
+set files [concat $files [ip_arria10_e2sg_ram_crw_crw::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set design_files $files
+foreach file $design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_files=$cmd_output
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ eval "$common_design_files"
+ eval "$design_files"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ export GENERIC_PARAM_COMPAT_CHECK=1
+ ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/modelsim_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/modelsim_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..38d58cac49bde688f31f77ff06475f2b34039a1a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/modelsim_files.tcl
@@ -0,0 +1,67 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_design_libraries {} {
+ set libraries [dict create]
+ dict set libraries ram_2port_2000 1
+ dict set libraries ip_arria10_e2sg_ram_crw_crw 1
+ return $libraries
+ }
+
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [list]
+ lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd"]\" -work ram_2port_2000"
+ lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/ip_arria10_e2sg_ram_crw_crw.vhd"]\" -work ip_arria10_e2sg_ram_crw_crw"
+ return $design_files
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ append ELAB_OPTIONS { -t fs}
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+ proc normalize_path {FILEPATH} {
+ if {[catch { package require fileutil } err]} {
+ return $FILEPATH
+ }
+ set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
+ if {[file pathtype $FILEPATH] eq "relative"} {
+ set path [fileutil::relative [pwd] $path]
+ }
+ return $path
+ }
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/ncsim_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/ncsim_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7885affcfd39ac84b4d92bc529876ff0a3e69113
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/ncsim_files.tcl
@@ -0,0 +1,56 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_design_libraries {} {
+ set libraries [dict create]
+ dict set libraries ram_2port_2000 1
+ dict set libraries ip_arria10_e2sg_ram_crw_crw 1
+ return $libraries
+ }
+
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [list]
+ lappend design_files "ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd\" -work ram_2port_2000 -cdslib ./cds_libs/ram_2port_2000.cds.lib"
+ lappend design_files "ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/ip_arria10_e2sg_ram_crw_crw.vhd\" -work ip_arria10_e2sg_ram_crw_crw"
+ return $design_files
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/riviera_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/riviera_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7a0206d4d807eafcfc281cc2930118f6ef9b53a3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/riviera_files.tcl
@@ -0,0 +1,66 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_design_libraries {} {
+ set libraries [dict create]
+ dict set libraries ram_2port_2000 1
+ dict set libraries ip_arria10_e2sg_ram_crw_crw 1
+ return $libraries
+ }
+
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [list]
+ lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd"]\" -work ram_2port_2000"
+ lappend design_files "vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/ip_arria10_e2sg_ram_crw_crw.vhd"]\" -work ip_arria10_e2sg_ram_crw_crw"
+ return $design_files
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+ proc normalize_path {FILEPATH} {
+ if {[catch { package require fileutil } err]} {
+ return $FILEPATH
+ }
+ set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
+ if {[file pathtype $FILEPATH] eq "relative"} {
+ set path [fileutil::relative [pwd] $path]
+ }
+ return $path
+ }
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcs_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcs_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c262463e1f817e23e16f5b7e70cebe81efe259cf
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcs_files.tcl
@@ -0,0 +1,47 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {QSYS_SIMDIR} {
+ set design_files [dict create]
+ error "Skipping VCS script generation since VHDL file $QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd is required for simulation"
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcsmx_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcsmx_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..edaeb6bebfae5d6c0f61490112e61767f0cd5753
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/vcsmx_files.tcl
@@ -0,0 +1,56 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_design_libraries {} {
+ set libraries [dict create]
+ dict set libraries ram_2port_2000 1
+ dict set libraries ip_arria10_e2sg_ram_crw_crw 1
+ return $libraries
+ }
+
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [list]
+ lappend design_files "vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd\" -work ram_2port_2000"
+ lappend design_files "vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/ip_arria10_e2sg_ram_crw_crw.vhd\" -work ip_arria10_e2sg_ram_crw_crw"
+ return $design_files
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/xcelium_files.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/xcelium_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..32c44128567a7d16a379a54f9bc6eef1e4031960
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/common/xcelium_files.tcl
@@ -0,0 +1,56 @@
+
+namespace eval ip_arria10_e2sg_ram_crw_crw {
+ proc get_design_libraries {} {
+ set libraries [dict create]
+ dict set libraries ram_2port_2000 1
+ dict set libraries ip_arria10_e2sg_ram_crw_crw 1
+ return $libraries
+ }
+
+ proc get_memory_files {QSYS_SIMDIR} {
+ set memory_files [list]
+ return $memory_files
+ }
+
+ proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [dict create]
+ return $design_files
+ }
+
+ proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
+ set design_files [list]
+ lappend design_files "xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/../ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd\" -work ram_2port_2000 -cdslib ./cds_libs/ram_2port_2000.cds.lib"
+ lappend design_files "xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/ip_arria10_e2sg_ram_crw_crw.vhd\" -work ip_arria10_e2sg_ram_crw_crw"
+ return $design_files
+ }
+
+ proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
+ set ELAB_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ELAB_OPTIONS
+ }
+
+
+ proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
+ set SIM_OPTIONS ""
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $SIM_OPTIONS
+ }
+
+
+ proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
+ set ENV_VARIABLES [dict create]
+ set LD_LIBRARY_PATH [dict create]
+ dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
+ if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
+ } else {
+ }
+ return $ENV_VARIABLES
+ }
+
+
+}
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ip_arria10_e2sg_ram_crw_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f64a23cd832d75e95228d48a0a5f7fd20c976708
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -0,0 +1,59 @@
+-- ip_arria10_e2sg_ram_crw_crw.vhd
+
+-- Generated using ACDS version 19.4 64
+
+library IEEE;
+library ram_2port_2000;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_arria10_e2sg_ram_crw_crw is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => '0'); -- data_a.datain_a
+ q_a : out std_logic_vector(7 downto 0); -- q_a.dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => '0'); -- data_b.datain_b
+ q_b : out std_logic_vector(7 downto 0); -- q_b.dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => '0'); -- address_a.address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => '0'); -- address_b.address_b
+ wren_a : in std_logic := '0'; -- wren_a.wren_a
+ wren_b : in std_logic := '0'; -- wren_b.wren_b
+ clock_a : in std_logic := '0'; -- clock_a.clk
+ clock_b : in std_logic := '0' -- clock_b.clk
+ );
+end entity ip_arria10_e2sg_ram_crw_crw;
+
+architecture rtl of ip_arria10_e2sg_ram_crw_crw is
+ component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
+ q_a : out std_logic_vector(7 downto 0); -- dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ q_b : out std_logic_vector(7 downto 0); -- dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clk
+ clock_b : in std_logic := 'X' -- clk
+ );
+ end component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp;
+
+ for ram_2port_0 : ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp
+ use entity ram_2port_2000.ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey;
+begin
+
+ ram_2port_0 : component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp
+ port map (
+ data_a => data_a, -- data_a.datain_a
+ q_a => q_a, -- q_a.dataout_a
+ data_b => data_b, -- data_b.datain_b
+ q_b => q_b, -- q_b.dataout_b
+ address_a => address_a, -- address_a.address_a
+ address_b => address_b, -- address_b.address_b
+ wren_a => wren_a, -- wren_a.wren_a
+ wren_b => wren_b, -- wren_b.wren_b
+ clock_a => clock_a, -- clock_a.clk
+ clock_b => clock_b -- clock_b.clk
+ );
+
+end architecture rtl; -- of ip_arria10_e2sg_ram_crw_crw
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/mentor/msim_setup.tcl b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/mentor/msim_setup.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6392b9c021dcb8d37bfa6e7ad58ece732086285a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/mentor/msim_setup.tcl
@@ -0,0 +1,361 @@
+
+# (C) 2001-2021 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Intel
+# Program License Subscription Agreement, Intel MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Intel and sold by Intel
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_arria10_e2sg_ram_crw_crw
+#
+# Intel recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level script that compiles Intel simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_arria10_e2sg_ram_crw_crw is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Intel IP
+# within the Quartus project, and generate a unified
+# script which supports all the Intel IP within the design.
+# ----------------------------------------
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] {
+ set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
+ set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] {
+ set TOP_LEVEL_NAME "ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw"
+}
+
+if ![info exists QSYS_SIMDIR] {
+ set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] {
+ set QUARTUS_INSTALL_DIR "/home/software/Altera/19.4.0.64/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
+ set USER_DEFINED_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
+ set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
+ set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+
+if ![info exists USER_DEFINED_ELAB_OPTIONS] {
+ set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+if ![info exists SILENCE] {
+ set SILENCE "false"
+}
+
+if ![info exists FORCE_MODELSIM_AE_SELECTION] {
+ set FORCE_MODELSIM_AE_SELECTION "false"
+}
+
+# ----------------------------------------
+# Source Common Tcl File
+source $QSYS_SIMDIR/common/modelsim_files.tcl
+
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+set LD_LIBRARY_PATH [dict create]
+if ![ string match "*-64 vsim*" [ vsimVersionString ] ] {
+ set SIMULATOR_TOOL_BITNESS "bit_32"
+} else {
+ set SIMULATOR_TOOL_BITNESS "bit_64"
+}
+set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [ip_arria10_e2sg_ram_crw_crw::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
+if {[dict size $LD_LIBRARY_PATH] !=0 } {
+ set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
+ setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
+}
+append ELAB_OPTIONS [subst [ip_arria10_e2sg_ram_crw_crw::get_elab_options $SIMULATOR_TOOL_BITNESS]]
+append SIM_OPTIONS [subst [ip_arria10_e2sg_ram_crw_crw::get_sim_options $SIMULATOR_TOOL_BITNESS]]
+
+proc modelsim_ae_select {force_select_modelsim_ae} {
+ if [string is true -strict $force_select_modelsim_ae] {
+ return 1
+ }
+ return [string match -nocase "*ModelSim*Intel*FPGA*" [ vsimVersionString ]]
+
+}
+
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] file_copy"
+ }
+ set memory_files [list]
+ set memory_files [concat $memory_files [ip_arria10_e2sg_ram_crw_crw::get_memory_files "$QSYS_SIMDIR"]]
+ foreach file $memory_files { file copy -force $file ./ }
+}
+
+# ----------------------------------------
+# Create compilation libraries
+
+set logical_libraries [list "work" "work_lib" "altera" "lpm" "sgate" "altera_mf" "altera_lnsim" "twentynm" "twentynm_hssi" "twentynm_hip"]
+
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib ./libraries/
+ensure_lib ./libraries/work/
+vmap work ./libraries/work/
+vmap work_lib ./libraries/work/
+if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
+ ensure_lib ./libraries/altera/
+ vmap altera ./libraries/altera/
+ ensure_lib ./libraries/lpm/
+ vmap lpm ./libraries/lpm/
+ ensure_lib ./libraries/sgate/
+ vmap sgate ./libraries/sgate/
+ ensure_lib ./libraries/altera_mf/
+ vmap altera_mf ./libraries/altera_mf/
+ ensure_lib ./libraries/altera_lnsim/
+ vmap altera_lnsim ./libraries/altera_lnsim/
+ ensure_lib ./libraries/twentynm/
+ vmap twentynm ./libraries/twentynm/
+ ensure_lib ./libraries/twentynm_hssi/
+ vmap twentynm_hssi ./libraries/twentynm_hssi/
+ ensure_lib ./libraries/twentynm_hip/
+ vmap twentynm_hip ./libraries/twentynm_hip/
+}
+set design_libraries [dict create]
+set design_libraries [dict merge $design_libraries [ip_arria10_e2sg_ram_crw_crw::get_design_libraries]]
+set libraries [dict keys $design_libraries]
+foreach library $libraries {
+ ensure_lib ./libraries/$library/
+ vmap $library ./libraries/$library/
+ lappend logical_libraries $library
+}
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] dev_com"
+ }
+ if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v" -work twentynm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_atoms.vhd" -work twentynm
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_components.vhd" -work twentynm
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/twentynm_hssi_atoms_ncrypt.v" -work twentynm_hssi
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_components.vhd" -work twentynm_hssi
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_atoms.vhd" -work twentynm_hssi
+ eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/twentynm_hip_atoms_ncrypt.v" -work twentynm_hip
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_components.vhd" -work twentynm_hip
+ eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_atoms.vhd" -work twentynm_hip
+ }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] com"
+ }
+ set design_files [dict create]
+ set design_files [dict merge [ip_arria10_e2sg_ram_crw_crw::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+ set common_design_files [dict values $design_files]
+ foreach file $common_design_files {
+ eval $file
+ }
+ set design_files [list]
+ set design_files [concat $design_files [ip_arria10_e2sg_ram_crw_crw::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+ foreach file $design_files {
+ eval $file
+ }
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] elab"
+ }
+ set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
+ foreach library $logical_libraries { append elabcommand " -L $library" }
+ append elabcommand " $TOP_LEVEL_NAME"
+ eval vsim $elabcommand
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+ if [string is false -strict $SILENCE] {
+ echo "\[exec\] elab_debug"
+ }
+ set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
+ foreach library $logical_libraries { append elabcommand " -L $library" }
+ append elabcommand " $TOP_LEVEL_NAME"
+ eval vsim -voptargs=+acc $elabcommand
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+ dev_com
+ com
+ elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+ dev_com
+ com
+ elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+ echo "List Of Command Line Aliases"
+ echo
+ echo "file_copy -- Copy ROM/RAM files to simulation directory"
+ echo
+ echo "dev_com -- Compile device library files"
+ echo
+ echo "com -- Compile the design files in correct order"
+ echo
+ echo "elab -- Elaborate top level design"
+ echo
+ echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
+ echo
+ echo "ld -- Compile all the design files and elaborate the top level design"
+ echo
+ echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+ echo
+ echo
+ echo
+ echo "List Of Variables"
+ echo
+ echo "TOP_LEVEL_NAME -- Top level module name."
+ echo " For most designs, this should be overridden"
+ echo " to enable the elab/elab_debug aliases."
+ echo
+ echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
+ echo
+ echo "QSYS_SIMDIR -- Qsys base simulation directory."
+ echo
+ echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
+ echo
+ echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
+ echo
+ echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
+ echo
+ echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
+ echo
+ echo "FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always."
+}
+file_copy
+h
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/synopsys_sim.setup b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/synopsys_sim.setup
new file mode 100644
index 0000000000000000000000000000000000000000..4075e5625f75095cdeeb70814c730f9e9b6de13d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/synopsys_sim.setup
@@ -0,0 +1,15 @@
+
+WORK > DEFAULT
+DEFAULT: ./libraries/work/
+work: ./libraries/work/
+ram_2port_2000: ./libraries/ram_2port_2000/
+ip_arria10_e2sg_ram_crw_crw: ./libraries/ip_arria10_e2sg_ram_crw_crw/
+altera: ./libraries/altera/
+lpm: ./libraries/lpm/
+sgate: ./libraries/sgate/
+altera_mf: ./libraries/altera_mf/
+altera_lnsim: ./libraries/altera_lnsim/
+twentynm: ./libraries/twentynm/
+twentynm_hssi: ./libraries/twentynm_hssi/
+twentynm_hip: ./libraries/twentynm_hip/
+LIBRARY_SCAN = TRUE
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/vcsmx_setup.sh b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/vcsmx_setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..fd2b67c6dd898d92efa1eaf6470b8996c1539ed0
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -0,0 +1,327 @@
+
+# (C) 2001-2021 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Intel
+# Program License Subscription Agreement, Intel MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Intel and sold by Intel
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_arria10_e2sg_ram_crw_crw
+#
+# Intel recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# To write a top-level shell script that compiles Intel simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_arria10_e2sg_ram_crw_crw is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Intel IP
+# within the Quartus project, and generate a unified
+# script which supports all the Intel IP within the design.
+# ----------------------------------------
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/software/Altera/19.4.0.64/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+#-------------------------------------------
+# check tclsh version no earlier than 8.5
+version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
+if [ $version -eq -1 ]; then
+ echo "Error: Minimum required tcl package version is 8.5." >&2
+ exit 1
+fi
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+ SIMULATOR_TOOL_BITNESS="bit_32"
+else
+ SIMULATOR_TOOL_BITNESS="bit_64"
+fi
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
+source $QSYS_SIMDIR/common/vcsmx_files.tcl
+set LD_LIBRARY_PATH [dict create]
+set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [ip_arria10_e2sg_ram_crw_crw::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
+if {[dict size $LD_LIBRARY_PATH] !=0 } {
+ set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
+ puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
+}
+
+set ELAB_OPTIONS ""
+append ELAB_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_elab_options $SIMULATOR_TOOL_BITNESS]
+puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
+set SIM_OPTIONS ""
+append SIM_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_sim_options $SIMULATOR_TOOL_BITNESS]
+puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+eval $cmd_output
+
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set libraries [dict create]
+source $QSYS_SIMDIR/common/vcsmx_files.tcl
+set libraries [dict merge $libraries [ip_arria10_e2sg_ram_crw_crw::get_design_libraries]]
+set design_libraries [dict keys $libraries]
+foreach file $design_libraries { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_libraries=$cmd_output
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/twentynm/
+mkdir -p ./libraries/twentynm_hssi/
+mkdir -p ./libraries/twentynm_hip/
+for library in $design_libraries
+do
+ mkdir -p ./libraries/$library
+done
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set memory_files [list]
+source $QSYS_SIMDIR/common/vcsmx_files.tcl
+set memory_files [concat $memory_files [ip_arria10_e2sg_ram_crw_crw::get_memory_files "$QSYS_SIMDIR"]]
+foreach file $memory_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+memory_files=$cmd_output
+if [ $SKIP_FILE_COPY -eq 0 ]; then
+ for file in $memory_files
+ do
+ cp -f $file ./
+ done
+fi
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/twentynm_atoms_ncrypt.v" -work twentynm
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_atoms.vhd" -work twentynm
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_components.vhd" -work twentynm
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/twentynm_hssi_atoms_ncrypt.v" -work twentynm_hssi
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_components.vhd" -work twentynm_hssi
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_atoms.vhd" -work twentynm_hssi
+ vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/twentynm_hip_atoms_ncrypt.v" -work twentynm_hip
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_components.vhd" -work twentynm_hip
+ vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_atoms.vhd" -work twentynm_hip
+fi
+
+# ----------------------------------------
+# get common system verilog package design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set design_files [dict create]
+source $QSYS_SIMDIR/common/vcsmx_files.tcl
+set design_files [dict merge $design_files [ip_arria10_e2sg_ram_crw_crw::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set common_design_files [dict values $design_files]
+foreach file $common_design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+common_design_files=$cmd_output
+
+# ----------------------------------------
+# get design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set files [list]
+source $QSYS_SIMDIR/common/vcsmx_files.tcl
+set files [concat $files [ip_arria10_e2sg_ram_crw_crw::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set design_files $files
+foreach file $design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_files=$cmd_output
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ eval "$common_design_files"
+ eval "$design_files"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ vcs -lca -t ps -liblist_work $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..c4bbf4b617cde8c5eea291ace049725ea8c898fe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds.lib
@@ -0,0 +1,21 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./libraries/work/
+DEFINE ram_2port_2000 ./libraries/ram_2port_2000/
+DEFINE ip_arria10_e2sg_ram_crw_crw ./libraries/ip_arria10_e2sg_ram_crw_crw/
+DEFINE altera ./libraries/altera/
+DEFINE lpm ./libraries/lpm/
+DEFINE sgate ./libraries/sgate/
+DEFINE altera_mf ./libraries/altera_mf/
+DEFINE altera_lnsim ./libraries/altera_lnsim/
+DEFINE twentynm ./libraries/twentynm/
+DEFINE twentynm_hssi ./libraries/twentynm_hssi/
+DEFINE twentynm_hip ./libraries/twentynm_hip/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..b69bd46f323b6c56fe97c3a27864f4a0d9ac517a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ip_arria10_e2sg_ram_crw_crw.cds.lib
@@ -0,0 +1,20 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./../libraries/work/
+DEFINE altera ./../libraries/altera/
+DEFINE lpm ./../libraries/lpm/
+DEFINE sgate ./../libraries/sgate/
+DEFINE altera_mf ./../libraries/altera_mf/
+DEFINE altera_lnsim ./../libraries/altera_lnsim/
+DEFINE twentynm ./../libraries/twentynm/
+DEFINE twentynm_hssi ./../libraries/twentynm_hssi/
+DEFINE twentynm_hip ./../libraries/twentynm_hip/
+DEFINE ip_arria10_e2sg_ram_crw_crw ./../libraries/ip_arria10_e2sg_ram_crw_crw/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ram_2port_2000.cds.lib b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ram_2port_2000.cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..cf2afc78bfef3b8c8ca80de405fd5658af814414
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/cds_libs/ram_2port_2000.cds.lib
@@ -0,0 +1,20 @@
+
+DEFINE std $CDS_ROOT/tools/inca/files/STD/
+DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
+DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
+DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
+DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
+DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
+DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
+DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work ./../libraries/work/
+DEFINE altera ./../libraries/altera/
+DEFINE lpm ./../libraries/lpm/
+DEFINE sgate ./../libraries/sgate/
+DEFINE altera_mf ./../libraries/altera_mf/
+DEFINE altera_lnsim ./../libraries/altera_lnsim/
+DEFINE twentynm ./../libraries/twentynm/
+DEFINE twentynm_hssi ./../libraries/twentynm_hssi/
+DEFINE twentynm_hip ./../libraries/twentynm_hip/
+DEFINE ram_2port_2000 ./../libraries/ram_2port_2000/
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/hdl.var b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/hdl.var
new file mode 100644
index 0000000000000000000000000000000000000000..c1b781426d042871372b372708619b1944b149db
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/hdl.var
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/xcelium_setup.sh b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/xcelium_setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..64217aaaaa4969c192df1aac494876ff28808e89
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/sim/xcelium/xcelium_setup.sh
@@ -0,0 +1,327 @@
+
+# (C) 2001-2021 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Intel
+# Program License Subscription Agreement, Intel MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Intel and sold by Intel
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+
+# ----------------------------------------
+# xcelium - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+# ip_arria10_e2sg_ram_crw_crw
+#
+# Intel recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+#
+# Xcelium Simulation Script.
+# To write a top-level shell script that compiles Intel simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
+#
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+#
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# # USER_DEFINED_COMPILE_OPTIONS
+# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/xcelium/xcelium_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# xmvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/xcelium/xcelium_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+#
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If ip_arria10_e2sg_ram_crw_crw is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+#
+# ip-setup-simulation --quartus-project=<quartus project>
+#
+# ip-setup-simulation will discover the Intel IP
+# within the Quartus project, and generate a unified
+# script which supports all the Intel IP within the design.
+# ----------------------------------------
+# ACDS 19.4 64 linux 2021.04.14.00:17:37
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="ip_arria10_e2sg_ram_crw_crw.ip_arria10_e2sg_ram_crw_crw"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/software/Altera/19.4.0.64/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for
+# overwriting variables. An example usage:
+# sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+ eval $expression
+ if [ $? -ne 0 ]; then
+ echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+ exit $?
+ fi
+done
+
+#-------------------------------------------
+# check tclsh version no earlier than 8.5
+version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
+if [ $version -eq -1 ]; then
+ echo "Error: Minimum required tcl package version is 8.5." >&2
+ exit 1
+fi
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
+ SIMULATOR_TOOL_BITNESS="bit_32"
+else
+ SIMULATOR_TOOL_BITNESS="bit_64"
+fi
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
+source $QSYS_SIMDIR/common/xcelium_files.tcl
+set LD_LIBRARY_PATH [dict create]
+set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [ip_arria10_e2sg_ram_crw_crw::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
+if {[dict size $LD_LIBRARY_PATH] !=0 } {
+ set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
+ puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
+}
+
+set ELAB_OPTIONS ""
+append ELAB_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_elab_options $SIMULATOR_TOOL_BITNESS]
+puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
+set SIM_OPTIONS ""
+append SIM_OPTIONS [ip_arria10_e2sg_ram_crw_crw::get_sim_options $SIMULATOR_TOOL_BITNESS]
+puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+eval $cmd_output
+
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set libraries [dict create]
+source $QSYS_SIMDIR/common/xcelium_files.tcl
+set libraries [dict merge $libraries [ip_arria10_e2sg_ram_crw_crw::get_design_libraries]]
+set design_libraries [dict keys $libraries]
+foreach file $design_libraries { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_libraries=$cmd_output
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/twentynm/
+mkdir -p ./libraries/twentynm_hssi/
+mkdir -p ./libraries/twentynm_hip/
+for library in $design_libraries
+do
+ mkdir -p ./libraries/$library
+done
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+TCLSCRIPT='
+set QSYS_SIMDIR [lindex $argv 1]
+set memory_files [list]
+source $QSYS_SIMDIR/common/xcelium_files.tcl
+set memory_files [concat $memory_files [ip_arria10_e2sg_ram_crw_crw::get_memory_files "$QSYS_SIMDIR"]]
+foreach file $memory_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+memory_files=$cmd_output
+if [ $SKIP_FILE_COPY -eq 0 ]; then
+ for file in $memory_files
+ do
+ cp -f $file ./
+ done
+fi
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
+ xmvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
+ xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_atoms_ncrypt.v" -work twentynm
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_atoms.vhd" -work twentynm
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_components.vhd" -work twentynm
+ xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_hssi_atoms_ncrypt.v" -work twentynm_hssi
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_components.vhd" -work twentynm_hssi
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hssi_atoms.vhd" -work twentynm_hssi
+ xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/twentynm_hip_atoms_ncrypt.v" -work twentynm_hip
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_components.vhd" -work twentynm_hip
+ xmvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/twentynm_hip_atoms.vhd" -work twentynm_hip
+fi
+
+# ----------------------------------------
+# get common system verilog package design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set design_files [dict create]
+source $QSYS_SIMDIR/common/xcelium_files.tcl
+set design_files [dict merge $design_files [ip_arria10_e2sg_ram_crw_crw::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set common_design_files [dict values $design_files]
+foreach file $common_design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+common_design_files=$cmd_output
+
+# ----------------------------------------
+# get design files
+TCLSCRIPT='
+set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
+set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
+set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
+set QSYS_SIMDIR [lindex $argv 4]
+set files [list]
+source $QSYS_SIMDIR/common/xcelium_files.tcl
+set files [concat $files [ip_arria10_e2sg_ram_crw_crw::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
+set design_files $files
+foreach file $design_files { puts "$file" }
+exit 0
+'
+cmd_output=$(
+tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
+ $TCLSCRIPT
+SCRIPT
+)
+
+design_files=$cmd_output
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+ eval "$common_design_files"
+ eval "$design_files"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+ xmelab -access +w+r+c -namemap_mixgen +DISABLEGENCHK -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+ eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/synth/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/synth/ip_arria10_e2sg_ram_crw_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f64a23cd832d75e95228d48a0a5f7fd20c976708
--- /dev/null
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/synth/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -0,0 +1,59 @@
+-- ip_arria10_e2sg_ram_crw_crw.vhd
+
+-- Generated using ACDS version 19.4 64
+
+library IEEE;
+library ram_2port_2000;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_arria10_e2sg_ram_crw_crw is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => '0'); -- data_a.datain_a
+ q_a : out std_logic_vector(7 downto 0); -- q_a.dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => '0'); -- data_b.datain_b
+ q_b : out std_logic_vector(7 downto 0); -- q_b.dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => '0'); -- address_a.address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => '0'); -- address_b.address_b
+ wren_a : in std_logic := '0'; -- wren_a.wren_a
+ wren_b : in std_logic := '0'; -- wren_b.wren_b
+ clock_a : in std_logic := '0'; -- clock_a.clk
+ clock_b : in std_logic := '0' -- clock_b.clk
+ );
+end entity ip_arria10_e2sg_ram_crw_crw;
+
+architecture rtl of ip_arria10_e2sg_ram_crw_crw is
+ component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
+ q_a : out std_logic_vector(7 downto 0); -- dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ q_b : out std_logic_vector(7 downto 0); -- dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clk
+ clock_b : in std_logic := 'X' -- clk
+ );
+ end component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp;
+
+ for ram_2port_0 : ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp
+ use entity ram_2port_2000.ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey;
+begin
+
+ ram_2port_0 : component ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey_cmp
+ port map (
+ data_a => data_a, -- data_a.datain_a
+ q_a => q_a, -- q_a.dataout_a
+ data_b => data_b, -- data_b.datain_b
+ q_b => q_b, -- q_b.dataout_b
+ address_a => address_a, -- address_a.address_a
+ address_b => address_b, -- address_b.address_b
+ wren_a => wren_a, -- wren_a.wren_a
+ wren_b => wren_b, -- wren_b.wren_b
+ clock_a => clock_a, -- clock_a.clk
+ clock_b => clock_b -- clock_b.clk
+ );
+
+end architecture rtl; -- of ip_arria10_e2sg_ram_crw_crw
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index b7427c05f0932d42571015ea2c2c5215825cf132..7b51dbf3f6b9c30e68c6118feaff0787d43c8805 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -15,12 +15,14 @@ synth_files =
tech_jesd204b.vhd
test_bench_files =
+# FIXME: broken, need fixing
# tb_tech_jesd204b_pkg.vhd
# tb_tech_jesd204b.vhd
# tb_tb_tech_jesd204b.vhd
regression_test_vhdl =
- tb_tech_jesd204b.vhd
+# FIXME: broken, need fixing
+# tb_tech_jesd204b.vhd
[modelsim_project_file]
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index d845941a08b564bc50fa73564d24cde089e980f8..6cec72909f1987c343efe91bf4226b69ef007453 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -13,6 +13,7 @@ hdl_lib_uses_synth = common technology
ip_arria10_e2sg_mult_add4
ip_arria10_e2sg_mult_add2
ip_arria10_e2sg_complex_mult
+
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index a7974a797728e81a5b1becefe4653a6e9f648436..bdaa07ad2df9bde03f94a4dd6c555db47fbe33fd 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -169,7 +169,7 @@ begin
-- RTL variant is the same for unb2, unb2a and unb2b
gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg ) AND g_variant="RTL") GENERATE
+ ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg) AND g_variant="RTL") GENERATE
u0 : ip_arria10_complex_mult_rtl
GENERIC MAP(
g_in_a_w => g_in_a_w,
@@ -195,7 +195,7 @@ begin
END GENERATE;
gen_ip_arria10_rtl_canonical : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg ) AND g_variant="RTL_C") GENERATE
+ ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg OR g_technology=c_tech_arria10_e2sg) AND g_variant="RTL_C") GENERATE
u0 : ip_arria10_complex_mult_rtl_canonical
GENERIC MAP(
g_in_a_w => g_in_a_w,