diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index f45a3937ec7e63481ac81da3773219029f7d3937..ba5ace7994c52065b2c62316717a2e6230e93370 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -37,10 +37,11 @@ use work.sdp_pkg.all;
entity node_sdp_adc_input_and_timing is
generic (
- g_no_jesd : boolean := false;
- -- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
- -- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
+ g_no_jesd : boolean := false; -- when false use Rx JESD204B and WG, else use only WG
+ -- When g_use_tech_jesd204b_v2 = false use tech_jesd204b with tech_jesd204b and FIFO in ait,
+ -- else use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
g_use_tech_jesd204b_v2 : boolean := false;
+ g_no_st_histogram : boolean := true; -- when false use input histogram, else not to save block RAM
g_buf_nof_data : natural := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_sim : boolean := false
@@ -286,6 +287,7 @@ begin
u_rx_ait : entity work.sdp_adc_input_and_timing
generic map (
g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
+ g_no_st_histogram => g_no_st_histogram,
g_buf_nof_data => g_buf_nof_data,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync, -- Default 200M, overide for short simulation
g_sim => g_sim
@@ -404,6 +406,7 @@ begin
u_dp_ait : entity work.sdp_adc_input_and_timing
generic map (
g_no_rx => g_no_jesd, -- when false use Rx and WG, else only use WG
+ g_no_st_histogram => g_no_st_histogram,
g_buf_nof_data => g_buf_nof_data,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync, -- Default 200M, overide for short simulation
g_sim => g_sim
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
index 82c3b624648d3bdad1dec43cd06e5518f5822ebd..a821ed5603536208ae8e9b3bb253d0af90390e9b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_adc_input_and_timing.vhd
@@ -37,6 +37,7 @@ use work.sdp_pkg.all;
entity sdp_adc_input_and_timing is
generic (
g_no_rx : boolean := false; -- when false use Rx and WG, else use only WG
+ g_no_st_histogram : boolean := true; -- when false use input histogram, else not to save block RAM
g_buf_nof_data : natural := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_sim : boolean := false
@@ -377,23 +378,29 @@ begin
-----------------------------------------------------------------------------
-- ST Histogram
-----------------------------------------------------------------------------
- u_st_histogram : entity st_lib.mmp_st_histogram
- generic map (
- g_nof_instances => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc,
- g_nof_bins => c_sdp_V_si_histogram,
- g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
- g_nof_data_per_sync_diff => c_sdp_N_fft / 2
- )
- port map (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
+ no_st_histogram : if g_no_st_histogram = true generate
+ ram_st_histogram_miso <= c_mem_miso_rst;
+ end generate;
- ram_copi => ram_st_histogram_mosi,
- ram_cipo => ram_st_histogram_miso,
+ gen_st_histogram : if g_no_st_histogram = false generate
+ u_st_histogram : entity st_lib.mmp_st_histogram
+ generic map (
+ g_nof_instances => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_nof_bins => c_sdp_V_si_histogram,
+ g_nof_data_per_sync => g_bsn_nof_clk_per_sync,
+ g_nof_data_per_sync_diff => c_sdp_N_fft / 2
+ )
+ port map (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- snk_in_arr => st_sosi_arr
- );
+ ram_copi => ram_st_histogram_mosi,
+ ram_cipo => ram_st_histogram_miso,
+
+ snk_in_arr => st_sosi_arr
+ );
+ end generate;
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index fb3f95f7390d0f9c436ac7d063c998d00fbacb32..727c59d7774ed8e9207a182450e5452e177994d0 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -62,10 +62,11 @@ entity sdp_station is
g_bsn_nof_clk_per_sync : natural := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_scope_selected_subband : natural := 0;
-- Use no default, to force instance to set it
- g_no_jesd : boolean;
- -- Use tech_jesd204b with tech_jesd204b and FIFO in ait, or
- -- use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
+ g_no_jesd : boolean; -- when false use Rx JESD204B and WG, else use only WG
+ -- When g_use_tech_jesd204b_v2 = false use tech_jesd204b with tech_jesd204b and FIFO in ait,
+ -- else use tech_jesd204b_v2 with FIFO in tech_jesd204b_v2
g_use_tech_jesd204b_v2 : boolean := true; --false;
+ g_no_st_histogram : boolean := true; -- when false use input histogram, else not to save block RAM
g_use_fsub : boolean;
g_use_oversample : boolean;
g_use_xsub : boolean;
@@ -674,6 +675,7 @@ begin
generic map(
g_sim => g_sim,
g_no_jesd => g_no_jesd,
+ g_no_st_histogram => g_no_st_histogram,
g_use_tech_jesd204b_v2 => g_use_tech_jesd204b_v2,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
)